if_bce.c revision 1.48
1 /* $NetBSD: if_bce.c,v 1.48 2018/12/09 11:14:02 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Clifford Wright. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Broadcom BCM440x 10/100 ethernet (broadcom.com) 32 * SiliconBackplane is technology from Sonics, Inc.(sonicsinc.com) 33 * 34 * Cliff Wright cliff (at) snipe444.org 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_bce.c,v 1.48 2018/12/09 11:14:02 jdolecek Exp $"); 39 40 #include "vlan.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/sockio.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/device.h> 50 #include <sys/socket.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #include <net/bpf.h> 58 #include <sys/rndsource.h> 59 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcidevs.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 #include <dev/mii/miidevs.h> 67 #include <dev/mii/brgphyreg.h> 68 69 #include <dev/pci/if_bcereg.h> 70 71 /* transmit buffer max frags allowed */ 72 #define BCE_NTXFRAGS 16 73 74 /* ring descriptor */ 75 struct bce_dma_slot { 76 uint32_t ctrl; 77 uint32_t addr; 78 }; 79 #define CTRL_BC_MASK 0x1fff /* buffer byte count */ 80 #define CTRL_EOT 0x10000000 /* end of descriptor table */ 81 #define CTRL_IOC 0x20000000 /* interrupt on completion */ 82 #define CTRL_EOF 0x40000000 /* end of frame */ 83 #define CTRL_SOF 0x80000000 /* start of frame */ 84 85 /* Packet status is returned in a pre-packet header */ 86 struct rx_pph { 87 uint16_t len; 88 uint16_t flags; 89 uint16_t pad[12]; 90 }; 91 92 /* packet status flags bits */ 93 #define RXF_NO 0x8 /* odd number of nibbles */ 94 #define RXF_RXER 0x4 /* receive symbol error */ 95 #define RXF_CRC 0x2 /* crc error */ 96 #define RXF_OV 0x1 /* fifo overflow */ 97 98 /* number of descriptors used in a ring */ 99 #define BCE_NRXDESC 128 100 #define BCE_NTXDESC 128 101 102 /* 103 * Mbuf pointers. We need these to keep track of the virtual addresses 104 * of our mbuf chains since we can only convert from physical to virtual, 105 * not the other way around. 106 */ 107 struct bce_chain_data { 108 struct mbuf *bce_tx_chain[BCE_NTXDESC]; 109 struct mbuf *bce_rx_chain[BCE_NRXDESC]; 110 bus_dmamap_t bce_tx_map[BCE_NTXDESC]; 111 bus_dmamap_t bce_rx_map[BCE_NRXDESC]; 112 }; 113 114 #define BCE_TIMEOUT 100 /* # 10us for mii read/write */ 115 116 struct bce_softc { 117 device_t bce_dev; 118 bus_space_tag_t bce_btag; 119 bus_space_handle_t bce_bhandle; 120 bus_dma_tag_t bce_dmatag; 121 struct ethercom ethercom; /* interface info */ 122 void *bce_intrhand; 123 struct pci_attach_args bce_pa; 124 struct mii_data bce_mii; 125 uint32_t bce_phy; /* eeprom indicated phy */ 126 struct ifmedia bce_ifmedia; /* media info *//* Check */ 127 uint8_t enaddr[ETHER_ADDR_LEN]; 128 struct bce_dma_slot *bce_rx_ring; /* receive ring */ 129 struct bce_dma_slot *bce_tx_ring; /* transmit ring */ 130 struct bce_chain_data bce_cdata; /* mbufs */ 131 bus_dmamap_t bce_ring_map; 132 uint32_t bce_intmask; /* current intr mask */ 133 uint32_t bce_rxin; /* last rx descriptor seen */ 134 uint32_t bce_txin; /* last tx descriptor seen */ 135 int bce_txsfree; /* no. tx slots available */ 136 int bce_txsnext; /* next available tx slot */ 137 callout_t bce_timeout; 138 krndsource_t rnd_source; 139 }; 140 141 /* for ring descriptors */ 142 #define BCE_RXBUF_LEN (MCLBYTES - 4) 143 #define BCE_INIT_RXDESC(sc, x) \ 144 do { \ 145 struct bce_dma_slot *__bced = &sc->bce_rx_ring[x]; \ 146 \ 147 *mtod(sc->bce_cdata.bce_rx_chain[x], uint32_t *) = 0; \ 148 __bced->addr = \ 149 htole32(sc->bce_cdata.bce_rx_map[x]->dm_segs[0].ds_addr \ 150 + 0x40000000); \ 151 if (x != (BCE_NRXDESC - 1)) \ 152 __bced->ctrl = htole32(BCE_RXBUF_LEN); \ 153 else \ 154 __bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT); \ 155 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, \ 156 sizeof(struct bce_dma_slot) * x, \ 157 sizeof(struct bce_dma_slot), \ 158 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 159 } while (/* CONSTCOND */ 0) 160 161 static int bce_probe(device_t, cfdata_t, void *); 162 static void bce_attach(device_t, device_t, void *); 163 static int bce_ioctl(struct ifnet *, u_long, void *); 164 static void bce_start(struct ifnet *); 165 static void bce_watchdog(struct ifnet *); 166 static int bce_intr(void *); 167 static void bce_rxintr(struct bce_softc *); 168 static void bce_txintr(struct bce_softc *); 169 static int bce_init(struct ifnet *); 170 static void bce_add_mac(struct bce_softc *, uint8_t *, unsigned long); 171 static int bce_add_rxbuf(struct bce_softc *, int); 172 static void bce_rxdrain(struct bce_softc *); 173 static void bce_stop(struct ifnet *, int); 174 static void bce_reset(struct bce_softc *); 175 static bool bce_resume(device_t, const pmf_qual_t *); 176 static void bce_set_filter(struct ifnet *); 177 static int bce_mii_read(device_t, int, int); 178 static void bce_mii_write(device_t, int, int, int); 179 static void bce_statchg(struct ifnet *); 180 static void bce_tick(void *); 181 182 CFATTACH_DECL_NEW(bce, sizeof(struct bce_softc), 183 bce_probe, bce_attach, NULL, NULL); 184 185 static const struct bce_product { 186 pci_vendor_id_t bp_vendor; 187 pci_product_id_t bp_product; 188 const char *bp_name; 189 } bce_products[] = { 190 { 191 PCI_VENDOR_BROADCOM, 192 PCI_PRODUCT_BROADCOM_BCM4401, 193 "Broadcom BCM4401 10/100 Ethernet" 194 }, 195 { 196 PCI_VENDOR_BROADCOM, 197 PCI_PRODUCT_BROADCOM_BCM4401_B0, 198 "Broadcom BCM4401-B0 10/100 Ethernet" 199 }, 200 { 201 PCI_VENDOR_BROADCOM, 202 PCI_PRODUCT_BROADCOM_BCM4401_B1, 203 "Broadcom BCM4401-B1 10/100 Ethernet" 204 }, 205 { 206 207 0, 208 0, 209 NULL 210 }, 211 }; 212 213 static const struct bce_product * 214 bce_lookup(const struct pci_attach_args * pa) 215 { 216 const struct bce_product *bp; 217 218 for (bp = bce_products; bp->bp_name != NULL; bp++) { 219 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 220 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 221 return (bp); 222 } 223 224 return (NULL); 225 } 226 227 /* 228 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 229 * against drivers product list, and return its name if a match is found. 230 */ 231 static int 232 bce_probe(device_t parent, cfdata_t match, void *aux) 233 { 234 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 235 236 if (bce_lookup(pa) != NULL) 237 return (1); 238 239 return (0); 240 } 241 242 static void 243 bce_attach(device_t parent, device_t self, void *aux) 244 { 245 struct bce_softc *sc = device_private(self); 246 struct pci_attach_args *pa = aux; 247 const struct bce_product *bp; 248 pci_chipset_tag_t pc = pa->pa_pc; 249 pci_intr_handle_t ih; 250 const char *intrstr = NULL; 251 uint32_t command; 252 pcireg_t memtype, pmode; 253 bus_addr_t memaddr; 254 bus_size_t memsize; 255 void *kva; 256 bus_dma_segment_t seg; 257 int error, i, pmreg, rseg; 258 struct ifnet *ifp; 259 char intrbuf[PCI_INTRSTR_LEN]; 260 261 sc->bce_dev = self; 262 263 bp = bce_lookup(pa); 264 KASSERT(bp != NULL); 265 266 sc->bce_pa = *pa; 267 268 /* BCM440x can only address 30 bits (1GB) */ 269 if (bus_dmatag_subregion(pa->pa_dmat, 0, (1 << 30), 270 &(sc->bce_dmatag), BUS_DMA_NOWAIT) != 0) { 271 aprint_error_dev(self, 272 "WARNING: failed to restrict dma range," 273 " falling back to parent bus dma range\n"); 274 sc->bce_dmatag = pa->pa_dmat; 275 } 276 277 aprint_naive(": Ethernet controller\n"); 278 aprint_normal(": %s\n", bp->bp_name); 279 280 /* 281 * Map control/status registers. 282 */ 283 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 284 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 285 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 286 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 287 288 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 289 aprint_error_dev(self, "failed to enable memory mapping!\n"); 290 return; 291 } 292 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BCE_PCI_BAR0); 293 switch (memtype) { 294 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 295 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 296 if (pci_mapreg_map(pa, BCE_PCI_BAR0, memtype, 0, &sc->bce_btag, 297 &sc->bce_bhandle, &memaddr, &memsize) == 0) 298 break; 299 default: 300 aprint_error_dev(self, "unable to find mem space\n"); 301 return; 302 } 303 304 /* Get it out of power save mode if needed. */ 305 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, NULL)) { 306 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) 307 & PCI_PMCSR_STATE_MASK; 308 if (pmode == PCI_PMCSR_STATE_D3) { 309 /* 310 * The card has lost all configuration data in 311 * this state, so punt. 312 */ 313 aprint_error_dev(self, 314 "unable to wake up from power state D3\n"); 315 return; 316 } 317 if (pmode != PCI_PMCSR_STATE_D0) { 318 aprint_normal_dev(self, 319 "waking up from power state D%d\n", pmode); 320 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 0); 321 } 322 } 323 if (pci_intr_map(pa, &ih)) { 324 aprint_error_dev(self, "couldn't map interrupt\n"); 325 return; 326 } 327 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 328 329 sc->bce_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, bce_intr, 330 sc, device_xname(self)); 331 332 if (sc->bce_intrhand == NULL) { 333 aprint_error_dev(self, "couldn't establish interrupt\n"); 334 if (intrstr != NULL) 335 aprint_error(" at %s", intrstr); 336 aprint_error("\n"); 337 return; 338 } 339 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 340 341 /* reset the chip */ 342 bce_reset(sc); 343 344 /* 345 * Allocate DMA-safe memory for ring descriptors. 346 * The receive, and transmit rings can not share the same 347 * 4k space, however both are allocated at once here. 348 */ 349 /* 350 * XXX PAGE_SIZE is wasteful; we only need 1KB + 1KB, but 351 * due to the limition above. ?? 352 */ 353 if ((error = bus_dmamem_alloc(sc->bce_dmatag, 354 2 * PAGE_SIZE, PAGE_SIZE, 2 * PAGE_SIZE, 355 &seg, 1, &rseg, BUS_DMA_NOWAIT))) { 356 aprint_error_dev(self, 357 "unable to alloc space for ring descriptors, error = %d\n", 358 error); 359 return; 360 } 361 /* map ring space to kernel */ 362 if ((error = bus_dmamem_map(sc->bce_dmatag, &seg, rseg, 363 2 * PAGE_SIZE, &kva, BUS_DMA_NOWAIT))) { 364 aprint_error_dev(self, 365 "unable to map DMA buffers, error = %d\n", error); 366 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 367 return; 368 } 369 /* create a dma map for the ring */ 370 if ((error = bus_dmamap_create(sc->bce_dmatag, 371 2 * PAGE_SIZE, 1, 2 * PAGE_SIZE, 0, BUS_DMA_NOWAIT, 372 &sc->bce_ring_map))) { 373 aprint_error_dev(self, 374 "unable to create ring DMA map, error = %d\n", error); 375 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 376 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 377 return; 378 } 379 /* connect the ring space to the dma map */ 380 if (bus_dmamap_load(sc->bce_dmatag, sc->bce_ring_map, kva, 381 2 * PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) { 382 bus_dmamap_destroy(sc->bce_dmatag, sc->bce_ring_map); 383 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 384 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 385 return; 386 } 387 /* save the ring space in softc */ 388 sc->bce_rx_ring = (struct bce_dma_slot *) kva; 389 sc->bce_tx_ring = (struct bce_dma_slot *) ((char *)kva + PAGE_SIZE); 390 391 /* Create the transmit buffer DMA maps. */ 392 for (i = 0; i < BCE_NTXDESC; i++) { 393 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 394 BCE_NTXFRAGS, MCLBYTES, 0, 0, &sc->bce_cdata.bce_tx_map[i])) != 0) { 395 aprint_error_dev(self, 396 "unable to create tx DMA map, error = %d\n", error); 397 } 398 sc->bce_cdata.bce_tx_chain[i] = NULL; 399 } 400 401 /* Create the receive buffer DMA maps. */ 402 for (i = 0; i < BCE_NRXDESC; i++) { 403 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 1, 404 MCLBYTES, 0, 0, &sc->bce_cdata.bce_rx_map[i])) != 0) { 405 aprint_error_dev(self, 406 "unable to create rx DMA map, error = %d\n", error); 407 } 408 sc->bce_cdata.bce_rx_chain[i] = NULL; 409 } 410 411 /* Set up ifnet structure */ 412 ifp = &sc->ethercom.ec_if; 413 strcpy(ifp->if_xname, device_xname(self)); 414 ifp->if_softc = sc; 415 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 416 ifp->if_ioctl = bce_ioctl; 417 ifp->if_start = bce_start; 418 ifp->if_watchdog = bce_watchdog; 419 ifp->if_init = bce_init; 420 ifp->if_stop = bce_stop; 421 IFQ_SET_READY(&ifp->if_snd); 422 423 /* Initialize our media structures and probe the MII. */ 424 425 sc->bce_mii.mii_ifp = ifp; 426 sc->bce_mii.mii_readreg = bce_mii_read; 427 sc->bce_mii.mii_writereg = bce_mii_write; 428 sc->bce_mii.mii_statchg = bce_statchg; 429 430 sc->ethercom.ec_mii = &sc->bce_mii; 431 ifmedia_init(&sc->bce_mii.mii_media, 0, ether_mediachange, 432 ether_mediastatus); 433 mii_attach(sc->bce_dev, &sc->bce_mii, 0xffffffff, MII_PHY_ANY, 434 MII_OFFSET_ANY, MIIF_FORCEANEG|MIIF_DOPAUSE); 435 if (LIST_FIRST(&sc->bce_mii.mii_phys) == NULL) { 436 ifmedia_add(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 437 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE); 438 } else 439 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_AUTO); 440 /* get the phy */ 441 sc->bce_phy = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 442 BCE_MAGIC_PHY) & 0x1f; 443 /* 444 * Enable activity led. 445 * XXX This should be in a phy driver, but not currently. 446 */ 447 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 448 bce_mii_read(sc->bce_dev, 1, 26) & 0x7fff); /* MAGIC */ 449 /* enable traffic meter led mode */ 450 bce_mii_write(sc->bce_dev, 1, 27, /* MAGIC */ 451 bce_mii_read(sc->bce_dev, 1, 27) | (1 << 6)); /* MAGIC */ 452 453 /* Attach the interface */ 454 if_attach(ifp); 455 if_deferred_start_init(ifp, NULL); 456 sc->enaddr[0] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 457 BCE_MAGIC_ENET0); 458 sc->enaddr[1] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 459 BCE_MAGIC_ENET1); 460 sc->enaddr[2] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 461 BCE_MAGIC_ENET2); 462 sc->enaddr[3] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 463 BCE_MAGIC_ENET3); 464 sc->enaddr[4] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 465 BCE_MAGIC_ENET4); 466 sc->enaddr[5] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 467 BCE_MAGIC_ENET5); 468 aprint_normal_dev(self, "Ethernet address %s\n", 469 ether_sprintf(sc->enaddr)); 470 ether_ifattach(ifp, sc->enaddr); 471 rnd_attach_source(&sc->rnd_source, device_xname(self), 472 RND_TYPE_NET, RND_FLAG_DEFAULT); 473 callout_init(&sc->bce_timeout, 0); 474 475 if (pmf_device_register(self, NULL, bce_resume)) 476 pmf_class_network_register(self, ifp); 477 else 478 aprint_error_dev(self, "couldn't establish power handler\n"); 479 } 480 481 /* handle media, and ethernet requests */ 482 static int 483 bce_ioctl(struct ifnet *ifp, u_long cmd, void *data) 484 { 485 int s, error; 486 487 s = splnet(); 488 error = ether_ioctl(ifp, cmd, data); 489 if (error == ENETRESET) { 490 /* change multicast list */ 491 error = 0; 492 } 493 494 /* Try to get more packets going. */ 495 bce_start(ifp); 496 497 splx(s); 498 return error; 499 } 500 501 /* Start packet transmission on the interface. */ 502 static void 503 bce_start(struct ifnet *ifp) 504 { 505 struct bce_softc *sc = ifp->if_softc; 506 struct mbuf *m0; 507 bus_dmamap_t dmamap; 508 int txstart; 509 int txsfree; 510 int newpkts = 0; 511 int error; 512 513 /* 514 * do not start another if currently transmitting, and more 515 * descriptors(tx slots) are needed for next packet. 516 */ 517 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 518 return; 519 520 /* determine number of descriptors available */ 521 if (sc->bce_txsnext >= sc->bce_txin) 522 txsfree = BCE_NTXDESC - 1 + sc->bce_txin - sc->bce_txsnext; 523 else 524 txsfree = sc->bce_txin - sc->bce_txsnext - 1; 525 526 /* 527 * Loop through the send queue, setting up transmit descriptors 528 * until we drain the queue, or use up all available transmit 529 * descriptors. 530 */ 531 while (txsfree > 0) { 532 int seg; 533 534 /* Grab a packet off the queue. */ 535 IFQ_POLL(&ifp->if_snd, m0); 536 if (m0 == NULL) 537 break; 538 539 /* get the transmit slot dma map */ 540 dmamap = sc->bce_cdata.bce_tx_map[sc->bce_txsnext]; 541 542 /* 543 * Load the DMA map. If this fails, the packet either 544 * didn't fit in the alloted number of segments, or we 545 * were short on resources. If the packet will not fit, 546 * it will be dropped. If short on resources, it will 547 * be tried again later. 548 */ 549 error = bus_dmamap_load_mbuf(sc->bce_dmatag, dmamap, m0, 550 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 551 if (error == EFBIG) { 552 aprint_error_dev(sc->bce_dev, 553 "Tx packet consumes too many DMA segments, " 554 "dropping...\n"); 555 IFQ_DEQUEUE(&ifp->if_snd, m0); 556 m_freem(m0); 557 ifp->if_oerrors++; 558 continue; 559 } else if (error) { 560 /* short on resources, come back later */ 561 aprint_error_dev(sc->bce_dev, 562 "unable to load Tx buffer, error = %d\n", 563 error); 564 break; 565 } 566 /* If not enough descriptors available, try again later */ 567 if (dmamap->dm_nsegs > txsfree) { 568 ifp->if_flags |= IFF_OACTIVE; 569 bus_dmamap_unload(sc->bce_dmatag, dmamap); 570 break; 571 } 572 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 573 574 /* So take it off the queue */ 575 IFQ_DEQUEUE(&ifp->if_snd, m0); 576 577 /* save the pointer so it can be freed later */ 578 sc->bce_cdata.bce_tx_chain[sc->bce_txsnext] = m0; 579 580 /* Sync the data DMA map. */ 581 bus_dmamap_sync(sc->bce_dmatag, dmamap, 0, dmamap->dm_mapsize, 582 BUS_DMASYNC_PREWRITE); 583 584 /* Initialize the transmit descriptor(s). */ 585 txstart = sc->bce_txsnext; 586 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 587 uint32_t ctrl; 588 589 ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK; 590 if (seg == 0) 591 ctrl |= CTRL_SOF; 592 if (seg == dmamap->dm_nsegs - 1) 593 ctrl |= CTRL_EOF; 594 if (sc->bce_txsnext == BCE_NTXDESC - 1) 595 ctrl |= CTRL_EOT; 596 ctrl |= CTRL_IOC; 597 sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl); 598 sc->bce_tx_ring[sc->bce_txsnext].addr = 599 htole32(dmamap->dm_segs[seg].ds_addr + 0x40000000); /* MAGIC */ 600 if (sc->bce_txsnext + 1 > BCE_NTXDESC - 1) 601 sc->bce_txsnext = 0; 602 else 603 sc->bce_txsnext++; 604 txsfree--; 605 } 606 /* sync descriptors being used */ 607 if ( sc->bce_txsnext > txstart ) { 608 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 609 PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart, 610 sizeof(struct bce_dma_slot) * dmamap->dm_nsegs, 611 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 612 } else { 613 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 614 PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart, 615 sizeof(struct bce_dma_slot) * 616 (BCE_NTXDESC - txstart), 617 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 618 if ( sc->bce_txsnext != 0 ) { 619 bus_dmamap_sync(sc->bce_dmatag, 620 sc->bce_ring_map, PAGE_SIZE, 621 sc->bce_txsnext * 622 sizeof(struct bce_dma_slot), 623 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 624 } 625 } 626 627 /* Give the packet to the chip. */ 628 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_DPTR, 629 sc->bce_txsnext * sizeof(struct bce_dma_slot)); 630 631 newpkts++; 632 633 /* Pass the packet to any BPF listeners. */ 634 bpf_mtap(ifp, m0, BPF_D_OUT); 635 } 636 if (txsfree == 0) { 637 /* No more slots left; notify upper layer. */ 638 ifp->if_flags |= IFF_OACTIVE; 639 } 640 if (newpkts) { 641 /* Set a watchdog timer in case the chip flakes out. */ 642 ifp->if_timer = 5; 643 } 644 } 645 646 /* Watchdog timer handler. */ 647 static void 648 bce_watchdog(struct ifnet *ifp) 649 { 650 struct bce_softc *sc = ifp->if_softc; 651 652 aprint_error_dev(sc->bce_dev, "device timeout\n"); 653 ifp->if_oerrors++; 654 655 (void) bce_init(ifp); 656 657 /* Try to get more packets going. */ 658 bce_start(ifp); 659 } 660 661 int 662 bce_intr(void *xsc) 663 { 664 struct bce_softc *sc; 665 struct ifnet *ifp; 666 uint32_t intstatus; 667 int wantinit; 668 int handled = 0; 669 670 sc = xsc; 671 ifp = &sc->ethercom.ec_if; 672 673 for (wantinit = 0; wantinit == 0;) { 674 intstatus = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 675 BCE_INT_STS); 676 677 /* ignore if not ours, or unsolicited interrupts */ 678 intstatus &= sc->bce_intmask; 679 if (intstatus == 0) 680 break; 681 682 handled = 1; 683 684 /* Ack interrupt */ 685 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS, 686 intstatus); 687 688 /* Receive interrupts. */ 689 if (intstatus & I_RI) 690 bce_rxintr(sc); 691 /* Transmit interrupts. */ 692 if (intstatus & I_XI) 693 bce_txintr(sc); 694 /* Error interrupts */ 695 if (intstatus & ~(I_RI | I_XI)) { 696 const char *msg = NULL; 697 if (intstatus & I_XU) 698 msg = "transmit fifo underflow"; 699 if (intstatus & I_RO) { 700 msg = "receive fifo overflow"; 701 ifp->if_ierrors++; 702 } 703 if (intstatus & I_RU) 704 msg = "receive descriptor underflow"; 705 if (intstatus & I_DE) 706 msg = "descriptor protocol error"; 707 if (intstatus & I_PD) 708 msg = "data error"; 709 if (intstatus & I_PC) 710 msg = "descriptor error"; 711 if (intstatus & I_TO) 712 msg = "general purpose timeout"; 713 if (msg != NULL) 714 aprint_error_dev(sc->bce_dev, "%s\n", msg); 715 wantinit = 1; 716 } 717 } 718 719 if (handled) { 720 if (wantinit) 721 bce_init(ifp); 722 rnd_add_uint32(&sc->rnd_source, intstatus); 723 /* Try to get more packets going. */ 724 if_schedule_deferred_start(ifp); 725 } 726 return (handled); 727 } 728 729 /* Receive interrupt handler */ 730 void 731 bce_rxintr(struct bce_softc *sc) 732 { 733 struct ifnet *ifp = &sc->ethercom.ec_if; 734 struct rx_pph *pph; 735 struct mbuf *m; 736 int curr; 737 int len; 738 int i; 739 740 /* get pointer to active receive slot */ 741 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS) 742 & RS_CD_MASK; 743 curr = curr / sizeof(struct bce_dma_slot); 744 if (curr >= BCE_NRXDESC) 745 curr = BCE_NRXDESC - 1; 746 747 /* process packets up to but not current packet being worked on */ 748 for (i = sc->bce_rxin; i != curr; 749 i + 1 > BCE_NRXDESC - 1 ? i = 0 : i++) { 750 /* complete any post dma memory ops on packet */ 751 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i], 0, 752 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 753 BUS_DMASYNC_POSTREAD); 754 755 /* 756 * If the packet had an error, simply recycle the buffer, 757 * resetting the len, and flags. 758 */ 759 pph = mtod(sc->bce_cdata.bce_rx_chain[i], struct rx_pph *); 760 if (pph->flags & (RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)) { 761 ifp->if_ierrors++; 762 pph->len = 0; 763 pph->flags = 0; 764 continue; 765 } 766 /* receive the packet */ 767 len = pph->len; 768 if (len == 0) 769 continue; /* no packet if empty */ 770 pph->len = 0; 771 pph->flags = 0; 772 /* bump past pre header to packet */ 773 sc->bce_cdata.bce_rx_chain[i]->m_data += 30; /* MAGIC */ 774 775 /* 776 * The chip includes the CRC with every packet. Trim 777 * it off here. 778 */ 779 len -= ETHER_CRC_LEN; 780 781 /* 782 * If the packet is small enough to fit in a 783 * single header mbuf, allocate one and copy 784 * the data into it. This greatly reduces 785 * memory consumption when receiving lots 786 * of small packets. 787 * 788 * Otherwise, add a new buffer to the receive 789 * chain. If this fails, drop the packet and 790 * recycle the old buffer. 791 */ 792 if (len <= (MHLEN - 2)) { 793 MGETHDR(m, M_DONTWAIT, MT_DATA); 794 if (m == NULL) 795 goto dropit; 796 m->m_data += 2; 797 memcpy(mtod(m, void *), 798 mtod(sc->bce_cdata.bce_rx_chain[i], void *), len); 799 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; /* MAGIC */ 800 } else { 801 m = sc->bce_cdata.bce_rx_chain[i]; 802 if (bce_add_rxbuf(sc, i) != 0) { 803 dropit: 804 ifp->if_ierrors++; 805 /* continue to use old buffer */ 806 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; 807 bus_dmamap_sync(sc->bce_dmatag, 808 sc->bce_cdata.bce_rx_map[i], 0, 809 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 810 BUS_DMASYNC_PREREAD); 811 continue; 812 } 813 } 814 815 m_set_rcvif(m, ifp); 816 m->m_pkthdr.len = m->m_len = len; 817 818 /* Pass it on. */ 819 if_percpuq_enqueue(ifp->if_percpuq, m); 820 821 /* re-check current in case it changed */ 822 curr = (bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 823 BCE_DMA_RXSTATUS) & RS_CD_MASK) / 824 sizeof(struct bce_dma_slot); 825 if (curr >= BCE_NRXDESC) 826 curr = BCE_NRXDESC - 1; 827 } 828 sc->bce_rxin = curr; 829 } 830 831 /* Transmit interrupt handler */ 832 void 833 bce_txintr(struct bce_softc *sc) 834 { 835 struct ifnet *ifp = &sc->ethercom.ec_if; 836 int curr; 837 int i; 838 839 ifp->if_flags &= ~IFF_OACTIVE; 840 841 /* 842 * Go through the Tx list and free mbufs for those 843 * frames which have been transmitted. 844 */ 845 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXSTATUS) & 846 RS_CD_MASK; 847 curr = curr / sizeof(struct bce_dma_slot); 848 if (curr >= BCE_NTXDESC) 849 curr = BCE_NTXDESC - 1; 850 for (i = sc->bce_txin; i != curr; 851 i + 1 > BCE_NTXDESC - 1 ? i = 0 : i++) { 852 /* do any post dma memory ops on transmit data */ 853 if (sc->bce_cdata.bce_tx_chain[i] == NULL) 854 continue; 855 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i], 0, 856 sc->bce_cdata.bce_tx_map[i]->dm_mapsize, 857 BUS_DMASYNC_POSTWRITE); 858 bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i]); 859 m_freem(sc->bce_cdata.bce_tx_chain[i]); 860 sc->bce_cdata.bce_tx_chain[i] = NULL; 861 ifp->if_opackets++; 862 } 863 sc->bce_txin = curr; 864 865 /* 866 * If there are no more pending transmissions, cancel the watchdog 867 * timer 868 */ 869 if (sc->bce_txsnext == sc->bce_txin) 870 ifp->if_timer = 0; 871 } 872 873 /* initialize the interface */ 874 static int 875 bce_init(struct ifnet *ifp) 876 { 877 struct bce_softc *sc = ifp->if_softc; 878 uint32_t reg_win; 879 int error; 880 int i; 881 882 /* Cancel any pending I/O. */ 883 bce_stop(ifp, 0); 884 885 /* enable pci inerrupts, bursts, and prefetch */ 886 887 /* remap the pci registers to the Sonics config registers */ 888 889 /* save the current map, so it can be restored */ 890 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 891 BCE_REG_WIN); 892 893 /* set register window to Sonics registers */ 894 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 895 BCE_SONICS_WIN); 896 897 /* enable SB to PCI interrupt */ 898 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 899 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) | 900 SBIV_ENET0); 901 902 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 903 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 904 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) | 905 SBTOPCI_PREF | SBTOPCI_BURST); 906 907 /* restore to ethernet register space */ 908 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 909 reg_win); 910 911 /* Reset the chip to a known state. */ 912 bce_reset(sc); 913 914 /* Initialize transmit descriptors */ 915 memset(sc->bce_tx_ring, 0, BCE_NTXDESC * sizeof(struct bce_dma_slot)); 916 sc->bce_txsnext = 0; 917 sc->bce_txin = 0; 918 919 /* enable crc32 generation */ 920 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 921 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) | 922 BCE_EMC_CG); 923 924 /* setup DMA interrupt control */ 925 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1 << 24); /* MAGIC */ 926 927 /* setup packet filter */ 928 bce_set_filter(ifp); 929 930 /* set max frame length, account for possible vlan tag */ 931 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_MAX, 932 ETHER_MAX_LEN + 32); 933 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_MAX, 934 ETHER_MAX_LEN + 32); 935 936 /* set tx watermark */ 937 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_WATER, 56); 938 939 /* enable transmit */ 940 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, XC_XE); 941 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXADDR, 942 sc->bce_ring_map->dm_segs[0].ds_addr + PAGE_SIZE + 0x40000000); /* MAGIC */ 943 944 /* 945 * Give the receive ring to the chip, and 946 * start the receive DMA engine. 947 */ 948 sc->bce_rxin = 0; 949 950 /* clear the rx descriptor ring */ 951 memset(sc->bce_rx_ring, 0, BCE_NRXDESC * sizeof(struct bce_dma_slot)); 952 /* enable receive */ 953 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 954 30 << 1 | 1); /* MAGIC */ 955 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXADDR, 956 sc->bce_ring_map->dm_segs[0].ds_addr + 0x40000000); /* MAGIC */ 957 958 /* Initalize receive descriptors */ 959 for (i = 0; i < BCE_NRXDESC; i++) { 960 if (sc->bce_cdata.bce_rx_chain[i] == NULL) { 961 if ((error = bce_add_rxbuf(sc, i)) != 0) { 962 aprint_error_dev(sc->bce_dev, 963 "unable to allocate or map rx(%d) " 964 "mbuf, error = %d\n", i, error); 965 bce_rxdrain(sc); 966 return (error); 967 } 968 } else 969 BCE_INIT_RXDESC(sc, i); 970 } 971 972 /* Enable interrupts */ 973 sc->bce_intmask = 974 I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO; 975 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 976 sc->bce_intmask); 977 978 /* start the receive dma */ 979 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR, 980 BCE_NRXDESC * sizeof(struct bce_dma_slot)); 981 982 /* set media */ 983 if ((error = ether_mediachange(ifp)) != 0) 984 return error; 985 986 /* turn on the ethernet mac */ 987 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 988 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 989 BCE_ENET_CTL) | EC_EE); 990 991 /* start timer */ 992 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 993 994 /* mark as running, and no outputs active */ 995 ifp->if_flags |= IFF_RUNNING; 996 ifp->if_flags &= ~IFF_OACTIVE; 997 998 return 0; 999 } 1000 1001 /* add a mac address to packet filter */ 1002 void 1003 bce_add_mac(struct bce_softc *sc, uint8_t *mac, u_long idx) 1004 { 1005 int i; 1006 uint32_t rval; 1007 1008 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_LOW, 1009 mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]); 1010 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_HI, 1011 mac[0] << 8 | mac[1] | 0x10000); /* MAGIC */ 1012 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1013 idx << 16 | 8); /* MAGIC */ 1014 /* wait for write to complete */ 1015 for (i = 0; i < 100; i++) { 1016 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1017 BCE_FILT_CTL); 1018 if (!(rval & 0x80000000)) /* MAGIC */ 1019 break; 1020 delay(10); 1021 } 1022 if (i == 100) { 1023 aprint_error_dev(sc->bce_dev, 1024 "timed out writing pkt filter ctl\n"); 1025 } 1026 } 1027 1028 /* Add a receive buffer to the indiciated descriptor. */ 1029 static int 1030 bce_add_rxbuf(struct bce_softc *sc, int idx) 1031 { 1032 struct mbuf *m; 1033 int error; 1034 1035 MGETHDR(m, M_DONTWAIT, MT_DATA); 1036 if (m == NULL) 1037 return (ENOBUFS); 1038 1039 MCLGET(m, M_DONTWAIT); 1040 if ((m->m_flags & M_EXT) == 0) { 1041 m_freem(m); 1042 return (ENOBUFS); 1043 } 1044 if (sc->bce_cdata.bce_rx_chain[idx] != NULL) 1045 bus_dmamap_unload(sc->bce_dmatag, 1046 sc->bce_cdata.bce_rx_map[idx]); 1047 1048 sc->bce_cdata.bce_rx_chain[idx] = m; 1049 1050 error = bus_dmamap_load(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 1051 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1052 BUS_DMA_READ | BUS_DMA_NOWAIT); 1053 if (error) 1054 return (error); 1055 1056 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 0, 1057 sc->bce_cdata.bce_rx_map[idx]->dm_mapsize, BUS_DMASYNC_PREREAD); 1058 1059 BCE_INIT_RXDESC(sc, idx); 1060 1061 return (0); 1062 1063 } 1064 1065 /* Drain the receive queue. */ 1066 static void 1067 bce_rxdrain(struct bce_softc *sc) 1068 { 1069 int i; 1070 1071 for (i = 0; i < BCE_NRXDESC; i++) { 1072 if (sc->bce_cdata.bce_rx_chain[i] != NULL) { 1073 bus_dmamap_unload(sc->bce_dmatag, 1074 sc->bce_cdata.bce_rx_map[i]); 1075 m_freem(sc->bce_cdata.bce_rx_chain[i]); 1076 sc->bce_cdata.bce_rx_chain[i] = NULL; 1077 } 1078 } 1079 } 1080 1081 /* Stop transmission on the interface */ 1082 static void 1083 bce_stop(struct ifnet *ifp, int disable) 1084 { 1085 struct bce_softc *sc = ifp->if_softc; 1086 int i; 1087 uint32_t val; 1088 1089 /* Stop the 1 second timer */ 1090 callout_stop(&sc->bce_timeout); 1091 1092 /* Down the MII. */ 1093 mii_down(&sc->bce_mii); 1094 1095 /* Disable interrupts. */ 1096 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0); 1097 sc->bce_intmask = 0; 1098 delay(10); 1099 1100 /* Disable emac */ 1101 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED); 1102 for (i = 0; i < 200; i++) { 1103 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1104 BCE_ENET_CTL); 1105 if (!(val & EC_ED)) 1106 break; 1107 delay(10); 1108 } 1109 1110 /* Stop the DMA */ 1111 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 0); 1112 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1113 delay(10); 1114 1115 /* Release any queued transmit buffers. */ 1116 for (i = 0; i < BCE_NTXDESC; i++) { 1117 if (sc->bce_cdata.bce_tx_chain[i] != NULL) { 1118 bus_dmamap_unload(sc->bce_dmatag, 1119 sc->bce_cdata.bce_tx_map[i]); 1120 m_freem(sc->bce_cdata.bce_tx_chain[i]); 1121 sc->bce_cdata.bce_tx_chain[i] = NULL; 1122 } 1123 } 1124 1125 /* Mark the interface down and cancel the watchdog timer. */ 1126 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1127 ifp->if_timer = 0; 1128 1129 /* drain receive queue */ 1130 if (disable) 1131 bce_rxdrain(sc); 1132 } 1133 1134 /* reset the chip */ 1135 static void 1136 bce_reset(struct bce_softc *sc) 1137 { 1138 uint32_t val; 1139 uint32_t sbval; 1140 int i; 1141 1142 /* if SB core is up */ 1143 sbval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1144 BCE_SBTMSTATELOW); 1145 if ((sbval & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK) { 1146 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1147 0); 1148 1149 /* disable emac */ 1150 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1151 EC_ED); 1152 for (i = 0; i < 200; i++) { 1153 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1154 BCE_ENET_CTL); 1155 if (!(val & EC_ED)) 1156 break; 1157 delay(10); 1158 } 1159 if (i == 200) { 1160 aprint_error_dev(sc->bce_dev, 1161 "timed out disabling ethernet mac\n"); 1162 } 1163 1164 /* reset the dma engines */ 1165 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1166 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS); 1167 /* if error on receive, wait to go idle */ 1168 if (val & RS_ERROR) { 1169 for (i = 0; i < 100; i++) { 1170 val = bus_space_read_4(sc->bce_btag, 1171 sc->bce_bhandle, BCE_DMA_RXSTATUS); 1172 if (val & RS_DMA_IDLE) 1173 break; 1174 delay(10); 1175 } 1176 if (i == 100) { 1177 aprint_error_dev(sc->bce_dev, 1178 "receive dma did not go idle after" 1179 " error\n"); 1180 } 1181 } 1182 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1183 BCE_DMA_RXSTATUS, 0); 1184 1185 /* reset ethernet mac */ 1186 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1187 EC_ES); 1188 for (i = 0; i < 200; i++) { 1189 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1190 BCE_ENET_CTL); 1191 if (!(val & EC_ES)) 1192 break; 1193 delay(10); 1194 } 1195 if (i == 200) { 1196 aprint_error_dev(sc->bce_dev, 1197 "timed out resetting ethernet mac\n"); 1198 } 1199 } else { 1200 uint32_t reg_win; 1201 1202 /* remap the pci registers to the Sonics config registers */ 1203 1204 /* save the current map, so it can be restored */ 1205 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1206 BCE_REG_WIN); 1207 /* set register window to Sonics registers */ 1208 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1209 BCE_REG_WIN, BCE_SONICS_WIN); 1210 1211 /* enable SB to PCI interrupt */ 1212 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 1213 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1214 BCE_SBINTVEC) | 1215 SBIV_ENET0); 1216 1217 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 1218 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 1219 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1220 BCE_SPCI_TR2) | 1221 SBTOPCI_PREF | SBTOPCI_BURST); 1222 1223 /* restore to ethernet register space */ 1224 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 1225 reg_win); 1226 } 1227 1228 /* disable SB core if not in reset */ 1229 if (!(sbval & SBTML_RESET)) { 1230 1231 /* set the reject bit */ 1232 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1233 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_CLK); 1234 for (i = 0; i < 200; i++) { 1235 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1236 BCE_SBTMSTATELOW); 1237 if (val & SBTML_REJ) 1238 break; 1239 delay(1); 1240 } 1241 if (i == 200) { 1242 aprint_error_dev(sc->bce_dev, 1243 "while resetting core, reject did not set\n"); 1244 } 1245 /* wait until busy is clear */ 1246 for (i = 0; i < 200; i++) { 1247 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1248 BCE_SBTMSTATEHI); 1249 if (!(val & 0x4)) 1250 break; 1251 delay(1); 1252 } 1253 if (i == 200) { 1254 aprint_error_dev(sc->bce_dev, 1255 "while resetting core, busy did not clear\n"); 1256 } 1257 /* set reset and reject while enabling the clocks */ 1258 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1259 BCE_SBTMSTATELOW, 1260 SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET); 1261 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1262 BCE_SBTMSTATELOW); 1263 delay(10); 1264 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1265 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_RESET); 1266 delay(1); 1267 } 1268 /* enable clock */ 1269 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1270 SBTML_FGC | SBTML_CLK | SBTML_RESET); 1271 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1272 delay(1); 1273 1274 /* clear any error bits that may be on */ 1275 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI); 1276 if (val & 1) 1277 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI, 1278 0); 1279 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE); 1280 if (val & SBIM_MAGIC_ERRORBITS) 1281 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE, 1282 val & ~SBIM_MAGIC_ERRORBITS); 1283 1284 /* clear reset and allow it to propagate throughout the core */ 1285 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1286 SBTML_FGC | SBTML_CLK); 1287 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1288 delay(1); 1289 1290 /* leave clock enabled */ 1291 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1292 SBTML_CLK); 1293 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1294 delay(1); 1295 1296 /* initialize MDC preamble, frequency */ 1297 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_CTL, 0x8d); /* MAGIC */ 1298 1299 /* enable phy, differs for internal, and external */ 1300 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL); 1301 if (!(val & BCE_DC_IP)) { 1302 /* select external phy */ 1303 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_EP); 1304 } else if (val & BCE_DC_ER) { /* internal, clear reset bit if on */ 1305 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL, 1306 val & ~BCE_DC_ER); 1307 delay(100); 1308 } 1309 } 1310 1311 /* Set up the receive filter. */ 1312 void 1313 bce_set_filter(struct ifnet *ifp) 1314 { 1315 struct bce_softc *sc = ifp->if_softc; 1316 1317 if (ifp->if_flags & IFF_PROMISC) { 1318 ifp->if_flags |= IFF_ALLMULTI; 1319 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1320 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) 1321 | ERC_PE); 1322 } else { 1323 ifp->if_flags &= ~IFF_ALLMULTI; 1324 1325 /* turn off promiscuous */ 1326 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1327 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1328 BCE_RX_CTL) & ~ERC_PE); 1329 1330 /* enable/disable broadcast */ 1331 if (ifp->if_flags & IFF_BROADCAST) 1332 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1333 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1334 sc->bce_bhandle, BCE_RX_CTL) & ~ERC_DB); 1335 else 1336 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1337 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1338 sc->bce_bhandle, BCE_RX_CTL) | ERC_DB); 1339 1340 /* disable the filter */ 1341 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1342 0); 1343 1344 /* add our own address */ 1345 bce_add_mac(sc, sc->enaddr, 0); 1346 1347 /* for now accept all multicast */ 1348 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1349 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) | 1350 ERC_AM); 1351 ifp->if_flags |= IFF_ALLMULTI; 1352 1353 /* enable the filter */ 1354 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1355 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1356 BCE_FILT_CTL) | 1); 1357 } 1358 } 1359 1360 static bool 1361 bce_resume(device_t self, const pmf_qual_t *qual) 1362 { 1363 struct bce_softc *sc = device_private(self); 1364 1365 bce_reset(sc); 1366 1367 return true; 1368 } 1369 1370 /* Read a PHY register on the MII. */ 1371 int 1372 bce_mii_read(device_t self, int phy, int reg) 1373 { 1374 struct bce_softc *sc = device_private(self); 1375 int i; 1376 uint32_t val; 1377 1378 /* clear mii_int */ 1379 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR); 1380 1381 /* Read the PHY register */ 1382 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1383 (MII_COMMAND_READ << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1384 (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */ 1385 1386 for (i = 0; i < BCE_TIMEOUT; i++) { 1387 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS); 1388 if (val & BCE_MIINTR) 1389 break; 1390 delay(10); 1391 } 1392 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1393 if (i == BCE_TIMEOUT) { 1394 aprint_error_dev(sc->bce_dev, 1395 "PHY read timed out reading phy %d, reg %d, val = " 1396 "0x%08x\n", phy, reg, val); 1397 return (0); 1398 } 1399 return (val & BCE_MICOMM_DATA); 1400 } 1401 1402 /* Write a PHY register on the MII */ 1403 void 1404 bce_mii_write(device_t self, int phy, int reg, int val) 1405 { 1406 struct bce_softc *sc = device_private(self); 1407 int i; 1408 uint32_t rval; 1409 1410 /* clear mii_int */ 1411 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, 1412 BCE_MIINTR); 1413 1414 /* Write the PHY register */ 1415 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1416 (MII_COMMAND_WRITE << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1417 (MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) | /* MAGIC */ 1418 BCE_MIPHY(phy) | BCE_MIREG(reg)); 1419 1420 /* wait for write to complete */ 1421 for (i = 0; i < BCE_TIMEOUT; i++) { 1422 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1423 BCE_MI_STS); 1424 if (rval & BCE_MIINTR) 1425 break; 1426 delay(10); 1427 } 1428 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1429 if (i == BCE_TIMEOUT) { 1430 aprint_error_dev(sc->bce_dev, 1431 "PHY timed out writing phy %d, reg %d, val = 0x%08x\n", phy, 1432 reg, val); 1433 } 1434 } 1435 1436 /* sync hardware duplex mode to software state */ 1437 void 1438 bce_statchg(struct ifnet *ifp) 1439 { 1440 struct bce_softc *sc = ifp->if_softc; 1441 uint32_t reg; 1442 1443 /* if needed, change register to match duplex mode */ 1444 reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL); 1445 if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD)) 1446 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1447 reg | EXC_FD); 1448 else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD) 1449 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1450 reg & ~EXC_FD); 1451 1452 /* 1453 * Enable activity led. 1454 * XXX This should be in a phy driver, but not currently. 1455 */ 1456 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 1457 bce_mii_read(sc->bce_dev, 1, 26) & 0x7fff); /* MAGIC */ 1458 /* enable traffic meter led mode */ 1459 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 1460 bce_mii_read(sc->bce_dev, 1, 27) | (1 << 6)); /* MAGIC */ 1461 } 1462 1463 /* One second timer, checks link status */ 1464 static void 1465 bce_tick(void *v) 1466 { 1467 struct bce_softc *sc = v; 1468 1469 /* Tick the MII. */ 1470 mii_tick(&sc->bce_mii); 1471 1472 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1473 } 1474
Indexes created Tue Sep 30 17:09:57 GMT 2025