if_bce.c revision 1.5
1 /* $NetBSD: if_bce.c,v 1.5 2004/07/09 05:08:22 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Clifford Wright. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Broadcom BCM440x 10/100 ethernet (broadcom.com) 32 * SiliconBackplane is technology from Sonics, Inc.(sonicsinc.com) 33 * 34 * Cliff Wright cliff (at) snipe444.org 35 */ 36 37 #include "bpfilter.h" 38 #include "vlan.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/callout.h> 43 #include <sys/sockio.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/device.h> 48 #include <sys/socket.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 #include <net/if_ether.h> 54 55 #if NBPFILTER > 0 56 #include <net/bpf.h> 57 #endif 58 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 #include <dev/mii/miidevs.h> 66 #include <dev/mii/brgphyreg.h> 67 68 #include <dev/pci/if_bcereg.h> 69 70 #include <uvm/uvm_extern.h> 71 72 /* transmit buffer max frags allowed */ 73 #define BCE_NTXFRAGS 16 74 75 /* ring descriptor */ 76 struct bce_dma_slot { 77 u_int32_t ctrl; 78 u_int32_t addr; 79 }; 80 #define CTRL_BC_MASK 0x1fff /* buffer byte count */ 81 #define CTRL_EOT 0x10000000 /* end of descriptor table */ 82 #define CTRL_IOC 0x20000000 /* interrupt on completion */ 83 #define CTRL_EOF 0x40000000 /* end of frame */ 84 #define CTRL_SOF 0x80000000 /* start of frame */ 85 86 /* Packet status is returned in a pre-packet header */ 87 struct rx_pph { 88 u_int16_t len; 89 u_int16_t flags; 90 u_int16_t pad[12]; 91 }; 92 93 /* packet status flags bits */ 94 #define RXF_NO 0x8 /* odd number of nibbles */ 95 #define RXF_RXER 0x4 /* receive symbol error */ 96 #define RXF_CRC 0x2 /* crc error */ 97 #define RXF_OV 0x1 /* fifo overflow */ 98 99 /* number of descriptors used in a ring */ 100 #define BCE_NRXDESC 128 101 #define BCE_NTXDESC 128 102 103 /* 104 * Mbuf pointers. We need these to keep track of the virtual addresses 105 * of our mbuf chains since we can only convert from physical to virtual, 106 * not the other way around. 107 */ 108 struct bce_chain_data { 109 struct mbuf *bce_tx_chain[BCE_NTXDESC]; 110 struct mbuf *bce_rx_chain[BCE_NRXDESC]; 111 bus_dmamap_t bce_tx_map[BCE_NTXDESC]; 112 bus_dmamap_t bce_rx_map[BCE_NRXDESC]; 113 }; 114 115 #define BCE_TIMEOUT 100 /* # 10us for mii read/write */ 116 117 struct bce_softc { 118 struct device bce_dev; 119 bus_space_tag_t bce_btag; 120 bus_space_handle_t bce_bhandle; 121 bus_dma_tag_t bce_dmatag; 122 struct ethercom ethercom; /* interface info */ 123 void *bce_intrhand; 124 struct pci_attach_args bce_pa; 125 struct mii_data bce_mii; 126 u_int32_t bce_phy; /* eeprom indicated phy */ 127 struct ifmedia bce_ifmedia; /* media info *//* Check */ 128 u_int8_t enaddr[ETHER_ADDR_LEN]; 129 struct bce_dma_slot *bce_rx_ring; /* receive ring */ 130 struct bce_dma_slot *bce_tx_ring; /* transmit ring */ 131 struct bce_chain_data bce_cdata; /* mbufs */ 132 bus_dmamap_t bce_ring_map; 133 u_int32_t bce_intmask; /* current intr mask */ 134 u_int32_t bce_rxin; /* last rx descriptor seen */ 135 u_int32_t bce_txin; /* last tx descriptor seen */ 136 int bce_txsfree; /* no. tx slots available */ 137 int bce_txsnext; /* next available tx slot */ 138 struct callout bce_timeout; 139 }; 140 141 /* for ring descriptors */ 142 #define BCE_RXBUF_LEN (MCLBYTES - 4) 143 #define BCE_INIT_RXDESC(sc, x) \ 144 do { \ 145 struct bce_dma_slot *__bced = &sc->bce_rx_ring[x]; \ 146 \ 147 *mtod(sc->bce_cdata.bce_rx_chain[x], u_int32_t *) = 0; \ 148 __bced->addr = \ 149 htole32(sc->bce_cdata.bce_rx_map[x]->dm_segs[0].ds_addr \ 150 + 0x40000000); \ 151 if (x != (BCE_NRXDESC - 1)) \ 152 __bced->ctrl = htole32(BCE_RXBUF_LEN); \ 153 else \ 154 __bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT); \ 155 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, \ 156 sizeof(struct bce_dma_slot) * x, \ 157 sizeof(struct bce_dma_slot), \ 158 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 159 } while (/* CONSTCOND */ 0) 160 161 static int bce_probe(struct device *, struct cfdata *, void *); 162 static void bce_attach(struct device *, struct device *, void *); 163 static int bce_ioctl(struct ifnet *, u_long, caddr_t); 164 static void bce_start(struct ifnet *); 165 static void bce_watchdog(struct ifnet *); 166 static int bce_intr(void *); 167 static void bce_rxintr(struct bce_softc *); 168 static void bce_txintr(struct bce_softc *); 169 static int bce_init(struct ifnet *); 170 static void bce_add_mac(struct bce_softc *, u_int8_t *, unsigned long); 171 static int bce_add_rxbuf(struct bce_softc *, int); 172 static void bce_rxdrain(struct bce_softc *); 173 static void bce_stop(struct ifnet *, int); 174 static void bce_reset(struct bce_softc *); 175 static void bce_set_filter(struct ifnet *); 176 static int bce_mii_read(struct device *, int, int); 177 static void bce_mii_write(struct device *, int, int, int); 178 static void bce_statchg(struct device *); 179 static int bce_mediachange(struct ifnet *); 180 static void bce_mediastatus(struct ifnet *, struct ifmediareq *); 181 static void bce_tick(void *); 182 183 #define BCE_DEBUG 184 #ifdef BCE_DEBUG 185 #define DPRINTF(x) do { \ 186 if (bcedebug) \ 187 printf x; \ 188 } while (/* CONSTCOND */ 0) 189 #define DPRINTFN(n,x) do { \ 190 if (bcedebug >= (n)) \ 191 printf x; \ 192 } while (/* CONSTCOND */ 0) 193 int bcedebug = 0; 194 #else 195 #define DPRINTF(x) 196 #define DPRINTFN(n,x) 197 #endif 198 199 #if __NetBSD_Version__ >= 106080000 200 CFATTACH_DECL(bce, sizeof(struct bce_softc), 201 bce_probe, bce_attach, NULL, NULL); 202 #else 203 struct cfattach bce_ca = { 204 sizeof(struct bce_softc), bce_probe, bce_attach 205 }; 206 #endif 207 208 #if __NetBSD_Version__ >= 106120000 209 #define APRINT_ERROR aprint_error 210 #define APRINT_NORMAL aprint_normal 211 #else 212 #define APRINT_ERROR printf 213 #define APRINT_NORMAL printf 214 #endif 215 216 217 static const struct bce_product { 218 pci_vendor_id_t bp_vendor; 219 pci_product_id_t bp_product; 220 const char *bp_name; 221 } bce_products[] = { 222 { 223 PCI_VENDOR_BROADCOM, 224 PCI_PRODUCT_BROADCOM_BCM4401, 225 "Broadcom BCM4401 10/100 Ethernet" 226 }, 227 { 228 0, 229 0, 230 NULL 231 }, 232 }; 233 234 static const struct bce_product * 235 bce_lookup(const struct pci_attach_args * pa) 236 { 237 const struct bce_product *bp; 238 239 for (bp = bce_products; bp->bp_name != NULL; bp++) { 240 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 241 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 242 return (bp); 243 } 244 245 return (NULL); 246 } 247 248 /* 249 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 250 * against drivers product list, and return its name if a match is found. 251 */ 252 int 253 bce_probe(parent, match, aux) 254 struct device *parent; 255 struct cfdata *match; 256 void *aux; 257 { 258 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 259 260 if (bce_lookup(pa) != NULL) 261 return (1); 262 263 return (0); 264 } 265 266 void 267 bce_attach(parent, self, aux) 268 struct device *parent, *self; 269 void *aux; 270 { 271 struct bce_softc *sc = (struct bce_softc *) self; 272 struct pci_attach_args *pa = aux; 273 const struct bce_product *bp; 274 pci_chipset_tag_t pc = pa->pa_pc; 275 pci_intr_handle_t ih; 276 const char *intrstr = NULL; 277 caddr_t kva; 278 bus_dma_segment_t seg; 279 int rseg; 280 u_int32_t command; 281 struct ifnet *ifp; 282 pcireg_t memtype; 283 bus_addr_t memaddr; 284 bus_size_t memsize; 285 int pmreg; 286 pcireg_t pmode; 287 int error; 288 int i; 289 290 bp = bce_lookup(pa); 291 KASSERT(bp != NULL); 292 293 sc->bce_pa = *pa; 294 sc->bce_dmatag = pa->pa_dmat; 295 296 #if __NetBSD_Version__ >= 106120000 297 aprint_naive(": Ethernet controller\n"); 298 #endif 299 APRINT_NORMAL(": %s\n", bp->bp_name); 300 301 /* 302 * Map control/status registers. 303 */ 304 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 305 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 306 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 307 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 308 309 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 310 APRINT_ERROR("%s: failed to enable memory mapping!\n", 311 sc->bce_dev.dv_xname); 312 return; 313 } 314 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BCE_PCI_BAR0); 315 switch (memtype) { 316 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 317 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 318 if (pci_mapreg_map(pa, BCE_PCI_BAR0, memtype, 0, &sc->bce_btag, 319 &sc->bce_bhandle, &memaddr, &memsize) == 0) 320 break; 321 default: 322 APRINT_ERROR("%s: unable to find mem space\n", 323 sc->bce_dev.dv_xname); 324 return; 325 } 326 327 /* Get it out of power save mode if needed. */ 328 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 329 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 330 if (pmode == 3) { 331 /* 332 * The card has lost all configuration data in 333 * this state, so punt. 334 */ 335 printf("%s: unable to wake up from power state D3\n", 336 sc->bce_dev.dv_xname); 337 return; 338 } 339 if (pmode != 0) { 340 printf("%s: waking up from power state D%d\n", 341 sc->bce_dev.dv_xname, pmode); 342 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 343 } 344 } 345 if (pci_intr_map(pa, &ih)) { 346 APRINT_ERROR("%s: couldn't map interrupt\n", 347 sc->bce_dev.dv_xname); 348 return; 349 } 350 intrstr = pci_intr_string(pc, ih); 351 352 sc->bce_intrhand = pci_intr_establish(pc, ih, IPL_NET, bce_intr, sc); 353 354 if (sc->bce_intrhand == NULL) { 355 APRINT_ERROR("%s: couldn't establish interrupt", 356 sc->bce_dev.dv_xname); 357 if (intrstr != NULL) 358 APRINT_NORMAL(" at %s", intrstr); 359 APRINT_NORMAL("\n"); 360 return; 361 } 362 APRINT_NORMAL("%s: interrupting at %s\n", 363 sc->bce_dev.dv_xname, intrstr); 364 365 /* reset the chip */ 366 bce_reset(sc); 367 368 /* 369 * Allocate DMA-safe memory for ring descriptors. 370 * The receive, and transmit rings can not share the same 371 * 4k space, however both are allocated at once here. 372 */ 373 /* 374 * XXX PAGE_SIZE is wasteful; we only need 1KB + 1KB, but 375 * due to the limition above. ?? 376 */ 377 if ((error = bus_dmamem_alloc(sc->bce_dmatag, 378 2 * PAGE_SIZE, PAGE_SIZE, 2 * PAGE_SIZE, 379 &seg, 1, &rseg, BUS_DMA_NOWAIT))) { 380 printf("%s: unable to alloc space for ring descriptors, " 381 "error = %d\n", sc->bce_dev.dv_xname, error); 382 return; 383 } 384 /* map ring space to kernel */ 385 if ((error = bus_dmamem_map(sc->bce_dmatag, &seg, rseg, 386 2 * PAGE_SIZE, &kva, BUS_DMA_NOWAIT))) { 387 printf("%s: unable to map DMA buffers, error = %d\n", 388 sc->bce_dev.dv_xname, error); 389 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 390 return; 391 } 392 /* create a dma map for the ring */ 393 if ((error = bus_dmamap_create(sc->bce_dmatag, 394 2 * PAGE_SIZE, 1, 2 * PAGE_SIZE, 0, BUS_DMA_NOWAIT, 395 &sc->bce_ring_map))) { 396 printf("%s: unable to create ring DMA map, error = %d\n", 397 sc->bce_dev.dv_xname, error); 398 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 399 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 400 return; 401 } 402 /* connect the ring space to the dma map */ 403 if (bus_dmamap_load(sc->bce_dmatag, sc->bce_ring_map, kva, 404 2 * PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) { 405 bus_dmamap_destroy(sc->bce_dmatag, sc->bce_ring_map); 406 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 407 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 408 return; 409 } 410 /* save the ring space in softc */ 411 sc->bce_rx_ring = (struct bce_dma_slot *) kva; 412 sc->bce_tx_ring = (struct bce_dma_slot *) (kva + PAGE_SIZE); 413 414 /* Create the transmit buffer DMA maps. */ 415 for (i = 0; i < BCE_NTXDESC; i++) { 416 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 417 BCE_NTXFRAGS, MCLBYTES, 0, 0, &sc->bce_cdata.bce_tx_map[i])) != 0) { 418 printf("%s: unable to create tx DMA map, error = %d\n", 419 sc->bce_dev.dv_xname, error); 420 } 421 sc->bce_cdata.bce_tx_chain[i] = NULL; 422 } 423 424 /* Create the receive buffer DMA maps. */ 425 for (i = 0; i < BCE_NRXDESC; i++) { 426 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 1, 427 MCLBYTES, 0, 0, &sc->bce_cdata.bce_rx_map[i])) != 0) { 428 printf("%s: unable to create rx DMA map, error = %d\n", 429 sc->bce_dev.dv_xname, error); 430 } 431 sc->bce_cdata.bce_rx_chain[i] = NULL; 432 } 433 434 /* Set up ifnet structure */ 435 ifp = &sc->ethercom.ec_if; 436 strcpy(ifp->if_xname, sc->bce_dev.dv_xname); 437 ifp->if_softc = sc; 438 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 439 ifp->if_ioctl = bce_ioctl; 440 ifp->if_start = bce_start; 441 ifp->if_watchdog = bce_watchdog; 442 ifp->if_init = bce_init; 443 ifp->if_stop = bce_stop; 444 IFQ_SET_READY(&ifp->if_snd); 445 446 /* Initialize our media structures and probe the MII. */ 447 448 sc->bce_mii.mii_ifp = ifp; 449 sc->bce_mii.mii_readreg = bce_mii_read; 450 sc->bce_mii.mii_writereg = bce_mii_write; 451 sc->bce_mii.mii_statchg = bce_statchg; 452 ifmedia_init(&sc->bce_mii.mii_media, 0, bce_mediachange, 453 bce_mediastatus); 454 mii_attach(&sc->bce_dev, &sc->bce_mii, 0xffffffff, MII_PHY_ANY, 455 MII_OFFSET_ANY, 0); 456 if (LIST_FIRST(&sc->bce_mii.mii_phys) == NULL) { 457 ifmedia_add(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 458 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE); 459 } else 460 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_AUTO); 461 /* get the phy */ 462 sc->bce_phy = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 463 BCE_MAGIC_PHY) & 0x1f; 464 /* 465 * Enable activity led. 466 * XXX This should be in a phy driver, but not currently. 467 */ 468 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 469 bce_mii_read((struct device *) sc, 1, 26) & 0x7fff); /* MAGIC */ 470 /* enable traffic meter led mode */ 471 bce_mii_write((struct device *) sc, 1, 27, /* MAGIC */ 472 bce_mii_read((struct device *) sc, 1, 27) | (1 << 6)); /* MAGIC */ 473 474 475 /* Attach the interface */ 476 if_attach(ifp); 477 sc->enaddr[0] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 478 BCE_MAGIC_ENET0); 479 sc->enaddr[1] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 480 BCE_MAGIC_ENET1); 481 sc->enaddr[2] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 482 BCE_MAGIC_ENET2); 483 sc->enaddr[3] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 484 BCE_MAGIC_ENET3); 485 sc->enaddr[4] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 486 BCE_MAGIC_ENET4); 487 sc->enaddr[5] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 488 BCE_MAGIC_ENET5); 489 printf("%s: Ethernet address %s\n", sc->bce_dev.dv_xname, 490 ether_sprintf(sc->enaddr)); 491 ether_ifattach(ifp, sc->enaddr); 492 callout_init(&sc->bce_timeout); 493 } 494 495 /* handle media, and ethernet requests */ 496 static int 497 bce_ioctl(ifp, cmd, data) 498 struct ifnet *ifp; 499 u_long cmd; 500 caddr_t data; 501 { 502 struct bce_softc *sc = ifp->if_softc; 503 struct ifreq *ifr = (struct ifreq *) data; 504 int s, error; 505 506 s = splnet(); 507 switch (cmd) { 508 case SIOCSIFMEDIA: 509 case SIOCGIFMEDIA: 510 error = ifmedia_ioctl(ifp, ifr, &sc->bce_mii.mii_media, cmd); 511 break; 512 default: 513 error = ether_ioctl(ifp, cmd, data); 514 if (error == ENETRESET) { 515 /* change multicast list */ 516 error = 0; 517 } 518 break; 519 } 520 521 /* Try to get more packets going. */ 522 bce_start(ifp); 523 524 splx(s); 525 return error; 526 } 527 528 /* Start packet transmission on the interface. */ 529 static void 530 bce_start(ifp) 531 struct ifnet *ifp; 532 { 533 struct bce_softc *sc = ifp->if_softc; 534 struct mbuf *m0; 535 bus_dmamap_t dmamap; 536 int txstart; 537 int txsfree; 538 int newpkts = 0; 539 int error; 540 541 /* 542 * do not start another if currently transmitting, and more 543 * descriptors(tx slots) are needed for next packet. 544 */ 545 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 546 return; 547 548 /* determine number of descriptors available */ 549 if (sc->bce_txsnext >= sc->bce_txin) 550 txsfree = BCE_NTXDESC - 1 + sc->bce_txin - sc->bce_txsnext; 551 else 552 txsfree = sc->bce_txin - sc->bce_txsnext - 1; 553 554 /* 555 * Loop through the send queue, setting up transmit descriptors 556 * until we drain the queue, or use up all available transmit 557 * descriptors. 558 */ 559 while (txsfree > 0) { 560 int seg; 561 562 /* Grab a packet off the queue. */ 563 IFQ_POLL(&ifp->if_snd, m0); 564 if (m0 == NULL) 565 break; 566 567 /* get the transmit slot dma map */ 568 dmamap = sc->bce_cdata.bce_tx_map[sc->bce_txsnext]; 569 570 /* 571 * Load the DMA map. If this fails, the packet either 572 * didn't fit in the alloted number of segments, or we 573 * were short on resources. If the packet will not fit, 574 * it will be dropped. If short on resources, it will 575 * be tried again later. 576 */ 577 error = bus_dmamap_load_mbuf(sc->bce_dmatag, dmamap, m0, 578 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 579 if (error == EFBIG) { 580 printf("%s: Tx packet consumes too many DMA segments, " 581 "dropping...\n", sc->bce_dev.dv_xname); 582 IFQ_DEQUEUE(&ifp->if_snd, m0); 583 m_freem(m0); 584 ifp->if_oerrors++; 585 continue; 586 } else if (error) { 587 /* short on resources, come back later */ 588 printf("%s: unable to load Tx buffer, error = %d\n", 589 sc->bce_dev.dv_xname, error); 590 break; 591 } 592 /* If not enough descriptors available, try again later */ 593 if (dmamap->dm_nsegs > txsfree) { 594 ifp->if_flags |= IFF_OACTIVE; 595 bus_dmamap_unload(sc->bce_dmatag, dmamap); 596 break; 597 } 598 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 599 600 /* So take it off the queue */ 601 IFQ_DEQUEUE(&ifp->if_snd, m0); 602 603 /* save the pointer so it can be freed later */ 604 sc->bce_cdata.bce_tx_chain[sc->bce_txsnext] = m0; 605 606 /* Sync the data DMA map. */ 607 bus_dmamap_sync(sc->bce_dmatag, dmamap, 0, dmamap->dm_mapsize, 608 BUS_DMASYNC_PREWRITE); 609 610 /* Initialize the transmit descriptor(s). */ 611 txstart = sc->bce_txsnext; 612 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 613 u_int32_t ctrl; 614 615 ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK; 616 if (seg == 0) 617 ctrl |= CTRL_SOF; 618 if (seg == dmamap->dm_nsegs - 1) 619 ctrl |= CTRL_EOF; 620 if (sc->bce_txsnext == BCE_NTXDESC - 1) 621 ctrl |= CTRL_EOT; 622 ctrl |= CTRL_IOC; 623 sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl); 624 sc->bce_tx_ring[sc->bce_txsnext].addr = 625 htole32(dmamap->dm_segs[seg].ds_addr + 0x40000000); /* MAGIC */ 626 if (sc->bce_txsnext + 1 > BCE_NTXDESC - 1) 627 sc->bce_txsnext = 0; 628 else 629 sc->bce_txsnext++; 630 txsfree--; 631 } 632 /* sync descriptors being used */ 633 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 634 sizeof(struct bce_dma_slot) * txstart + PAGE_SIZE, 635 sizeof(struct bce_dma_slot) * dmamap->dm_nsegs, 636 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 637 638 /* Give the packet to the chip. */ 639 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_DPTR, 640 sc->bce_txsnext * sizeof(struct bce_dma_slot)); 641 642 newpkts++; 643 644 #if NBPFILTER > 0 645 /* Pass the packet to any BPF listeners. */ 646 if (ifp->if_bpf) 647 bpf_mtap(ifp->if_bpf, m0); 648 #endif /* NBPFILTER > 0 */ 649 } 650 if (txsfree == 0) { 651 /* No more slots left; notify upper layer. */ 652 ifp->if_flags |= IFF_OACTIVE; 653 } 654 if (newpkts) { 655 /* Set a watchdog timer in case the chip flakes out. */ 656 ifp->if_timer = 5; 657 } 658 } 659 660 /* Watchdog timer handler. */ 661 static void 662 bce_watchdog(ifp) 663 struct ifnet *ifp; 664 { 665 struct bce_softc *sc = ifp->if_softc; 666 667 printf("%s: device timeout\n", sc->bce_dev.dv_xname); 668 ifp->if_oerrors++; 669 670 (void) bce_init(ifp); 671 672 /* Try to get more packets going. */ 673 bce_start(ifp); 674 } 675 676 int 677 bce_intr(xsc) 678 void *xsc; 679 { 680 struct bce_softc *sc; 681 struct ifnet *ifp; 682 u_int32_t intstatus; 683 int wantinit; 684 int handled = 0; 685 686 sc = xsc; 687 ifp = &sc->ethercom.ec_if; 688 689 690 for (wantinit = 0; wantinit == 0;) { 691 intstatus = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 692 BCE_INT_STS); 693 694 /* ignore if not ours, or unsolicited interrupts */ 695 intstatus &= sc->bce_intmask; 696 if (intstatus == 0) 697 break; 698 699 handled = 1; 700 701 /* Ack interrupt */ 702 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS, 703 intstatus); 704 705 /* Receive interrupts. */ 706 if (intstatus & I_RI) 707 bce_rxintr(sc); 708 /* Transmit interrupts. */ 709 if (intstatus & I_XI) 710 bce_txintr(sc); 711 /* Error interrupts */ 712 if (intstatus & ~(I_RI | I_XI)) { 713 if (intstatus & I_XU) 714 printf("%s: transmit fifo underflow\n", 715 sc->bce_dev.dv_xname); 716 if (intstatus & I_RO) { 717 printf("%s: receive fifo overflow\n", 718 sc->bce_dev.dv_xname); 719 ifp->if_ierrors++; 720 } 721 if (intstatus & I_RU) 722 printf("%s: receive descriptor underflow\n", 723 sc->bce_dev.dv_xname); 724 if (intstatus & I_DE) 725 printf("%s: descriptor protocol error\n", 726 sc->bce_dev.dv_xname); 727 if (intstatus & I_PD) 728 printf("%s: data error\n", 729 sc->bce_dev.dv_xname); 730 if (intstatus & I_PC) 731 printf("%s: descriptor error\n", 732 sc->bce_dev.dv_xname); 733 if (intstatus & I_TO) 734 printf("%s: general purpose timeout\n", 735 sc->bce_dev.dv_xname); 736 wantinit = 1; 737 } 738 } 739 740 if (handled) { 741 if (wantinit) 742 bce_init(ifp); 743 /* Try to get more packets going. */ 744 bce_start(ifp); 745 } 746 return (handled); 747 } 748 749 /* Receive interrupt handler */ 750 void 751 bce_rxintr(sc) 752 struct bce_softc *sc; 753 { 754 struct ifnet *ifp = &sc->ethercom.ec_if; 755 struct rx_pph *pph; 756 struct mbuf *m; 757 int curr; 758 int len; 759 int i; 760 761 /* get pointer to active receive slot */ 762 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS) 763 & RS_CD_MASK; 764 curr = curr / sizeof(struct bce_dma_slot); 765 if (curr >= BCE_NRXDESC) 766 curr = BCE_NRXDESC - 1; 767 768 /* process packets up to but not current packet being worked on */ 769 for (i = sc->bce_rxin; i != curr; 770 i + 1 > BCE_NRXDESC - 1 ? i = 0 : i++) { 771 /* complete any post dma memory ops on packet */ 772 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i], 0, 773 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 774 BUS_DMASYNC_POSTREAD); 775 776 /* 777 * If the packet had an error, simply recycle the buffer, 778 * resetting the len, and flags. 779 */ 780 pph = mtod(sc->bce_cdata.bce_rx_chain[i], struct rx_pph *); 781 if (pph->flags & (RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)) { 782 ifp->if_ierrors++; 783 pph->len = 0; 784 pph->flags = 0; 785 continue; 786 } 787 /* receive the packet */ 788 len = pph->len; 789 if (len == 0) 790 continue; /* no packet if empty */ 791 pph->len = 0; 792 pph->flags = 0; 793 /* bump past pre header to packet */ 794 sc->bce_cdata.bce_rx_chain[i]->m_data += 30; /* MAGIC */ 795 796 /* 797 * If the packet is small enough to fit in a 798 * single header mbuf, allocate one and copy 799 * the data into it. This greatly reduces 800 * memory consumption when receiving lots 801 * of small packets. 802 * 803 * Otherwise, add a new buffer to the receive 804 * chain. If this fails, drop the packet and 805 * recycle the old buffer. 806 */ 807 if (len <= (MHLEN - 2)) { 808 MGETHDR(m, M_DONTWAIT, MT_DATA); 809 if (m == NULL) 810 goto dropit; 811 m->m_data += 2; 812 memcpy(mtod(m, caddr_t), 813 mtod(sc->bce_cdata.bce_rx_chain[i], caddr_t), len); 814 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; /* MAGIC */ 815 } else { 816 m = sc->bce_cdata.bce_rx_chain[i]; 817 if (bce_add_rxbuf(sc, i) != 0) { 818 dropit: 819 ifp->if_ierrors++; 820 /* continue to use old buffer */ 821 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; 822 bus_dmamap_sync(sc->bce_dmatag, 823 sc->bce_cdata.bce_rx_map[i], 0, 824 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 825 BUS_DMASYNC_PREREAD); 826 continue; 827 } 828 } 829 830 m->m_flags |= M_HASFCS; 831 m->m_pkthdr.rcvif = ifp; 832 m->m_pkthdr.len = m->m_len = len; 833 ifp->if_ipackets++; 834 835 #if NBPFILTER > 0 836 /* 837 * Pass this up to any BPF listeners, but only 838 * pass it up the stack if it's for us. 839 */ 840 if (ifp->if_bpf) 841 bpf_mtap(ifp->if_bpf, m); 842 #endif /* NBPFILTER > 0 */ 843 844 /* Pass it on. */ 845 (*ifp->if_input) (ifp, m); 846 847 /* re-check current in case it changed */ 848 curr = (bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 849 BCE_DMA_RXSTATUS) & RS_CD_MASK) / 850 sizeof(struct bce_dma_slot); 851 if (curr >= BCE_NRXDESC) 852 curr = BCE_NRXDESC - 1; 853 } 854 sc->bce_rxin = curr; 855 } 856 857 /* Transmit interrupt handler */ 858 void 859 bce_txintr(sc) 860 struct bce_softc *sc; 861 { 862 struct ifnet *ifp = &sc->ethercom.ec_if; 863 int curr; 864 int i; 865 866 ifp->if_flags &= ~IFF_OACTIVE; 867 868 /* 869 * Go through the Tx list and free mbufs for those 870 * frames which have been transmitted. 871 */ 872 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXSTATUS) & 873 RS_CD_MASK; 874 curr = curr / sizeof(struct bce_dma_slot); 875 if (curr >= BCE_NTXDESC) 876 curr = BCE_NTXDESC - 1; 877 for (i = sc->bce_txin; i != curr; 878 i + 1 > BCE_NTXDESC - 1 ? i = 0 : i++) { 879 /* do any post dma memory ops on transmit data */ 880 if (sc->bce_cdata.bce_tx_chain[i] == NULL) 881 continue; 882 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i], 0, 883 sc->bce_cdata.bce_tx_map[i]->dm_mapsize, 884 BUS_DMASYNC_POSTWRITE); 885 bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i]); 886 m_freem(sc->bce_cdata.bce_tx_chain[i]); 887 sc->bce_cdata.bce_tx_chain[i] = NULL; 888 ifp->if_opackets++; 889 } 890 sc->bce_txin = curr; 891 892 /* 893 * If there are no more pending transmissions, cancel the watchdog 894 * timer 895 */ 896 if (sc->bce_txsnext == sc->bce_txin) 897 ifp->if_timer = 0; 898 } 899 900 /* initialize the interface */ 901 static int 902 bce_init(ifp) 903 struct ifnet *ifp; 904 { 905 struct bce_softc *sc = ifp->if_softc; 906 u_int32_t reg_win; 907 int error; 908 int i; 909 910 /* Cancel any pending I/O. */ 911 bce_stop(ifp, 0); 912 913 /* enable pci inerrupts, bursts, and prefetch */ 914 915 /* remap the pci registers to the Sonics config registers */ 916 917 /* save the current map, so it can be restored */ 918 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 919 BCE_REG_WIN); 920 921 /* set register window to Sonics registers */ 922 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 923 BCE_SONICS_WIN); 924 925 /* enable SB to PCI interrupt */ 926 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 927 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) | 928 SBIV_ENET0); 929 930 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 931 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 932 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) | 933 SBTOPCI_PREF | SBTOPCI_BURST); 934 935 /* restore to ethernet register space */ 936 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 937 reg_win); 938 939 /* Reset the chip to a known state. */ 940 bce_reset(sc); 941 942 /* Initialize transmit descriptors */ 943 memset(sc->bce_tx_ring, 0, BCE_NTXDESC * sizeof(struct bce_dma_slot)); 944 sc->bce_txsnext = 0; 945 sc->bce_txin = 0; 946 947 /* enable crc32 generation */ 948 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 949 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) | 950 BCE_EMC_CG); 951 952 /* setup DMA interrupt control */ 953 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1 << 24); /* MAGIC */ 954 955 /* setup packet filter */ 956 bce_set_filter(ifp); 957 958 /* set max frame length, account for possible vlan tag */ 959 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_MAX, 960 ETHER_MAX_LEN + 32); 961 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_MAX, 962 ETHER_MAX_LEN + 32); 963 964 /* set tx watermark */ 965 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_WATER, 56); 966 967 /* enable transmit */ 968 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, XC_XE); 969 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXADDR, 970 sc->bce_ring_map->dm_segs[0].ds_addr + PAGE_SIZE + 0x40000000); /* MAGIC */ 971 972 /* 973 * Give the receive ring to the chip, and 974 * start the receive DMA engine. 975 */ 976 sc->bce_rxin = 0; 977 978 /* clear the rx descriptor ring */ 979 memset(sc->bce_rx_ring, 0, BCE_NRXDESC * sizeof(struct bce_dma_slot)); 980 /* enable receive */ 981 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 982 30 << 1 | 1); /* MAGIC */ 983 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXADDR, 984 sc->bce_ring_map->dm_segs[0].ds_addr + 0x40000000); /* MAGIC */ 985 986 /* Initalize receive descriptors */ 987 for (i = 0; i < BCE_NRXDESC; i++) { 988 if (sc->bce_cdata.bce_rx_chain[i] == NULL) { 989 if ((error = bce_add_rxbuf(sc, i)) != 0) { 990 printf("%s: unable to allocate or map rx(%d) " 991 "mbuf, error = %d\n", sc->bce_dev.dv_xname, 992 i, error); 993 bce_rxdrain(sc); 994 return (error); 995 } 996 } else 997 BCE_INIT_RXDESC(sc, i); 998 } 999 1000 /* Enable interrupts */ 1001 sc->bce_intmask = 1002 I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO; 1003 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 1004 sc->bce_intmask); 1005 1006 /* start the receive dma */ 1007 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR, 1008 BCE_NRXDESC * sizeof(struct bce_dma_slot)); 1009 1010 /* set media */ 1011 mii_mediachg(&sc->bce_mii); 1012 1013 /* turn on the ethernet mac */ 1014 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1015 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1016 BCE_ENET_CTL) | EC_EE); 1017 1018 /* start timer */ 1019 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1020 1021 /* mark as running, and no outputs active */ 1022 ifp->if_flags |= IFF_RUNNING; 1023 ifp->if_flags &= ~IFF_OACTIVE; 1024 1025 return 0; 1026 } 1027 1028 /* add a mac address to packet filter */ 1029 void 1030 bce_add_mac(sc, mac, idx) 1031 struct bce_softc *sc; 1032 u_int8_t *mac; 1033 unsigned long idx; 1034 { 1035 int i; 1036 u_int32_t rval; 1037 1038 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_LOW, 1039 mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]); 1040 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_HI, 1041 mac[0] << 8 | mac[1] | 0x10000); /* MAGIC */ 1042 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1043 idx << 16 | 8); /* MAGIC */ 1044 /* wait for write to complete */ 1045 for (i = 0; i < 100; i++) { 1046 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1047 BCE_FILT_CTL); 1048 if (!(rval & 0x80000000)) /* MAGIC */ 1049 break; 1050 delay(10); 1051 } 1052 if (i == 100) { 1053 printf("%s: timed out writting pkt filter ctl\n", 1054 sc->bce_dev.dv_xname); 1055 } 1056 } 1057 1058 /* Add a receive buffer to the indiciated descriptor. */ 1059 static int 1060 bce_add_rxbuf(sc, idx) 1061 struct bce_softc *sc; 1062 int idx; 1063 { 1064 struct mbuf *m; 1065 int error; 1066 1067 MGETHDR(m, M_DONTWAIT, MT_DATA); 1068 if (m == NULL) 1069 return (ENOBUFS); 1070 1071 MCLGET(m, M_DONTWAIT); 1072 if ((m->m_flags & M_EXT) == 0) { 1073 m_freem(m); 1074 return (ENOBUFS); 1075 } 1076 if (sc->bce_cdata.bce_rx_chain[idx] != NULL) 1077 bus_dmamap_unload(sc->bce_dmatag, 1078 sc->bce_cdata.bce_rx_map[idx]); 1079 1080 sc->bce_cdata.bce_rx_chain[idx] = m; 1081 1082 error = bus_dmamap_load(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 1083 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1084 BUS_DMA_READ | BUS_DMA_NOWAIT); 1085 if (error) 1086 return (error); 1087 1088 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 0, 1089 sc->bce_cdata.bce_rx_map[idx]->dm_mapsize, BUS_DMASYNC_PREREAD); 1090 1091 BCE_INIT_RXDESC(sc, idx); 1092 1093 return (0); 1094 1095 } 1096 1097 /* Drain the receive queue. */ 1098 static void 1099 bce_rxdrain(sc) 1100 struct bce_softc *sc; 1101 { 1102 int i; 1103 1104 for (i = 0; i < BCE_NRXDESC; i++) { 1105 if (sc->bce_cdata.bce_rx_chain[i] != NULL) { 1106 bus_dmamap_unload(sc->bce_dmatag, 1107 sc->bce_cdata.bce_rx_map[i]); 1108 m_freem(sc->bce_cdata.bce_rx_chain[i]); 1109 sc->bce_cdata.bce_rx_chain[i] = NULL; 1110 } 1111 } 1112 } 1113 1114 /* Stop transmission on the interface */ 1115 static void 1116 bce_stop(ifp, disable) 1117 struct ifnet *ifp; 1118 int disable; 1119 { 1120 struct bce_softc *sc = ifp->if_softc; 1121 int i; 1122 u_int32_t val; 1123 1124 /* Stop the 1 second timer */ 1125 callout_stop(&sc->bce_timeout); 1126 1127 /* Down the MII. */ 1128 mii_down(&sc->bce_mii); 1129 1130 /* Disable interrupts. */ 1131 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0); 1132 sc->bce_intmask = 0; 1133 delay(10); 1134 1135 /* Disable emac */ 1136 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED); 1137 for (i = 0; i < 200; i++) { 1138 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1139 BCE_ENET_CTL); 1140 if (!(val & EC_ED)) 1141 break; 1142 delay(10); 1143 } 1144 1145 /* Stop the DMA */ 1146 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 0); 1147 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1148 delay(10); 1149 1150 /* Release any queued transmit buffers. */ 1151 for (i = 0; i < BCE_NTXDESC; i++) { 1152 if (sc->bce_cdata.bce_tx_chain[i] != NULL) { 1153 bus_dmamap_unload(sc->bce_dmatag, 1154 sc->bce_cdata.bce_tx_map[i]); 1155 m_freem(sc->bce_cdata.bce_tx_chain[i]); 1156 sc->bce_cdata.bce_tx_chain[i] = NULL; 1157 } 1158 } 1159 1160 /* drain receive queue */ 1161 if (disable) 1162 bce_rxdrain(sc); 1163 1164 /* Mark the interface down and cancel the watchdog timer. */ 1165 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1166 ifp->if_timer = 0; 1167 } 1168 1169 /* reset the chip */ 1170 static void 1171 bce_reset(sc) 1172 struct bce_softc *sc; 1173 { 1174 u_int32_t val; 1175 u_int32_t sbval; 1176 int i; 1177 1178 /* if SB core is up */ 1179 sbval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1180 BCE_SBTMSTATELOW); 1181 if ((sbval & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK) { 1182 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1183 0); 1184 1185 /* disable emac */ 1186 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1187 EC_ED); 1188 for (i = 0; i < 200; i++) { 1189 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1190 BCE_ENET_CTL); 1191 if (!(val & EC_ED)) 1192 break; 1193 delay(10); 1194 } 1195 if (i == 200) 1196 printf("%s: timed out disabling ethernet mac\n", 1197 sc->bce_dev.dv_xname); 1198 1199 /* reset the dma engines */ 1200 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1201 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS); 1202 /* if error on receive, wait to go idle */ 1203 if (val & RS_ERROR) { 1204 for (i = 0; i < 100; i++) { 1205 val = bus_space_read_4(sc->bce_btag, 1206 sc->bce_bhandle, BCE_DMA_RXSTATUS); 1207 if (val & RS_DMA_IDLE) 1208 break; 1209 delay(10); 1210 } 1211 if (i == 100) 1212 printf("%s: receive dma did not go idle after" 1213 " error\n", sc->bce_dev.dv_xname); 1214 } 1215 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1216 BCE_DMA_RXSTATUS, 0); 1217 1218 /* reset ethernet mac */ 1219 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1220 EC_ES); 1221 for (i = 0; i < 200; i++) { 1222 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1223 BCE_ENET_CTL); 1224 if (!(val & EC_ES)) 1225 break; 1226 delay(10); 1227 } 1228 if (i == 200) 1229 printf("%s: timed out restting ethernet mac\n", 1230 sc->bce_dev.dv_xname); 1231 } else { 1232 u_int32_t reg_win; 1233 1234 /* remap the pci registers to the Sonics config registers */ 1235 1236 /* save the current map, so it can be restored */ 1237 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1238 BCE_REG_WIN); 1239 /* set register window to Sonics registers */ 1240 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1241 BCE_REG_WIN, BCE_SONICS_WIN); 1242 1243 /* enable SB to PCI interrupt */ 1244 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 1245 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1246 BCE_SBINTVEC) | 1247 SBIV_ENET0); 1248 1249 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 1250 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 1251 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1252 BCE_SPCI_TR2) | 1253 SBTOPCI_PREF | SBTOPCI_BURST); 1254 1255 /* restore to ethernet register space */ 1256 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 1257 reg_win); 1258 } 1259 1260 /* disable SB core if not in reset */ 1261 if (!(sbval & SBTML_RESET)) { 1262 1263 /* set the reject bit */ 1264 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1265 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_CLK); 1266 for (i = 0; i < 200; i++) { 1267 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1268 BCE_SBTMSTATELOW); 1269 if (val & SBTML_REJ) 1270 break; 1271 delay(1); 1272 } 1273 if (i == 200) 1274 printf("%s: while restting core, reject did not set\n", 1275 sc->bce_dev.dv_xname); 1276 /* wait until busy is clear */ 1277 for (i = 0; i < 200; i++) { 1278 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1279 BCE_SBTMSTATEHI); 1280 if (!(val & 0x4)) 1281 break; 1282 delay(1); 1283 } 1284 if (i == 200) 1285 printf("%s: while restting core, busy did not clear\n", 1286 sc->bce_dev.dv_xname); 1287 /* set reset and reject while enabling the clocks */ 1288 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1289 BCE_SBTMSTATELOW, 1290 SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET); 1291 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1292 BCE_SBTMSTATELOW); 1293 delay(10); 1294 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1295 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_RESET); 1296 delay(1); 1297 } 1298 /* enable clock */ 1299 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1300 SBTML_FGC | SBTML_CLK | SBTML_RESET); 1301 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1302 delay(1); 1303 1304 /* clear any error bits that may be on */ 1305 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI); 1306 if (val & 1) 1307 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI, 1308 0); 1309 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE); 1310 if (val & SBIM_MAGIC_ERRORBITS) 1311 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE, 1312 val & ~SBIM_MAGIC_ERRORBITS); 1313 1314 /* clear reset and allow it to propagate throughout the core */ 1315 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1316 SBTML_FGC | SBTML_CLK); 1317 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1318 delay(1); 1319 1320 /* leave clock enabled */ 1321 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1322 SBTML_CLK); 1323 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1324 delay(1); 1325 1326 /* initialize MDC preamble, frequency */ 1327 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_CTL, 0x8d); /* MAGIC */ 1328 1329 /* enable phy, differs for internal, and external */ 1330 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL); 1331 if (!(val & BCE_DC_IP)) { 1332 /* select external phy */ 1333 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_EP); 1334 } else if (val & BCE_DC_ER) { /* internal, clear reset bit if on */ 1335 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL, 1336 val & ~BCE_DC_ER); 1337 delay(100); 1338 } 1339 } 1340 1341 /* Set up the receive filter. */ 1342 void 1343 bce_set_filter(ifp) 1344 struct ifnet *ifp; 1345 { 1346 struct bce_softc *sc = ifp->if_softc; 1347 1348 if (ifp->if_flags & IFF_PROMISC) { 1349 ifp->if_flags |= IFF_ALLMULTI; 1350 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1351 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) 1352 | ERC_PE); 1353 } else { 1354 ifp->if_flags &= ~IFF_ALLMULTI; 1355 1356 /* turn off promiscuous */ 1357 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1358 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1359 BCE_RX_CTL) & ~ERC_PE); 1360 1361 /* enable/disable broadcast */ 1362 if (ifp->if_flags & IFF_BROADCAST) 1363 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1364 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1365 sc->bce_bhandle, BCE_RX_CTL) & ~ERC_DB); 1366 else 1367 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1368 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1369 sc->bce_bhandle, BCE_RX_CTL) | ERC_DB); 1370 1371 /* disable the filter */ 1372 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1373 0); 1374 1375 /* add our own address */ 1376 bce_add_mac(sc, sc->enaddr, 0); 1377 1378 /* for now accept all multicast */ 1379 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1380 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) | 1381 ERC_AM); 1382 ifp->if_flags |= IFF_ALLMULTI; 1383 1384 /* enable the filter */ 1385 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1386 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1387 BCE_FILT_CTL) | 1); 1388 } 1389 } 1390 1391 /* Read a PHY register on the MII. */ 1392 int 1393 bce_mii_read(self, phy, reg) 1394 struct device *self; 1395 int phy, reg; 1396 { 1397 struct bce_softc *sc = (struct bce_softc *) self; 1398 int i; 1399 u_int32_t val; 1400 1401 /* clear mii_int */ 1402 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR); 1403 1404 /* Read the PHY register */ 1405 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1406 (MII_COMMAND_READ << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1407 (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */ 1408 1409 for (i = 0; i < BCE_TIMEOUT; i++) { 1410 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS); 1411 if (val & BCE_MIINTR) 1412 break; 1413 delay(10); 1414 } 1415 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1416 if (i == BCE_TIMEOUT) { 1417 printf("%s: PHY read timed out reading phy %d, reg %d, val = " 1418 "0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val); 1419 return (0); 1420 } 1421 return (val & BCE_MICOMM_DATA); 1422 } 1423 1424 /* Write a PHY register on the MII */ 1425 void 1426 bce_mii_write(self, phy, reg, val) 1427 struct device *self; 1428 int phy, reg, val; 1429 { 1430 struct bce_softc *sc = (struct bce_softc *) self; 1431 int i; 1432 u_int32_t rval; 1433 1434 /* clear mii_int */ 1435 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, 1436 BCE_MIINTR); 1437 1438 /* Write the PHY register */ 1439 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1440 (MII_COMMAND_WRITE << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1441 (MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) | /* MAGIC */ 1442 BCE_MIPHY(phy) | BCE_MIREG(reg)); 1443 1444 /* wait for write to complete */ 1445 for (i = 0; i < BCE_TIMEOUT; i++) { 1446 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1447 BCE_MI_STS); 1448 if (rval & BCE_MIINTR) 1449 break; 1450 delay(10); 1451 } 1452 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1453 if (i == BCE_TIMEOUT) { 1454 printf("%s: PHY timed out writting phy %d, reg %d, val " 1455 "= 0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val); 1456 } 1457 } 1458 1459 /* sync hardware duplex mode to software state */ 1460 void 1461 bce_statchg(self) 1462 struct device *self; 1463 { 1464 struct bce_softc *sc = (struct bce_softc *) self; 1465 u_int32_t reg; 1466 1467 /* if needed, change register to match duplex mode */ 1468 reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL); 1469 if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD)) 1470 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1471 reg | EXC_FD); 1472 else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD) 1473 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1474 reg & ~EXC_FD); 1475 1476 /* 1477 * Enable activity led. 1478 * XXX This should be in a phy driver, but not currently. 1479 */ 1480 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 1481 bce_mii_read((struct device *) sc, 1, 26) & 0x7fff); /* MAGIC */ 1482 /* enable traffic meter led mode */ 1483 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 1484 bce_mii_read((struct device *) sc, 1, 27) | (1 << 6)); /* MAGIC */ 1485 } 1486 1487 /* Set hardware to newly-selected media */ 1488 int 1489 bce_mediachange(ifp) 1490 struct ifnet *ifp; 1491 { 1492 struct bce_softc *sc = ifp->if_softc; 1493 1494 if (ifp->if_flags & IFF_UP) 1495 mii_mediachg(&sc->bce_mii); 1496 return (0); 1497 } 1498 1499 /* Get the current interface media status */ 1500 static void 1501 bce_mediastatus(ifp, ifmr) 1502 struct ifnet *ifp; 1503 struct ifmediareq *ifmr; 1504 { 1505 struct bce_softc *sc = ifp->if_softc; 1506 1507 mii_pollstat(&sc->bce_mii); 1508 ifmr->ifm_active = sc->bce_mii.mii_media_active; 1509 ifmr->ifm_status = sc->bce_mii.mii_media_status; 1510 } 1511 1512 /* One second timer, checks link status */ 1513 static void 1514 bce_tick(v) 1515 void *v; 1516 { 1517 struct bce_softc *sc = v; 1518 1519 /* Tick the MII. */ 1520 mii_tick(&sc->bce_mii); 1521 1522 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1523 } 1524
Indexes created Tue Sep 30 11:09:46 GMT 2025