if_bce.c revision 1.50
1 /* $NetBSD: if_bce.c,v 1.50 2019/01/22 03:42:27 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Clifford Wright. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Broadcom BCM440x 10/100 ethernet (broadcom.com) 32 * SiliconBackplane is technology from Sonics, Inc.(sonicsinc.com) 33 * 34 * Cliff Wright cliff (at) snipe444.org 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_bce.c,v 1.50 2019/01/22 03:42:27 msaitoh Exp $"); 39 40 #include "vlan.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/sockio.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/device.h> 50 #include <sys/socket.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #include <net/bpf.h> 58 #include <sys/rndsource.h> 59 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcidevs.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 #include <dev/mii/miidevs.h> 67 #include <dev/mii/brgphyreg.h> 68 69 #include <dev/pci/if_bcereg.h> 70 71 /* transmit buffer max frags allowed */ 72 #define BCE_NTXFRAGS 16 73 74 /* ring descriptor */ 75 struct bce_dma_slot { 76 uint32_t ctrl; 77 uint32_t addr; 78 }; 79 #define CTRL_BC_MASK 0x1fff /* buffer byte count */ 80 #define CTRL_EOT 0x10000000 /* end of descriptor table */ 81 #define CTRL_IOC 0x20000000 /* interrupt on completion */ 82 #define CTRL_EOF 0x40000000 /* end of frame */ 83 #define CTRL_SOF 0x80000000 /* start of frame */ 84 85 /* Packet status is returned in a pre-packet header */ 86 struct rx_pph { 87 uint16_t len; 88 uint16_t flags; 89 uint16_t pad[12]; 90 }; 91 92 /* packet status flags bits */ 93 #define RXF_NO 0x8 /* odd number of nibbles */ 94 #define RXF_RXER 0x4 /* receive symbol error */ 95 #define RXF_CRC 0x2 /* crc error */ 96 #define RXF_OV 0x1 /* fifo overflow */ 97 98 /* number of descriptors used in a ring */ 99 #define BCE_NRXDESC 128 100 #define BCE_NTXDESC 128 101 102 /* 103 * Mbuf pointers. We need these to keep track of the virtual addresses 104 * of our mbuf chains since we can only convert from physical to virtual, 105 * not the other way around. 106 */ 107 struct bce_chain_data { 108 struct mbuf *bce_tx_chain[BCE_NTXDESC]; 109 struct mbuf *bce_rx_chain[BCE_NRXDESC]; 110 bus_dmamap_t bce_tx_map[BCE_NTXDESC]; 111 bus_dmamap_t bce_rx_map[BCE_NRXDESC]; 112 }; 113 114 #define BCE_TIMEOUT 100 /* # 10us for mii read/write */ 115 116 struct bce_softc { 117 device_t bce_dev; 118 bus_space_tag_t bce_btag; 119 bus_space_handle_t bce_bhandle; 120 bus_dma_tag_t bce_dmatag; 121 struct ethercom ethercom; /* interface info */ 122 void *bce_intrhand; 123 struct pci_attach_args bce_pa; 124 struct mii_data bce_mii; 125 uint32_t bce_phy; /* eeprom indicated phy */ 126 struct ifmedia bce_ifmedia; /* media info *//* Check */ 127 uint8_t enaddr[ETHER_ADDR_LEN]; 128 struct bce_dma_slot *bce_rx_ring; /* receive ring */ 129 struct bce_dma_slot *bce_tx_ring; /* transmit ring */ 130 struct bce_chain_data bce_cdata; /* mbufs */ 131 bus_dmamap_t bce_ring_map; 132 uint32_t bce_intmask; /* current intr mask */ 133 uint32_t bce_rxin; /* last rx descriptor seen */ 134 uint32_t bce_txin; /* last tx descriptor seen */ 135 int bce_txsfree; /* no. tx slots available */ 136 int bce_txsnext; /* next available tx slot */ 137 callout_t bce_timeout; 138 krndsource_t rnd_source; 139 }; 140 141 /* for ring descriptors */ 142 #define BCE_RXBUF_LEN (MCLBYTES - 4) 143 #define BCE_INIT_RXDESC(sc, x) \ 144 do { \ 145 struct bce_dma_slot *__bced = &sc->bce_rx_ring[x]; \ 146 \ 147 *mtod(sc->bce_cdata.bce_rx_chain[x], uint32_t *) = 0; \ 148 __bced->addr = \ 149 htole32(sc->bce_cdata.bce_rx_map[x]->dm_segs[0].ds_addr \ 150 + 0x40000000); \ 151 if (x != (BCE_NRXDESC - 1)) \ 152 __bced->ctrl = htole32(BCE_RXBUF_LEN); \ 153 else \ 154 __bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT); \ 155 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, \ 156 sizeof(struct bce_dma_slot) * x, \ 157 sizeof(struct bce_dma_slot), \ 158 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 159 } while (/* CONSTCOND */ 0) 160 161 static int bce_probe(device_t, cfdata_t, void *); 162 static void bce_attach(device_t, device_t, void *); 163 static int bce_ioctl(struct ifnet *, u_long, void *); 164 static void bce_start(struct ifnet *); 165 static void bce_watchdog(struct ifnet *); 166 static int bce_intr(void *); 167 static void bce_rxintr(struct bce_softc *); 168 static void bce_txintr(struct bce_softc *); 169 static int bce_init(struct ifnet *); 170 static void bce_add_mac(struct bce_softc *, uint8_t *, unsigned long); 171 static int bce_add_rxbuf(struct bce_softc *, int); 172 static void bce_rxdrain(struct bce_softc *); 173 static void bce_stop(struct ifnet *, int); 174 static void bce_reset(struct bce_softc *); 175 static bool bce_resume(device_t, const pmf_qual_t *); 176 static void bce_set_filter(struct ifnet *); 177 static int bce_mii_read(device_t, int, int, uint16_t *); 178 static int bce_mii_write(device_t, int, int, uint16_t); 179 static void bce_statchg(struct ifnet *); 180 static void bce_tick(void *); 181 182 CFATTACH_DECL_NEW(bce, sizeof(struct bce_softc), 183 bce_probe, bce_attach, NULL, NULL); 184 185 static const struct bce_product { 186 pci_vendor_id_t bp_vendor; 187 pci_product_id_t bp_product; 188 const char *bp_name; 189 } bce_products[] = { 190 { 191 PCI_VENDOR_BROADCOM, 192 PCI_PRODUCT_BROADCOM_BCM4401, 193 "Broadcom BCM4401 10/100 Ethernet" 194 }, 195 { 196 PCI_VENDOR_BROADCOM, 197 PCI_PRODUCT_BROADCOM_BCM4401_B0, 198 "Broadcom BCM4401-B0 10/100 Ethernet" 199 }, 200 { 201 PCI_VENDOR_BROADCOM, 202 PCI_PRODUCT_BROADCOM_BCM4401_B1, 203 "Broadcom BCM4401-B1 10/100 Ethernet" 204 }, 205 { 206 207 0, 208 0, 209 NULL 210 }, 211 }; 212 213 static const struct bce_product * 214 bce_lookup(const struct pci_attach_args * pa) 215 { 216 const struct bce_product *bp; 217 218 for (bp = bce_products; bp->bp_name != NULL; bp++) { 219 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 220 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 221 return (bp); 222 } 223 224 return (NULL); 225 } 226 227 /* 228 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 229 * against drivers product list, and return its name if a match is found. 230 */ 231 static int 232 bce_probe(device_t parent, cfdata_t match, void *aux) 233 { 234 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 235 236 if (bce_lookup(pa) != NULL) 237 return (1); 238 239 return (0); 240 } 241 242 static void 243 bce_attach(device_t parent, device_t self, void *aux) 244 { 245 struct bce_softc *sc = device_private(self); 246 struct pci_attach_args *pa = aux; 247 const struct bce_product *bp; 248 pci_chipset_tag_t pc = pa->pa_pc; 249 pci_intr_handle_t ih; 250 const char *intrstr = NULL; 251 uint32_t command; 252 pcireg_t memtype, pmode; 253 bus_addr_t memaddr; 254 bus_size_t memsize; 255 void *kva; 256 bus_dma_segment_t seg; 257 int error, i, pmreg, rseg; 258 uint16_t phyval; 259 struct ifnet *ifp; 260 char intrbuf[PCI_INTRSTR_LEN]; 261 262 sc->bce_dev = self; 263 264 bp = bce_lookup(pa); 265 KASSERT(bp != NULL); 266 267 sc->bce_pa = *pa; 268 269 /* BCM440x can only address 30 bits (1GB) */ 270 if (bus_dmatag_subregion(pa->pa_dmat, 0, (1 << 30), 271 &(sc->bce_dmatag), BUS_DMA_NOWAIT) != 0) { 272 aprint_error_dev(self, 273 "WARNING: failed to restrict dma range," 274 " falling back to parent bus dma range\n"); 275 sc->bce_dmatag = pa->pa_dmat; 276 } 277 278 aprint_naive(": Ethernet controller\n"); 279 aprint_normal(": %s\n", bp->bp_name); 280 281 /* 282 * Map control/status registers. 283 */ 284 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 285 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 286 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 287 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 288 289 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 290 aprint_error_dev(self, "failed to enable memory mapping!\n"); 291 return; 292 } 293 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BCE_PCI_BAR0); 294 switch (memtype) { 295 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 296 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 297 if (pci_mapreg_map(pa, BCE_PCI_BAR0, memtype, 0, &sc->bce_btag, 298 &sc->bce_bhandle, &memaddr, &memsize) == 0) 299 break; 300 default: 301 aprint_error_dev(self, "unable to find mem space\n"); 302 return; 303 } 304 305 /* Get it out of power save mode if needed. */ 306 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, NULL)) { 307 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) 308 & PCI_PMCSR_STATE_MASK; 309 if (pmode == PCI_PMCSR_STATE_D3) { 310 /* 311 * The card has lost all configuration data in 312 * this state, so punt. 313 */ 314 aprint_error_dev(self, 315 "unable to wake up from power state D3\n"); 316 return; 317 } 318 if (pmode != PCI_PMCSR_STATE_D0) { 319 aprint_normal_dev(self, 320 "waking up from power state D%d\n", pmode); 321 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 0); 322 } 323 } 324 if (pci_intr_map(pa, &ih)) { 325 aprint_error_dev(self, "couldn't map interrupt\n"); 326 return; 327 } 328 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 329 330 sc->bce_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, bce_intr, 331 sc, device_xname(self)); 332 333 if (sc->bce_intrhand == NULL) { 334 aprint_error_dev(self, "couldn't establish interrupt\n"); 335 if (intrstr != NULL) 336 aprint_error(" at %s", intrstr); 337 aprint_error("\n"); 338 return; 339 } 340 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 341 342 /* reset the chip */ 343 bce_reset(sc); 344 345 /* 346 * Allocate DMA-safe memory for ring descriptors. 347 * The receive, and transmit rings can not share the same 348 * 4k space, however both are allocated at once here. 349 */ 350 /* 351 * XXX PAGE_SIZE is wasteful; we only need 1KB + 1KB, but 352 * due to the limition above. ?? 353 */ 354 if ((error = bus_dmamem_alloc(sc->bce_dmatag, 355 2 * PAGE_SIZE, PAGE_SIZE, 2 * PAGE_SIZE, 356 &seg, 1, &rseg, BUS_DMA_NOWAIT))) { 357 aprint_error_dev(self, 358 "unable to alloc space for ring descriptors, error = %d\n", 359 error); 360 return; 361 } 362 /* map ring space to kernel */ 363 if ((error = bus_dmamem_map(sc->bce_dmatag, &seg, rseg, 364 2 * PAGE_SIZE, &kva, BUS_DMA_NOWAIT))) { 365 aprint_error_dev(self, 366 "unable to map DMA buffers, error = %d\n", error); 367 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 368 return; 369 } 370 /* create a dma map for the ring */ 371 if ((error = bus_dmamap_create(sc->bce_dmatag, 372 2 * PAGE_SIZE, 1, 2 * PAGE_SIZE, 0, BUS_DMA_NOWAIT, 373 &sc->bce_ring_map))) { 374 aprint_error_dev(self, 375 "unable to create ring DMA map, error = %d\n", error); 376 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 377 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 378 return; 379 } 380 /* connect the ring space to the dma map */ 381 if (bus_dmamap_load(sc->bce_dmatag, sc->bce_ring_map, kva, 382 2 * PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) { 383 bus_dmamap_destroy(sc->bce_dmatag, sc->bce_ring_map); 384 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 385 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 386 return; 387 } 388 /* save the ring space in softc */ 389 sc->bce_rx_ring = (struct bce_dma_slot *) kva; 390 sc->bce_tx_ring = (struct bce_dma_slot *) ((char *)kva + PAGE_SIZE); 391 392 /* Create the transmit buffer DMA maps. */ 393 for (i = 0; i < BCE_NTXDESC; i++) { 394 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 395 BCE_NTXFRAGS, MCLBYTES, 0, 0, &sc->bce_cdata.bce_tx_map[i])) != 0) { 396 aprint_error_dev(self, 397 "unable to create tx DMA map, error = %d\n", error); 398 } 399 sc->bce_cdata.bce_tx_chain[i] = NULL; 400 } 401 402 /* Create the receive buffer DMA maps. */ 403 for (i = 0; i < BCE_NRXDESC; i++) { 404 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 1, 405 MCLBYTES, 0, 0, &sc->bce_cdata.bce_rx_map[i])) != 0) { 406 aprint_error_dev(self, 407 "unable to create rx DMA map, error = %d\n", error); 408 } 409 sc->bce_cdata.bce_rx_chain[i] = NULL; 410 } 411 412 /* Set up ifnet structure */ 413 ifp = &sc->ethercom.ec_if; 414 strcpy(ifp->if_xname, device_xname(self)); 415 ifp->if_softc = sc; 416 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 417 ifp->if_ioctl = bce_ioctl; 418 ifp->if_start = bce_start; 419 ifp->if_watchdog = bce_watchdog; 420 ifp->if_init = bce_init; 421 ifp->if_stop = bce_stop; 422 IFQ_SET_READY(&ifp->if_snd); 423 424 /* Initialize our media structures and probe the MII. */ 425 426 sc->bce_mii.mii_ifp = ifp; 427 sc->bce_mii.mii_readreg = bce_mii_read; 428 sc->bce_mii.mii_writereg = bce_mii_write; 429 sc->bce_mii.mii_statchg = bce_statchg; 430 431 sc->ethercom.ec_mii = &sc->bce_mii; 432 ifmedia_init(&sc->bce_mii.mii_media, 0, ether_mediachange, 433 ether_mediastatus); 434 mii_attach(sc->bce_dev, &sc->bce_mii, 0xffffffff, MII_PHY_ANY, 435 MII_OFFSET_ANY, MIIF_FORCEANEG|MIIF_DOPAUSE); 436 if (LIST_FIRST(&sc->bce_mii.mii_phys) == NULL) { 437 ifmedia_add(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 438 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE); 439 } else 440 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_AUTO); 441 /* get the phy */ 442 sc->bce_phy = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 443 BCE_MAGIC_PHY) & 0x1f; 444 /* 445 * Enable activity led. 446 * XXX This should be in a phy driver, but not currently. 447 */ 448 bce_mii_read(sc->bce_dev, 1, 26, &phyval); 449 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 450 phyval & 0x7fff); /* MAGIC */ 451 /* enable traffic meter led mode */ 452 bce_mii_read(sc->bce_dev, 1, 27, &phyval); 453 bce_mii_write(sc->bce_dev, 1, 27, /* MAGIC */ 454 phyval | (1 << 6)); /* MAGIC */ 455 456 /* Attach the interface */ 457 if_attach(ifp); 458 if_deferred_start_init(ifp, NULL); 459 sc->enaddr[0] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 460 BCE_MAGIC_ENET0); 461 sc->enaddr[1] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 462 BCE_MAGIC_ENET1); 463 sc->enaddr[2] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 464 BCE_MAGIC_ENET2); 465 sc->enaddr[3] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 466 BCE_MAGIC_ENET3); 467 sc->enaddr[4] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 468 BCE_MAGIC_ENET4); 469 sc->enaddr[5] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 470 BCE_MAGIC_ENET5); 471 aprint_normal_dev(self, "Ethernet address %s\n", 472 ether_sprintf(sc->enaddr)); 473 ether_ifattach(ifp, sc->enaddr); 474 rnd_attach_source(&sc->rnd_source, device_xname(self), 475 RND_TYPE_NET, RND_FLAG_DEFAULT); 476 callout_init(&sc->bce_timeout, 0); 477 478 if (pmf_device_register(self, NULL, bce_resume)) 479 pmf_class_network_register(self, ifp); 480 else 481 aprint_error_dev(self, "couldn't establish power handler\n"); 482 } 483 484 /* handle media, and ethernet requests */ 485 static int 486 bce_ioctl(struct ifnet *ifp, u_long cmd, void *data) 487 { 488 int s, error; 489 490 s = splnet(); 491 error = ether_ioctl(ifp, cmd, data); 492 if (error == ENETRESET) { 493 /* change multicast list */ 494 error = 0; 495 } 496 497 /* Try to get more packets going. */ 498 bce_start(ifp); 499 500 splx(s); 501 return error; 502 } 503 504 /* Start packet transmission on the interface. */ 505 static void 506 bce_start(struct ifnet *ifp) 507 { 508 struct bce_softc *sc = ifp->if_softc; 509 struct mbuf *m0; 510 bus_dmamap_t dmamap; 511 int txstart; 512 int txsfree; 513 int newpkts = 0; 514 int error; 515 516 /* 517 * do not start another if currently transmitting, and more 518 * descriptors(tx slots) are needed for next packet. 519 */ 520 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 521 return; 522 523 /* determine number of descriptors available */ 524 if (sc->bce_txsnext >= sc->bce_txin) 525 txsfree = BCE_NTXDESC - 1 + sc->bce_txin - sc->bce_txsnext; 526 else 527 txsfree = sc->bce_txin - sc->bce_txsnext - 1; 528 529 /* 530 * Loop through the send queue, setting up transmit descriptors 531 * until we drain the queue, or use up all available transmit 532 * descriptors. 533 */ 534 while (txsfree > 0) { 535 int seg; 536 537 /* Grab a packet off the queue. */ 538 IFQ_POLL(&ifp->if_snd, m0); 539 if (m0 == NULL) 540 break; 541 542 /* get the transmit slot dma map */ 543 dmamap = sc->bce_cdata.bce_tx_map[sc->bce_txsnext]; 544 545 /* 546 * Load the DMA map. If this fails, the packet either 547 * didn't fit in the alloted number of segments, or we 548 * were short on resources. If the packet will not fit, 549 * it will be dropped. If short on resources, it will 550 * be tried again later. 551 */ 552 error = bus_dmamap_load_mbuf(sc->bce_dmatag, dmamap, m0, 553 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 554 if (error == EFBIG) { 555 aprint_error_dev(sc->bce_dev, 556 "Tx packet consumes too many DMA segments, " 557 "dropping...\n"); 558 IFQ_DEQUEUE(&ifp->if_snd, m0); 559 m_freem(m0); 560 ifp->if_oerrors++; 561 continue; 562 } else if (error) { 563 /* short on resources, come back later */ 564 aprint_error_dev(sc->bce_dev, 565 "unable to load Tx buffer, error = %d\n", 566 error); 567 break; 568 } 569 /* If not enough descriptors available, try again later */ 570 if (dmamap->dm_nsegs > txsfree) { 571 ifp->if_flags |= IFF_OACTIVE; 572 bus_dmamap_unload(sc->bce_dmatag, dmamap); 573 break; 574 } 575 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 576 577 /* So take it off the queue */ 578 IFQ_DEQUEUE(&ifp->if_snd, m0); 579 580 /* save the pointer so it can be freed later */ 581 sc->bce_cdata.bce_tx_chain[sc->bce_txsnext] = m0; 582 583 /* Sync the data DMA map. */ 584 bus_dmamap_sync(sc->bce_dmatag, dmamap, 0, dmamap->dm_mapsize, 585 BUS_DMASYNC_PREWRITE); 586 587 /* Initialize the transmit descriptor(s). */ 588 txstart = sc->bce_txsnext; 589 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 590 uint32_t ctrl; 591 592 ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK; 593 if (seg == 0) 594 ctrl |= CTRL_SOF; 595 if (seg == dmamap->dm_nsegs - 1) 596 ctrl |= CTRL_EOF; 597 if (sc->bce_txsnext == BCE_NTXDESC - 1) 598 ctrl |= CTRL_EOT; 599 ctrl |= CTRL_IOC; 600 sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl); 601 sc->bce_tx_ring[sc->bce_txsnext].addr = 602 htole32(dmamap->dm_segs[seg].ds_addr + 0x40000000); /* MAGIC */ 603 if (sc->bce_txsnext + 1 > BCE_NTXDESC - 1) 604 sc->bce_txsnext = 0; 605 else 606 sc->bce_txsnext++; 607 txsfree--; 608 } 609 /* sync descriptors being used */ 610 if ( sc->bce_txsnext > txstart ) { 611 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 612 PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart, 613 sizeof(struct bce_dma_slot) * dmamap->dm_nsegs, 614 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 615 } else { 616 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 617 PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart, 618 sizeof(struct bce_dma_slot) * 619 (BCE_NTXDESC - txstart), 620 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 621 if ( sc->bce_txsnext != 0 ) { 622 bus_dmamap_sync(sc->bce_dmatag, 623 sc->bce_ring_map, PAGE_SIZE, 624 sc->bce_txsnext * 625 sizeof(struct bce_dma_slot), 626 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 627 } 628 } 629 630 /* Give the packet to the chip. */ 631 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_DPTR, 632 sc->bce_txsnext * sizeof(struct bce_dma_slot)); 633 634 newpkts++; 635 636 /* Pass the packet to any BPF listeners. */ 637 bpf_mtap(ifp, m0, BPF_D_OUT); 638 } 639 if (txsfree == 0) { 640 /* No more slots left; notify upper layer. */ 641 ifp->if_flags |= IFF_OACTIVE; 642 } 643 if (newpkts) { 644 /* Set a watchdog timer in case the chip flakes out. */ 645 ifp->if_timer = 5; 646 } 647 } 648 649 /* Watchdog timer handler. */ 650 static void 651 bce_watchdog(struct ifnet *ifp) 652 { 653 struct bce_softc *sc = ifp->if_softc; 654 655 aprint_error_dev(sc->bce_dev, "device timeout\n"); 656 ifp->if_oerrors++; 657 658 (void) bce_init(ifp); 659 660 /* Try to get more packets going. */ 661 bce_start(ifp); 662 } 663 664 int 665 bce_intr(void *xsc) 666 { 667 struct bce_softc *sc; 668 struct ifnet *ifp; 669 uint32_t intstatus; 670 int wantinit; 671 int handled = 0; 672 673 sc = xsc; 674 ifp = &sc->ethercom.ec_if; 675 676 for (wantinit = 0; wantinit == 0;) { 677 intstatus = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 678 BCE_INT_STS); 679 680 /* ignore if not ours, or unsolicited interrupts */ 681 intstatus &= sc->bce_intmask; 682 if (intstatus == 0) 683 break; 684 685 handled = 1; 686 687 /* Ack interrupt */ 688 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS, 689 intstatus); 690 691 /* Receive interrupts. */ 692 if (intstatus & I_RI) 693 bce_rxintr(sc); 694 /* Transmit interrupts. */ 695 if (intstatus & I_XI) 696 bce_txintr(sc); 697 /* Error interrupts */ 698 if (intstatus & ~(I_RI | I_XI)) { 699 const char *msg = NULL; 700 if (intstatus & I_XU) 701 msg = "transmit fifo underflow"; 702 if (intstatus & I_RO) { 703 msg = "receive fifo overflow"; 704 ifp->if_ierrors++; 705 } 706 if (intstatus & I_RU) 707 msg = "receive descriptor underflow"; 708 if (intstatus & I_DE) 709 msg = "descriptor protocol error"; 710 if (intstatus & I_PD) 711 msg = "data error"; 712 if (intstatus & I_PC) 713 msg = "descriptor error"; 714 if (intstatus & I_TO) 715 msg = "general purpose timeout"; 716 if (msg != NULL) 717 aprint_error_dev(sc->bce_dev, "%s\n", msg); 718 wantinit = 1; 719 } 720 } 721 722 if (handled) { 723 if (wantinit) 724 bce_init(ifp); 725 rnd_add_uint32(&sc->rnd_source, intstatus); 726 /* Try to get more packets going. */ 727 if_schedule_deferred_start(ifp); 728 } 729 return (handled); 730 } 731 732 /* Receive interrupt handler */ 733 void 734 bce_rxintr(struct bce_softc *sc) 735 { 736 struct ifnet *ifp = &sc->ethercom.ec_if; 737 struct rx_pph *pph; 738 struct mbuf *m; 739 int curr; 740 int len; 741 int i; 742 743 /* get pointer to active receive slot */ 744 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS) 745 & RS_CD_MASK; 746 curr = curr / sizeof(struct bce_dma_slot); 747 if (curr >= BCE_NRXDESC) 748 curr = BCE_NRXDESC - 1; 749 750 /* process packets up to but not current packet being worked on */ 751 for (i = sc->bce_rxin; i != curr; 752 i + 1 > BCE_NRXDESC - 1 ? i = 0 : i++) { 753 /* complete any post dma memory ops on packet */ 754 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i], 0, 755 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 756 BUS_DMASYNC_POSTREAD); 757 758 /* 759 * If the packet had an error, simply recycle the buffer, 760 * resetting the len, and flags. 761 */ 762 pph = mtod(sc->bce_cdata.bce_rx_chain[i], struct rx_pph *); 763 if (pph->flags & (RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)) { 764 ifp->if_ierrors++; 765 pph->len = 0; 766 pph->flags = 0; 767 continue; 768 } 769 /* receive the packet */ 770 len = pph->len; 771 if (len == 0) 772 continue; /* no packet if empty */ 773 pph->len = 0; 774 pph->flags = 0; 775 /* bump past pre header to packet */ 776 sc->bce_cdata.bce_rx_chain[i]->m_data += 30; /* MAGIC */ 777 778 /* 779 * The chip includes the CRC with every packet. Trim 780 * it off here. 781 */ 782 len -= ETHER_CRC_LEN; 783 784 /* 785 * If the packet is small enough to fit in a 786 * single header mbuf, allocate one and copy 787 * the data into it. This greatly reduces 788 * memory consumption when receiving lots 789 * of small packets. 790 * 791 * Otherwise, add a new buffer to the receive 792 * chain. If this fails, drop the packet and 793 * recycle the old buffer. 794 */ 795 if (len <= (MHLEN - 2)) { 796 MGETHDR(m, M_DONTWAIT, MT_DATA); 797 if (m == NULL) 798 goto dropit; 799 m->m_data += 2; 800 memcpy(mtod(m, void *), 801 mtod(sc->bce_cdata.bce_rx_chain[i], void *), len); 802 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; /* MAGIC */ 803 } else { 804 m = sc->bce_cdata.bce_rx_chain[i]; 805 if (bce_add_rxbuf(sc, i) != 0) { 806 dropit: 807 ifp->if_ierrors++; 808 /* continue to use old buffer */ 809 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; 810 bus_dmamap_sync(sc->bce_dmatag, 811 sc->bce_cdata.bce_rx_map[i], 0, 812 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 813 BUS_DMASYNC_PREREAD); 814 continue; 815 } 816 } 817 818 m_set_rcvif(m, ifp); 819 m->m_pkthdr.len = m->m_len = len; 820 821 /* Pass it on. */ 822 if_percpuq_enqueue(ifp->if_percpuq, m); 823 824 /* re-check current in case it changed */ 825 curr = (bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 826 BCE_DMA_RXSTATUS) & RS_CD_MASK) / 827 sizeof(struct bce_dma_slot); 828 if (curr >= BCE_NRXDESC) 829 curr = BCE_NRXDESC - 1; 830 } 831 sc->bce_rxin = curr; 832 } 833 834 /* Transmit interrupt handler */ 835 void 836 bce_txintr(struct bce_softc *sc) 837 { 838 struct ifnet *ifp = &sc->ethercom.ec_if; 839 int curr; 840 int i; 841 842 ifp->if_flags &= ~IFF_OACTIVE; 843 844 /* 845 * Go through the Tx list and free mbufs for those 846 * frames which have been transmitted. 847 */ 848 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXSTATUS) & 849 RS_CD_MASK; 850 curr = curr / sizeof(struct bce_dma_slot); 851 if (curr >= BCE_NTXDESC) 852 curr = BCE_NTXDESC - 1; 853 for (i = sc->bce_txin; i != curr; 854 i + 1 > BCE_NTXDESC - 1 ? i = 0 : i++) { 855 /* do any post dma memory ops on transmit data */ 856 if (sc->bce_cdata.bce_tx_chain[i] == NULL) 857 continue; 858 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i], 0, 859 sc->bce_cdata.bce_tx_map[i]->dm_mapsize, 860 BUS_DMASYNC_POSTWRITE); 861 bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i]); 862 m_freem(sc->bce_cdata.bce_tx_chain[i]); 863 sc->bce_cdata.bce_tx_chain[i] = NULL; 864 ifp->if_opackets++; 865 } 866 sc->bce_txin = curr; 867 868 /* 869 * If there are no more pending transmissions, cancel the watchdog 870 * timer 871 */ 872 if (sc->bce_txsnext == sc->bce_txin) 873 ifp->if_timer = 0; 874 } 875 876 /* initialize the interface */ 877 static int 878 bce_init(struct ifnet *ifp) 879 { 880 struct bce_softc *sc = ifp->if_softc; 881 uint32_t reg_win; 882 int error; 883 int i; 884 885 /* Cancel any pending I/O. */ 886 bce_stop(ifp, 0); 887 888 /* enable pci inerrupts, bursts, and prefetch */ 889 890 /* remap the pci registers to the Sonics config registers */ 891 892 /* save the current map, so it can be restored */ 893 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 894 BCE_REG_WIN); 895 896 /* set register window to Sonics registers */ 897 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 898 BCE_SONICS_WIN); 899 900 /* enable SB to PCI interrupt */ 901 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 902 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) | 903 SBIV_ENET0); 904 905 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 906 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 907 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) | 908 SBTOPCI_PREF | SBTOPCI_BURST); 909 910 /* restore to ethernet register space */ 911 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 912 reg_win); 913 914 /* Reset the chip to a known state. */ 915 bce_reset(sc); 916 917 /* Initialize transmit descriptors */ 918 memset(sc->bce_tx_ring, 0, BCE_NTXDESC * sizeof(struct bce_dma_slot)); 919 sc->bce_txsnext = 0; 920 sc->bce_txin = 0; 921 922 /* enable crc32 generation */ 923 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 924 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) | 925 BCE_EMC_CG); 926 927 /* setup DMA interrupt control */ 928 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1 << 24); /* MAGIC */ 929 930 /* setup packet filter */ 931 bce_set_filter(ifp); 932 933 /* set max frame length, account for possible vlan tag */ 934 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_MAX, 935 ETHER_MAX_LEN + 32); 936 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_MAX, 937 ETHER_MAX_LEN + 32); 938 939 /* set tx watermark */ 940 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_WATER, 56); 941 942 /* enable transmit */ 943 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, XC_XE); 944 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXADDR, 945 sc->bce_ring_map->dm_segs[0].ds_addr + PAGE_SIZE + 0x40000000); /* MAGIC */ 946 947 /* 948 * Give the receive ring to the chip, and 949 * start the receive DMA engine. 950 */ 951 sc->bce_rxin = 0; 952 953 /* clear the rx descriptor ring */ 954 memset(sc->bce_rx_ring, 0, BCE_NRXDESC * sizeof(struct bce_dma_slot)); 955 /* enable receive */ 956 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 957 30 << 1 | 1); /* MAGIC */ 958 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXADDR, 959 sc->bce_ring_map->dm_segs[0].ds_addr + 0x40000000); /* MAGIC */ 960 961 /* Initalize receive descriptors */ 962 for (i = 0; i < BCE_NRXDESC; i++) { 963 if (sc->bce_cdata.bce_rx_chain[i] == NULL) { 964 if ((error = bce_add_rxbuf(sc, i)) != 0) { 965 aprint_error_dev(sc->bce_dev, 966 "unable to allocate or map rx(%d) " 967 "mbuf, error = %d\n", i, error); 968 bce_rxdrain(sc); 969 return (error); 970 } 971 } else 972 BCE_INIT_RXDESC(sc, i); 973 } 974 975 /* Enable interrupts */ 976 sc->bce_intmask = 977 I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO; 978 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 979 sc->bce_intmask); 980 981 /* start the receive dma */ 982 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR, 983 BCE_NRXDESC * sizeof(struct bce_dma_slot)); 984 985 /* set media */ 986 if ((error = ether_mediachange(ifp)) != 0) 987 return error; 988 989 /* turn on the ethernet mac */ 990 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 991 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 992 BCE_ENET_CTL) | EC_EE); 993 994 /* start timer */ 995 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 996 997 /* mark as running, and no outputs active */ 998 ifp->if_flags |= IFF_RUNNING; 999 ifp->if_flags &= ~IFF_OACTIVE; 1000 1001 return 0; 1002 } 1003 1004 /* add a mac address to packet filter */ 1005 void 1006 bce_add_mac(struct bce_softc *sc, uint8_t *mac, u_long idx) 1007 { 1008 int i; 1009 uint32_t rval; 1010 1011 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_LOW, 1012 mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]); 1013 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_HI, 1014 mac[0] << 8 | mac[1] | 0x10000); /* MAGIC */ 1015 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1016 idx << 16 | 8); /* MAGIC */ 1017 /* wait for write to complete */ 1018 for (i = 0; i < 100; i++) { 1019 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1020 BCE_FILT_CTL); 1021 if (!(rval & 0x80000000)) /* MAGIC */ 1022 break; 1023 delay(10); 1024 } 1025 if (i == 100) { 1026 aprint_error_dev(sc->bce_dev, 1027 "timed out writing pkt filter ctl\n"); 1028 } 1029 } 1030 1031 /* Add a receive buffer to the indiciated descriptor. */ 1032 static int 1033 bce_add_rxbuf(struct bce_softc *sc, int idx) 1034 { 1035 struct mbuf *m; 1036 int error; 1037 1038 MGETHDR(m, M_DONTWAIT, MT_DATA); 1039 if (m == NULL) 1040 return (ENOBUFS); 1041 1042 MCLGET(m, M_DONTWAIT); 1043 if ((m->m_flags & M_EXT) == 0) { 1044 m_freem(m); 1045 return (ENOBUFS); 1046 } 1047 if (sc->bce_cdata.bce_rx_chain[idx] != NULL) 1048 bus_dmamap_unload(sc->bce_dmatag, 1049 sc->bce_cdata.bce_rx_map[idx]); 1050 1051 sc->bce_cdata.bce_rx_chain[idx] = m; 1052 1053 error = bus_dmamap_load(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 1054 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1055 BUS_DMA_READ | BUS_DMA_NOWAIT); 1056 if (error) 1057 return (error); 1058 1059 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 0, 1060 sc->bce_cdata.bce_rx_map[idx]->dm_mapsize, BUS_DMASYNC_PREREAD); 1061 1062 BCE_INIT_RXDESC(sc, idx); 1063 1064 return (0); 1065 1066 } 1067 1068 /* Drain the receive queue. */ 1069 static void 1070 bce_rxdrain(struct bce_softc *sc) 1071 { 1072 int i; 1073 1074 for (i = 0; i < BCE_NRXDESC; i++) { 1075 if (sc->bce_cdata.bce_rx_chain[i] != NULL) { 1076 bus_dmamap_unload(sc->bce_dmatag, 1077 sc->bce_cdata.bce_rx_map[i]); 1078 m_freem(sc->bce_cdata.bce_rx_chain[i]); 1079 sc->bce_cdata.bce_rx_chain[i] = NULL; 1080 } 1081 } 1082 } 1083 1084 /* Stop transmission on the interface */ 1085 static void 1086 bce_stop(struct ifnet *ifp, int disable) 1087 { 1088 struct bce_softc *sc = ifp->if_softc; 1089 int i; 1090 uint32_t val; 1091 1092 /* Stop the 1 second timer */ 1093 callout_stop(&sc->bce_timeout); 1094 1095 /* Down the MII. */ 1096 mii_down(&sc->bce_mii); 1097 1098 /* Disable interrupts. */ 1099 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0); 1100 sc->bce_intmask = 0; 1101 delay(10); 1102 1103 /* Disable emac */ 1104 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED); 1105 for (i = 0; i < 200; i++) { 1106 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1107 BCE_ENET_CTL); 1108 if (!(val & EC_ED)) 1109 break; 1110 delay(10); 1111 } 1112 1113 /* Stop the DMA */ 1114 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 0); 1115 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1116 delay(10); 1117 1118 /* Release any queued transmit buffers. */ 1119 for (i = 0; i < BCE_NTXDESC; i++) { 1120 if (sc->bce_cdata.bce_tx_chain[i] != NULL) { 1121 bus_dmamap_unload(sc->bce_dmatag, 1122 sc->bce_cdata.bce_tx_map[i]); 1123 m_freem(sc->bce_cdata.bce_tx_chain[i]); 1124 sc->bce_cdata.bce_tx_chain[i] = NULL; 1125 } 1126 } 1127 1128 /* Mark the interface down and cancel the watchdog timer. */ 1129 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1130 ifp->if_timer = 0; 1131 1132 /* drain receive queue */ 1133 if (disable) 1134 bce_rxdrain(sc); 1135 } 1136 1137 /* reset the chip */ 1138 static void 1139 bce_reset(struct bce_softc *sc) 1140 { 1141 uint32_t val; 1142 uint32_t sbval; 1143 int i; 1144 1145 /* if SB core is up */ 1146 sbval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1147 BCE_SBTMSTATELOW); 1148 if ((sbval & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK) { 1149 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1150 0); 1151 1152 /* disable emac */ 1153 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1154 EC_ED); 1155 for (i = 0; i < 200; i++) { 1156 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1157 BCE_ENET_CTL); 1158 if (!(val & EC_ED)) 1159 break; 1160 delay(10); 1161 } 1162 if (i == 200) { 1163 aprint_error_dev(sc->bce_dev, 1164 "timed out disabling ethernet mac\n"); 1165 } 1166 1167 /* reset the dma engines */ 1168 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1169 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS); 1170 /* if error on receive, wait to go idle */ 1171 if (val & RS_ERROR) { 1172 for (i = 0; i < 100; i++) { 1173 val = bus_space_read_4(sc->bce_btag, 1174 sc->bce_bhandle, BCE_DMA_RXSTATUS); 1175 if (val & RS_DMA_IDLE) 1176 break; 1177 delay(10); 1178 } 1179 if (i == 100) { 1180 aprint_error_dev(sc->bce_dev, 1181 "receive dma did not go idle after" 1182 " error\n"); 1183 } 1184 } 1185 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1186 BCE_DMA_RXSTATUS, 0); 1187 1188 /* reset ethernet mac */ 1189 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1190 EC_ES); 1191 for (i = 0; i < 200; i++) { 1192 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1193 BCE_ENET_CTL); 1194 if (!(val & EC_ES)) 1195 break; 1196 delay(10); 1197 } 1198 if (i == 200) { 1199 aprint_error_dev(sc->bce_dev, 1200 "timed out resetting ethernet mac\n"); 1201 } 1202 } else { 1203 uint32_t reg_win; 1204 1205 /* remap the pci registers to the Sonics config registers */ 1206 1207 /* save the current map, so it can be restored */ 1208 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1209 BCE_REG_WIN); 1210 /* set register window to Sonics registers */ 1211 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1212 BCE_REG_WIN, BCE_SONICS_WIN); 1213 1214 /* enable SB to PCI interrupt */ 1215 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 1216 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1217 BCE_SBINTVEC) | 1218 SBIV_ENET0); 1219 1220 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 1221 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 1222 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1223 BCE_SPCI_TR2) | 1224 SBTOPCI_PREF | SBTOPCI_BURST); 1225 1226 /* restore to ethernet register space */ 1227 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 1228 reg_win); 1229 } 1230 1231 /* disable SB core if not in reset */ 1232 if (!(sbval & SBTML_RESET)) { 1233 1234 /* set the reject bit */ 1235 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1236 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_CLK); 1237 for (i = 0; i < 200; i++) { 1238 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1239 BCE_SBTMSTATELOW); 1240 if (val & SBTML_REJ) 1241 break; 1242 delay(1); 1243 } 1244 if (i == 200) { 1245 aprint_error_dev(sc->bce_dev, 1246 "while resetting core, reject did not set\n"); 1247 } 1248 /* wait until busy is clear */ 1249 for (i = 0; i < 200; i++) { 1250 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1251 BCE_SBTMSTATEHI); 1252 if (!(val & 0x4)) 1253 break; 1254 delay(1); 1255 } 1256 if (i == 200) { 1257 aprint_error_dev(sc->bce_dev, 1258 "while resetting core, busy did not clear\n"); 1259 } 1260 /* set reset and reject while enabling the clocks */ 1261 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1262 BCE_SBTMSTATELOW, 1263 SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET); 1264 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1265 BCE_SBTMSTATELOW); 1266 delay(10); 1267 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1268 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_RESET); 1269 delay(1); 1270 } 1271 /* enable clock */ 1272 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1273 SBTML_FGC | SBTML_CLK | SBTML_RESET); 1274 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1275 delay(1); 1276 1277 /* clear any error bits that may be on */ 1278 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI); 1279 if (val & 1) 1280 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI, 1281 0); 1282 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE); 1283 if (val & SBIM_MAGIC_ERRORBITS) 1284 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE, 1285 val & ~SBIM_MAGIC_ERRORBITS); 1286 1287 /* clear reset and allow it to propagate throughout the core */ 1288 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1289 SBTML_FGC | SBTML_CLK); 1290 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1291 delay(1); 1292 1293 /* leave clock enabled */ 1294 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1295 SBTML_CLK); 1296 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1297 delay(1); 1298 1299 /* initialize MDC preamble, frequency */ 1300 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_CTL, 0x8d); /* MAGIC */ 1301 1302 /* enable phy, differs for internal, and external */ 1303 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL); 1304 if (!(val & BCE_DC_IP)) { 1305 /* select external phy */ 1306 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_EP); 1307 } else if (val & BCE_DC_ER) { /* internal, clear reset bit if on */ 1308 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL, 1309 val & ~BCE_DC_ER); 1310 delay(100); 1311 } 1312 } 1313 1314 /* Set up the receive filter. */ 1315 void 1316 bce_set_filter(struct ifnet *ifp) 1317 { 1318 struct bce_softc *sc = ifp->if_softc; 1319 1320 if (ifp->if_flags & IFF_PROMISC) { 1321 ifp->if_flags |= IFF_ALLMULTI; 1322 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1323 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) 1324 | ERC_PE); 1325 } else { 1326 ifp->if_flags &= ~IFF_ALLMULTI; 1327 1328 /* turn off promiscuous */ 1329 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1330 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1331 BCE_RX_CTL) & ~ERC_PE); 1332 1333 /* enable/disable broadcast */ 1334 if (ifp->if_flags & IFF_BROADCAST) 1335 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1336 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1337 sc->bce_bhandle, BCE_RX_CTL) & ~ERC_DB); 1338 else 1339 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1340 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1341 sc->bce_bhandle, BCE_RX_CTL) | ERC_DB); 1342 1343 /* disable the filter */ 1344 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1345 0); 1346 1347 /* add our own address */ 1348 bce_add_mac(sc, sc->enaddr, 0); 1349 1350 /* for now accept all multicast */ 1351 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1352 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) | 1353 ERC_AM); 1354 ifp->if_flags |= IFF_ALLMULTI; 1355 1356 /* enable the filter */ 1357 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1358 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1359 BCE_FILT_CTL) | 1); 1360 } 1361 } 1362 1363 static bool 1364 bce_resume(device_t self, const pmf_qual_t *qual) 1365 { 1366 struct bce_softc *sc = device_private(self); 1367 1368 bce_reset(sc); 1369 1370 return true; 1371 } 1372 1373 /* Read a PHY register on the MII. */ 1374 int 1375 bce_mii_read(device_t self, int phy, int reg, uint16_t *val) 1376 { 1377 struct bce_softc *sc = device_private(self); 1378 int i; 1379 uint32_t data; 1380 1381 /* clear mii_int */ 1382 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR); 1383 1384 /* Read the PHY register */ 1385 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1386 (MII_COMMAND_READ << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1387 (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */ 1388 1389 for (i = 0; i < BCE_TIMEOUT; i++) { 1390 data = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1391 BCE_MI_STS); 1392 if (data & BCE_MIINTR) 1393 break; 1394 delay(10); 1395 } 1396 data = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1397 if (i == BCE_TIMEOUT) { 1398 aprint_error_dev(sc->bce_dev, 1399 "PHY read timed out reading phy %d, reg %d, val = " 1400 "0x%08x\n", phy, reg, data); 1401 return ETIMEDOUT; 1402 } 1403 *val = data & BCE_MICOMM_DATA; 1404 return 0; 1405 } 1406 1407 /* Write a PHY register on the MII */ 1408 int 1409 bce_mii_write(device_t self, int phy, int reg, uint16_t val) 1410 { 1411 struct bce_softc *sc = device_private(self); 1412 int i; 1413 uint32_t data; 1414 1415 /* clear mii_int */ 1416 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, 1417 BCE_MIINTR); 1418 1419 /* Write the PHY register */ 1420 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1421 (MII_COMMAND_WRITE << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1422 (MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) | /* MAGIC */ 1423 BCE_MIPHY(phy) | BCE_MIREG(reg)); 1424 1425 /* wait for write to complete */ 1426 for (i = 0; i < BCE_TIMEOUT; i++) { 1427 data = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1428 BCE_MI_STS); 1429 if (data & BCE_MIINTR) 1430 break; 1431 delay(10); 1432 } 1433 if (i == BCE_TIMEOUT) { 1434 aprint_error_dev(sc->bce_dev, 1435 "PHY timed out writing phy %d, reg %d, val = 0x%04hx\n", 1436 phy, reg, val); 1437 return ETIMEDOUT; 1438 } 1439 1440 return 0; 1441 } 1442 1443 /* sync hardware duplex mode to software state */ 1444 void 1445 bce_statchg(struct ifnet *ifp) 1446 { 1447 struct bce_softc *sc = ifp->if_softc; 1448 uint32_t reg; 1449 uint16_t phyval; 1450 1451 /* if needed, change register to match duplex mode */ 1452 reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL); 1453 if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD)) 1454 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1455 reg | EXC_FD); 1456 else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD) 1457 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1458 reg & ~EXC_FD); 1459 1460 /* 1461 * Enable activity led. 1462 * XXX This should be in a phy driver, but not currently. 1463 */ 1464 bce_mii_read(sc->bce_dev, 1, 26, &phyval); 1465 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 1466 phyval & 0x7fff); /* MAGIC */ 1467 /* enable traffic meter led mode */ 1468 bce_mii_read(sc->bce_dev, 1, 27, &phyval); 1469 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 1470 phyval | (1 << 6)); /* MAGIC */ 1471 } 1472 1473 /* One second timer, checks link status */ 1474 static void 1475 bce_tick(void *v) 1476 { 1477 struct bce_softc *sc = v; 1478 1479 /* Tick the MII. */ 1480 mii_tick(&sc->bce_mii); 1481 1482 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1483 } 1484
Indexes created Tue Sep 30 17:09:57 GMT 2025