if_bce.c revision 1.54
1 /* $NetBSD: if_bce.c,v 1.54 2019/10/18 04:09:02 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Clifford Wright. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Broadcom BCM440x 10/100 ethernet (broadcom.com) 32 * SiliconBackplane is technology from Sonics, Inc.(sonicsinc.com) 33 * 34 * Cliff Wright cliff (at) snipe444.org 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_bce.c,v 1.54 2019/10/18 04:09:02 msaitoh Exp $"); 39 40 #include "vlan.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/sockio.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/device.h> 50 #include <sys/socket.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #include <net/bpf.h> 58 #include <sys/rndsource.h> 59 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcidevs.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 #include <dev/mii/miidevs.h> 67 #include <dev/mii/brgphyreg.h> 68 69 #include <dev/pci/if_bcereg.h> 70 71 /* transmit buffer max frags allowed */ 72 #define BCE_NTXFRAGS 16 73 74 /* ring descriptor */ 75 struct bce_dma_slot { 76 uint32_t ctrl; 77 uint32_t addr; 78 }; 79 #define CTRL_BC_MASK 0x1fff /* buffer byte count */ 80 #define CTRL_EOT 0x10000000 /* end of descriptor table */ 81 #define CTRL_IOC 0x20000000 /* interrupt on completion */ 82 #define CTRL_EOF 0x40000000 /* end of frame */ 83 #define CTRL_SOF 0x80000000 /* start of frame */ 84 85 /* Packet status is returned in a pre-packet header */ 86 struct rx_pph { 87 uint16_t len; 88 uint16_t flags; 89 uint16_t pad[12]; 90 }; 91 92 /* packet status flags bits */ 93 #define RXF_NO 0x8 /* odd number of nibbles */ 94 #define RXF_RXER 0x4 /* receive symbol error */ 95 #define RXF_CRC 0x2 /* crc error */ 96 #define RXF_OV 0x1 /* fifo overflow */ 97 98 /* number of descriptors used in a ring */ 99 #define BCE_NRXDESC 128 100 #define BCE_NTXDESC 128 101 102 /* 103 * Mbuf pointers. We need these to keep track of the virtual addresses 104 * of our mbuf chains since we can only convert from physical to virtual, 105 * not the other way around. 106 */ 107 struct bce_chain_data { 108 struct mbuf *bce_tx_chain[BCE_NTXDESC]; 109 struct mbuf *bce_rx_chain[BCE_NRXDESC]; 110 bus_dmamap_t bce_tx_map[BCE_NTXDESC]; 111 bus_dmamap_t bce_rx_map[BCE_NRXDESC]; 112 }; 113 114 #define BCE_TIMEOUT 100 /* # 10us for mii read/write */ 115 116 struct bce_softc { 117 device_t bce_dev; 118 bus_space_tag_t bce_btag; 119 bus_space_handle_t bce_bhandle; 120 bus_dma_tag_t bce_dmatag; 121 struct ethercom ethercom; /* interface info */ 122 void *bce_intrhand; 123 struct pci_attach_args bce_pa; 124 struct mii_data bce_mii; 125 uint32_t bce_phy; /* eeprom indicated phy */ 126 struct ifmedia bce_ifmedia; /* media info *//* Check */ 127 uint8_t enaddr[ETHER_ADDR_LEN]; 128 struct bce_dma_slot *bce_rx_ring; /* receive ring */ 129 struct bce_dma_slot *bce_tx_ring; /* transmit ring */ 130 struct bce_chain_data bce_cdata; /* mbufs */ 131 bus_dmamap_t bce_ring_map; 132 uint32_t bce_intmask; /* current intr mask */ 133 uint32_t bce_rxin; /* last rx descriptor seen */ 134 uint32_t bce_txin; /* last tx descriptor seen */ 135 int bce_txsfree; /* no. tx slots available */ 136 int bce_txsnext; /* next available tx slot */ 137 callout_t bce_timeout; 138 krndsource_t rnd_source; 139 }; 140 141 /* for ring descriptors */ 142 #define BCE_RXBUF_LEN (MCLBYTES - 4) 143 #define BCE_INIT_RXDESC(sc, x) \ 144 do { \ 145 struct bce_dma_slot *__bced = &sc->bce_rx_ring[x]; \ 146 \ 147 *mtod(sc->bce_cdata.bce_rx_chain[x], uint32_t *) = 0; \ 148 __bced->addr = \ 149 htole32(sc->bce_cdata.bce_rx_map[x]->dm_segs[0].ds_addr \ 150 + 0x40000000); \ 151 if (x != (BCE_NRXDESC - 1)) \ 152 __bced->ctrl = htole32(BCE_RXBUF_LEN); \ 153 else \ 154 __bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT); \ 155 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, \ 156 sizeof(struct bce_dma_slot) * x, \ 157 sizeof(struct bce_dma_slot), \ 158 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 159 } while (/* CONSTCOND */ 0) 160 161 static int bce_probe(device_t, cfdata_t, void *); 162 static void bce_attach(device_t, device_t, void *); 163 static int bce_ioctl(struct ifnet *, u_long, void *); 164 static void bce_start(struct ifnet *); 165 static void bce_watchdog(struct ifnet *); 166 static int bce_intr(void *); 167 static void bce_rxintr(struct bce_softc *); 168 static void bce_txintr(struct bce_softc *); 169 static int bce_init(struct ifnet *); 170 static void bce_add_mac(struct bce_softc *, uint8_t *, unsigned long); 171 static int bce_add_rxbuf(struct bce_softc *, int); 172 static void bce_rxdrain(struct bce_softc *); 173 static void bce_stop(struct ifnet *, int); 174 static void bce_reset(struct bce_softc *); 175 static bool bce_resume(device_t, const pmf_qual_t *); 176 static void bce_set_filter(struct ifnet *); 177 static int bce_mii_read(device_t, int, int, uint16_t *); 178 static int bce_mii_write(device_t, int, int, uint16_t); 179 static void bce_statchg(struct ifnet *); 180 static void bce_tick(void *); 181 182 CFATTACH_DECL_NEW(bce, sizeof(struct bce_softc), 183 bce_probe, bce_attach, NULL, NULL); 184 185 static const struct bce_product { 186 pci_vendor_id_t bp_vendor; 187 pci_product_id_t bp_product; 188 const char *bp_name; 189 } bce_products[] = { 190 { 191 PCI_VENDOR_BROADCOM, 192 PCI_PRODUCT_BROADCOM_BCM4401, 193 "Broadcom BCM4401 10/100 Ethernet" 194 }, 195 { 196 PCI_VENDOR_BROADCOM, 197 PCI_PRODUCT_BROADCOM_BCM4401_B0, 198 "Broadcom BCM4401-B0 10/100 Ethernet" 199 }, 200 { 201 PCI_VENDOR_BROADCOM, 202 PCI_PRODUCT_BROADCOM_BCM4401_B1, 203 "Broadcom BCM4401-B1 10/100 Ethernet" 204 }, 205 { 206 207 0, 208 0, 209 NULL 210 }, 211 }; 212 213 static const struct bce_product * 214 bce_lookup(const struct pci_attach_args * pa) 215 { 216 const struct bce_product *bp; 217 218 for (bp = bce_products; bp->bp_name != NULL; bp++) { 219 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 220 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 221 return (bp); 222 } 223 224 return (NULL); 225 } 226 227 /* 228 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 229 * against drivers product list, and return its name if a match is found. 230 */ 231 static int 232 bce_probe(device_t parent, cfdata_t match, void *aux) 233 { 234 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 235 236 if (bce_lookup(pa) != NULL) 237 return (1); 238 239 return (0); 240 } 241 242 static void 243 bce_attach(device_t parent, device_t self, void *aux) 244 { 245 struct bce_softc *sc = device_private(self); 246 struct pci_attach_args *pa = aux; 247 const struct bce_product *bp; 248 pci_chipset_tag_t pc = pa->pa_pc; 249 pci_intr_handle_t ih; 250 const char *intrstr = NULL; 251 uint32_t command; 252 pcireg_t memtype, pmode; 253 bus_addr_t memaddr; 254 bus_size_t memsize; 255 void *kva; 256 bus_dma_segment_t seg; 257 int error, i, pmreg, rseg; 258 uint16_t phyval; 259 struct ifnet *ifp; 260 struct mii_data *mii = &sc->bce_mii; 261 char intrbuf[PCI_INTRSTR_LEN]; 262 263 sc->bce_dev = self; 264 265 bp = bce_lookup(pa); 266 KASSERT(bp != NULL); 267 268 sc->bce_pa = *pa; 269 270 /* BCM440x can only address 30 bits (1GB) */ 271 if (bus_dmatag_subregion(pa->pa_dmat, 0, (1 << 30), 272 &(sc->bce_dmatag), BUS_DMA_NOWAIT) != 0) { 273 aprint_error_dev(self, 274 "WARNING: failed to restrict dma range," 275 " falling back to parent bus dma range\n"); 276 sc->bce_dmatag = pa->pa_dmat; 277 } 278 279 aprint_naive(": Ethernet controller\n"); 280 aprint_normal(": %s\n", bp->bp_name); 281 282 /* 283 * Map control/status registers. 284 */ 285 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 286 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 287 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 288 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 289 290 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 291 aprint_error_dev(self, "failed to enable memory mapping!\n"); 292 return; 293 } 294 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BCE_PCI_BAR0); 295 switch (memtype) { 296 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 297 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 298 if (pci_mapreg_map(pa, BCE_PCI_BAR0, memtype, 0, &sc->bce_btag, 299 &sc->bce_bhandle, &memaddr, &memsize) == 0) 300 break; 301 /* FALLTHROUGH */ 302 default: 303 aprint_error_dev(self, "unable to find mem space\n"); 304 return; 305 } 306 307 /* Get it out of power save mode if needed. */ 308 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, NULL)) { 309 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) 310 & PCI_PMCSR_STATE_MASK; 311 if (pmode == PCI_PMCSR_STATE_D3) { 312 /* 313 * The card has lost all configuration data in 314 * this state, so punt. 315 */ 316 aprint_error_dev(self, 317 "unable to wake up from power state D3\n"); 318 return; 319 } 320 if (pmode != PCI_PMCSR_STATE_D0) { 321 aprint_normal_dev(self, 322 "waking up from power state D%d\n", pmode); 323 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 0); 324 } 325 } 326 if (pci_intr_map(pa, &ih)) { 327 aprint_error_dev(self, "couldn't map interrupt\n"); 328 return; 329 } 330 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 331 332 sc->bce_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, bce_intr, 333 sc, device_xname(self)); 334 335 if (sc->bce_intrhand == NULL) { 336 aprint_error_dev(self, "couldn't establish interrupt\n"); 337 if (intrstr != NULL) 338 aprint_error(" at %s", intrstr); 339 aprint_error("\n"); 340 return; 341 } 342 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 343 344 /* reset the chip */ 345 bce_reset(sc); 346 347 /* 348 * Allocate DMA-safe memory for ring descriptors. 349 * The receive, and transmit rings can not share the same 350 * 4k space, however both are allocated at once here. 351 */ 352 /* 353 * XXX PAGE_SIZE is wasteful; we only need 1KB + 1KB, but 354 * due to the limition above. ?? 355 */ 356 if ((error = bus_dmamem_alloc(sc->bce_dmatag, 357 2 * PAGE_SIZE, PAGE_SIZE, 2 * PAGE_SIZE, 358 &seg, 1, &rseg, BUS_DMA_NOWAIT))) { 359 aprint_error_dev(self, 360 "unable to alloc space for ring descriptors, error = %d\n", 361 error); 362 return; 363 } 364 /* map ring space to kernel */ 365 if ((error = bus_dmamem_map(sc->bce_dmatag, &seg, rseg, 366 2 * PAGE_SIZE, &kva, BUS_DMA_NOWAIT))) { 367 aprint_error_dev(self, 368 "unable to map DMA buffers, error = %d\n", error); 369 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 370 return; 371 } 372 /* create a dma map for the ring */ 373 if ((error = bus_dmamap_create(sc->bce_dmatag, 374 2 * PAGE_SIZE, 1, 2 * PAGE_SIZE, 0, BUS_DMA_NOWAIT, 375 &sc->bce_ring_map))) { 376 aprint_error_dev(self, 377 "unable to create ring DMA map, error = %d\n", error); 378 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 379 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 380 return; 381 } 382 /* connect the ring space to the dma map */ 383 if (bus_dmamap_load(sc->bce_dmatag, sc->bce_ring_map, kva, 384 2 * PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) { 385 bus_dmamap_destroy(sc->bce_dmatag, sc->bce_ring_map); 386 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 387 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 388 return; 389 } 390 /* save the ring space in softc */ 391 sc->bce_rx_ring = (struct bce_dma_slot *) kva; 392 sc->bce_tx_ring = (struct bce_dma_slot *) ((char *)kva + PAGE_SIZE); 393 394 /* Create the transmit buffer DMA maps. */ 395 for (i = 0; i < BCE_NTXDESC; i++) { 396 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 397 BCE_NTXFRAGS, MCLBYTES, 0, 0, &sc->bce_cdata.bce_tx_map[i])) != 0) { 398 aprint_error_dev(self, 399 "unable to create tx DMA map, error = %d\n", error); 400 } 401 sc->bce_cdata.bce_tx_chain[i] = NULL; 402 } 403 404 /* Create the receive buffer DMA maps. */ 405 for (i = 0; i < BCE_NRXDESC; i++) { 406 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 1, 407 MCLBYTES, 0, 0, &sc->bce_cdata.bce_rx_map[i])) != 0) { 408 aprint_error_dev(self, 409 "unable to create rx DMA map, error = %d\n", error); 410 } 411 sc->bce_cdata.bce_rx_chain[i] = NULL; 412 } 413 414 /* Set up ifnet structure */ 415 ifp = &sc->ethercom.ec_if; 416 strcpy(ifp->if_xname, device_xname(self)); 417 ifp->if_softc = sc; 418 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 419 ifp->if_ioctl = bce_ioctl; 420 ifp->if_start = bce_start; 421 ifp->if_watchdog = bce_watchdog; 422 ifp->if_init = bce_init; 423 ifp->if_stop = bce_stop; 424 IFQ_SET_READY(&ifp->if_snd); 425 426 /* Initialize our media structures and probe the MII. */ 427 428 mii->mii_ifp = ifp; 429 mii->mii_readreg = bce_mii_read; 430 mii->mii_writereg = bce_mii_write; 431 mii->mii_statchg = bce_statchg; 432 433 sc->ethercom.ec_mii = mii; 434 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 435 mii_attach(sc->bce_dev, mii, 0xffffffff, MII_PHY_ANY, 436 MII_OFFSET_ANY, MIIF_FORCEANEG|MIIF_DOPAUSE); 437 if (LIST_FIRST(&mii->mii_phys) == NULL) { 438 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 439 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 440 } else 441 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 442 /* get the phy */ 443 sc->bce_phy = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 444 BCE_MAGIC_PHY) & 0x1f; 445 /* 446 * Enable activity led. 447 * XXX This should be in a phy driver, but not currently. 448 */ 449 bce_mii_read(sc->bce_dev, 1, 26, &phyval); 450 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 451 phyval & 0x7fff); /* MAGIC */ 452 /* enable traffic meter led mode */ 453 bce_mii_read(sc->bce_dev, 1, 27, &phyval); 454 bce_mii_write(sc->bce_dev, 1, 27, /* MAGIC */ 455 phyval | (1 << 6)); /* MAGIC */ 456 457 /* Attach the interface */ 458 if_attach(ifp); 459 if_deferred_start_init(ifp, NULL); 460 sc->enaddr[0] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 461 BCE_MAGIC_ENET0); 462 sc->enaddr[1] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 463 BCE_MAGIC_ENET1); 464 sc->enaddr[2] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 465 BCE_MAGIC_ENET2); 466 sc->enaddr[3] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 467 BCE_MAGIC_ENET3); 468 sc->enaddr[4] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 469 BCE_MAGIC_ENET4); 470 sc->enaddr[5] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 471 BCE_MAGIC_ENET5); 472 aprint_normal_dev(self, "Ethernet address %s\n", 473 ether_sprintf(sc->enaddr)); 474 ether_ifattach(ifp, sc->enaddr); 475 rnd_attach_source(&sc->rnd_source, device_xname(self), 476 RND_TYPE_NET, RND_FLAG_DEFAULT); 477 callout_init(&sc->bce_timeout, 0); 478 479 if (pmf_device_register(self, NULL, bce_resume)) 480 pmf_class_network_register(self, ifp); 481 else 482 aprint_error_dev(self, "couldn't establish power handler\n"); 483 } 484 485 /* handle media, and ethernet requests */ 486 static int 487 bce_ioctl(struct ifnet *ifp, u_long cmd, void *data) 488 { 489 int s, error; 490 491 s = splnet(); 492 error = ether_ioctl(ifp, cmd, data); 493 if (error == ENETRESET) { 494 /* change multicast list */ 495 error = 0; 496 } 497 498 /* Try to get more packets going. */ 499 bce_start(ifp); 500 501 splx(s); 502 return error; 503 } 504 505 /* Start packet transmission on the interface. */ 506 static void 507 bce_start(struct ifnet *ifp) 508 { 509 struct bce_softc *sc = ifp->if_softc; 510 struct mbuf *m0; 511 bus_dmamap_t dmamap; 512 int txstart; 513 int txsfree; 514 int newpkts = 0; 515 int error; 516 517 /* 518 * do not start another if currently transmitting, and more 519 * descriptors(tx slots) are needed for next packet. 520 */ 521 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 522 return; 523 524 /* determine number of descriptors available */ 525 if (sc->bce_txsnext >= sc->bce_txin) 526 txsfree = BCE_NTXDESC - 1 + sc->bce_txin - sc->bce_txsnext; 527 else 528 txsfree = sc->bce_txin - sc->bce_txsnext - 1; 529 530 /* 531 * Loop through the send queue, setting up transmit descriptors 532 * until we drain the queue, or use up all available transmit 533 * descriptors. 534 */ 535 while (txsfree > 0) { 536 int seg; 537 538 /* Grab a packet off the queue. */ 539 IFQ_POLL(&ifp->if_snd, m0); 540 if (m0 == NULL) 541 break; 542 543 /* get the transmit slot dma map */ 544 dmamap = sc->bce_cdata.bce_tx_map[sc->bce_txsnext]; 545 546 /* 547 * Load the DMA map. If this fails, the packet either 548 * didn't fit in the alloted number of segments, or we 549 * were short on resources. If the packet will not fit, 550 * it will be dropped. If short on resources, it will 551 * be tried again later. 552 */ 553 error = bus_dmamap_load_mbuf(sc->bce_dmatag, dmamap, m0, 554 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 555 if (error == EFBIG) { 556 aprint_error_dev(sc->bce_dev, 557 "Tx packet consumes too many DMA segments, " 558 "dropping...\n"); 559 IFQ_DEQUEUE(&ifp->if_snd, m0); 560 m_freem(m0); 561 ifp->if_oerrors++; 562 continue; 563 } else if (error) { 564 /* short on resources, come back later */ 565 aprint_error_dev(sc->bce_dev, 566 "unable to load Tx buffer, error = %d\n", 567 error); 568 break; 569 } 570 /* If not enough descriptors available, try again later */ 571 if (dmamap->dm_nsegs > txsfree) { 572 ifp->if_flags |= IFF_OACTIVE; 573 bus_dmamap_unload(sc->bce_dmatag, dmamap); 574 break; 575 } 576 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 577 578 /* So take it off the queue */ 579 IFQ_DEQUEUE(&ifp->if_snd, m0); 580 581 /* save the pointer so it can be freed later */ 582 sc->bce_cdata.bce_tx_chain[sc->bce_txsnext] = m0; 583 584 /* Sync the data DMA map. */ 585 bus_dmamap_sync(sc->bce_dmatag, dmamap, 0, dmamap->dm_mapsize, 586 BUS_DMASYNC_PREWRITE); 587 588 /* Initialize the transmit descriptor(s). */ 589 txstart = sc->bce_txsnext; 590 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 591 uint32_t ctrl; 592 593 ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK; 594 if (seg == 0) 595 ctrl |= CTRL_SOF; 596 if (seg == dmamap->dm_nsegs - 1) 597 ctrl |= CTRL_EOF; 598 if (sc->bce_txsnext == BCE_NTXDESC - 1) 599 ctrl |= CTRL_EOT; 600 ctrl |= CTRL_IOC; 601 sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl); 602 sc->bce_tx_ring[sc->bce_txsnext].addr = 603 htole32(dmamap->dm_segs[seg].ds_addr + 0x40000000); /* MAGIC */ 604 if (sc->bce_txsnext + 1 > BCE_NTXDESC - 1) 605 sc->bce_txsnext = 0; 606 else 607 sc->bce_txsnext++; 608 txsfree--; 609 } 610 /* sync descriptors being used */ 611 if ( sc->bce_txsnext > txstart ) { 612 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 613 PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart, 614 sizeof(struct bce_dma_slot) * dmamap->dm_nsegs, 615 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 616 } else { 617 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 618 PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart, 619 sizeof(struct bce_dma_slot) * 620 (BCE_NTXDESC - txstart), 621 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 622 if ( sc->bce_txsnext != 0 ) { 623 bus_dmamap_sync(sc->bce_dmatag, 624 sc->bce_ring_map, PAGE_SIZE, 625 sc->bce_txsnext * 626 sizeof(struct bce_dma_slot), 627 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 628 } 629 } 630 631 /* Give the packet to the chip. */ 632 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_DPTR, 633 sc->bce_txsnext * sizeof(struct bce_dma_slot)); 634 635 newpkts++; 636 637 /* Pass the packet to any BPF listeners. */ 638 bpf_mtap(ifp, m0, BPF_D_OUT); 639 } 640 if (txsfree == 0) { 641 /* No more slots left; notify upper layer. */ 642 ifp->if_flags |= IFF_OACTIVE; 643 } 644 if (newpkts) { 645 /* Set a watchdog timer in case the chip flakes out. */ 646 ifp->if_timer = 5; 647 } 648 } 649 650 /* Watchdog timer handler. */ 651 static void 652 bce_watchdog(struct ifnet *ifp) 653 { 654 struct bce_softc *sc = ifp->if_softc; 655 656 aprint_error_dev(sc->bce_dev, "device timeout\n"); 657 ifp->if_oerrors++; 658 659 (void) bce_init(ifp); 660 661 /* Try to get more packets going. */ 662 bce_start(ifp); 663 } 664 665 int 666 bce_intr(void *xsc) 667 { 668 struct bce_softc *sc; 669 struct ifnet *ifp; 670 uint32_t intstatus; 671 int wantinit; 672 int handled = 0; 673 674 sc = xsc; 675 ifp = &sc->ethercom.ec_if; 676 677 for (wantinit = 0; wantinit == 0;) { 678 intstatus = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 679 BCE_INT_STS); 680 681 /* ignore if not ours, or unsolicited interrupts */ 682 intstatus &= sc->bce_intmask; 683 if (intstatus == 0) 684 break; 685 686 handled = 1; 687 688 /* Ack interrupt */ 689 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS, 690 intstatus); 691 692 /* Receive interrupts. */ 693 if (intstatus & I_RI) 694 bce_rxintr(sc); 695 /* Transmit interrupts. */ 696 if (intstatus & I_XI) 697 bce_txintr(sc); 698 /* Error interrupts */ 699 if (intstatus & ~(I_RI | I_XI)) { 700 const char *msg = NULL; 701 if (intstatus & I_XU) 702 msg = "transmit fifo underflow"; 703 if (intstatus & I_RO) { 704 msg = "receive fifo overflow"; 705 ifp->if_ierrors++; 706 } 707 if (intstatus & I_RU) 708 msg = "receive descriptor underflow"; 709 if (intstatus & I_DE) 710 msg = "descriptor protocol error"; 711 if (intstatus & I_PD) 712 msg = "data error"; 713 if (intstatus & I_PC) 714 msg = "descriptor error"; 715 if (intstatus & I_TO) 716 msg = "general purpose timeout"; 717 if (msg != NULL) 718 aprint_error_dev(sc->bce_dev, "%s\n", msg); 719 wantinit = 1; 720 } 721 } 722 723 if (handled) { 724 if (wantinit) 725 bce_init(ifp); 726 rnd_add_uint32(&sc->rnd_source, intstatus); 727 /* Try to get more packets going. */ 728 if_schedule_deferred_start(ifp); 729 } 730 return (handled); 731 } 732 733 /* Receive interrupt handler */ 734 void 735 bce_rxintr(struct bce_softc *sc) 736 { 737 struct ifnet *ifp = &sc->ethercom.ec_if; 738 struct rx_pph *pph; 739 struct mbuf *m; 740 int curr; 741 int len; 742 int i; 743 744 /* get pointer to active receive slot */ 745 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS) 746 & RS_CD_MASK; 747 curr = curr / sizeof(struct bce_dma_slot); 748 if (curr >= BCE_NRXDESC) 749 curr = BCE_NRXDESC - 1; 750 751 /* process packets up to but not current packet being worked on */ 752 for (i = sc->bce_rxin; i != curr; 753 i + 1 > BCE_NRXDESC - 1 ? i = 0 : i++) { 754 /* complete any post dma memory ops on packet */ 755 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i], 0, 756 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 757 BUS_DMASYNC_POSTREAD); 758 759 /* 760 * If the packet had an error, simply recycle the buffer, 761 * resetting the len, and flags. 762 */ 763 pph = mtod(sc->bce_cdata.bce_rx_chain[i], struct rx_pph *); 764 if (pph->flags & (RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)) { 765 ifp->if_ierrors++; 766 pph->len = 0; 767 pph->flags = 0; 768 continue; 769 } 770 /* receive the packet */ 771 len = pph->len; 772 if (len == 0) 773 continue; /* no packet if empty */ 774 pph->len = 0; 775 pph->flags = 0; 776 /* bump past pre header to packet */ 777 sc->bce_cdata.bce_rx_chain[i]->m_data += 30; /* MAGIC */ 778 779 /* 780 * The chip includes the CRC with every packet. Trim 781 * it off here. 782 */ 783 len -= ETHER_CRC_LEN; 784 785 /* 786 * If the packet is small enough to fit in a 787 * single header mbuf, allocate one and copy 788 * the data into it. This greatly reduces 789 * memory consumption when receiving lots 790 * of small packets. 791 * 792 * Otherwise, add a new buffer to the receive 793 * chain. If this fails, drop the packet and 794 * recycle the old buffer. 795 */ 796 if (len <= (MHLEN - 2)) { 797 MGETHDR(m, M_DONTWAIT, MT_DATA); 798 if (m == NULL) 799 goto dropit; 800 m->m_data += 2; 801 memcpy(mtod(m, void *), 802 mtod(sc->bce_cdata.bce_rx_chain[i], void *), len); 803 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; /* MAGIC */ 804 } else { 805 m = sc->bce_cdata.bce_rx_chain[i]; 806 if (bce_add_rxbuf(sc, i) != 0) { 807 dropit: 808 ifp->if_ierrors++; 809 /* continue to use old buffer */ 810 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; 811 bus_dmamap_sync(sc->bce_dmatag, 812 sc->bce_cdata.bce_rx_map[i], 0, 813 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 814 BUS_DMASYNC_PREREAD); 815 continue; 816 } 817 } 818 819 m_set_rcvif(m, ifp); 820 m->m_pkthdr.len = m->m_len = len; 821 822 /* Pass it on. */ 823 if_percpuq_enqueue(ifp->if_percpuq, m); 824 825 /* re-check current in case it changed */ 826 curr = (bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 827 BCE_DMA_RXSTATUS) & RS_CD_MASK) / 828 sizeof(struct bce_dma_slot); 829 if (curr >= BCE_NRXDESC) 830 curr = BCE_NRXDESC - 1; 831 } 832 sc->bce_rxin = curr; 833 } 834 835 /* Transmit interrupt handler */ 836 void 837 bce_txintr(struct bce_softc *sc) 838 { 839 struct ifnet *ifp = &sc->ethercom.ec_if; 840 int curr; 841 int i; 842 843 ifp->if_flags &= ~IFF_OACTIVE; 844 845 /* 846 * Go through the Tx list and free mbufs for those 847 * frames which have been transmitted. 848 */ 849 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXSTATUS) & 850 RS_CD_MASK; 851 curr = curr / sizeof(struct bce_dma_slot); 852 if (curr >= BCE_NTXDESC) 853 curr = BCE_NTXDESC - 1; 854 for (i = sc->bce_txin; i != curr; 855 i + 1 > BCE_NTXDESC - 1 ? i = 0 : i++) { 856 /* do any post dma memory ops on transmit data */ 857 if (sc->bce_cdata.bce_tx_chain[i] == NULL) 858 continue; 859 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i], 0, 860 sc->bce_cdata.bce_tx_map[i]->dm_mapsize, 861 BUS_DMASYNC_POSTWRITE); 862 bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i]); 863 m_freem(sc->bce_cdata.bce_tx_chain[i]); 864 sc->bce_cdata.bce_tx_chain[i] = NULL; 865 ifp->if_opackets++; 866 } 867 sc->bce_txin = curr; 868 869 /* 870 * If there are no more pending transmissions, cancel the watchdog 871 * timer 872 */ 873 if (sc->bce_txsnext == sc->bce_txin) 874 ifp->if_timer = 0; 875 } 876 877 /* initialize the interface */ 878 static int 879 bce_init(struct ifnet *ifp) 880 { 881 struct bce_softc *sc = ifp->if_softc; 882 uint32_t reg_win; 883 int error; 884 int i; 885 886 /* Cancel any pending I/O. */ 887 bce_stop(ifp, 0); 888 889 /* enable pci inerrupts, bursts, and prefetch */ 890 891 /* remap the pci registers to the Sonics config registers */ 892 893 /* save the current map, so it can be restored */ 894 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 895 BCE_REG_WIN); 896 897 /* set register window to Sonics registers */ 898 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 899 BCE_SONICS_WIN); 900 901 /* enable SB to PCI interrupt */ 902 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 903 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) | 904 SBIV_ENET0); 905 906 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 907 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 908 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) | 909 SBTOPCI_PREF | SBTOPCI_BURST); 910 911 /* restore to ethernet register space */ 912 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 913 reg_win); 914 915 /* Reset the chip to a known state. */ 916 bce_reset(sc); 917 918 /* Initialize transmit descriptors */ 919 memset(sc->bce_tx_ring, 0, BCE_NTXDESC * sizeof(struct bce_dma_slot)); 920 sc->bce_txsnext = 0; 921 sc->bce_txin = 0; 922 923 /* enable crc32 generation */ 924 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 925 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) | 926 BCE_EMC_CG); 927 928 /* setup DMA interrupt control */ 929 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1 << 24); /* MAGIC */ 930 931 /* setup packet filter */ 932 bce_set_filter(ifp); 933 934 /* set max frame length, account for possible vlan tag */ 935 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_MAX, 936 ETHER_MAX_LEN + 32); 937 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_MAX, 938 ETHER_MAX_LEN + 32); 939 940 /* set tx watermark */ 941 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_WATER, 56); 942 943 /* enable transmit */ 944 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, XC_XE); 945 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXADDR, 946 sc->bce_ring_map->dm_segs[0].ds_addr + PAGE_SIZE + 0x40000000); /* MAGIC */ 947 948 /* 949 * Give the receive ring to the chip, and 950 * start the receive DMA engine. 951 */ 952 sc->bce_rxin = 0; 953 954 /* clear the rx descriptor ring */ 955 memset(sc->bce_rx_ring, 0, BCE_NRXDESC * sizeof(struct bce_dma_slot)); 956 /* enable receive */ 957 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 958 30 << 1 | 1); /* MAGIC */ 959 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXADDR, 960 sc->bce_ring_map->dm_segs[0].ds_addr + 0x40000000); /* MAGIC */ 961 962 /* Initialize receive descriptors */ 963 for (i = 0; i < BCE_NRXDESC; i++) { 964 if (sc->bce_cdata.bce_rx_chain[i] == NULL) { 965 if ((error = bce_add_rxbuf(sc, i)) != 0) { 966 aprint_error_dev(sc->bce_dev, 967 "unable to allocate or map rx(%d) " 968 "mbuf, error = %d\n", i, error); 969 bce_rxdrain(sc); 970 return (error); 971 } 972 } else 973 BCE_INIT_RXDESC(sc, i); 974 } 975 976 /* Enable interrupts */ 977 sc->bce_intmask = 978 I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO; 979 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 980 sc->bce_intmask); 981 982 /* start the receive dma */ 983 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR, 984 BCE_NRXDESC * sizeof(struct bce_dma_slot)); 985 986 /* set media */ 987 if ((error = ether_mediachange(ifp)) != 0) 988 return error; 989 990 /* turn on the ethernet mac */ 991 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 992 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 993 BCE_ENET_CTL) | EC_EE); 994 995 /* start timer */ 996 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 997 998 /* mark as running, and no outputs active */ 999 ifp->if_flags |= IFF_RUNNING; 1000 ifp->if_flags &= ~IFF_OACTIVE; 1001 1002 return 0; 1003 } 1004 1005 /* add a mac address to packet filter */ 1006 void 1007 bce_add_mac(struct bce_softc *sc, uint8_t *mac, u_long idx) 1008 { 1009 int i; 1010 uint32_t rval; 1011 1012 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_LOW, 1013 (uint32_t)mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]); 1014 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_HI, 1015 mac[0] << 8 | mac[1] | 0x10000); /* MAGIC */ 1016 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1017 idx << 16 | 8); /* MAGIC */ 1018 /* wait for write to complete */ 1019 for (i = 0; i < 100; i++) { 1020 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1021 BCE_FILT_CTL); 1022 if (!(rval & 0x80000000)) /* MAGIC */ 1023 break; 1024 delay(10); 1025 } 1026 if (i == 100) { 1027 aprint_error_dev(sc->bce_dev, 1028 "timed out writing pkt filter ctl\n"); 1029 } 1030 } 1031 1032 /* Add a receive buffer to the indiciated descriptor. */ 1033 static int 1034 bce_add_rxbuf(struct bce_softc *sc, int idx) 1035 { 1036 struct mbuf *m; 1037 int error; 1038 1039 MGETHDR(m, M_DONTWAIT, MT_DATA); 1040 if (m == NULL) 1041 return (ENOBUFS); 1042 1043 MCLGET(m, M_DONTWAIT); 1044 if ((m->m_flags & M_EXT) == 0) { 1045 m_freem(m); 1046 return (ENOBUFS); 1047 } 1048 if (sc->bce_cdata.bce_rx_chain[idx] != NULL) 1049 bus_dmamap_unload(sc->bce_dmatag, 1050 sc->bce_cdata.bce_rx_map[idx]); 1051 1052 sc->bce_cdata.bce_rx_chain[idx] = m; 1053 1054 error = bus_dmamap_load(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 1055 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1056 BUS_DMA_READ | BUS_DMA_NOWAIT); 1057 if (error) 1058 return (error); 1059 1060 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 0, 1061 sc->bce_cdata.bce_rx_map[idx]->dm_mapsize, BUS_DMASYNC_PREREAD); 1062 1063 BCE_INIT_RXDESC(sc, idx); 1064 1065 return (0); 1066 1067 } 1068 1069 /* Drain the receive queue. */ 1070 static void 1071 bce_rxdrain(struct bce_softc *sc) 1072 { 1073 int i; 1074 1075 for (i = 0; i < BCE_NRXDESC; i++) { 1076 if (sc->bce_cdata.bce_rx_chain[i] != NULL) { 1077 bus_dmamap_unload(sc->bce_dmatag, 1078 sc->bce_cdata.bce_rx_map[i]); 1079 m_freem(sc->bce_cdata.bce_rx_chain[i]); 1080 sc->bce_cdata.bce_rx_chain[i] = NULL; 1081 } 1082 } 1083 } 1084 1085 /* Stop transmission on the interface */ 1086 static void 1087 bce_stop(struct ifnet *ifp, int disable) 1088 { 1089 struct bce_softc *sc = ifp->if_softc; 1090 int i; 1091 uint32_t val; 1092 1093 /* Stop the 1 second timer */ 1094 callout_stop(&sc->bce_timeout); 1095 1096 /* Down the MII. */ 1097 mii_down(&sc->bce_mii); 1098 1099 /* Disable interrupts. */ 1100 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0); 1101 sc->bce_intmask = 0; 1102 delay(10); 1103 1104 /* Disable emac */ 1105 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED); 1106 for (i = 0; i < 200; i++) { 1107 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1108 BCE_ENET_CTL); 1109 if (!(val & EC_ED)) 1110 break; 1111 delay(10); 1112 } 1113 1114 /* Stop the DMA */ 1115 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 0); 1116 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1117 delay(10); 1118 1119 /* Release any queued transmit buffers. */ 1120 for (i = 0; i < BCE_NTXDESC; i++) { 1121 if (sc->bce_cdata.bce_tx_chain[i] != NULL) { 1122 bus_dmamap_unload(sc->bce_dmatag, 1123 sc->bce_cdata.bce_tx_map[i]); 1124 m_freem(sc->bce_cdata.bce_tx_chain[i]); 1125 sc->bce_cdata.bce_tx_chain[i] = NULL; 1126 } 1127 } 1128 1129 /* Mark the interface down and cancel the watchdog timer. */ 1130 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1131 ifp->if_timer = 0; 1132 1133 /* drain receive queue */ 1134 if (disable) 1135 bce_rxdrain(sc); 1136 } 1137 1138 /* reset the chip */ 1139 static void 1140 bce_reset(struct bce_softc *sc) 1141 { 1142 uint32_t val; 1143 uint32_t sbval; 1144 int i; 1145 1146 /* if SB core is up */ 1147 sbval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1148 BCE_SBTMSTATELOW); 1149 if ((sbval & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK) { 1150 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1151 0); 1152 1153 /* disable emac */ 1154 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1155 EC_ED); 1156 for (i = 0; i < 200; i++) { 1157 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1158 BCE_ENET_CTL); 1159 if (!(val & EC_ED)) 1160 break; 1161 delay(10); 1162 } 1163 if (i == 200) { 1164 aprint_error_dev(sc->bce_dev, 1165 "timed out disabling ethernet mac\n"); 1166 } 1167 1168 /* reset the dma engines */ 1169 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1170 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS); 1171 /* if error on receive, wait to go idle */ 1172 if (val & RS_ERROR) { 1173 for (i = 0; i < 100; i++) { 1174 val = bus_space_read_4(sc->bce_btag, 1175 sc->bce_bhandle, BCE_DMA_RXSTATUS); 1176 if (val & RS_DMA_IDLE) 1177 break; 1178 delay(10); 1179 } 1180 if (i == 100) { 1181 aprint_error_dev(sc->bce_dev, 1182 "receive dma did not go idle after" 1183 " error\n"); 1184 } 1185 } 1186 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1187 BCE_DMA_RXSTATUS, 0); 1188 1189 /* reset ethernet mac */ 1190 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1191 EC_ES); 1192 for (i = 0; i < 200; i++) { 1193 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1194 BCE_ENET_CTL); 1195 if (!(val & EC_ES)) 1196 break; 1197 delay(10); 1198 } 1199 if (i == 200) { 1200 aprint_error_dev(sc->bce_dev, 1201 "timed out resetting ethernet mac\n"); 1202 } 1203 } else { 1204 uint32_t reg_win; 1205 1206 /* remap the pci registers to the Sonics config registers */ 1207 1208 /* save the current map, so it can be restored */ 1209 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1210 BCE_REG_WIN); 1211 /* set register window to Sonics registers */ 1212 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1213 BCE_REG_WIN, BCE_SONICS_WIN); 1214 1215 /* enable SB to PCI interrupt */ 1216 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 1217 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1218 BCE_SBINTVEC) | 1219 SBIV_ENET0); 1220 1221 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 1222 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 1223 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1224 BCE_SPCI_TR2) | 1225 SBTOPCI_PREF | SBTOPCI_BURST); 1226 1227 /* restore to ethernet register space */ 1228 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 1229 reg_win); 1230 } 1231 1232 /* disable SB core if not in reset */ 1233 if (!(sbval & SBTML_RESET)) { 1234 1235 /* set the reject bit */ 1236 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1237 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_CLK); 1238 for (i = 0; i < 200; i++) { 1239 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1240 BCE_SBTMSTATELOW); 1241 if (val & SBTML_REJ) 1242 break; 1243 delay(1); 1244 } 1245 if (i == 200) { 1246 aprint_error_dev(sc->bce_dev, 1247 "while resetting core, reject did not set\n"); 1248 } 1249 /* wait until busy is clear */ 1250 for (i = 0; i < 200; i++) { 1251 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1252 BCE_SBTMSTATEHI); 1253 if (!(val & 0x4)) 1254 break; 1255 delay(1); 1256 } 1257 if (i == 200) { 1258 aprint_error_dev(sc->bce_dev, 1259 "while resetting core, busy did not clear\n"); 1260 } 1261 /* set reset and reject while enabling the clocks */ 1262 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1263 BCE_SBTMSTATELOW, 1264 SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET); 1265 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1266 BCE_SBTMSTATELOW); 1267 delay(10); 1268 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1269 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_RESET); 1270 delay(1); 1271 } 1272 /* enable clock */ 1273 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1274 SBTML_FGC | SBTML_CLK | SBTML_RESET); 1275 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1276 delay(1); 1277 1278 /* clear any error bits that may be on */ 1279 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI); 1280 if (val & 1) 1281 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI, 1282 0); 1283 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE); 1284 if (val & SBIM_MAGIC_ERRORBITS) 1285 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE, 1286 val & ~SBIM_MAGIC_ERRORBITS); 1287 1288 /* clear reset and allow it to propagate throughout the core */ 1289 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1290 SBTML_FGC | SBTML_CLK); 1291 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1292 delay(1); 1293 1294 /* leave clock enabled */ 1295 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1296 SBTML_CLK); 1297 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1298 delay(1); 1299 1300 /* initialize MDC preamble, frequency */ 1301 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_CTL, 0x8d); /* MAGIC */ 1302 1303 /* enable phy, differs for internal, and external */ 1304 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL); 1305 if (!(val & BCE_DC_IP)) { 1306 /* select external phy */ 1307 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_EP); 1308 } else if (val & BCE_DC_ER) { /* internal, clear reset bit if on */ 1309 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL, 1310 val & ~BCE_DC_ER); 1311 delay(100); 1312 } 1313 } 1314 1315 /* Set up the receive filter. */ 1316 void 1317 bce_set_filter(struct ifnet *ifp) 1318 { 1319 struct bce_softc *sc = ifp->if_softc; 1320 1321 if (ifp->if_flags & IFF_PROMISC) { 1322 ifp->if_flags |= IFF_ALLMULTI; 1323 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1324 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) 1325 | ERC_PE); 1326 } else { 1327 ifp->if_flags &= ~IFF_ALLMULTI; 1328 1329 /* turn off promiscuous */ 1330 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1331 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1332 BCE_RX_CTL) & ~ERC_PE); 1333 1334 /* enable/disable broadcast */ 1335 if (ifp->if_flags & IFF_BROADCAST) 1336 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1337 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1338 sc->bce_bhandle, BCE_RX_CTL) & ~ERC_DB); 1339 else 1340 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1341 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1342 sc->bce_bhandle, BCE_RX_CTL) | ERC_DB); 1343 1344 /* disable the filter */ 1345 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1346 0); 1347 1348 /* add our own address */ 1349 bce_add_mac(sc, sc->enaddr, 0); 1350 1351 /* for now accept all multicast */ 1352 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1353 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) | 1354 ERC_AM); 1355 ifp->if_flags |= IFF_ALLMULTI; 1356 1357 /* enable the filter */ 1358 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1359 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1360 BCE_FILT_CTL) | 1); 1361 } 1362 } 1363 1364 static bool 1365 bce_resume(device_t self, const pmf_qual_t *qual) 1366 { 1367 struct bce_softc *sc = device_private(self); 1368 1369 bce_reset(sc); 1370 1371 return true; 1372 } 1373 1374 /* Read a PHY register on the MII. */ 1375 int 1376 bce_mii_read(device_t self, int phy, int reg, uint16_t *val) 1377 { 1378 struct bce_softc *sc = device_private(self); 1379 int i; 1380 uint32_t data; 1381 1382 /* clear mii_int */ 1383 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR); 1384 1385 /* Read the PHY register */ 1386 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1387 (MII_COMMAND_READ << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1388 (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */ 1389 1390 for (i = 0; i < BCE_TIMEOUT; i++) { 1391 data = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1392 BCE_MI_STS); 1393 if (data & BCE_MIINTR) 1394 break; 1395 delay(10); 1396 } 1397 data = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1398 if (i == BCE_TIMEOUT) { 1399 aprint_error_dev(sc->bce_dev, 1400 "PHY read timed out reading phy %d, reg %d, val = " 1401 "0x%08x\n", phy, reg, data); 1402 return ETIMEDOUT; 1403 } 1404 *val = data & BCE_MICOMM_DATA; 1405 return 0; 1406 } 1407 1408 /* Write a PHY register on the MII */ 1409 int 1410 bce_mii_write(device_t self, int phy, int reg, uint16_t val) 1411 { 1412 struct bce_softc *sc = device_private(self); 1413 int i; 1414 uint32_t data; 1415 1416 /* clear mii_int */ 1417 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, 1418 BCE_MIINTR); 1419 1420 /* Write the PHY register */ 1421 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1422 (MII_COMMAND_WRITE << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1423 (MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) | /* MAGIC */ 1424 BCE_MIPHY(phy) | BCE_MIREG(reg)); 1425 1426 /* wait for write to complete */ 1427 for (i = 0; i < BCE_TIMEOUT; i++) { 1428 data = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1429 BCE_MI_STS); 1430 if (data & BCE_MIINTR) 1431 break; 1432 delay(10); 1433 } 1434 if (i == BCE_TIMEOUT) { 1435 aprint_error_dev(sc->bce_dev, 1436 "PHY timed out writing phy %d, reg %d, val = 0x%04hx\n", 1437 phy, reg, val); 1438 return ETIMEDOUT; 1439 } 1440 1441 return 0; 1442 } 1443 1444 /* sync hardware duplex mode to software state */ 1445 void 1446 bce_statchg(struct ifnet *ifp) 1447 { 1448 struct bce_softc *sc = ifp->if_softc; 1449 uint32_t reg; 1450 uint16_t phyval; 1451 1452 /* if needed, change register to match duplex mode */ 1453 reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL); 1454 if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD)) 1455 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1456 reg | EXC_FD); 1457 else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD) 1458 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1459 reg & ~EXC_FD); 1460 1461 /* 1462 * Enable activity led. 1463 * XXX This should be in a phy driver, but not currently. 1464 */ 1465 bce_mii_read(sc->bce_dev, 1, 26, &phyval); 1466 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 1467 phyval & 0x7fff); /* MAGIC */ 1468 /* enable traffic meter led mode */ 1469 bce_mii_read(sc->bce_dev, 1, 27, &phyval); 1470 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 1471 phyval | (1 << 6)); /* MAGIC */ 1472 } 1473 1474 /* One second timer, checks link status */ 1475 static void 1476 bce_tick(void *v) 1477 { 1478 struct bce_softc *sc = v; 1479 1480 /* Tick the MII. */ 1481 mii_tick(&sc->bce_mii); 1482 1483 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1484 } 1485
Indexes created Tue Sep 30 17:09:57 GMT 2025