if_bce.c revision 1.55
1 /* $NetBSD: if_bce.c,v 1.55 2019/10/18 23:06:57 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Clifford Wright. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Broadcom BCM440x 10/100 ethernet (broadcom.com) 32 * SiliconBackplane is technology from Sonics, Inc.(sonicsinc.com) 33 * 34 * Cliff Wright cliff (at) snipe444.org 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_bce.c,v 1.55 2019/10/18 23:06:57 msaitoh Exp $"); 39 40 #include "vlan.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/sockio.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/device.h> 50 #include <sys/socket.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #include <net/bpf.h> 58 #include <sys/rndsource.h> 59 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcidevs.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include <dev/pci/if_bcereg.h> 68 69 /* transmit buffer max frags allowed */ 70 #define BCE_NTXFRAGS 16 71 72 /* ring descriptor */ 73 struct bce_dma_slot { 74 uint32_t ctrl; 75 uint32_t addr; 76 }; 77 #define CTRL_BC_MASK 0x1fff /* buffer byte count */ 78 #define CTRL_EOT 0x10000000 /* end of descriptor table */ 79 #define CTRL_IOC 0x20000000 /* interrupt on completion */ 80 #define CTRL_EOF 0x40000000 /* end of frame */ 81 #define CTRL_SOF 0x80000000 /* start of frame */ 82 83 /* Packet status is returned in a pre-packet header */ 84 struct rx_pph { 85 uint16_t len; 86 uint16_t flags; 87 uint16_t pad[12]; 88 }; 89 90 /* packet status flags bits */ 91 #define RXF_NO 0x8 /* odd number of nibbles */ 92 #define RXF_RXER 0x4 /* receive symbol error */ 93 #define RXF_CRC 0x2 /* crc error */ 94 #define RXF_OV 0x1 /* fifo overflow */ 95 96 /* number of descriptors used in a ring */ 97 #define BCE_NRXDESC 128 98 #define BCE_NTXDESC 128 99 100 /* 101 * Mbuf pointers. We need these to keep track of the virtual addresses 102 * of our mbuf chains since we can only convert from physical to virtual, 103 * not the other way around. 104 */ 105 struct bce_chain_data { 106 struct mbuf *bce_tx_chain[BCE_NTXDESC]; 107 struct mbuf *bce_rx_chain[BCE_NRXDESC]; 108 bus_dmamap_t bce_tx_map[BCE_NTXDESC]; 109 bus_dmamap_t bce_rx_map[BCE_NRXDESC]; 110 }; 111 112 #define BCE_TIMEOUT 100 /* # 10us for mii read/write */ 113 114 struct bce_softc { 115 device_t bce_dev; 116 bus_space_tag_t bce_btag; 117 bus_space_handle_t bce_bhandle; 118 bus_dma_tag_t bce_dmatag; 119 struct ethercom ethercom; /* interface info */ 120 void *bce_intrhand; 121 struct pci_attach_args bce_pa; 122 struct mii_data bce_mii; 123 uint32_t bce_phy; /* eeprom indicated phy */ 124 struct ifmedia bce_ifmedia; /* media info *//* Check */ 125 uint8_t enaddr[ETHER_ADDR_LEN]; 126 struct bce_dma_slot *bce_rx_ring; /* receive ring */ 127 struct bce_dma_slot *bce_tx_ring; /* transmit ring */ 128 struct bce_chain_data bce_cdata; /* mbufs */ 129 bus_dmamap_t bce_ring_map; 130 uint32_t bce_intmask; /* current intr mask */ 131 uint32_t bce_rxin; /* last rx descriptor seen */ 132 uint32_t bce_txin; /* last tx descriptor seen */ 133 int bce_txsfree; /* no. tx slots available */ 134 int bce_txsnext; /* next available tx slot */ 135 callout_t bce_timeout; 136 krndsource_t rnd_source; 137 }; 138 139 /* for ring descriptors */ 140 #define BCE_RXBUF_LEN (MCLBYTES - 4) 141 #define BCE_INIT_RXDESC(sc, x) \ 142 do { \ 143 struct bce_dma_slot *__bced = &sc->bce_rx_ring[x]; \ 144 \ 145 *mtod(sc->bce_cdata.bce_rx_chain[x], uint32_t *) = 0; \ 146 __bced->addr = \ 147 htole32(sc->bce_cdata.bce_rx_map[x]->dm_segs[0].ds_addr \ 148 + 0x40000000); \ 149 if (x != (BCE_NRXDESC - 1)) \ 150 __bced->ctrl = htole32(BCE_RXBUF_LEN); \ 151 else \ 152 __bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT); \ 153 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, \ 154 sizeof(struct bce_dma_slot) * x, \ 155 sizeof(struct bce_dma_slot), \ 156 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 157 } while (/* CONSTCOND */ 0) 158 159 static int bce_probe(device_t, cfdata_t, void *); 160 static void bce_attach(device_t, device_t, void *); 161 static int bce_ioctl(struct ifnet *, u_long, void *); 162 static void bce_start(struct ifnet *); 163 static void bce_watchdog(struct ifnet *); 164 static int bce_intr(void *); 165 static void bce_rxintr(struct bce_softc *); 166 static void bce_txintr(struct bce_softc *); 167 static int bce_init(struct ifnet *); 168 static void bce_add_mac(struct bce_softc *, uint8_t *, unsigned long); 169 static int bce_add_rxbuf(struct bce_softc *, int); 170 static void bce_rxdrain(struct bce_softc *); 171 static void bce_stop(struct ifnet *, int); 172 static void bce_reset(struct bce_softc *); 173 static bool bce_resume(device_t, const pmf_qual_t *); 174 static void bce_set_filter(struct ifnet *); 175 static int bce_mii_read(device_t, int, int, uint16_t *); 176 static int bce_mii_write(device_t, int, int, uint16_t); 177 static void bce_statchg(struct ifnet *); 178 static void bce_tick(void *); 179 180 CFATTACH_DECL_NEW(bce, sizeof(struct bce_softc), 181 bce_probe, bce_attach, NULL, NULL); 182 183 static const struct bce_product { 184 pci_vendor_id_t bp_vendor; 185 pci_product_id_t bp_product; 186 const char *bp_name; 187 } bce_products[] = { 188 { 189 PCI_VENDOR_BROADCOM, 190 PCI_PRODUCT_BROADCOM_BCM4401, 191 "Broadcom BCM4401 10/100 Ethernet" 192 }, 193 { 194 PCI_VENDOR_BROADCOM, 195 PCI_PRODUCT_BROADCOM_BCM4401_B0, 196 "Broadcom BCM4401-B0 10/100 Ethernet" 197 }, 198 { 199 PCI_VENDOR_BROADCOM, 200 PCI_PRODUCT_BROADCOM_BCM4401_B1, 201 "Broadcom BCM4401-B1 10/100 Ethernet" 202 }, 203 { 204 205 0, 206 0, 207 NULL 208 }, 209 }; 210 211 static const struct bce_product * 212 bce_lookup(const struct pci_attach_args * pa) 213 { 214 const struct bce_product *bp; 215 216 for (bp = bce_products; bp->bp_name != NULL; bp++) { 217 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 218 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 219 return (bp); 220 } 221 222 return (NULL); 223 } 224 225 /* 226 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 227 * against drivers product list, and return its name if a match is found. 228 */ 229 static int 230 bce_probe(device_t parent, cfdata_t match, void *aux) 231 { 232 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 233 234 if (bce_lookup(pa) != NULL) 235 return (1); 236 237 return (0); 238 } 239 240 static void 241 bce_attach(device_t parent, device_t self, void *aux) 242 { 243 struct bce_softc *sc = device_private(self); 244 struct pci_attach_args *pa = aux; 245 const struct bce_product *bp; 246 pci_chipset_tag_t pc = pa->pa_pc; 247 pci_intr_handle_t ih; 248 const char *intrstr = NULL; 249 uint32_t command; 250 pcireg_t memtype, pmode; 251 bus_addr_t memaddr; 252 bus_size_t memsize; 253 void *kva; 254 bus_dma_segment_t seg; 255 int error, i, pmreg, rseg; 256 uint16_t phyval; 257 struct ifnet *ifp; 258 struct mii_data *mii = &sc->bce_mii; 259 char intrbuf[PCI_INTRSTR_LEN]; 260 261 sc->bce_dev = self; 262 263 bp = bce_lookup(pa); 264 KASSERT(bp != NULL); 265 266 sc->bce_pa = *pa; 267 268 /* BCM440x can only address 30 bits (1GB) */ 269 if (bus_dmatag_subregion(pa->pa_dmat, 0, (1 << 30), 270 &(sc->bce_dmatag), BUS_DMA_NOWAIT) != 0) { 271 aprint_error_dev(self, 272 "WARNING: failed to restrict dma range," 273 " falling back to parent bus dma range\n"); 274 sc->bce_dmatag = pa->pa_dmat; 275 } 276 277 aprint_naive(": Ethernet controller\n"); 278 aprint_normal(": %s\n", bp->bp_name); 279 280 /* 281 * Map control/status registers. 282 */ 283 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 284 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 285 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 286 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 287 288 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 289 aprint_error_dev(self, "failed to enable memory mapping!\n"); 290 return; 291 } 292 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BCE_PCI_BAR0); 293 switch (memtype) { 294 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 295 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 296 if (pci_mapreg_map(pa, BCE_PCI_BAR0, memtype, 0, &sc->bce_btag, 297 &sc->bce_bhandle, &memaddr, &memsize) == 0) 298 break; 299 /* FALLTHROUGH */ 300 default: 301 aprint_error_dev(self, "unable to find mem space\n"); 302 return; 303 } 304 305 /* Get it out of power save mode if needed. */ 306 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, NULL)) { 307 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) 308 & PCI_PMCSR_STATE_MASK; 309 if (pmode == PCI_PMCSR_STATE_D3) { 310 /* 311 * The card has lost all configuration data in 312 * this state, so punt. 313 */ 314 aprint_error_dev(self, 315 "unable to wake up from power state D3\n"); 316 return; 317 } 318 if (pmode != PCI_PMCSR_STATE_D0) { 319 aprint_normal_dev(self, 320 "waking up from power state D%d\n", pmode); 321 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 0); 322 } 323 } 324 if (pci_intr_map(pa, &ih)) { 325 aprint_error_dev(self, "couldn't map interrupt\n"); 326 return; 327 } 328 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 329 330 sc->bce_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, bce_intr, 331 sc, device_xname(self)); 332 333 if (sc->bce_intrhand == NULL) { 334 aprint_error_dev(self, "couldn't establish interrupt\n"); 335 if (intrstr != NULL) 336 aprint_error(" at %s", intrstr); 337 aprint_error("\n"); 338 return; 339 } 340 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 341 342 /* reset the chip */ 343 bce_reset(sc); 344 345 /* 346 * Allocate DMA-safe memory for ring descriptors. 347 * The receive, and transmit rings can not share the same 348 * 4k space, however both are allocated at once here. 349 */ 350 /* 351 * XXX PAGE_SIZE is wasteful; we only need 1KB + 1KB, but 352 * due to the limition above. ?? 353 */ 354 if ((error = bus_dmamem_alloc(sc->bce_dmatag, 355 2 * PAGE_SIZE, PAGE_SIZE, 2 * PAGE_SIZE, 356 &seg, 1, &rseg, BUS_DMA_NOWAIT))) { 357 aprint_error_dev(self, 358 "unable to alloc space for ring descriptors, error = %d\n", 359 error); 360 return; 361 } 362 /* map ring space to kernel */ 363 if ((error = bus_dmamem_map(sc->bce_dmatag, &seg, rseg, 364 2 * PAGE_SIZE, &kva, BUS_DMA_NOWAIT))) { 365 aprint_error_dev(self, 366 "unable to map DMA buffers, error = %d\n", error); 367 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 368 return; 369 } 370 /* create a dma map for the ring */ 371 if ((error = bus_dmamap_create(sc->bce_dmatag, 372 2 * PAGE_SIZE, 1, 2 * PAGE_SIZE, 0, BUS_DMA_NOWAIT, 373 &sc->bce_ring_map))) { 374 aprint_error_dev(self, 375 "unable to create ring DMA map, error = %d\n", error); 376 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 377 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 378 return; 379 } 380 /* connect the ring space to the dma map */ 381 if (bus_dmamap_load(sc->bce_dmatag, sc->bce_ring_map, kva, 382 2 * PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) { 383 bus_dmamap_destroy(sc->bce_dmatag, sc->bce_ring_map); 384 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 385 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 386 return; 387 } 388 /* save the ring space in softc */ 389 sc->bce_rx_ring = (struct bce_dma_slot *) kva; 390 sc->bce_tx_ring = (struct bce_dma_slot *) ((char *)kva + PAGE_SIZE); 391 392 /* Create the transmit buffer DMA maps. */ 393 for (i = 0; i < BCE_NTXDESC; i++) { 394 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 395 BCE_NTXFRAGS, MCLBYTES, 0, 0, &sc->bce_cdata.bce_tx_map[i])) != 0) { 396 aprint_error_dev(self, 397 "unable to create tx DMA map, error = %d\n", error); 398 } 399 sc->bce_cdata.bce_tx_chain[i] = NULL; 400 } 401 402 /* Create the receive buffer DMA maps. */ 403 for (i = 0; i < BCE_NRXDESC; i++) { 404 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 1, 405 MCLBYTES, 0, 0, &sc->bce_cdata.bce_rx_map[i])) != 0) { 406 aprint_error_dev(self, 407 "unable to create rx DMA map, error = %d\n", error); 408 } 409 sc->bce_cdata.bce_rx_chain[i] = NULL; 410 } 411 412 /* Set up ifnet structure */ 413 ifp = &sc->ethercom.ec_if; 414 strcpy(ifp->if_xname, device_xname(self)); 415 ifp->if_softc = sc; 416 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 417 ifp->if_ioctl = bce_ioctl; 418 ifp->if_start = bce_start; 419 ifp->if_watchdog = bce_watchdog; 420 ifp->if_init = bce_init; 421 ifp->if_stop = bce_stop; 422 IFQ_SET_READY(&ifp->if_snd); 423 424 /* Initialize our media structures and probe the MII. */ 425 426 mii->mii_ifp = ifp; 427 mii->mii_readreg = bce_mii_read; 428 mii->mii_writereg = bce_mii_write; 429 mii->mii_statchg = bce_statchg; 430 431 sc->ethercom.ec_mii = mii; 432 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 433 mii_attach(sc->bce_dev, mii, 0xffffffff, MII_PHY_ANY, 434 MII_OFFSET_ANY, MIIF_FORCEANEG|MIIF_DOPAUSE); 435 if (LIST_FIRST(&mii->mii_phys) == NULL) { 436 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 437 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 438 } else 439 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 440 /* get the phy */ 441 sc->bce_phy = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 442 BCE_MAGIC_PHY) & 0x1f; 443 /* 444 * Enable activity led. 445 * XXX This should be in a phy driver, but not currently. 446 */ 447 bce_mii_read(sc->bce_dev, 1, 26, &phyval); 448 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 449 phyval & 0x7fff); /* MAGIC */ 450 /* enable traffic meter led mode */ 451 bce_mii_read(sc->bce_dev, 1, 27, &phyval); 452 bce_mii_write(sc->bce_dev, 1, 27, /* MAGIC */ 453 phyval | (1 << 6)); /* MAGIC */ 454 455 /* Attach the interface */ 456 if_attach(ifp); 457 if_deferred_start_init(ifp, NULL); 458 sc->enaddr[0] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 459 BCE_MAGIC_ENET0); 460 sc->enaddr[1] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 461 BCE_MAGIC_ENET1); 462 sc->enaddr[2] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 463 BCE_MAGIC_ENET2); 464 sc->enaddr[3] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 465 BCE_MAGIC_ENET3); 466 sc->enaddr[4] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 467 BCE_MAGIC_ENET4); 468 sc->enaddr[5] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 469 BCE_MAGIC_ENET5); 470 aprint_normal_dev(self, "Ethernet address %s\n", 471 ether_sprintf(sc->enaddr)); 472 ether_ifattach(ifp, sc->enaddr); 473 rnd_attach_source(&sc->rnd_source, device_xname(self), 474 RND_TYPE_NET, RND_FLAG_DEFAULT); 475 callout_init(&sc->bce_timeout, 0); 476 477 if (pmf_device_register(self, NULL, bce_resume)) 478 pmf_class_network_register(self, ifp); 479 else 480 aprint_error_dev(self, "couldn't establish power handler\n"); 481 } 482 483 /* handle media, and ethernet requests */ 484 static int 485 bce_ioctl(struct ifnet *ifp, u_long cmd, void *data) 486 { 487 int s, error; 488 489 s = splnet(); 490 error = ether_ioctl(ifp, cmd, data); 491 if (error == ENETRESET) { 492 /* change multicast list */ 493 error = 0; 494 } 495 496 /* Try to get more packets going. */ 497 bce_start(ifp); 498 499 splx(s); 500 return error; 501 } 502 503 /* Start packet transmission on the interface. */ 504 static void 505 bce_start(struct ifnet *ifp) 506 { 507 struct bce_softc *sc = ifp->if_softc; 508 struct mbuf *m0; 509 bus_dmamap_t dmamap; 510 int txstart; 511 int txsfree; 512 int newpkts = 0; 513 int error; 514 515 /* 516 * do not start another if currently transmitting, and more 517 * descriptors(tx slots) are needed for next packet. 518 */ 519 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 520 return; 521 522 /* determine number of descriptors available */ 523 if (sc->bce_txsnext >= sc->bce_txin) 524 txsfree = BCE_NTXDESC - 1 + sc->bce_txin - sc->bce_txsnext; 525 else 526 txsfree = sc->bce_txin - sc->bce_txsnext - 1; 527 528 /* 529 * Loop through the send queue, setting up transmit descriptors 530 * until we drain the queue, or use up all available transmit 531 * descriptors. 532 */ 533 while (txsfree > 0) { 534 int seg; 535 536 /* Grab a packet off the queue. */ 537 IFQ_POLL(&ifp->if_snd, m0); 538 if (m0 == NULL) 539 break; 540 541 /* get the transmit slot dma map */ 542 dmamap = sc->bce_cdata.bce_tx_map[sc->bce_txsnext]; 543 544 /* 545 * Load the DMA map. If this fails, the packet either 546 * didn't fit in the alloted number of segments, or we 547 * were short on resources. If the packet will not fit, 548 * it will be dropped. If short on resources, it will 549 * be tried again later. 550 */ 551 error = bus_dmamap_load_mbuf(sc->bce_dmatag, dmamap, m0, 552 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 553 if (error == EFBIG) { 554 aprint_error_dev(sc->bce_dev, 555 "Tx packet consumes too many DMA segments, " 556 "dropping...\n"); 557 IFQ_DEQUEUE(&ifp->if_snd, m0); 558 m_freem(m0); 559 ifp->if_oerrors++; 560 continue; 561 } else if (error) { 562 /* short on resources, come back later */ 563 aprint_error_dev(sc->bce_dev, 564 "unable to load Tx buffer, error = %d\n", 565 error); 566 break; 567 } 568 /* If not enough descriptors available, try again later */ 569 if (dmamap->dm_nsegs > txsfree) { 570 ifp->if_flags |= IFF_OACTIVE; 571 bus_dmamap_unload(sc->bce_dmatag, dmamap); 572 break; 573 } 574 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 575 576 /* So take it off the queue */ 577 IFQ_DEQUEUE(&ifp->if_snd, m0); 578 579 /* save the pointer so it can be freed later */ 580 sc->bce_cdata.bce_tx_chain[sc->bce_txsnext] = m0; 581 582 /* Sync the data DMA map. */ 583 bus_dmamap_sync(sc->bce_dmatag, dmamap, 0, dmamap->dm_mapsize, 584 BUS_DMASYNC_PREWRITE); 585 586 /* Initialize the transmit descriptor(s). */ 587 txstart = sc->bce_txsnext; 588 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 589 uint32_t ctrl; 590 591 ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK; 592 if (seg == 0) 593 ctrl |= CTRL_SOF; 594 if (seg == dmamap->dm_nsegs - 1) 595 ctrl |= CTRL_EOF; 596 if (sc->bce_txsnext == BCE_NTXDESC - 1) 597 ctrl |= CTRL_EOT; 598 ctrl |= CTRL_IOC; 599 sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl); 600 sc->bce_tx_ring[sc->bce_txsnext].addr = 601 htole32(dmamap->dm_segs[seg].ds_addr + 0x40000000); /* MAGIC */ 602 if (sc->bce_txsnext + 1 > BCE_NTXDESC - 1) 603 sc->bce_txsnext = 0; 604 else 605 sc->bce_txsnext++; 606 txsfree--; 607 } 608 /* sync descriptors being used */ 609 if ( sc->bce_txsnext > txstart ) { 610 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 611 PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart, 612 sizeof(struct bce_dma_slot) * dmamap->dm_nsegs, 613 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 614 } else { 615 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 616 PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart, 617 sizeof(struct bce_dma_slot) * 618 (BCE_NTXDESC - txstart), 619 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 620 if ( sc->bce_txsnext != 0 ) { 621 bus_dmamap_sync(sc->bce_dmatag, 622 sc->bce_ring_map, PAGE_SIZE, 623 sc->bce_txsnext * 624 sizeof(struct bce_dma_slot), 625 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 626 } 627 } 628 629 /* Give the packet to the chip. */ 630 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_DPTR, 631 sc->bce_txsnext * sizeof(struct bce_dma_slot)); 632 633 newpkts++; 634 635 /* Pass the packet to any BPF listeners. */ 636 bpf_mtap(ifp, m0, BPF_D_OUT); 637 } 638 if (txsfree == 0) { 639 /* No more slots left; notify upper layer. */ 640 ifp->if_flags |= IFF_OACTIVE; 641 } 642 if (newpkts) { 643 /* Set a watchdog timer in case the chip flakes out. */ 644 ifp->if_timer = 5; 645 } 646 } 647 648 /* Watchdog timer handler. */ 649 static void 650 bce_watchdog(struct ifnet *ifp) 651 { 652 struct bce_softc *sc = ifp->if_softc; 653 654 device_printf(sc->bce_dev, "device timeout\n"); 655 ifp->if_oerrors++; 656 657 (void) bce_init(ifp); 658 659 /* Try to get more packets going. */ 660 bce_start(ifp); 661 } 662 663 int 664 bce_intr(void *xsc) 665 { 666 struct bce_softc *sc; 667 struct ifnet *ifp; 668 uint32_t intstatus; 669 int wantinit; 670 int handled = 0; 671 672 sc = xsc; 673 ifp = &sc->ethercom.ec_if; 674 675 for (wantinit = 0; wantinit == 0;) { 676 intstatus = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 677 BCE_INT_STS); 678 679 /* ignore if not ours, or unsolicited interrupts */ 680 intstatus &= sc->bce_intmask; 681 if (intstatus == 0) 682 break; 683 684 handled = 1; 685 686 /* Ack interrupt */ 687 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS, 688 intstatus); 689 690 /* Receive interrupts. */ 691 if (intstatus & I_RI) 692 bce_rxintr(sc); 693 /* Transmit interrupts. */ 694 if (intstatus & I_XI) 695 bce_txintr(sc); 696 /* Error interrupts */ 697 if (intstatus & ~(I_RI | I_XI)) { 698 const char *msg = NULL; 699 if (intstatus & I_XU) 700 msg = "transmit fifo underflow"; 701 if (intstatus & I_RO) { 702 msg = "receive fifo overflow"; 703 ifp->if_ierrors++; 704 } 705 if (intstatus & I_RU) 706 msg = "receive descriptor underflow"; 707 if (intstatus & I_DE) 708 msg = "descriptor protocol error"; 709 if (intstatus & I_PD) 710 msg = "data error"; 711 if (intstatus & I_PC) 712 msg = "descriptor error"; 713 if (intstatus & I_TO) 714 msg = "general purpose timeout"; 715 if (msg != NULL) 716 aprint_error_dev(sc->bce_dev, "%s\n", msg); 717 wantinit = 1; 718 } 719 } 720 721 if (handled) { 722 if (wantinit) 723 bce_init(ifp); 724 rnd_add_uint32(&sc->rnd_source, intstatus); 725 /* Try to get more packets going. */ 726 if_schedule_deferred_start(ifp); 727 } 728 return (handled); 729 } 730 731 /* Receive interrupt handler */ 732 void 733 bce_rxintr(struct bce_softc *sc) 734 { 735 struct ifnet *ifp = &sc->ethercom.ec_if; 736 struct rx_pph *pph; 737 struct mbuf *m; 738 int curr; 739 int len; 740 int i; 741 742 /* get pointer to active receive slot */ 743 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS) 744 & RS_CD_MASK; 745 curr = curr / sizeof(struct bce_dma_slot); 746 if (curr >= BCE_NRXDESC) 747 curr = BCE_NRXDESC - 1; 748 749 /* process packets up to but not current packet being worked on */ 750 for (i = sc->bce_rxin; i != curr; 751 i + 1 > BCE_NRXDESC - 1 ? i = 0 : i++) { 752 /* complete any post dma memory ops on packet */ 753 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i], 0, 754 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 755 BUS_DMASYNC_POSTREAD); 756 757 /* 758 * If the packet had an error, simply recycle the buffer, 759 * resetting the len, and flags. 760 */ 761 pph = mtod(sc->bce_cdata.bce_rx_chain[i], struct rx_pph *); 762 if (pph->flags & (RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)) { 763 ifp->if_ierrors++; 764 pph->len = 0; 765 pph->flags = 0; 766 continue; 767 } 768 /* receive the packet */ 769 len = pph->len; 770 if (len == 0) 771 continue; /* no packet if empty */ 772 pph->len = 0; 773 pph->flags = 0; 774 /* bump past pre header to packet */ 775 sc->bce_cdata.bce_rx_chain[i]->m_data += 30; /* MAGIC */ 776 777 /* 778 * The chip includes the CRC with every packet. Trim 779 * it off here. 780 */ 781 len -= ETHER_CRC_LEN; 782 783 /* 784 * If the packet is small enough to fit in a 785 * single header mbuf, allocate one and copy 786 * the data into it. This greatly reduces 787 * memory consumption when receiving lots 788 * of small packets. 789 * 790 * Otherwise, add a new buffer to the receive 791 * chain. If this fails, drop the packet and 792 * recycle the old buffer. 793 */ 794 if (len <= (MHLEN - 2)) { 795 MGETHDR(m, M_DONTWAIT, MT_DATA); 796 if (m == NULL) 797 goto dropit; 798 m->m_data += 2; 799 memcpy(mtod(m, void *), 800 mtod(sc->bce_cdata.bce_rx_chain[i], void *), len); 801 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; /* MAGIC */ 802 } else { 803 m = sc->bce_cdata.bce_rx_chain[i]; 804 if (bce_add_rxbuf(sc, i) != 0) { 805 dropit: 806 ifp->if_ierrors++; 807 /* continue to use old buffer */ 808 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; 809 bus_dmamap_sync(sc->bce_dmatag, 810 sc->bce_cdata.bce_rx_map[i], 0, 811 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 812 BUS_DMASYNC_PREREAD); 813 continue; 814 } 815 } 816 817 m_set_rcvif(m, ifp); 818 m->m_pkthdr.len = m->m_len = len; 819 820 /* Pass it on. */ 821 if_percpuq_enqueue(ifp->if_percpuq, m); 822 823 /* re-check current in case it changed */ 824 curr = (bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 825 BCE_DMA_RXSTATUS) & RS_CD_MASK) / 826 sizeof(struct bce_dma_slot); 827 if (curr >= BCE_NRXDESC) 828 curr = BCE_NRXDESC - 1; 829 } 830 sc->bce_rxin = curr; 831 } 832 833 /* Transmit interrupt handler */ 834 void 835 bce_txintr(struct bce_softc *sc) 836 { 837 struct ifnet *ifp = &sc->ethercom.ec_if; 838 int curr; 839 int i; 840 841 ifp->if_flags &= ~IFF_OACTIVE; 842 843 /* 844 * Go through the Tx list and free mbufs for those 845 * frames which have been transmitted. 846 */ 847 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXSTATUS) & 848 RS_CD_MASK; 849 curr = curr / sizeof(struct bce_dma_slot); 850 if (curr >= BCE_NTXDESC) 851 curr = BCE_NTXDESC - 1; 852 for (i = sc->bce_txin; i != curr; 853 i + 1 > BCE_NTXDESC - 1 ? i = 0 : i++) { 854 /* do any post dma memory ops on transmit data */ 855 if (sc->bce_cdata.bce_tx_chain[i] == NULL) 856 continue; 857 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i], 0, 858 sc->bce_cdata.bce_tx_map[i]->dm_mapsize, 859 BUS_DMASYNC_POSTWRITE); 860 bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i]); 861 m_freem(sc->bce_cdata.bce_tx_chain[i]); 862 sc->bce_cdata.bce_tx_chain[i] = NULL; 863 ifp->if_opackets++; 864 } 865 sc->bce_txin = curr; 866 867 /* 868 * If there are no more pending transmissions, cancel the watchdog 869 * timer 870 */ 871 if (sc->bce_txsnext == sc->bce_txin) 872 ifp->if_timer = 0; 873 } 874 875 /* initialize the interface */ 876 static int 877 bce_init(struct ifnet *ifp) 878 { 879 struct bce_softc *sc = ifp->if_softc; 880 uint32_t reg_win; 881 int error; 882 int i; 883 884 /* Cancel any pending I/O. */ 885 bce_stop(ifp, 0); 886 887 /* enable pci inerrupts, bursts, and prefetch */ 888 889 /* remap the pci registers to the Sonics config registers */ 890 891 /* save the current map, so it can be restored */ 892 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 893 BCE_REG_WIN); 894 895 /* set register window to Sonics registers */ 896 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 897 BCE_SONICS_WIN); 898 899 /* enable SB to PCI interrupt */ 900 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 901 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) | 902 SBIV_ENET0); 903 904 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 905 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 906 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) | 907 SBTOPCI_PREF | SBTOPCI_BURST); 908 909 /* restore to ethernet register space */ 910 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 911 reg_win); 912 913 /* Reset the chip to a known state. */ 914 bce_reset(sc); 915 916 /* Initialize transmit descriptors */ 917 memset(sc->bce_tx_ring, 0, BCE_NTXDESC * sizeof(struct bce_dma_slot)); 918 sc->bce_txsnext = 0; 919 sc->bce_txin = 0; 920 921 /* enable crc32 generation */ 922 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 923 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) | 924 BCE_EMC_CG); 925 926 /* setup DMA interrupt control */ 927 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1 << 24); /* MAGIC */ 928 929 /* setup packet filter */ 930 bce_set_filter(ifp); 931 932 /* set max frame length, account for possible vlan tag */ 933 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_MAX, 934 ETHER_MAX_LEN + 32); 935 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_MAX, 936 ETHER_MAX_LEN + 32); 937 938 /* set tx watermark */ 939 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_WATER, 56); 940 941 /* enable transmit */ 942 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, XC_XE); 943 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXADDR, 944 sc->bce_ring_map->dm_segs[0].ds_addr + PAGE_SIZE + 0x40000000); /* MAGIC */ 945 946 /* 947 * Give the receive ring to the chip, and 948 * start the receive DMA engine. 949 */ 950 sc->bce_rxin = 0; 951 952 /* clear the rx descriptor ring */ 953 memset(sc->bce_rx_ring, 0, BCE_NRXDESC * sizeof(struct bce_dma_slot)); 954 /* enable receive */ 955 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 956 30 << 1 | 1); /* MAGIC */ 957 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXADDR, 958 sc->bce_ring_map->dm_segs[0].ds_addr + 0x40000000); /* MAGIC */ 959 960 /* Initialize receive descriptors */ 961 for (i = 0; i < BCE_NRXDESC; i++) { 962 if (sc->bce_cdata.bce_rx_chain[i] == NULL) { 963 if ((error = bce_add_rxbuf(sc, i)) != 0) { 964 aprint_error_dev(sc->bce_dev, 965 "unable to allocate or map rx(%d) " 966 "mbuf, error = %d\n", i, error); 967 bce_rxdrain(sc); 968 return (error); 969 } 970 } else 971 BCE_INIT_RXDESC(sc, i); 972 } 973 974 /* Enable interrupts */ 975 sc->bce_intmask = 976 I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO; 977 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 978 sc->bce_intmask); 979 980 /* start the receive dma */ 981 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR, 982 BCE_NRXDESC * sizeof(struct bce_dma_slot)); 983 984 /* set media */ 985 if ((error = ether_mediachange(ifp)) != 0) 986 return error; 987 988 /* turn on the ethernet mac */ 989 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 990 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 991 BCE_ENET_CTL) | EC_EE); 992 993 /* start timer */ 994 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 995 996 /* mark as running, and no outputs active */ 997 ifp->if_flags |= IFF_RUNNING; 998 ifp->if_flags &= ~IFF_OACTIVE; 999 1000 return 0; 1001 } 1002 1003 /* add a mac address to packet filter */ 1004 void 1005 bce_add_mac(struct bce_softc *sc, uint8_t *mac, u_long idx) 1006 { 1007 int i; 1008 uint32_t rval; 1009 1010 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_LOW, 1011 (uint32_t)mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]); 1012 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_HI, 1013 mac[0] << 8 | mac[1] | 0x10000); /* MAGIC */ 1014 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1015 idx << 16 | 8); /* MAGIC */ 1016 /* wait for write to complete */ 1017 for (i = 0; i < 100; i++) { 1018 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1019 BCE_FILT_CTL); 1020 if (!(rval & 0x80000000)) /* MAGIC */ 1021 break; 1022 delay(10); 1023 } 1024 if (i == 100) { 1025 aprint_error_dev(sc->bce_dev, 1026 "timed out writing pkt filter ctl\n"); 1027 } 1028 } 1029 1030 /* Add a receive buffer to the indiciated descriptor. */ 1031 static int 1032 bce_add_rxbuf(struct bce_softc *sc, int idx) 1033 { 1034 struct mbuf *m; 1035 int error; 1036 1037 MGETHDR(m, M_DONTWAIT, MT_DATA); 1038 if (m == NULL) 1039 return (ENOBUFS); 1040 1041 MCLGET(m, M_DONTWAIT); 1042 if ((m->m_flags & M_EXT) == 0) { 1043 m_freem(m); 1044 return (ENOBUFS); 1045 } 1046 if (sc->bce_cdata.bce_rx_chain[idx] != NULL) 1047 bus_dmamap_unload(sc->bce_dmatag, 1048 sc->bce_cdata.bce_rx_map[idx]); 1049 1050 sc->bce_cdata.bce_rx_chain[idx] = m; 1051 1052 error = bus_dmamap_load(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 1053 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1054 BUS_DMA_READ | BUS_DMA_NOWAIT); 1055 if (error) 1056 return (error); 1057 1058 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 0, 1059 sc->bce_cdata.bce_rx_map[idx]->dm_mapsize, BUS_DMASYNC_PREREAD); 1060 1061 BCE_INIT_RXDESC(sc, idx); 1062 1063 return (0); 1064 1065 } 1066 1067 /* Drain the receive queue. */ 1068 static void 1069 bce_rxdrain(struct bce_softc *sc) 1070 { 1071 int i; 1072 1073 for (i = 0; i < BCE_NRXDESC; i++) { 1074 if (sc->bce_cdata.bce_rx_chain[i] != NULL) { 1075 bus_dmamap_unload(sc->bce_dmatag, 1076 sc->bce_cdata.bce_rx_map[i]); 1077 m_freem(sc->bce_cdata.bce_rx_chain[i]); 1078 sc->bce_cdata.bce_rx_chain[i] = NULL; 1079 } 1080 } 1081 } 1082 1083 /* Stop transmission on the interface */ 1084 static void 1085 bce_stop(struct ifnet *ifp, int disable) 1086 { 1087 struct bce_softc *sc = ifp->if_softc; 1088 int i; 1089 uint32_t val; 1090 1091 /* Stop the 1 second timer */ 1092 callout_stop(&sc->bce_timeout); 1093 1094 /* Down the MII. */ 1095 mii_down(&sc->bce_mii); 1096 1097 /* Disable interrupts. */ 1098 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0); 1099 sc->bce_intmask = 0; 1100 delay(10); 1101 1102 /* Disable emac */ 1103 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED); 1104 for (i = 0; i < 200; i++) { 1105 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1106 BCE_ENET_CTL); 1107 if (!(val & EC_ED)) 1108 break; 1109 delay(10); 1110 } 1111 1112 /* Stop the DMA */ 1113 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 0); 1114 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1115 delay(10); 1116 1117 /* Release any queued transmit buffers. */ 1118 for (i = 0; i < BCE_NTXDESC; i++) { 1119 if (sc->bce_cdata.bce_tx_chain[i] != NULL) { 1120 bus_dmamap_unload(sc->bce_dmatag, 1121 sc->bce_cdata.bce_tx_map[i]); 1122 m_freem(sc->bce_cdata.bce_tx_chain[i]); 1123 sc->bce_cdata.bce_tx_chain[i] = NULL; 1124 } 1125 } 1126 1127 /* Mark the interface down and cancel the watchdog timer. */ 1128 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1129 ifp->if_timer = 0; 1130 1131 /* drain receive queue */ 1132 if (disable) 1133 bce_rxdrain(sc); 1134 } 1135 1136 /* reset the chip */ 1137 static void 1138 bce_reset(struct bce_softc *sc) 1139 { 1140 uint32_t val; 1141 uint32_t sbval; 1142 int i; 1143 1144 /* if SB core is up */ 1145 sbval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1146 BCE_SBTMSTATELOW); 1147 if ((sbval & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK) { 1148 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1149 0); 1150 1151 /* disable emac */ 1152 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1153 EC_ED); 1154 for (i = 0; i < 200; i++) { 1155 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1156 BCE_ENET_CTL); 1157 if (!(val & EC_ED)) 1158 break; 1159 delay(10); 1160 } 1161 if (i == 200) { 1162 aprint_error_dev(sc->bce_dev, 1163 "timed out disabling ethernet mac\n"); 1164 } 1165 1166 /* reset the dma engines */ 1167 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1168 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS); 1169 /* if error on receive, wait to go idle */ 1170 if (val & RS_ERROR) { 1171 for (i = 0; i < 100; i++) { 1172 val = bus_space_read_4(sc->bce_btag, 1173 sc->bce_bhandle, BCE_DMA_RXSTATUS); 1174 if (val & RS_DMA_IDLE) 1175 break; 1176 delay(10); 1177 } 1178 if (i == 100) { 1179 aprint_error_dev(sc->bce_dev, 1180 "receive dma did not go idle after" 1181 " error\n"); 1182 } 1183 } 1184 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1185 BCE_DMA_RXSTATUS, 0); 1186 1187 /* reset ethernet mac */ 1188 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1189 EC_ES); 1190 for (i = 0; i < 200; i++) { 1191 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1192 BCE_ENET_CTL); 1193 if (!(val & EC_ES)) 1194 break; 1195 delay(10); 1196 } 1197 if (i == 200) { 1198 aprint_error_dev(sc->bce_dev, 1199 "timed out resetting ethernet mac\n"); 1200 } 1201 } else { 1202 uint32_t reg_win; 1203 1204 /* remap the pci registers to the Sonics config registers */ 1205 1206 /* save the current map, so it can be restored */ 1207 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1208 BCE_REG_WIN); 1209 /* set register window to Sonics registers */ 1210 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1211 BCE_REG_WIN, BCE_SONICS_WIN); 1212 1213 /* enable SB to PCI interrupt */ 1214 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 1215 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1216 BCE_SBINTVEC) | 1217 SBIV_ENET0); 1218 1219 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 1220 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 1221 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1222 BCE_SPCI_TR2) | 1223 SBTOPCI_PREF | SBTOPCI_BURST); 1224 1225 /* restore to ethernet register space */ 1226 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 1227 reg_win); 1228 } 1229 1230 /* disable SB core if not in reset */ 1231 if (!(sbval & SBTML_RESET)) { 1232 1233 /* set the reject bit */ 1234 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1235 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_CLK); 1236 for (i = 0; i < 200; i++) { 1237 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1238 BCE_SBTMSTATELOW); 1239 if (val & SBTML_REJ) 1240 break; 1241 delay(1); 1242 } 1243 if (i == 200) { 1244 aprint_error_dev(sc->bce_dev, 1245 "while resetting core, reject did not set\n"); 1246 } 1247 /* wait until busy is clear */ 1248 for (i = 0; i < 200; i++) { 1249 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1250 BCE_SBTMSTATEHI); 1251 if (!(val & 0x4)) 1252 break; 1253 delay(1); 1254 } 1255 if (i == 200) { 1256 aprint_error_dev(sc->bce_dev, 1257 "while resetting core, busy did not clear\n"); 1258 } 1259 /* set reset and reject while enabling the clocks */ 1260 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1261 BCE_SBTMSTATELOW, 1262 SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET); 1263 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1264 BCE_SBTMSTATELOW); 1265 delay(10); 1266 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1267 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_RESET); 1268 delay(1); 1269 } 1270 /* enable clock */ 1271 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1272 SBTML_FGC | SBTML_CLK | SBTML_RESET); 1273 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1274 delay(1); 1275 1276 /* clear any error bits that may be on */ 1277 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI); 1278 if (val & 1) 1279 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI, 1280 0); 1281 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE); 1282 if (val & SBIM_MAGIC_ERRORBITS) 1283 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE, 1284 val & ~SBIM_MAGIC_ERRORBITS); 1285 1286 /* clear reset and allow it to propagate throughout the core */ 1287 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1288 SBTML_FGC | SBTML_CLK); 1289 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1290 delay(1); 1291 1292 /* leave clock enabled */ 1293 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1294 SBTML_CLK); 1295 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1296 delay(1); 1297 1298 /* initialize MDC preamble, frequency */ 1299 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_CTL, 0x8d); /* MAGIC */ 1300 1301 /* enable phy, differs for internal, and external */ 1302 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL); 1303 if (!(val & BCE_DC_IP)) { 1304 /* select external phy */ 1305 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_EP); 1306 } else if (val & BCE_DC_ER) { /* internal, clear reset bit if on */ 1307 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL, 1308 val & ~BCE_DC_ER); 1309 delay(100); 1310 } 1311 } 1312 1313 /* Set up the receive filter. */ 1314 void 1315 bce_set_filter(struct ifnet *ifp) 1316 { 1317 struct bce_softc *sc = ifp->if_softc; 1318 1319 if (ifp->if_flags & IFF_PROMISC) { 1320 ifp->if_flags |= IFF_ALLMULTI; 1321 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1322 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) 1323 | ERC_PE); 1324 } else { 1325 ifp->if_flags &= ~IFF_ALLMULTI; 1326 1327 /* turn off promiscuous */ 1328 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1329 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1330 BCE_RX_CTL) & ~ERC_PE); 1331 1332 /* enable/disable broadcast */ 1333 if (ifp->if_flags & IFF_BROADCAST) 1334 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1335 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1336 sc->bce_bhandle, BCE_RX_CTL) & ~ERC_DB); 1337 else 1338 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1339 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1340 sc->bce_bhandle, BCE_RX_CTL) | ERC_DB); 1341 1342 /* disable the filter */ 1343 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1344 0); 1345 1346 /* add our own address */ 1347 bce_add_mac(sc, sc->enaddr, 0); 1348 1349 /* for now accept all multicast */ 1350 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1351 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) | 1352 ERC_AM); 1353 ifp->if_flags |= IFF_ALLMULTI; 1354 1355 /* enable the filter */ 1356 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1357 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1358 BCE_FILT_CTL) | 1); 1359 } 1360 } 1361 1362 static bool 1363 bce_resume(device_t self, const pmf_qual_t *qual) 1364 { 1365 struct bce_softc *sc = device_private(self); 1366 1367 bce_reset(sc); 1368 1369 return true; 1370 } 1371 1372 /* Read a PHY register on the MII. */ 1373 int 1374 bce_mii_read(device_t self, int phy, int reg, uint16_t *val) 1375 { 1376 struct bce_softc *sc = device_private(self); 1377 int i; 1378 uint32_t data; 1379 1380 /* clear mii_int */ 1381 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR); 1382 1383 /* Read the PHY register */ 1384 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1385 (MII_COMMAND_READ << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1386 (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */ 1387 1388 for (i = 0; i < BCE_TIMEOUT; i++) { 1389 data = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1390 BCE_MI_STS); 1391 if (data & BCE_MIINTR) 1392 break; 1393 delay(10); 1394 } 1395 data = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1396 if (i == BCE_TIMEOUT) { 1397 aprint_error_dev(sc->bce_dev, 1398 "PHY read timed out reading phy %d, reg %d, val = " 1399 "0x%08x\n", phy, reg, data); 1400 return ETIMEDOUT; 1401 } 1402 *val = data & BCE_MICOMM_DATA; 1403 return 0; 1404 } 1405 1406 /* Write a PHY register on the MII */ 1407 int 1408 bce_mii_write(device_t self, int phy, int reg, uint16_t val) 1409 { 1410 struct bce_softc *sc = device_private(self); 1411 int i; 1412 uint32_t data; 1413 1414 /* clear mii_int */ 1415 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, 1416 BCE_MIINTR); 1417 1418 /* Write the PHY register */ 1419 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1420 (MII_COMMAND_WRITE << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1421 (MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) | /* MAGIC */ 1422 BCE_MIPHY(phy) | BCE_MIREG(reg)); 1423 1424 /* wait for write to complete */ 1425 for (i = 0; i < BCE_TIMEOUT; i++) { 1426 data = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1427 BCE_MI_STS); 1428 if (data & BCE_MIINTR) 1429 break; 1430 delay(10); 1431 } 1432 if (i == BCE_TIMEOUT) { 1433 aprint_error_dev(sc->bce_dev, 1434 "PHY timed out writing phy %d, reg %d, val = 0x%04hx\n", 1435 phy, reg, val); 1436 return ETIMEDOUT; 1437 } 1438 1439 return 0; 1440 } 1441 1442 /* sync hardware duplex mode to software state */ 1443 void 1444 bce_statchg(struct ifnet *ifp) 1445 { 1446 struct bce_softc *sc = ifp->if_softc; 1447 uint32_t reg; 1448 uint16_t phyval; 1449 1450 /* if needed, change register to match duplex mode */ 1451 reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL); 1452 if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD)) 1453 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1454 reg | EXC_FD); 1455 else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD) 1456 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1457 reg & ~EXC_FD); 1458 1459 /* 1460 * Enable activity led. 1461 * XXX This should be in a phy driver, but not currently. 1462 */ 1463 bce_mii_read(sc->bce_dev, 1, 26, &phyval); 1464 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 1465 phyval & 0x7fff); /* MAGIC */ 1466 /* enable traffic meter led mode */ 1467 bce_mii_read(sc->bce_dev, 1, 27, &phyval); 1468 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 1469 phyval | (1 << 6)); /* MAGIC */ 1470 } 1471 1472 /* One second timer, checks link status */ 1473 static void 1474 bce_tick(void *v) 1475 { 1476 struct bce_softc *sc = v; 1477 int s; 1478 1479 s = splnet(); 1480 mii_tick(&sc->bce_mii); 1481 splx(s); 1482 1483 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1484 } 1485
Indexes created Tue Sep 30 11:09:46 GMT 2025