if_bce.c revision 1.58
1 /* $NetBSD: if_bce.c,v 1.58 2020/02/07 00:04:28 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Clifford Wright. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Broadcom BCM440x 10/100 ethernet (broadcom.com) 32 * SiliconBackplane is technology from Sonics, Inc.(sonicsinc.com) 33 * 34 * Cliff Wright cliff (at) snipe444.org 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_bce.c,v 1.58 2020/02/07 00:04:28 thorpej Exp $"); 39 40 #include "vlan.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/sockio.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/device.h> 50 #include <sys/socket.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #include <net/bpf.h> 58 #include <sys/rndsource.h> 59 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcidevs.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include <dev/pci/if_bcereg.h> 68 69 /* transmit buffer max frags allowed */ 70 #define BCE_NTXFRAGS 16 71 72 /* ring descriptor */ 73 struct bce_dma_slot { 74 uint32_t ctrl; 75 uint32_t addr; 76 }; 77 #define CTRL_BC_MASK 0x1fff /* buffer byte count */ 78 #define CTRL_EOT 0x10000000 /* end of descriptor table */ 79 #define CTRL_IOC 0x20000000 /* interrupt on completion */ 80 #define CTRL_EOF 0x40000000 /* end of frame */ 81 #define CTRL_SOF 0x80000000 /* start of frame */ 82 83 /* Packet status is returned in a pre-packet header */ 84 struct rx_pph { 85 uint16_t len; 86 uint16_t flags; 87 uint16_t pad[12]; 88 }; 89 90 /* packet status flags bits */ 91 #define RXF_NO 0x8 /* odd number of nibbles */ 92 #define RXF_RXER 0x4 /* receive symbol error */ 93 #define RXF_CRC 0x2 /* crc error */ 94 #define RXF_OV 0x1 /* fifo overflow */ 95 96 /* number of descriptors used in a ring */ 97 #define BCE_NRXDESC 128 98 #define BCE_NTXDESC 128 99 100 /* 101 * Mbuf pointers. We need these to keep track of the virtual addresses 102 * of our mbuf chains since we can only convert from physical to virtual, 103 * not the other way around. 104 */ 105 struct bce_chain_data { 106 struct mbuf *bce_tx_chain[BCE_NTXDESC]; 107 struct mbuf *bce_rx_chain[BCE_NRXDESC]; 108 bus_dmamap_t bce_tx_map[BCE_NTXDESC]; 109 bus_dmamap_t bce_rx_map[BCE_NRXDESC]; 110 }; 111 112 #define BCE_TIMEOUT 100 /* # 10us for mii read/write */ 113 114 struct bce_softc { 115 device_t bce_dev; 116 bus_space_tag_t bce_btag; 117 bus_space_handle_t bce_bhandle; 118 bus_dma_tag_t bce_dmatag; 119 struct ethercom ethercom; /* interface info */ 120 void *bce_intrhand; 121 struct pci_attach_args bce_pa; 122 struct mii_data bce_mii; 123 uint32_t bce_phy; /* eeprom indicated phy */ 124 struct ifmedia bce_ifmedia; /* media info *//* Check */ 125 uint8_t enaddr[ETHER_ADDR_LEN]; 126 struct bce_dma_slot *bce_rx_ring; /* receive ring */ 127 struct bce_dma_slot *bce_tx_ring; /* transmit ring */ 128 struct bce_chain_data bce_cdata; /* mbufs */ 129 bus_dmamap_t bce_ring_map; 130 uint32_t bce_intmask; /* current intr mask */ 131 uint32_t bce_rxin; /* last rx descriptor seen */ 132 uint32_t bce_txin; /* last tx descriptor seen */ 133 int bce_txsfree; /* no. tx slots available */ 134 int bce_txsnext; /* next available tx slot */ 135 callout_t bce_timeout; 136 krndsource_t rnd_source; 137 }; 138 139 /* for ring descriptors */ 140 #define BCE_RXBUF_LEN (MCLBYTES - 4) 141 #define BCE_INIT_RXDESC(sc, x) \ 142 do { \ 143 struct bce_dma_slot *__bced = &sc->bce_rx_ring[x]; \ 144 \ 145 *mtod(sc->bce_cdata.bce_rx_chain[x], uint32_t *) = 0; \ 146 __bced->addr = \ 147 htole32(sc->bce_cdata.bce_rx_map[x]->dm_segs[0].ds_addr \ 148 + 0x40000000); \ 149 if (x != (BCE_NRXDESC - 1)) \ 150 __bced->ctrl = htole32(BCE_RXBUF_LEN); \ 151 else \ 152 __bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT); \ 153 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, \ 154 sizeof(struct bce_dma_slot) * x, \ 155 sizeof(struct bce_dma_slot), \ 156 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 157 } while (/* CONSTCOND */ 0) 158 159 static int bce_probe(device_t, cfdata_t, void *); 160 static void bce_attach(device_t, device_t, void *); 161 static int bce_ioctl(struct ifnet *, u_long, void *); 162 static void bce_start(struct ifnet *); 163 static void bce_watchdog(struct ifnet *); 164 static int bce_intr(void *); 165 static void bce_rxintr(struct bce_softc *); 166 static void bce_txintr(struct bce_softc *); 167 static int bce_init(struct ifnet *); 168 static void bce_add_mac(struct bce_softc *, uint8_t *, unsigned long); 169 static int bce_add_rxbuf(struct bce_softc *, int); 170 static void bce_rxdrain(struct bce_softc *); 171 static void bce_stop(struct ifnet *, int); 172 static void bce_reset(struct bce_softc *); 173 static bool bce_resume(device_t, const pmf_qual_t *); 174 static void bce_set_filter(struct ifnet *); 175 static int bce_mii_read(device_t, int, int, uint16_t *); 176 static int bce_mii_write(device_t, int, int, uint16_t); 177 static void bce_statchg(struct ifnet *); 178 static void bce_tick(void *); 179 180 CFATTACH_DECL_NEW(bce, sizeof(struct bce_softc), 181 bce_probe, bce_attach, NULL, NULL); 182 183 static const struct bce_product { 184 pci_vendor_id_t bp_vendor; 185 pci_product_id_t bp_product; 186 const char *bp_name; 187 } bce_products[] = { 188 { 189 PCI_VENDOR_BROADCOM, 190 PCI_PRODUCT_BROADCOM_BCM4401, 191 "Broadcom BCM4401 10/100 Ethernet" 192 }, 193 { 194 PCI_VENDOR_BROADCOM, 195 PCI_PRODUCT_BROADCOM_BCM4401_B0, 196 "Broadcom BCM4401-B0 10/100 Ethernet" 197 }, 198 { 199 PCI_VENDOR_BROADCOM, 200 PCI_PRODUCT_BROADCOM_BCM4401_B1, 201 "Broadcom BCM4401-B1 10/100 Ethernet" 202 }, 203 { 204 205 0, 206 0, 207 NULL 208 }, 209 }; 210 211 static const struct bce_product * 212 bce_lookup(const struct pci_attach_args * pa) 213 { 214 const struct bce_product *bp; 215 216 for (bp = bce_products; bp->bp_name != NULL; bp++) { 217 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 218 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 219 return (bp); 220 } 221 222 return (NULL); 223 } 224 225 /* 226 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 227 * against drivers product list, and return its name if a match is found. 228 */ 229 static int 230 bce_probe(device_t parent, cfdata_t match, void *aux) 231 { 232 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 233 234 if (bce_lookup(pa) != NULL) 235 return (1); 236 237 return (0); 238 } 239 240 static void 241 bce_attach(device_t parent, device_t self, void *aux) 242 { 243 struct bce_softc *sc = device_private(self); 244 struct pci_attach_args *pa = aux; 245 const struct bce_product *bp; 246 pci_chipset_tag_t pc = pa->pa_pc; 247 pci_intr_handle_t ih; 248 const char *intrstr = NULL; 249 uint32_t command; 250 pcireg_t memtype, pmode; 251 bus_addr_t memaddr; 252 bus_size_t memsize; 253 void *kva; 254 bus_dma_segment_t seg; 255 int error, i, pmreg, rseg; 256 uint16_t phyval; 257 struct ifnet *ifp; 258 struct mii_data *mii = &sc->bce_mii; 259 char intrbuf[PCI_INTRSTR_LEN]; 260 261 sc->bce_dev = self; 262 263 bp = bce_lookup(pa); 264 KASSERT(bp != NULL); 265 266 sc->bce_pa = *pa; 267 268 /* BCM440x can only address 30 bits (1GB) */ 269 if (bus_dmatag_subregion(pa->pa_dmat, 0, (1 << 30), 270 &(sc->bce_dmatag), BUS_DMA_NOWAIT) != 0) { 271 aprint_error_dev(self, 272 "WARNING: failed to restrict dma range," 273 " falling back to parent bus dma range\n"); 274 sc->bce_dmatag = pa->pa_dmat; 275 } 276 277 aprint_naive(": Ethernet controller\n"); 278 aprint_normal(": %s\n", bp->bp_name); 279 280 /* 281 * Map control/status registers. 282 */ 283 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 284 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 285 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 286 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 287 288 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 289 aprint_error_dev(self, "failed to enable memory mapping!\n"); 290 return; 291 } 292 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BCE_PCI_BAR0); 293 switch (memtype) { 294 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 295 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 296 if (pci_mapreg_map(pa, BCE_PCI_BAR0, memtype, 0, &sc->bce_btag, 297 &sc->bce_bhandle, &memaddr, &memsize) == 0) 298 break; 299 /* FALLTHROUGH */ 300 default: 301 aprint_error_dev(self, "unable to find mem space\n"); 302 return; 303 } 304 305 /* Get it out of power save mode if needed. */ 306 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, NULL)) { 307 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) 308 & PCI_PMCSR_STATE_MASK; 309 if (pmode == PCI_PMCSR_STATE_D3) { 310 /* 311 * The card has lost all configuration data in 312 * this state, so punt. 313 */ 314 aprint_error_dev(self, 315 "unable to wake up from power state D3\n"); 316 return; 317 } 318 if (pmode != PCI_PMCSR_STATE_D0) { 319 aprint_normal_dev(self, 320 "waking up from power state D%d\n", pmode); 321 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 0); 322 } 323 } 324 if (pci_intr_map(pa, &ih)) { 325 aprint_error_dev(self, "couldn't map interrupt\n"); 326 return; 327 } 328 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 329 330 sc->bce_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, bce_intr, 331 sc, device_xname(self)); 332 333 if (sc->bce_intrhand == NULL) { 334 aprint_error_dev(self, "couldn't establish interrupt\n"); 335 if (intrstr != NULL) 336 aprint_error(" at %s", intrstr); 337 aprint_error("\n"); 338 return; 339 } 340 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 341 342 /* reset the chip */ 343 bce_reset(sc); 344 345 /* 346 * Allocate DMA-safe memory for ring descriptors. 347 * The receive, and transmit rings can not share the same 348 * 4k space, however both are allocated at once here. 349 */ 350 /* 351 * XXX PAGE_SIZE is wasteful; we only need 1KB + 1KB, but 352 * due to the limition above. ?? 353 */ 354 if ((error = bus_dmamem_alloc(sc->bce_dmatag, 355 2 * PAGE_SIZE, PAGE_SIZE, 2 * PAGE_SIZE, 356 &seg, 1, &rseg, BUS_DMA_NOWAIT))) { 357 aprint_error_dev(self, 358 "unable to alloc space for ring descriptors, error = %d\n", 359 error); 360 return; 361 } 362 /* map ring space to kernel */ 363 if ((error = bus_dmamem_map(sc->bce_dmatag, &seg, rseg, 364 2 * PAGE_SIZE, &kva, BUS_DMA_NOWAIT))) { 365 aprint_error_dev(self, 366 "unable to map DMA buffers, error = %d\n", error); 367 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 368 return; 369 } 370 /* create a dma map for the ring */ 371 if ((error = bus_dmamap_create(sc->bce_dmatag, 372 2 * PAGE_SIZE, 1, 2 * PAGE_SIZE, 0, BUS_DMA_NOWAIT, 373 &sc->bce_ring_map))) { 374 aprint_error_dev(self, 375 "unable to create ring DMA map, error = %d\n", error); 376 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 377 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 378 return; 379 } 380 /* connect the ring space to the dma map */ 381 if (bus_dmamap_load(sc->bce_dmatag, sc->bce_ring_map, kva, 382 2 * PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) { 383 bus_dmamap_destroy(sc->bce_dmatag, sc->bce_ring_map); 384 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 385 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 386 return; 387 } 388 /* save the ring space in softc */ 389 sc->bce_rx_ring = (struct bce_dma_slot *) kva; 390 sc->bce_tx_ring = (struct bce_dma_slot *) ((char *)kva + PAGE_SIZE); 391 392 /* Create the transmit buffer DMA maps. */ 393 for (i = 0; i < BCE_NTXDESC; i++) { 394 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 395 BCE_NTXFRAGS, MCLBYTES, 0, 0, &sc->bce_cdata.bce_tx_map[i])) != 0) { 396 aprint_error_dev(self, 397 "unable to create tx DMA map, error = %d\n", error); 398 } 399 sc->bce_cdata.bce_tx_chain[i] = NULL; 400 } 401 402 /* Create the receive buffer DMA maps. */ 403 for (i = 0; i < BCE_NRXDESC; i++) { 404 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 1, 405 MCLBYTES, 0, 0, &sc->bce_cdata.bce_rx_map[i])) != 0) { 406 aprint_error_dev(self, 407 "unable to create rx DMA map, error = %d\n", error); 408 } 409 sc->bce_cdata.bce_rx_chain[i] = NULL; 410 } 411 412 /* Set up ifnet structure */ 413 ifp = &sc->ethercom.ec_if; 414 strcpy(ifp->if_xname, device_xname(self)); 415 ifp->if_softc = sc; 416 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 417 ifp->if_ioctl = bce_ioctl; 418 ifp->if_start = bce_start; 419 ifp->if_watchdog = bce_watchdog; 420 ifp->if_init = bce_init; 421 ifp->if_stop = bce_stop; 422 IFQ_SET_READY(&ifp->if_snd); 423 424 sc->ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 425 426 /* Initialize our media structures and probe the MII. */ 427 428 mii->mii_ifp = ifp; 429 mii->mii_readreg = bce_mii_read; 430 mii->mii_writereg = bce_mii_write; 431 mii->mii_statchg = bce_statchg; 432 433 sc->ethercom.ec_mii = mii; 434 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 435 mii_attach(sc->bce_dev, mii, 0xffffffff, MII_PHY_ANY, 436 MII_OFFSET_ANY, MIIF_FORCEANEG|MIIF_DOPAUSE); 437 if (LIST_FIRST(&mii->mii_phys) == NULL) { 438 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 439 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 440 } else 441 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 442 /* get the phy */ 443 sc->bce_phy = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 444 BCE_MAGIC_PHY) & 0x1f; 445 /* 446 * Enable activity led. 447 * XXX This should be in a phy driver, but not currently. 448 */ 449 bce_mii_read(sc->bce_dev, 1, 26, &phyval); 450 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 451 phyval & 0x7fff); /* MAGIC */ 452 /* enable traffic meter led mode */ 453 bce_mii_read(sc->bce_dev, 1, 27, &phyval); 454 bce_mii_write(sc->bce_dev, 1, 27, /* MAGIC */ 455 phyval | (1 << 6)); /* MAGIC */ 456 457 /* Attach the interface */ 458 if_attach(ifp); 459 if_deferred_start_init(ifp, NULL); 460 sc->enaddr[0] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 461 BCE_MAGIC_ENET0); 462 sc->enaddr[1] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 463 BCE_MAGIC_ENET1); 464 sc->enaddr[2] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 465 BCE_MAGIC_ENET2); 466 sc->enaddr[3] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 467 BCE_MAGIC_ENET3); 468 sc->enaddr[4] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 469 BCE_MAGIC_ENET4); 470 sc->enaddr[5] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 471 BCE_MAGIC_ENET5); 472 aprint_normal_dev(self, "Ethernet address %s\n", 473 ether_sprintf(sc->enaddr)); 474 ether_ifattach(ifp, sc->enaddr); 475 rnd_attach_source(&sc->rnd_source, device_xname(self), 476 RND_TYPE_NET, RND_FLAG_DEFAULT); 477 callout_init(&sc->bce_timeout, 0); 478 callout_setfunc(&sc->bce_timeout, bce_tick, sc); 479 480 if (pmf_device_register(self, NULL, bce_resume)) 481 pmf_class_network_register(self, ifp); 482 else 483 aprint_error_dev(self, "couldn't establish power handler\n"); 484 } 485 486 /* handle media, and ethernet requests */ 487 static int 488 bce_ioctl(struct ifnet *ifp, u_long cmd, void *data) 489 { 490 int s, error; 491 492 s = splnet(); 493 error = ether_ioctl(ifp, cmd, data); 494 if (error == ENETRESET) { 495 /* change multicast list */ 496 error = 0; 497 } 498 499 /* Try to get more packets going. */ 500 bce_start(ifp); 501 502 splx(s); 503 return error; 504 } 505 506 /* Start packet transmission on the interface. */ 507 static void 508 bce_start(struct ifnet *ifp) 509 { 510 struct bce_softc *sc = ifp->if_softc; 511 struct mbuf *m0; 512 bus_dmamap_t dmamap; 513 int txstart; 514 int txsfree; 515 int newpkts = 0; 516 int error; 517 518 /* 519 * do not start another if currently transmitting, and more 520 * descriptors(tx slots) are needed for next packet. 521 */ 522 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 523 return; 524 525 /* determine number of descriptors available */ 526 if (sc->bce_txsnext >= sc->bce_txin) 527 txsfree = BCE_NTXDESC - 1 + sc->bce_txin - sc->bce_txsnext; 528 else 529 txsfree = sc->bce_txin - sc->bce_txsnext - 1; 530 531 /* 532 * Loop through the send queue, setting up transmit descriptors 533 * until we drain the queue, or use up all available transmit 534 * descriptors. 535 */ 536 while (txsfree > 0) { 537 int seg; 538 539 /* Grab a packet off the queue. */ 540 IFQ_POLL(&ifp->if_snd, m0); 541 if (m0 == NULL) 542 break; 543 544 /* get the transmit slot dma map */ 545 dmamap = sc->bce_cdata.bce_tx_map[sc->bce_txsnext]; 546 547 /* 548 * Load the DMA map. If this fails, the packet either 549 * didn't fit in the alloted number of segments, or we 550 * were short on resources. If the packet will not fit, 551 * it will be dropped. If short on resources, it will 552 * be tried again later. 553 */ 554 error = bus_dmamap_load_mbuf(sc->bce_dmatag, dmamap, m0, 555 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 556 if (error == EFBIG) { 557 aprint_error_dev(sc->bce_dev, 558 "Tx packet consumes too many DMA segments, " 559 "dropping...\n"); 560 IFQ_DEQUEUE(&ifp->if_snd, m0); 561 m_freem(m0); 562 if_statinc(ifp, if_oerrors); 563 continue; 564 } else if (error) { 565 /* short on resources, come back later */ 566 aprint_error_dev(sc->bce_dev, 567 "unable to load Tx buffer, error = %d\n", 568 error); 569 break; 570 } 571 /* If not enough descriptors available, try again later */ 572 if (dmamap->dm_nsegs > txsfree) { 573 ifp->if_flags |= IFF_OACTIVE; 574 bus_dmamap_unload(sc->bce_dmatag, dmamap); 575 break; 576 } 577 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 578 579 /* So take it off the queue */ 580 IFQ_DEQUEUE(&ifp->if_snd, m0); 581 582 /* save the pointer so it can be freed later */ 583 sc->bce_cdata.bce_tx_chain[sc->bce_txsnext] = m0; 584 585 /* Sync the data DMA map. */ 586 bus_dmamap_sync(sc->bce_dmatag, dmamap, 0, dmamap->dm_mapsize, 587 BUS_DMASYNC_PREWRITE); 588 589 /* Initialize the transmit descriptor(s). */ 590 txstart = sc->bce_txsnext; 591 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 592 uint32_t ctrl; 593 594 ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK; 595 if (seg == 0) 596 ctrl |= CTRL_SOF; 597 if (seg == dmamap->dm_nsegs - 1) 598 ctrl |= CTRL_EOF; 599 if (sc->bce_txsnext == BCE_NTXDESC - 1) 600 ctrl |= CTRL_EOT; 601 ctrl |= CTRL_IOC; 602 sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl); 603 sc->bce_tx_ring[sc->bce_txsnext].addr = 604 htole32(dmamap->dm_segs[seg].ds_addr + 0x40000000); /* MAGIC */ 605 if (sc->bce_txsnext + 1 > BCE_NTXDESC - 1) 606 sc->bce_txsnext = 0; 607 else 608 sc->bce_txsnext++; 609 txsfree--; 610 } 611 /* sync descriptors being used */ 612 if ( sc->bce_txsnext > txstart ) { 613 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 614 PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart, 615 sizeof(struct bce_dma_slot) * dmamap->dm_nsegs, 616 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 617 } else { 618 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 619 PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart, 620 sizeof(struct bce_dma_slot) * 621 (BCE_NTXDESC - txstart), 622 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 623 if ( sc->bce_txsnext != 0 ) { 624 bus_dmamap_sync(sc->bce_dmatag, 625 sc->bce_ring_map, PAGE_SIZE, 626 sc->bce_txsnext * 627 sizeof(struct bce_dma_slot), 628 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 629 } 630 } 631 632 /* Give the packet to the chip. */ 633 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_DPTR, 634 sc->bce_txsnext * sizeof(struct bce_dma_slot)); 635 636 newpkts++; 637 638 /* Pass the packet to any BPF listeners. */ 639 bpf_mtap(ifp, m0, BPF_D_OUT); 640 } 641 if (txsfree == 0) { 642 /* No more slots left; notify upper layer. */ 643 ifp->if_flags |= IFF_OACTIVE; 644 } 645 if (newpkts) { 646 /* Set a watchdog timer in case the chip flakes out. */ 647 ifp->if_timer = 5; 648 } 649 } 650 651 /* Watchdog timer handler. */ 652 static void 653 bce_watchdog(struct ifnet *ifp) 654 { 655 struct bce_softc *sc = ifp->if_softc; 656 657 device_printf(sc->bce_dev, "device timeout\n"); 658 if_statinc(ifp, if_oerrors); 659 660 (void) bce_init(ifp); 661 662 /* Try to get more packets going. */ 663 bce_start(ifp); 664 } 665 666 int 667 bce_intr(void *xsc) 668 { 669 struct bce_softc *sc; 670 struct ifnet *ifp; 671 uint32_t intstatus; 672 int wantinit; 673 int handled = 0; 674 675 sc = xsc; 676 ifp = &sc->ethercom.ec_if; 677 678 for (wantinit = 0; wantinit == 0;) { 679 intstatus = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 680 BCE_INT_STS); 681 682 /* ignore if not ours, or unsolicited interrupts */ 683 intstatus &= sc->bce_intmask; 684 if (intstatus == 0) 685 break; 686 687 handled = 1; 688 689 /* Ack interrupt */ 690 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS, 691 intstatus); 692 693 /* Receive interrupts. */ 694 if (intstatus & I_RI) 695 bce_rxintr(sc); 696 /* Transmit interrupts. */ 697 if (intstatus & I_XI) 698 bce_txintr(sc); 699 /* Error interrupts */ 700 if (intstatus & ~(I_RI | I_XI)) { 701 const char *msg = NULL; 702 if (intstatus & I_XU) 703 msg = "transmit fifo underflow"; 704 if (intstatus & I_RO) { 705 msg = "receive fifo overflow"; 706 if_statinc(ifp, if_ierrors); 707 } 708 if (intstatus & I_RU) 709 msg = "receive descriptor underflow"; 710 if (intstatus & I_DE) 711 msg = "descriptor protocol error"; 712 if (intstatus & I_PD) 713 msg = "data error"; 714 if (intstatus & I_PC) 715 msg = "descriptor error"; 716 if (intstatus & I_TO) 717 msg = "general purpose timeout"; 718 if (msg != NULL) 719 aprint_error_dev(sc->bce_dev, "%s\n", msg); 720 wantinit = 1; 721 } 722 } 723 724 if (handled) { 725 if (wantinit) 726 bce_init(ifp); 727 rnd_add_uint32(&sc->rnd_source, intstatus); 728 /* Try to get more packets going. */ 729 if_schedule_deferred_start(ifp); 730 } 731 return (handled); 732 } 733 734 /* Receive interrupt handler */ 735 void 736 bce_rxintr(struct bce_softc *sc) 737 { 738 struct ifnet *ifp = &sc->ethercom.ec_if; 739 struct rx_pph *pph; 740 struct mbuf *m; 741 int curr; 742 int len; 743 int i; 744 745 /* get pointer to active receive slot */ 746 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS) 747 & RS_CD_MASK; 748 curr = curr / sizeof(struct bce_dma_slot); 749 if (curr >= BCE_NRXDESC) 750 curr = BCE_NRXDESC - 1; 751 752 /* process packets up to but not current packet being worked on */ 753 for (i = sc->bce_rxin; i != curr; 754 i + 1 > BCE_NRXDESC - 1 ? i = 0 : i++) { 755 /* complete any post dma memory ops on packet */ 756 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i], 0, 757 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 758 BUS_DMASYNC_POSTREAD); 759 760 /* 761 * If the packet had an error, simply recycle the buffer, 762 * resetting the len, and flags. 763 */ 764 pph = mtod(sc->bce_cdata.bce_rx_chain[i], struct rx_pph *); 765 if (pph->flags & (RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)) { 766 if_statinc(ifp, if_ierrors); 767 pph->len = 0; 768 pph->flags = 0; 769 continue; 770 } 771 /* receive the packet */ 772 len = pph->len; 773 if (len == 0) 774 continue; /* no packet if empty */ 775 pph->len = 0; 776 pph->flags = 0; 777 /* bump past pre header to packet */ 778 sc->bce_cdata.bce_rx_chain[i]->m_data += 30; /* MAGIC */ 779 780 /* 781 * The chip includes the CRC with every packet. Trim 782 * it off here. 783 */ 784 len -= ETHER_CRC_LEN; 785 786 /* 787 * If the packet is small enough to fit in a 788 * single header mbuf, allocate one and copy 789 * the data into it. This greatly reduces 790 * memory consumption when receiving lots 791 * of small packets. 792 * 793 * Otherwise, add a new buffer to the receive 794 * chain. If this fails, drop the packet and 795 * recycle the old buffer. 796 */ 797 if (len <= (MHLEN - 2)) { 798 MGETHDR(m, M_DONTWAIT, MT_DATA); 799 if (m == NULL) 800 goto dropit; 801 m->m_data += 2; 802 memcpy(mtod(m, void *), 803 mtod(sc->bce_cdata.bce_rx_chain[i], void *), len); 804 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; /* MAGIC */ 805 } else { 806 m = sc->bce_cdata.bce_rx_chain[i]; 807 if (bce_add_rxbuf(sc, i) != 0) { 808 dropit: 809 if_statinc(ifp, if_ierrors); 810 /* continue to use old buffer */ 811 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; 812 bus_dmamap_sync(sc->bce_dmatag, 813 sc->bce_cdata.bce_rx_map[i], 0, 814 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 815 BUS_DMASYNC_PREREAD); 816 continue; 817 } 818 } 819 820 m_set_rcvif(m, ifp); 821 m->m_pkthdr.len = m->m_len = len; 822 823 /* Pass it on. */ 824 if_percpuq_enqueue(ifp->if_percpuq, m); 825 826 /* re-check current in case it changed */ 827 curr = (bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 828 BCE_DMA_RXSTATUS) & RS_CD_MASK) / 829 sizeof(struct bce_dma_slot); 830 if (curr >= BCE_NRXDESC) 831 curr = BCE_NRXDESC - 1; 832 } 833 sc->bce_rxin = curr; 834 } 835 836 /* Transmit interrupt handler */ 837 void 838 bce_txintr(struct bce_softc *sc) 839 { 840 struct ifnet *ifp = &sc->ethercom.ec_if; 841 int curr; 842 int i; 843 844 ifp->if_flags &= ~IFF_OACTIVE; 845 846 /* 847 * Go through the Tx list and free mbufs for those 848 * frames which have been transmitted. 849 */ 850 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXSTATUS) & 851 RS_CD_MASK; 852 curr = curr / sizeof(struct bce_dma_slot); 853 if (curr >= BCE_NTXDESC) 854 curr = BCE_NTXDESC - 1; 855 for (i = sc->bce_txin; i != curr; 856 i + 1 > BCE_NTXDESC - 1 ? i = 0 : i++) { 857 /* do any post dma memory ops on transmit data */ 858 if (sc->bce_cdata.bce_tx_chain[i] == NULL) 859 continue; 860 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i], 0, 861 sc->bce_cdata.bce_tx_map[i]->dm_mapsize, 862 BUS_DMASYNC_POSTWRITE); 863 bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i]); 864 m_freem(sc->bce_cdata.bce_tx_chain[i]); 865 sc->bce_cdata.bce_tx_chain[i] = NULL; 866 if_statinc(ifp, if_opackets); 867 } 868 sc->bce_txin = curr; 869 870 /* 871 * If there are no more pending transmissions, cancel the watchdog 872 * timer 873 */ 874 if (sc->bce_txsnext == sc->bce_txin) 875 ifp->if_timer = 0; 876 } 877 878 /* initialize the interface */ 879 static int 880 bce_init(struct ifnet *ifp) 881 { 882 struct bce_softc *sc = ifp->if_softc; 883 uint32_t reg_win; 884 int error; 885 int i; 886 887 /* Cancel any pending I/O. */ 888 bce_stop(ifp, 0); 889 890 /* enable pci inerrupts, bursts, and prefetch */ 891 892 /* remap the pci registers to the Sonics config registers */ 893 894 /* save the current map, so it can be restored */ 895 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 896 BCE_REG_WIN); 897 898 /* set register window to Sonics registers */ 899 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 900 BCE_SONICS_WIN); 901 902 /* enable SB to PCI interrupt */ 903 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 904 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) | 905 SBIV_ENET0); 906 907 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 908 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 909 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) | 910 SBTOPCI_PREF | SBTOPCI_BURST); 911 912 /* restore to ethernet register space */ 913 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 914 reg_win); 915 916 /* Reset the chip to a known state. */ 917 bce_reset(sc); 918 919 /* Initialize transmit descriptors */ 920 memset(sc->bce_tx_ring, 0, BCE_NTXDESC * sizeof(struct bce_dma_slot)); 921 sc->bce_txsnext = 0; 922 sc->bce_txin = 0; 923 924 /* enable crc32 generation and set proper LED modes */ 925 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 926 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) | 927 BCE_EMC_CRC32_ENAB | BCE_EMC_LED); 928 929 /* reset or clear powerdown control bit */ 930 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 931 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) & 932 ~BCE_EMC_PDOWN); 933 934 /* setup DMA interrupt control */ 935 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1 << 24); /* MAGIC */ 936 937 /* setup packet filter */ 938 bce_set_filter(ifp); 939 940 /* set max frame length, account for possible vlan tag */ 941 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_MAX, 942 ETHER_MAX_LEN + 32); 943 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_MAX, 944 ETHER_MAX_LEN + 32); 945 946 /* set tx watermark */ 947 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_WATER, 56); 948 949 /* enable transmit */ 950 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, XC_XE); 951 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXADDR, 952 sc->bce_ring_map->dm_segs[0].ds_addr + PAGE_SIZE + 0x40000000); /* MAGIC */ 953 954 /* 955 * Give the receive ring to the chip, and 956 * start the receive DMA engine. 957 */ 958 sc->bce_rxin = 0; 959 960 /* clear the rx descriptor ring */ 961 memset(sc->bce_rx_ring, 0, BCE_NRXDESC * sizeof(struct bce_dma_slot)); 962 /* enable receive */ 963 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 964 30 << 1 | 1); /* MAGIC */ 965 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXADDR, 966 sc->bce_ring_map->dm_segs[0].ds_addr + 0x40000000); /* MAGIC */ 967 968 /* Initialize receive descriptors */ 969 for (i = 0; i < BCE_NRXDESC; i++) { 970 if (sc->bce_cdata.bce_rx_chain[i] == NULL) { 971 if ((error = bce_add_rxbuf(sc, i)) != 0) { 972 aprint_error_dev(sc->bce_dev, 973 "unable to allocate or map rx(%d) " 974 "mbuf, error = %d\n", i, error); 975 bce_rxdrain(sc); 976 return (error); 977 } 978 } else 979 BCE_INIT_RXDESC(sc, i); 980 } 981 982 /* Enable interrupts */ 983 sc->bce_intmask = 984 I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO; 985 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 986 sc->bce_intmask); 987 988 /* start the receive dma */ 989 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR, 990 BCE_NRXDESC * sizeof(struct bce_dma_slot)); 991 992 /* set media */ 993 if ((error = ether_mediachange(ifp)) != 0) 994 return error; 995 996 /* turn on the ethernet mac */ 997 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 998 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 999 BCE_ENET_CTL) | EC_EE); 1000 1001 /* start timer */ 1002 callout_schedule(&sc->bce_timeout, hz); 1003 1004 /* mark as running, and no outputs active */ 1005 ifp->if_flags |= IFF_RUNNING; 1006 ifp->if_flags &= ~IFF_OACTIVE; 1007 1008 return 0; 1009 } 1010 1011 /* add a mac address to packet filter */ 1012 void 1013 bce_add_mac(struct bce_softc *sc, uint8_t *mac, u_long idx) 1014 { 1015 int i; 1016 uint32_t rval; 1017 1018 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_LOW, 1019 (uint32_t)mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]); 1020 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_HI, 1021 mac[0] << 8 | mac[1] | 0x10000); /* MAGIC */ 1022 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1023 idx << 16 | 8); /* MAGIC */ 1024 /* wait for write to complete */ 1025 for (i = 0; i < 100; i++) { 1026 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1027 BCE_FILT_CTL); 1028 if (!(rval & 0x80000000)) /* MAGIC */ 1029 break; 1030 delay(10); 1031 } 1032 if (i == 100) { 1033 aprint_error_dev(sc->bce_dev, 1034 "timed out writing pkt filter ctl\n"); 1035 } 1036 } 1037 1038 /* Add a receive buffer to the indiciated descriptor. */ 1039 static int 1040 bce_add_rxbuf(struct bce_softc *sc, int idx) 1041 { 1042 struct mbuf *m; 1043 int error; 1044 1045 MGETHDR(m, M_DONTWAIT, MT_DATA); 1046 if (m == NULL) 1047 return (ENOBUFS); 1048 1049 MCLGET(m, M_DONTWAIT); 1050 if ((m->m_flags & M_EXT) == 0) { 1051 m_freem(m); 1052 return (ENOBUFS); 1053 } 1054 if (sc->bce_cdata.bce_rx_chain[idx] != NULL) 1055 bus_dmamap_unload(sc->bce_dmatag, 1056 sc->bce_cdata.bce_rx_map[idx]); 1057 1058 sc->bce_cdata.bce_rx_chain[idx] = m; 1059 1060 error = bus_dmamap_load(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 1061 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1062 BUS_DMA_READ | BUS_DMA_NOWAIT); 1063 if (error) 1064 return (error); 1065 1066 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 0, 1067 sc->bce_cdata.bce_rx_map[idx]->dm_mapsize, BUS_DMASYNC_PREREAD); 1068 1069 BCE_INIT_RXDESC(sc, idx); 1070 1071 return (0); 1072 1073 } 1074 1075 /* Drain the receive queue. */ 1076 static void 1077 bce_rxdrain(struct bce_softc *sc) 1078 { 1079 int i; 1080 1081 for (i = 0; i < BCE_NRXDESC; i++) { 1082 if (sc->bce_cdata.bce_rx_chain[i] != NULL) { 1083 bus_dmamap_unload(sc->bce_dmatag, 1084 sc->bce_cdata.bce_rx_map[i]); 1085 m_freem(sc->bce_cdata.bce_rx_chain[i]); 1086 sc->bce_cdata.bce_rx_chain[i] = NULL; 1087 } 1088 } 1089 } 1090 1091 /* Stop transmission on the interface */ 1092 static void 1093 bce_stop(struct ifnet *ifp, int disable) 1094 { 1095 struct bce_softc *sc = ifp->if_softc; 1096 int i; 1097 uint32_t val; 1098 1099 /* Stop the 1 second timer */ 1100 callout_stop(&sc->bce_timeout); 1101 1102 /* Down the MII. */ 1103 mii_down(&sc->bce_mii); 1104 1105 /* Disable interrupts. */ 1106 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0); 1107 sc->bce_intmask = 0; 1108 delay(10); 1109 1110 /* Disable emac */ 1111 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED); 1112 for (i = 0; i < 200; i++) { 1113 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1114 BCE_ENET_CTL); 1115 if (!(val & EC_ED)) 1116 break; 1117 delay(10); 1118 } 1119 1120 /* Stop the DMA */ 1121 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 0); 1122 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1123 delay(10); 1124 1125 /* Release any queued transmit buffers. */ 1126 for (i = 0; i < BCE_NTXDESC; i++) { 1127 if (sc->bce_cdata.bce_tx_chain[i] != NULL) { 1128 bus_dmamap_unload(sc->bce_dmatag, 1129 sc->bce_cdata.bce_tx_map[i]); 1130 m_freem(sc->bce_cdata.bce_tx_chain[i]); 1131 sc->bce_cdata.bce_tx_chain[i] = NULL; 1132 } 1133 } 1134 1135 /* Mark the interface down and cancel the watchdog timer. */ 1136 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1137 ifp->if_timer = 0; 1138 1139 /* drain receive queue */ 1140 if (disable) 1141 bce_rxdrain(sc); 1142 } 1143 1144 /* reset the chip */ 1145 static void 1146 bce_reset(struct bce_softc *sc) 1147 { 1148 uint32_t val; 1149 uint32_t sbval; 1150 int i; 1151 1152 /* if SB core is up */ 1153 sbval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1154 BCE_SBTMSTATELOW); 1155 if ((sbval & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK) { 1156 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1157 0); 1158 1159 /* disable emac */ 1160 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1161 EC_ED); 1162 for (i = 0; i < 200; i++) { 1163 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1164 BCE_ENET_CTL); 1165 if (!(val & EC_ED)) 1166 break; 1167 delay(10); 1168 } 1169 if (i == 200) { 1170 aprint_error_dev(sc->bce_dev, 1171 "timed out disabling ethernet mac\n"); 1172 } 1173 1174 /* reset the dma engines */ 1175 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1176 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS); 1177 /* if error on receive, wait to go idle */ 1178 if (val & RS_ERROR) { 1179 for (i = 0; i < 100; i++) { 1180 val = bus_space_read_4(sc->bce_btag, 1181 sc->bce_bhandle, BCE_DMA_RXSTATUS); 1182 if (val & RS_DMA_IDLE) 1183 break; 1184 delay(10); 1185 } 1186 if (i == 100) { 1187 aprint_error_dev(sc->bce_dev, 1188 "receive dma did not go idle after" 1189 " error\n"); 1190 } 1191 } 1192 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1193 BCE_DMA_RXSTATUS, 0); 1194 1195 /* reset ethernet mac */ 1196 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1197 EC_ES); 1198 for (i = 0; i < 200; i++) { 1199 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1200 BCE_ENET_CTL); 1201 if (!(val & EC_ES)) 1202 break; 1203 delay(10); 1204 } 1205 if (i == 200) { 1206 aprint_error_dev(sc->bce_dev, 1207 "timed out resetting ethernet mac\n"); 1208 } 1209 } else { 1210 uint32_t reg_win; 1211 1212 /* remap the pci registers to the Sonics config registers */ 1213 1214 /* save the current map, so it can be restored */ 1215 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1216 BCE_REG_WIN); 1217 /* set register window to Sonics registers */ 1218 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1219 BCE_REG_WIN, BCE_SONICS_WIN); 1220 1221 /* enable SB to PCI interrupt */ 1222 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 1223 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1224 BCE_SBINTVEC) | 1225 SBIV_ENET0); 1226 1227 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 1228 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 1229 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1230 BCE_SPCI_TR2) | 1231 SBTOPCI_PREF | SBTOPCI_BURST); 1232 1233 /* restore to ethernet register space */ 1234 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 1235 reg_win); 1236 } 1237 1238 /* disable SB core if not in reset */ 1239 if (!(sbval & SBTML_RESET)) { 1240 1241 /* set the reject bit */ 1242 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1243 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_CLK); 1244 for (i = 0; i < 200; i++) { 1245 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1246 BCE_SBTMSTATELOW); 1247 if (val & SBTML_REJ) 1248 break; 1249 delay(1); 1250 } 1251 if (i == 200) { 1252 aprint_error_dev(sc->bce_dev, 1253 "while resetting core, reject did not set\n"); 1254 } 1255 /* wait until busy is clear */ 1256 for (i = 0; i < 200; i++) { 1257 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1258 BCE_SBTMSTATEHI); 1259 if (!(val & 0x4)) 1260 break; 1261 delay(1); 1262 } 1263 if (i == 200) { 1264 aprint_error_dev(sc->bce_dev, 1265 "while resetting core, busy did not clear\n"); 1266 } 1267 /* set reset and reject while enabling the clocks */ 1268 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1269 BCE_SBTMSTATELOW, 1270 SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET); 1271 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1272 BCE_SBTMSTATELOW); 1273 delay(10); 1274 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1275 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_RESET); 1276 delay(1); 1277 } 1278 /* enable clock */ 1279 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1280 SBTML_FGC | SBTML_CLK | SBTML_RESET); 1281 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1282 delay(1); 1283 1284 /* clear any error bits that may be on */ 1285 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI); 1286 if (val & 1) 1287 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI, 1288 0); 1289 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE); 1290 if (val & SBIM_MAGIC_ERRORBITS) 1291 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE, 1292 val & ~SBIM_MAGIC_ERRORBITS); 1293 1294 /* clear reset and allow it to propagate throughout the core */ 1295 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1296 SBTML_FGC | SBTML_CLK); 1297 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1298 delay(1); 1299 1300 /* leave clock enabled */ 1301 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1302 SBTML_CLK); 1303 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1304 delay(1); 1305 1306 /* initialize MDC preamble, frequency */ 1307 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_CTL, 0x8d); /* MAGIC */ 1308 1309 /* enable phy, differs for internal, and external */ 1310 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL); 1311 if (!(val & BCE_DC_IP)) { 1312 /* select external phy */ 1313 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_EP); 1314 } else if (val & BCE_DC_ER) { /* internal, clear reset bit if on */ 1315 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL, 1316 val & ~BCE_DC_ER); 1317 delay(100); 1318 } 1319 } 1320 1321 /* Set up the receive filter. */ 1322 void 1323 bce_set_filter(struct ifnet *ifp) 1324 { 1325 struct bce_softc *sc = ifp->if_softc; 1326 1327 if (ifp->if_flags & IFF_PROMISC) { 1328 ifp->if_flags |= IFF_ALLMULTI; 1329 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1330 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) 1331 | ERC_PE); 1332 } else { 1333 ifp->if_flags &= ~IFF_ALLMULTI; 1334 1335 /* turn off promiscuous */ 1336 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1337 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1338 BCE_RX_CTL) & ~ERC_PE); 1339 1340 /* enable/disable broadcast */ 1341 if (ifp->if_flags & IFF_BROADCAST) 1342 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1343 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1344 sc->bce_bhandle, BCE_RX_CTL) & ~ERC_DB); 1345 else 1346 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1347 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1348 sc->bce_bhandle, BCE_RX_CTL) | ERC_DB); 1349 1350 /* disable the filter */ 1351 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1352 0); 1353 1354 /* add our own address */ 1355 bce_add_mac(sc, sc->enaddr, 0); 1356 1357 /* for now accept all multicast */ 1358 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1359 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) | 1360 ERC_AM); 1361 ifp->if_flags |= IFF_ALLMULTI; 1362 1363 /* enable the filter */ 1364 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1365 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1366 BCE_FILT_CTL) | 1); 1367 } 1368 } 1369 1370 static bool 1371 bce_resume(device_t self, const pmf_qual_t *qual) 1372 { 1373 struct bce_softc *sc = device_private(self); 1374 1375 bce_reset(sc); 1376 1377 return true; 1378 } 1379 1380 /* Read a PHY register on the MII. */ 1381 int 1382 bce_mii_read(device_t self, int phy, int reg, uint16_t *val) 1383 { 1384 struct bce_softc *sc = device_private(self); 1385 int i; 1386 uint32_t data; 1387 1388 /* clear mii_int */ 1389 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR); 1390 1391 /* Read the PHY register */ 1392 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1393 (MII_COMMAND_READ << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1394 (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */ 1395 1396 for (i = 0; i < BCE_TIMEOUT; i++) { 1397 data = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1398 BCE_MI_STS); 1399 if (data & BCE_MIINTR) 1400 break; 1401 delay(10); 1402 } 1403 data = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1404 if (i == BCE_TIMEOUT) { 1405 aprint_error_dev(sc->bce_dev, 1406 "PHY read timed out reading phy %d, reg %d, val = " 1407 "0x%08x\n", phy, reg, data); 1408 return ETIMEDOUT; 1409 } 1410 *val = data & BCE_MICOMM_DATA; 1411 return 0; 1412 } 1413 1414 /* Write a PHY register on the MII */ 1415 int 1416 bce_mii_write(device_t self, int phy, int reg, uint16_t val) 1417 { 1418 struct bce_softc *sc = device_private(self); 1419 int i; 1420 uint32_t data; 1421 1422 /* clear mii_int */ 1423 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, 1424 BCE_MIINTR); 1425 1426 /* Write the PHY register */ 1427 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1428 (MII_COMMAND_WRITE << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1429 (MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) | /* MAGIC */ 1430 BCE_MIPHY(phy) | BCE_MIREG(reg)); 1431 1432 /* wait for write to complete */ 1433 for (i = 0; i < BCE_TIMEOUT; i++) { 1434 data = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1435 BCE_MI_STS); 1436 if (data & BCE_MIINTR) 1437 break; 1438 delay(10); 1439 } 1440 if (i == BCE_TIMEOUT) { 1441 aprint_error_dev(sc->bce_dev, 1442 "PHY timed out writing phy %d, reg %d, val = 0x%04hx\n", 1443 phy, reg, val); 1444 return ETIMEDOUT; 1445 } 1446 1447 return 0; 1448 } 1449 1450 /* sync hardware duplex mode to software state */ 1451 void 1452 bce_statchg(struct ifnet *ifp) 1453 { 1454 struct bce_softc *sc = ifp->if_softc; 1455 uint32_t reg; 1456 uint16_t phyval; 1457 1458 /* if needed, change register to match duplex mode */ 1459 reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL); 1460 if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD)) 1461 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1462 reg | EXC_FD); 1463 else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD) 1464 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1465 reg & ~EXC_FD); 1466 1467 /* 1468 * Enable activity led. 1469 * XXX This should be in a phy driver, but not currently. 1470 */ 1471 bce_mii_read(sc->bce_dev, 1, 26, &phyval); 1472 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 1473 phyval & 0x7fff); /* MAGIC */ 1474 /* enable traffic meter led mode */ 1475 bce_mii_read(sc->bce_dev, 1, 27, &phyval); 1476 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 1477 phyval | (1 << 6)); /* MAGIC */ 1478 } 1479 1480 /* One second timer, checks link status */ 1481 static void 1482 bce_tick(void *v) 1483 { 1484 struct bce_softc *sc = v; 1485 int s; 1486 1487 s = splnet(); 1488 mii_tick(&sc->bce_mii); 1489 splx(s); 1490 1491 callout_schedule(&sc->bce_timeout, hz); 1492 } 1493
Indexes created Tue Sep 30 17:09:57 GMT 2025