if_bce.c revision 1.6
1 /* $NetBSD: if_bce.c,v 1.6 2004/08/21 23:48:33 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Clifford Wright. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Broadcom BCM440x 10/100 ethernet (broadcom.com) 32 * SiliconBackplane is technology from Sonics, Inc.(sonicsinc.com) 33 * 34 * Cliff Wright cliff (at) snipe444.org 35 */ 36 37 #include "bpfilter.h" 38 #include "vlan.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/callout.h> 43 #include <sys/sockio.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/device.h> 48 #include <sys/socket.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 #include <net/if_ether.h> 54 55 #if NBPFILTER > 0 56 #include <net/bpf.h> 57 #endif 58 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 #include <dev/mii/miidevs.h> 66 #include <dev/mii/brgphyreg.h> 67 68 #include <dev/pci/if_bcereg.h> 69 70 #include <uvm/uvm_extern.h> 71 72 /* transmit buffer max frags allowed */ 73 #define BCE_NTXFRAGS 16 74 75 /* ring descriptor */ 76 struct bce_dma_slot { 77 u_int32_t ctrl; 78 u_int32_t addr; 79 }; 80 #define CTRL_BC_MASK 0x1fff /* buffer byte count */ 81 #define CTRL_EOT 0x10000000 /* end of descriptor table */ 82 #define CTRL_IOC 0x20000000 /* interrupt on completion */ 83 #define CTRL_EOF 0x40000000 /* end of frame */ 84 #define CTRL_SOF 0x80000000 /* start of frame */ 85 86 /* Packet status is returned in a pre-packet header */ 87 struct rx_pph { 88 u_int16_t len; 89 u_int16_t flags; 90 u_int16_t pad[12]; 91 }; 92 93 /* packet status flags bits */ 94 #define RXF_NO 0x8 /* odd number of nibbles */ 95 #define RXF_RXER 0x4 /* receive symbol error */ 96 #define RXF_CRC 0x2 /* crc error */ 97 #define RXF_OV 0x1 /* fifo overflow */ 98 99 /* number of descriptors used in a ring */ 100 #define BCE_NRXDESC 128 101 #define BCE_NTXDESC 128 102 103 /* 104 * Mbuf pointers. We need these to keep track of the virtual addresses 105 * of our mbuf chains since we can only convert from physical to virtual, 106 * not the other way around. 107 */ 108 struct bce_chain_data { 109 struct mbuf *bce_tx_chain[BCE_NTXDESC]; 110 struct mbuf *bce_rx_chain[BCE_NRXDESC]; 111 bus_dmamap_t bce_tx_map[BCE_NTXDESC]; 112 bus_dmamap_t bce_rx_map[BCE_NRXDESC]; 113 }; 114 115 #define BCE_TIMEOUT 100 /* # 10us for mii read/write */ 116 117 struct bce_softc { 118 struct device bce_dev; 119 bus_space_tag_t bce_btag; 120 bus_space_handle_t bce_bhandle; 121 bus_dma_tag_t bce_dmatag; 122 struct ethercom ethercom; /* interface info */ 123 void *bce_intrhand; 124 struct pci_attach_args bce_pa; 125 struct mii_data bce_mii; 126 u_int32_t bce_phy; /* eeprom indicated phy */ 127 struct ifmedia bce_ifmedia; /* media info *//* Check */ 128 u_int8_t enaddr[ETHER_ADDR_LEN]; 129 struct bce_dma_slot *bce_rx_ring; /* receive ring */ 130 struct bce_dma_slot *bce_tx_ring; /* transmit ring */ 131 struct bce_chain_data bce_cdata; /* mbufs */ 132 bus_dmamap_t bce_ring_map; 133 u_int32_t bce_intmask; /* current intr mask */ 134 u_int32_t bce_rxin; /* last rx descriptor seen */ 135 u_int32_t bce_txin; /* last tx descriptor seen */ 136 int bce_txsfree; /* no. tx slots available */ 137 int bce_txsnext; /* next available tx slot */ 138 struct callout bce_timeout; 139 }; 140 141 /* for ring descriptors */ 142 #define BCE_RXBUF_LEN (MCLBYTES - 4) 143 #define BCE_INIT_RXDESC(sc, x) \ 144 do { \ 145 struct bce_dma_slot *__bced = &sc->bce_rx_ring[x]; \ 146 \ 147 *mtod(sc->bce_cdata.bce_rx_chain[x], u_int32_t *) = 0; \ 148 __bced->addr = \ 149 htole32(sc->bce_cdata.bce_rx_map[x]->dm_segs[0].ds_addr \ 150 + 0x40000000); \ 151 if (x != (BCE_NRXDESC - 1)) \ 152 __bced->ctrl = htole32(BCE_RXBUF_LEN); \ 153 else \ 154 __bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT); \ 155 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, \ 156 sizeof(struct bce_dma_slot) * x, \ 157 sizeof(struct bce_dma_slot), \ 158 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 159 } while (/* CONSTCOND */ 0) 160 161 static int bce_probe(struct device *, struct cfdata *, void *); 162 static void bce_attach(struct device *, struct device *, void *); 163 static int bce_ioctl(struct ifnet *, u_long, caddr_t); 164 static void bce_start(struct ifnet *); 165 static void bce_watchdog(struct ifnet *); 166 static int bce_intr(void *); 167 static void bce_rxintr(struct bce_softc *); 168 static void bce_txintr(struct bce_softc *); 169 static int bce_init(struct ifnet *); 170 static void bce_add_mac(struct bce_softc *, u_int8_t *, unsigned long); 171 static int bce_add_rxbuf(struct bce_softc *, int); 172 static void bce_rxdrain(struct bce_softc *); 173 static void bce_stop(struct ifnet *, int); 174 static void bce_reset(struct bce_softc *); 175 static void bce_set_filter(struct ifnet *); 176 static int bce_mii_read(struct device *, int, int); 177 static void bce_mii_write(struct device *, int, int, int); 178 static void bce_statchg(struct device *); 179 static int bce_mediachange(struct ifnet *); 180 static void bce_mediastatus(struct ifnet *, struct ifmediareq *); 181 static void bce_tick(void *); 182 183 #define BCE_DEBUG 184 #ifdef BCE_DEBUG 185 #define DPRINTF(x) do { \ 186 if (bcedebug) \ 187 printf x; \ 188 } while (/* CONSTCOND */ 0) 189 #define DPRINTFN(n,x) do { \ 190 if (bcedebug >= (n)) \ 191 printf x; \ 192 } while (/* CONSTCOND */ 0) 193 int bcedebug = 0; 194 #else 195 #define DPRINTF(x) 196 #define DPRINTFN(n,x) 197 #endif 198 199 #if __NetBSD_Version__ >= 106080000 200 CFATTACH_DECL(bce, sizeof(struct bce_softc), 201 bce_probe, bce_attach, NULL, NULL); 202 #else 203 struct cfattach bce_ca = { 204 sizeof(struct bce_softc), bce_probe, bce_attach 205 }; 206 #endif 207 208 #if __NetBSD_Version__ >= 106120000 209 #define APRINT_ERROR aprint_error 210 #define APRINT_NORMAL aprint_normal 211 #else 212 #define APRINT_ERROR printf 213 #define APRINT_NORMAL printf 214 #endif 215 216 217 static const struct bce_product { 218 pci_vendor_id_t bp_vendor; 219 pci_product_id_t bp_product; 220 const char *bp_name; 221 } bce_products[] = { 222 { 223 PCI_VENDOR_BROADCOM, 224 PCI_PRODUCT_BROADCOM_BCM4401, 225 "Broadcom BCM4401 10/100 Ethernet" 226 }, 227 { 228 0, 229 0, 230 NULL 231 }, 232 }; 233 234 static const struct bce_product * 235 bce_lookup(const struct pci_attach_args * pa) 236 { 237 const struct bce_product *bp; 238 239 for (bp = bce_products; bp->bp_name != NULL; bp++) { 240 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 241 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 242 return (bp); 243 } 244 245 return (NULL); 246 } 247 248 /* 249 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 250 * against drivers product list, and return its name if a match is found. 251 */ 252 static int 253 bce_probe(struct device *parent, struct cfdata *match, void *aux) 254 { 255 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 256 257 if (bce_lookup(pa) != NULL) 258 return (1); 259 260 return (0); 261 } 262 263 static void 264 bce_attach(struct device *parent, struct device *self, void *aux) 265 { 266 struct bce_softc *sc = (struct bce_softc *) self; 267 struct pci_attach_args *pa = aux; 268 const struct bce_product *bp; 269 pci_chipset_tag_t pc = pa->pa_pc; 270 pci_intr_handle_t ih; 271 const char *intrstr = NULL; 272 caddr_t kva; 273 bus_dma_segment_t seg; 274 int rseg; 275 u_int32_t command; 276 struct ifnet *ifp; 277 pcireg_t memtype; 278 bus_addr_t memaddr; 279 bus_size_t memsize; 280 int pmreg; 281 pcireg_t pmode; 282 int error; 283 int i; 284 285 bp = bce_lookup(pa); 286 KASSERT(bp != NULL); 287 288 sc->bce_pa = *pa; 289 sc->bce_dmatag = pa->pa_dmat; 290 291 #if __NetBSD_Version__ >= 106120000 292 aprint_naive(": Ethernet controller\n"); 293 #endif 294 APRINT_NORMAL(": %s\n", bp->bp_name); 295 296 /* 297 * Map control/status registers. 298 */ 299 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 300 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 301 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 302 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 303 304 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 305 APRINT_ERROR("%s: failed to enable memory mapping!\n", 306 sc->bce_dev.dv_xname); 307 return; 308 } 309 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BCE_PCI_BAR0); 310 switch (memtype) { 311 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 312 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 313 if (pci_mapreg_map(pa, BCE_PCI_BAR0, memtype, 0, &sc->bce_btag, 314 &sc->bce_bhandle, &memaddr, &memsize) == 0) 315 break; 316 default: 317 APRINT_ERROR("%s: unable to find mem space\n", 318 sc->bce_dev.dv_xname); 319 return; 320 } 321 322 /* Get it out of power save mode if needed. */ 323 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 324 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 325 if (pmode == 3) { 326 /* 327 * The card has lost all configuration data in 328 * this state, so punt. 329 */ 330 printf("%s: unable to wake up from power state D3\n", 331 sc->bce_dev.dv_xname); 332 return; 333 } 334 if (pmode != 0) { 335 printf("%s: waking up from power state D%d\n", 336 sc->bce_dev.dv_xname, pmode); 337 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 338 } 339 } 340 if (pci_intr_map(pa, &ih)) { 341 APRINT_ERROR("%s: couldn't map interrupt\n", 342 sc->bce_dev.dv_xname); 343 return; 344 } 345 intrstr = pci_intr_string(pc, ih); 346 347 sc->bce_intrhand = pci_intr_establish(pc, ih, IPL_NET, bce_intr, sc); 348 349 if (sc->bce_intrhand == NULL) { 350 APRINT_ERROR("%s: couldn't establish interrupt", 351 sc->bce_dev.dv_xname); 352 if (intrstr != NULL) 353 APRINT_NORMAL(" at %s", intrstr); 354 APRINT_NORMAL("\n"); 355 return; 356 } 357 APRINT_NORMAL("%s: interrupting at %s\n", 358 sc->bce_dev.dv_xname, intrstr); 359 360 /* reset the chip */ 361 bce_reset(sc); 362 363 /* 364 * Allocate DMA-safe memory for ring descriptors. 365 * The receive, and transmit rings can not share the same 366 * 4k space, however both are allocated at once here. 367 */ 368 /* 369 * XXX PAGE_SIZE is wasteful; we only need 1KB + 1KB, but 370 * due to the limition above. ?? 371 */ 372 if ((error = bus_dmamem_alloc(sc->bce_dmatag, 373 2 * PAGE_SIZE, PAGE_SIZE, 2 * PAGE_SIZE, 374 &seg, 1, &rseg, BUS_DMA_NOWAIT))) { 375 printf("%s: unable to alloc space for ring descriptors, " 376 "error = %d\n", sc->bce_dev.dv_xname, error); 377 return; 378 } 379 /* map ring space to kernel */ 380 if ((error = bus_dmamem_map(sc->bce_dmatag, &seg, rseg, 381 2 * PAGE_SIZE, &kva, BUS_DMA_NOWAIT))) { 382 printf("%s: unable to map DMA buffers, error = %d\n", 383 sc->bce_dev.dv_xname, error); 384 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 385 return; 386 } 387 /* create a dma map for the ring */ 388 if ((error = bus_dmamap_create(sc->bce_dmatag, 389 2 * PAGE_SIZE, 1, 2 * PAGE_SIZE, 0, BUS_DMA_NOWAIT, 390 &sc->bce_ring_map))) { 391 printf("%s: unable to create ring DMA map, error = %d\n", 392 sc->bce_dev.dv_xname, error); 393 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 394 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 395 return; 396 } 397 /* connect the ring space to the dma map */ 398 if (bus_dmamap_load(sc->bce_dmatag, sc->bce_ring_map, kva, 399 2 * PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) { 400 bus_dmamap_destroy(sc->bce_dmatag, sc->bce_ring_map); 401 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 402 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 403 return; 404 } 405 /* save the ring space in softc */ 406 sc->bce_rx_ring = (struct bce_dma_slot *) kva; 407 sc->bce_tx_ring = (struct bce_dma_slot *) (kva + PAGE_SIZE); 408 409 /* Create the transmit buffer DMA maps. */ 410 for (i = 0; i < BCE_NTXDESC; i++) { 411 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 412 BCE_NTXFRAGS, MCLBYTES, 0, 0, &sc->bce_cdata.bce_tx_map[i])) != 0) { 413 printf("%s: unable to create tx DMA map, error = %d\n", 414 sc->bce_dev.dv_xname, error); 415 } 416 sc->bce_cdata.bce_tx_chain[i] = NULL; 417 } 418 419 /* Create the receive buffer DMA maps. */ 420 for (i = 0; i < BCE_NRXDESC; i++) { 421 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 1, 422 MCLBYTES, 0, 0, &sc->bce_cdata.bce_rx_map[i])) != 0) { 423 printf("%s: unable to create rx DMA map, error = %d\n", 424 sc->bce_dev.dv_xname, error); 425 } 426 sc->bce_cdata.bce_rx_chain[i] = NULL; 427 } 428 429 /* Set up ifnet structure */ 430 ifp = &sc->ethercom.ec_if; 431 strcpy(ifp->if_xname, sc->bce_dev.dv_xname); 432 ifp->if_softc = sc; 433 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 434 ifp->if_ioctl = bce_ioctl; 435 ifp->if_start = bce_start; 436 ifp->if_watchdog = bce_watchdog; 437 ifp->if_init = bce_init; 438 ifp->if_stop = bce_stop; 439 IFQ_SET_READY(&ifp->if_snd); 440 441 /* Initialize our media structures and probe the MII. */ 442 443 sc->bce_mii.mii_ifp = ifp; 444 sc->bce_mii.mii_readreg = bce_mii_read; 445 sc->bce_mii.mii_writereg = bce_mii_write; 446 sc->bce_mii.mii_statchg = bce_statchg; 447 ifmedia_init(&sc->bce_mii.mii_media, 0, bce_mediachange, 448 bce_mediastatus); 449 mii_attach(&sc->bce_dev, &sc->bce_mii, 0xffffffff, MII_PHY_ANY, 450 MII_OFFSET_ANY, 0); 451 if (LIST_FIRST(&sc->bce_mii.mii_phys) == NULL) { 452 ifmedia_add(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 453 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE); 454 } else 455 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_AUTO); 456 /* get the phy */ 457 sc->bce_phy = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 458 BCE_MAGIC_PHY) & 0x1f; 459 /* 460 * Enable activity led. 461 * XXX This should be in a phy driver, but not currently. 462 */ 463 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 464 bce_mii_read((struct device *) sc, 1, 26) & 0x7fff); /* MAGIC */ 465 /* enable traffic meter led mode */ 466 bce_mii_write((struct device *) sc, 1, 27, /* MAGIC */ 467 bce_mii_read((struct device *) sc, 1, 27) | (1 << 6)); /* MAGIC */ 468 469 470 /* Attach the interface */ 471 if_attach(ifp); 472 sc->enaddr[0] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 473 BCE_MAGIC_ENET0); 474 sc->enaddr[1] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 475 BCE_MAGIC_ENET1); 476 sc->enaddr[2] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 477 BCE_MAGIC_ENET2); 478 sc->enaddr[3] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 479 BCE_MAGIC_ENET3); 480 sc->enaddr[4] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 481 BCE_MAGIC_ENET4); 482 sc->enaddr[5] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 483 BCE_MAGIC_ENET5); 484 printf("%s: Ethernet address %s\n", sc->bce_dev.dv_xname, 485 ether_sprintf(sc->enaddr)); 486 ether_ifattach(ifp, sc->enaddr); 487 callout_init(&sc->bce_timeout); 488 } 489 490 /* handle media, and ethernet requests */ 491 static int 492 bce_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 493 { 494 struct bce_softc *sc = ifp->if_softc; 495 struct ifreq *ifr = (struct ifreq *) data; 496 int s, error; 497 498 s = splnet(); 499 switch (cmd) { 500 case SIOCSIFMEDIA: 501 case SIOCGIFMEDIA: 502 error = ifmedia_ioctl(ifp, ifr, &sc->bce_mii.mii_media, cmd); 503 break; 504 default: 505 error = ether_ioctl(ifp, cmd, data); 506 if (error == ENETRESET) { 507 /* change multicast list */ 508 error = 0; 509 } 510 break; 511 } 512 513 /* Try to get more packets going. */ 514 bce_start(ifp); 515 516 splx(s); 517 return error; 518 } 519 520 /* Start packet transmission on the interface. */ 521 static void 522 bce_start(struct ifnet *ifp) 523 { 524 struct bce_softc *sc = ifp->if_softc; 525 struct mbuf *m0; 526 bus_dmamap_t dmamap; 527 int txstart; 528 int txsfree; 529 int newpkts = 0; 530 int error; 531 532 /* 533 * do not start another if currently transmitting, and more 534 * descriptors(tx slots) are needed for next packet. 535 */ 536 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 537 return; 538 539 /* determine number of descriptors available */ 540 if (sc->bce_txsnext >= sc->bce_txin) 541 txsfree = BCE_NTXDESC - 1 + sc->bce_txin - sc->bce_txsnext; 542 else 543 txsfree = sc->bce_txin - sc->bce_txsnext - 1; 544 545 /* 546 * Loop through the send queue, setting up transmit descriptors 547 * until we drain the queue, or use up all available transmit 548 * descriptors. 549 */ 550 while (txsfree > 0) { 551 int seg; 552 553 /* Grab a packet off the queue. */ 554 IFQ_POLL(&ifp->if_snd, m0); 555 if (m0 == NULL) 556 break; 557 558 /* get the transmit slot dma map */ 559 dmamap = sc->bce_cdata.bce_tx_map[sc->bce_txsnext]; 560 561 /* 562 * Load the DMA map. If this fails, the packet either 563 * didn't fit in the alloted number of segments, or we 564 * were short on resources. If the packet will not fit, 565 * it will be dropped. If short on resources, it will 566 * be tried again later. 567 */ 568 error = bus_dmamap_load_mbuf(sc->bce_dmatag, dmamap, m0, 569 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 570 if (error == EFBIG) { 571 printf("%s: Tx packet consumes too many DMA segments, " 572 "dropping...\n", sc->bce_dev.dv_xname); 573 IFQ_DEQUEUE(&ifp->if_snd, m0); 574 m_freem(m0); 575 ifp->if_oerrors++; 576 continue; 577 } else if (error) { 578 /* short on resources, come back later */ 579 printf("%s: unable to load Tx buffer, error = %d\n", 580 sc->bce_dev.dv_xname, error); 581 break; 582 } 583 /* If not enough descriptors available, try again later */ 584 if (dmamap->dm_nsegs > txsfree) { 585 ifp->if_flags |= IFF_OACTIVE; 586 bus_dmamap_unload(sc->bce_dmatag, dmamap); 587 break; 588 } 589 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 590 591 /* So take it off the queue */ 592 IFQ_DEQUEUE(&ifp->if_snd, m0); 593 594 /* save the pointer so it can be freed later */ 595 sc->bce_cdata.bce_tx_chain[sc->bce_txsnext] = m0; 596 597 /* Sync the data DMA map. */ 598 bus_dmamap_sync(sc->bce_dmatag, dmamap, 0, dmamap->dm_mapsize, 599 BUS_DMASYNC_PREWRITE); 600 601 /* Initialize the transmit descriptor(s). */ 602 txstart = sc->bce_txsnext; 603 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 604 u_int32_t ctrl; 605 606 ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK; 607 if (seg == 0) 608 ctrl |= CTRL_SOF; 609 if (seg == dmamap->dm_nsegs - 1) 610 ctrl |= CTRL_EOF; 611 if (sc->bce_txsnext == BCE_NTXDESC - 1) 612 ctrl |= CTRL_EOT; 613 ctrl |= CTRL_IOC; 614 sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl); 615 sc->bce_tx_ring[sc->bce_txsnext].addr = 616 htole32(dmamap->dm_segs[seg].ds_addr + 0x40000000); /* MAGIC */ 617 if (sc->bce_txsnext + 1 > BCE_NTXDESC - 1) 618 sc->bce_txsnext = 0; 619 else 620 sc->bce_txsnext++; 621 txsfree--; 622 } 623 /* sync descriptors being used */ 624 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 625 sizeof(struct bce_dma_slot) * txstart + PAGE_SIZE, 626 sizeof(struct bce_dma_slot) * dmamap->dm_nsegs, 627 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 628 629 /* Give the packet to the chip. */ 630 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_DPTR, 631 sc->bce_txsnext * sizeof(struct bce_dma_slot)); 632 633 newpkts++; 634 635 #if NBPFILTER > 0 636 /* Pass the packet to any BPF listeners. */ 637 if (ifp->if_bpf) 638 bpf_mtap(ifp->if_bpf, m0); 639 #endif /* NBPFILTER > 0 */ 640 } 641 if (txsfree == 0) { 642 /* No more slots left; notify upper layer. */ 643 ifp->if_flags |= IFF_OACTIVE; 644 } 645 if (newpkts) { 646 /* Set a watchdog timer in case the chip flakes out. */ 647 ifp->if_timer = 5; 648 } 649 } 650 651 /* Watchdog timer handler. */ 652 static void 653 bce_watchdog(struct ifnet *ifp) 654 { 655 struct bce_softc *sc = ifp->if_softc; 656 657 printf("%s: device timeout\n", sc->bce_dev.dv_xname); 658 ifp->if_oerrors++; 659 660 (void) bce_init(ifp); 661 662 /* Try to get more packets going. */ 663 bce_start(ifp); 664 } 665 666 int 667 bce_intr(void *xsc) 668 { 669 struct bce_softc *sc; 670 struct ifnet *ifp; 671 u_int32_t intstatus; 672 int wantinit; 673 int handled = 0; 674 675 sc = xsc; 676 ifp = &sc->ethercom.ec_if; 677 678 679 for (wantinit = 0; wantinit == 0;) { 680 intstatus = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 681 BCE_INT_STS); 682 683 /* ignore if not ours, or unsolicited interrupts */ 684 intstatus &= sc->bce_intmask; 685 if (intstatus == 0) 686 break; 687 688 handled = 1; 689 690 /* Ack interrupt */ 691 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS, 692 intstatus); 693 694 /* Receive interrupts. */ 695 if (intstatus & I_RI) 696 bce_rxintr(sc); 697 /* Transmit interrupts. */ 698 if (intstatus & I_XI) 699 bce_txintr(sc); 700 /* Error interrupts */ 701 if (intstatus & ~(I_RI | I_XI)) { 702 if (intstatus & I_XU) 703 printf("%s: transmit fifo underflow\n", 704 sc->bce_dev.dv_xname); 705 if (intstatus & I_RO) { 706 printf("%s: receive fifo overflow\n", 707 sc->bce_dev.dv_xname); 708 ifp->if_ierrors++; 709 } 710 if (intstatus & I_RU) 711 printf("%s: receive descriptor underflow\n", 712 sc->bce_dev.dv_xname); 713 if (intstatus & I_DE) 714 printf("%s: descriptor protocol error\n", 715 sc->bce_dev.dv_xname); 716 if (intstatus & I_PD) 717 printf("%s: data error\n", 718 sc->bce_dev.dv_xname); 719 if (intstatus & I_PC) 720 printf("%s: descriptor error\n", 721 sc->bce_dev.dv_xname); 722 if (intstatus & I_TO) 723 printf("%s: general purpose timeout\n", 724 sc->bce_dev.dv_xname); 725 wantinit = 1; 726 } 727 } 728 729 if (handled) { 730 if (wantinit) 731 bce_init(ifp); 732 /* Try to get more packets going. */ 733 bce_start(ifp); 734 } 735 return (handled); 736 } 737 738 /* Receive interrupt handler */ 739 void 740 bce_rxintr(struct bce_softc *sc) 741 { 742 struct ifnet *ifp = &sc->ethercom.ec_if; 743 struct rx_pph *pph; 744 struct mbuf *m; 745 int curr; 746 int len; 747 int i; 748 749 /* get pointer to active receive slot */ 750 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS) 751 & RS_CD_MASK; 752 curr = curr / sizeof(struct bce_dma_slot); 753 if (curr >= BCE_NRXDESC) 754 curr = BCE_NRXDESC - 1; 755 756 /* process packets up to but not current packet being worked on */ 757 for (i = sc->bce_rxin; i != curr; 758 i + 1 > BCE_NRXDESC - 1 ? i = 0 : i++) { 759 /* complete any post dma memory ops on packet */ 760 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i], 0, 761 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 762 BUS_DMASYNC_POSTREAD); 763 764 /* 765 * If the packet had an error, simply recycle the buffer, 766 * resetting the len, and flags. 767 */ 768 pph = mtod(sc->bce_cdata.bce_rx_chain[i], struct rx_pph *); 769 if (pph->flags & (RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)) { 770 ifp->if_ierrors++; 771 pph->len = 0; 772 pph->flags = 0; 773 continue; 774 } 775 /* receive the packet */ 776 len = pph->len; 777 if (len == 0) 778 continue; /* no packet if empty */ 779 pph->len = 0; 780 pph->flags = 0; 781 /* bump past pre header to packet */ 782 sc->bce_cdata.bce_rx_chain[i]->m_data += 30; /* MAGIC */ 783 784 /* 785 * If the packet is small enough to fit in a 786 * single header mbuf, allocate one and copy 787 * the data into it. This greatly reduces 788 * memory consumption when receiving lots 789 * of small packets. 790 * 791 * Otherwise, add a new buffer to the receive 792 * chain. If this fails, drop the packet and 793 * recycle the old buffer. 794 */ 795 if (len <= (MHLEN - 2)) { 796 MGETHDR(m, M_DONTWAIT, MT_DATA); 797 if (m == NULL) 798 goto dropit; 799 m->m_data += 2; 800 memcpy(mtod(m, caddr_t), 801 mtod(sc->bce_cdata.bce_rx_chain[i], caddr_t), len); 802 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; /* MAGIC */ 803 } else { 804 m = sc->bce_cdata.bce_rx_chain[i]; 805 if (bce_add_rxbuf(sc, i) != 0) { 806 dropit: 807 ifp->if_ierrors++; 808 /* continue to use old buffer */ 809 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; 810 bus_dmamap_sync(sc->bce_dmatag, 811 sc->bce_cdata.bce_rx_map[i], 0, 812 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 813 BUS_DMASYNC_PREREAD); 814 continue; 815 } 816 } 817 818 m->m_flags |= M_HASFCS; 819 m->m_pkthdr.rcvif = ifp; 820 m->m_pkthdr.len = m->m_len = len; 821 ifp->if_ipackets++; 822 823 #if NBPFILTER > 0 824 /* 825 * Pass this up to any BPF listeners, but only 826 * pass it up the stack if it's for us. 827 */ 828 if (ifp->if_bpf) 829 bpf_mtap(ifp->if_bpf, m); 830 #endif /* NBPFILTER > 0 */ 831 832 /* Pass it on. */ 833 (*ifp->if_input) (ifp, m); 834 835 /* re-check current in case it changed */ 836 curr = (bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 837 BCE_DMA_RXSTATUS) & RS_CD_MASK) / 838 sizeof(struct bce_dma_slot); 839 if (curr >= BCE_NRXDESC) 840 curr = BCE_NRXDESC - 1; 841 } 842 sc->bce_rxin = curr; 843 } 844 845 /* Transmit interrupt handler */ 846 void 847 bce_txintr(struct bce_softc *sc) 848 { 849 struct ifnet *ifp = &sc->ethercom.ec_if; 850 int curr; 851 int i; 852 853 ifp->if_flags &= ~IFF_OACTIVE; 854 855 /* 856 * Go through the Tx list and free mbufs for those 857 * frames which have been transmitted. 858 */ 859 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXSTATUS) & 860 RS_CD_MASK; 861 curr = curr / sizeof(struct bce_dma_slot); 862 if (curr >= BCE_NTXDESC) 863 curr = BCE_NTXDESC - 1; 864 for (i = sc->bce_txin; i != curr; 865 i + 1 > BCE_NTXDESC - 1 ? i = 0 : i++) { 866 /* do any post dma memory ops on transmit data */ 867 if (sc->bce_cdata.bce_tx_chain[i] == NULL) 868 continue; 869 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i], 0, 870 sc->bce_cdata.bce_tx_map[i]->dm_mapsize, 871 BUS_DMASYNC_POSTWRITE); 872 bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i]); 873 m_freem(sc->bce_cdata.bce_tx_chain[i]); 874 sc->bce_cdata.bce_tx_chain[i] = NULL; 875 ifp->if_opackets++; 876 } 877 sc->bce_txin = curr; 878 879 /* 880 * If there are no more pending transmissions, cancel the watchdog 881 * timer 882 */ 883 if (sc->bce_txsnext == sc->bce_txin) 884 ifp->if_timer = 0; 885 } 886 887 /* initialize the interface */ 888 static int 889 bce_init(struct ifnet *ifp) 890 { 891 struct bce_softc *sc = ifp->if_softc; 892 u_int32_t reg_win; 893 int error; 894 int i; 895 896 /* Cancel any pending I/O. */ 897 bce_stop(ifp, 0); 898 899 /* enable pci inerrupts, bursts, and prefetch */ 900 901 /* remap the pci registers to the Sonics config registers */ 902 903 /* save the current map, so it can be restored */ 904 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 905 BCE_REG_WIN); 906 907 /* set register window to Sonics registers */ 908 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 909 BCE_SONICS_WIN); 910 911 /* enable SB to PCI interrupt */ 912 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 913 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) | 914 SBIV_ENET0); 915 916 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 917 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 918 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) | 919 SBTOPCI_PREF | SBTOPCI_BURST); 920 921 /* restore to ethernet register space */ 922 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 923 reg_win); 924 925 /* Reset the chip to a known state. */ 926 bce_reset(sc); 927 928 /* Initialize transmit descriptors */ 929 memset(sc->bce_tx_ring, 0, BCE_NTXDESC * sizeof(struct bce_dma_slot)); 930 sc->bce_txsnext = 0; 931 sc->bce_txin = 0; 932 933 /* enable crc32 generation */ 934 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 935 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) | 936 BCE_EMC_CG); 937 938 /* setup DMA interrupt control */ 939 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1 << 24); /* MAGIC */ 940 941 /* setup packet filter */ 942 bce_set_filter(ifp); 943 944 /* set max frame length, account for possible vlan tag */ 945 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_MAX, 946 ETHER_MAX_LEN + 32); 947 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_MAX, 948 ETHER_MAX_LEN + 32); 949 950 /* set tx watermark */ 951 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_WATER, 56); 952 953 /* enable transmit */ 954 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, XC_XE); 955 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXADDR, 956 sc->bce_ring_map->dm_segs[0].ds_addr + PAGE_SIZE + 0x40000000); /* MAGIC */ 957 958 /* 959 * Give the receive ring to the chip, and 960 * start the receive DMA engine. 961 */ 962 sc->bce_rxin = 0; 963 964 /* clear the rx descriptor ring */ 965 memset(sc->bce_rx_ring, 0, BCE_NRXDESC * sizeof(struct bce_dma_slot)); 966 /* enable receive */ 967 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 968 30 << 1 | 1); /* MAGIC */ 969 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXADDR, 970 sc->bce_ring_map->dm_segs[0].ds_addr + 0x40000000); /* MAGIC */ 971 972 /* Initalize receive descriptors */ 973 for (i = 0; i < BCE_NRXDESC; i++) { 974 if (sc->bce_cdata.bce_rx_chain[i] == NULL) { 975 if ((error = bce_add_rxbuf(sc, i)) != 0) { 976 printf("%s: unable to allocate or map rx(%d) " 977 "mbuf, error = %d\n", sc->bce_dev.dv_xname, 978 i, error); 979 bce_rxdrain(sc); 980 return (error); 981 } 982 } else 983 BCE_INIT_RXDESC(sc, i); 984 } 985 986 /* Enable interrupts */ 987 sc->bce_intmask = 988 I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO; 989 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 990 sc->bce_intmask); 991 992 /* start the receive dma */ 993 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR, 994 BCE_NRXDESC * sizeof(struct bce_dma_slot)); 995 996 /* set media */ 997 mii_mediachg(&sc->bce_mii); 998 999 /* turn on the ethernet mac */ 1000 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1001 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1002 BCE_ENET_CTL) | EC_EE); 1003 1004 /* start timer */ 1005 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1006 1007 /* mark as running, and no outputs active */ 1008 ifp->if_flags |= IFF_RUNNING; 1009 ifp->if_flags &= ~IFF_OACTIVE; 1010 1011 return 0; 1012 } 1013 1014 /* add a mac address to packet filter */ 1015 void 1016 bce_add_mac(struct bce_softc *sc, u_int8_t *mac, u_long idx) 1017 { 1018 int i; 1019 u_int32_t rval; 1020 1021 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_LOW, 1022 mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]); 1023 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_HI, 1024 mac[0] << 8 | mac[1] | 0x10000); /* MAGIC */ 1025 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1026 idx << 16 | 8); /* MAGIC */ 1027 /* wait for write to complete */ 1028 for (i = 0; i < 100; i++) { 1029 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1030 BCE_FILT_CTL); 1031 if (!(rval & 0x80000000)) /* MAGIC */ 1032 break; 1033 delay(10); 1034 } 1035 if (i == 100) { 1036 printf("%s: timed out writting pkt filter ctl\n", 1037 sc->bce_dev.dv_xname); 1038 } 1039 } 1040 1041 /* Add a receive buffer to the indiciated descriptor. */ 1042 static int 1043 bce_add_rxbuf(struct bce_softc *sc, int idx) 1044 { 1045 struct mbuf *m; 1046 int error; 1047 1048 MGETHDR(m, M_DONTWAIT, MT_DATA); 1049 if (m == NULL) 1050 return (ENOBUFS); 1051 1052 MCLGET(m, M_DONTWAIT); 1053 if ((m->m_flags & M_EXT) == 0) { 1054 m_freem(m); 1055 return (ENOBUFS); 1056 } 1057 if (sc->bce_cdata.bce_rx_chain[idx] != NULL) 1058 bus_dmamap_unload(sc->bce_dmatag, 1059 sc->bce_cdata.bce_rx_map[idx]); 1060 1061 sc->bce_cdata.bce_rx_chain[idx] = m; 1062 1063 error = bus_dmamap_load(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 1064 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1065 BUS_DMA_READ | BUS_DMA_NOWAIT); 1066 if (error) 1067 return (error); 1068 1069 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 0, 1070 sc->bce_cdata.bce_rx_map[idx]->dm_mapsize, BUS_DMASYNC_PREREAD); 1071 1072 BCE_INIT_RXDESC(sc, idx); 1073 1074 return (0); 1075 1076 } 1077 1078 /* Drain the receive queue. */ 1079 static void 1080 bce_rxdrain(struct bce_softc *sc) 1081 { 1082 int i; 1083 1084 for (i = 0; i < BCE_NRXDESC; i++) { 1085 if (sc->bce_cdata.bce_rx_chain[i] != NULL) { 1086 bus_dmamap_unload(sc->bce_dmatag, 1087 sc->bce_cdata.bce_rx_map[i]); 1088 m_freem(sc->bce_cdata.bce_rx_chain[i]); 1089 sc->bce_cdata.bce_rx_chain[i] = NULL; 1090 } 1091 } 1092 } 1093 1094 /* Stop transmission on the interface */ 1095 static void 1096 bce_stop(struct ifnet *ifp, int disable) 1097 { 1098 struct bce_softc *sc = ifp->if_softc; 1099 int i; 1100 u_int32_t val; 1101 1102 /* Stop the 1 second timer */ 1103 callout_stop(&sc->bce_timeout); 1104 1105 /* Down the MII. */ 1106 mii_down(&sc->bce_mii); 1107 1108 /* Disable interrupts. */ 1109 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0); 1110 sc->bce_intmask = 0; 1111 delay(10); 1112 1113 /* Disable emac */ 1114 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED); 1115 for (i = 0; i < 200; i++) { 1116 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1117 BCE_ENET_CTL); 1118 if (!(val & EC_ED)) 1119 break; 1120 delay(10); 1121 } 1122 1123 /* Stop the DMA */ 1124 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 0); 1125 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1126 delay(10); 1127 1128 /* Release any queued transmit buffers. */ 1129 for (i = 0; i < BCE_NTXDESC; i++) { 1130 if (sc->bce_cdata.bce_tx_chain[i] != NULL) { 1131 bus_dmamap_unload(sc->bce_dmatag, 1132 sc->bce_cdata.bce_tx_map[i]); 1133 m_freem(sc->bce_cdata.bce_tx_chain[i]); 1134 sc->bce_cdata.bce_tx_chain[i] = NULL; 1135 } 1136 } 1137 1138 /* drain receive queue */ 1139 if (disable) 1140 bce_rxdrain(sc); 1141 1142 /* Mark the interface down and cancel the watchdog timer. */ 1143 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1144 ifp->if_timer = 0; 1145 } 1146 1147 /* reset the chip */ 1148 static void 1149 bce_reset(struct bce_softc *sc) 1150 { 1151 u_int32_t val; 1152 u_int32_t sbval; 1153 int i; 1154 1155 /* if SB core is up */ 1156 sbval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1157 BCE_SBTMSTATELOW); 1158 if ((sbval & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK) { 1159 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1160 0); 1161 1162 /* disable emac */ 1163 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1164 EC_ED); 1165 for (i = 0; i < 200; i++) { 1166 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1167 BCE_ENET_CTL); 1168 if (!(val & EC_ED)) 1169 break; 1170 delay(10); 1171 } 1172 if (i == 200) 1173 printf("%s: timed out disabling ethernet mac\n", 1174 sc->bce_dev.dv_xname); 1175 1176 /* reset the dma engines */ 1177 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1178 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS); 1179 /* if error on receive, wait to go idle */ 1180 if (val & RS_ERROR) { 1181 for (i = 0; i < 100; i++) { 1182 val = bus_space_read_4(sc->bce_btag, 1183 sc->bce_bhandle, BCE_DMA_RXSTATUS); 1184 if (val & RS_DMA_IDLE) 1185 break; 1186 delay(10); 1187 } 1188 if (i == 100) 1189 printf("%s: receive dma did not go idle after" 1190 " error\n", sc->bce_dev.dv_xname); 1191 } 1192 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1193 BCE_DMA_RXSTATUS, 0); 1194 1195 /* reset ethernet mac */ 1196 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1197 EC_ES); 1198 for (i = 0; i < 200; i++) { 1199 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1200 BCE_ENET_CTL); 1201 if (!(val & EC_ES)) 1202 break; 1203 delay(10); 1204 } 1205 if (i == 200) 1206 printf("%s: timed out restting ethernet mac\n", 1207 sc->bce_dev.dv_xname); 1208 } else { 1209 u_int32_t reg_win; 1210 1211 /* remap the pci registers to the Sonics config registers */ 1212 1213 /* save the current map, so it can be restored */ 1214 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1215 BCE_REG_WIN); 1216 /* set register window to Sonics registers */ 1217 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1218 BCE_REG_WIN, BCE_SONICS_WIN); 1219 1220 /* enable SB to PCI interrupt */ 1221 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 1222 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1223 BCE_SBINTVEC) | 1224 SBIV_ENET0); 1225 1226 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 1227 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 1228 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1229 BCE_SPCI_TR2) | 1230 SBTOPCI_PREF | SBTOPCI_BURST); 1231 1232 /* restore to ethernet register space */ 1233 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 1234 reg_win); 1235 } 1236 1237 /* disable SB core if not in reset */ 1238 if (!(sbval & SBTML_RESET)) { 1239 1240 /* set the reject bit */ 1241 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1242 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_CLK); 1243 for (i = 0; i < 200; i++) { 1244 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1245 BCE_SBTMSTATELOW); 1246 if (val & SBTML_REJ) 1247 break; 1248 delay(1); 1249 } 1250 if (i == 200) 1251 printf("%s: while restting core, reject did not set\n", 1252 sc->bce_dev.dv_xname); 1253 /* wait until busy is clear */ 1254 for (i = 0; i < 200; i++) { 1255 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1256 BCE_SBTMSTATEHI); 1257 if (!(val & 0x4)) 1258 break; 1259 delay(1); 1260 } 1261 if (i == 200) 1262 printf("%s: while restting core, busy did not clear\n", 1263 sc->bce_dev.dv_xname); 1264 /* set reset and reject while enabling the clocks */ 1265 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1266 BCE_SBTMSTATELOW, 1267 SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET); 1268 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1269 BCE_SBTMSTATELOW); 1270 delay(10); 1271 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1272 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_RESET); 1273 delay(1); 1274 } 1275 /* enable clock */ 1276 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1277 SBTML_FGC | SBTML_CLK | SBTML_RESET); 1278 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1279 delay(1); 1280 1281 /* clear any error bits that may be on */ 1282 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI); 1283 if (val & 1) 1284 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI, 1285 0); 1286 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE); 1287 if (val & SBIM_MAGIC_ERRORBITS) 1288 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE, 1289 val & ~SBIM_MAGIC_ERRORBITS); 1290 1291 /* clear reset and allow it to propagate throughout the core */ 1292 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1293 SBTML_FGC | SBTML_CLK); 1294 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1295 delay(1); 1296 1297 /* leave clock enabled */ 1298 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1299 SBTML_CLK); 1300 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1301 delay(1); 1302 1303 /* initialize MDC preamble, frequency */ 1304 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_CTL, 0x8d); /* MAGIC */ 1305 1306 /* enable phy, differs for internal, and external */ 1307 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL); 1308 if (!(val & BCE_DC_IP)) { 1309 /* select external phy */ 1310 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_EP); 1311 } else if (val & BCE_DC_ER) { /* internal, clear reset bit if on */ 1312 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL, 1313 val & ~BCE_DC_ER); 1314 delay(100); 1315 } 1316 } 1317 1318 /* Set up the receive filter. */ 1319 void 1320 bce_set_filter(struct ifnet *ifp) 1321 { 1322 struct bce_softc *sc = ifp->if_softc; 1323 1324 if (ifp->if_flags & IFF_PROMISC) { 1325 ifp->if_flags |= IFF_ALLMULTI; 1326 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1327 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) 1328 | ERC_PE); 1329 } else { 1330 ifp->if_flags &= ~IFF_ALLMULTI; 1331 1332 /* turn off promiscuous */ 1333 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1334 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1335 BCE_RX_CTL) & ~ERC_PE); 1336 1337 /* enable/disable broadcast */ 1338 if (ifp->if_flags & IFF_BROADCAST) 1339 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1340 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1341 sc->bce_bhandle, BCE_RX_CTL) & ~ERC_DB); 1342 else 1343 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1344 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1345 sc->bce_bhandle, BCE_RX_CTL) | ERC_DB); 1346 1347 /* disable the filter */ 1348 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1349 0); 1350 1351 /* add our own address */ 1352 bce_add_mac(sc, sc->enaddr, 0); 1353 1354 /* for now accept all multicast */ 1355 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1356 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) | 1357 ERC_AM); 1358 ifp->if_flags |= IFF_ALLMULTI; 1359 1360 /* enable the filter */ 1361 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1362 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1363 BCE_FILT_CTL) | 1); 1364 } 1365 } 1366 1367 /* Read a PHY register on the MII. */ 1368 int 1369 bce_mii_read(struct device *self, int phy, int reg) 1370 { 1371 struct bce_softc *sc = (struct bce_softc *) self; 1372 int i; 1373 u_int32_t val; 1374 1375 /* clear mii_int */ 1376 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR); 1377 1378 /* Read the PHY register */ 1379 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1380 (MII_COMMAND_READ << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1381 (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */ 1382 1383 for (i = 0; i < BCE_TIMEOUT; i++) { 1384 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS); 1385 if (val & BCE_MIINTR) 1386 break; 1387 delay(10); 1388 } 1389 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1390 if (i == BCE_TIMEOUT) { 1391 printf("%s: PHY read timed out reading phy %d, reg %d, val = " 1392 "0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val); 1393 return (0); 1394 } 1395 return (val & BCE_MICOMM_DATA); 1396 } 1397 1398 /* Write a PHY register on the MII */ 1399 void 1400 bce_mii_write(struct device *self, int phy, int reg, int val) 1401 { 1402 struct bce_softc *sc = (struct bce_softc *) self; 1403 int i; 1404 u_int32_t rval; 1405 1406 /* clear mii_int */ 1407 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, 1408 BCE_MIINTR); 1409 1410 /* Write the PHY register */ 1411 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1412 (MII_COMMAND_WRITE << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1413 (MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) | /* MAGIC */ 1414 BCE_MIPHY(phy) | BCE_MIREG(reg)); 1415 1416 /* wait for write to complete */ 1417 for (i = 0; i < BCE_TIMEOUT; i++) { 1418 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1419 BCE_MI_STS); 1420 if (rval & BCE_MIINTR) 1421 break; 1422 delay(10); 1423 } 1424 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1425 if (i == BCE_TIMEOUT) { 1426 printf("%s: PHY timed out writting phy %d, reg %d, val " 1427 "= 0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val); 1428 } 1429 } 1430 1431 /* sync hardware duplex mode to software state */ 1432 void 1433 bce_statchg(struct device *self) 1434 { 1435 struct bce_softc *sc = (struct bce_softc *) self; 1436 u_int32_t reg; 1437 1438 /* if needed, change register to match duplex mode */ 1439 reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL); 1440 if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD)) 1441 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1442 reg | EXC_FD); 1443 else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD) 1444 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1445 reg & ~EXC_FD); 1446 1447 /* 1448 * Enable activity led. 1449 * XXX This should be in a phy driver, but not currently. 1450 */ 1451 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 1452 bce_mii_read((struct device *) sc, 1, 26) & 0x7fff); /* MAGIC */ 1453 /* enable traffic meter led mode */ 1454 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 1455 bce_mii_read((struct device *) sc, 1, 27) | (1 << 6)); /* MAGIC */ 1456 } 1457 1458 /* Set hardware to newly-selected media */ 1459 int 1460 bce_mediachange(struct ifnet *ifp) 1461 { 1462 struct bce_softc *sc = ifp->if_softc; 1463 1464 if (ifp->if_flags & IFF_UP) 1465 mii_mediachg(&sc->bce_mii); 1466 return (0); 1467 } 1468 1469 /* Get the current interface media status */ 1470 static void 1471 bce_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1472 { 1473 struct bce_softc *sc = ifp->if_softc; 1474 1475 mii_pollstat(&sc->bce_mii); 1476 ifmr->ifm_active = sc->bce_mii.mii_media_active; 1477 ifmr->ifm_status = sc->bce_mii.mii_media_status; 1478 } 1479 1480 /* One second timer, checks link status */ 1481 static void 1482 bce_tick(void *v) 1483 { 1484 struct bce_softc *sc = v; 1485 1486 /* Tick the MII. */ 1487 mii_tick(&sc->bce_mii); 1488 1489 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1490 } 1491
Indexes created Tue Sep 30 20:09:53 GMT 2025