if_bce.c revision 1.60
1 /* $NetBSD: if_bce.c,v 1.60 2022/01/22 15:10:32 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Clifford Wright. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Broadcom BCM440x 10/100 ethernet (broadcom.com) 32 * SiliconBackplane is technology from Sonics, Inc.(sonicsinc.com) 33 * 34 * Cliff Wright cliff (at) snipe444.org 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_bce.c,v 1.60 2022/01/22 15:10:32 skrll Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/callout.h> 43 #include <sys/sockio.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/device.h> 48 #include <sys/socket.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 #include <net/if_ether.h> 54 55 #include <net/bpf.h> 56 #include <sys/rndsource.h> 57 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 65 #include <dev/pci/if_bcereg.h> 66 67 /* transmit buffer max frags allowed */ 68 #define BCE_NTXFRAGS 16 69 70 /* ring descriptor */ 71 struct bce_dma_slot { 72 uint32_t ctrl; 73 uint32_t addr; 74 }; 75 #define CTRL_BC_MASK 0x1fff /* buffer byte count */ 76 #define CTRL_EOT 0x10000000 /* end of descriptor table */ 77 #define CTRL_IOC 0x20000000 /* interrupt on completion */ 78 #define CTRL_EOF 0x40000000 /* end of frame */ 79 #define CTRL_SOF 0x80000000 /* start of frame */ 80 81 /* Packet status is returned in a pre-packet header */ 82 struct rx_pph { 83 uint16_t len; 84 uint16_t flags; 85 uint16_t pad[12]; 86 }; 87 88 /* packet status flags bits */ 89 #define RXF_NO 0x8 /* odd number of nibbles */ 90 #define RXF_RXER 0x4 /* receive symbol error */ 91 #define RXF_CRC 0x2 /* crc error */ 92 #define RXF_OV 0x1 /* fifo overflow */ 93 94 /* number of descriptors used in a ring */ 95 #define BCE_NRXDESC 128 96 #define BCE_NTXDESC 128 97 98 /* 99 * Mbuf pointers. We need these to keep track of the virtual addresses 100 * of our mbuf chains since we can only convert from physical to virtual, 101 * not the other way around. 102 */ 103 struct bce_chain_data { 104 struct mbuf *bce_tx_chain[BCE_NTXDESC]; 105 struct mbuf *bce_rx_chain[BCE_NRXDESC]; 106 bus_dmamap_t bce_tx_map[BCE_NTXDESC]; 107 bus_dmamap_t bce_rx_map[BCE_NRXDESC]; 108 }; 109 110 #define BCE_TIMEOUT 100 /* # 10us for mii read/write */ 111 112 struct bce_softc { 113 device_t bce_dev; 114 bus_space_tag_t bce_btag; 115 bus_space_handle_t bce_bhandle; 116 bus_dma_tag_t bce_dmatag; 117 struct ethercom ethercom; /* interface info */ 118 void *bce_intrhand; 119 struct pci_attach_args bce_pa; 120 struct mii_data bce_mii; 121 uint32_t bce_phy; /* eeprom indicated phy */ 122 struct ifmedia bce_ifmedia; /* media info *//* Check */ 123 uint8_t enaddr[ETHER_ADDR_LEN]; 124 struct bce_dma_slot *bce_rx_ring; /* receive ring */ 125 struct bce_dma_slot *bce_tx_ring; /* transmit ring */ 126 struct bce_chain_data bce_cdata; /* mbufs */ 127 bus_dmamap_t bce_ring_map; 128 uint32_t bce_intmask; /* current intr mask */ 129 uint32_t bce_rxin; /* last rx descriptor seen */ 130 uint32_t bce_txin; /* last tx descriptor seen */ 131 int bce_txsfree; /* no. tx slots available */ 132 int bce_txsnext; /* next available tx slot */ 133 callout_t bce_timeout; 134 krndsource_t rnd_source; 135 }; 136 137 /* for ring descriptors */ 138 #define BCE_RXBUF_LEN (MCLBYTES - 4) 139 #define BCE_INIT_RXDESC(sc, x) \ 140 do { \ 141 struct bce_dma_slot *__bced = &sc->bce_rx_ring[x]; \ 142 \ 143 *mtod(sc->bce_cdata.bce_rx_chain[x], uint32_t *) = 0; \ 144 __bced->addr = \ 145 htole32(sc->bce_cdata.bce_rx_map[x]->dm_segs[0].ds_addr \ 146 + 0x40000000); \ 147 if (x != (BCE_NRXDESC - 1)) \ 148 __bced->ctrl = htole32(BCE_RXBUF_LEN); \ 149 else \ 150 __bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT); \ 151 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, \ 152 sizeof(struct bce_dma_slot) * x, \ 153 sizeof(struct bce_dma_slot), \ 154 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 155 } while (/* CONSTCOND */ 0) 156 157 static int bce_probe(device_t, cfdata_t, void *); 158 static void bce_attach(device_t, device_t, void *); 159 static int bce_ioctl(struct ifnet *, u_long, void *); 160 static void bce_start(struct ifnet *); 161 static void bce_watchdog(struct ifnet *); 162 static int bce_intr(void *); 163 static void bce_rxintr(struct bce_softc *); 164 static void bce_txintr(struct bce_softc *); 165 static int bce_init(struct ifnet *); 166 static void bce_add_mac(struct bce_softc *, uint8_t *, unsigned long); 167 static int bce_add_rxbuf(struct bce_softc *, int); 168 static void bce_rxdrain(struct bce_softc *); 169 static void bce_stop(struct ifnet *, int); 170 static void bce_reset(struct bce_softc *); 171 static bool bce_resume(device_t, const pmf_qual_t *); 172 static void bce_set_filter(struct ifnet *); 173 static int bce_mii_read(device_t, int, int, uint16_t *); 174 static int bce_mii_write(device_t, int, int, uint16_t); 175 static void bce_statchg(struct ifnet *); 176 static void bce_tick(void *); 177 178 CFATTACH_DECL_NEW(bce, sizeof(struct bce_softc), 179 bce_probe, bce_attach, NULL, NULL); 180 181 static const struct bce_product { 182 pci_vendor_id_t bp_vendor; 183 pci_product_id_t bp_product; 184 const char *bp_name; 185 } bce_products[] = { 186 { 187 PCI_VENDOR_BROADCOM, 188 PCI_PRODUCT_BROADCOM_BCM4401, 189 "Broadcom BCM4401 10/100 Ethernet" 190 }, 191 { 192 PCI_VENDOR_BROADCOM, 193 PCI_PRODUCT_BROADCOM_BCM4401_B0, 194 "Broadcom BCM4401-B0 10/100 Ethernet" 195 }, 196 { 197 PCI_VENDOR_BROADCOM, 198 PCI_PRODUCT_BROADCOM_BCM4401_B1, 199 "Broadcom BCM4401-B1 10/100 Ethernet" 200 }, 201 { 202 203 0, 204 0, 205 NULL 206 }, 207 }; 208 209 static const struct bce_product * 210 bce_lookup(const struct pci_attach_args * pa) 211 { 212 const struct bce_product *bp; 213 214 for (bp = bce_products; bp->bp_name != NULL; bp++) { 215 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 216 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 217 return (bp); 218 } 219 220 return (NULL); 221 } 222 223 /* 224 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 225 * against drivers product list, and return its name if a match is found. 226 */ 227 static int 228 bce_probe(device_t parent, cfdata_t match, void *aux) 229 { 230 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 231 232 if (bce_lookup(pa) != NULL) 233 return (1); 234 235 return (0); 236 } 237 238 static void 239 bce_attach(device_t parent, device_t self, void *aux) 240 { 241 struct bce_softc *sc = device_private(self); 242 struct pci_attach_args *pa = aux; 243 const struct bce_product *bp; 244 pci_chipset_tag_t pc = pa->pa_pc; 245 pci_intr_handle_t ih; 246 const char *intrstr = NULL; 247 uint32_t command; 248 pcireg_t memtype, pmode; 249 bus_addr_t memaddr; 250 bus_size_t memsize; 251 void *kva; 252 bus_dma_segment_t seg; 253 int error, i, pmreg, rseg; 254 uint16_t phyval; 255 struct ifnet *ifp; 256 struct mii_data *mii = &sc->bce_mii; 257 char intrbuf[PCI_INTRSTR_LEN]; 258 259 sc->bce_dev = self; 260 261 bp = bce_lookup(pa); 262 KASSERT(bp != NULL); 263 264 sc->bce_pa = *pa; 265 266 /* BCM440x can only address 30 bits (1GB) */ 267 if (bus_dmatag_subregion(pa->pa_dmat, 0, __MASK(30), 268 &(sc->bce_dmatag), BUS_DMA_NOWAIT) != 0) { 269 aprint_error_dev(self, 270 "WARNING: failed to restrict dma range," 271 " falling back to parent bus dma range\n"); 272 sc->bce_dmatag = pa->pa_dmat; 273 } 274 275 aprint_naive(": Ethernet controller\n"); 276 aprint_normal(": %s\n", bp->bp_name); 277 278 /* 279 * Map control/status registers. 280 */ 281 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 282 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 283 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 284 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 285 286 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 287 aprint_error_dev(self, "failed to enable memory mapping!\n"); 288 return; 289 } 290 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BCE_PCI_BAR0); 291 switch (memtype) { 292 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 293 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 294 if (pci_mapreg_map(pa, BCE_PCI_BAR0, memtype, 0, &sc->bce_btag, 295 &sc->bce_bhandle, &memaddr, &memsize) == 0) 296 break; 297 /* FALLTHROUGH */ 298 default: 299 aprint_error_dev(self, "unable to find mem space\n"); 300 return; 301 } 302 303 /* Get it out of power save mode if needed. */ 304 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, NULL)) { 305 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) 306 & PCI_PMCSR_STATE_MASK; 307 if (pmode == PCI_PMCSR_STATE_D3) { 308 /* 309 * The card has lost all configuration data in 310 * this state, so punt. 311 */ 312 aprint_error_dev(self, 313 "unable to wake up from power state D3\n"); 314 return; 315 } 316 if (pmode != PCI_PMCSR_STATE_D0) { 317 aprint_normal_dev(self, 318 "waking up from power state D%d\n", pmode); 319 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 0); 320 } 321 } 322 if (pci_intr_map(pa, &ih)) { 323 aprint_error_dev(self, "couldn't map interrupt\n"); 324 return; 325 } 326 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 327 328 sc->bce_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, bce_intr, 329 sc, device_xname(self)); 330 331 if (sc->bce_intrhand == NULL) { 332 aprint_error_dev(self, "couldn't establish interrupt\n"); 333 if (intrstr != NULL) 334 aprint_error(" at %s", intrstr); 335 aprint_error("\n"); 336 return; 337 } 338 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 339 340 /* reset the chip */ 341 bce_reset(sc); 342 343 /* 344 * Allocate DMA-safe memory for ring descriptors. 345 * The receive, and transmit rings can not share the same 346 * 4k space, however both are allocated at once here. 347 */ 348 /* 349 * XXX PAGE_SIZE is wasteful; we only need 1KB + 1KB, but 350 * due to the limition above. ?? 351 */ 352 if ((error = bus_dmamem_alloc(sc->bce_dmatag, 353 2 * PAGE_SIZE, PAGE_SIZE, 2 * PAGE_SIZE, 354 &seg, 1, &rseg, BUS_DMA_NOWAIT))) { 355 aprint_error_dev(self, 356 "unable to alloc space for ring descriptors, error = %d\n", 357 error); 358 return; 359 } 360 /* map ring space to kernel */ 361 if ((error = bus_dmamem_map(sc->bce_dmatag, &seg, rseg, 362 2 * PAGE_SIZE, &kva, BUS_DMA_NOWAIT))) { 363 aprint_error_dev(self, 364 "unable to map DMA buffers, error = %d\n", error); 365 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 366 return; 367 } 368 /* create a dma map for the ring */ 369 if ((error = bus_dmamap_create(sc->bce_dmatag, 370 2 * PAGE_SIZE, 1, 2 * PAGE_SIZE, 0, BUS_DMA_NOWAIT, 371 &sc->bce_ring_map))) { 372 aprint_error_dev(self, 373 "unable to create ring DMA map, error = %d\n", error); 374 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 375 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 376 return; 377 } 378 /* connect the ring space to the dma map */ 379 if (bus_dmamap_load(sc->bce_dmatag, sc->bce_ring_map, kva, 380 2 * PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) { 381 bus_dmamap_destroy(sc->bce_dmatag, sc->bce_ring_map); 382 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 383 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 384 return; 385 } 386 /* save the ring space in softc */ 387 sc->bce_rx_ring = (struct bce_dma_slot *) kva; 388 sc->bce_tx_ring = (struct bce_dma_slot *) ((char *)kva + PAGE_SIZE); 389 390 /* Create the transmit buffer DMA maps. */ 391 for (i = 0; i < BCE_NTXDESC; i++) { 392 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 393 BCE_NTXFRAGS, MCLBYTES, 0, 0, &sc->bce_cdata.bce_tx_map[i])) != 0) { 394 aprint_error_dev(self, 395 "unable to create tx DMA map, error = %d\n", error); 396 } 397 sc->bce_cdata.bce_tx_chain[i] = NULL; 398 } 399 400 /* Create the receive buffer DMA maps. */ 401 for (i = 0; i < BCE_NRXDESC; i++) { 402 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 1, 403 MCLBYTES, 0, 0, &sc->bce_cdata.bce_rx_map[i])) != 0) { 404 aprint_error_dev(self, 405 "unable to create rx DMA map, error = %d\n", error); 406 } 407 sc->bce_cdata.bce_rx_chain[i] = NULL; 408 } 409 410 /* Set up ifnet structure */ 411 ifp = &sc->ethercom.ec_if; 412 strcpy(ifp->if_xname, device_xname(self)); 413 ifp->if_softc = sc; 414 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 415 ifp->if_ioctl = bce_ioctl; 416 ifp->if_start = bce_start; 417 ifp->if_watchdog = bce_watchdog; 418 ifp->if_init = bce_init; 419 ifp->if_stop = bce_stop; 420 IFQ_SET_READY(&ifp->if_snd); 421 422 sc->ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 423 424 /* Initialize our media structures and probe the MII. */ 425 426 mii->mii_ifp = ifp; 427 mii->mii_readreg = bce_mii_read; 428 mii->mii_writereg = bce_mii_write; 429 mii->mii_statchg = bce_statchg; 430 431 sc->ethercom.ec_mii = mii; 432 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 433 mii_attach(sc->bce_dev, mii, 0xffffffff, MII_PHY_ANY, 434 MII_OFFSET_ANY, MIIF_FORCEANEG|MIIF_DOPAUSE); 435 if (LIST_FIRST(&mii->mii_phys) == NULL) { 436 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 437 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 438 } else 439 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 440 /* get the phy */ 441 sc->bce_phy = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 442 BCE_MAGIC_PHY) & 0x1f; 443 /* 444 * Enable activity led. 445 * XXX This should be in a phy driver, but not currently. 446 */ 447 bce_mii_read(sc->bce_dev, 1, 26, &phyval); 448 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 449 phyval & 0x7fff); /* MAGIC */ 450 /* enable traffic meter led mode */ 451 bce_mii_read(sc->bce_dev, 1, 27, &phyval); 452 bce_mii_write(sc->bce_dev, 1, 27, /* MAGIC */ 453 phyval | (1 << 6)); /* MAGIC */ 454 455 /* Attach the interface */ 456 if_attach(ifp); 457 if_deferred_start_init(ifp, NULL); 458 sc->enaddr[0] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 459 BCE_MAGIC_ENET0); 460 sc->enaddr[1] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 461 BCE_MAGIC_ENET1); 462 sc->enaddr[2] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 463 BCE_MAGIC_ENET2); 464 sc->enaddr[3] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 465 BCE_MAGIC_ENET3); 466 sc->enaddr[4] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 467 BCE_MAGIC_ENET4); 468 sc->enaddr[5] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 469 BCE_MAGIC_ENET5); 470 aprint_normal_dev(self, "Ethernet address %s\n", 471 ether_sprintf(sc->enaddr)); 472 ether_ifattach(ifp, sc->enaddr); 473 rnd_attach_source(&sc->rnd_source, device_xname(self), 474 RND_TYPE_NET, RND_FLAG_DEFAULT); 475 callout_init(&sc->bce_timeout, 0); 476 callout_setfunc(&sc->bce_timeout, bce_tick, sc); 477 478 if (pmf_device_register(self, NULL, bce_resume)) 479 pmf_class_network_register(self, ifp); 480 else 481 aprint_error_dev(self, "couldn't establish power handler\n"); 482 } 483 484 /* handle media, and ethernet requests */ 485 static int 486 bce_ioctl(struct ifnet *ifp, u_long cmd, void *data) 487 { 488 int s, error; 489 490 s = splnet(); 491 error = ether_ioctl(ifp, cmd, data); 492 if (error == ENETRESET) { 493 /* change multicast list */ 494 error = 0; 495 } 496 497 /* Try to get more packets going. */ 498 bce_start(ifp); 499 500 splx(s); 501 return error; 502 } 503 504 /* Start packet transmission on the interface. */ 505 static void 506 bce_start(struct ifnet *ifp) 507 { 508 struct bce_softc *sc = ifp->if_softc; 509 struct mbuf *m0; 510 bus_dmamap_t dmamap; 511 int txstart; 512 int txsfree; 513 int newpkts = 0; 514 int error; 515 516 /* 517 * do not start another if currently transmitting, and more 518 * descriptors(tx slots) are needed for next packet. 519 */ 520 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 521 return; 522 523 /* determine number of descriptors available */ 524 if (sc->bce_txsnext >= sc->bce_txin) 525 txsfree = BCE_NTXDESC - 1 + sc->bce_txin - sc->bce_txsnext; 526 else 527 txsfree = sc->bce_txin - sc->bce_txsnext - 1; 528 529 /* 530 * Loop through the send queue, setting up transmit descriptors 531 * until we drain the queue, or use up all available transmit 532 * descriptors. 533 */ 534 while (txsfree > 0) { 535 int seg; 536 537 /* Grab a packet off the queue. */ 538 IFQ_POLL(&ifp->if_snd, m0); 539 if (m0 == NULL) 540 break; 541 542 /* get the transmit slot dma map */ 543 dmamap = sc->bce_cdata.bce_tx_map[sc->bce_txsnext]; 544 545 /* 546 * Load the DMA map. If this fails, the packet either 547 * didn't fit in the alloted number of segments, or we 548 * were short on resources. If the packet will not fit, 549 * it will be dropped. If short on resources, it will 550 * be tried again later. 551 */ 552 error = bus_dmamap_load_mbuf(sc->bce_dmatag, dmamap, m0, 553 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 554 if (error == EFBIG) { 555 aprint_error_dev(sc->bce_dev, 556 "Tx packet consumes too many DMA segments, " 557 "dropping...\n"); 558 IFQ_DEQUEUE(&ifp->if_snd, m0); 559 m_freem(m0); 560 if_statinc(ifp, if_oerrors); 561 continue; 562 } else if (error) { 563 /* short on resources, come back later */ 564 aprint_error_dev(sc->bce_dev, 565 "unable to load Tx buffer, error = %d\n", 566 error); 567 break; 568 } 569 /* If not enough descriptors available, try again later */ 570 if (dmamap->dm_nsegs > txsfree) { 571 ifp->if_flags |= IFF_OACTIVE; 572 bus_dmamap_unload(sc->bce_dmatag, dmamap); 573 break; 574 } 575 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 576 577 /* So take it off the queue */ 578 IFQ_DEQUEUE(&ifp->if_snd, m0); 579 580 /* save the pointer so it can be freed later */ 581 sc->bce_cdata.bce_tx_chain[sc->bce_txsnext] = m0; 582 583 /* Sync the data DMA map. */ 584 bus_dmamap_sync(sc->bce_dmatag, dmamap, 0, dmamap->dm_mapsize, 585 BUS_DMASYNC_PREWRITE); 586 587 /* Initialize the transmit descriptor(s). */ 588 txstart = sc->bce_txsnext; 589 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 590 uint32_t ctrl; 591 592 ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK; 593 if (seg == 0) 594 ctrl |= CTRL_SOF; 595 if (seg == dmamap->dm_nsegs - 1) 596 ctrl |= CTRL_EOF; 597 if (sc->bce_txsnext == BCE_NTXDESC - 1) 598 ctrl |= CTRL_EOT; 599 ctrl |= CTRL_IOC; 600 sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl); 601 sc->bce_tx_ring[sc->bce_txsnext].addr = 602 htole32(dmamap->dm_segs[seg].ds_addr + 0x40000000); /* MAGIC */ 603 if (sc->bce_txsnext + 1 > BCE_NTXDESC - 1) 604 sc->bce_txsnext = 0; 605 else 606 sc->bce_txsnext++; 607 txsfree--; 608 } 609 /* sync descriptors being used */ 610 if ( sc->bce_txsnext > txstart ) { 611 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 612 PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart, 613 sizeof(struct bce_dma_slot) * dmamap->dm_nsegs, 614 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 615 } else { 616 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 617 PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart, 618 sizeof(struct bce_dma_slot) * 619 (BCE_NTXDESC - txstart), 620 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 621 if ( sc->bce_txsnext != 0 ) { 622 bus_dmamap_sync(sc->bce_dmatag, 623 sc->bce_ring_map, PAGE_SIZE, 624 sc->bce_txsnext * 625 sizeof(struct bce_dma_slot), 626 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 627 } 628 } 629 630 /* Give the packet to the chip. */ 631 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_DPTR, 632 sc->bce_txsnext * sizeof(struct bce_dma_slot)); 633 634 newpkts++; 635 636 /* Pass the packet to any BPF listeners. */ 637 bpf_mtap(ifp, m0, BPF_D_OUT); 638 } 639 if (txsfree == 0) { 640 /* No more slots left; notify upper layer. */ 641 ifp->if_flags |= IFF_OACTIVE; 642 } 643 if (newpkts) { 644 /* Set a watchdog timer in case the chip flakes out. */ 645 ifp->if_timer = 5; 646 } 647 } 648 649 /* Watchdog timer handler. */ 650 static void 651 bce_watchdog(struct ifnet *ifp) 652 { 653 struct bce_softc *sc = ifp->if_softc; 654 655 device_printf(sc->bce_dev, "device timeout\n"); 656 if_statinc(ifp, if_oerrors); 657 658 (void) bce_init(ifp); 659 660 /* Try to get more packets going. */ 661 bce_start(ifp); 662 } 663 664 int 665 bce_intr(void *xsc) 666 { 667 struct bce_softc *sc; 668 struct ifnet *ifp; 669 uint32_t intstatus; 670 int wantinit; 671 int handled = 0; 672 673 sc = xsc; 674 ifp = &sc->ethercom.ec_if; 675 676 for (wantinit = 0; wantinit == 0;) { 677 intstatus = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 678 BCE_INT_STS); 679 680 /* ignore if not ours, or unsolicited interrupts */ 681 intstatus &= sc->bce_intmask; 682 if (intstatus == 0) 683 break; 684 685 handled = 1; 686 687 /* Ack interrupt */ 688 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS, 689 intstatus); 690 691 /* Receive interrupts. */ 692 if (intstatus & I_RI) 693 bce_rxintr(sc); 694 /* Transmit interrupts. */ 695 if (intstatus & I_XI) 696 bce_txintr(sc); 697 /* Error interrupts */ 698 if (intstatus & ~(I_RI | I_XI)) { 699 const char *msg = NULL; 700 if (intstatus & I_XU) 701 msg = "transmit fifo underflow"; 702 if (intstatus & I_RO) { 703 msg = "receive fifo overflow"; 704 if_statinc(ifp, if_ierrors); 705 } 706 if (intstatus & I_RU) 707 msg = "receive descriptor underflow"; 708 if (intstatus & I_DE) 709 msg = "descriptor protocol error"; 710 if (intstatus & I_PD) 711 msg = "data error"; 712 if (intstatus & I_PC) 713 msg = "descriptor error"; 714 if (intstatus & I_TO) 715 msg = "general purpose timeout"; 716 if (msg != NULL) 717 aprint_error_dev(sc->bce_dev, "%s\n", msg); 718 wantinit = 1; 719 } 720 } 721 722 if (handled) { 723 if (wantinit) 724 bce_init(ifp); 725 rnd_add_uint32(&sc->rnd_source, intstatus); 726 /* Try to get more packets going. */ 727 if_schedule_deferred_start(ifp); 728 } 729 return (handled); 730 } 731 732 /* Receive interrupt handler */ 733 void 734 bce_rxintr(struct bce_softc *sc) 735 { 736 struct ifnet *ifp = &sc->ethercom.ec_if; 737 struct rx_pph *pph; 738 struct mbuf *m; 739 int curr; 740 int len; 741 int i; 742 743 /* get pointer to active receive slot */ 744 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS) 745 & RS_CD_MASK; 746 curr = curr / sizeof(struct bce_dma_slot); 747 if (curr >= BCE_NRXDESC) 748 curr = BCE_NRXDESC - 1; 749 750 /* process packets up to but not current packet being worked on */ 751 for (i = sc->bce_rxin; i != curr; 752 i + 1 > BCE_NRXDESC - 1 ? i = 0 : i++) { 753 /* complete any post dma memory ops on packet */ 754 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i], 0, 755 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 756 BUS_DMASYNC_POSTREAD); 757 758 /* 759 * If the packet had an error, simply recycle the buffer, 760 * resetting the len, and flags. 761 */ 762 pph = mtod(sc->bce_cdata.bce_rx_chain[i], struct rx_pph *); 763 if (pph->flags & (RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)) { 764 if_statinc(ifp, if_ierrors); 765 pph->len = 0; 766 pph->flags = 0; 767 continue; 768 } 769 /* receive the packet */ 770 len = pph->len; 771 if (len == 0) 772 continue; /* no packet if empty */ 773 pph->len = 0; 774 pph->flags = 0; 775 /* bump past pre header to packet */ 776 sc->bce_cdata.bce_rx_chain[i]->m_data += 30; /* MAGIC */ 777 778 /* 779 * The chip includes the CRC with every packet. Trim 780 * it off here. 781 */ 782 len -= ETHER_CRC_LEN; 783 784 /* 785 * If the packet is small enough to fit in a 786 * single header mbuf, allocate one and copy 787 * the data into it. This greatly reduces 788 * memory consumption when receiving lots 789 * of small packets. 790 * 791 * Otherwise, add a new buffer to the receive 792 * chain. If this fails, drop the packet and 793 * recycle the old buffer. 794 */ 795 if (len <= (MHLEN - 2)) { 796 MGETHDR(m, M_DONTWAIT, MT_DATA); 797 if (m == NULL) 798 goto dropit; 799 m->m_data += 2; 800 memcpy(mtod(m, void *), 801 mtod(sc->bce_cdata.bce_rx_chain[i], void *), len); 802 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; /* MAGIC */ 803 } else { 804 m = sc->bce_cdata.bce_rx_chain[i]; 805 if (bce_add_rxbuf(sc, i) != 0) { 806 dropit: 807 if_statinc(ifp, if_ierrors); 808 /* continue to use old buffer */ 809 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; 810 bus_dmamap_sync(sc->bce_dmatag, 811 sc->bce_cdata.bce_rx_map[i], 0, 812 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 813 BUS_DMASYNC_PREREAD); 814 continue; 815 } 816 } 817 818 m_set_rcvif(m, ifp); 819 m->m_pkthdr.len = m->m_len = len; 820 821 /* Pass it on. */ 822 if_percpuq_enqueue(ifp->if_percpuq, m); 823 824 /* re-check current in case it changed */ 825 curr = (bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 826 BCE_DMA_RXSTATUS) & RS_CD_MASK) / 827 sizeof(struct bce_dma_slot); 828 if (curr >= BCE_NRXDESC) 829 curr = BCE_NRXDESC - 1; 830 } 831 sc->bce_rxin = curr; 832 } 833 834 /* Transmit interrupt handler */ 835 void 836 bce_txintr(struct bce_softc *sc) 837 { 838 struct ifnet *ifp = &sc->ethercom.ec_if; 839 int curr; 840 int i; 841 842 ifp->if_flags &= ~IFF_OACTIVE; 843 844 /* 845 * Go through the Tx list and free mbufs for those 846 * frames which have been transmitted. 847 */ 848 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXSTATUS) & 849 RS_CD_MASK; 850 curr = curr / sizeof(struct bce_dma_slot); 851 if (curr >= BCE_NTXDESC) 852 curr = BCE_NTXDESC - 1; 853 for (i = sc->bce_txin; i != curr; 854 i + 1 > BCE_NTXDESC - 1 ? i = 0 : i++) { 855 /* do any post dma memory ops on transmit data */ 856 if (sc->bce_cdata.bce_tx_chain[i] == NULL) 857 continue; 858 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i], 0, 859 sc->bce_cdata.bce_tx_map[i]->dm_mapsize, 860 BUS_DMASYNC_POSTWRITE); 861 bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i]); 862 m_freem(sc->bce_cdata.bce_tx_chain[i]); 863 sc->bce_cdata.bce_tx_chain[i] = NULL; 864 if_statinc(ifp, if_opackets); 865 } 866 sc->bce_txin = curr; 867 868 /* 869 * If there are no more pending transmissions, cancel the watchdog 870 * timer 871 */ 872 if (sc->bce_txsnext == sc->bce_txin) 873 ifp->if_timer = 0; 874 } 875 876 /* initialize the interface */ 877 static int 878 bce_init(struct ifnet *ifp) 879 { 880 struct bce_softc *sc = ifp->if_softc; 881 uint32_t reg_win; 882 int error; 883 int i; 884 885 /* Cancel any pending I/O. */ 886 bce_stop(ifp, 0); 887 888 /* enable pci inerrupts, bursts, and prefetch */ 889 890 /* remap the pci registers to the Sonics config registers */ 891 892 /* save the current map, so it can be restored */ 893 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 894 BCE_REG_WIN); 895 896 /* set register window to Sonics registers */ 897 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 898 BCE_SONICS_WIN); 899 900 /* enable SB to PCI interrupt */ 901 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 902 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) | 903 SBIV_ENET0); 904 905 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 906 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 907 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) | 908 SBTOPCI_PREF | SBTOPCI_BURST); 909 910 /* restore to ethernet register space */ 911 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 912 reg_win); 913 914 /* Reset the chip to a known state. */ 915 bce_reset(sc); 916 917 /* Initialize transmit descriptors */ 918 memset(sc->bce_tx_ring, 0, BCE_NTXDESC * sizeof(struct bce_dma_slot)); 919 sc->bce_txsnext = 0; 920 sc->bce_txin = 0; 921 922 /* enable crc32 generation and set proper LED modes */ 923 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 924 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) | 925 BCE_EMC_CRC32_ENAB | BCE_EMC_LED); 926 927 /* reset or clear powerdown control bit */ 928 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 929 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) & 930 ~BCE_EMC_PDOWN); 931 932 /* setup DMA interrupt control */ 933 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1 << 24); /* MAGIC */ 934 935 /* setup packet filter */ 936 bce_set_filter(ifp); 937 938 /* set max frame length, account for possible vlan tag */ 939 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_MAX, 940 ETHER_MAX_LEN + 32); 941 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_MAX, 942 ETHER_MAX_LEN + 32); 943 944 /* set tx watermark */ 945 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_WATER, 56); 946 947 /* enable transmit */ 948 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, XC_XE); 949 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXADDR, 950 sc->bce_ring_map->dm_segs[0].ds_addr + PAGE_SIZE + 0x40000000); /* MAGIC */ 951 952 /* 953 * Give the receive ring to the chip, and 954 * start the receive DMA engine. 955 */ 956 sc->bce_rxin = 0; 957 958 /* clear the rx descriptor ring */ 959 memset(sc->bce_rx_ring, 0, BCE_NRXDESC * sizeof(struct bce_dma_slot)); 960 /* enable receive */ 961 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 962 30 << 1 | 1); /* MAGIC */ 963 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXADDR, 964 sc->bce_ring_map->dm_segs[0].ds_addr + 0x40000000); /* MAGIC */ 965 966 /* Initialize receive descriptors */ 967 for (i = 0; i < BCE_NRXDESC; i++) { 968 if (sc->bce_cdata.bce_rx_chain[i] == NULL) { 969 if ((error = bce_add_rxbuf(sc, i)) != 0) { 970 aprint_error_dev(sc->bce_dev, 971 "unable to allocate or map rx(%d) " 972 "mbuf, error = %d\n", i, error); 973 bce_rxdrain(sc); 974 return (error); 975 } 976 } else 977 BCE_INIT_RXDESC(sc, i); 978 } 979 980 /* Enable interrupts */ 981 sc->bce_intmask = 982 I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO; 983 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 984 sc->bce_intmask); 985 986 /* start the receive dma */ 987 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR, 988 BCE_NRXDESC * sizeof(struct bce_dma_slot)); 989 990 /* set media */ 991 if ((error = ether_mediachange(ifp)) != 0) 992 return error; 993 994 /* turn on the ethernet mac */ 995 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 996 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 997 BCE_ENET_CTL) | EC_EE); 998 999 /* start timer */ 1000 callout_schedule(&sc->bce_timeout, hz); 1001 1002 /* mark as running, and no outputs active */ 1003 ifp->if_flags |= IFF_RUNNING; 1004 ifp->if_flags &= ~IFF_OACTIVE; 1005 1006 return 0; 1007 } 1008 1009 /* add a mac address to packet filter */ 1010 void 1011 bce_add_mac(struct bce_softc *sc, uint8_t *mac, u_long idx) 1012 { 1013 int i; 1014 uint32_t rval; 1015 1016 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_LOW, 1017 (uint32_t)mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]); 1018 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_HI, 1019 mac[0] << 8 | mac[1] | 0x10000); /* MAGIC */ 1020 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1021 idx << 16 | 8); /* MAGIC */ 1022 /* wait for write to complete */ 1023 for (i = 0; i < 100; i++) { 1024 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1025 BCE_FILT_CTL); 1026 if (!(rval & 0x80000000)) /* MAGIC */ 1027 break; 1028 delay(10); 1029 } 1030 if (i == 100) { 1031 aprint_error_dev(sc->bce_dev, 1032 "timed out writing pkt filter ctl\n"); 1033 } 1034 } 1035 1036 /* Add a receive buffer to the indiciated descriptor. */ 1037 static int 1038 bce_add_rxbuf(struct bce_softc *sc, int idx) 1039 { 1040 struct mbuf *m; 1041 int error; 1042 1043 MGETHDR(m, M_DONTWAIT, MT_DATA); 1044 if (m == NULL) 1045 return (ENOBUFS); 1046 1047 MCLGET(m, M_DONTWAIT); 1048 if ((m->m_flags & M_EXT) == 0) { 1049 m_freem(m); 1050 return (ENOBUFS); 1051 } 1052 if (sc->bce_cdata.bce_rx_chain[idx] != NULL) 1053 bus_dmamap_unload(sc->bce_dmatag, 1054 sc->bce_cdata.bce_rx_map[idx]); 1055 1056 sc->bce_cdata.bce_rx_chain[idx] = m; 1057 1058 error = bus_dmamap_load(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 1059 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1060 BUS_DMA_READ | BUS_DMA_NOWAIT); 1061 if (error) 1062 return (error); 1063 1064 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 0, 1065 sc->bce_cdata.bce_rx_map[idx]->dm_mapsize, BUS_DMASYNC_PREREAD); 1066 1067 BCE_INIT_RXDESC(sc, idx); 1068 1069 return (0); 1070 1071 } 1072 1073 /* Drain the receive queue. */ 1074 static void 1075 bce_rxdrain(struct bce_softc *sc) 1076 { 1077 int i; 1078 1079 for (i = 0; i < BCE_NRXDESC; i++) { 1080 if (sc->bce_cdata.bce_rx_chain[i] != NULL) { 1081 bus_dmamap_unload(sc->bce_dmatag, 1082 sc->bce_cdata.bce_rx_map[i]); 1083 m_freem(sc->bce_cdata.bce_rx_chain[i]); 1084 sc->bce_cdata.bce_rx_chain[i] = NULL; 1085 } 1086 } 1087 } 1088 1089 /* Stop transmission on the interface */ 1090 static void 1091 bce_stop(struct ifnet *ifp, int disable) 1092 { 1093 struct bce_softc *sc = ifp->if_softc; 1094 int i; 1095 uint32_t val; 1096 1097 /* Stop the 1 second timer */ 1098 callout_stop(&sc->bce_timeout); 1099 1100 /* Down the MII. */ 1101 mii_down(&sc->bce_mii); 1102 1103 /* Disable interrupts. */ 1104 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0); 1105 sc->bce_intmask = 0; 1106 delay(10); 1107 1108 /* Disable emac */ 1109 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED); 1110 for (i = 0; i < 200; i++) { 1111 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1112 BCE_ENET_CTL); 1113 if (!(val & EC_ED)) 1114 break; 1115 delay(10); 1116 } 1117 1118 /* Stop the DMA */ 1119 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 0); 1120 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1121 delay(10); 1122 1123 /* Release any queued transmit buffers. */ 1124 for (i = 0; i < BCE_NTXDESC; i++) { 1125 if (sc->bce_cdata.bce_tx_chain[i] != NULL) { 1126 bus_dmamap_unload(sc->bce_dmatag, 1127 sc->bce_cdata.bce_tx_map[i]); 1128 m_freem(sc->bce_cdata.bce_tx_chain[i]); 1129 sc->bce_cdata.bce_tx_chain[i] = NULL; 1130 } 1131 } 1132 1133 /* Mark the interface down and cancel the watchdog timer. */ 1134 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1135 ifp->if_timer = 0; 1136 1137 /* drain receive queue */ 1138 if (disable) 1139 bce_rxdrain(sc); 1140 } 1141 1142 /* reset the chip */ 1143 static void 1144 bce_reset(struct bce_softc *sc) 1145 { 1146 uint32_t val; 1147 uint32_t sbval; 1148 int i; 1149 1150 /* if SB core is up */ 1151 sbval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1152 BCE_SBTMSTATELOW); 1153 if ((sbval & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK) { 1154 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1155 0); 1156 1157 /* disable emac */ 1158 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1159 EC_ED); 1160 for (i = 0; i < 200; i++) { 1161 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1162 BCE_ENET_CTL); 1163 if (!(val & EC_ED)) 1164 break; 1165 delay(10); 1166 } 1167 if (i == 200) { 1168 aprint_error_dev(sc->bce_dev, 1169 "timed out disabling ethernet mac\n"); 1170 } 1171 1172 /* reset the dma engines */ 1173 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1174 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS); 1175 /* if error on receive, wait to go idle */ 1176 if (val & RS_ERROR) { 1177 for (i = 0; i < 100; i++) { 1178 val = bus_space_read_4(sc->bce_btag, 1179 sc->bce_bhandle, BCE_DMA_RXSTATUS); 1180 if (val & RS_DMA_IDLE) 1181 break; 1182 delay(10); 1183 } 1184 if (i == 100) { 1185 aprint_error_dev(sc->bce_dev, 1186 "receive dma did not go idle after" 1187 " error\n"); 1188 } 1189 } 1190 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1191 BCE_DMA_RXSTATUS, 0); 1192 1193 /* reset ethernet mac */ 1194 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1195 EC_ES); 1196 for (i = 0; i < 200; i++) { 1197 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1198 BCE_ENET_CTL); 1199 if (!(val & EC_ES)) 1200 break; 1201 delay(10); 1202 } 1203 if (i == 200) { 1204 aprint_error_dev(sc->bce_dev, 1205 "timed out resetting ethernet mac\n"); 1206 } 1207 } else { 1208 uint32_t reg_win; 1209 1210 /* remap the pci registers to the Sonics config registers */ 1211 1212 /* save the current map, so it can be restored */ 1213 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1214 BCE_REG_WIN); 1215 /* set register window to Sonics registers */ 1216 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1217 BCE_REG_WIN, BCE_SONICS_WIN); 1218 1219 /* enable SB to PCI interrupt */ 1220 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 1221 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1222 BCE_SBINTVEC) | 1223 SBIV_ENET0); 1224 1225 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 1226 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 1227 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1228 BCE_SPCI_TR2) | 1229 SBTOPCI_PREF | SBTOPCI_BURST); 1230 1231 /* restore to ethernet register space */ 1232 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 1233 reg_win); 1234 } 1235 1236 /* disable SB core if not in reset */ 1237 if (!(sbval & SBTML_RESET)) { 1238 1239 /* set the reject bit */ 1240 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1241 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_CLK); 1242 for (i = 0; i < 200; i++) { 1243 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1244 BCE_SBTMSTATELOW); 1245 if (val & SBTML_REJ) 1246 break; 1247 delay(1); 1248 } 1249 if (i == 200) { 1250 aprint_error_dev(sc->bce_dev, 1251 "while resetting core, reject did not set\n"); 1252 } 1253 /* wait until busy is clear */ 1254 for (i = 0; i < 200; i++) { 1255 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1256 BCE_SBTMSTATEHI); 1257 if (!(val & 0x4)) 1258 break; 1259 delay(1); 1260 } 1261 if (i == 200) { 1262 aprint_error_dev(sc->bce_dev, 1263 "while resetting core, busy did not clear\n"); 1264 } 1265 /* set reset and reject while enabling the clocks */ 1266 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1267 BCE_SBTMSTATELOW, 1268 SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET); 1269 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1270 BCE_SBTMSTATELOW); 1271 delay(10); 1272 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1273 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_RESET); 1274 delay(1); 1275 } 1276 /* enable clock */ 1277 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1278 SBTML_FGC | SBTML_CLK | SBTML_RESET); 1279 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1280 delay(1); 1281 1282 /* clear any error bits that may be on */ 1283 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI); 1284 if (val & 1) 1285 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI, 1286 0); 1287 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE); 1288 if (val & SBIM_MAGIC_ERRORBITS) 1289 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE, 1290 val & ~SBIM_MAGIC_ERRORBITS); 1291 1292 /* clear reset and allow it to propagate throughout the core */ 1293 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1294 SBTML_FGC | SBTML_CLK); 1295 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1296 delay(1); 1297 1298 /* leave clock enabled */ 1299 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1300 SBTML_CLK); 1301 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1302 delay(1); 1303 1304 /* initialize MDC preamble, frequency */ 1305 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_CTL, 0x8d); /* MAGIC */ 1306 1307 /* enable phy, differs for internal, and external */ 1308 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL); 1309 if (!(val & BCE_DC_IP)) { 1310 /* select external phy */ 1311 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_EP); 1312 } else if (val & BCE_DC_ER) { /* internal, clear reset bit if on */ 1313 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL, 1314 val & ~BCE_DC_ER); 1315 delay(100); 1316 } 1317 } 1318 1319 /* Set up the receive filter. */ 1320 void 1321 bce_set_filter(struct ifnet *ifp) 1322 { 1323 struct bce_softc *sc = ifp->if_softc; 1324 1325 if (ifp->if_flags & IFF_PROMISC) { 1326 ifp->if_flags |= IFF_ALLMULTI; 1327 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1328 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) 1329 | ERC_PE); 1330 } else { 1331 ifp->if_flags &= ~IFF_ALLMULTI; 1332 1333 /* turn off promiscuous */ 1334 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1335 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1336 BCE_RX_CTL) & ~ERC_PE); 1337 1338 /* enable/disable broadcast */ 1339 if (ifp->if_flags & IFF_BROADCAST) 1340 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1341 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1342 sc->bce_bhandle, BCE_RX_CTL) & ~ERC_DB); 1343 else 1344 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1345 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1346 sc->bce_bhandle, BCE_RX_CTL) | ERC_DB); 1347 1348 /* disable the filter */ 1349 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1350 0); 1351 1352 /* add our own address */ 1353 bce_add_mac(sc, sc->enaddr, 0); 1354 1355 /* for now accept all multicast */ 1356 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1357 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) | 1358 ERC_AM); 1359 ifp->if_flags |= IFF_ALLMULTI; 1360 1361 /* enable the filter */ 1362 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1363 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1364 BCE_FILT_CTL) | 1); 1365 } 1366 } 1367 1368 static bool 1369 bce_resume(device_t self, const pmf_qual_t *qual) 1370 { 1371 struct bce_softc *sc = device_private(self); 1372 1373 bce_reset(sc); 1374 1375 return true; 1376 } 1377 1378 /* Read a PHY register on the MII. */ 1379 int 1380 bce_mii_read(device_t self, int phy, int reg, uint16_t *val) 1381 { 1382 struct bce_softc *sc = device_private(self); 1383 int i; 1384 uint32_t data; 1385 1386 /* clear mii_int */ 1387 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR); 1388 1389 /* Read the PHY register */ 1390 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1391 (MII_COMMAND_READ << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1392 (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */ 1393 1394 for (i = 0; i < BCE_TIMEOUT; i++) { 1395 data = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1396 BCE_MI_STS); 1397 if (data & BCE_MIINTR) 1398 break; 1399 delay(10); 1400 } 1401 data = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1402 if (i == BCE_TIMEOUT) { 1403 aprint_error_dev(sc->bce_dev, 1404 "PHY read timed out reading phy %d, reg %d, val = " 1405 "0x%08x\n", phy, reg, data); 1406 return ETIMEDOUT; 1407 } 1408 *val = data & BCE_MICOMM_DATA; 1409 return 0; 1410 } 1411 1412 /* Write a PHY register on the MII */ 1413 int 1414 bce_mii_write(device_t self, int phy, int reg, uint16_t val) 1415 { 1416 struct bce_softc *sc = device_private(self); 1417 int i; 1418 uint32_t data; 1419 1420 /* clear mii_int */ 1421 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, 1422 BCE_MIINTR); 1423 1424 /* Write the PHY register */ 1425 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1426 (MII_COMMAND_WRITE << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1427 (MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) | /* MAGIC */ 1428 BCE_MIPHY(phy) | BCE_MIREG(reg)); 1429 1430 /* wait for write to complete */ 1431 for (i = 0; i < BCE_TIMEOUT; i++) { 1432 data = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1433 BCE_MI_STS); 1434 if (data & BCE_MIINTR) 1435 break; 1436 delay(10); 1437 } 1438 if (i == BCE_TIMEOUT) { 1439 aprint_error_dev(sc->bce_dev, 1440 "PHY timed out writing phy %d, reg %d, val = 0x%04hx\n", 1441 phy, reg, val); 1442 return ETIMEDOUT; 1443 } 1444 1445 return 0; 1446 } 1447 1448 /* sync hardware duplex mode to software state */ 1449 void 1450 bce_statchg(struct ifnet *ifp) 1451 { 1452 struct bce_softc *sc = ifp->if_softc; 1453 uint32_t reg; 1454 uint16_t phyval; 1455 1456 /* if needed, change register to match duplex mode */ 1457 reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL); 1458 if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD)) 1459 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1460 reg | EXC_FD); 1461 else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD) 1462 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1463 reg & ~EXC_FD); 1464 1465 /* 1466 * Enable activity led. 1467 * XXX This should be in a phy driver, but not currently. 1468 */ 1469 bce_mii_read(sc->bce_dev, 1, 26, &phyval); 1470 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 1471 phyval & 0x7fff); /* MAGIC */ 1472 /* enable traffic meter led mode */ 1473 bce_mii_read(sc->bce_dev, 1, 27, &phyval); 1474 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 1475 phyval | (1 << 6)); /* MAGIC */ 1476 } 1477 1478 /* One second timer, checks link status */ 1479 static void 1480 bce_tick(void *v) 1481 { 1482 struct bce_softc *sc = v; 1483 int s; 1484 1485 s = splnet(); 1486 mii_tick(&sc->bce_mii); 1487 splx(s); 1488 1489 callout_schedule(&sc->bce_timeout, hz); 1490 } 1491
Indexes created Tue Sep 30 17:09:57 GMT 2025