if_bce.c revision 1.8
1 /* $NetBSD: if_bce.c,v 1.8 2005/02/02 13:26:06 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Clifford Wright. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Broadcom BCM440x 10/100 ethernet (broadcom.com) 32 * SiliconBackplane is technology from Sonics, Inc.(sonicsinc.com) 33 * 34 * Cliff Wright cliff (at) snipe444.org 35 */ 36 37 #include "bpfilter.h" 38 #include "vlan.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/callout.h> 43 #include <sys/sockio.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/device.h> 48 #include <sys/socket.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 #include <net/if_ether.h> 54 55 #if NBPFILTER > 0 56 #include <net/bpf.h> 57 #endif 58 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 #include <dev/mii/miidevs.h> 66 #include <dev/mii/brgphyreg.h> 67 68 #include <dev/pci/if_bcereg.h> 69 70 #include <uvm/uvm_extern.h> 71 72 /* transmit buffer max frags allowed */ 73 #define BCE_NTXFRAGS 16 74 75 /* ring descriptor */ 76 struct bce_dma_slot { 77 u_int32_t ctrl; 78 u_int32_t addr; 79 }; 80 #define CTRL_BC_MASK 0x1fff /* buffer byte count */ 81 #define CTRL_EOT 0x10000000 /* end of descriptor table */ 82 #define CTRL_IOC 0x20000000 /* interrupt on completion */ 83 #define CTRL_EOF 0x40000000 /* end of frame */ 84 #define CTRL_SOF 0x80000000 /* start of frame */ 85 86 /* Packet status is returned in a pre-packet header */ 87 struct rx_pph { 88 u_int16_t len; 89 u_int16_t flags; 90 u_int16_t pad[12]; 91 }; 92 93 /* packet status flags bits */ 94 #define RXF_NO 0x8 /* odd number of nibbles */ 95 #define RXF_RXER 0x4 /* receive symbol error */ 96 #define RXF_CRC 0x2 /* crc error */ 97 #define RXF_OV 0x1 /* fifo overflow */ 98 99 /* number of descriptors used in a ring */ 100 #define BCE_NRXDESC 128 101 #define BCE_NTXDESC 128 102 103 /* 104 * Mbuf pointers. We need these to keep track of the virtual addresses 105 * of our mbuf chains since we can only convert from physical to virtual, 106 * not the other way around. 107 */ 108 struct bce_chain_data { 109 struct mbuf *bce_tx_chain[BCE_NTXDESC]; 110 struct mbuf *bce_rx_chain[BCE_NRXDESC]; 111 bus_dmamap_t bce_tx_map[BCE_NTXDESC]; 112 bus_dmamap_t bce_rx_map[BCE_NRXDESC]; 113 }; 114 115 #define BCE_TIMEOUT 100 /* # 10us for mii read/write */ 116 117 struct bce_softc { 118 struct device bce_dev; 119 bus_space_tag_t bce_btag; 120 bus_space_handle_t bce_bhandle; 121 bus_dma_tag_t bce_dmatag; 122 struct ethercom ethercom; /* interface info */ 123 void *bce_intrhand; 124 struct pci_attach_args bce_pa; 125 struct mii_data bce_mii; 126 u_int32_t bce_phy; /* eeprom indicated phy */ 127 struct ifmedia bce_ifmedia; /* media info *//* Check */ 128 u_int8_t enaddr[ETHER_ADDR_LEN]; 129 struct bce_dma_slot *bce_rx_ring; /* receive ring */ 130 struct bce_dma_slot *bce_tx_ring; /* transmit ring */ 131 struct bce_chain_data bce_cdata; /* mbufs */ 132 bus_dmamap_t bce_ring_map; 133 u_int32_t bce_intmask; /* current intr mask */ 134 u_int32_t bce_rxin; /* last rx descriptor seen */ 135 u_int32_t bce_txin; /* last tx descriptor seen */ 136 int bce_txsfree; /* no. tx slots available */ 137 int bce_txsnext; /* next available tx slot */ 138 struct callout bce_timeout; 139 }; 140 141 /* for ring descriptors */ 142 #define BCE_RXBUF_LEN (MCLBYTES - 4) 143 #define BCE_INIT_RXDESC(sc, x) \ 144 do { \ 145 struct bce_dma_slot *__bced = &sc->bce_rx_ring[x]; \ 146 \ 147 *mtod(sc->bce_cdata.bce_rx_chain[x], u_int32_t *) = 0; \ 148 __bced->addr = \ 149 htole32(sc->bce_cdata.bce_rx_map[x]->dm_segs[0].ds_addr \ 150 + 0x40000000); \ 151 if (x != (BCE_NRXDESC - 1)) \ 152 __bced->ctrl = htole32(BCE_RXBUF_LEN); \ 153 else \ 154 __bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT); \ 155 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, \ 156 sizeof(struct bce_dma_slot) * x, \ 157 sizeof(struct bce_dma_slot), \ 158 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 159 } while (/* CONSTCOND */ 0) 160 161 static int bce_probe(struct device *, struct cfdata *, void *); 162 static void bce_attach(struct device *, struct device *, void *); 163 static int bce_ioctl(struct ifnet *, u_long, caddr_t); 164 static void bce_start(struct ifnet *); 165 static void bce_watchdog(struct ifnet *); 166 static int bce_intr(void *); 167 static void bce_rxintr(struct bce_softc *); 168 static void bce_txintr(struct bce_softc *); 169 static int bce_init(struct ifnet *); 170 static void bce_add_mac(struct bce_softc *, u_int8_t *, unsigned long); 171 static int bce_add_rxbuf(struct bce_softc *, int); 172 static void bce_rxdrain(struct bce_softc *); 173 static void bce_stop(struct ifnet *, int); 174 static void bce_reset(struct bce_softc *); 175 static void bce_set_filter(struct ifnet *); 176 static int bce_mii_read(struct device *, int, int); 177 static void bce_mii_write(struct device *, int, int, int); 178 static void bce_statchg(struct device *); 179 static int bce_mediachange(struct ifnet *); 180 static void bce_mediastatus(struct ifnet *, struct ifmediareq *); 181 static void bce_tick(void *); 182 183 #define BCE_DEBUG 184 #ifdef BCE_DEBUG 185 #define DPRINTF(x) do { \ 186 if (bcedebug) \ 187 printf x; \ 188 } while (/* CONSTCOND */ 0) 189 #define DPRINTFN(n,x) do { \ 190 if (bcedebug >= (n)) \ 191 printf x; \ 192 } while (/* CONSTCOND */ 0) 193 int bcedebug = 0; 194 #else 195 #define DPRINTF(x) 196 #define DPRINTFN(n,x) 197 #endif 198 199 #if __NetBSD_Version__ >= 106080000 200 CFATTACH_DECL(bce, sizeof(struct bce_softc), 201 bce_probe, bce_attach, NULL, NULL); 202 #else 203 struct cfattach bce_ca = { 204 sizeof(struct bce_softc), bce_probe, bce_attach 205 }; 206 #endif 207 208 #if __NetBSD_Version__ >= 106120000 209 #define APRINT_ERROR aprint_error 210 #define APRINT_NORMAL aprint_normal 211 #else 212 #define APRINT_ERROR printf 213 #define APRINT_NORMAL printf 214 #endif 215 216 217 static const struct bce_product { 218 pci_vendor_id_t bp_vendor; 219 pci_product_id_t bp_product; 220 const char *bp_name; 221 } bce_products[] = { 222 { 223 PCI_VENDOR_BROADCOM, 224 PCI_PRODUCT_BROADCOM_BCM4401, 225 "Broadcom BCM4401 10/100 Ethernet" 226 }, 227 { 228 PCI_VENDOR_BROADCOM, 229 PCI_PRODUCT_BROADCOM_BCM4401_B0, 230 "Broadcom BCM4401-B0 10/100 Ethernet" 231 }, 232 { 233 234 0, 235 0, 236 NULL 237 }, 238 }; 239 240 static const struct bce_product * 241 bce_lookup(const struct pci_attach_args * pa) 242 { 243 const struct bce_product *bp; 244 245 for (bp = bce_products; bp->bp_name != NULL; bp++) { 246 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 247 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 248 return (bp); 249 } 250 251 return (NULL); 252 } 253 254 /* 255 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 256 * against drivers product list, and return its name if a match is found. 257 */ 258 static int 259 bce_probe(struct device *parent, struct cfdata *match, void *aux) 260 { 261 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 262 263 if (bce_lookup(pa) != NULL) 264 return (1); 265 266 return (0); 267 } 268 269 static void 270 bce_attach(struct device *parent, struct device *self, void *aux) 271 { 272 struct bce_softc *sc = (struct bce_softc *) self; 273 struct pci_attach_args *pa = aux; 274 const struct bce_product *bp; 275 pci_chipset_tag_t pc = pa->pa_pc; 276 pci_intr_handle_t ih; 277 const char *intrstr = NULL; 278 caddr_t kva; 279 bus_dma_segment_t seg; 280 int rseg; 281 u_int32_t command; 282 struct ifnet *ifp; 283 pcireg_t memtype; 284 bus_addr_t memaddr; 285 bus_size_t memsize; 286 int pmreg; 287 pcireg_t pmode; 288 int error; 289 int i; 290 291 bp = bce_lookup(pa); 292 KASSERT(bp != NULL); 293 294 sc->bce_pa = *pa; 295 sc->bce_dmatag = pa->pa_dmat; 296 297 #if __NetBSD_Version__ >= 106120000 298 aprint_naive(": Ethernet controller\n"); 299 #endif 300 APRINT_NORMAL(": %s\n", bp->bp_name); 301 302 /* 303 * Map control/status registers. 304 */ 305 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 306 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 307 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 308 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 309 310 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 311 APRINT_ERROR("%s: failed to enable memory mapping!\n", 312 sc->bce_dev.dv_xname); 313 return; 314 } 315 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BCE_PCI_BAR0); 316 switch (memtype) { 317 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 318 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 319 if (pci_mapreg_map(pa, BCE_PCI_BAR0, memtype, 0, &sc->bce_btag, 320 &sc->bce_bhandle, &memaddr, &memsize) == 0) 321 break; 322 default: 323 APRINT_ERROR("%s: unable to find mem space\n", 324 sc->bce_dev.dv_xname); 325 return; 326 } 327 328 /* Get it out of power save mode if needed. */ 329 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 330 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 331 if (pmode == 3) { 332 /* 333 * The card has lost all configuration data in 334 * this state, so punt. 335 */ 336 printf("%s: unable to wake up from power state D3\n", 337 sc->bce_dev.dv_xname); 338 return; 339 } 340 if (pmode != 0) { 341 printf("%s: waking up from power state D%d\n", 342 sc->bce_dev.dv_xname, pmode); 343 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 344 } 345 } 346 if (pci_intr_map(pa, &ih)) { 347 APRINT_ERROR("%s: couldn't map interrupt\n", 348 sc->bce_dev.dv_xname); 349 return; 350 } 351 intrstr = pci_intr_string(pc, ih); 352 353 sc->bce_intrhand = pci_intr_establish(pc, ih, IPL_NET, bce_intr, sc); 354 355 if (sc->bce_intrhand == NULL) { 356 APRINT_ERROR("%s: couldn't establish interrupt", 357 sc->bce_dev.dv_xname); 358 if (intrstr != NULL) 359 APRINT_NORMAL(" at %s", intrstr); 360 APRINT_NORMAL("\n"); 361 return; 362 } 363 APRINT_NORMAL("%s: interrupting at %s\n", 364 sc->bce_dev.dv_xname, intrstr); 365 366 /* reset the chip */ 367 bce_reset(sc); 368 369 /* 370 * Allocate DMA-safe memory for ring descriptors. 371 * The receive, and transmit rings can not share the same 372 * 4k space, however both are allocated at once here. 373 */ 374 /* 375 * XXX PAGE_SIZE is wasteful; we only need 1KB + 1KB, but 376 * due to the limition above. ?? 377 */ 378 if ((error = bus_dmamem_alloc(sc->bce_dmatag, 379 2 * PAGE_SIZE, PAGE_SIZE, 2 * PAGE_SIZE, 380 &seg, 1, &rseg, BUS_DMA_NOWAIT))) { 381 printf("%s: unable to alloc space for ring descriptors, " 382 "error = %d\n", sc->bce_dev.dv_xname, error); 383 return; 384 } 385 /* map ring space to kernel */ 386 if ((error = bus_dmamem_map(sc->bce_dmatag, &seg, rseg, 387 2 * PAGE_SIZE, &kva, BUS_DMA_NOWAIT))) { 388 printf("%s: unable to map DMA buffers, error = %d\n", 389 sc->bce_dev.dv_xname, error); 390 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 391 return; 392 } 393 /* create a dma map for the ring */ 394 if ((error = bus_dmamap_create(sc->bce_dmatag, 395 2 * PAGE_SIZE, 1, 2 * PAGE_SIZE, 0, BUS_DMA_NOWAIT, 396 &sc->bce_ring_map))) { 397 printf("%s: unable to create ring DMA map, error = %d\n", 398 sc->bce_dev.dv_xname, error); 399 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 400 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 401 return; 402 } 403 /* connect the ring space to the dma map */ 404 if (bus_dmamap_load(sc->bce_dmatag, sc->bce_ring_map, kva, 405 2 * PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) { 406 bus_dmamap_destroy(sc->bce_dmatag, sc->bce_ring_map); 407 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 408 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 409 return; 410 } 411 /* save the ring space in softc */ 412 sc->bce_rx_ring = (struct bce_dma_slot *) kva; 413 sc->bce_tx_ring = (struct bce_dma_slot *) (kva + PAGE_SIZE); 414 415 /* Create the transmit buffer DMA maps. */ 416 for (i = 0; i < BCE_NTXDESC; i++) { 417 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 418 BCE_NTXFRAGS, MCLBYTES, 0, 0, &sc->bce_cdata.bce_tx_map[i])) != 0) { 419 printf("%s: unable to create tx DMA map, error = %d\n", 420 sc->bce_dev.dv_xname, error); 421 } 422 sc->bce_cdata.bce_tx_chain[i] = NULL; 423 } 424 425 /* Create the receive buffer DMA maps. */ 426 for (i = 0; i < BCE_NRXDESC; i++) { 427 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 1, 428 MCLBYTES, 0, 0, &sc->bce_cdata.bce_rx_map[i])) != 0) { 429 printf("%s: unable to create rx DMA map, error = %d\n", 430 sc->bce_dev.dv_xname, error); 431 } 432 sc->bce_cdata.bce_rx_chain[i] = NULL; 433 } 434 435 /* Set up ifnet structure */ 436 ifp = &sc->ethercom.ec_if; 437 strcpy(ifp->if_xname, sc->bce_dev.dv_xname); 438 ifp->if_softc = sc; 439 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 440 ifp->if_ioctl = bce_ioctl; 441 ifp->if_start = bce_start; 442 ifp->if_watchdog = bce_watchdog; 443 ifp->if_init = bce_init; 444 ifp->if_stop = bce_stop; 445 IFQ_SET_READY(&ifp->if_snd); 446 447 /* Initialize our media structures and probe the MII. */ 448 449 sc->bce_mii.mii_ifp = ifp; 450 sc->bce_mii.mii_readreg = bce_mii_read; 451 sc->bce_mii.mii_writereg = bce_mii_write; 452 sc->bce_mii.mii_statchg = bce_statchg; 453 ifmedia_init(&sc->bce_mii.mii_media, 0, bce_mediachange, 454 bce_mediastatus); 455 mii_attach(&sc->bce_dev, &sc->bce_mii, 0xffffffff, MII_PHY_ANY, 456 MII_OFFSET_ANY, 0); 457 if (LIST_FIRST(&sc->bce_mii.mii_phys) == NULL) { 458 ifmedia_add(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 459 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE); 460 } else 461 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_AUTO); 462 /* get the phy */ 463 sc->bce_phy = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 464 BCE_MAGIC_PHY) & 0x1f; 465 /* 466 * Enable activity led. 467 * XXX This should be in a phy driver, but not currently. 468 */ 469 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 470 bce_mii_read((struct device *) sc, 1, 26) & 0x7fff); /* MAGIC */ 471 /* enable traffic meter led mode */ 472 bce_mii_write((struct device *) sc, 1, 27, /* MAGIC */ 473 bce_mii_read((struct device *) sc, 1, 27) | (1 << 6)); /* MAGIC */ 474 475 476 /* Attach the interface */ 477 if_attach(ifp); 478 sc->enaddr[0] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 479 BCE_MAGIC_ENET0); 480 sc->enaddr[1] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 481 BCE_MAGIC_ENET1); 482 sc->enaddr[2] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 483 BCE_MAGIC_ENET2); 484 sc->enaddr[3] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 485 BCE_MAGIC_ENET3); 486 sc->enaddr[4] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 487 BCE_MAGIC_ENET4); 488 sc->enaddr[5] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 489 BCE_MAGIC_ENET5); 490 printf("%s: Ethernet address %s\n", sc->bce_dev.dv_xname, 491 ether_sprintf(sc->enaddr)); 492 ether_ifattach(ifp, sc->enaddr); 493 callout_init(&sc->bce_timeout); 494 } 495 496 /* handle media, and ethernet requests */ 497 static int 498 bce_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 499 { 500 struct bce_softc *sc = ifp->if_softc; 501 struct ifreq *ifr = (struct ifreq *) data; 502 int s, error; 503 504 s = splnet(); 505 switch (cmd) { 506 case SIOCSIFMEDIA: 507 case SIOCGIFMEDIA: 508 error = ifmedia_ioctl(ifp, ifr, &sc->bce_mii.mii_media, cmd); 509 break; 510 default: 511 error = ether_ioctl(ifp, cmd, data); 512 if (error == ENETRESET) { 513 /* change multicast list */ 514 error = 0; 515 } 516 break; 517 } 518 519 /* Try to get more packets going. */ 520 bce_start(ifp); 521 522 splx(s); 523 return error; 524 } 525 526 /* Start packet transmission on the interface. */ 527 static void 528 bce_start(struct ifnet *ifp) 529 { 530 struct bce_softc *sc = ifp->if_softc; 531 struct mbuf *m0; 532 bus_dmamap_t dmamap; 533 int txstart; 534 int txsfree; 535 int newpkts = 0; 536 int error; 537 538 /* 539 * do not start another if currently transmitting, and more 540 * descriptors(tx slots) are needed for next packet. 541 */ 542 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 543 return; 544 545 /* determine number of descriptors available */ 546 if (sc->bce_txsnext >= sc->bce_txin) 547 txsfree = BCE_NTXDESC - 1 + sc->bce_txin - sc->bce_txsnext; 548 else 549 txsfree = sc->bce_txin - sc->bce_txsnext - 1; 550 551 /* 552 * Loop through the send queue, setting up transmit descriptors 553 * until we drain the queue, or use up all available transmit 554 * descriptors. 555 */ 556 while (txsfree > 0) { 557 int seg; 558 559 /* Grab a packet off the queue. */ 560 IFQ_POLL(&ifp->if_snd, m0); 561 if (m0 == NULL) 562 break; 563 564 /* get the transmit slot dma map */ 565 dmamap = sc->bce_cdata.bce_tx_map[sc->bce_txsnext]; 566 567 /* 568 * Load the DMA map. If this fails, the packet either 569 * didn't fit in the alloted number of segments, or we 570 * were short on resources. If the packet will not fit, 571 * it will be dropped. If short on resources, it will 572 * be tried again later. 573 */ 574 error = bus_dmamap_load_mbuf(sc->bce_dmatag, dmamap, m0, 575 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 576 if (error == EFBIG) { 577 printf("%s: Tx packet consumes too many DMA segments, " 578 "dropping...\n", sc->bce_dev.dv_xname); 579 IFQ_DEQUEUE(&ifp->if_snd, m0); 580 m_freem(m0); 581 ifp->if_oerrors++; 582 continue; 583 } else if (error) { 584 /* short on resources, come back later */ 585 printf("%s: unable to load Tx buffer, error = %d\n", 586 sc->bce_dev.dv_xname, error); 587 break; 588 } 589 /* If not enough descriptors available, try again later */ 590 if (dmamap->dm_nsegs > txsfree) { 591 ifp->if_flags |= IFF_OACTIVE; 592 bus_dmamap_unload(sc->bce_dmatag, dmamap); 593 break; 594 } 595 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 596 597 /* So take it off the queue */ 598 IFQ_DEQUEUE(&ifp->if_snd, m0); 599 600 /* save the pointer so it can be freed later */ 601 sc->bce_cdata.bce_tx_chain[sc->bce_txsnext] = m0; 602 603 /* Sync the data DMA map. */ 604 bus_dmamap_sync(sc->bce_dmatag, dmamap, 0, dmamap->dm_mapsize, 605 BUS_DMASYNC_PREWRITE); 606 607 /* Initialize the transmit descriptor(s). */ 608 txstart = sc->bce_txsnext; 609 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 610 u_int32_t ctrl; 611 612 ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK; 613 if (seg == 0) 614 ctrl |= CTRL_SOF; 615 if (seg == dmamap->dm_nsegs - 1) 616 ctrl |= CTRL_EOF; 617 if (sc->bce_txsnext == BCE_NTXDESC - 1) 618 ctrl |= CTRL_EOT; 619 ctrl |= CTRL_IOC; 620 sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl); 621 sc->bce_tx_ring[sc->bce_txsnext].addr = 622 htole32(dmamap->dm_segs[seg].ds_addr + 0x40000000); /* MAGIC */ 623 if (sc->bce_txsnext + 1 > BCE_NTXDESC - 1) 624 sc->bce_txsnext = 0; 625 else 626 sc->bce_txsnext++; 627 txsfree--; 628 } 629 /* sync descriptors being used */ 630 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 631 sizeof(struct bce_dma_slot) * txstart + PAGE_SIZE, 632 sizeof(struct bce_dma_slot) * dmamap->dm_nsegs, 633 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 634 635 /* Give the packet to the chip. */ 636 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_DPTR, 637 sc->bce_txsnext * sizeof(struct bce_dma_slot)); 638 639 newpkts++; 640 641 #if NBPFILTER > 0 642 /* Pass the packet to any BPF listeners. */ 643 if (ifp->if_bpf) 644 bpf_mtap(ifp->if_bpf, m0); 645 #endif /* NBPFILTER > 0 */ 646 } 647 if (txsfree == 0) { 648 /* No more slots left; notify upper layer. */ 649 ifp->if_flags |= IFF_OACTIVE; 650 } 651 if (newpkts) { 652 /* Set a watchdog timer in case the chip flakes out. */ 653 ifp->if_timer = 5; 654 } 655 } 656 657 /* Watchdog timer handler. */ 658 static void 659 bce_watchdog(struct ifnet *ifp) 660 { 661 struct bce_softc *sc = ifp->if_softc; 662 663 printf("%s: device timeout\n", sc->bce_dev.dv_xname); 664 ifp->if_oerrors++; 665 666 (void) bce_init(ifp); 667 668 /* Try to get more packets going. */ 669 bce_start(ifp); 670 } 671 672 int 673 bce_intr(void *xsc) 674 { 675 struct bce_softc *sc; 676 struct ifnet *ifp; 677 u_int32_t intstatus; 678 int wantinit; 679 int handled = 0; 680 681 sc = xsc; 682 ifp = &sc->ethercom.ec_if; 683 684 685 for (wantinit = 0; wantinit == 0;) { 686 intstatus = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 687 BCE_INT_STS); 688 689 /* ignore if not ours, or unsolicited interrupts */ 690 intstatus &= sc->bce_intmask; 691 if (intstatus == 0) 692 break; 693 694 handled = 1; 695 696 /* Ack interrupt */ 697 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS, 698 intstatus); 699 700 /* Receive interrupts. */ 701 if (intstatus & I_RI) 702 bce_rxintr(sc); 703 /* Transmit interrupts. */ 704 if (intstatus & I_XI) 705 bce_txintr(sc); 706 /* Error interrupts */ 707 if (intstatus & ~(I_RI | I_XI)) { 708 if (intstatus & I_XU) 709 printf("%s: transmit fifo underflow\n", 710 sc->bce_dev.dv_xname); 711 if (intstatus & I_RO) { 712 printf("%s: receive fifo overflow\n", 713 sc->bce_dev.dv_xname); 714 ifp->if_ierrors++; 715 } 716 if (intstatus & I_RU) 717 printf("%s: receive descriptor underflow\n", 718 sc->bce_dev.dv_xname); 719 if (intstatus & I_DE) 720 printf("%s: descriptor protocol error\n", 721 sc->bce_dev.dv_xname); 722 if (intstatus & I_PD) 723 printf("%s: data error\n", 724 sc->bce_dev.dv_xname); 725 if (intstatus & I_PC) 726 printf("%s: descriptor error\n", 727 sc->bce_dev.dv_xname); 728 if (intstatus & I_TO) 729 printf("%s: general purpose timeout\n", 730 sc->bce_dev.dv_xname); 731 wantinit = 1; 732 } 733 } 734 735 if (handled) { 736 if (wantinit) 737 bce_init(ifp); 738 /* Try to get more packets going. */ 739 bce_start(ifp); 740 } 741 return (handled); 742 } 743 744 /* Receive interrupt handler */ 745 void 746 bce_rxintr(struct bce_softc *sc) 747 { 748 struct ifnet *ifp = &sc->ethercom.ec_if; 749 struct rx_pph *pph; 750 struct mbuf *m; 751 int curr; 752 int len; 753 int i; 754 755 /* get pointer to active receive slot */ 756 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS) 757 & RS_CD_MASK; 758 curr = curr / sizeof(struct bce_dma_slot); 759 if (curr >= BCE_NRXDESC) 760 curr = BCE_NRXDESC - 1; 761 762 /* process packets up to but not current packet being worked on */ 763 for (i = sc->bce_rxin; i != curr; 764 i + 1 > BCE_NRXDESC - 1 ? i = 0 : i++) { 765 /* complete any post dma memory ops on packet */ 766 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i], 0, 767 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 768 BUS_DMASYNC_POSTREAD); 769 770 /* 771 * If the packet had an error, simply recycle the buffer, 772 * resetting the len, and flags. 773 */ 774 pph = mtod(sc->bce_cdata.bce_rx_chain[i], struct rx_pph *); 775 if (pph->flags & (RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)) { 776 ifp->if_ierrors++; 777 pph->len = 0; 778 pph->flags = 0; 779 continue; 780 } 781 /* receive the packet */ 782 len = pph->len; 783 if (len == 0) 784 continue; /* no packet if empty */ 785 pph->len = 0; 786 pph->flags = 0; 787 /* bump past pre header to packet */ 788 sc->bce_cdata.bce_rx_chain[i]->m_data += 30; /* MAGIC */ 789 790 /* 791 * The chip includes the CRC with every packet. Trim 792 * it off here. 793 */ 794 len -= ETHER_CRC_LEN; 795 796 /* 797 * If the packet is small enough to fit in a 798 * single header mbuf, allocate one and copy 799 * the data into it. This greatly reduces 800 * memory consumption when receiving lots 801 * of small packets. 802 * 803 * Otherwise, add a new buffer to the receive 804 * chain. If this fails, drop the packet and 805 * recycle the old buffer. 806 */ 807 if (len <= (MHLEN - 2)) { 808 MGETHDR(m, M_DONTWAIT, MT_DATA); 809 if (m == NULL) 810 goto dropit; 811 m->m_data += 2; 812 memcpy(mtod(m, caddr_t), 813 mtod(sc->bce_cdata.bce_rx_chain[i], caddr_t), len); 814 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; /* MAGIC */ 815 } else { 816 m = sc->bce_cdata.bce_rx_chain[i]; 817 if (bce_add_rxbuf(sc, i) != 0) { 818 dropit: 819 ifp->if_ierrors++; 820 /* continue to use old buffer */ 821 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; 822 bus_dmamap_sync(sc->bce_dmatag, 823 sc->bce_cdata.bce_rx_map[i], 0, 824 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 825 BUS_DMASYNC_PREREAD); 826 continue; 827 } 828 } 829 830 m->m_pkthdr.rcvif = ifp; 831 m->m_pkthdr.len = m->m_len = len; 832 ifp->if_ipackets++; 833 834 #if NBPFILTER > 0 835 /* 836 * Pass this up to any BPF listeners, but only 837 * pass it up the stack if it's for us. 838 */ 839 if (ifp->if_bpf) 840 bpf_mtap(ifp->if_bpf, m); 841 #endif /* NBPFILTER > 0 */ 842 843 /* Pass it on. */ 844 (*ifp->if_input) (ifp, m); 845 846 /* re-check current in case it changed */ 847 curr = (bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 848 BCE_DMA_RXSTATUS) & RS_CD_MASK) / 849 sizeof(struct bce_dma_slot); 850 if (curr >= BCE_NRXDESC) 851 curr = BCE_NRXDESC - 1; 852 } 853 sc->bce_rxin = curr; 854 } 855 856 /* Transmit interrupt handler */ 857 void 858 bce_txintr(struct bce_softc *sc) 859 { 860 struct ifnet *ifp = &sc->ethercom.ec_if; 861 int curr; 862 int i; 863 864 ifp->if_flags &= ~IFF_OACTIVE; 865 866 /* 867 * Go through the Tx list and free mbufs for those 868 * frames which have been transmitted. 869 */ 870 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXSTATUS) & 871 RS_CD_MASK; 872 curr = curr / sizeof(struct bce_dma_slot); 873 if (curr >= BCE_NTXDESC) 874 curr = BCE_NTXDESC - 1; 875 for (i = sc->bce_txin; i != curr; 876 i + 1 > BCE_NTXDESC - 1 ? i = 0 : i++) { 877 /* do any post dma memory ops on transmit data */ 878 if (sc->bce_cdata.bce_tx_chain[i] == NULL) 879 continue; 880 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i], 0, 881 sc->bce_cdata.bce_tx_map[i]->dm_mapsize, 882 BUS_DMASYNC_POSTWRITE); 883 bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i]); 884 m_freem(sc->bce_cdata.bce_tx_chain[i]); 885 sc->bce_cdata.bce_tx_chain[i] = NULL; 886 ifp->if_opackets++; 887 } 888 sc->bce_txin = curr; 889 890 /* 891 * If there are no more pending transmissions, cancel the watchdog 892 * timer 893 */ 894 if (sc->bce_txsnext == sc->bce_txin) 895 ifp->if_timer = 0; 896 } 897 898 /* initialize the interface */ 899 static int 900 bce_init(struct ifnet *ifp) 901 { 902 struct bce_softc *sc = ifp->if_softc; 903 u_int32_t reg_win; 904 int error; 905 int i; 906 907 /* Cancel any pending I/O. */ 908 bce_stop(ifp, 0); 909 910 /* enable pci inerrupts, bursts, and prefetch */ 911 912 /* remap the pci registers to the Sonics config registers */ 913 914 /* save the current map, so it can be restored */ 915 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 916 BCE_REG_WIN); 917 918 /* set register window to Sonics registers */ 919 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 920 BCE_SONICS_WIN); 921 922 /* enable SB to PCI interrupt */ 923 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 924 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) | 925 SBIV_ENET0); 926 927 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 928 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 929 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) | 930 SBTOPCI_PREF | SBTOPCI_BURST); 931 932 /* restore to ethernet register space */ 933 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 934 reg_win); 935 936 /* Reset the chip to a known state. */ 937 bce_reset(sc); 938 939 /* Initialize transmit descriptors */ 940 memset(sc->bce_tx_ring, 0, BCE_NTXDESC * sizeof(struct bce_dma_slot)); 941 sc->bce_txsnext = 0; 942 sc->bce_txin = 0; 943 944 /* enable crc32 generation */ 945 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 946 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) | 947 BCE_EMC_CG); 948 949 /* setup DMA interrupt control */ 950 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1 << 24); /* MAGIC */ 951 952 /* setup packet filter */ 953 bce_set_filter(ifp); 954 955 /* set max frame length, account for possible vlan tag */ 956 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_MAX, 957 ETHER_MAX_LEN + 32); 958 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_MAX, 959 ETHER_MAX_LEN + 32); 960 961 /* set tx watermark */ 962 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_WATER, 56); 963 964 /* enable transmit */ 965 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, XC_XE); 966 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXADDR, 967 sc->bce_ring_map->dm_segs[0].ds_addr + PAGE_SIZE + 0x40000000); /* MAGIC */ 968 969 /* 970 * Give the receive ring to the chip, and 971 * start the receive DMA engine. 972 */ 973 sc->bce_rxin = 0; 974 975 /* clear the rx descriptor ring */ 976 memset(sc->bce_rx_ring, 0, BCE_NRXDESC * sizeof(struct bce_dma_slot)); 977 /* enable receive */ 978 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 979 30 << 1 | 1); /* MAGIC */ 980 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXADDR, 981 sc->bce_ring_map->dm_segs[0].ds_addr + 0x40000000); /* MAGIC */ 982 983 /* Initalize receive descriptors */ 984 for (i = 0; i < BCE_NRXDESC; i++) { 985 if (sc->bce_cdata.bce_rx_chain[i] == NULL) { 986 if ((error = bce_add_rxbuf(sc, i)) != 0) { 987 printf("%s: unable to allocate or map rx(%d) " 988 "mbuf, error = %d\n", sc->bce_dev.dv_xname, 989 i, error); 990 bce_rxdrain(sc); 991 return (error); 992 } 993 } else 994 BCE_INIT_RXDESC(sc, i); 995 } 996 997 /* Enable interrupts */ 998 sc->bce_intmask = 999 I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO; 1000 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 1001 sc->bce_intmask); 1002 1003 /* start the receive dma */ 1004 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR, 1005 BCE_NRXDESC * sizeof(struct bce_dma_slot)); 1006 1007 /* set media */ 1008 mii_mediachg(&sc->bce_mii); 1009 1010 /* turn on the ethernet mac */ 1011 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1012 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1013 BCE_ENET_CTL) | EC_EE); 1014 1015 /* start timer */ 1016 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1017 1018 /* mark as running, and no outputs active */ 1019 ifp->if_flags |= IFF_RUNNING; 1020 ifp->if_flags &= ~IFF_OACTIVE; 1021 1022 return 0; 1023 } 1024 1025 /* add a mac address to packet filter */ 1026 void 1027 bce_add_mac(struct bce_softc *sc, u_int8_t *mac, u_long idx) 1028 { 1029 int i; 1030 u_int32_t rval; 1031 1032 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_LOW, 1033 mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]); 1034 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_HI, 1035 mac[0] << 8 | mac[1] | 0x10000); /* MAGIC */ 1036 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1037 idx << 16 | 8); /* MAGIC */ 1038 /* wait for write to complete */ 1039 for (i = 0; i < 100; i++) { 1040 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1041 BCE_FILT_CTL); 1042 if (!(rval & 0x80000000)) /* MAGIC */ 1043 break; 1044 delay(10); 1045 } 1046 if (i == 100) { 1047 printf("%s: timed out writting pkt filter ctl\n", 1048 sc->bce_dev.dv_xname); 1049 } 1050 } 1051 1052 /* Add a receive buffer to the indiciated descriptor. */ 1053 static int 1054 bce_add_rxbuf(struct bce_softc *sc, int idx) 1055 { 1056 struct mbuf *m; 1057 int error; 1058 1059 MGETHDR(m, M_DONTWAIT, MT_DATA); 1060 if (m == NULL) 1061 return (ENOBUFS); 1062 1063 MCLGET(m, M_DONTWAIT); 1064 if ((m->m_flags & M_EXT) == 0) { 1065 m_freem(m); 1066 return (ENOBUFS); 1067 } 1068 if (sc->bce_cdata.bce_rx_chain[idx] != NULL) 1069 bus_dmamap_unload(sc->bce_dmatag, 1070 sc->bce_cdata.bce_rx_map[idx]); 1071 1072 sc->bce_cdata.bce_rx_chain[idx] = m; 1073 1074 error = bus_dmamap_load(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 1075 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1076 BUS_DMA_READ | BUS_DMA_NOWAIT); 1077 if (error) 1078 return (error); 1079 1080 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 0, 1081 sc->bce_cdata.bce_rx_map[idx]->dm_mapsize, BUS_DMASYNC_PREREAD); 1082 1083 BCE_INIT_RXDESC(sc, idx); 1084 1085 return (0); 1086 1087 } 1088 1089 /* Drain the receive queue. */ 1090 static void 1091 bce_rxdrain(struct bce_softc *sc) 1092 { 1093 int i; 1094 1095 for (i = 0; i < BCE_NRXDESC; i++) { 1096 if (sc->bce_cdata.bce_rx_chain[i] != NULL) { 1097 bus_dmamap_unload(sc->bce_dmatag, 1098 sc->bce_cdata.bce_rx_map[i]); 1099 m_freem(sc->bce_cdata.bce_rx_chain[i]); 1100 sc->bce_cdata.bce_rx_chain[i] = NULL; 1101 } 1102 } 1103 } 1104 1105 /* Stop transmission on the interface */ 1106 static void 1107 bce_stop(struct ifnet *ifp, int disable) 1108 { 1109 struct bce_softc *sc = ifp->if_softc; 1110 int i; 1111 u_int32_t val; 1112 1113 /* Stop the 1 second timer */ 1114 callout_stop(&sc->bce_timeout); 1115 1116 /* Down the MII. */ 1117 mii_down(&sc->bce_mii); 1118 1119 /* Disable interrupts. */ 1120 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0); 1121 sc->bce_intmask = 0; 1122 delay(10); 1123 1124 /* Disable emac */ 1125 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED); 1126 for (i = 0; i < 200; i++) { 1127 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1128 BCE_ENET_CTL); 1129 if (!(val & EC_ED)) 1130 break; 1131 delay(10); 1132 } 1133 1134 /* Stop the DMA */ 1135 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 0); 1136 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1137 delay(10); 1138 1139 /* Release any queued transmit buffers. */ 1140 for (i = 0; i < BCE_NTXDESC; i++) { 1141 if (sc->bce_cdata.bce_tx_chain[i] != NULL) { 1142 bus_dmamap_unload(sc->bce_dmatag, 1143 sc->bce_cdata.bce_tx_map[i]); 1144 m_freem(sc->bce_cdata.bce_tx_chain[i]); 1145 sc->bce_cdata.bce_tx_chain[i] = NULL; 1146 } 1147 } 1148 1149 /* drain receive queue */ 1150 if (disable) 1151 bce_rxdrain(sc); 1152 1153 /* Mark the interface down and cancel the watchdog timer. */ 1154 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1155 ifp->if_timer = 0; 1156 } 1157 1158 /* reset the chip */ 1159 static void 1160 bce_reset(struct bce_softc *sc) 1161 { 1162 u_int32_t val; 1163 u_int32_t sbval; 1164 int i; 1165 1166 /* if SB core is up */ 1167 sbval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1168 BCE_SBTMSTATELOW); 1169 if ((sbval & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK) { 1170 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1171 0); 1172 1173 /* disable emac */ 1174 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1175 EC_ED); 1176 for (i = 0; i < 200; i++) { 1177 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1178 BCE_ENET_CTL); 1179 if (!(val & EC_ED)) 1180 break; 1181 delay(10); 1182 } 1183 if (i == 200) 1184 printf("%s: timed out disabling ethernet mac\n", 1185 sc->bce_dev.dv_xname); 1186 1187 /* reset the dma engines */ 1188 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1189 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS); 1190 /* if error on receive, wait to go idle */ 1191 if (val & RS_ERROR) { 1192 for (i = 0; i < 100; i++) { 1193 val = bus_space_read_4(sc->bce_btag, 1194 sc->bce_bhandle, BCE_DMA_RXSTATUS); 1195 if (val & RS_DMA_IDLE) 1196 break; 1197 delay(10); 1198 } 1199 if (i == 100) 1200 printf("%s: receive dma did not go idle after" 1201 " error\n", sc->bce_dev.dv_xname); 1202 } 1203 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1204 BCE_DMA_RXSTATUS, 0); 1205 1206 /* reset ethernet mac */ 1207 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1208 EC_ES); 1209 for (i = 0; i < 200; i++) { 1210 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1211 BCE_ENET_CTL); 1212 if (!(val & EC_ES)) 1213 break; 1214 delay(10); 1215 } 1216 if (i == 200) 1217 printf("%s: timed out restting ethernet mac\n", 1218 sc->bce_dev.dv_xname); 1219 } else { 1220 u_int32_t reg_win; 1221 1222 /* remap the pci registers to the Sonics config registers */ 1223 1224 /* save the current map, so it can be restored */ 1225 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1226 BCE_REG_WIN); 1227 /* set register window to Sonics registers */ 1228 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1229 BCE_REG_WIN, BCE_SONICS_WIN); 1230 1231 /* enable SB to PCI interrupt */ 1232 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 1233 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1234 BCE_SBINTVEC) | 1235 SBIV_ENET0); 1236 1237 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 1238 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 1239 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1240 BCE_SPCI_TR2) | 1241 SBTOPCI_PREF | SBTOPCI_BURST); 1242 1243 /* restore to ethernet register space */ 1244 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 1245 reg_win); 1246 } 1247 1248 /* disable SB core if not in reset */ 1249 if (!(sbval & SBTML_RESET)) { 1250 1251 /* set the reject bit */ 1252 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1253 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_CLK); 1254 for (i = 0; i < 200; i++) { 1255 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1256 BCE_SBTMSTATELOW); 1257 if (val & SBTML_REJ) 1258 break; 1259 delay(1); 1260 } 1261 if (i == 200) 1262 printf("%s: while restting core, reject did not set\n", 1263 sc->bce_dev.dv_xname); 1264 /* wait until busy is clear */ 1265 for (i = 0; i < 200; i++) { 1266 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1267 BCE_SBTMSTATEHI); 1268 if (!(val & 0x4)) 1269 break; 1270 delay(1); 1271 } 1272 if (i == 200) 1273 printf("%s: while restting core, busy did not clear\n", 1274 sc->bce_dev.dv_xname); 1275 /* set reset and reject while enabling the clocks */ 1276 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1277 BCE_SBTMSTATELOW, 1278 SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET); 1279 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1280 BCE_SBTMSTATELOW); 1281 delay(10); 1282 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1283 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_RESET); 1284 delay(1); 1285 } 1286 /* enable clock */ 1287 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1288 SBTML_FGC | SBTML_CLK | SBTML_RESET); 1289 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1290 delay(1); 1291 1292 /* clear any error bits that may be on */ 1293 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI); 1294 if (val & 1) 1295 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI, 1296 0); 1297 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE); 1298 if (val & SBIM_MAGIC_ERRORBITS) 1299 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE, 1300 val & ~SBIM_MAGIC_ERRORBITS); 1301 1302 /* clear reset and allow it to propagate throughout the core */ 1303 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1304 SBTML_FGC | SBTML_CLK); 1305 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1306 delay(1); 1307 1308 /* leave clock enabled */ 1309 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1310 SBTML_CLK); 1311 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1312 delay(1); 1313 1314 /* initialize MDC preamble, frequency */ 1315 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_CTL, 0x8d); /* MAGIC */ 1316 1317 /* enable phy, differs for internal, and external */ 1318 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL); 1319 if (!(val & BCE_DC_IP)) { 1320 /* select external phy */ 1321 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_EP); 1322 } else if (val & BCE_DC_ER) { /* internal, clear reset bit if on */ 1323 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL, 1324 val & ~BCE_DC_ER); 1325 delay(100); 1326 } 1327 } 1328 1329 /* Set up the receive filter. */ 1330 void 1331 bce_set_filter(struct ifnet *ifp) 1332 { 1333 struct bce_softc *sc = ifp->if_softc; 1334 1335 if (ifp->if_flags & IFF_PROMISC) { 1336 ifp->if_flags |= IFF_ALLMULTI; 1337 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1338 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) 1339 | ERC_PE); 1340 } else { 1341 ifp->if_flags &= ~IFF_ALLMULTI; 1342 1343 /* turn off promiscuous */ 1344 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1345 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1346 BCE_RX_CTL) & ~ERC_PE); 1347 1348 /* enable/disable broadcast */ 1349 if (ifp->if_flags & IFF_BROADCAST) 1350 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1351 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1352 sc->bce_bhandle, BCE_RX_CTL) & ~ERC_DB); 1353 else 1354 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1355 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1356 sc->bce_bhandle, BCE_RX_CTL) | ERC_DB); 1357 1358 /* disable the filter */ 1359 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1360 0); 1361 1362 /* add our own address */ 1363 bce_add_mac(sc, sc->enaddr, 0); 1364 1365 /* for now accept all multicast */ 1366 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1367 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) | 1368 ERC_AM); 1369 ifp->if_flags |= IFF_ALLMULTI; 1370 1371 /* enable the filter */ 1372 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1373 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1374 BCE_FILT_CTL) | 1); 1375 } 1376 } 1377 1378 /* Read a PHY register on the MII. */ 1379 int 1380 bce_mii_read(struct device *self, int phy, int reg) 1381 { 1382 struct bce_softc *sc = (struct bce_softc *) self; 1383 int i; 1384 u_int32_t val; 1385 1386 /* clear mii_int */ 1387 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR); 1388 1389 /* Read the PHY register */ 1390 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1391 (MII_COMMAND_READ << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1392 (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */ 1393 1394 for (i = 0; i < BCE_TIMEOUT; i++) { 1395 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS); 1396 if (val & BCE_MIINTR) 1397 break; 1398 delay(10); 1399 } 1400 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1401 if (i == BCE_TIMEOUT) { 1402 printf("%s: PHY read timed out reading phy %d, reg %d, val = " 1403 "0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val); 1404 return (0); 1405 } 1406 return (val & BCE_MICOMM_DATA); 1407 } 1408 1409 /* Write a PHY register on the MII */ 1410 void 1411 bce_mii_write(struct device *self, int phy, int reg, int val) 1412 { 1413 struct bce_softc *sc = (struct bce_softc *) self; 1414 int i; 1415 u_int32_t rval; 1416 1417 /* clear mii_int */ 1418 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, 1419 BCE_MIINTR); 1420 1421 /* Write the PHY register */ 1422 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1423 (MII_COMMAND_WRITE << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1424 (MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) | /* MAGIC */ 1425 BCE_MIPHY(phy) | BCE_MIREG(reg)); 1426 1427 /* wait for write to complete */ 1428 for (i = 0; i < BCE_TIMEOUT; i++) { 1429 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1430 BCE_MI_STS); 1431 if (rval & BCE_MIINTR) 1432 break; 1433 delay(10); 1434 } 1435 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1436 if (i == BCE_TIMEOUT) { 1437 printf("%s: PHY timed out writting phy %d, reg %d, val " 1438 "= 0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val); 1439 } 1440 } 1441 1442 /* sync hardware duplex mode to software state */ 1443 void 1444 bce_statchg(struct device *self) 1445 { 1446 struct bce_softc *sc = (struct bce_softc *) self; 1447 u_int32_t reg; 1448 1449 /* if needed, change register to match duplex mode */ 1450 reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL); 1451 if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD)) 1452 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1453 reg | EXC_FD); 1454 else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD) 1455 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1456 reg & ~EXC_FD); 1457 1458 /* 1459 * Enable activity led. 1460 * XXX This should be in a phy driver, but not currently. 1461 */ 1462 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 1463 bce_mii_read((struct device *) sc, 1, 26) & 0x7fff); /* MAGIC */ 1464 /* enable traffic meter led mode */ 1465 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 1466 bce_mii_read((struct device *) sc, 1, 27) | (1 << 6)); /* MAGIC */ 1467 } 1468 1469 /* Set hardware to newly-selected media */ 1470 int 1471 bce_mediachange(struct ifnet *ifp) 1472 { 1473 struct bce_softc *sc = ifp->if_softc; 1474 1475 if (ifp->if_flags & IFF_UP) 1476 mii_mediachg(&sc->bce_mii); 1477 return (0); 1478 } 1479 1480 /* Get the current interface media status */ 1481 static void 1482 bce_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1483 { 1484 struct bce_softc *sc = ifp->if_softc; 1485 1486 mii_pollstat(&sc->bce_mii); 1487 ifmr->ifm_active = sc->bce_mii.mii_media_active; 1488 ifmr->ifm_status = sc->bce_mii.mii_media_status; 1489 } 1490 1491 /* One second timer, checks link status */ 1492 static void 1493 bce_tick(void *v) 1494 { 1495 struct bce_softc *sc = v; 1496 1497 /* Tick the MII. */ 1498 mii_tick(&sc->bce_mii); 1499 1500 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1501 } 1502
Indexes created Tue Sep 30 20:09:53 GMT 2025