ixgbe_82598.c revision 1.1.12.1
1 /* $NetBSD: ixgbe_82598.c,v 1.1.12.1 2017/12/03 11:37:29 jdolecek Exp $ */ 2 3 /****************************************************************************** 4 5 Copyright (c) 2001-2017, Intel Corporation 6 All rights reserved. 7 8 Redistribution and use in source and binary forms, with or without 9 modification, are permitted provided that the following conditions are met: 10 11 1. Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 2. Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 18 3. Neither the name of the Intel Corporation nor the names of its 19 contributors may be used to endorse or promote products derived from 20 this software without specific prior written permission. 21 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 POSSIBILITY OF SUCH DAMAGE. 33 34 ******************************************************************************/ 35 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_82598.c 320688 2017-07-05 17:27:03Z erj $*/ 36 37 #include "ixgbe_type.h" 38 #include "ixgbe_82598.h" 39 #include "ixgbe_api.h" 40 #include "ixgbe_common.h" 41 #include "ixgbe_phy.h" 42 43 #define IXGBE_82598_MAX_TX_QUEUES 32 44 #define IXGBE_82598_MAX_RX_QUEUES 64 45 #define IXGBE_82598_RAR_ENTRIES 16 46 #define IXGBE_82598_MC_TBL_SIZE 128 47 #define IXGBE_82598_VFT_TBL_SIZE 128 48 #define IXGBE_82598_RX_PB_SIZE 512 49 50 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 51 ixgbe_link_speed *speed, 52 bool *autoneg); 53 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw); 54 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, 55 bool autoneg_wait_to_complete); 56 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 57 ixgbe_link_speed *speed, bool *link_up, 58 bool link_up_wait_to_complete); 59 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, 60 ixgbe_link_speed speed, 61 bool autoneg_wait_to_complete); 62 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 63 ixgbe_link_speed speed, 64 bool autoneg_wait_to_complete); 65 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw); 66 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 67 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw); 68 static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb, 69 u32 headroom, int strategy); 70 static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset, 71 u8 *sff8472_data); 72 /** 73 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout 74 * @hw: pointer to the HW structure 75 * 76 * The defaults for 82598 should be in the range of 50us to 50ms, 77 * however the hardware default for these parts is 500us to 1ms which is less 78 * than the 10ms recommended by the pci-e spec. To address this we need to 79 * increase the value to either 10ms to 250ms for capability version 1 config, 80 * or 16ms to 55ms for version 2. 81 **/ 82 void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) 83 { 84 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); 85 u16 pcie_devctl2; 86 87 /* only take action if timeout value is defaulted to 0 */ 88 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK) 89 goto out; 90 91 /* 92 * if capababilities version is type 1 we can write the 93 * timeout of 10ms to 250ms through the GCR register 94 */ 95 if (!(gcr & IXGBE_GCR_CAP_VER2)) { 96 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms; 97 goto out; 98 } 99 100 /* 101 * for version 2 capabilities we need to write the config space 102 * directly in order to set the completion timeout value for 103 * 16ms to 55ms 104 */ 105 pcie_devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); 106 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms; 107 IXGBE_WRITE_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2); 108 out: 109 /* disable completion timeout resend */ 110 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND; 111 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); 112 } 113 114 /** 115 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type 116 * @hw: pointer to hardware structure 117 * 118 * Initialize the function pointers and assign the MAC type for 82598. 119 * Does not touch the hardware. 120 **/ 121 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw) 122 { 123 struct ixgbe_mac_info *mac = &hw->mac; 124 struct ixgbe_phy_info *phy = &hw->phy; 125 s32 ret_val; 126 127 DEBUGFUNC("ixgbe_init_ops_82598"); 128 129 ret_val = ixgbe_init_phy_ops_generic(hw); 130 ret_val = ixgbe_init_ops_generic(hw); 131 132 /* PHY */ 133 phy->ops.init = ixgbe_init_phy_ops_82598; 134 135 /* MAC */ 136 mac->ops.start_hw = ixgbe_start_hw_82598; 137 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_82598; 138 mac->ops.reset_hw = ixgbe_reset_hw_82598; 139 mac->ops.get_media_type = ixgbe_get_media_type_82598; 140 mac->ops.get_supported_physical_layer = 141 ixgbe_get_supported_physical_layer_82598; 142 mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82598; 143 mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82598; 144 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie_82598; 145 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82598; 146 147 /* RAR, Multicast, VLAN */ 148 mac->ops.set_vmdq = ixgbe_set_vmdq_82598; 149 mac->ops.clear_vmdq = ixgbe_clear_vmdq_82598; 150 mac->ops.set_vfta = ixgbe_set_vfta_82598; 151 mac->ops.set_vlvf = NULL; 152 mac->ops.clear_vfta = ixgbe_clear_vfta_82598; 153 154 /* Flow Control */ 155 mac->ops.fc_enable = ixgbe_fc_enable_82598; 156 157 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE; 158 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE; 159 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES; 160 mac->rx_pb_size = IXGBE_82598_RX_PB_SIZE; 161 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES; 162 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES; 163 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 164 165 /* SFP+ Module */ 166 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_82598; 167 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_82598; 168 169 /* Link */ 170 mac->ops.check_link = ixgbe_check_mac_link_82598; 171 mac->ops.setup_link = ixgbe_setup_mac_link_82598; 172 mac->ops.flap_tx_laser = NULL; 173 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82598; 174 mac->ops.setup_rxpba = ixgbe_set_rxpba_82598; 175 176 /* Manageability interface */ 177 mac->ops.set_fw_drv_ver = NULL; 178 179 mac->ops.get_rtrup2tc = NULL; 180 181 return ret_val; 182 } 183 184 /** 185 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init 186 * @hw: pointer to hardware structure 187 * 188 * Initialize any function pointers that were not able to be 189 * set during init_shared_code because the PHY/SFP type was 190 * not known. Perform the SFP init if necessary. 191 * 192 **/ 193 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) 194 { 195 struct ixgbe_mac_info *mac = &hw->mac; 196 struct ixgbe_phy_info *phy = &hw->phy; 197 s32 ret_val = IXGBE_SUCCESS; 198 u16 list_offset, data_offset; 199 200 DEBUGFUNC("ixgbe_init_phy_ops_82598"); 201 202 /* Identify the PHY */ 203 phy->ops.identify(hw); 204 205 /* Overwrite the link function pointers if copper PHY */ 206 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 207 mac->ops.setup_link = ixgbe_setup_copper_link_82598; 208 mac->ops.get_link_capabilities = 209 ixgbe_get_copper_link_capabilities_generic; 210 } 211 212 switch (hw->phy.type) { 213 case ixgbe_phy_tn: 214 phy->ops.setup_link = ixgbe_setup_phy_link_tnx; 215 phy->ops.check_link = ixgbe_check_phy_link_tnx; 216 phy->ops.get_firmware_version = 217 ixgbe_get_phy_firmware_version_tnx; 218 break; 219 case ixgbe_phy_nl: 220 phy->ops.reset = ixgbe_reset_phy_nl; 221 222 /* Call SFP+ identify routine to get the SFP+ module type */ 223 ret_val = phy->ops.identify_sfp(hw); 224 if (ret_val != IXGBE_SUCCESS) 225 goto out; 226 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) { 227 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 228 goto out; 229 } 230 231 /* Check to see if SFP+ module is supported */ 232 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, 233 &list_offset, 234 &data_offset); 235 if (ret_val != IXGBE_SUCCESS) { 236 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 237 goto out; 238 } 239 break; 240 default: 241 break; 242 } 243 244 out: 245 return ret_val; 246 } 247 248 /** 249 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx 250 * @hw: pointer to hardware structure 251 * 252 * Starts the hardware using the generic start_hw function. 253 * Disables relaxed ordering Then set pcie completion timeout 254 * 255 **/ 256 s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) 257 { 258 u32 regval; 259 u32 i; 260 s32 ret_val = IXGBE_SUCCESS; 261 262 DEBUGFUNC("ixgbe_start_hw_82598"); 263 264 ret_val = ixgbe_start_hw_generic(hw); 265 if (ret_val) 266 return ret_val; 267 268 /* Disable relaxed ordering */ 269 for (i = 0; ((i < hw->mac.max_tx_queues) && 270 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { 271 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); 272 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 273 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); 274 } 275 276 for (i = 0; ((i < hw->mac.max_rx_queues) && 277 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { 278 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 279 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 280 IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 281 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 282 } 283 284 /* set the completion timeout for interface */ 285 ixgbe_set_pcie_completion_timeout(hw); 286 287 return ret_val; 288 } 289 290 /** 291 * ixgbe_get_link_capabilities_82598 - Determines link capabilities 292 * @hw: pointer to hardware structure 293 * @speed: pointer to link speed 294 * @autoneg: boolean auto-negotiation value 295 * 296 * Determines the link capabilities by reading the AUTOC register. 297 **/ 298 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 299 ixgbe_link_speed *speed, 300 bool *autoneg) 301 { 302 s32 status = IXGBE_SUCCESS; 303 u32 autoc = 0; 304 305 DEBUGFUNC("ixgbe_get_link_capabilities_82598"); 306 307 /* 308 * Determine link capabilities based on the stored value of AUTOC, 309 * which represents EEPROM defaults. If AUTOC value has not been 310 * stored, use the current register value. 311 */ 312 if (hw->mac.orig_link_settings_stored) 313 autoc = hw->mac.orig_autoc; 314 else 315 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 316 317 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 318 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 319 *speed = IXGBE_LINK_SPEED_1GB_FULL; 320 *autoneg = FALSE; 321 break; 322 323 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 324 *speed = IXGBE_LINK_SPEED_10GB_FULL; 325 *autoneg = FALSE; 326 break; 327 328 case IXGBE_AUTOC_LMS_1G_AN: 329 *speed = IXGBE_LINK_SPEED_1GB_FULL; 330 *autoneg = TRUE; 331 break; 332 333 case IXGBE_AUTOC_LMS_KX4_AN: 334 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 335 *speed = IXGBE_LINK_SPEED_UNKNOWN; 336 if (autoc & IXGBE_AUTOC_KX4_SUPP) 337 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 338 if (autoc & IXGBE_AUTOC_KX_SUPP) 339 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 340 *autoneg = TRUE; 341 break; 342 343 default: 344 status = IXGBE_ERR_LINK_SETUP; 345 break; 346 } 347 348 return status; 349 } 350 351 /** 352 * ixgbe_get_media_type_82598 - Determines media type 353 * @hw: pointer to hardware structure 354 * 355 * Returns the media type (fiber, copper, backplane) 356 **/ 357 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) 358 { 359 enum ixgbe_media_type media_type; 360 361 DEBUGFUNC("ixgbe_get_media_type_82598"); 362 363 /* Detect if there is a copper PHY attached. */ 364 switch (hw->phy.type) { 365 case ixgbe_phy_cu_unknown: 366 case ixgbe_phy_tn: 367 media_type = ixgbe_media_type_copper; 368 goto out; 369 default: 370 break; 371 } 372 373 /* Media type for I82598 is based on device ID */ 374 switch (hw->device_id) { 375 case IXGBE_DEV_ID_82598: 376 case IXGBE_DEV_ID_82598_BX: 377 /* Default device ID is mezzanine card KX/KX4 */ 378 media_type = ixgbe_media_type_backplane; 379 break; 380 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 381 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 382 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 383 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 384 case IXGBE_DEV_ID_82598EB_XF_LR: 385 case IXGBE_DEV_ID_82598EB_SFP_LOM: 386 media_type = ixgbe_media_type_fiber; 387 break; 388 case IXGBE_DEV_ID_82598EB_CX4: 389 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 390 media_type = ixgbe_media_type_cx4; 391 break; 392 case IXGBE_DEV_ID_82598AT: 393 case IXGBE_DEV_ID_82598AT2: 394 media_type = ixgbe_media_type_copper; 395 break; 396 default: 397 media_type = ixgbe_media_type_unknown; 398 break; 399 } 400 out: 401 return media_type; 402 } 403 404 /** 405 * ixgbe_fc_enable_82598 - Enable flow control 406 * @hw: pointer to hardware structure 407 * 408 * Enable flow control according to the current settings. 409 **/ 410 s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw) 411 { 412 s32 ret_val = IXGBE_SUCCESS; 413 u32 fctrl_reg; 414 u32 rmcs_reg; 415 u32 reg; 416 u32 fcrtl, fcrth; 417 u32 link_speed = 0; 418 int i; 419 bool link_up; 420 421 DEBUGFUNC("ixgbe_fc_enable_82598"); 422 423 /* Validate the water mark configuration */ 424 if (!hw->fc.pause_time) { 425 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 426 goto out; 427 } 428 429 /* Low water mark of zero causes XOFF floods */ 430 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 431 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 432 hw->fc.high_water[i]) { 433 if (!hw->fc.low_water[i] || 434 hw->fc.low_water[i] >= hw->fc.high_water[i]) { 435 DEBUGOUT("Invalid water mark configuration\n"); 436 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 437 goto out; 438 } 439 } 440 } 441 442 /* 443 * On 82598 having Rx FC on causes resets while doing 1G 444 * so if it's on turn it off once we know link_speed. For 445 * more details see 82598 Specification update. 446 */ 447 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE); 448 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) { 449 switch (hw->fc.requested_mode) { 450 case ixgbe_fc_full: 451 hw->fc.requested_mode = ixgbe_fc_tx_pause; 452 break; 453 case ixgbe_fc_rx_pause: 454 hw->fc.requested_mode = ixgbe_fc_none; 455 break; 456 default: 457 /* no change */ 458 break; 459 } 460 } 461 462 /* Negotiate the fc mode to use */ 463 ixgbe_fc_autoneg(hw); 464 465 /* Disable any previous flow control settings */ 466 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 467 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); 468 469 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 470 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); 471 472 /* 473 * The possible values of fc.current_mode are: 474 * 0: Flow control is completely disabled 475 * 1: Rx flow control is enabled (we can receive pause frames, 476 * but not send pause frames). 477 * 2: Tx flow control is enabled (we can send pause frames but 478 * we do not support receiving pause frames). 479 * 3: Both Rx and Tx flow control (symmetric) are enabled. 480 * other: Invalid. 481 */ 482 switch (hw->fc.current_mode) { 483 case ixgbe_fc_none: 484 /* 485 * Flow control is disabled by software override or autoneg. 486 * The code below will actually disable it in the HW. 487 */ 488 break; 489 case ixgbe_fc_rx_pause: 490 /* 491 * Rx Flow control is enabled and Tx Flow control is 492 * disabled by software override. Since there really 493 * isn't a way to advertise that we are capable of RX 494 * Pause ONLY, we will advertise that we support both 495 * symmetric and asymmetric Rx PAUSE. Later, we will 496 * disable the adapter's ability to send PAUSE frames. 497 */ 498 fctrl_reg |= IXGBE_FCTRL_RFCE; 499 break; 500 case ixgbe_fc_tx_pause: 501 /* 502 * Tx Flow control is enabled, and Rx Flow control is 503 * disabled by software override. 504 */ 505 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 506 break; 507 case ixgbe_fc_full: 508 /* Flow control (both Rx and Tx) is enabled by SW override. */ 509 fctrl_reg |= IXGBE_FCTRL_RFCE; 510 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 511 break; 512 default: 513 DEBUGOUT("Flow control param set incorrectly\n"); 514 ret_val = IXGBE_ERR_CONFIG; 515 goto out; 516 break; 517 } 518 519 /* Set 802.3x based flow control settings. */ 520 fctrl_reg |= IXGBE_FCTRL_DPF; 521 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); 522 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); 523 524 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 525 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 526 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 527 hw->fc.high_water[i]) { 528 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 529 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 530 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl); 531 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth); 532 } else { 533 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0); 534 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0); 535 } 536 537 } 538 539 /* Configure pause time (2 TCs per register) */ 540 reg = hw->fc.pause_time * 0x00010001; 541 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 542 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 543 544 /* Configure flow control refresh threshold value */ 545 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 546 547 out: 548 return ret_val; 549 } 550 551 /** 552 * ixgbe_start_mac_link_82598 - Configures MAC link settings 553 * @hw: pointer to hardware structure 554 * 555 * Configures link settings based on values in the ixgbe_hw struct. 556 * Restarts the link. Performs autonegotiation if needed. 557 **/ 558 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, 559 bool autoneg_wait_to_complete) 560 { 561 u32 autoc_reg; 562 u32 links_reg; 563 u32 i; 564 s32 status = IXGBE_SUCCESS; 565 566 DEBUGFUNC("ixgbe_start_mac_link_82598"); 567 568 /* Restart link */ 569 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 570 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 571 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 572 573 /* Only poll for autoneg to complete if specified to do so */ 574 if (autoneg_wait_to_complete) { 575 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 576 IXGBE_AUTOC_LMS_KX4_AN || 577 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 578 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 579 links_reg = 0; /* Just in case Autoneg time = 0 */ 580 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 581 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 582 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 583 break; 584 msec_delay(100); 585 } 586 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 587 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 588 DEBUGOUT("Autonegotiation did not complete.\n"); 589 } 590 } 591 } 592 593 /* Add delay to filter out noises during initial link setup */ 594 msec_delay(50); 595 596 return status; 597 } 598 599 /** 600 * ixgbe_validate_link_ready - Function looks for phy link 601 * @hw: pointer to hardware structure 602 * 603 * Function indicates success when phy link is available. If phy is not ready 604 * within 5 seconds of MAC indicating link, the function returns error. 605 **/ 606 static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw) 607 { 608 u32 timeout; 609 u16 an_reg; 610 611 if (hw->device_id != IXGBE_DEV_ID_82598AT2) 612 return IXGBE_SUCCESS; 613 614 for (timeout = 0; 615 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) { 616 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 617 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_reg); 618 619 if ((an_reg & IXGBE_MII_AUTONEG_COMPLETE) && 620 (an_reg & IXGBE_MII_AUTONEG_LINK_UP)) 621 break; 622 623 msec_delay(100); 624 } 625 626 if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) { 627 DEBUGOUT("Link was indicated but link is down\n"); 628 return IXGBE_ERR_LINK_SETUP; 629 } 630 631 return IXGBE_SUCCESS; 632 } 633 634 /** 635 * ixgbe_check_mac_link_82598 - Get link/speed status 636 * @hw: pointer to hardware structure 637 * @speed: pointer to link speed 638 * @link_up: TRUE is link is up, FALSE otherwise 639 * @link_up_wait_to_complete: bool used to wait for link up or not 640 * 641 * Reads the links register to determine if link is up and the current speed 642 **/ 643 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 644 ixgbe_link_speed *speed, bool *link_up, 645 bool link_up_wait_to_complete) 646 { 647 u32 links_reg; 648 u32 i; 649 u16 link_reg, adapt_comp_reg; 650 651 DEBUGFUNC("ixgbe_check_mac_link_82598"); 652 653 /* 654 * SERDES PHY requires us to read link status from undocumented 655 * register 0xC79F. Bit 0 set indicates link is up/ready; clear 656 * indicates link down. OxC00C is read to check that the XAUI lanes 657 * are active. Bit 0 clear indicates active; set indicates inactive. 658 */ 659 if (hw->phy.type == ixgbe_phy_nl) { 660 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 661 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 662 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV, 663 &adapt_comp_reg); 664 if (link_up_wait_to_complete) { 665 for (i = 0; i < hw->mac.max_link_up_time; i++) { 666 if ((link_reg & 1) && 667 ((adapt_comp_reg & 1) == 0)) { 668 *link_up = TRUE; 669 break; 670 } else { 671 *link_up = FALSE; 672 } 673 msec_delay(100); 674 hw->phy.ops.read_reg(hw, 0xC79F, 675 IXGBE_TWINAX_DEV, 676 &link_reg); 677 hw->phy.ops.read_reg(hw, 0xC00C, 678 IXGBE_TWINAX_DEV, 679 &adapt_comp_reg); 680 } 681 } else { 682 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0)) 683 *link_up = TRUE; 684 else 685 *link_up = FALSE; 686 } 687 688 if (*link_up == FALSE) 689 goto out; 690 } 691 692 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 693 if (link_up_wait_to_complete) { 694 for (i = 0; i < hw->mac.max_link_up_time; i++) { 695 if (links_reg & IXGBE_LINKS_UP) { 696 *link_up = TRUE; 697 break; 698 } else { 699 *link_up = FALSE; 700 } 701 msec_delay(100); 702 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 703 } 704 } else { 705 if (links_reg & IXGBE_LINKS_UP) 706 *link_up = TRUE; 707 else 708 *link_up = FALSE; 709 } 710 711 if (links_reg & IXGBE_LINKS_SPEED) 712 *speed = IXGBE_LINK_SPEED_10GB_FULL; 713 else 714 *speed = IXGBE_LINK_SPEED_1GB_FULL; 715 716 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == TRUE) && 717 (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS)) 718 *link_up = FALSE; 719 720 out: 721 return IXGBE_SUCCESS; 722 } 723 724 /** 725 * ixgbe_setup_mac_link_82598 - Set MAC link speed 726 * @hw: pointer to hardware structure 727 * @speed: new link speed 728 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 729 * 730 * Set the link speed in the AUTOC register and restarts link. 731 **/ 732 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, 733 ixgbe_link_speed speed, 734 bool autoneg_wait_to_complete) 735 { 736 bool autoneg = FALSE; 737 s32 status = IXGBE_SUCCESS; 738 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 739 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 740 u32 autoc = curr_autoc; 741 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 742 743 DEBUGFUNC("ixgbe_setup_mac_link_82598"); 744 745 /* Check to see if speed passed in is supported. */ 746 ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg); 747 speed &= link_capabilities; 748 749 if (speed == IXGBE_LINK_SPEED_UNKNOWN) 750 status = IXGBE_ERR_LINK_SETUP; 751 752 /* Set KX4/KX support according to speed requested */ 753 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || 754 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 755 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; 756 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 757 autoc |= IXGBE_AUTOC_KX4_SUPP; 758 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 759 autoc |= IXGBE_AUTOC_KX_SUPP; 760 if (autoc != curr_autoc) 761 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 762 } 763 764 if (status == IXGBE_SUCCESS) { 765 /* 766 * Setup and restart the link based on the new values in 767 * ixgbe_hw This will write the AUTOC register based on the new 768 * stored values 769 */ 770 status = ixgbe_start_mac_link_82598(hw, 771 autoneg_wait_to_complete); 772 } 773 774 return status; 775 } 776 777 778 /** 779 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field 780 * @hw: pointer to hardware structure 781 * @speed: new link speed 782 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 783 * 784 * Sets the link speed in the AUTOC register in the MAC and restarts link. 785 **/ 786 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 787 ixgbe_link_speed speed, 788 bool autoneg_wait_to_complete) 789 { 790 s32 status; 791 792 DEBUGFUNC("ixgbe_setup_copper_link_82598"); 793 794 /* Setup the PHY according to input speed */ 795 status = hw->phy.ops.setup_link_speed(hw, speed, 796 autoneg_wait_to_complete); 797 /* Set up MAC */ 798 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); 799 800 return status; 801 } 802 803 /** 804 * ixgbe_reset_hw_82598 - Performs hardware reset 805 * @hw: pointer to hardware structure 806 * 807 * Resets the hardware by resetting the transmit and receive units, masks and 808 * clears all interrupts, performing a PHY reset, and performing a link (MAC) 809 * reset. 810 **/ 811 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) 812 { 813 s32 status = IXGBE_SUCCESS; 814 s32 phy_status = IXGBE_SUCCESS; 815 u32 ctrl; 816 u32 gheccr; 817 u32 i; 818 u32 autoc; 819 u8 analog_val; 820 821 DEBUGFUNC("ixgbe_reset_hw_82598"); 822 823 /* Call adapter stop to disable tx/rx and clear interrupts */ 824 status = hw->mac.ops.stop_adapter(hw); 825 if (status != IXGBE_SUCCESS) 826 goto reset_hw_out; 827 828 /* 829 * Power up the Atlas Tx lanes if they are currently powered down. 830 * Atlas Tx lanes are powered down for MAC loopback tests, but 831 * they are not automatically restored on reset. 832 */ 833 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 834 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { 835 /* Enable Tx Atlas so packets can be transmitted again */ 836 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 837 &analog_val); 838 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; 839 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 840 analog_val); 841 842 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 843 &analog_val); 844 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 845 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 846 analog_val); 847 848 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 849 &analog_val); 850 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 851 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 852 analog_val); 853 854 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 855 &analog_val); 856 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 857 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 858 analog_val); 859 } 860 861 /* Reset PHY */ 862 if (hw->phy.reset_disable == FALSE) { 863 /* PHY ops must be identified and initialized prior to reset */ 864 865 /* Init PHY and function pointers, perform SFP setup */ 866 phy_status = hw->phy.ops.init(hw); 867 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED) 868 goto reset_hw_out; 869 if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT) 870 goto mac_reset_top; 871 872 hw->phy.ops.reset(hw); 873 } 874 875 mac_reset_top: 876 /* 877 * Issue global reset to the MAC. This needs to be a SW reset. 878 * If link reset is used, it might reset the MAC when mng is using it 879 */ 880 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST; 881 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 882 IXGBE_WRITE_FLUSH(hw); 883 884 /* Poll for reset bit to self-clear indicating reset is complete */ 885 for (i = 0; i < 10; i++) { 886 usec_delay(1); 887 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 888 if (!(ctrl & IXGBE_CTRL_RST)) 889 break; 890 } 891 if (ctrl & IXGBE_CTRL_RST) { 892 status = IXGBE_ERR_RESET_FAILED; 893 DEBUGOUT("Reset polling failed to complete.\n"); 894 } 895 896 msec_delay(50); 897 898 /* 899 * Double resets are required for recovery from certain error 900 * conditions. Between resets, it is necessary to stall to allow time 901 * for any pending HW events to complete. 902 */ 903 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 904 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 905 goto mac_reset_top; 906 } 907 908 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 909 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); 910 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 911 912 /* 913 * Store the original AUTOC value if it has not been 914 * stored off yet. Otherwise restore the stored original 915 * AUTOC value since the reset operation sets back to deaults. 916 */ 917 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 918 if (hw->mac.orig_link_settings_stored == FALSE) { 919 hw->mac.orig_autoc = autoc; 920 hw->mac.orig_link_settings_stored = TRUE; 921 } else if (autoc != hw->mac.orig_autoc) { 922 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); 923 } 924 925 /* Store the permanent mac address */ 926 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 927 928 /* 929 * Store MAC address from RAR0, clear receive address registers, and 930 * clear the multicast table 931 */ 932 hw->mac.ops.init_rx_addrs(hw); 933 934 reset_hw_out: 935 if (phy_status != IXGBE_SUCCESS) 936 status = phy_status; 937 938 return status; 939 } 940 941 /** 942 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address 943 * @hw: pointer to hardware struct 944 * @rar: receive address register index to associate with a VMDq index 945 * @vmdq: VMDq set index 946 **/ 947 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 948 { 949 u32 rar_high; 950 u32 rar_entries = hw->mac.num_rar_entries; 951 952 DEBUGFUNC("ixgbe_set_vmdq_82598"); 953 954 /* Make sure we are using a valid rar index range */ 955 if (rar >= rar_entries) { 956 DEBUGOUT1("RAR index %d is out of range.\n", rar); 957 return IXGBE_ERR_INVALID_ARGUMENT; 958 } 959 960 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 961 rar_high &= ~IXGBE_RAH_VIND_MASK; 962 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); 963 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 964 return IXGBE_SUCCESS; 965 } 966 967 /** 968 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address 969 * @hw: pointer to hardware struct 970 * @rar: receive address register index to associate with a VMDq index 971 * @vmdq: VMDq clear index (not used in 82598, but elsewhere) 972 **/ 973 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 974 { 975 u32 rar_high; 976 u32 rar_entries = hw->mac.num_rar_entries; 977 978 UNREFERENCED_1PARAMETER(vmdq); 979 980 /* Make sure we are using a valid rar index range */ 981 if (rar >= rar_entries) { 982 DEBUGOUT1("RAR index %d is out of range.\n", rar); 983 return IXGBE_ERR_INVALID_ARGUMENT; 984 } 985 986 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 987 if (rar_high & IXGBE_RAH_VIND_MASK) { 988 rar_high &= ~IXGBE_RAH_VIND_MASK; 989 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 990 } 991 992 return IXGBE_SUCCESS; 993 } 994 995 /** 996 * ixgbe_set_vfta_82598 - Set VLAN filter table 997 * @hw: pointer to hardware structure 998 * @vlan: VLAN id to write to VLAN filter 999 * @vind: VMDq output index that maps queue to VLAN id in VFTA 1000 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 1001 * @vlvf_bypass: boolean flag - unused 1002 * 1003 * Turn on/off specified VLAN in the VLAN filter table. 1004 **/ 1005 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, 1006 bool vlan_on, bool vlvf_bypass) 1007 { 1008 u32 regindex; 1009 u32 bitindex; 1010 u32 bits; 1011 u32 vftabyte; 1012 1013 UNREFERENCED_1PARAMETER(vlvf_bypass); 1014 1015 DEBUGFUNC("ixgbe_set_vfta_82598"); 1016 1017 if (vlan > 4095) 1018 return IXGBE_ERR_PARAM; 1019 1020 /* Determine 32-bit word position in array */ 1021 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ 1022 1023 /* Determine the location of the (VMD) queue index */ 1024 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ 1025 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ 1026 1027 /* Set the nibble for VMD queue index */ 1028 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); 1029 bits &= (~(0x0F << bitindex)); 1030 bits |= (vind << bitindex); 1031 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); 1032 1033 /* Determine the location of the bit for this VLAN id */ 1034 bitindex = vlan & 0x1F; /* lower five bits */ 1035 1036 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 1037 if (vlan_on) 1038 /* Turn on this VLAN id */ 1039 bits |= (1 << bitindex); 1040 else 1041 /* Turn off this VLAN id */ 1042 bits &= ~(1 << bitindex); 1043 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); 1044 1045 return IXGBE_SUCCESS; 1046 } 1047 1048 /** 1049 * ixgbe_clear_vfta_82598 - Clear VLAN filter table 1050 * @hw: pointer to hardware structure 1051 * 1052 * Clears the VLAN filer table, and the VMDq index associated with the filter 1053 **/ 1054 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) 1055 { 1056 u32 offset; 1057 u32 vlanbyte; 1058 1059 DEBUGFUNC("ixgbe_clear_vfta_82598"); 1060 1061 for (offset = 0; offset < hw->mac.vft_size; offset++) 1062 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 1063 1064 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) 1065 for (offset = 0; offset < hw->mac.vft_size; offset++) 1066 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), 1067 0); 1068 1069 return IXGBE_SUCCESS; 1070 } 1071 1072 /** 1073 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register 1074 * @hw: pointer to hardware structure 1075 * @reg: analog register to read 1076 * @val: read value 1077 * 1078 * Performs read operation to Atlas analog register specified. 1079 **/ 1080 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) 1081 { 1082 u32 atlas_ctl; 1083 1084 DEBUGFUNC("ixgbe_read_analog_reg8_82598"); 1085 1086 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, 1087 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); 1088 IXGBE_WRITE_FLUSH(hw); 1089 usec_delay(10); 1090 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 1091 *val = (u8)atlas_ctl; 1092 1093 return IXGBE_SUCCESS; 1094 } 1095 1096 /** 1097 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register 1098 * @hw: pointer to hardware structure 1099 * @reg: atlas register to write 1100 * @val: value to write 1101 * 1102 * Performs write operation to Atlas analog register specified. 1103 **/ 1104 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) 1105 { 1106 u32 atlas_ctl; 1107 1108 DEBUGFUNC("ixgbe_write_analog_reg8_82598"); 1109 1110 atlas_ctl = (reg << 8) | val; 1111 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); 1112 IXGBE_WRITE_FLUSH(hw); 1113 usec_delay(10); 1114 1115 return IXGBE_SUCCESS; 1116 } 1117 1118 /** 1119 * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface. 1120 * @hw: pointer to hardware structure 1121 * @dev_addr: address to read from 1122 * @byte_offset: byte offset to read from dev_addr 1123 * @eeprom_data: value read 1124 * 1125 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. 1126 **/ 1127 static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr, 1128 u8 byte_offset, u8 *eeprom_data) 1129 { 1130 s32 status = IXGBE_SUCCESS; 1131 u16 sfp_addr = 0; 1132 u16 sfp_data = 0; 1133 u16 sfp_stat = 0; 1134 u16 gssr; 1135 u32 i; 1136 1137 DEBUGFUNC("ixgbe_read_i2c_phy_82598"); 1138 1139 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1140 gssr = IXGBE_GSSR_PHY1_SM; 1141 else 1142 gssr = IXGBE_GSSR_PHY0_SM; 1143 1144 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 1145 return IXGBE_ERR_SWFW_SYNC; 1146 1147 if (hw->phy.type == ixgbe_phy_nl) { 1148 /* 1149 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to 1150 * 0xC30D. These registers are used to talk to the SFP+ 1151 * module's EEPROM through the SDA/SCL (I2C) interface. 1152 */ 1153 sfp_addr = (dev_addr << 8) + byte_offset; 1154 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); 1155 hw->phy.ops.write_reg_mdi(hw, 1156 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, 1157 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 1158 sfp_addr); 1159 1160 /* Poll status */ 1161 for (i = 0; i < 100; i++) { 1162 hw->phy.ops.read_reg_mdi(hw, 1163 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, 1164 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 1165 &sfp_stat); 1166 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; 1167 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) 1168 break; 1169 msec_delay(10); 1170 } 1171 1172 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { 1173 DEBUGOUT("EEPROM read did not pass.\n"); 1174 status = IXGBE_ERR_SFP_NOT_PRESENT; 1175 goto out; 1176 } 1177 1178 /* Read data */ 1179 hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, 1180 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data); 1181 1182 *eeprom_data = (u8)(sfp_data >> 8); 1183 } else { 1184 status = IXGBE_ERR_PHY; 1185 } 1186 1187 out: 1188 hw->mac.ops.release_swfw_sync(hw, gssr); 1189 return status; 1190 } 1191 1192 /** 1193 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface. 1194 * @hw: pointer to hardware structure 1195 * @byte_offset: EEPROM byte offset to read 1196 * @eeprom_data: value read 1197 * 1198 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. 1199 **/ 1200 s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 1201 u8 *eeprom_data) 1202 { 1203 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR, 1204 byte_offset, eeprom_data); 1205 } 1206 1207 /** 1208 * ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface. 1209 * @hw: pointer to hardware structure 1210 * @byte_offset: byte offset at address 0xA2 1211 * @eeprom_data: value read 1212 * 1213 * Performs 8 byte read operation to SFP module's SFF-8472 data over I2C 1214 **/ 1215 static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset, 1216 u8 *sff8472_data) 1217 { 1218 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2, 1219 byte_offset, sff8472_data); 1220 } 1221 1222 /** 1223 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type 1224 * @hw: pointer to hardware structure 1225 * 1226 * Determines physical layer capabilities of the current configuration. 1227 **/ 1228 u64 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) 1229 { 1230 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1231 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1232 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 1233 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1234 u16 ext_ability = 0; 1235 1236 DEBUGFUNC("ixgbe_get_supported_physical_layer_82598"); 1237 1238 hw->phy.ops.identify(hw); 1239 1240 /* Copper PHY must be checked before AUTOC LMS to determine correct 1241 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */ 1242 switch (hw->phy.type) { 1243 case ixgbe_phy_tn: 1244 case ixgbe_phy_cu_unknown: 1245 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 1246 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 1247 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 1248 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1249 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 1250 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1251 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 1252 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1253 goto out; 1254 default: 1255 break; 1256 } 1257 1258 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1259 case IXGBE_AUTOC_LMS_1G_AN: 1260 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 1261 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX) 1262 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1263 else 1264 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1265 break; 1266 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 1267 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4) 1268 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1269 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4) 1270 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1271 else /* XAUI */ 1272 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1273 break; 1274 case IXGBE_AUTOC_LMS_KX4_AN: 1275 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 1276 if (autoc & IXGBE_AUTOC_KX_SUPP) 1277 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1278 if (autoc & IXGBE_AUTOC_KX4_SUPP) 1279 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1280 break; 1281 default: 1282 break; 1283 } 1284 1285 if (hw->phy.type == ixgbe_phy_nl) { 1286 hw->phy.ops.identify_sfp(hw); 1287 1288 switch (hw->phy.sfp_type) { 1289 case ixgbe_sfp_type_da_cu: 1290 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1291 break; 1292 case ixgbe_sfp_type_sr: 1293 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1294 break; 1295 case ixgbe_sfp_type_lr: 1296 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1297 break; 1298 default: 1299 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1300 break; 1301 } 1302 } 1303 1304 switch (hw->device_id) { 1305 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 1306 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1307 break; 1308 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 1309 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 1310 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 1311 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1312 break; 1313 case IXGBE_DEV_ID_82598EB_XF_LR: 1314 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1315 break; 1316 default: 1317 break; 1318 } 1319 1320 out: 1321 return physical_layer; 1322 } 1323 1324 /** 1325 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple 1326 * port devices. 1327 * @hw: pointer to the HW structure 1328 * 1329 * Calls common function and corrects issue with some single port devices 1330 * that enable LAN1 but not LAN0. 1331 **/ 1332 void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw) 1333 { 1334 struct ixgbe_bus_info *bus = &hw->bus; 1335 u16 pci_gen = 0; 1336 u16 pci_ctrl2 = 0; 1337 1338 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie_82598"); 1339 1340 ixgbe_set_lan_id_multi_port_pcie(hw); 1341 1342 /* check if LAN0 is disabled */ 1343 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen); 1344 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) { 1345 1346 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2); 1347 1348 /* if LAN0 is completely disabled force function to 0 */ 1349 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) && 1350 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) && 1351 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) { 1352 1353 bus->func = 0; 1354 } 1355 } 1356 } 1357 1358 /** 1359 * ixgbe_enable_relaxed_ordering_82598 - enable relaxed ordering 1360 * @hw: pointer to hardware structure 1361 * 1362 **/ 1363 void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw) 1364 { 1365 u32 regval; 1366 u32 i; 1367 1368 DEBUGFUNC("ixgbe_enable_relaxed_ordering_82598"); 1369 1370 /* Enable relaxed ordering */ 1371 for (i = 0; ((i < hw->mac.max_tx_queues) && 1372 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { 1373 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); 1374 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN; 1375 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); 1376 } 1377 1378 for (i = 0; ((i < hw->mac.max_rx_queues) && 1379 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { 1380 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 1381 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | 1382 IXGBE_DCA_RXCTRL_HEAD_WRO_EN; 1383 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 1384 } 1385 1386 } 1387 1388 /** 1389 * ixgbe_set_rxpba_82598 - Initialize RX packet buffer 1390 * @hw: pointer to hardware structure 1391 * @num_pb: number of packet buffers to allocate 1392 * @headroom: reserve n KB of headroom 1393 * @strategy: packet buffer allocation strategy 1394 **/ 1395 static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb, 1396 u32 headroom, int strategy) 1397 { 1398 u32 rxpktsize = IXGBE_RXPBSIZE_64KB; 1399 u8 i = 0; 1400 UNREFERENCED_1PARAMETER(headroom); 1401 1402 if (!num_pb) 1403 return; 1404 1405 /* Setup Rx packet buffer sizes */ 1406 switch (strategy) { 1407 case PBA_STRATEGY_WEIGHTED: 1408 /* Setup the first four at 80KB */ 1409 rxpktsize = IXGBE_RXPBSIZE_80KB; 1410 for (; i < 4; i++) 1411 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 1412 /* Setup the last four at 48KB...don't re-init i */ 1413 rxpktsize = IXGBE_RXPBSIZE_48KB; 1414 /* Fall Through */ 1415 case PBA_STRATEGY_EQUAL: 1416 default: 1417 /* Divide the remaining Rx packet buffer evenly among the TCs */ 1418 for (; i < IXGBE_MAX_PACKET_BUFFERS; i++) 1419 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 1420 break; 1421 } 1422 1423 /* Setup Tx packet buffer sizes */ 1424 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) 1425 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB); 1426 } 1427 1428 /** 1429 * ixgbe_enable_rx_dma_82598 - Enable the Rx DMA unit 1430 * @hw: pointer to hardware structure 1431 * @regval: register value to write to RXCTRL 1432 * 1433 * Enables the Rx DMA unit 1434 **/ 1435 s32 ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, u32 regval) 1436 { 1437 DEBUGFUNC("ixgbe_enable_rx_dma_82598"); 1438 1439 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 1440 1441 return IXGBE_SUCCESS; 1442 } 1443
Indexes created Thu Oct 23 22:10:10 GMT 2025