ixgbe_x550.c revision 1.3.2.2
1 1.3.2.2 skrll /****************************************************************************** 2 1.3.2.2 skrll 3 1.3.2.2 skrll Copyright (c) 2001-2015, Intel Corporation 4 1.3.2.2 skrll All rights reserved. 5 1.3.2.2 skrll 6 1.3.2.2 skrll Redistribution and use in source and binary forms, with or without 7 1.3.2.2 skrll modification, are permitted provided that the following conditions are met: 8 1.3.2.2 skrll 9 1.3.2.2 skrll 1. Redistributions of source code must retain the above copyright notice, 10 1.3.2.2 skrll this list of conditions and the following disclaimer. 11 1.3.2.2 skrll 12 1.3.2.2 skrll 2. Redistributions in binary form must reproduce the above copyright 13 1.3.2.2 skrll notice, this list of conditions and the following disclaimer in the 14 1.3.2.2 skrll documentation and/or other materials provided with the distribution. 15 1.3.2.2 skrll 16 1.3.2.2 skrll 3. Neither the name of the Intel Corporation nor the names of its 17 1.3.2.2 skrll contributors may be used to endorse or promote products derived from 18 1.3.2.2 skrll this software without specific prior written permission. 19 1.3.2.2 skrll 20 1.3.2.2 skrll THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 1.3.2.2 skrll AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 1.3.2.2 skrll IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 1.3.2.2 skrll ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 1.3.2.2 skrll LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 1.3.2.2 skrll CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 1.3.2.2 skrll SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 1.3.2.2 skrll INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 1.3.2.2 skrll CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 1.3.2.2 skrll ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 1.3.2.2 skrll POSSIBILITY OF SUCH DAMAGE. 31 1.3.2.2 skrll 32 1.3.2.2 skrll ******************************************************************************/ 33 1.3.2.2 skrll /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x550.c 292674 2015-12-23 22:45:17Z sbruno $*/ 34 1.3.2.2 skrll 35 1.3.2.2 skrll #include "ixgbe_x550.h" 36 1.3.2.2 skrll #include "ixgbe_x540.h" 37 1.3.2.2 skrll #include "ixgbe_type.h" 38 1.3.2.2 skrll #include "ixgbe_api.h" 39 1.3.2.2 skrll #include "ixgbe_common.h" 40 1.3.2.2 skrll #include "ixgbe_phy.h" 41 1.3.2.2 skrll 42 1.3.2.2 skrll static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed); 43 1.3.2.2 skrll 44 1.3.2.2 skrll /** 45 1.3.2.2 skrll * ixgbe_init_ops_X550 - Inits func ptrs and MAC type 46 1.3.2.2 skrll * @hw: pointer to hardware structure 47 1.3.2.2 skrll * 48 1.3.2.2 skrll * Initialize the function pointers and assign the MAC type for X550. 49 1.3.2.2 skrll * Does not touch the hardware. 50 1.3.2.2 skrll **/ 51 1.3.2.2 skrll s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw) 52 1.3.2.2 skrll { 53 1.3.2.2 skrll struct ixgbe_mac_info *mac = &hw->mac; 54 1.3.2.2 skrll struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 55 1.3.2.2 skrll s32 ret_val; 56 1.3.2.2 skrll 57 1.3.2.2 skrll DEBUGFUNC("ixgbe_init_ops_X550"); 58 1.3.2.2 skrll 59 1.3.2.2 skrll ret_val = ixgbe_init_ops_X540(hw); 60 1.3.2.2 skrll mac->ops.dmac_config = ixgbe_dmac_config_X550; 61 1.3.2.2 skrll mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550; 62 1.3.2.2 skrll mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550; 63 1.3.2.2 skrll mac->ops.setup_eee = ixgbe_setup_eee_X550; 64 1.3.2.2 skrll mac->ops.set_source_address_pruning = 65 1.3.2.2 skrll ixgbe_set_source_address_pruning_X550; 66 1.3.2.2 skrll mac->ops.set_ethertype_anti_spoofing = 67 1.3.2.2 skrll ixgbe_set_ethertype_anti_spoofing_X550; 68 1.3.2.2 skrll 69 1.3.2.2 skrll mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; 70 1.3.2.2 skrll eeprom->ops.init_params = ixgbe_init_eeprom_params_X550; 71 1.3.2.2 skrll eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550; 72 1.3.2.2 skrll eeprom->ops.read = ixgbe_read_ee_hostif_X550; 73 1.3.2.2 skrll eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550; 74 1.3.2.2 skrll eeprom->ops.write = ixgbe_write_ee_hostif_X550; 75 1.3.2.2 skrll eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550; 76 1.3.2.2 skrll eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550; 77 1.3.2.2 skrll eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550; 78 1.3.2.2 skrll 79 1.3.2.2 skrll mac->ops.disable_mdd = ixgbe_disable_mdd_X550; 80 1.3.2.2 skrll mac->ops.enable_mdd = ixgbe_enable_mdd_X550; 81 1.3.2.2 skrll mac->ops.mdd_event = ixgbe_mdd_event_X550; 82 1.3.2.2 skrll mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550; 83 1.3.2.2 skrll mac->ops.disable_rx = ixgbe_disable_rx_x550; 84 1.3.2.2 skrll if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) { 85 1.3.2.2 skrll hw->mac.ops.led_on = ixgbe_led_on_t_X550em; 86 1.3.2.2 skrll hw->mac.ops.led_off = ixgbe_led_off_t_X550em; 87 1.3.2.2 skrll } 88 1.3.2.2 skrll return ret_val; 89 1.3.2.2 skrll } 90 1.3.2.2 skrll 91 1.3.2.2 skrll /** 92 1.3.2.2 skrll * ixgbe_read_cs4227 - Read CS4227 register 93 1.3.2.2 skrll * @hw: pointer to hardware structure 94 1.3.2.2 skrll * @reg: register number to write 95 1.3.2.2 skrll * @value: pointer to receive value read 96 1.3.2.2 skrll * 97 1.3.2.2 skrll * Returns status code 98 1.3.2.2 skrll **/ 99 1.3.2.2 skrll static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value) 100 1.3.2.2 skrll { 101 1.3.2.2 skrll return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value); 102 1.3.2.2 skrll } 103 1.3.2.2 skrll 104 1.3.2.2 skrll /** 105 1.3.2.2 skrll * ixgbe_write_cs4227 - Write CS4227 register 106 1.3.2.2 skrll * @hw: pointer to hardware structure 107 1.3.2.2 skrll * @reg: register number to write 108 1.3.2.2 skrll * @value: value to write to register 109 1.3.2.2 skrll * 110 1.3.2.2 skrll * Returns status code 111 1.3.2.2 skrll **/ 112 1.3.2.2 skrll static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) 113 1.3.2.2 skrll { 114 1.3.2.2 skrll return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value); 115 1.3.2.2 skrll } 116 1.3.2.2 skrll 117 1.3.2.2 skrll /** 118 1.3.2.2 skrll * ixgbe_read_pe - Read register from port expander 119 1.3.2.2 skrll * @hw: pointer to hardware structure 120 1.3.2.2 skrll * @reg: register number to read 121 1.3.2.2 skrll * @value: pointer to receive read value 122 1.3.2.2 skrll * 123 1.3.2.2 skrll * Returns status code 124 1.3.2.2 skrll **/ 125 1.3.2.2 skrll static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) 126 1.3.2.2 skrll { 127 1.3.2.2 skrll s32 status; 128 1.3.2.2 skrll 129 1.3.2.2 skrll status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value); 130 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 131 1.3.2.2 skrll ERROR_REPORT2(IXGBE_ERROR_CAUTION, 132 1.3.2.2 skrll "port expander access failed with %d\n", status); 133 1.3.2.2 skrll return status; 134 1.3.2.2 skrll } 135 1.3.2.2 skrll 136 1.3.2.2 skrll /** 137 1.3.2.2 skrll * ixgbe_write_pe - Write register to port expander 138 1.3.2.2 skrll * @hw: pointer to hardware structure 139 1.3.2.2 skrll * @reg: register number to write 140 1.3.2.2 skrll * @value: value to write 141 1.3.2.2 skrll * 142 1.3.2.2 skrll * Returns status code 143 1.3.2.2 skrll **/ 144 1.3.2.2 skrll static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value) 145 1.3.2.2 skrll { 146 1.3.2.2 skrll s32 status; 147 1.3.2.2 skrll 148 1.3.2.2 skrll status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value); 149 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 150 1.3.2.2 skrll ERROR_REPORT2(IXGBE_ERROR_CAUTION, 151 1.3.2.2 skrll "port expander access failed with %d\n", status); 152 1.3.2.2 skrll return status; 153 1.3.2.2 skrll } 154 1.3.2.2 skrll 155 1.3.2.2 skrll /** 156 1.3.2.2 skrll * ixgbe_reset_cs4227 - Reset CS4227 using port expander 157 1.3.2.2 skrll * @hw: pointer to hardware structure 158 1.3.2.2 skrll * 159 1.3.2.2 skrll * This function assumes that the caller has acquired the proper semaphore. 160 1.3.2.2 skrll * Returns error code 161 1.3.2.2 skrll **/ 162 1.3.2.2 skrll static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw) 163 1.3.2.2 skrll { 164 1.3.2.2 skrll s32 status; 165 1.3.2.2 skrll u32 retry; 166 1.3.2.2 skrll u16 value; 167 1.3.2.2 skrll u8 reg; 168 1.3.2.2 skrll 169 1.3.2.2 skrll /* Trigger hard reset. */ 170 1.3.2.2 skrll status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 171 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 172 1.3.2.2 skrll return status; 173 1.3.2.2 skrll reg |= IXGBE_PE_BIT1; 174 1.3.2.2 skrll status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 175 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 176 1.3.2.2 skrll return status; 177 1.3.2.2 skrll 178 1.3.2.2 skrll status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®); 179 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 180 1.3.2.2 skrll return status; 181 1.3.2.2 skrll reg &= ~IXGBE_PE_BIT1; 182 1.3.2.2 skrll status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg); 183 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 184 1.3.2.2 skrll return status; 185 1.3.2.2 skrll 186 1.3.2.2 skrll status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 187 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 188 1.3.2.2 skrll return status; 189 1.3.2.2 skrll reg &= ~IXGBE_PE_BIT1; 190 1.3.2.2 skrll status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 191 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 192 1.3.2.2 skrll return status; 193 1.3.2.2 skrll 194 1.3.2.2 skrll usec_delay(IXGBE_CS4227_RESET_HOLD); 195 1.3.2.2 skrll 196 1.3.2.2 skrll status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 197 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 198 1.3.2.2 skrll return status; 199 1.3.2.2 skrll reg |= IXGBE_PE_BIT1; 200 1.3.2.2 skrll status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 201 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 202 1.3.2.2 skrll return status; 203 1.3.2.2 skrll 204 1.3.2.2 skrll /* Wait for the reset to complete. */ 205 1.3.2.2 skrll msec_delay(IXGBE_CS4227_RESET_DELAY); 206 1.3.2.2 skrll for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 207 1.3.2.2 skrll status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS, 208 1.3.2.2 skrll &value); 209 1.3.2.2 skrll if (status == IXGBE_SUCCESS && 210 1.3.2.2 skrll value == IXGBE_CS4227_EEPROM_LOAD_OK) 211 1.3.2.2 skrll break; 212 1.3.2.2 skrll msec_delay(IXGBE_CS4227_CHECK_DELAY); 213 1.3.2.2 skrll } 214 1.3.2.2 skrll if (retry == IXGBE_CS4227_RETRIES) { 215 1.3.2.2 skrll ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 216 1.3.2.2 skrll "CS4227 reset did not complete."); 217 1.3.2.2 skrll return IXGBE_ERR_PHY; 218 1.3.2.2 skrll } 219 1.3.2.2 skrll 220 1.3.2.2 skrll status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value); 221 1.3.2.2 skrll if (status != IXGBE_SUCCESS || 222 1.3.2.2 skrll !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) { 223 1.3.2.2 skrll ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 224 1.3.2.2 skrll "CS4227 EEPROM did not load successfully."); 225 1.3.2.2 skrll return IXGBE_ERR_PHY; 226 1.3.2.2 skrll } 227 1.3.2.2 skrll 228 1.3.2.2 skrll return IXGBE_SUCCESS; 229 1.3.2.2 skrll } 230 1.3.2.2 skrll 231 1.3.2.2 skrll /** 232 1.3.2.2 skrll * ixgbe_check_cs4227 - Check CS4227 and reset as needed 233 1.3.2.2 skrll * @hw: pointer to hardware structure 234 1.3.2.2 skrll **/ 235 1.3.2.2 skrll static void ixgbe_check_cs4227(struct ixgbe_hw *hw) 236 1.3.2.2 skrll { 237 1.3.2.2 skrll s32 status = IXGBE_SUCCESS; 238 1.3.2.2 skrll u32 swfw_mask = hw->phy.phy_semaphore_mask; 239 1.3.2.2 skrll u16 value = 0; 240 1.3.2.2 skrll u8 retry; 241 1.3.2.2 skrll 242 1.3.2.2 skrll for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 243 1.3.2.2 skrll status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 244 1.3.2.2 skrll if (status != IXGBE_SUCCESS) { 245 1.3.2.2 skrll ERROR_REPORT2(IXGBE_ERROR_CAUTION, 246 1.3.2.2 skrll "semaphore failed with %d", status); 247 1.3.2.2 skrll msec_delay(IXGBE_CS4227_CHECK_DELAY); 248 1.3.2.2 skrll continue; 249 1.3.2.2 skrll } 250 1.3.2.2 skrll 251 1.3.2.2 skrll /* Get status of reset flow. */ 252 1.3.2.2 skrll status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); 253 1.3.2.2 skrll 254 1.3.2.2 skrll if (status == IXGBE_SUCCESS && 255 1.3.2.2 skrll value == IXGBE_CS4227_RESET_COMPLETE) 256 1.3.2.2 skrll goto out; 257 1.3.2.2 skrll 258 1.3.2.2 skrll if (status != IXGBE_SUCCESS || 259 1.3.2.2 skrll value != IXGBE_CS4227_RESET_PENDING) 260 1.3.2.2 skrll break; 261 1.3.2.2 skrll 262 1.3.2.2 skrll /* Reset is pending. Wait and check again. */ 263 1.3.2.2 skrll hw->mac.ops.release_swfw_sync(hw, swfw_mask); 264 1.3.2.2 skrll msec_delay(IXGBE_CS4227_CHECK_DELAY); 265 1.3.2.2 skrll } 266 1.3.2.2 skrll 267 1.3.2.2 skrll /* If still pending, assume other instance failed. */ 268 1.3.2.2 skrll if (retry == IXGBE_CS4227_RETRIES) { 269 1.3.2.2 skrll status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 270 1.3.2.2 skrll if (status != IXGBE_SUCCESS) { 271 1.3.2.2 skrll ERROR_REPORT2(IXGBE_ERROR_CAUTION, 272 1.3.2.2 skrll "semaphore failed with %d", status); 273 1.3.2.2 skrll return; 274 1.3.2.2 skrll } 275 1.3.2.2 skrll } 276 1.3.2.2 skrll 277 1.3.2.2 skrll /* Reset the CS4227. */ 278 1.3.2.2 skrll status = ixgbe_reset_cs4227(hw); 279 1.3.2.2 skrll if (status != IXGBE_SUCCESS) { 280 1.3.2.2 skrll ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 281 1.3.2.2 skrll "CS4227 reset failed: %d", status); 282 1.3.2.2 skrll goto out; 283 1.3.2.2 skrll } 284 1.3.2.2 skrll 285 1.3.2.2 skrll /* Reset takes so long, temporarily release semaphore in case the 286 1.3.2.2 skrll * other driver instance is waiting for the reset indication. 287 1.3.2.2 skrll */ 288 1.3.2.2 skrll ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 289 1.3.2.2 skrll IXGBE_CS4227_RESET_PENDING); 290 1.3.2.2 skrll hw->mac.ops.release_swfw_sync(hw, swfw_mask); 291 1.3.2.2 skrll msec_delay(10); 292 1.3.2.2 skrll status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 293 1.3.2.2 skrll if (status != IXGBE_SUCCESS) { 294 1.3.2.2 skrll ERROR_REPORT2(IXGBE_ERROR_CAUTION, 295 1.3.2.2 skrll "semaphore failed with %d", status); 296 1.3.2.2 skrll return; 297 1.3.2.2 skrll } 298 1.3.2.2 skrll 299 1.3.2.2 skrll /* Record completion for next time. */ 300 1.3.2.2 skrll status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 301 1.3.2.2 skrll IXGBE_CS4227_RESET_COMPLETE); 302 1.3.2.2 skrll 303 1.3.2.2 skrll out: 304 1.3.2.2 skrll hw->mac.ops.release_swfw_sync(hw, swfw_mask); 305 1.3.2.2 skrll msec_delay(hw->eeprom.semaphore_delay); 306 1.3.2.2 skrll } 307 1.3.2.2 skrll 308 1.3.2.2 skrll /** 309 1.3.2.2 skrll * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control 310 1.3.2.2 skrll * @hw: pointer to hardware structure 311 1.3.2.2 skrll **/ 312 1.3.2.2 skrll static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) 313 1.3.2.2 skrll { 314 1.3.2.2 skrll u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 315 1.3.2.2 skrll 316 1.3.2.2 skrll if (hw->bus.lan_id) { 317 1.3.2.2 skrll esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); 318 1.3.2.2 skrll esdp |= IXGBE_ESDP_SDP1_DIR; 319 1.3.2.2 skrll } 320 1.3.2.2 skrll esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); 321 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 322 1.3.2.2 skrll IXGBE_WRITE_FLUSH(hw); 323 1.3.2.2 skrll } 324 1.3.2.2 skrll 325 1.3.2.2 skrll /** 326 1.3.2.2 skrll * ixgbe_identify_phy_x550em - Get PHY type based on device id 327 1.3.2.2 skrll * @hw: pointer to hardware structure 328 1.3.2.2 skrll * 329 1.3.2.2 skrll * Returns error code 330 1.3.2.2 skrll */ 331 1.3.2.2 skrll static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) 332 1.3.2.2 skrll { 333 1.3.2.2 skrll switch (hw->device_id) { 334 1.3.2.2 skrll case IXGBE_DEV_ID_X550EM_X_SFP: 335 1.3.2.2 skrll /* set up for CS4227 usage */ 336 1.3.2.2 skrll hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 337 1.3.2.2 skrll ixgbe_setup_mux_ctl(hw); 338 1.3.2.2 skrll ixgbe_check_cs4227(hw); 339 1.3.2.2 skrll 340 1.3.2.2 skrll return ixgbe_identify_module_generic(hw); 341 1.3.2.2 skrll break; 342 1.3.2.2 skrll case IXGBE_DEV_ID_X550EM_X_KX4: 343 1.3.2.2 skrll hw->phy.type = ixgbe_phy_x550em_kx4; 344 1.3.2.2 skrll break; 345 1.3.2.2 skrll case IXGBE_DEV_ID_X550EM_X_KR: 346 1.3.2.2 skrll hw->phy.type = ixgbe_phy_x550em_kr; 347 1.3.2.2 skrll break; 348 1.3.2.2 skrll case IXGBE_DEV_ID_X550EM_X_1G_T: 349 1.3.2.2 skrll case IXGBE_DEV_ID_X550EM_X_10G_T: 350 1.3.2.2 skrll return ixgbe_identify_phy_generic(hw); 351 1.3.2.2 skrll default: 352 1.3.2.2 skrll break; 353 1.3.2.2 skrll } 354 1.3.2.2 skrll return IXGBE_SUCCESS; 355 1.3.2.2 skrll } 356 1.3.2.2 skrll 357 1.3.2.2 skrll static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 358 1.3.2.2 skrll u32 device_type, u16 *phy_data) 359 1.3.2.2 skrll { 360 1.3.2.2 skrll UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data); 361 1.3.2.2 skrll return IXGBE_NOT_IMPLEMENTED; 362 1.3.2.2 skrll } 363 1.3.2.2 skrll 364 1.3.2.2 skrll static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 365 1.3.2.2 skrll u32 device_type, u16 phy_data) 366 1.3.2.2 skrll { 367 1.3.2.2 skrll UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data); 368 1.3.2.2 skrll return IXGBE_NOT_IMPLEMENTED; 369 1.3.2.2 skrll } 370 1.3.2.2 skrll 371 1.3.2.2 skrll /** 372 1.3.2.2 skrll * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type 373 1.3.2.2 skrll * @hw: pointer to hardware structure 374 1.3.2.2 skrll * 375 1.3.2.2 skrll * Initialize the function pointers and for MAC type X550EM. 376 1.3.2.2 skrll * Does not touch the hardware. 377 1.3.2.2 skrll **/ 378 1.3.2.2 skrll s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw) 379 1.3.2.2 skrll { 380 1.3.2.2 skrll struct ixgbe_mac_info *mac = &hw->mac; 381 1.3.2.2 skrll struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 382 1.3.2.2 skrll struct ixgbe_phy_info *phy = &hw->phy; 383 1.3.2.2 skrll s32 ret_val; 384 1.3.2.2 skrll 385 1.3.2.2 skrll DEBUGFUNC("ixgbe_init_ops_X550EM"); 386 1.3.2.2 skrll 387 1.3.2.2 skrll /* Similar to X550 so start there. */ 388 1.3.2.2 skrll ret_val = ixgbe_init_ops_X550(hw); 389 1.3.2.2 skrll 390 1.3.2.2 skrll /* Since this function eventually calls 391 1.3.2.2 skrll * ixgbe_init_ops_540 by design, we are setting 392 1.3.2.2 skrll * the pointers to NULL explicitly here to overwrite 393 1.3.2.2 skrll * the values being set in the x540 function. 394 1.3.2.2 skrll */ 395 1.3.2.2 skrll 396 1.3.2.2 skrll /* FCOE not supported in x550EM */ 397 1.3.2.2 skrll mac->ops.get_san_mac_addr = NULL; 398 1.3.2.2 skrll mac->ops.set_san_mac_addr = NULL; 399 1.3.2.2 skrll mac->ops.get_wwn_prefix = NULL; 400 1.3.2.2 skrll mac->ops.get_fcoe_boot_status = NULL; 401 1.3.2.2 skrll 402 1.3.2.2 skrll /* IPsec not supported in x550EM */ 403 1.3.2.2 skrll mac->ops.disable_sec_rx_path = NULL; 404 1.3.2.2 skrll mac->ops.enable_sec_rx_path = NULL; 405 1.3.2.2 skrll 406 1.3.2.2 skrll /* AUTOC register is not present in x550EM. */ 407 1.3.2.2 skrll mac->ops.prot_autoc_read = NULL; 408 1.3.2.2 skrll mac->ops.prot_autoc_write = NULL; 409 1.3.2.2 skrll 410 1.3.2.2 skrll /* X550EM bus type is internal*/ 411 1.3.2.2 skrll hw->bus.type = ixgbe_bus_type_internal; 412 1.3.2.2 skrll mac->ops.get_bus_info = ixgbe_get_bus_info_X550em; 413 1.3.2.2 skrll 414 1.3.2.2 skrll if (hw->mac.type == ixgbe_mac_X550EM_x) { 415 1.3.2.2 skrll mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550; 416 1.3.2.2 skrll mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550; 417 1.3.2.2 skrll } 418 1.3.2.2 skrll 419 1.3.2.2 skrll mac->ops.get_media_type = ixgbe_get_media_type_X550em; 420 1.3.2.2 skrll mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em; 421 1.3.2.2 skrll mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em; 422 1.3.2.2 skrll mac->ops.reset_hw = ixgbe_reset_hw_X550em; 423 1.3.2.2 skrll mac->ops.get_supported_physical_layer = 424 1.3.2.2 skrll ixgbe_get_supported_physical_layer_X550em; 425 1.3.2.2 skrll 426 1.3.2.2 skrll if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) 427 1.3.2.2 skrll mac->ops.setup_fc = ixgbe_setup_fc_generic; 428 1.3.2.2 skrll else 429 1.3.2.2 skrll mac->ops.setup_fc = ixgbe_setup_fc_X550em; 430 1.3.2.2 skrll 431 1.3.2.2 skrll mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em; 432 1.3.2.2 skrll mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em; 433 1.3.2.2 skrll 434 1.3.2.2 skrll if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR) 435 1.3.2.2 skrll mac->ops.setup_eee = NULL; 436 1.3.2.2 skrll 437 1.3.2.2 skrll /* PHY */ 438 1.3.2.2 skrll phy->ops.init = ixgbe_init_phy_ops_X550em; 439 1.3.2.2 skrll phy->ops.identify = ixgbe_identify_phy_x550em; 440 1.3.2.2 skrll if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 441 1.3.2.2 skrll phy->ops.set_phy_power = NULL; 442 1.3.2.2 skrll 443 1.3.2.2 skrll 444 1.3.2.2 skrll /* EEPROM */ 445 1.3.2.2 skrll eeprom->ops.init_params = ixgbe_init_eeprom_params_X540; 446 1.3.2.2 skrll eeprom->ops.read = ixgbe_read_ee_hostif_X550; 447 1.3.2.2 skrll eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550; 448 1.3.2.2 skrll eeprom->ops.write = ixgbe_write_ee_hostif_X550; 449 1.3.2.2 skrll eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550; 450 1.3.2.2 skrll eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550; 451 1.3.2.2 skrll eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550; 452 1.3.2.2 skrll eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550; 453 1.3.2.2 skrll 454 1.3.2.2 skrll return ret_val; 455 1.3.2.2 skrll } 456 1.3.2.2 skrll 457 1.3.2.2 skrll /** 458 1.3.2.2 skrll * ixgbe_dmac_config_X550 459 1.3.2.2 skrll * @hw: pointer to hardware structure 460 1.3.2.2 skrll * 461 1.3.2.2 skrll * Configure DMA coalescing. If enabling dmac, dmac is activated. 462 1.3.2.2 skrll * When disabling dmac, dmac enable dmac bit is cleared. 463 1.3.2.2 skrll **/ 464 1.3.2.2 skrll s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw) 465 1.3.2.2 skrll { 466 1.3.2.2 skrll u32 reg, high_pri_tc; 467 1.3.2.2 skrll 468 1.3.2.2 skrll DEBUGFUNC("ixgbe_dmac_config_X550"); 469 1.3.2.2 skrll 470 1.3.2.2 skrll /* Disable DMA coalescing before configuring */ 471 1.3.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 472 1.3.2.2 skrll reg &= ~IXGBE_DMACR_DMAC_EN; 473 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 474 1.3.2.2 skrll 475 1.3.2.2 skrll /* Disable DMA Coalescing if the watchdog timer is 0 */ 476 1.3.2.2 skrll if (!hw->mac.dmac_config.watchdog_timer) 477 1.3.2.2 skrll goto out; 478 1.3.2.2 skrll 479 1.3.2.2 skrll ixgbe_dmac_config_tcs_X550(hw); 480 1.3.2.2 skrll 481 1.3.2.2 skrll /* Configure DMA Coalescing Control Register */ 482 1.3.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 483 1.3.2.2 skrll 484 1.3.2.2 skrll /* Set the watchdog timer in units of 40.96 usec */ 485 1.3.2.2 skrll reg &= ~IXGBE_DMACR_DMACWT_MASK; 486 1.3.2.2 skrll reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096; 487 1.3.2.2 skrll 488 1.3.2.2 skrll reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK; 489 1.3.2.2 skrll /* If fcoe is enabled, set high priority traffic class */ 490 1.3.2.2 skrll if (hw->mac.dmac_config.fcoe_en) { 491 1.3.2.2 skrll high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc; 492 1.3.2.2 skrll reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) & 493 1.3.2.2 skrll IXGBE_DMACR_HIGH_PRI_TC_MASK); 494 1.3.2.2 skrll } 495 1.3.2.2 skrll reg |= IXGBE_DMACR_EN_MNG_IND; 496 1.3.2.2 skrll 497 1.3.2.2 skrll /* Enable DMA coalescing after configuration */ 498 1.3.2.2 skrll reg |= IXGBE_DMACR_DMAC_EN; 499 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 500 1.3.2.2 skrll 501 1.3.2.2 skrll out: 502 1.3.2.2 skrll return IXGBE_SUCCESS; 503 1.3.2.2 skrll } 504 1.3.2.2 skrll 505 1.3.2.2 skrll /** 506 1.3.2.2 skrll * ixgbe_dmac_config_tcs_X550 507 1.3.2.2 skrll * @hw: pointer to hardware structure 508 1.3.2.2 skrll * 509 1.3.2.2 skrll * Configure DMA coalescing threshold per TC. The dmac enable bit must 510 1.3.2.2 skrll * be cleared before configuring. 511 1.3.2.2 skrll **/ 512 1.3.2.2 skrll s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw) 513 1.3.2.2 skrll { 514 1.3.2.2 skrll u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb; 515 1.3.2.2 skrll 516 1.3.2.2 skrll DEBUGFUNC("ixgbe_dmac_config_tcs_X550"); 517 1.3.2.2 skrll 518 1.3.2.2 skrll /* Configure DMA coalescing enabled */ 519 1.3.2.2 skrll switch (hw->mac.dmac_config.link_speed) { 520 1.3.2.2 skrll case IXGBE_LINK_SPEED_100_FULL: 521 1.3.2.2 skrll pb_headroom = IXGBE_DMACRXT_100M; 522 1.3.2.2 skrll break; 523 1.3.2.2 skrll case IXGBE_LINK_SPEED_1GB_FULL: 524 1.3.2.2 skrll pb_headroom = IXGBE_DMACRXT_1G; 525 1.3.2.2 skrll break; 526 1.3.2.2 skrll default: 527 1.3.2.2 skrll pb_headroom = IXGBE_DMACRXT_10G; 528 1.3.2.2 skrll break; 529 1.3.2.2 skrll } 530 1.3.2.2 skrll 531 1.3.2.2 skrll maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >> 532 1.3.2.2 skrll IXGBE_MHADD_MFS_SHIFT) / 1024); 533 1.3.2.2 skrll 534 1.3.2.2 skrll /* Set the per Rx packet buffer receive threshold */ 535 1.3.2.2 skrll for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) { 536 1.3.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc)); 537 1.3.2.2 skrll reg &= ~IXGBE_DMCTH_DMACRXT_MASK; 538 1.3.2.2 skrll 539 1.3.2.2 skrll if (tc < hw->mac.dmac_config.num_tcs) { 540 1.3.2.2 skrll /* Get Rx PB size */ 541 1.3.2.2 skrll rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc)); 542 1.3.2.2 skrll rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >> 543 1.3.2.2 skrll IXGBE_RXPBSIZE_SHIFT; 544 1.3.2.2 skrll 545 1.3.2.2 skrll /* Calculate receive buffer threshold in kilobytes */ 546 1.3.2.2 skrll if (rx_pb_size > pb_headroom) 547 1.3.2.2 skrll rx_pb_size = rx_pb_size - pb_headroom; 548 1.3.2.2 skrll else 549 1.3.2.2 skrll rx_pb_size = 0; 550 1.3.2.2 skrll 551 1.3.2.2 skrll /* Minimum of MFS shall be set for DMCTH */ 552 1.3.2.2 skrll reg |= (rx_pb_size > maxframe_size_kb) ? 553 1.3.2.2 skrll rx_pb_size : maxframe_size_kb; 554 1.3.2.2 skrll } 555 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg); 556 1.3.2.2 skrll } 557 1.3.2.2 skrll return IXGBE_SUCCESS; 558 1.3.2.2 skrll } 559 1.3.2.2 skrll 560 1.3.2.2 skrll /** 561 1.3.2.2 skrll * ixgbe_dmac_update_tcs_X550 562 1.3.2.2 skrll * @hw: pointer to hardware structure 563 1.3.2.2 skrll * 564 1.3.2.2 skrll * Disables dmac, updates per TC settings, and then enables dmac. 565 1.3.2.2 skrll **/ 566 1.3.2.2 skrll s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw) 567 1.3.2.2 skrll { 568 1.3.2.2 skrll u32 reg; 569 1.3.2.2 skrll 570 1.3.2.2 skrll DEBUGFUNC("ixgbe_dmac_update_tcs_X550"); 571 1.3.2.2 skrll 572 1.3.2.2 skrll /* Disable DMA coalescing before configuring */ 573 1.3.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 574 1.3.2.2 skrll reg &= ~IXGBE_DMACR_DMAC_EN; 575 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 576 1.3.2.2 skrll 577 1.3.2.2 skrll ixgbe_dmac_config_tcs_X550(hw); 578 1.3.2.2 skrll 579 1.3.2.2 skrll /* Enable DMA coalescing after configuration */ 580 1.3.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 581 1.3.2.2 skrll reg |= IXGBE_DMACR_DMAC_EN; 582 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 583 1.3.2.2 skrll 584 1.3.2.2 skrll return IXGBE_SUCCESS; 585 1.3.2.2 skrll } 586 1.3.2.2 skrll 587 1.3.2.2 skrll /** 588 1.3.2.2 skrll * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params 589 1.3.2.2 skrll * @hw: pointer to hardware structure 590 1.3.2.2 skrll * 591 1.3.2.2 skrll * Initializes the EEPROM parameters ixgbe_eeprom_info within the 592 1.3.2.2 skrll * ixgbe_hw struct in order to set up EEPROM access. 593 1.3.2.2 skrll **/ 594 1.3.2.2 skrll s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) 595 1.3.2.2 skrll { 596 1.3.2.2 skrll struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 597 1.3.2.2 skrll u32 eec; 598 1.3.2.2 skrll u16 eeprom_size; 599 1.3.2.2 skrll 600 1.3.2.2 skrll DEBUGFUNC("ixgbe_init_eeprom_params_X550"); 601 1.3.2.2 skrll 602 1.3.2.2 skrll if (eeprom->type == ixgbe_eeprom_uninitialized) { 603 1.3.2.2 skrll eeprom->semaphore_delay = 10; 604 1.3.2.2 skrll eeprom->type = ixgbe_flash; 605 1.3.2.2 skrll 606 1.3.2.2 skrll eec = IXGBE_READ_REG(hw, IXGBE_EEC); 607 1.3.2.2 skrll eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 608 1.3.2.2 skrll IXGBE_EEC_SIZE_SHIFT); 609 1.3.2.2 skrll eeprom->word_size = 1 << (eeprom_size + 610 1.3.2.2 skrll IXGBE_EEPROM_WORD_SIZE_SHIFT); 611 1.3.2.2 skrll 612 1.3.2.2 skrll DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 613 1.3.2.2 skrll eeprom->type, eeprom->word_size); 614 1.3.2.2 skrll } 615 1.3.2.2 skrll 616 1.3.2.2 skrll return IXGBE_SUCCESS; 617 1.3.2.2 skrll } 618 1.3.2.2 skrll 619 1.3.2.2 skrll /** 620 1.3.2.2 skrll * ixgbe_setup_eee_X550 - Enable/disable EEE support 621 1.3.2.2 skrll * @hw: pointer to the HW structure 622 1.3.2.2 skrll * @enable_eee: boolean flag to enable EEE 623 1.3.2.2 skrll * 624 1.3.2.2 skrll * Enable/disable EEE based on enable_eee flag. 625 1.3.2.2 skrll * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 626 1.3.2.2 skrll * are modified. 627 1.3.2.2 skrll * 628 1.3.2.2 skrll **/ 629 1.3.2.2 skrll s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee) 630 1.3.2.2 skrll { 631 1.3.2.2 skrll u32 eeer; 632 1.3.2.2 skrll u16 autoneg_eee_reg; 633 1.3.2.2 skrll u32 link_reg; 634 1.3.2.2 skrll s32 status; 635 1.3.2.2 skrll u32 fuse; 636 1.3.2.2 skrll 637 1.3.2.2 skrll DEBUGFUNC("ixgbe_setup_eee_X550"); 638 1.3.2.2 skrll 639 1.3.2.2 skrll eeer = IXGBE_READ_REG(hw, IXGBE_EEER); 640 1.3.2.2 skrll /* Enable or disable EEE per flag */ 641 1.3.2.2 skrll if (enable_eee) { 642 1.3.2.2 skrll eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN); 643 1.3.2.2 skrll 644 1.3.2.2 skrll if (hw->mac.type == ixgbe_mac_X550) { 645 1.3.2.2 skrll /* Advertise EEE capability */ 646 1.3.2.2 skrll hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, 647 1.3.2.2 skrll IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg); 648 1.3.2.2 skrll 649 1.3.2.2 skrll autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT | 650 1.3.2.2 skrll IXGBE_AUTO_NEG_1000BASE_EEE_ADVT | 651 1.3.2.2 skrll IXGBE_AUTO_NEG_100BASE_EEE_ADVT); 652 1.3.2.2 skrll 653 1.3.2.2 skrll hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, 654 1.3.2.2 skrll IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg); 655 1.3.2.2 skrll } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) { 656 1.3.2.2 skrll /* Not supported on first revision. */ 657 1.3.2.2 skrll fuse = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)); 658 1.3.2.2 skrll if (!(fuse & IXGBE_FUSES0_REV1)) 659 1.3.2.2 skrll return IXGBE_SUCCESS; 660 1.3.2.2 skrll 661 1.3.2.2 skrll status = ixgbe_read_iosf_sb_reg_x550(hw, 662 1.3.2.2 skrll IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 663 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg); 664 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 665 1.3.2.2 skrll return status; 666 1.3.2.2 skrll 667 1.3.2.2 skrll link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR | 668 1.3.2.2 skrll IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX; 669 1.3.2.2 skrll 670 1.3.2.2 skrll /* Don't advertise FEC capability when EEE enabled. */ 671 1.3.2.2 skrll link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC; 672 1.3.2.2 skrll 673 1.3.2.2 skrll status = ixgbe_write_iosf_sb_reg_x550(hw, 674 1.3.2.2 skrll IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 675 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg); 676 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 677 1.3.2.2 skrll return status; 678 1.3.2.2 skrll } 679 1.3.2.2 skrll } else { 680 1.3.2.2 skrll eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN); 681 1.3.2.2 skrll 682 1.3.2.2 skrll if (hw->mac.type == ixgbe_mac_X550) { 683 1.3.2.2 skrll /* Disable advertised EEE capability */ 684 1.3.2.2 skrll hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, 685 1.3.2.2 skrll IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg); 686 1.3.2.2 skrll 687 1.3.2.2 skrll autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT | 688 1.3.2.2 skrll IXGBE_AUTO_NEG_1000BASE_EEE_ADVT | 689 1.3.2.2 skrll IXGBE_AUTO_NEG_100BASE_EEE_ADVT); 690 1.3.2.2 skrll 691 1.3.2.2 skrll hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, 692 1.3.2.2 skrll IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg); 693 1.3.2.2 skrll } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) { 694 1.3.2.2 skrll status = ixgbe_read_iosf_sb_reg_x550(hw, 695 1.3.2.2 skrll IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 696 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg); 697 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 698 1.3.2.2 skrll return status; 699 1.3.2.2 skrll 700 1.3.2.2 skrll link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR | 701 1.3.2.2 skrll IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX); 702 1.3.2.2 skrll 703 1.3.2.2 skrll /* Advertise FEC capability when EEE is disabled. */ 704 1.3.2.2 skrll link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC; 705 1.3.2.2 skrll 706 1.3.2.2 skrll status = ixgbe_write_iosf_sb_reg_x550(hw, 707 1.3.2.2 skrll IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 708 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg); 709 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 710 1.3.2.2 skrll return status; 711 1.3.2.2 skrll } 712 1.3.2.2 skrll } 713 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer); 714 1.3.2.2 skrll 715 1.3.2.2 skrll return IXGBE_SUCCESS; 716 1.3.2.2 skrll } 717 1.3.2.2 skrll 718 1.3.2.2 skrll /** 719 1.3.2.2 skrll * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning 720 1.3.2.2 skrll * @hw: pointer to hardware structure 721 1.3.2.2 skrll * @enable: enable or disable source address pruning 722 1.3.2.2 skrll * @pool: Rx pool to set source address pruning for 723 1.3.2.2 skrll **/ 724 1.3.2.2 skrll void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable, 725 1.3.2.2 skrll unsigned int pool) 726 1.3.2.2 skrll { 727 1.3.2.2 skrll u64 pfflp; 728 1.3.2.2 skrll 729 1.3.2.2 skrll /* max rx pool is 63 */ 730 1.3.2.2 skrll if (pool > 63) 731 1.3.2.2 skrll return; 732 1.3.2.2 skrll 733 1.3.2.2 skrll pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL); 734 1.3.2.2 skrll pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32; 735 1.3.2.2 skrll 736 1.3.2.2 skrll if (enable) 737 1.3.2.2 skrll pfflp |= (1ULL << pool); 738 1.3.2.2 skrll else 739 1.3.2.2 skrll pfflp &= ~(1ULL << pool); 740 1.3.2.2 skrll 741 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); 742 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); 743 1.3.2.2 skrll } 744 1.3.2.2 skrll 745 1.3.2.2 skrll /** 746 1.3.2.2 skrll * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing 747 1.3.2.2 skrll * @hw: pointer to hardware structure 748 1.3.2.2 skrll * @enable: enable or disable switch for Ethertype anti-spoofing 749 1.3.2.2 skrll * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 750 1.3.2.2 skrll * 751 1.3.2.2 skrll **/ 752 1.3.2.2 skrll void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, 753 1.3.2.2 skrll bool enable, int vf) 754 1.3.2.2 skrll { 755 1.3.2.2 skrll int vf_target_reg = vf >> 3; 756 1.3.2.2 skrll int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT; 757 1.3.2.2 skrll u32 pfvfspoof; 758 1.3.2.2 skrll 759 1.3.2.2 skrll DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550"); 760 1.3.2.2 skrll 761 1.3.2.2 skrll pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 762 1.3.2.2 skrll if (enable) 763 1.3.2.2 skrll pfvfspoof |= (1 << vf_target_shift); 764 1.3.2.2 skrll else 765 1.3.2.2 skrll pfvfspoof &= ~(1 << vf_target_shift); 766 1.3.2.2 skrll 767 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 768 1.3.2.2 skrll } 769 1.3.2.2 skrll 770 1.3.2.2 skrll /** 771 1.3.2.2 skrll * ixgbe_iosf_wait - Wait for IOSF command completion 772 1.3.2.2 skrll * @hw: pointer to hardware structure 773 1.3.2.2 skrll * @ctrl: pointer to location to receive final IOSF control value 774 1.3.2.2 skrll * 775 1.3.2.2 skrll * Returns failing status on timeout 776 1.3.2.2 skrll * 777 1.3.2.2 skrll * Note: ctrl can be NULL if the IOSF control register value is not needed 778 1.3.2.2 skrll **/ 779 1.3.2.2 skrll static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) 780 1.3.2.2 skrll { 781 1.3.2.2 skrll u32 i, command = 0; 782 1.3.2.2 skrll 783 1.3.2.2 skrll /* Check every 10 usec to see if the address cycle completed. 784 1.3.2.2 skrll * The SB IOSF BUSY bit will clear when the operation is 785 1.3.2.2 skrll * complete 786 1.3.2.2 skrll */ 787 1.3.2.2 skrll for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 788 1.3.2.2 skrll command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); 789 1.3.2.2 skrll if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0) 790 1.3.2.2 skrll break; 791 1.3.2.2 skrll usec_delay(10); 792 1.3.2.2 skrll } 793 1.3.2.2 skrll if (ctrl) 794 1.3.2.2 skrll *ctrl = command; 795 1.3.2.2 skrll if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { 796 1.3.2.2 skrll ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n"); 797 1.3.2.2 skrll return IXGBE_ERR_PHY; 798 1.3.2.2 skrll } 799 1.3.2.2 skrll 800 1.3.2.2 skrll return IXGBE_SUCCESS; 801 1.3.2.2 skrll } 802 1.3.2.2 skrll 803 1.3.2.2 skrll /** 804 1.3.2.2 skrll * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF 805 1.3.2.2 skrll * device 806 1.3.2.2 skrll * @hw: pointer to hardware structure 807 1.3.2.2 skrll * @reg_addr: 32 bit PHY register to write 808 1.3.2.2 skrll * @device_type: 3 bit device type 809 1.3.2.2 skrll * @data: Data to write to the register 810 1.3.2.2 skrll **/ 811 1.3.2.2 skrll s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 812 1.3.2.2 skrll u32 device_type, u32 data) 813 1.3.2.2 skrll { 814 1.3.2.2 skrll u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 815 1.3.2.2 skrll u32 command, error __unused; 816 1.3.2.2 skrll s32 ret; 817 1.3.2.2 skrll 818 1.3.2.2 skrll ret = ixgbe_acquire_swfw_semaphore(hw, gssr); 819 1.3.2.2 skrll if (ret != IXGBE_SUCCESS) 820 1.3.2.2 skrll return ret; 821 1.3.2.2 skrll 822 1.3.2.2 skrll ret = ixgbe_iosf_wait(hw, NULL); 823 1.3.2.2 skrll if (ret != IXGBE_SUCCESS) 824 1.3.2.2 skrll goto out; 825 1.3.2.2 skrll 826 1.3.2.2 skrll command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 827 1.3.2.2 skrll (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 828 1.3.2.2 skrll 829 1.3.2.2 skrll /* Write IOSF control register */ 830 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 831 1.3.2.2 skrll 832 1.3.2.2 skrll /* Write IOSF data register */ 833 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); 834 1.3.2.2 skrll 835 1.3.2.2 skrll ret = ixgbe_iosf_wait(hw, &command); 836 1.3.2.2 skrll 837 1.3.2.2 skrll if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 838 1.3.2.2 skrll error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 839 1.3.2.2 skrll IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 840 1.3.2.2 skrll ERROR_REPORT2(IXGBE_ERROR_POLLING, 841 1.3.2.2 skrll "Failed to write, error %x\n", error); 842 1.3.2.2 skrll ret = IXGBE_ERR_PHY; 843 1.3.2.2 skrll } 844 1.3.2.2 skrll 845 1.3.2.2 skrll out: 846 1.3.2.2 skrll ixgbe_release_swfw_semaphore(hw, gssr); 847 1.3.2.2 skrll return ret; 848 1.3.2.2 skrll } 849 1.3.2.2 skrll 850 1.3.2.2 skrll /** 851 1.3.2.2 skrll * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF 852 1.3.2.2 skrll * device 853 1.3.2.2 skrll * @hw: pointer to hardware structure 854 1.3.2.2 skrll * @reg_addr: 32 bit PHY register to write 855 1.3.2.2 skrll * @device_type: 3 bit device type 856 1.3.2.2 skrll * @phy_data: Pointer to read data from the register 857 1.3.2.2 skrll **/ 858 1.3.2.2 skrll s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 859 1.3.2.2 skrll u32 device_type, u32 *data) 860 1.3.2.2 skrll { 861 1.3.2.2 skrll u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 862 1.3.2.2 skrll u32 command, error __unused; 863 1.3.2.2 skrll s32 ret; 864 1.3.2.2 skrll 865 1.3.2.2 skrll ret = ixgbe_acquire_swfw_semaphore(hw, gssr); 866 1.3.2.2 skrll if (ret != IXGBE_SUCCESS) 867 1.3.2.2 skrll return ret; 868 1.3.2.2 skrll 869 1.3.2.2 skrll ret = ixgbe_iosf_wait(hw, NULL); 870 1.3.2.2 skrll if (ret != IXGBE_SUCCESS) 871 1.3.2.2 skrll goto out; 872 1.3.2.2 skrll 873 1.3.2.2 skrll command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 874 1.3.2.2 skrll (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 875 1.3.2.2 skrll 876 1.3.2.2 skrll /* Write IOSF control register */ 877 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 878 1.3.2.2 skrll 879 1.3.2.2 skrll ret = ixgbe_iosf_wait(hw, &command); 880 1.3.2.2 skrll 881 1.3.2.2 skrll if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 882 1.3.2.2 skrll error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 883 1.3.2.2 skrll IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 884 1.3.2.2 skrll ERROR_REPORT2(IXGBE_ERROR_POLLING, 885 1.3.2.2 skrll "Failed to read, error %x\n", error); 886 1.3.2.2 skrll ret = IXGBE_ERR_PHY; 887 1.3.2.2 skrll } 888 1.3.2.2 skrll 889 1.3.2.2 skrll if (ret == IXGBE_SUCCESS) 890 1.3.2.2 skrll *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); 891 1.3.2.2 skrll 892 1.3.2.2 skrll out: 893 1.3.2.2 skrll ixgbe_release_swfw_semaphore(hw, gssr); 894 1.3.2.2 skrll return ret; 895 1.3.2.2 skrll } 896 1.3.2.2 skrll 897 1.3.2.2 skrll /** 898 1.3.2.2 skrll * ixgbe_disable_mdd_X550 899 1.3.2.2 skrll * @hw: pointer to hardware structure 900 1.3.2.2 skrll * 901 1.3.2.2 skrll * Disable malicious driver detection 902 1.3.2.2 skrll **/ 903 1.3.2.2 skrll void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw) 904 1.3.2.2 skrll { 905 1.3.2.2 skrll u32 reg; 906 1.3.2.2 skrll 907 1.3.2.2 skrll DEBUGFUNC("ixgbe_disable_mdd_X550"); 908 1.3.2.2 skrll 909 1.3.2.2 skrll /* Disable MDD for TX DMA and interrupt */ 910 1.3.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 911 1.3.2.2 skrll reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN); 912 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 913 1.3.2.2 skrll 914 1.3.2.2 skrll /* Disable MDD for RX and interrupt */ 915 1.3.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 916 1.3.2.2 skrll reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN); 917 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 918 1.3.2.2 skrll } 919 1.3.2.2 skrll 920 1.3.2.2 skrll /** 921 1.3.2.2 skrll * ixgbe_enable_mdd_X550 922 1.3.2.2 skrll * @hw: pointer to hardware structure 923 1.3.2.2 skrll * 924 1.3.2.2 skrll * Enable malicious driver detection 925 1.3.2.2 skrll **/ 926 1.3.2.2 skrll void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw) 927 1.3.2.2 skrll { 928 1.3.2.2 skrll u32 reg; 929 1.3.2.2 skrll 930 1.3.2.2 skrll DEBUGFUNC("ixgbe_enable_mdd_X550"); 931 1.3.2.2 skrll 932 1.3.2.2 skrll /* Enable MDD for TX DMA and interrupt */ 933 1.3.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 934 1.3.2.2 skrll reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN); 935 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 936 1.3.2.2 skrll 937 1.3.2.2 skrll /* Enable MDD for RX and interrupt */ 938 1.3.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 939 1.3.2.2 skrll reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN); 940 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 941 1.3.2.2 skrll } 942 1.3.2.2 skrll 943 1.3.2.2 skrll /** 944 1.3.2.2 skrll * ixgbe_restore_mdd_vf_X550 945 1.3.2.2 skrll * @hw: pointer to hardware structure 946 1.3.2.2 skrll * @vf: vf index 947 1.3.2.2 skrll * 948 1.3.2.2 skrll * Restore VF that was disabled during malicious driver detection event 949 1.3.2.2 skrll **/ 950 1.3.2.2 skrll void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf) 951 1.3.2.2 skrll { 952 1.3.2.2 skrll u32 idx, reg, num_qs, start_q, bitmask; 953 1.3.2.2 skrll 954 1.3.2.2 skrll DEBUGFUNC("ixgbe_restore_mdd_vf_X550"); 955 1.3.2.2 skrll 956 1.3.2.2 skrll /* Map VF to queues */ 957 1.3.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_MRQC); 958 1.3.2.2 skrll switch (reg & IXGBE_MRQC_MRQE_MASK) { 959 1.3.2.2 skrll case IXGBE_MRQC_VMDQRT8TCEN: 960 1.3.2.2 skrll num_qs = 8; /* 16 VFs / pools */ 961 1.3.2.2 skrll bitmask = 0x000000FF; 962 1.3.2.2 skrll break; 963 1.3.2.2 skrll case IXGBE_MRQC_VMDQRSS32EN: 964 1.3.2.2 skrll case IXGBE_MRQC_VMDQRT4TCEN: 965 1.3.2.2 skrll num_qs = 4; /* 32 VFs / pools */ 966 1.3.2.2 skrll bitmask = 0x0000000F; 967 1.3.2.2 skrll break; 968 1.3.2.2 skrll default: /* 64 VFs / pools */ 969 1.3.2.2 skrll num_qs = 2; 970 1.3.2.2 skrll bitmask = 0x00000003; 971 1.3.2.2 skrll break; 972 1.3.2.2 skrll } 973 1.3.2.2 skrll start_q = vf * num_qs; 974 1.3.2.2 skrll 975 1.3.2.2 skrll /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */ 976 1.3.2.2 skrll idx = start_q / 32; 977 1.3.2.2 skrll reg = 0; 978 1.3.2.2 skrll reg |= (bitmask << (start_q % 32)); 979 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg); 980 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg); 981 1.3.2.2 skrll } 982 1.3.2.2 skrll 983 1.3.2.2 skrll /** 984 1.3.2.2 skrll * ixgbe_mdd_event_X550 985 1.3.2.2 skrll * @hw: pointer to hardware structure 986 1.3.2.2 skrll * @vf_bitmap: vf bitmap of malicious vfs 987 1.3.2.2 skrll * 988 1.3.2.2 skrll * Handle malicious driver detection event. 989 1.3.2.2 skrll **/ 990 1.3.2.2 skrll void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap) 991 1.3.2.2 skrll { 992 1.3.2.2 skrll u32 wqbr; 993 1.3.2.2 skrll u32 i, j, reg, q, shift, vf, idx; 994 1.3.2.2 skrll 995 1.3.2.2 skrll DEBUGFUNC("ixgbe_mdd_event_X550"); 996 1.3.2.2 skrll 997 1.3.2.2 skrll /* figure out pool size for mapping to vf's */ 998 1.3.2.2 skrll reg = IXGBE_READ_REG(hw, IXGBE_MRQC); 999 1.3.2.2 skrll switch (reg & IXGBE_MRQC_MRQE_MASK) { 1000 1.3.2.2 skrll case IXGBE_MRQC_VMDQRT8TCEN: 1001 1.3.2.2 skrll shift = 3; /* 16 VFs / pools */ 1002 1.3.2.2 skrll break; 1003 1.3.2.2 skrll case IXGBE_MRQC_VMDQRSS32EN: 1004 1.3.2.2 skrll case IXGBE_MRQC_VMDQRT4TCEN: 1005 1.3.2.2 skrll shift = 2; /* 32 VFs / pools */ 1006 1.3.2.2 skrll break; 1007 1.3.2.2 skrll default: 1008 1.3.2.2 skrll shift = 1; /* 64 VFs / pools */ 1009 1.3.2.2 skrll break; 1010 1.3.2.2 skrll } 1011 1.3.2.2 skrll 1012 1.3.2.2 skrll /* Read WQBR_TX and WQBR_RX and check for malicious queues */ 1013 1.3.2.2 skrll for (i = 0; i < 4; i++) { 1014 1.3.2.2 skrll wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i)); 1015 1.3.2.2 skrll wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i)); 1016 1.3.2.2 skrll 1017 1.3.2.2 skrll if (!wqbr) 1018 1.3.2.2 skrll continue; 1019 1.3.2.2 skrll 1020 1.3.2.2 skrll /* Get malicious queue */ 1021 1.3.2.2 skrll for (j = 0; j < 32 && wqbr; j++) { 1022 1.3.2.2 skrll 1023 1.3.2.2 skrll if (!(wqbr & (1 << j))) 1024 1.3.2.2 skrll continue; 1025 1.3.2.2 skrll 1026 1.3.2.2 skrll /* Get queue from bitmask */ 1027 1.3.2.2 skrll q = j + (i * 32); 1028 1.3.2.2 skrll 1029 1.3.2.2 skrll /* Map queue to vf */ 1030 1.3.2.2 skrll vf = (q >> shift); 1031 1.3.2.2 skrll 1032 1.3.2.2 skrll /* Set vf bit in vf_bitmap */ 1033 1.3.2.2 skrll idx = vf / 32; 1034 1.3.2.2 skrll vf_bitmap[idx] |= (1 << (vf % 32)); 1035 1.3.2.2 skrll wqbr &= ~(1 << j); 1036 1.3.2.2 skrll } 1037 1.3.2.2 skrll } 1038 1.3.2.2 skrll } 1039 1.3.2.2 skrll 1040 1.3.2.2 skrll /** 1041 1.3.2.2 skrll * ixgbe_get_media_type_X550em - Get media type 1042 1.3.2.2 skrll * @hw: pointer to hardware structure 1043 1.3.2.2 skrll * 1044 1.3.2.2 skrll * Returns the media type (fiber, copper, backplane) 1045 1.3.2.2 skrll */ 1046 1.3.2.2 skrll enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) 1047 1.3.2.2 skrll { 1048 1.3.2.2 skrll enum ixgbe_media_type media_type; 1049 1.3.2.2 skrll 1050 1.3.2.2 skrll DEBUGFUNC("ixgbe_get_media_type_X550em"); 1051 1.3.2.2 skrll 1052 1.3.2.2 skrll /* Detect if there is a copper PHY attached. */ 1053 1.3.2.2 skrll switch (hw->device_id) { 1054 1.3.2.2 skrll case IXGBE_DEV_ID_X550EM_X_KR: 1055 1.3.2.2 skrll case IXGBE_DEV_ID_X550EM_X_KX4: 1056 1.3.2.2 skrll media_type = ixgbe_media_type_backplane; 1057 1.3.2.2 skrll break; 1058 1.3.2.2 skrll case IXGBE_DEV_ID_X550EM_X_SFP: 1059 1.3.2.2 skrll media_type = ixgbe_media_type_fiber; 1060 1.3.2.2 skrll break; 1061 1.3.2.2 skrll case IXGBE_DEV_ID_X550EM_X_1G_T: 1062 1.3.2.2 skrll case IXGBE_DEV_ID_X550EM_X_10G_T: 1063 1.3.2.2 skrll media_type = ixgbe_media_type_copper; 1064 1.3.2.2 skrll break; 1065 1.3.2.2 skrll default: 1066 1.3.2.2 skrll media_type = ixgbe_media_type_unknown; 1067 1.3.2.2 skrll break; 1068 1.3.2.2 skrll } 1069 1.3.2.2 skrll return media_type; 1070 1.3.2.2 skrll } 1071 1.3.2.2 skrll 1072 1.3.2.2 skrll /** 1073 1.3.2.2 skrll * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported 1074 1.3.2.2 skrll * @hw: pointer to hardware structure 1075 1.3.2.2 skrll * @linear: TRUE if SFP module is linear 1076 1.3.2.2 skrll */ 1077 1.3.2.2 skrll static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear) 1078 1.3.2.2 skrll { 1079 1.3.2.2 skrll DEBUGFUNC("ixgbe_supported_sfp_modules_X550em"); 1080 1.3.2.2 skrll 1081 1.3.2.2 skrll switch (hw->phy.sfp_type) { 1082 1.3.2.2 skrll case ixgbe_sfp_type_not_present: 1083 1.3.2.2 skrll return IXGBE_ERR_SFP_NOT_PRESENT; 1084 1.3.2.2 skrll case ixgbe_sfp_type_da_cu_core0: 1085 1.3.2.2 skrll case ixgbe_sfp_type_da_cu_core1: 1086 1.3.2.2 skrll *linear = TRUE; 1087 1.3.2.2 skrll break; 1088 1.3.2.2 skrll case ixgbe_sfp_type_srlr_core0: 1089 1.3.2.2 skrll case ixgbe_sfp_type_srlr_core1: 1090 1.3.2.2 skrll case ixgbe_sfp_type_da_act_lmt_core0: 1091 1.3.2.2 skrll case ixgbe_sfp_type_da_act_lmt_core1: 1092 1.3.2.2 skrll case ixgbe_sfp_type_1g_sx_core0: 1093 1.3.2.2 skrll case ixgbe_sfp_type_1g_sx_core1: 1094 1.3.2.2 skrll case ixgbe_sfp_type_1g_lx_core0: 1095 1.3.2.2 skrll case ixgbe_sfp_type_1g_lx_core1: 1096 1.3.2.2 skrll *linear = FALSE; 1097 1.3.2.2 skrll break; 1098 1.3.2.2 skrll case ixgbe_sfp_type_unknown: 1099 1.3.2.2 skrll case ixgbe_sfp_type_1g_cu_core0: 1100 1.3.2.2 skrll case ixgbe_sfp_type_1g_cu_core1: 1101 1.3.2.2 skrll default: 1102 1.3.2.2 skrll return IXGBE_ERR_SFP_NOT_SUPPORTED; 1103 1.3.2.2 skrll } 1104 1.3.2.2 skrll 1105 1.3.2.2 skrll return IXGBE_SUCCESS; 1106 1.3.2.2 skrll } 1107 1.3.2.2 skrll 1108 1.3.2.2 skrll /** 1109 1.3.2.2 skrll * ixgbe_identify_sfp_module_X550em - Identifies SFP modules 1110 1.3.2.2 skrll * @hw: pointer to hardware structure 1111 1.3.2.2 skrll * 1112 1.3.2.2 skrll * Searches for and identifies the SFP module and assigns appropriate PHY type. 1113 1.3.2.2 skrll **/ 1114 1.3.2.2 skrll s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw) 1115 1.3.2.2 skrll { 1116 1.3.2.2 skrll s32 status; 1117 1.3.2.2 skrll bool linear; 1118 1.3.2.2 skrll 1119 1.3.2.2 skrll DEBUGFUNC("ixgbe_identify_sfp_module_X550em"); 1120 1.3.2.2 skrll 1121 1.3.2.2 skrll status = ixgbe_identify_module_generic(hw); 1122 1.3.2.2 skrll 1123 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1124 1.3.2.2 skrll return status; 1125 1.3.2.2 skrll 1126 1.3.2.2 skrll /* Check if SFP module is supported */ 1127 1.3.2.2 skrll status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 1128 1.3.2.2 skrll 1129 1.3.2.2 skrll return status; 1130 1.3.2.2 skrll } 1131 1.3.2.2 skrll 1132 1.3.2.2 skrll /** 1133 1.3.2.2 skrll * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops 1134 1.3.2.2 skrll * @hw: pointer to hardware structure 1135 1.3.2.2 skrll */ 1136 1.3.2.2 skrll s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) 1137 1.3.2.2 skrll { 1138 1.3.2.2 skrll s32 status; 1139 1.3.2.2 skrll bool linear; 1140 1.3.2.2 skrll 1141 1.3.2.2 skrll DEBUGFUNC("ixgbe_setup_sfp_modules_X550em"); 1142 1.3.2.2 skrll 1143 1.3.2.2 skrll /* Check if SFP module is supported */ 1144 1.3.2.2 skrll status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 1145 1.3.2.2 skrll 1146 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1147 1.3.2.2 skrll return status; 1148 1.3.2.2 skrll 1149 1.3.2.2 skrll ixgbe_init_mac_link_ops_X550em(hw); 1150 1.3.2.2 skrll hw->phy.ops.reset = NULL; 1151 1.3.2.2 skrll 1152 1.3.2.2 skrll return IXGBE_SUCCESS; 1153 1.3.2.2 skrll } 1154 1.3.2.2 skrll 1155 1.3.2.2 skrll /** 1156 1.3.2.2 skrll * ixgbe_init_mac_link_ops_X550em - init mac link function pointers 1157 1.3.2.2 skrll * @hw: pointer to hardware structure 1158 1.3.2.2 skrll */ 1159 1.3.2.2 skrll void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) 1160 1.3.2.2 skrll { 1161 1.3.2.2 skrll struct ixgbe_mac_info *mac = &hw->mac; 1162 1.3.2.2 skrll 1163 1.3.2.2 skrll DEBUGFUNC("ixgbe_init_mac_link_ops_X550em"); 1164 1.3.2.2 skrll 1165 1.3.2.2 skrll switch (hw->mac.ops.get_media_type(hw)) { 1166 1.3.2.2 skrll case ixgbe_media_type_fiber: 1167 1.3.2.2 skrll /* CS4227 does not support autoneg, so disable the laser control 1168 1.3.2.2 skrll * functions for SFP+ fiber 1169 1.3.2.2 skrll */ 1170 1.3.2.2 skrll mac->ops.disable_tx_laser = NULL; 1171 1.3.2.2 skrll mac->ops.enable_tx_laser = NULL; 1172 1.3.2.2 skrll mac->ops.flap_tx_laser = NULL; 1173 1.3.2.2 skrll mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 1174 1.3.2.2 skrll mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em; 1175 1.3.2.2 skrll mac->ops.set_rate_select_speed = 1176 1.3.2.2 skrll ixgbe_set_soft_rate_select_speed; 1177 1.3.2.2 skrll break; 1178 1.3.2.2 skrll case ixgbe_media_type_copper: 1179 1.3.2.2 skrll mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 1180 1.3.2.2 skrll mac->ops.check_link = ixgbe_check_link_t_X550em; 1181 1.3.2.2 skrll break; 1182 1.3.2.2 skrll default: 1183 1.3.2.2 skrll break; 1184 1.3.2.2 skrll } 1185 1.3.2.2 skrll } 1186 1.3.2.2 skrll 1187 1.3.2.2 skrll /** 1188 1.3.2.2 skrll * ixgbe_get_link_capabilities_x550em - Determines link capabilities 1189 1.3.2.2 skrll * @hw: pointer to hardware structure 1190 1.3.2.2 skrll * @speed: pointer to link speed 1191 1.3.2.2 skrll * @autoneg: TRUE when autoneg or autotry is enabled 1192 1.3.2.2 skrll */ 1193 1.3.2.2 skrll s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, 1194 1.3.2.2 skrll ixgbe_link_speed *speed, 1195 1.3.2.2 skrll bool *autoneg) 1196 1.3.2.2 skrll { 1197 1.3.2.2 skrll DEBUGFUNC("ixgbe_get_link_capabilities_X550em"); 1198 1.3.2.2 skrll 1199 1.3.2.2 skrll /* SFP */ 1200 1.3.2.2 skrll if (hw->phy.media_type == ixgbe_media_type_fiber) { 1201 1.3.2.2 skrll 1202 1.3.2.2 skrll /* CS4227 SFP must not enable auto-negotiation */ 1203 1.3.2.2 skrll *autoneg = FALSE; 1204 1.3.2.2 skrll 1205 1.3.2.2 skrll /* Check if 1G SFP module. */ 1206 1.3.2.2 skrll if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1207 1.3.2.2 skrll hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 1208 1.3.2.2 skrll || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1209 1.3.2.2 skrll hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) { 1210 1.3.2.2 skrll *speed = IXGBE_LINK_SPEED_1GB_FULL; 1211 1.3.2.2 skrll return IXGBE_SUCCESS; 1212 1.3.2.2 skrll } 1213 1.3.2.2 skrll 1214 1.3.2.2 skrll /* Link capabilities are based on SFP */ 1215 1.3.2.2 skrll if (hw->phy.multispeed_fiber) 1216 1.3.2.2 skrll *speed = IXGBE_LINK_SPEED_10GB_FULL | 1217 1.3.2.2 skrll IXGBE_LINK_SPEED_1GB_FULL; 1218 1.3.2.2 skrll else 1219 1.3.2.2 skrll *speed = IXGBE_LINK_SPEED_10GB_FULL; 1220 1.3.2.2 skrll } else { 1221 1.3.2.2 skrll *speed = IXGBE_LINK_SPEED_10GB_FULL | 1222 1.3.2.2 skrll IXGBE_LINK_SPEED_1GB_FULL; 1223 1.3.2.2 skrll *autoneg = TRUE; 1224 1.3.2.2 skrll } 1225 1.3.2.2 skrll 1226 1.3.2.2 skrll return IXGBE_SUCCESS; 1227 1.3.2.2 skrll } 1228 1.3.2.2 skrll 1229 1.3.2.2 skrll /** 1230 1.3.2.2 skrll * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause 1231 1.3.2.2 skrll * @hw: pointer to hardware structure 1232 1.3.2.2 skrll * @lsc: pointer to boolean flag which indicates whether external Base T 1233 1.3.2.2 skrll * PHY interrupt is lsc 1234 1.3.2.2 skrll * 1235 1.3.2.2 skrll * Determime if external Base T PHY interrupt cause is high temperature 1236 1.3.2.2 skrll * failure alarm or link status change. 1237 1.3.2.2 skrll * 1238 1.3.2.2 skrll * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1239 1.3.2.2 skrll * failure alarm, else return PHY access status. 1240 1.3.2.2 skrll */ 1241 1.3.2.2 skrll static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc) 1242 1.3.2.2 skrll { 1243 1.3.2.2 skrll u32 status; 1244 1.3.2.2 skrll u16 reg; 1245 1.3.2.2 skrll 1246 1.3.2.2 skrll *lsc = FALSE; 1247 1.3.2.2 skrll 1248 1.3.2.2 skrll /* Vendor alarm triggered */ 1249 1.3.2.2 skrll status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 1250 1.3.2.2 skrll IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1251 1.3.2.2 skrll ®); 1252 1.3.2.2 skrll 1253 1.3.2.2 skrll if (status != IXGBE_SUCCESS || 1254 1.3.2.2 skrll !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN)) 1255 1.3.2.2 skrll return status; 1256 1.3.2.2 skrll 1257 1.3.2.2 skrll /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */ 1258 1.3.2.2 skrll status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, 1259 1.3.2.2 skrll IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1260 1.3.2.2 skrll ®); 1261 1.3.2.2 skrll 1262 1.3.2.2 skrll if (status != IXGBE_SUCCESS || 1263 1.3.2.2 skrll !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 1264 1.3.2.2 skrll IXGBE_MDIO_GLOBAL_ALARM_1_INT))) 1265 1.3.2.2 skrll return status; 1266 1.3.2.2 skrll 1267 1.3.2.2 skrll /* High temperature failure alarm triggered */ 1268 1.3.2.2 skrll status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, 1269 1.3.2.2 skrll IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1270 1.3.2.2 skrll ®); 1271 1.3.2.2 skrll 1272 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1273 1.3.2.2 skrll return status; 1274 1.3.2.2 skrll 1275 1.3.2.2 skrll /* If high temperature failure, then return over temp error and exit */ 1276 1.3.2.2 skrll if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) { 1277 1.3.2.2 skrll /* power down the PHY in case the PHY FW didn't already */ 1278 1.3.2.2 skrll ixgbe_set_copper_phy_power(hw, FALSE); 1279 1.3.2.2 skrll return IXGBE_ERR_OVERTEMP; 1280 1.3.2.2 skrll } 1281 1.3.2.2 skrll 1282 1.3.2.2 skrll /* Vendor alarm 2 triggered */ 1283 1.3.2.2 skrll status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 1284 1.3.2.2 skrll IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 1285 1.3.2.2 skrll 1286 1.3.2.2 skrll if (status != IXGBE_SUCCESS || 1287 1.3.2.2 skrll !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT)) 1288 1.3.2.2 skrll return status; 1289 1.3.2.2 skrll 1290 1.3.2.2 skrll /* link connect/disconnect event occurred */ 1291 1.3.2.2 skrll status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2, 1292 1.3.2.2 skrll IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 1293 1.3.2.2 skrll 1294 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1295 1.3.2.2 skrll return status; 1296 1.3.2.2 skrll 1297 1.3.2.2 skrll /* Indicate LSC */ 1298 1.3.2.2 skrll if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC) 1299 1.3.2.2 skrll *lsc = TRUE; 1300 1.3.2.2 skrll 1301 1.3.2.2 skrll return IXGBE_SUCCESS; 1302 1.3.2.2 skrll } 1303 1.3.2.2 skrll 1304 1.3.2.2 skrll /** 1305 1.3.2.2 skrll * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts 1306 1.3.2.2 skrll * @hw: pointer to hardware structure 1307 1.3.2.2 skrll * 1308 1.3.2.2 skrll * Enable link status change and temperature failure alarm for the external 1309 1.3.2.2 skrll * Base T PHY 1310 1.3.2.2 skrll * 1311 1.3.2.2 skrll * Returns PHY access status 1312 1.3.2.2 skrll */ 1313 1.3.2.2 skrll static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw) 1314 1.3.2.2 skrll { 1315 1.3.2.2 skrll u32 status; 1316 1.3.2.2 skrll u16 reg; 1317 1.3.2.2 skrll bool lsc; 1318 1.3.2.2 skrll 1319 1.3.2.2 skrll /* Clear interrupt flags */ 1320 1.3.2.2 skrll status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 1321 1.3.2.2 skrll 1322 1.3.2.2 skrll /* Enable link status change alarm */ 1323 1.3.2.2 skrll status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 1324 1.3.2.2 skrll IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 1325 1.3.2.2 skrll 1326 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1327 1.3.2.2 skrll return status; 1328 1.3.2.2 skrll 1329 1.3.2.2 skrll reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN; 1330 1.3.2.2 skrll 1331 1.3.2.2 skrll status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 1332 1.3.2.2 skrll IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg); 1333 1.3.2.2 skrll 1334 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1335 1.3.2.2 skrll return status; 1336 1.3.2.2 skrll 1337 1.3.2.2 skrll /* Enables high temperature failure alarm */ 1338 1.3.2.2 skrll status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 1339 1.3.2.2 skrll IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1340 1.3.2.2 skrll ®); 1341 1.3.2.2 skrll 1342 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1343 1.3.2.2 skrll return status; 1344 1.3.2.2 skrll 1345 1.3.2.2 skrll reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN; 1346 1.3.2.2 skrll 1347 1.3.2.2 skrll status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 1348 1.3.2.2 skrll IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1349 1.3.2.2 skrll reg); 1350 1.3.2.2 skrll 1351 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1352 1.3.2.2 skrll return status; 1353 1.3.2.2 skrll 1354 1.3.2.2 skrll /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */ 1355 1.3.2.2 skrll status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 1356 1.3.2.2 skrll IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1357 1.3.2.2 skrll ®); 1358 1.3.2.2 skrll 1359 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1360 1.3.2.2 skrll return status; 1361 1.3.2.2 skrll 1362 1.3.2.2 skrll reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 1363 1.3.2.2 skrll IXGBE_MDIO_GLOBAL_ALARM_1_INT); 1364 1.3.2.2 skrll 1365 1.3.2.2 skrll status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 1366 1.3.2.2 skrll IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1367 1.3.2.2 skrll reg); 1368 1.3.2.2 skrll 1369 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1370 1.3.2.2 skrll return status; 1371 1.3.2.2 skrll 1372 1.3.2.2 skrll /* Enable chip-wide vendor alarm */ 1373 1.3.2.2 skrll status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 1374 1.3.2.2 skrll IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1375 1.3.2.2 skrll ®); 1376 1.3.2.2 skrll 1377 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1378 1.3.2.2 skrll return status; 1379 1.3.2.2 skrll 1380 1.3.2.2 skrll reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN; 1381 1.3.2.2 skrll 1382 1.3.2.2 skrll status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 1383 1.3.2.2 skrll IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1384 1.3.2.2 skrll reg); 1385 1.3.2.2 skrll 1386 1.3.2.2 skrll return status; 1387 1.3.2.2 skrll } 1388 1.3.2.2 skrll 1389 1.3.2.2 skrll /** 1390 1.3.2.2 skrll * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed. 1391 1.3.2.2 skrll * @hw: pointer to hardware structure 1392 1.3.2.2 skrll * @speed: link speed 1393 1.3.2.2 skrll * 1394 1.3.2.2 skrll * Configures the integrated KR PHY. 1395 1.3.2.2 skrll **/ 1396 1.3.2.2 skrll static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, 1397 1.3.2.2 skrll ixgbe_link_speed speed) 1398 1.3.2.2 skrll { 1399 1.3.2.2 skrll s32 status; 1400 1.3.2.2 skrll u32 reg_val; 1401 1.3.2.2 skrll 1402 1.3.2.2 skrll status = ixgbe_read_iosf_sb_reg_x550(hw, 1403 1.3.2.2 skrll IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1404 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1405 1.3.2.2 skrll if (status) 1406 1.3.2.2 skrll return status; 1407 1.3.2.2 skrll 1408 1.3.2.2 skrll reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1409 1.3.2.2 skrll reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | 1410 1.3.2.2 skrll IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); 1411 1.3.2.2 skrll 1412 1.3.2.2 skrll /* Advertise 10G support. */ 1413 1.3.2.2 skrll if (speed & IXGBE_LINK_SPEED_10GB_FULL) 1414 1.3.2.2 skrll reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; 1415 1.3.2.2 skrll 1416 1.3.2.2 skrll /* Advertise 1G support. */ 1417 1.3.2.2 skrll if (speed & IXGBE_LINK_SPEED_1GB_FULL) 1418 1.3.2.2 skrll reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; 1419 1.3.2.2 skrll 1420 1.3.2.2 skrll /* Restart auto-negotiation. */ 1421 1.3.2.2 skrll reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1422 1.3.2.2 skrll status = ixgbe_write_iosf_sb_reg_x550(hw, 1423 1.3.2.2 skrll IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1424 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1425 1.3.2.2 skrll 1426 1.3.2.2 skrll return status; 1427 1.3.2.2 skrll } 1428 1.3.2.2 skrll 1429 1.3.2.2 skrll /** 1430 1.3.2.2 skrll * ixgbe_init_phy_ops_X550em - PHY/SFP specific init 1431 1.3.2.2 skrll * @hw: pointer to hardware structure 1432 1.3.2.2 skrll * 1433 1.3.2.2 skrll * Initialize any function pointers that were not able to be 1434 1.3.2.2 skrll * set during init_shared_code because the PHY/SFP type was 1435 1.3.2.2 skrll * not known. Perform the SFP init if necessary. 1436 1.3.2.2 skrll */ 1437 1.3.2.2 skrll s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) 1438 1.3.2.2 skrll { 1439 1.3.2.2 skrll struct ixgbe_phy_info *phy = &hw->phy; 1440 1.3.2.2 skrll ixgbe_link_speed speed; 1441 1.3.2.2 skrll s32 ret_val; 1442 1.3.2.2 skrll 1443 1.3.2.2 skrll DEBUGFUNC("ixgbe_init_phy_ops_X550em"); 1444 1.3.2.2 skrll 1445 1.3.2.2 skrll hw->mac.ops.set_lan_id(hw); 1446 1.3.2.2 skrll 1447 1.3.2.2 skrll if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { 1448 1.3.2.2 skrll phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 1449 1.3.2.2 skrll ixgbe_setup_mux_ctl(hw); 1450 1.3.2.2 skrll 1451 1.3.2.2 skrll /* Save NW management interface connected on board. This is used 1452 1.3.2.2 skrll * to determine internal PHY mode. 1453 1.3.2.2 skrll */ 1454 1.3.2.2 skrll phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 1455 1.3.2.2 skrll if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) { 1456 1.3.2.2 skrll speed = IXGBE_LINK_SPEED_10GB_FULL | 1457 1.3.2.2 skrll IXGBE_LINK_SPEED_1GB_FULL; 1458 1.3.2.2 skrll } 1459 1.3.2.2 skrll phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em; 1460 1.3.2.2 skrll } 1461 1.3.2.2 skrll 1462 1.3.2.2 skrll /* Identify the PHY or SFP module */ 1463 1.3.2.2 skrll ret_val = phy->ops.identify(hw); 1464 1.3.2.2 skrll if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) 1465 1.3.2.2 skrll return ret_val; 1466 1.3.2.2 skrll 1467 1.3.2.2 skrll /* Setup function pointers based on detected hardware */ 1468 1.3.2.2 skrll ixgbe_init_mac_link_ops_X550em(hw); 1469 1.3.2.2 skrll if (phy->sfp_type != ixgbe_sfp_type_unknown) 1470 1.3.2.2 skrll phy->ops.reset = NULL; 1471 1.3.2.2 skrll 1472 1.3.2.2 skrll /* Set functions pointers based on phy type */ 1473 1.3.2.2 skrll switch (hw->phy.type) { 1474 1.3.2.2 skrll case ixgbe_phy_x550em_kx4: 1475 1.3.2.2 skrll phy->ops.setup_link = NULL; 1476 1.3.2.2 skrll phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 1477 1.3.2.2 skrll phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 1478 1.3.2.2 skrll break; 1479 1.3.2.2 skrll case ixgbe_phy_x550em_kr: 1480 1.3.2.2 skrll phy->ops.setup_link = ixgbe_setup_kr_x550em; 1481 1.3.2.2 skrll phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 1482 1.3.2.2 skrll phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 1483 1.3.2.2 skrll break; 1484 1.3.2.2 skrll case ixgbe_phy_x550em_ext_t: 1485 1.3.2.2 skrll /* Save NW management interface connected on board. This is used 1486 1.3.2.2 skrll * to determine internal PHY mode 1487 1.3.2.2 skrll */ 1488 1.3.2.2 skrll phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 1489 1.3.2.2 skrll 1490 1.3.2.2 skrll /* If internal link mode is XFI, then setup iXFI internal link, 1491 1.3.2.2 skrll * else setup KR now. 1492 1.3.2.2 skrll */ 1493 1.3.2.2 skrll if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 1494 1.3.2.2 skrll phy->ops.setup_internal_link = 1495 1.3.2.2 skrll ixgbe_setup_internal_phy_t_x550em; 1496 1.3.2.2 skrll } else { 1497 1.3.2.2 skrll speed = IXGBE_LINK_SPEED_10GB_FULL | 1498 1.3.2.2 skrll IXGBE_LINK_SPEED_1GB_FULL; 1499 1.3.2.2 skrll ret_val = ixgbe_setup_kr_speed_x550em(hw, speed); 1500 1.3.2.2 skrll } 1501 1.3.2.2 skrll 1502 1.3.2.2 skrll /* setup SW LPLU only for first revision */ 1503 1.3.2.2 skrll if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, 1504 1.3.2.2 skrll IXGBE_FUSES0_GROUP(0)))) 1505 1.3.2.2 skrll phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em; 1506 1.3.2.2 skrll 1507 1.3.2.2 skrll phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; 1508 1.3.2.2 skrll phy->ops.reset = ixgbe_reset_phy_t_X550em; 1509 1.3.2.2 skrll break; 1510 1.3.2.2 skrll default: 1511 1.3.2.2 skrll break; 1512 1.3.2.2 skrll } 1513 1.3.2.2 skrll return ret_val; 1514 1.3.2.2 skrll } 1515 1.3.2.2 skrll 1516 1.3.2.2 skrll /** 1517 1.3.2.2 skrll * ixgbe_reset_hw_X550em - Perform hardware reset 1518 1.3.2.2 skrll * @hw: pointer to hardware structure 1519 1.3.2.2 skrll * 1520 1.3.2.2 skrll * Resets the hardware by resetting the transmit and receive units, masks 1521 1.3.2.2 skrll * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 1522 1.3.2.2 skrll * reset. 1523 1.3.2.2 skrll */ 1524 1.3.2.2 skrll s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) 1525 1.3.2.2 skrll { 1526 1.3.2.2 skrll ixgbe_link_speed link_speed; 1527 1.3.2.2 skrll s32 status; 1528 1.3.2.2 skrll u32 ctrl = 0; 1529 1.3.2.2 skrll u32 i; 1530 1.3.2.2 skrll u32 hlreg0; 1531 1.3.2.2 skrll bool link_up = FALSE; 1532 1.3.2.2 skrll 1533 1.3.2.2 skrll DEBUGFUNC("ixgbe_reset_hw_X550em"); 1534 1.3.2.2 skrll 1535 1.3.2.2 skrll /* Call adapter stop to disable Tx/Rx and clear interrupts */ 1536 1.3.2.2 skrll status = hw->mac.ops.stop_adapter(hw); 1537 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1538 1.3.2.2 skrll return status; 1539 1.3.2.2 skrll 1540 1.3.2.2 skrll /* flush pending Tx transactions */ 1541 1.3.2.2 skrll ixgbe_clear_tx_pending(hw); 1542 1.3.2.2 skrll 1543 1.3.2.2 skrll if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) { 1544 1.3.2.2 skrll /* Config MDIO clock speed before the first MDIO PHY access */ 1545 1.3.2.2 skrll hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 1546 1.3.2.2 skrll hlreg0 &= ~IXGBE_HLREG0_MDCSPD; 1547 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 1548 1.3.2.2 skrll } 1549 1.3.2.2 skrll 1550 1.3.2.2 skrll /* PHY ops must be identified and initialized prior to reset */ 1551 1.3.2.2 skrll status = hw->phy.ops.init(hw); 1552 1.3.2.2 skrll 1553 1.3.2.2 skrll if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1554 1.3.2.2 skrll return status; 1555 1.3.2.2 skrll 1556 1.3.2.2 skrll /* start the external PHY */ 1557 1.3.2.2 skrll if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 1558 1.3.2.2 skrll status = ixgbe_init_ext_t_x550em(hw); 1559 1.3.2.2 skrll if (status) 1560 1.3.2.2 skrll return status; 1561 1.3.2.2 skrll } 1562 1.3.2.2 skrll 1563 1.3.2.2 skrll /* Setup SFP module if there is one present. */ 1564 1.3.2.2 skrll if (hw->phy.sfp_setup_needed) { 1565 1.3.2.2 skrll status = hw->mac.ops.setup_sfp(hw); 1566 1.3.2.2 skrll hw->phy.sfp_setup_needed = FALSE; 1567 1.3.2.2 skrll } 1568 1.3.2.2 skrll 1569 1.3.2.2 skrll if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1570 1.3.2.2 skrll return status; 1571 1.3.2.2 skrll 1572 1.3.2.2 skrll /* Reset PHY */ 1573 1.3.2.2 skrll if (!hw->phy.reset_disable && hw->phy.ops.reset) 1574 1.3.2.2 skrll hw->phy.ops.reset(hw); 1575 1.3.2.2 skrll 1576 1.3.2.2 skrll mac_reset_top: 1577 1.3.2.2 skrll /* Issue global reset to the MAC. Needs to be SW reset if link is up. 1578 1.3.2.2 skrll * If link reset is used when link is up, it might reset the PHY when 1579 1.3.2.2 skrll * mng is using it. If link is down or the flag to force full link 1580 1.3.2.2 skrll * reset is set, then perform link reset. 1581 1.3.2.2 skrll */ 1582 1.3.2.2 skrll ctrl = IXGBE_CTRL_LNK_RST; 1583 1.3.2.2 skrll if (!hw->force_full_reset) { 1584 1.3.2.2 skrll hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE); 1585 1.3.2.2 skrll if (link_up) 1586 1.3.2.2 skrll ctrl = IXGBE_CTRL_RST; 1587 1.3.2.2 skrll } 1588 1.3.2.2 skrll 1589 1.3.2.2 skrll ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 1590 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 1591 1.3.2.2 skrll IXGBE_WRITE_FLUSH(hw); 1592 1.3.2.2 skrll 1593 1.3.2.2 skrll /* Poll for reset bit to self-clear meaning reset is complete */ 1594 1.3.2.2 skrll for (i = 0; i < 10; i++) { 1595 1.3.2.2 skrll usec_delay(1); 1596 1.3.2.2 skrll ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1597 1.3.2.2 skrll if (!(ctrl & IXGBE_CTRL_RST_MASK)) 1598 1.3.2.2 skrll break; 1599 1.3.2.2 skrll } 1600 1.3.2.2 skrll 1601 1.3.2.2 skrll if (ctrl & IXGBE_CTRL_RST_MASK) { 1602 1.3.2.2 skrll status = IXGBE_ERR_RESET_FAILED; 1603 1.3.2.2 skrll DEBUGOUT("Reset polling failed to complete.\n"); 1604 1.3.2.2 skrll } 1605 1.3.2.2 skrll 1606 1.3.2.2 skrll msec_delay(50); 1607 1.3.2.2 skrll 1608 1.3.2.2 skrll /* Double resets are required for recovery from certain error 1609 1.3.2.2 skrll * conditions. Between resets, it is necessary to stall to 1610 1.3.2.2 skrll * allow time for any pending HW events to complete. 1611 1.3.2.2 skrll */ 1612 1.3.2.2 skrll if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1613 1.3.2.2 skrll hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1614 1.3.2.2 skrll goto mac_reset_top; 1615 1.3.2.2 skrll } 1616 1.3.2.2 skrll 1617 1.3.2.2 skrll /* Store the permanent mac address */ 1618 1.3.2.2 skrll hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1619 1.3.2.2 skrll 1620 1.3.2.2 skrll /* Store MAC address from RAR0, clear receive address registers, and 1621 1.3.2.2 skrll * clear the multicast table. Also reset num_rar_entries to 128, 1622 1.3.2.2 skrll * since we modify this value when programming the SAN MAC address. 1623 1.3.2.2 skrll */ 1624 1.3.2.2 skrll hw->mac.num_rar_entries = 128; 1625 1.3.2.2 skrll hw->mac.ops.init_rx_addrs(hw); 1626 1.3.2.2 skrll 1627 1.3.2.2 skrll if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) 1628 1.3.2.2 skrll ixgbe_setup_mux_ctl(hw); 1629 1.3.2.2 skrll 1630 1.3.2.2 skrll return status; 1631 1.3.2.2 skrll } 1632 1.3.2.2 skrll 1633 1.3.2.2 skrll /** 1634 1.3.2.2 skrll * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. 1635 1.3.2.2 skrll * @hw: pointer to hardware structure 1636 1.3.2.2 skrll */ 1637 1.3.2.2 skrll s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) 1638 1.3.2.2 skrll { 1639 1.3.2.2 skrll u32 status; 1640 1.3.2.2 skrll u16 reg; 1641 1.3.2.2 skrll 1642 1.3.2.2 skrll status = hw->phy.ops.read_reg(hw, 1643 1.3.2.2 skrll IXGBE_MDIO_TX_VENDOR_ALARMS_3, 1644 1.3.2.2 skrll IXGBE_MDIO_PMA_PMD_DEV_TYPE, 1645 1.3.2.2 skrll ®); 1646 1.3.2.2 skrll 1647 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1648 1.3.2.2 skrll return status; 1649 1.3.2.2 skrll 1650 1.3.2.2 skrll /* If PHY FW reset completed bit is set then this is the first 1651 1.3.2.2 skrll * SW instance after a power on so the PHY FW must be un-stalled. 1652 1.3.2.2 skrll */ 1653 1.3.2.2 skrll if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 1654 1.3.2.2 skrll status = hw->phy.ops.read_reg(hw, 1655 1.3.2.2 skrll IXGBE_MDIO_GLOBAL_RES_PR_10, 1656 1.3.2.2 skrll IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1657 1.3.2.2 skrll ®); 1658 1.3.2.2 skrll 1659 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1660 1.3.2.2 skrll return status; 1661 1.3.2.2 skrll 1662 1.3.2.2 skrll reg &= ~IXGBE_MDIO_POWER_UP_STALL; 1663 1.3.2.2 skrll 1664 1.3.2.2 skrll status = hw->phy.ops.write_reg(hw, 1665 1.3.2.2 skrll IXGBE_MDIO_GLOBAL_RES_PR_10, 1666 1.3.2.2 skrll IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1667 1.3.2.2 skrll reg); 1668 1.3.2.2 skrll 1669 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1670 1.3.2.2 skrll return status; 1671 1.3.2.2 skrll } 1672 1.3.2.2 skrll 1673 1.3.2.2 skrll return status; 1674 1.3.2.2 skrll } 1675 1.3.2.2 skrll 1676 1.3.2.2 skrll /** 1677 1.3.2.2 skrll * ixgbe_setup_kr_x550em - Configure the KR PHY. 1678 1.3.2.2 skrll * @hw: pointer to hardware structure 1679 1.3.2.2 skrll * 1680 1.3.2.2 skrll * Configures the integrated KR PHY. 1681 1.3.2.2 skrll **/ 1682 1.3.2.2 skrll s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) 1683 1.3.2.2 skrll { 1684 1.3.2.2 skrll return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); 1685 1.3.2.2 skrll } 1686 1.3.2.2 skrll 1687 1.3.2.2 skrll /** 1688 1.3.2.2 skrll * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP 1689 1.3.2.2 skrll * @hw: pointer to hardware structure 1690 1.3.2.2 skrll * 1691 1.3.2.2 skrll * Configure the external PHY and the integrated KR PHY for SFP support. 1692 1.3.2.2 skrll **/ 1693 1.3.2.2 skrll s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, 1694 1.3.2.2 skrll ixgbe_link_speed speed, 1695 1.3.2.2 skrll bool autoneg_wait_to_complete) 1696 1.3.2.2 skrll { 1697 1.3.2.2 skrll s32 ret_val; 1698 1.3.2.2 skrll u16 reg_slice, reg_val; 1699 1.3.2.2 skrll bool setup_linear = FALSE; 1700 1.3.2.2 skrll UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 1701 1.3.2.2 skrll 1702 1.3.2.2 skrll /* Check if SFP module is supported and linear */ 1703 1.3.2.2 skrll ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1704 1.3.2.2 skrll 1705 1.3.2.2 skrll /* If no SFP module present, then return success. Return success since 1706 1.3.2.2 skrll * there is no reason to configure CS4227 and SFP not present error is 1707 1.3.2.2 skrll * not excepted in the setup MAC link flow. 1708 1.3.2.2 skrll */ 1709 1.3.2.2 skrll if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 1710 1.3.2.2 skrll return IXGBE_SUCCESS; 1711 1.3.2.2 skrll 1712 1.3.2.2 skrll if (ret_val != IXGBE_SUCCESS) 1713 1.3.2.2 skrll return ret_val; 1714 1.3.2.2 skrll 1715 1.3.2.2 skrll if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 1716 1.3.2.2 skrll /* Configure CS4227 LINE side to 10G SR. */ 1717 1.3.2.2 skrll reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + 1718 1.3.2.2 skrll (hw->bus.lan_id << 12); 1719 1.3.2.2 skrll reg_val = IXGBE_CS4227_SPEED_10G; 1720 1.3.2.2 skrll ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1721 1.3.2.2 skrll reg_val); 1722 1.3.2.2 skrll 1723 1.3.2.2 skrll reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + 1724 1.3.2.2 skrll (hw->bus.lan_id << 12); 1725 1.3.2.2 skrll reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1726 1.3.2.2 skrll ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1727 1.3.2.2 skrll reg_val); 1728 1.3.2.2 skrll 1729 1.3.2.2 skrll /* Configure CS4227 for HOST connection rate then type. */ 1730 1.3.2.2 skrll reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + 1731 1.3.2.2 skrll (hw->bus.lan_id << 12); 1732 1.3.2.2 skrll reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 1733 1.3.2.2 skrll IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G; 1734 1.3.2.2 skrll ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1735 1.3.2.2 skrll reg_val); 1736 1.3.2.2 skrll 1737 1.3.2.2 skrll reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + 1738 1.3.2.2 skrll (hw->bus.lan_id << 12); 1739 1.3.2.2 skrll if (setup_linear) 1740 1.3.2.2 skrll reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 1741 1.3.2.2 skrll else 1742 1.3.2.2 skrll reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1743 1.3.2.2 skrll ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1744 1.3.2.2 skrll reg_val); 1745 1.3.2.2 skrll 1746 1.3.2.2 skrll /* Setup XFI internal link. */ 1747 1.3.2.2 skrll ret_val = ixgbe_setup_ixfi_x550em(hw, &speed); 1748 1.3.2.2 skrll } else { 1749 1.3.2.2 skrll /* Configure internal PHY for KR/KX. */ 1750 1.3.2.2 skrll ixgbe_setup_kr_speed_x550em(hw, speed); 1751 1.3.2.2 skrll 1752 1.3.2.2 skrll /* Configure CS4227 LINE side to proper mode. */ 1753 1.3.2.2 skrll reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + 1754 1.3.2.2 skrll (hw->bus.lan_id << 12); 1755 1.3.2.2 skrll if (setup_linear) 1756 1.3.2.2 skrll reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 1757 1.3.2.2 skrll else 1758 1.3.2.2 skrll reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1759 1.3.2.2 skrll ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1760 1.3.2.2 skrll reg_val); 1761 1.3.2.2 skrll } 1762 1.3.2.2 skrll return ret_val; 1763 1.3.2.2 skrll } 1764 1.3.2.2 skrll 1765 1.3.2.2 skrll /** 1766 1.3.2.2 skrll * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. 1767 1.3.2.2 skrll * @hw: pointer to hardware structure 1768 1.3.2.2 skrll * @speed: the link speed to force 1769 1.3.2.2 skrll * 1770 1.3.2.2 skrll * Configures the integrated KR PHY to use iXFI mode. Used to connect an 1771 1.3.2.2 skrll * internal and external PHY at a specific speed, without autonegotiation. 1772 1.3.2.2 skrll **/ 1773 1.3.2.2 skrll static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 1774 1.3.2.2 skrll { 1775 1.3.2.2 skrll s32 status; 1776 1.3.2.2 skrll u32 reg_val; 1777 1.3.2.2 skrll 1778 1.3.2.2 skrll /* Disable AN and force speed to 10G Serial. */ 1779 1.3.2.2 skrll status = ixgbe_read_iosf_sb_reg_x550(hw, 1780 1.3.2.2 skrll IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1781 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1782 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1783 1.3.2.2 skrll return status; 1784 1.3.2.2 skrll 1785 1.3.2.2 skrll reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1786 1.3.2.2 skrll reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1787 1.3.2.2 skrll 1788 1.3.2.2 skrll /* Select forced link speed for internal PHY. */ 1789 1.3.2.2 skrll switch (*speed) { 1790 1.3.2.2 skrll case IXGBE_LINK_SPEED_10GB_FULL: 1791 1.3.2.2 skrll reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 1792 1.3.2.2 skrll break; 1793 1.3.2.2 skrll case IXGBE_LINK_SPEED_1GB_FULL: 1794 1.3.2.2 skrll reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1795 1.3.2.2 skrll break; 1796 1.3.2.2 skrll default: 1797 1.3.2.2 skrll /* Other link speeds are not supported by internal KR PHY. */ 1798 1.3.2.2 skrll return IXGBE_ERR_LINK_SETUP; 1799 1.3.2.2 skrll } 1800 1.3.2.2 skrll 1801 1.3.2.2 skrll status = ixgbe_write_iosf_sb_reg_x550(hw, 1802 1.3.2.2 skrll IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1803 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1804 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1805 1.3.2.2 skrll return status; 1806 1.3.2.2 skrll 1807 1.3.2.2 skrll /* Disable training protocol FSM. */ 1808 1.3.2.2 skrll status = ixgbe_read_iosf_sb_reg_x550(hw, 1809 1.3.2.2 skrll IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1810 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1811 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1812 1.3.2.2 skrll return status; 1813 1.3.2.2 skrll reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; 1814 1.3.2.2 skrll status = ixgbe_write_iosf_sb_reg_x550(hw, 1815 1.3.2.2 skrll IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1816 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1817 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1818 1.3.2.2 skrll return status; 1819 1.3.2.2 skrll 1820 1.3.2.2 skrll /* Disable Flex from training TXFFE. */ 1821 1.3.2.2 skrll status = ixgbe_read_iosf_sb_reg_x550(hw, 1822 1.3.2.2 skrll IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1823 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1824 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1825 1.3.2.2 skrll return status; 1826 1.3.2.2 skrll reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1827 1.3.2.2 skrll reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1828 1.3.2.2 skrll reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1829 1.3.2.2 skrll status = ixgbe_write_iosf_sb_reg_x550(hw, 1830 1.3.2.2 skrll IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1831 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1832 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1833 1.3.2.2 skrll return status; 1834 1.3.2.2 skrll status = ixgbe_read_iosf_sb_reg_x550(hw, 1835 1.3.2.2 skrll IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1836 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1837 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1838 1.3.2.2 skrll return status; 1839 1.3.2.2 skrll reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1840 1.3.2.2 skrll reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1841 1.3.2.2 skrll reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1842 1.3.2.2 skrll status = ixgbe_write_iosf_sb_reg_x550(hw, 1843 1.3.2.2 skrll IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1844 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1845 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1846 1.3.2.2 skrll return status; 1847 1.3.2.2 skrll 1848 1.3.2.2 skrll /* Enable override for coefficients. */ 1849 1.3.2.2 skrll status = ixgbe_read_iosf_sb_reg_x550(hw, 1850 1.3.2.2 skrll IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1851 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1852 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1853 1.3.2.2 skrll return status; 1854 1.3.2.2 skrll reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; 1855 1.3.2.2 skrll reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; 1856 1.3.2.2 skrll reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; 1857 1.3.2.2 skrll reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; 1858 1.3.2.2 skrll status = ixgbe_write_iosf_sb_reg_x550(hw, 1859 1.3.2.2 skrll IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1860 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1861 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1862 1.3.2.2 skrll return status; 1863 1.3.2.2 skrll 1864 1.3.2.2 skrll /* Toggle port SW reset by AN reset. */ 1865 1.3.2.2 skrll status = ixgbe_read_iosf_sb_reg_x550(hw, 1866 1.3.2.2 skrll IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1867 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1868 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1869 1.3.2.2 skrll return status; 1870 1.3.2.2 skrll reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1871 1.3.2.2 skrll status = ixgbe_write_iosf_sb_reg_x550(hw, 1872 1.3.2.2 skrll IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1873 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1874 1.3.2.2 skrll 1875 1.3.2.2 skrll return status; 1876 1.3.2.2 skrll } 1877 1.3.2.2 skrll 1878 1.3.2.2 skrll /** 1879 1.3.2.2 skrll * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status 1880 1.3.2.2 skrll * @hw: address of hardware structure 1881 1.3.2.2 skrll * @link_up: address of boolean to indicate link status 1882 1.3.2.2 skrll * 1883 1.3.2.2 skrll * Returns error code if unable to get link status. 1884 1.3.2.2 skrll */ 1885 1.3.2.2 skrll static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up) 1886 1.3.2.2 skrll { 1887 1.3.2.2 skrll u32 ret; 1888 1.3.2.2 skrll u16 autoneg_status; 1889 1.3.2.2 skrll 1890 1.3.2.2 skrll *link_up = FALSE; 1891 1.3.2.2 skrll 1892 1.3.2.2 skrll /* read this twice back to back to indicate current status */ 1893 1.3.2.2 skrll ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 1894 1.3.2.2 skrll IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1895 1.3.2.2 skrll &autoneg_status); 1896 1.3.2.2 skrll if (ret != IXGBE_SUCCESS) 1897 1.3.2.2 skrll return ret; 1898 1.3.2.2 skrll 1899 1.3.2.2 skrll ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 1900 1.3.2.2 skrll IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1901 1.3.2.2 skrll &autoneg_status); 1902 1.3.2.2 skrll if (ret != IXGBE_SUCCESS) 1903 1.3.2.2 skrll return ret; 1904 1.3.2.2 skrll 1905 1.3.2.2 skrll *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS); 1906 1.3.2.2 skrll 1907 1.3.2.2 skrll return IXGBE_SUCCESS; 1908 1.3.2.2 skrll } 1909 1.3.2.2 skrll 1910 1.3.2.2 skrll /** 1911 1.3.2.2 skrll * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link 1912 1.3.2.2 skrll * @hw: point to hardware structure 1913 1.3.2.2 skrll * 1914 1.3.2.2 skrll * Configures the link between the integrated KR PHY and the external X557 PHY 1915 1.3.2.2 skrll * The driver will call this function when it gets a link status change 1916 1.3.2.2 skrll * interrupt from the X557 PHY. This function configures the link speed 1917 1.3.2.2 skrll * between the PHYs to match the link speed of the BASE-T link. 1918 1.3.2.2 skrll * 1919 1.3.2.2 skrll * A return of a non-zero value indicates an error, and the base driver should 1920 1.3.2.2 skrll * not report link up. 1921 1.3.2.2 skrll */ 1922 1.3.2.2 skrll s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw) 1923 1.3.2.2 skrll { 1924 1.3.2.2 skrll ixgbe_link_speed force_speed; 1925 1.3.2.2 skrll bool link_up; 1926 1.3.2.2 skrll u32 status; 1927 1.3.2.2 skrll u16 speed; 1928 1.3.2.2 skrll 1929 1.3.2.2 skrll if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 1930 1.3.2.2 skrll return IXGBE_ERR_CONFIG; 1931 1.3.2.2 skrll 1932 1.3.2.2 skrll /* If link is not up, then there is no setup necessary so return */ 1933 1.3.2.2 skrll status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 1934 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1935 1.3.2.2 skrll return status; 1936 1.3.2.2 skrll 1937 1.3.2.2 skrll if (!link_up) 1938 1.3.2.2 skrll return IXGBE_SUCCESS; 1939 1.3.2.2 skrll 1940 1.3.2.2 skrll status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 1941 1.3.2.2 skrll IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1942 1.3.2.2 skrll &speed); 1943 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1944 1.3.2.2 skrll return status; 1945 1.3.2.2 skrll 1946 1.3.2.2 skrll /* If link is not still up, then no setup is necessary so return */ 1947 1.3.2.2 skrll status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 1948 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1949 1.3.2.2 skrll return status; 1950 1.3.2.2 skrll if (!link_up) 1951 1.3.2.2 skrll return IXGBE_SUCCESS; 1952 1.3.2.2 skrll 1953 1.3.2.2 skrll /* clear everything but the speed and duplex bits */ 1954 1.3.2.2 skrll speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK; 1955 1.3.2.2 skrll 1956 1.3.2.2 skrll switch (speed) { 1957 1.3.2.2 skrll case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL: 1958 1.3.2.2 skrll force_speed = IXGBE_LINK_SPEED_10GB_FULL; 1959 1.3.2.2 skrll break; 1960 1.3.2.2 skrll case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL: 1961 1.3.2.2 skrll force_speed = IXGBE_LINK_SPEED_1GB_FULL; 1962 1.3.2.2 skrll break; 1963 1.3.2.2 skrll default: 1964 1.3.2.2 skrll /* Internal PHY does not support anything else */ 1965 1.3.2.2 skrll return IXGBE_ERR_INVALID_LINK_SETTINGS; 1966 1.3.2.2 skrll } 1967 1.3.2.2 skrll 1968 1.3.2.2 skrll return ixgbe_setup_ixfi_x550em(hw, &force_speed); 1969 1.3.2.2 skrll } 1970 1.3.2.2 skrll 1971 1.3.2.2 skrll /** 1972 1.3.2.2 skrll * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback. 1973 1.3.2.2 skrll * @hw: pointer to hardware structure 1974 1.3.2.2 skrll * 1975 1.3.2.2 skrll * Configures the integrated KR PHY to use internal loopback mode. 1976 1.3.2.2 skrll **/ 1977 1.3.2.2 skrll s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw) 1978 1.3.2.2 skrll { 1979 1.3.2.2 skrll s32 status; 1980 1.3.2.2 skrll u32 reg_val; 1981 1.3.2.2 skrll 1982 1.3.2.2 skrll /* Disable AN and force speed to 10G Serial. */ 1983 1.3.2.2 skrll status = ixgbe_read_iosf_sb_reg_x550(hw, 1984 1.3.2.2 skrll IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1985 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1986 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1987 1.3.2.2 skrll return status; 1988 1.3.2.2 skrll reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1989 1.3.2.2 skrll reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1990 1.3.2.2 skrll reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 1991 1.3.2.2 skrll status = ixgbe_write_iosf_sb_reg_x550(hw, 1992 1.3.2.2 skrll IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1993 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1994 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 1995 1.3.2.2 skrll return status; 1996 1.3.2.2 skrll 1997 1.3.2.2 skrll /* Set near-end loopback clocks. */ 1998 1.3.2.2 skrll status = ixgbe_read_iosf_sb_reg_x550(hw, 1999 1.3.2.2 skrll IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id), 2000 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2001 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 2002 1.3.2.2 skrll return status; 2003 1.3.2.2 skrll reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B; 2004 1.3.2.2 skrll reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS; 2005 1.3.2.2 skrll status = ixgbe_write_iosf_sb_reg_x550(hw, 2006 1.3.2.2 skrll IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id), 2007 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2008 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 2009 1.3.2.2 skrll return status; 2010 1.3.2.2 skrll 2011 1.3.2.2 skrll /* Set loopback enable. */ 2012 1.3.2.2 skrll status = ixgbe_read_iosf_sb_reg_x550(hw, 2013 1.3.2.2 skrll IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id), 2014 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2015 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 2016 1.3.2.2 skrll return status; 2017 1.3.2.2 skrll reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK; 2018 1.3.2.2 skrll status = ixgbe_write_iosf_sb_reg_x550(hw, 2019 1.3.2.2 skrll IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id), 2020 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2021 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 2022 1.3.2.2 skrll return status; 2023 1.3.2.2 skrll 2024 1.3.2.2 skrll /* Training bypass. */ 2025 1.3.2.2 skrll status = ixgbe_read_iosf_sb_reg_x550(hw, 2026 1.3.2.2 skrll IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 2027 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2028 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 2029 1.3.2.2 skrll return status; 2030 1.3.2.2 skrll reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS; 2031 1.3.2.2 skrll status = ixgbe_write_iosf_sb_reg_x550(hw, 2032 1.3.2.2 skrll IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 2033 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2034 1.3.2.2 skrll 2035 1.3.2.2 skrll return status; 2036 1.3.2.2 skrll } 2037 1.3.2.2 skrll 2038 1.3.2.2 skrll /** 2039 1.3.2.2 skrll * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 2040 1.3.2.2 skrll * assuming that the semaphore is already obtained. 2041 1.3.2.2 skrll * @hw: pointer to hardware structure 2042 1.3.2.2 skrll * @offset: offset of word in the EEPROM to read 2043 1.3.2.2 skrll * @data: word read from the EEPROM 2044 1.3.2.2 skrll * 2045 1.3.2.2 skrll * Reads a 16 bit word from the EEPROM using the hostif. 2046 1.3.2.2 skrll **/ 2047 1.3.2.2 skrll s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 2048 1.3.2.2 skrll u16 *data) 2049 1.3.2.2 skrll { 2050 1.3.2.2 skrll s32 status; 2051 1.3.2.2 skrll struct ixgbe_hic_read_shadow_ram buffer; 2052 1.3.2.2 skrll 2053 1.3.2.2 skrll DEBUGFUNC("ixgbe_read_ee_hostif_data_X550"); 2054 1.3.2.2 skrll buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 2055 1.3.2.2 skrll buffer.hdr.req.buf_lenh = 0; 2056 1.3.2.2 skrll buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 2057 1.3.2.2 skrll buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 2058 1.3.2.2 skrll 2059 1.3.2.2 skrll /* convert offset from words to bytes */ 2060 1.3.2.2 skrll buffer.address = IXGBE_CPU_TO_BE32(offset * 2); 2061 1.3.2.2 skrll /* one word */ 2062 1.3.2.2 skrll buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16)); 2063 1.3.2.2 skrll 2064 1.3.2.2 skrll status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 2065 1.3.2.2 skrll sizeof(buffer), 2066 1.3.2.2 skrll IXGBE_HI_COMMAND_TIMEOUT, FALSE); 2067 1.3.2.2 skrll 2068 1.3.2.2 skrll if (status) 2069 1.3.2.2 skrll return status; 2070 1.3.2.2 skrll 2071 1.3.2.2 skrll *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 2072 1.3.2.2 skrll FW_NVM_DATA_OFFSET); 2073 1.3.2.2 skrll 2074 1.3.2.2 skrll return 0; 2075 1.3.2.2 skrll } 2076 1.3.2.2 skrll 2077 1.3.2.2 skrll /** 2078 1.3.2.2 skrll * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 2079 1.3.2.2 skrll * @hw: pointer to hardware structure 2080 1.3.2.2 skrll * @offset: offset of word in the EEPROM to read 2081 1.3.2.2 skrll * @data: word read from the EEPROM 2082 1.3.2.2 skrll * 2083 1.3.2.2 skrll * Reads a 16 bit word from the EEPROM using the hostif. 2084 1.3.2.2 skrll **/ 2085 1.3.2.2 skrll s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, 2086 1.3.2.2 skrll u16 *data) 2087 1.3.2.2 skrll { 2088 1.3.2.2 skrll s32 status = IXGBE_SUCCESS; 2089 1.3.2.2 skrll 2090 1.3.2.2 skrll DEBUGFUNC("ixgbe_read_ee_hostif_X550"); 2091 1.3.2.2 skrll 2092 1.3.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 2093 1.3.2.2 skrll IXGBE_SUCCESS) { 2094 1.3.2.2 skrll status = ixgbe_read_ee_hostif_data_X550(hw, offset, data); 2095 1.3.2.2 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2096 1.3.2.2 skrll } else { 2097 1.3.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 2098 1.3.2.2 skrll } 2099 1.3.2.2 skrll 2100 1.3.2.2 skrll return status; 2101 1.3.2.2 skrll } 2102 1.3.2.2 skrll 2103 1.3.2.2 skrll /** 2104 1.3.2.2 skrll * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif 2105 1.3.2.2 skrll * @hw: pointer to hardware structure 2106 1.3.2.2 skrll * @offset: offset of word in the EEPROM to read 2107 1.3.2.2 skrll * @words: number of words 2108 1.3.2.2 skrll * @data: word(s) read from the EEPROM 2109 1.3.2.2 skrll * 2110 1.3.2.2 skrll * Reads a 16 bit word(s) from the EEPROM using the hostif. 2111 1.3.2.2 skrll **/ 2112 1.3.2.2 skrll s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 2113 1.3.2.2 skrll u16 offset, u16 words, u16 *data) 2114 1.3.2.2 skrll { 2115 1.3.2.2 skrll struct ixgbe_hic_read_shadow_ram buffer; 2116 1.3.2.2 skrll u32 current_word = 0; 2117 1.3.2.2 skrll u16 words_to_read; 2118 1.3.2.2 skrll s32 status; 2119 1.3.2.2 skrll u32 i; 2120 1.3.2.2 skrll 2121 1.3.2.2 skrll DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550"); 2122 1.3.2.2 skrll 2123 1.3.2.2 skrll /* Take semaphore for the entire operation. */ 2124 1.3.2.2 skrll status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2125 1.3.2.2 skrll if (status) { 2126 1.3.2.2 skrll DEBUGOUT("EEPROM read buffer - semaphore failed\n"); 2127 1.3.2.2 skrll return status; 2128 1.3.2.2 skrll } 2129 1.3.2.2 skrll while (words) { 2130 1.3.2.2 skrll if (words > FW_MAX_READ_BUFFER_SIZE / 2) 2131 1.3.2.2 skrll words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 2132 1.3.2.2 skrll else 2133 1.3.2.2 skrll words_to_read = words; 2134 1.3.2.2 skrll 2135 1.3.2.2 skrll buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 2136 1.3.2.2 skrll buffer.hdr.req.buf_lenh = 0; 2137 1.3.2.2 skrll buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 2138 1.3.2.2 skrll buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 2139 1.3.2.2 skrll 2140 1.3.2.2 skrll /* convert offset from words to bytes */ 2141 1.3.2.2 skrll buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2); 2142 1.3.2.2 skrll buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2); 2143 1.3.2.2 skrll 2144 1.3.2.2 skrll status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 2145 1.3.2.2 skrll sizeof(buffer), 2146 1.3.2.2 skrll IXGBE_HI_COMMAND_TIMEOUT, 2147 1.3.2.2 skrll FALSE); 2148 1.3.2.2 skrll 2149 1.3.2.2 skrll if (status) { 2150 1.3.2.2 skrll DEBUGOUT("Host interface command failed\n"); 2151 1.3.2.2 skrll goto out; 2152 1.3.2.2 skrll } 2153 1.3.2.2 skrll 2154 1.3.2.2 skrll for (i = 0; i < words_to_read; i++) { 2155 1.3.2.2 skrll u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + 2156 1.3.2.2 skrll 2 * i; 2157 1.3.2.2 skrll u32 value = IXGBE_READ_REG(hw, reg); 2158 1.3.2.2 skrll 2159 1.3.2.2 skrll data[current_word] = (u16)(value & 0xffff); 2160 1.3.2.2 skrll current_word++; 2161 1.3.2.2 skrll i++; 2162 1.3.2.2 skrll if (i < words_to_read) { 2163 1.3.2.2 skrll value >>= 16; 2164 1.3.2.2 skrll data[current_word] = (u16)(value & 0xffff); 2165 1.3.2.2 skrll current_word++; 2166 1.3.2.2 skrll } 2167 1.3.2.2 skrll } 2168 1.3.2.2 skrll words -= words_to_read; 2169 1.3.2.2 skrll } 2170 1.3.2.2 skrll 2171 1.3.2.2 skrll out: 2172 1.3.2.2 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2173 1.3.2.2 skrll return status; 2174 1.3.2.2 skrll } 2175 1.3.2.2 skrll 2176 1.3.2.2 skrll /** 2177 1.3.2.2 skrll * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 2178 1.3.2.2 skrll * @hw: pointer to hardware structure 2179 1.3.2.2 skrll * @offset: offset of word in the EEPROM to write 2180 1.3.2.2 skrll * @data: word write to the EEPROM 2181 1.3.2.2 skrll * 2182 1.3.2.2 skrll * Write a 16 bit word to the EEPROM using the hostif. 2183 1.3.2.2 skrll **/ 2184 1.3.2.2 skrll s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 2185 1.3.2.2 skrll u16 data) 2186 1.3.2.2 skrll { 2187 1.3.2.2 skrll s32 status; 2188 1.3.2.2 skrll struct ixgbe_hic_write_shadow_ram buffer; 2189 1.3.2.2 skrll 2190 1.3.2.2 skrll DEBUGFUNC("ixgbe_write_ee_hostif_data_X550"); 2191 1.3.2.2 skrll 2192 1.3.2.2 skrll buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; 2193 1.3.2.2 skrll buffer.hdr.req.buf_lenh = 0; 2194 1.3.2.2 skrll buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; 2195 1.3.2.2 skrll buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 2196 1.3.2.2 skrll 2197 1.3.2.2 skrll /* one word */ 2198 1.3.2.2 skrll buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16)); 2199 1.3.2.2 skrll buffer.data = data; 2200 1.3.2.2 skrll buffer.address = IXGBE_CPU_TO_BE32(offset * 2); 2201 1.3.2.2 skrll 2202 1.3.2.2 skrll status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 2203 1.3.2.2 skrll sizeof(buffer), 2204 1.3.2.2 skrll IXGBE_HI_COMMAND_TIMEOUT, FALSE); 2205 1.3.2.2 skrll 2206 1.3.2.2 skrll return status; 2207 1.3.2.2 skrll } 2208 1.3.2.2 skrll 2209 1.3.2.2 skrll /** 2210 1.3.2.2 skrll * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 2211 1.3.2.2 skrll * @hw: pointer to hardware structure 2212 1.3.2.2 skrll * @offset: offset of word in the EEPROM to write 2213 1.3.2.2 skrll * @data: word write to the EEPROM 2214 1.3.2.2 skrll * 2215 1.3.2.2 skrll * Write a 16 bit word to the EEPROM using the hostif. 2216 1.3.2.2 skrll **/ 2217 1.3.2.2 skrll s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, 2218 1.3.2.2 skrll u16 data) 2219 1.3.2.2 skrll { 2220 1.3.2.2 skrll s32 status = IXGBE_SUCCESS; 2221 1.3.2.2 skrll 2222 1.3.2.2 skrll DEBUGFUNC("ixgbe_write_ee_hostif_X550"); 2223 1.3.2.2 skrll 2224 1.3.2.2 skrll if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 2225 1.3.2.2 skrll IXGBE_SUCCESS) { 2226 1.3.2.2 skrll status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); 2227 1.3.2.2 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2228 1.3.2.2 skrll } else { 2229 1.3.2.2 skrll DEBUGOUT("write ee hostif failed to get semaphore"); 2230 1.3.2.2 skrll status = IXGBE_ERR_SWFW_SYNC; 2231 1.3.2.2 skrll } 2232 1.3.2.2 skrll 2233 1.3.2.2 skrll return status; 2234 1.3.2.2 skrll } 2235 1.3.2.2 skrll 2236 1.3.2.2 skrll /** 2237 1.3.2.2 skrll * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif 2238 1.3.2.2 skrll * @hw: pointer to hardware structure 2239 1.3.2.2 skrll * @offset: offset of word in the EEPROM to write 2240 1.3.2.2 skrll * @words: number of words 2241 1.3.2.2 skrll * @data: word(s) write to the EEPROM 2242 1.3.2.2 skrll * 2243 1.3.2.2 skrll * Write a 16 bit word(s) to the EEPROM using the hostif. 2244 1.3.2.2 skrll **/ 2245 1.3.2.2 skrll s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 2246 1.3.2.2 skrll u16 offset, u16 words, u16 *data) 2247 1.3.2.2 skrll { 2248 1.3.2.2 skrll s32 status = IXGBE_SUCCESS; 2249 1.3.2.2 skrll u32 i = 0; 2250 1.3.2.2 skrll 2251 1.3.2.2 skrll DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550"); 2252 1.3.2.2 skrll 2253 1.3.2.2 skrll /* Take semaphore for the entire operation. */ 2254 1.3.2.2 skrll status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2255 1.3.2.2 skrll if (status != IXGBE_SUCCESS) { 2256 1.3.2.2 skrll DEBUGOUT("EEPROM write buffer - semaphore failed\n"); 2257 1.3.2.2 skrll goto out; 2258 1.3.2.2 skrll } 2259 1.3.2.2 skrll 2260 1.3.2.2 skrll for (i = 0; i < words; i++) { 2261 1.3.2.2 skrll status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, 2262 1.3.2.2 skrll data[i]); 2263 1.3.2.2 skrll 2264 1.3.2.2 skrll if (status != IXGBE_SUCCESS) { 2265 1.3.2.2 skrll DEBUGOUT("Eeprom buffered write failed\n"); 2266 1.3.2.2 skrll break; 2267 1.3.2.2 skrll } 2268 1.3.2.2 skrll } 2269 1.3.2.2 skrll 2270 1.3.2.2 skrll hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2271 1.3.2.2 skrll out: 2272 1.3.2.2 skrll 2273 1.3.2.2 skrll return status; 2274 1.3.2.2 skrll } 2275 1.3.2.2 skrll 2276 1.3.2.2 skrll /** 2277 1.3.2.2 skrll * ixgbe_checksum_ptr_x550 - Checksum one pointer region 2278 1.3.2.2 skrll * @hw: pointer to hardware structure 2279 1.3.2.2 skrll * @ptr: pointer offset in eeprom 2280 1.3.2.2 skrll * @size: size of section pointed by ptr, if 0 first word will be used as size 2281 1.3.2.2 skrll * @csum: address of checksum to update 2282 1.3.2.2 skrll * 2283 1.3.2.2 skrll * Returns error status for any failure 2284 1.3.2.2 skrll */ 2285 1.3.2.2 skrll static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, 2286 1.3.2.2 skrll u16 size, u16 *csum, u16 *buffer, 2287 1.3.2.2 skrll u32 buffer_size) 2288 1.3.2.2 skrll { 2289 1.3.2.2 skrll u16 buf[256]; 2290 1.3.2.2 skrll s32 status; 2291 1.3.2.2 skrll u16 length, bufsz, i, start; 2292 1.3.2.2 skrll u16 *local_buffer; 2293 1.3.2.2 skrll 2294 1.3.2.2 skrll bufsz = sizeof(buf) / sizeof(buf[0]); 2295 1.3.2.2 skrll 2296 1.3.2.2 skrll /* Read a chunk at the pointer location */ 2297 1.3.2.2 skrll if (!buffer) { 2298 1.3.2.2 skrll status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); 2299 1.3.2.2 skrll if (status) { 2300 1.3.2.2 skrll DEBUGOUT("Failed to read EEPROM image\n"); 2301 1.3.2.2 skrll return status; 2302 1.3.2.2 skrll } 2303 1.3.2.2 skrll local_buffer = buf; 2304 1.3.2.2 skrll } else { 2305 1.3.2.2 skrll if (buffer_size < ptr) 2306 1.3.2.2 skrll return IXGBE_ERR_PARAM; 2307 1.3.2.2 skrll local_buffer = &buffer[ptr]; 2308 1.3.2.2 skrll } 2309 1.3.2.2 skrll 2310 1.3.2.2 skrll if (size) { 2311 1.3.2.2 skrll start = 0; 2312 1.3.2.2 skrll length = size; 2313 1.3.2.2 skrll } else { 2314 1.3.2.2 skrll start = 1; 2315 1.3.2.2 skrll length = local_buffer[0]; 2316 1.3.2.2 skrll 2317 1.3.2.2 skrll /* Skip pointer section if length is invalid. */ 2318 1.3.2.2 skrll if (length == 0xFFFF || length == 0 || 2319 1.3.2.2 skrll (ptr + length) >= hw->eeprom.word_size) 2320 1.3.2.2 skrll return IXGBE_SUCCESS; 2321 1.3.2.2 skrll } 2322 1.3.2.2 skrll 2323 1.3.2.2 skrll if (buffer && ((u32)start + (u32)length > buffer_size)) 2324 1.3.2.2 skrll return IXGBE_ERR_PARAM; 2325 1.3.2.2 skrll 2326 1.3.2.2 skrll for (i = start; length; i++, length--) { 2327 1.3.2.2 skrll if (i == bufsz && !buffer) { 2328 1.3.2.2 skrll ptr += bufsz; 2329 1.3.2.2 skrll i = 0; 2330 1.3.2.2 skrll if (length < bufsz) 2331 1.3.2.2 skrll bufsz = length; 2332 1.3.2.2 skrll 2333 1.3.2.2 skrll /* Read a chunk at the pointer location */ 2334 1.3.2.2 skrll status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, 2335 1.3.2.2 skrll bufsz, buf); 2336 1.3.2.2 skrll if (status) { 2337 1.3.2.2 skrll DEBUGOUT("Failed to read EEPROM image\n"); 2338 1.3.2.2 skrll return status; 2339 1.3.2.2 skrll } 2340 1.3.2.2 skrll } 2341 1.3.2.2 skrll *csum += local_buffer[i]; 2342 1.3.2.2 skrll } 2343 1.3.2.2 skrll return IXGBE_SUCCESS; 2344 1.3.2.2 skrll } 2345 1.3.2.2 skrll 2346 1.3.2.2 skrll /** 2347 1.3.2.2 skrll * ixgbe_calc_checksum_X550 - Calculates and returns the checksum 2348 1.3.2.2 skrll * @hw: pointer to hardware structure 2349 1.3.2.2 skrll * @buffer: pointer to buffer containing calculated checksum 2350 1.3.2.2 skrll * @buffer_size: size of buffer 2351 1.3.2.2 skrll * 2352 1.3.2.2 skrll * Returns a negative error code on error, or the 16-bit checksum 2353 1.3.2.2 skrll **/ 2354 1.3.2.2 skrll s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size) 2355 1.3.2.2 skrll { 2356 1.3.2.2 skrll u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1]; 2357 1.3.2.2 skrll u16 *local_buffer; 2358 1.3.2.2 skrll s32 status; 2359 1.3.2.2 skrll u16 checksum = 0; 2360 1.3.2.2 skrll u16 pointer, i, size; 2361 1.3.2.2 skrll 2362 1.3.2.2 skrll DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550"); 2363 1.3.2.2 skrll 2364 1.3.2.2 skrll hw->eeprom.ops.init_params(hw); 2365 1.3.2.2 skrll 2366 1.3.2.2 skrll if (!buffer) { 2367 1.3.2.2 skrll /* Read pointer area */ 2368 1.3.2.2 skrll status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, 2369 1.3.2.2 skrll IXGBE_EEPROM_LAST_WORD + 1, 2370 1.3.2.2 skrll eeprom_ptrs); 2371 1.3.2.2 skrll if (status) { 2372 1.3.2.2 skrll DEBUGOUT("Failed to read EEPROM image\n"); 2373 1.3.2.2 skrll return status; 2374 1.3.2.2 skrll } 2375 1.3.2.2 skrll local_buffer = eeprom_ptrs; 2376 1.3.2.2 skrll } else { 2377 1.3.2.2 skrll if (buffer_size < IXGBE_EEPROM_LAST_WORD) 2378 1.3.2.2 skrll return IXGBE_ERR_PARAM; 2379 1.3.2.2 skrll local_buffer = buffer; 2380 1.3.2.2 skrll } 2381 1.3.2.2 skrll 2382 1.3.2.2 skrll /* 2383 1.3.2.2 skrll * For X550 hardware include 0x0-0x41 in the checksum, skip the 2384 1.3.2.2 skrll * checksum word itself 2385 1.3.2.2 skrll */ 2386 1.3.2.2 skrll for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++) 2387 1.3.2.2 skrll if (i != IXGBE_EEPROM_CHECKSUM) 2388 1.3.2.2 skrll checksum += local_buffer[i]; 2389 1.3.2.2 skrll 2390 1.3.2.2 skrll /* 2391 1.3.2.2 skrll * Include all data from pointers 0x3, 0x6-0xE. This excludes the 2392 1.3.2.2 skrll * FW, PHY module, and PCIe Expansion/Option ROM pointers. 2393 1.3.2.2 skrll */ 2394 1.3.2.2 skrll for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) { 2395 1.3.2.2 skrll if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 2396 1.3.2.2 skrll continue; 2397 1.3.2.2 skrll 2398 1.3.2.2 skrll pointer = local_buffer[i]; 2399 1.3.2.2 skrll 2400 1.3.2.2 skrll /* Skip pointer section if the pointer is invalid. */ 2401 1.3.2.2 skrll if (pointer == 0xFFFF || pointer == 0 || 2402 1.3.2.2 skrll pointer >= hw->eeprom.word_size) 2403 1.3.2.2 skrll continue; 2404 1.3.2.2 skrll 2405 1.3.2.2 skrll switch (i) { 2406 1.3.2.2 skrll case IXGBE_PCIE_GENERAL_PTR: 2407 1.3.2.2 skrll size = IXGBE_IXGBE_PCIE_GENERAL_SIZE; 2408 1.3.2.2 skrll break; 2409 1.3.2.2 skrll case IXGBE_PCIE_CONFIG0_PTR: 2410 1.3.2.2 skrll case IXGBE_PCIE_CONFIG1_PTR: 2411 1.3.2.2 skrll size = IXGBE_PCIE_CONFIG_SIZE; 2412 1.3.2.2 skrll break; 2413 1.3.2.2 skrll default: 2414 1.3.2.2 skrll size = 0; 2415 1.3.2.2 skrll break; 2416 1.3.2.2 skrll } 2417 1.3.2.2 skrll 2418 1.3.2.2 skrll status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, 2419 1.3.2.2 skrll buffer, buffer_size); 2420 1.3.2.2 skrll if (status) 2421 1.3.2.2 skrll return status; 2422 1.3.2.2 skrll } 2423 1.3.2.2 skrll 2424 1.3.2.2 skrll checksum = (u16)IXGBE_EEPROM_SUM - checksum; 2425 1.3.2.2 skrll 2426 1.3.2.2 skrll return (s32)checksum; 2427 1.3.2.2 skrll } 2428 1.3.2.2 skrll 2429 1.3.2.2 skrll /** 2430 1.3.2.2 skrll * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum 2431 1.3.2.2 skrll * @hw: pointer to hardware structure 2432 1.3.2.2 skrll * 2433 1.3.2.2 skrll * Returns a negative error code on error, or the 16-bit checksum 2434 1.3.2.2 skrll **/ 2435 1.3.2.2 skrll s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) 2436 1.3.2.2 skrll { 2437 1.3.2.2 skrll return ixgbe_calc_checksum_X550(hw, NULL, 0); 2438 1.3.2.2 skrll } 2439 1.3.2.2 skrll 2440 1.3.2.2 skrll /** 2441 1.3.2.2 skrll * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum 2442 1.3.2.2 skrll * @hw: pointer to hardware structure 2443 1.3.2.2 skrll * @checksum_val: calculated checksum 2444 1.3.2.2 skrll * 2445 1.3.2.2 skrll * Performs checksum calculation and validates the EEPROM checksum. If the 2446 1.3.2.2 skrll * caller does not need checksum_val, the value can be NULL. 2447 1.3.2.2 skrll **/ 2448 1.3.2.2 skrll s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val) 2449 1.3.2.2 skrll { 2450 1.3.2.2 skrll s32 status; 2451 1.3.2.2 skrll u16 checksum; 2452 1.3.2.2 skrll u16 read_checksum = 0; 2453 1.3.2.2 skrll 2454 1.3.2.2 skrll DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550"); 2455 1.3.2.2 skrll 2456 1.3.2.2 skrll /* Read the first word from the EEPROM. If this times out or fails, do 2457 1.3.2.2 skrll * not continue or we could be in for a very long wait while every 2458 1.3.2.2 skrll * EEPROM read fails 2459 1.3.2.2 skrll */ 2460 1.3.2.2 skrll status = hw->eeprom.ops.read(hw, 0, &checksum); 2461 1.3.2.2 skrll if (status) { 2462 1.3.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 2463 1.3.2.2 skrll return status; 2464 1.3.2.2 skrll } 2465 1.3.2.2 skrll 2466 1.3.2.2 skrll status = hw->eeprom.ops.calc_checksum(hw); 2467 1.3.2.2 skrll if (status < 0) 2468 1.3.2.2 skrll return status; 2469 1.3.2.2 skrll 2470 1.3.2.2 skrll checksum = (u16)(status & 0xffff); 2471 1.3.2.2 skrll 2472 1.3.2.2 skrll status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 2473 1.3.2.2 skrll &read_checksum); 2474 1.3.2.2 skrll if (status) 2475 1.3.2.2 skrll return status; 2476 1.3.2.2 skrll 2477 1.3.2.2 skrll /* Verify read checksum from EEPROM is the same as 2478 1.3.2.2 skrll * calculated checksum 2479 1.3.2.2 skrll */ 2480 1.3.2.2 skrll if (read_checksum != checksum) { 2481 1.3.2.2 skrll status = IXGBE_ERR_EEPROM_CHECKSUM; 2482 1.3.2.2 skrll ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 2483 1.3.2.2 skrll "Invalid EEPROM checksum"); 2484 1.3.2.2 skrll } 2485 1.3.2.2 skrll 2486 1.3.2.2 skrll /* If the user cares, return the calculated checksum */ 2487 1.3.2.2 skrll if (checksum_val) 2488 1.3.2.2 skrll *checksum_val = checksum; 2489 1.3.2.2 skrll 2490 1.3.2.2 skrll return status; 2491 1.3.2.2 skrll } 2492 1.3.2.2 skrll 2493 1.3.2.2 skrll /** 2494 1.3.2.2 skrll * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash 2495 1.3.2.2 skrll * @hw: pointer to hardware structure 2496 1.3.2.2 skrll * 2497 1.3.2.2 skrll * After writing EEPROM to shadow RAM using EEWR register, software calculates 2498 1.3.2.2 skrll * checksum and updates the EEPROM and instructs the hardware to update 2499 1.3.2.2 skrll * the flash. 2500 1.3.2.2 skrll **/ 2501 1.3.2.2 skrll s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) 2502 1.3.2.2 skrll { 2503 1.3.2.2 skrll s32 status; 2504 1.3.2.2 skrll u16 checksum = 0; 2505 1.3.2.2 skrll 2506 1.3.2.2 skrll DEBUGFUNC("ixgbe_update_eeprom_checksum_X550"); 2507 1.3.2.2 skrll 2508 1.3.2.2 skrll /* Read the first word from the EEPROM. If this times out or fails, do 2509 1.3.2.2 skrll * not continue or we could be in for a very long wait while every 2510 1.3.2.2 skrll * EEPROM read fails 2511 1.3.2.2 skrll */ 2512 1.3.2.2 skrll status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); 2513 1.3.2.2 skrll if (status) { 2514 1.3.2.2 skrll DEBUGOUT("EEPROM read failed\n"); 2515 1.3.2.2 skrll return status; 2516 1.3.2.2 skrll } 2517 1.3.2.2 skrll 2518 1.3.2.2 skrll status = ixgbe_calc_eeprom_checksum_X550(hw); 2519 1.3.2.2 skrll if (status < 0) 2520 1.3.2.2 skrll return status; 2521 1.3.2.2 skrll 2522 1.3.2.2 skrll checksum = (u16)(status & 0xffff); 2523 1.3.2.2 skrll 2524 1.3.2.2 skrll status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 2525 1.3.2.2 skrll checksum); 2526 1.3.2.2 skrll if (status) 2527 1.3.2.2 skrll return status; 2528 1.3.2.2 skrll 2529 1.3.2.2 skrll status = ixgbe_update_flash_X550(hw); 2530 1.3.2.2 skrll 2531 1.3.2.2 skrll return status; 2532 1.3.2.2 skrll } 2533 1.3.2.2 skrll 2534 1.3.2.2 skrll /** 2535 1.3.2.2 skrll * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device 2536 1.3.2.2 skrll * @hw: pointer to hardware structure 2537 1.3.2.2 skrll * 2538 1.3.2.2 skrll * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash. 2539 1.3.2.2 skrll **/ 2540 1.3.2.2 skrll s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) 2541 1.3.2.2 skrll { 2542 1.3.2.2 skrll s32 status = IXGBE_SUCCESS; 2543 1.3.2.2 skrll union ixgbe_hic_hdr2 buffer; 2544 1.3.2.2 skrll 2545 1.3.2.2 skrll DEBUGFUNC("ixgbe_update_flash_X550"); 2546 1.3.2.2 skrll 2547 1.3.2.2 skrll buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; 2548 1.3.2.2 skrll buffer.req.buf_lenh = 0; 2549 1.3.2.2 skrll buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; 2550 1.3.2.2 skrll buffer.req.checksum = FW_DEFAULT_CHECKSUM; 2551 1.3.2.2 skrll 2552 1.3.2.2 skrll status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 2553 1.3.2.2 skrll sizeof(buffer), 2554 1.3.2.2 skrll IXGBE_HI_COMMAND_TIMEOUT, FALSE); 2555 1.3.2.2 skrll 2556 1.3.2.2 skrll return status; 2557 1.3.2.2 skrll } 2558 1.3.2.2 skrll 2559 1.3.2.2 skrll /** 2560 1.3.2.2 skrll * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type 2561 1.3.2.2 skrll * @hw: pointer to hardware structure 2562 1.3.2.2 skrll * 2563 1.3.2.2 skrll * Determines physical layer capabilities of the current configuration. 2564 1.3.2.2 skrll **/ 2565 1.3.2.2 skrll u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw) 2566 1.3.2.2 skrll { 2567 1.3.2.2 skrll u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 2568 1.3.2.2 skrll u16 ext_ability = 0; 2569 1.3.2.2 skrll 2570 1.3.2.2 skrll DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em"); 2571 1.3.2.2 skrll 2572 1.3.2.2 skrll hw->phy.ops.identify(hw); 2573 1.3.2.2 skrll 2574 1.3.2.2 skrll switch (hw->phy.type) { 2575 1.3.2.2 skrll case ixgbe_phy_x550em_kr: 2576 1.3.2.2 skrll physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR | 2577 1.3.2.2 skrll IXGBE_PHYSICAL_LAYER_1000BASE_KX; 2578 1.3.2.2 skrll break; 2579 1.3.2.2 skrll case ixgbe_phy_x550em_kx4: 2580 1.3.2.2 skrll physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 | 2581 1.3.2.2 skrll IXGBE_PHYSICAL_LAYER_1000BASE_KX; 2582 1.3.2.2 skrll break; 2583 1.3.2.2 skrll case ixgbe_phy_x550em_ext_t: 2584 1.3.2.2 skrll hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 2585 1.3.2.2 skrll IXGBE_MDIO_PMA_PMD_DEV_TYPE, 2586 1.3.2.2 skrll &ext_ability); 2587 1.3.2.2 skrll if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 2588 1.3.2.2 skrll physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 2589 1.3.2.2 skrll if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 2590 1.3.2.2 skrll physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 2591 1.3.2.2 skrll break; 2592 1.3.2.2 skrll default: 2593 1.3.2.2 skrll break; 2594 1.3.2.2 skrll } 2595 1.3.2.2 skrll 2596 1.3.2.2 skrll if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) 2597 1.3.2.2 skrll physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw); 2598 1.3.2.2 skrll 2599 1.3.2.2 skrll return physical_layer; 2600 1.3.2.2 skrll } 2601 1.3.2.2 skrll 2602 1.3.2.2 skrll /** 2603 1.3.2.2 skrll * ixgbe_get_bus_info_x550em - Set PCI bus info 2604 1.3.2.2 skrll * @hw: pointer to hardware structure 2605 1.3.2.2 skrll * 2606 1.3.2.2 skrll * Sets bus link width and speed to unknown because X550em is 2607 1.3.2.2 skrll * not a PCI device. 2608 1.3.2.2 skrll **/ 2609 1.3.2.2 skrll s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw) 2610 1.3.2.2 skrll { 2611 1.3.2.2 skrll 2612 1.3.2.2 skrll DEBUGFUNC("ixgbe_get_bus_info_x550em"); 2613 1.3.2.2 skrll 2614 1.3.2.2 skrll hw->bus.width = ixgbe_bus_width_unknown; 2615 1.3.2.2 skrll hw->bus.speed = ixgbe_bus_speed_unknown; 2616 1.3.2.2 skrll 2617 1.3.2.2 skrll hw->mac.ops.set_lan_id(hw); 2618 1.3.2.2 skrll 2619 1.3.2.2 skrll return IXGBE_SUCCESS; 2620 1.3.2.2 skrll } 2621 1.3.2.2 skrll 2622 1.3.2.2 skrll /** 2623 1.3.2.2 skrll * ixgbe_disable_rx_x550 - Disable RX unit 2624 1.3.2.2 skrll * 2625 1.3.2.2 skrll * Enables the Rx DMA unit for x550 2626 1.3.2.2 skrll **/ 2627 1.3.2.2 skrll void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) 2628 1.3.2.2 skrll { 2629 1.3.2.2 skrll u32 rxctrl, pfdtxgswc; 2630 1.3.2.2 skrll s32 status; 2631 1.3.2.2 skrll struct ixgbe_hic_disable_rxen fw_cmd; 2632 1.3.2.2 skrll 2633 1.3.2.2 skrll DEBUGFUNC("ixgbe_enable_rx_dma_x550"); 2634 1.3.2.2 skrll 2635 1.3.2.2 skrll rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 2636 1.3.2.2 skrll if (rxctrl & IXGBE_RXCTRL_RXEN) { 2637 1.3.2.2 skrll pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 2638 1.3.2.2 skrll if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 2639 1.3.2.2 skrll pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 2640 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 2641 1.3.2.2 skrll hw->mac.set_lben = TRUE; 2642 1.3.2.2 skrll } else { 2643 1.3.2.2 skrll hw->mac.set_lben = FALSE; 2644 1.3.2.2 skrll } 2645 1.3.2.2 skrll 2646 1.3.2.2 skrll fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD; 2647 1.3.2.2 skrll fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN; 2648 1.3.2.2 skrll fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 2649 1.3.2.2 skrll fw_cmd.port_number = (u8)hw->bus.lan_id; 2650 1.3.2.2 skrll 2651 1.3.2.2 skrll status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 2652 1.3.2.2 skrll sizeof(struct ixgbe_hic_disable_rxen), 2653 1.3.2.2 skrll IXGBE_HI_COMMAND_TIMEOUT, TRUE); 2654 1.3.2.2 skrll 2655 1.3.2.2 skrll /* If we fail - disable RX using register write */ 2656 1.3.2.2 skrll if (status) { 2657 1.3.2.2 skrll rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 2658 1.3.2.2 skrll if (rxctrl & IXGBE_RXCTRL_RXEN) { 2659 1.3.2.2 skrll rxctrl &= ~IXGBE_RXCTRL_RXEN; 2660 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 2661 1.3.2.2 skrll } 2662 1.3.2.2 skrll } 2663 1.3.2.2 skrll } 2664 1.3.2.2 skrll } 2665 1.3.2.2 skrll 2666 1.3.2.2 skrll /** 2667 1.3.2.2 skrll * ixgbe_enter_lplu_x550em - Transition to low power states 2668 1.3.2.2 skrll * @hw: pointer to hardware structure 2669 1.3.2.2 skrll * 2670 1.3.2.2 skrll * Configures Low Power Link Up on transition to low power states 2671 1.3.2.2 skrll * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the 2672 1.3.2.2 skrll * X557 PHY immediately prior to entering LPLU. 2673 1.3.2.2 skrll **/ 2674 1.3.2.2 skrll s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) 2675 1.3.2.2 skrll { 2676 1.3.2.2 skrll u16 an_10g_cntl_reg, autoneg_reg, speed; 2677 1.3.2.2 skrll s32 status; 2678 1.3.2.2 skrll ixgbe_link_speed lcd_speed; 2679 1.3.2.2 skrll u32 save_autoneg; 2680 1.3.2.2 skrll bool link_up; 2681 1.3.2.2 skrll 2682 1.3.2.2 skrll /* SW LPLU not required on later HW revisions. */ 2683 1.3.2.2 skrll if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))) 2684 1.3.2.2 skrll return IXGBE_SUCCESS; 2685 1.3.2.2 skrll 2686 1.3.2.2 skrll /* If blocked by MNG FW, then don't restart AN */ 2687 1.3.2.2 skrll if (ixgbe_check_reset_blocked(hw)) 2688 1.3.2.2 skrll return IXGBE_SUCCESS; 2689 1.3.2.2 skrll 2690 1.3.2.2 skrll status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2691 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 2692 1.3.2.2 skrll return status; 2693 1.3.2.2 skrll 2694 1.3.2.2 skrll status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3); 2695 1.3.2.2 skrll 2696 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 2697 1.3.2.2 skrll return status; 2698 1.3.2.2 skrll 2699 1.3.2.2 skrll /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability 2700 1.3.2.2 skrll * disabled, then force link down by entering low power mode. 2701 1.3.2.2 skrll */ 2702 1.3.2.2 skrll if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) || 2703 1.3.2.2 skrll !(hw->wol_enabled || ixgbe_mng_present(hw))) 2704 1.3.2.2 skrll return ixgbe_set_copper_phy_power(hw, FALSE); 2705 1.3.2.2 skrll 2706 1.3.2.2 skrll /* Determine LCD */ 2707 1.3.2.2 skrll status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed); 2708 1.3.2.2 skrll 2709 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 2710 1.3.2.2 skrll return status; 2711 1.3.2.2 skrll 2712 1.3.2.2 skrll /* If no valid LCD link speed, then force link down and exit. */ 2713 1.3.2.2 skrll if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN) 2714 1.3.2.2 skrll return ixgbe_set_copper_phy_power(hw, FALSE); 2715 1.3.2.2 skrll 2716 1.3.2.2 skrll status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 2717 1.3.2.2 skrll IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2718 1.3.2.2 skrll &speed); 2719 1.3.2.2 skrll 2720 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 2721 1.3.2.2 skrll return status; 2722 1.3.2.2 skrll 2723 1.3.2.2 skrll /* If no link now, speed is invalid so take link down */ 2724 1.3.2.2 skrll status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2725 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 2726 1.3.2.2 skrll return ixgbe_set_copper_phy_power(hw, FALSE); 2727 1.3.2.2 skrll 2728 1.3.2.2 skrll /* clear everything but the speed bits */ 2729 1.3.2.2 skrll speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK; 2730 1.3.2.2 skrll 2731 1.3.2.2 skrll /* If current speed is already LCD, then exit. */ 2732 1.3.2.2 skrll if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) && 2733 1.3.2.2 skrll (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) || 2734 1.3.2.2 skrll ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) && 2735 1.3.2.2 skrll (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL))) 2736 1.3.2.2 skrll return status; 2737 1.3.2.2 skrll 2738 1.3.2.2 skrll /* Clear AN completed indication */ 2739 1.3.2.2 skrll status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM, 2740 1.3.2.2 skrll IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2741 1.3.2.2 skrll &autoneg_reg); 2742 1.3.2.2 skrll 2743 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 2744 1.3.2.2 skrll return status; 2745 1.3.2.2 skrll 2746 1.3.2.2 skrll status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 2747 1.3.2.2 skrll IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2748 1.3.2.2 skrll &an_10g_cntl_reg); 2749 1.3.2.2 skrll 2750 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 2751 1.3.2.2 skrll return status; 2752 1.3.2.2 skrll 2753 1.3.2.2 skrll status = hw->phy.ops.read_reg(hw, 2754 1.3.2.2 skrll IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 2755 1.3.2.2 skrll IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2756 1.3.2.2 skrll &autoneg_reg); 2757 1.3.2.2 skrll 2758 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 2759 1.3.2.2 skrll return status; 2760 1.3.2.2 skrll 2761 1.3.2.2 skrll save_autoneg = hw->phy.autoneg_advertised; 2762 1.3.2.2 skrll 2763 1.3.2.2 skrll /* Setup link at least common link speed */ 2764 1.3.2.2 skrll status = hw->mac.ops.setup_link(hw, lcd_speed, FALSE); 2765 1.3.2.2 skrll 2766 1.3.2.2 skrll /* restore autoneg from before setting lplu speed */ 2767 1.3.2.2 skrll hw->phy.autoneg_advertised = save_autoneg; 2768 1.3.2.2 skrll 2769 1.3.2.2 skrll return status; 2770 1.3.2.2 skrll } 2771 1.3.2.2 skrll 2772 1.3.2.2 skrll /** 2773 1.3.2.2 skrll * ixgbe_get_lcd_x550em - Determine lowest common denominator 2774 1.3.2.2 skrll * @hw: pointer to hardware structure 2775 1.3.2.2 skrll * @lcd_speed: pointer to lowest common link speed 2776 1.3.2.2 skrll * 2777 1.3.2.2 skrll * Determine lowest common link speed with link partner. 2778 1.3.2.2 skrll **/ 2779 1.3.2.2 skrll s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed) 2780 1.3.2.2 skrll { 2781 1.3.2.2 skrll u16 an_lp_status; 2782 1.3.2.2 skrll s32 status; 2783 1.3.2.2 skrll u16 word = hw->eeprom.ctrl_word_3; 2784 1.3.2.2 skrll 2785 1.3.2.2 skrll *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN; 2786 1.3.2.2 skrll 2787 1.3.2.2 skrll status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS, 2788 1.3.2.2 skrll IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2789 1.3.2.2 skrll &an_lp_status); 2790 1.3.2.2 skrll 2791 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 2792 1.3.2.2 skrll return status; 2793 1.3.2.2 skrll 2794 1.3.2.2 skrll /* If link partner advertised 1G, return 1G */ 2795 1.3.2.2 skrll if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) { 2796 1.3.2.2 skrll *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL; 2797 1.3.2.2 skrll return status; 2798 1.3.2.2 skrll } 2799 1.3.2.2 skrll 2800 1.3.2.2 skrll /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */ 2801 1.3.2.2 skrll if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) || 2802 1.3.2.2 skrll (word & NVM_INIT_CTRL_3_D10GMP_PORT0)) 2803 1.3.2.2 skrll return status; 2804 1.3.2.2 skrll 2805 1.3.2.2 skrll /* Link partner not capable of lower speeds, return 10G */ 2806 1.3.2.2 skrll *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL; 2807 1.3.2.2 skrll return status; 2808 1.3.2.2 skrll } 2809 1.3.2.2 skrll 2810 1.3.2.2 skrll /** 2811 1.3.2.2 skrll * ixgbe_setup_fc_X550em - Set up flow control 2812 1.3.2.2 skrll * @hw: pointer to hardware structure 2813 1.3.2.2 skrll * 2814 1.3.2.2 skrll * Called at init time to set up flow control. 2815 1.3.2.2 skrll **/ 2816 1.3.2.2 skrll s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw) 2817 1.3.2.2 skrll { 2818 1.3.2.2 skrll s32 ret_val = IXGBE_SUCCESS; 2819 1.3.2.2 skrll u32 pause, asm_dir, reg_val; 2820 1.3.2.2 skrll 2821 1.3.2.2 skrll DEBUGFUNC("ixgbe_setup_fc_X550em"); 2822 1.3.2.2 skrll 2823 1.3.2.2 skrll /* Validate the requested mode */ 2824 1.3.2.2 skrll if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 2825 1.3.2.2 skrll ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 2826 1.3.2.2 skrll "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 2827 1.3.2.2 skrll ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2828 1.3.2.2 skrll goto out; 2829 1.3.2.2 skrll } 2830 1.3.2.2 skrll 2831 1.3.2.2 skrll /* 10gig parts do not have a word in the EEPROM to determine the 2832 1.3.2.2 skrll * default flow control setting, so we explicitly set it to full. 2833 1.3.2.2 skrll */ 2834 1.3.2.2 skrll if (hw->fc.requested_mode == ixgbe_fc_default) 2835 1.3.2.2 skrll hw->fc.requested_mode = ixgbe_fc_full; 2836 1.3.2.2 skrll 2837 1.3.2.2 skrll /* Determine PAUSE and ASM_DIR bits. */ 2838 1.3.2.2 skrll switch (hw->fc.requested_mode) { 2839 1.3.2.2 skrll case ixgbe_fc_none: 2840 1.3.2.2 skrll pause = 0; 2841 1.3.2.2 skrll asm_dir = 0; 2842 1.3.2.2 skrll break; 2843 1.3.2.2 skrll case ixgbe_fc_tx_pause: 2844 1.3.2.2 skrll pause = 0; 2845 1.3.2.2 skrll asm_dir = 1; 2846 1.3.2.2 skrll break; 2847 1.3.2.2 skrll case ixgbe_fc_rx_pause: 2848 1.3.2.2 skrll /* Rx Flow control is enabled and Tx Flow control is 2849 1.3.2.2 skrll * disabled by software override. Since there really 2850 1.3.2.2 skrll * isn't a way to advertise that we are capable of RX 2851 1.3.2.2 skrll * Pause ONLY, we will advertise that we support both 2852 1.3.2.2 skrll * symmetric and asymmetric Rx PAUSE, as such we fall 2853 1.3.2.2 skrll * through to the fc_full statement. Later, we will 2854 1.3.2.2 skrll * disable the adapter's ability to send PAUSE frames. 2855 1.3.2.2 skrll */ 2856 1.3.2.2 skrll case ixgbe_fc_full: 2857 1.3.2.2 skrll pause = 1; 2858 1.3.2.2 skrll asm_dir = 1; 2859 1.3.2.2 skrll break; 2860 1.3.2.2 skrll default: 2861 1.3.2.2 skrll ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 2862 1.3.2.2 skrll "Flow control param set incorrectly\n"); 2863 1.3.2.2 skrll ret_val = IXGBE_ERR_CONFIG; 2864 1.3.2.2 skrll goto out; 2865 1.3.2.2 skrll } 2866 1.3.2.2 skrll 2867 1.3.2.2 skrll if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) { 2868 1.3.2.2 skrll ret_val = ixgbe_read_iosf_sb_reg_x550(hw, 2869 1.3.2.2 skrll IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2870 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2871 1.3.2.2 skrll if (ret_val != IXGBE_SUCCESS) 2872 1.3.2.2 skrll goto out; 2873 1.3.2.2 skrll reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 2874 1.3.2.2 skrll IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 2875 1.3.2.2 skrll if (pause) 2876 1.3.2.2 skrll reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 2877 1.3.2.2 skrll if (asm_dir) 2878 1.3.2.2 skrll reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 2879 1.3.2.2 skrll ret_val = ixgbe_write_iosf_sb_reg_x550(hw, 2880 1.3.2.2 skrll IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2881 1.3.2.2 skrll IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2882 1.3.2.2 skrll 2883 1.3.2.2 skrll /* This device does not fully support AN. */ 2884 1.3.2.2 skrll hw->fc.disable_fc_autoneg = TRUE; 2885 1.3.2.2 skrll } 2886 1.3.2.2 skrll 2887 1.3.2.2 skrll out: 2888 1.3.2.2 skrll return ret_val; 2889 1.3.2.2 skrll } 2890 1.3.2.2 skrll 2891 1.3.2.2 skrll /** 2892 1.3.2.2 skrll * ixgbe_set_mux - Set mux for port 1 access with CS4227 2893 1.3.2.2 skrll * @hw: pointer to hardware structure 2894 1.3.2.2 skrll * @state: set mux if 1, clear if 0 2895 1.3.2.2 skrll */ 2896 1.3.2.2 skrll static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state) 2897 1.3.2.2 skrll { 2898 1.3.2.2 skrll u32 esdp; 2899 1.3.2.2 skrll 2900 1.3.2.2 skrll if (!hw->bus.lan_id) 2901 1.3.2.2 skrll return; 2902 1.3.2.2 skrll esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2903 1.3.2.2 skrll if (state) 2904 1.3.2.2 skrll esdp |= IXGBE_ESDP_SDP1; 2905 1.3.2.2 skrll else 2906 1.3.2.2 skrll esdp &= ~IXGBE_ESDP_SDP1; 2907 1.3.2.2 skrll IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2908 1.3.2.2 skrll IXGBE_WRITE_FLUSH(hw); 2909 1.3.2.2 skrll } 2910 1.3.2.2 skrll 2911 1.3.2.2 skrll /** 2912 1.3.2.2 skrll * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore 2913 1.3.2.2 skrll * @hw: pointer to hardware structure 2914 1.3.2.2 skrll * @mask: Mask to specify which semaphore to acquire 2915 1.3.2.2 skrll * 2916 1.3.2.2 skrll * Acquires the SWFW semaphore and sets the I2C MUX 2917 1.3.2.2 skrll **/ 2918 1.3.2.2 skrll s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 2919 1.3.2.2 skrll { 2920 1.3.2.2 skrll s32 status; 2921 1.3.2.2 skrll 2922 1.3.2.2 skrll DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em"); 2923 1.3.2.2 skrll 2924 1.3.2.2 skrll status = ixgbe_acquire_swfw_sync_X540(hw, mask); 2925 1.3.2.2 skrll if (status) 2926 1.3.2.2 skrll return status; 2927 1.3.2.2 skrll 2928 1.3.2.2 skrll if (mask & IXGBE_GSSR_I2C_MASK) 2929 1.3.2.2 skrll ixgbe_set_mux(hw, 1); 2930 1.3.2.2 skrll 2931 1.3.2.2 skrll return IXGBE_SUCCESS; 2932 1.3.2.2 skrll } 2933 1.3.2.2 skrll 2934 1.3.2.2 skrll /** 2935 1.3.2.2 skrll * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore 2936 1.3.2.2 skrll * @hw: pointer to hardware structure 2937 1.3.2.2 skrll * @mask: Mask to specify which semaphore to release 2938 1.3.2.2 skrll * 2939 1.3.2.2 skrll * Releases the SWFW semaphore and sets the I2C MUX 2940 1.3.2.2 skrll **/ 2941 1.3.2.2 skrll void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 2942 1.3.2.2 skrll { 2943 1.3.2.2 skrll DEBUGFUNC("ixgbe_release_swfw_sync_X550em"); 2944 1.3.2.2 skrll 2945 1.3.2.2 skrll if (mask & IXGBE_GSSR_I2C_MASK) 2946 1.3.2.2 skrll ixgbe_set_mux(hw, 0); 2947 1.3.2.2 skrll 2948 1.3.2.2 skrll ixgbe_release_swfw_sync_X540(hw, mask); 2949 1.3.2.2 skrll } 2950 1.3.2.2 skrll 2951 1.3.2.2 skrll /** 2952 1.3.2.2 skrll * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt 2953 1.3.2.2 skrll * @hw: pointer to hardware structure 2954 1.3.2.2 skrll * 2955 1.3.2.2 skrll * Handle external Base T PHY interrupt. If high temperature 2956 1.3.2.2 skrll * failure alarm then return error, else if link status change 2957 1.3.2.2 skrll * then setup internal/external PHY link 2958 1.3.2.2 skrll * 2959 1.3.2.2 skrll * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 2960 1.3.2.2 skrll * failure alarm, else return PHY access status. 2961 1.3.2.2 skrll */ 2962 1.3.2.2 skrll s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw) 2963 1.3.2.2 skrll { 2964 1.3.2.2 skrll bool lsc; 2965 1.3.2.2 skrll u32 status; 2966 1.3.2.2 skrll 2967 1.3.2.2 skrll status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 2968 1.3.2.2 skrll 2969 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 2970 1.3.2.2 skrll return status; 2971 1.3.2.2 skrll 2972 1.3.2.2 skrll if (lsc) 2973 1.3.2.2 skrll return ixgbe_setup_internal_phy(hw); 2974 1.3.2.2 skrll 2975 1.3.2.2 skrll return IXGBE_SUCCESS; 2976 1.3.2.2 skrll } 2977 1.3.2.2 skrll 2978 1.3.2.2 skrll /** 2979 1.3.2.2 skrll * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed 2980 1.3.2.2 skrll * @hw: pointer to hardware structure 2981 1.3.2.2 skrll * @speed: new link speed 2982 1.3.2.2 skrll * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 2983 1.3.2.2 skrll * 2984 1.3.2.2 skrll * Setup internal/external PHY link speed based on link speed, then set 2985 1.3.2.2 skrll * external PHY auto advertised link speed. 2986 1.3.2.2 skrll * 2987 1.3.2.2 skrll * Returns error status for any failure 2988 1.3.2.2 skrll **/ 2989 1.3.2.2 skrll s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, 2990 1.3.2.2 skrll ixgbe_link_speed speed, 2991 1.3.2.2 skrll bool autoneg_wait_to_complete) 2992 1.3.2.2 skrll { 2993 1.3.2.2 skrll s32 status; 2994 1.3.2.2 skrll ixgbe_link_speed force_speed; 2995 1.3.2.2 skrll 2996 1.3.2.2 skrll DEBUGFUNC("ixgbe_setup_mac_link_t_X550em"); 2997 1.3.2.2 skrll 2998 1.3.2.2 skrll /* Setup internal/external PHY link speed to iXFI (10G), unless 2999 1.3.2.2 skrll * only 1G is auto advertised then setup KX link. 3000 1.3.2.2 skrll */ 3001 1.3.2.2 skrll if (speed & IXGBE_LINK_SPEED_10GB_FULL) 3002 1.3.2.2 skrll force_speed = IXGBE_LINK_SPEED_10GB_FULL; 3003 1.3.2.2 skrll else 3004 1.3.2.2 skrll force_speed = IXGBE_LINK_SPEED_1GB_FULL; 3005 1.3.2.2 skrll 3006 1.3.2.2 skrll /* If internal link mode is XFI, then setup XFI internal link. */ 3007 1.3.2.2 skrll if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 3008 1.3.2.2 skrll status = ixgbe_setup_ixfi_x550em(hw, &force_speed); 3009 1.3.2.2 skrll 3010 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 3011 1.3.2.2 skrll return status; 3012 1.3.2.2 skrll } 3013 1.3.2.2 skrll 3014 1.3.2.2 skrll return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); 3015 1.3.2.2 skrll } 3016 1.3.2.2 skrll 3017 1.3.2.2 skrll /** 3018 1.3.2.2 skrll * ixgbe_check_link_t_X550em - Determine link and speed status 3019 1.3.2.2 skrll * @hw: pointer to hardware structure 3020 1.3.2.2 skrll * @speed: pointer to link speed 3021 1.3.2.2 skrll * @link_up: TRUE when link is up 3022 1.3.2.2 skrll * @link_up_wait_to_complete: bool used to wait for link up or not 3023 1.3.2.2 skrll * 3024 1.3.2.2 skrll * Check that both the MAC and X557 external PHY have link. 3025 1.3.2.2 skrll **/ 3026 1.3.2.2 skrll s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3027 1.3.2.2 skrll bool *link_up, bool link_up_wait_to_complete) 3028 1.3.2.2 skrll { 3029 1.3.2.2 skrll u32 status; 3030 1.3.2.2 skrll u16 autoneg_status; 3031 1.3.2.2 skrll 3032 1.3.2.2 skrll if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 3033 1.3.2.2 skrll return IXGBE_ERR_CONFIG; 3034 1.3.2.2 skrll 3035 1.3.2.2 skrll status = ixgbe_check_mac_link_generic(hw, speed, link_up, 3036 1.3.2.2 skrll link_up_wait_to_complete); 3037 1.3.2.2 skrll 3038 1.3.2.2 skrll /* If check link fails or MAC link is not up, then return */ 3039 1.3.2.2 skrll if (status != IXGBE_SUCCESS || !(*link_up)) 3040 1.3.2.2 skrll return status; 3041 1.3.2.2 skrll 3042 1.3.2.2 skrll /* MAC link is up, so check external PHY link. 3043 1.3.2.2 skrll * Read this twice back to back to indicate current status. 3044 1.3.2.2 skrll */ 3045 1.3.2.2 skrll status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 3046 1.3.2.2 skrll IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3047 1.3.2.2 skrll &autoneg_status); 3048 1.3.2.2 skrll 3049 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 3050 1.3.2.2 skrll return status; 3051 1.3.2.2 skrll 3052 1.3.2.2 skrll status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 3053 1.3.2.2 skrll IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3054 1.3.2.2 skrll &autoneg_status); 3055 1.3.2.2 skrll 3056 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 3057 1.3.2.2 skrll return status; 3058 1.3.2.2 skrll 3059 1.3.2.2 skrll /* If external PHY link is not up, then indicate link not up */ 3060 1.3.2.2 skrll if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) 3061 1.3.2.2 skrll *link_up = FALSE; 3062 1.3.2.2 skrll 3063 1.3.2.2 skrll return IXGBE_SUCCESS; 3064 1.3.2.2 skrll } 3065 1.3.2.2 skrll 3066 1.3.2.2 skrll /** 3067 1.3.2.2 skrll * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI 3068 1.3.2.2 skrll * @hw: pointer to hardware structure 3069 1.3.2.2 skrll **/ 3070 1.3.2.2 skrll s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw) 3071 1.3.2.2 skrll { 3072 1.3.2.2 skrll s32 status; 3073 1.3.2.2 skrll 3074 1.3.2.2 skrll status = ixgbe_reset_phy_generic(hw); 3075 1.3.2.2 skrll 3076 1.3.2.2 skrll if (status != IXGBE_SUCCESS) 3077 1.3.2.2 skrll return status; 3078 1.3.2.2 skrll 3079 1.3.2.2 skrll /* Configure Link Status Alarm and Temperature Threshold interrupts */ 3080 1.3.2.2 skrll return ixgbe_enable_lasi_ext_t_x550em(hw); 3081 1.3.2.2 skrll } 3082 1.3.2.2 skrll 3083 1.3.2.2 skrll /** 3084 1.3.2.2 skrll * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs. 3085 1.3.2.2 skrll * @hw: pointer to hardware structure 3086 1.3.2.2 skrll * @led_idx: led number to turn on 3087 1.3.2.2 skrll **/ 3088 1.3.2.2 skrll s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx) 3089 1.3.2.2 skrll { 3090 1.3.2.2 skrll u16 phy_data; 3091 1.3.2.2 skrll 3092 1.3.2.2 skrll DEBUGFUNC("ixgbe_led_on_t_X550em"); 3093 1.3.2.2 skrll 3094 1.3.2.2 skrll if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 3095 1.3.2.2 skrll return IXGBE_ERR_PARAM; 3096 1.3.2.2 skrll 3097 1.3.2.2 skrll /* To turn on the LED, set mode to ON. */ 3098 1.3.2.2 skrll ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 3099 1.3.2.2 skrll IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data); 3100 1.3.2.2 skrll phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK; 3101 1.3.2.2 skrll ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 3102 1.3.2.2 skrll IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data); 3103 1.3.2.2 skrll 3104 1.3.2.2 skrll return IXGBE_SUCCESS; 3105 1.3.2.2 skrll } 3106 1.3.2.2 skrll 3107 1.3.2.2 skrll /** 3108 1.3.2.2 skrll * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs. 3109 1.3.2.2 skrll * @hw: pointer to hardware structure 3110 1.3.2.2 skrll * @led_idx: led number to turn off 3111 1.3.2.2 skrll **/ 3112 1.3.2.2 skrll s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx) 3113 1.3.2.2 skrll { 3114 1.3.2.2 skrll u16 phy_data; 3115 1.3.2.2 skrll 3116 1.3.2.2 skrll DEBUGFUNC("ixgbe_led_off_t_X550em"); 3117 1.3.2.2 skrll 3118 1.3.2.2 skrll if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 3119 1.3.2.2 skrll return IXGBE_ERR_PARAM; 3120 1.3.2.2 skrll 3121 1.3.2.2 skrll /* To turn on the LED, set mode to ON. */ 3122 1.3.2.2 skrll ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 3123 1.3.2.2 skrll IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data); 3124 1.3.2.2 skrll phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK; 3125 1.3.2.2 skrll ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 3126 1.3.2.2 skrll IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data); 3127 1.3.2.2 skrll 3128 1.3.2.2 skrll return IXGBE_SUCCESS; 3129 1.3.2.2 skrll } 3130 1.3.2.2 skrll 3131
Indexes created Mon Oct 20 08:09:54 GMT 2025