ixgbe_x550.c revision 1.4.2.3
1 1.4.2.2 pgoyette /****************************************************************************** 2 1.4.2.2 pgoyette 3 1.4.2.2 pgoyette Copyright (c) 2001-2015, Intel Corporation 4 1.4.2.2 pgoyette All rights reserved. 5 1.4.2.2 pgoyette 6 1.4.2.2 pgoyette Redistribution and use in source and binary forms, with or without 7 1.4.2.2 pgoyette modification, are permitted provided that the following conditions are met: 8 1.4.2.2 pgoyette 9 1.4.2.2 pgoyette 1. Redistributions of source code must retain the above copyright notice, 10 1.4.2.2 pgoyette this list of conditions and the following disclaimer. 11 1.4.2.2 pgoyette 12 1.4.2.2 pgoyette 2. Redistributions in binary form must reproduce the above copyright 13 1.4.2.2 pgoyette notice, this list of conditions and the following disclaimer in the 14 1.4.2.2 pgoyette documentation and/or other materials provided with the distribution. 15 1.4.2.2 pgoyette 16 1.4.2.2 pgoyette 3. Neither the name of the Intel Corporation nor the names of its 17 1.4.2.2 pgoyette contributors may be used to endorse or promote products derived from 18 1.4.2.2 pgoyette this software without specific prior written permission. 19 1.4.2.2 pgoyette 20 1.4.2.2 pgoyette THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 1.4.2.2 pgoyette AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 1.4.2.2 pgoyette IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 1.4.2.2 pgoyette ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 1.4.2.2 pgoyette LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 1.4.2.2 pgoyette CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 1.4.2.2 pgoyette SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 1.4.2.2 pgoyette INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 1.4.2.2 pgoyette CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 1.4.2.2 pgoyette ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 1.4.2.2 pgoyette POSSIBILITY OF SUCH DAMAGE. 31 1.4.2.2 pgoyette 32 1.4.2.2 pgoyette ******************************************************************************/ 33 1.4.2.2 pgoyette /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x550.c 295093 2016-01-31 15:14:23Z smh $*/ 34 1.4.2.2 pgoyette 35 1.4.2.2 pgoyette #include "ixgbe_x550.h" 36 1.4.2.2 pgoyette #include "ixgbe_x540.h" 37 1.4.2.2 pgoyette #include "ixgbe_type.h" 38 1.4.2.2 pgoyette #include "ixgbe_api.h" 39 1.4.2.2 pgoyette #include "ixgbe_common.h" 40 1.4.2.2 pgoyette #include "ixgbe_phy.h" 41 1.4.2.2 pgoyette 42 1.4.2.2 pgoyette static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed); 43 1.4.2.2 pgoyette 44 1.4.2.2 pgoyette /** 45 1.4.2.2 pgoyette * ixgbe_init_ops_X550 - Inits func ptrs and MAC type 46 1.4.2.2 pgoyette * @hw: pointer to hardware structure 47 1.4.2.2 pgoyette * 48 1.4.2.2 pgoyette * Initialize the function pointers and assign the MAC type for X550. 49 1.4.2.2 pgoyette * Does not touch the hardware. 50 1.4.2.2 pgoyette **/ 51 1.4.2.2 pgoyette s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw) 52 1.4.2.2 pgoyette { 53 1.4.2.2 pgoyette struct ixgbe_mac_info *mac = &hw->mac; 54 1.4.2.2 pgoyette struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 55 1.4.2.2 pgoyette s32 ret_val; 56 1.4.2.2 pgoyette 57 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_init_ops_X550"); 58 1.4.2.2 pgoyette 59 1.4.2.2 pgoyette ret_val = ixgbe_init_ops_X540(hw); 60 1.4.2.2 pgoyette mac->ops.dmac_config = ixgbe_dmac_config_X550; 61 1.4.2.2 pgoyette mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550; 62 1.4.2.2 pgoyette mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550; 63 1.4.2.2 pgoyette mac->ops.setup_eee = ixgbe_setup_eee_X550; 64 1.4.2.2 pgoyette mac->ops.set_source_address_pruning = 65 1.4.2.2 pgoyette ixgbe_set_source_address_pruning_X550; 66 1.4.2.2 pgoyette mac->ops.set_ethertype_anti_spoofing = 67 1.4.2.2 pgoyette ixgbe_set_ethertype_anti_spoofing_X550; 68 1.4.2.2 pgoyette 69 1.4.2.2 pgoyette mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; 70 1.4.2.2 pgoyette eeprom->ops.init_params = ixgbe_init_eeprom_params_X550; 71 1.4.2.2 pgoyette eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550; 72 1.4.2.2 pgoyette eeprom->ops.read = ixgbe_read_ee_hostif_X550; 73 1.4.2.2 pgoyette eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550; 74 1.4.2.2 pgoyette eeprom->ops.write = ixgbe_write_ee_hostif_X550; 75 1.4.2.2 pgoyette eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550; 76 1.4.2.2 pgoyette eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550; 77 1.4.2.2 pgoyette eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550; 78 1.4.2.2 pgoyette 79 1.4.2.2 pgoyette mac->ops.disable_mdd = ixgbe_disable_mdd_X550; 80 1.4.2.2 pgoyette mac->ops.enable_mdd = ixgbe_enable_mdd_X550; 81 1.4.2.2 pgoyette mac->ops.mdd_event = ixgbe_mdd_event_X550; 82 1.4.2.2 pgoyette mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550; 83 1.4.2.2 pgoyette mac->ops.disable_rx = ixgbe_disable_rx_x550; 84 1.4.2.2 pgoyette if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) { 85 1.4.2.2 pgoyette hw->mac.ops.led_on = ixgbe_led_on_t_X550em; 86 1.4.2.2 pgoyette hw->mac.ops.led_off = ixgbe_led_off_t_X550em; 87 1.4.2.2 pgoyette } 88 1.4.2.2 pgoyette return ret_val; 89 1.4.2.2 pgoyette } 90 1.4.2.2 pgoyette 91 1.4.2.2 pgoyette /** 92 1.4.2.2 pgoyette * ixgbe_read_cs4227 - Read CS4227 register 93 1.4.2.2 pgoyette * @hw: pointer to hardware structure 94 1.4.2.2 pgoyette * @reg: register number to write 95 1.4.2.2 pgoyette * @value: pointer to receive value read 96 1.4.2.2 pgoyette * 97 1.4.2.2 pgoyette * Returns status code 98 1.4.2.2 pgoyette **/ 99 1.4.2.2 pgoyette static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value) 100 1.4.2.2 pgoyette { 101 1.4.2.2 pgoyette return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value); 102 1.4.2.2 pgoyette } 103 1.4.2.2 pgoyette 104 1.4.2.2 pgoyette /** 105 1.4.2.2 pgoyette * ixgbe_write_cs4227 - Write CS4227 register 106 1.4.2.2 pgoyette * @hw: pointer to hardware structure 107 1.4.2.2 pgoyette * @reg: register number to write 108 1.4.2.2 pgoyette * @value: value to write to register 109 1.4.2.2 pgoyette * 110 1.4.2.2 pgoyette * Returns status code 111 1.4.2.2 pgoyette **/ 112 1.4.2.2 pgoyette static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) 113 1.4.2.2 pgoyette { 114 1.4.2.2 pgoyette return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value); 115 1.4.2.2 pgoyette } 116 1.4.2.2 pgoyette 117 1.4.2.2 pgoyette /** 118 1.4.2.2 pgoyette * ixgbe_read_pe - Read register from port expander 119 1.4.2.2 pgoyette * @hw: pointer to hardware structure 120 1.4.2.2 pgoyette * @reg: register number to read 121 1.4.2.2 pgoyette * @value: pointer to receive read value 122 1.4.2.2 pgoyette * 123 1.4.2.2 pgoyette * Returns status code 124 1.4.2.2 pgoyette **/ 125 1.4.2.2 pgoyette static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) 126 1.4.2.2 pgoyette { 127 1.4.2.2 pgoyette s32 status; 128 1.4.2.2 pgoyette 129 1.4.2.2 pgoyette status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value); 130 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 131 1.4.2.2 pgoyette ERROR_REPORT2(IXGBE_ERROR_CAUTION, 132 1.4.2.2 pgoyette "port expander access failed with %d\n", status); 133 1.4.2.2 pgoyette return status; 134 1.4.2.2 pgoyette } 135 1.4.2.2 pgoyette 136 1.4.2.2 pgoyette /** 137 1.4.2.2 pgoyette * ixgbe_write_pe - Write register to port expander 138 1.4.2.2 pgoyette * @hw: pointer to hardware structure 139 1.4.2.2 pgoyette * @reg: register number to write 140 1.4.2.2 pgoyette * @value: value to write 141 1.4.2.2 pgoyette * 142 1.4.2.2 pgoyette * Returns status code 143 1.4.2.2 pgoyette **/ 144 1.4.2.2 pgoyette static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value) 145 1.4.2.2 pgoyette { 146 1.4.2.2 pgoyette s32 status; 147 1.4.2.2 pgoyette 148 1.4.2.2 pgoyette status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value); 149 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 150 1.4.2.2 pgoyette ERROR_REPORT2(IXGBE_ERROR_CAUTION, 151 1.4.2.2 pgoyette "port expander access failed with %d\n", status); 152 1.4.2.2 pgoyette return status; 153 1.4.2.2 pgoyette } 154 1.4.2.2 pgoyette 155 1.4.2.2 pgoyette /** 156 1.4.2.2 pgoyette * ixgbe_reset_cs4227 - Reset CS4227 using port expander 157 1.4.2.2 pgoyette * @hw: pointer to hardware structure 158 1.4.2.2 pgoyette * 159 1.4.2.2 pgoyette * This function assumes that the caller has acquired the proper semaphore. 160 1.4.2.2 pgoyette * Returns error code 161 1.4.2.2 pgoyette **/ 162 1.4.2.2 pgoyette static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw) 163 1.4.2.2 pgoyette { 164 1.4.2.2 pgoyette s32 status; 165 1.4.2.2 pgoyette u32 retry; 166 1.4.2.2 pgoyette u16 value; 167 1.4.2.2 pgoyette u8 reg; 168 1.4.2.2 pgoyette 169 1.4.2.2 pgoyette /* Trigger hard reset. */ 170 1.4.2.2 pgoyette status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 171 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 172 1.4.2.2 pgoyette return status; 173 1.4.2.2 pgoyette reg |= IXGBE_PE_BIT1; 174 1.4.2.2 pgoyette status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 175 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 176 1.4.2.2 pgoyette return status; 177 1.4.2.2 pgoyette 178 1.4.2.2 pgoyette status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®); 179 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 180 1.4.2.2 pgoyette return status; 181 1.4.2.2 pgoyette reg &= ~IXGBE_PE_BIT1; 182 1.4.2.2 pgoyette status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg); 183 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 184 1.4.2.2 pgoyette return status; 185 1.4.2.2 pgoyette 186 1.4.2.2 pgoyette status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 187 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 188 1.4.2.2 pgoyette return status; 189 1.4.2.2 pgoyette reg &= ~IXGBE_PE_BIT1; 190 1.4.2.2 pgoyette status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 191 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 192 1.4.2.2 pgoyette return status; 193 1.4.2.2 pgoyette 194 1.4.2.2 pgoyette usec_delay(IXGBE_CS4227_RESET_HOLD); 195 1.4.2.2 pgoyette 196 1.4.2.2 pgoyette status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 197 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 198 1.4.2.2 pgoyette return status; 199 1.4.2.2 pgoyette reg |= IXGBE_PE_BIT1; 200 1.4.2.2 pgoyette status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 201 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 202 1.4.2.2 pgoyette return status; 203 1.4.2.2 pgoyette 204 1.4.2.2 pgoyette /* Wait for the reset to complete. */ 205 1.4.2.2 pgoyette msec_delay(IXGBE_CS4227_RESET_DELAY); 206 1.4.2.2 pgoyette for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 207 1.4.2.2 pgoyette status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS, 208 1.4.2.2 pgoyette &value); 209 1.4.2.2 pgoyette if (status == IXGBE_SUCCESS && 210 1.4.2.2 pgoyette value == IXGBE_CS4227_EEPROM_LOAD_OK) 211 1.4.2.2 pgoyette break; 212 1.4.2.2 pgoyette msec_delay(IXGBE_CS4227_CHECK_DELAY); 213 1.4.2.2 pgoyette } 214 1.4.2.2 pgoyette if (retry == IXGBE_CS4227_RETRIES) { 215 1.4.2.2 pgoyette ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 216 1.4.2.2 pgoyette "CS4227 reset did not complete."); 217 1.4.2.2 pgoyette return IXGBE_ERR_PHY; 218 1.4.2.2 pgoyette } 219 1.4.2.2 pgoyette 220 1.4.2.2 pgoyette status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value); 221 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS || 222 1.4.2.2 pgoyette !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) { 223 1.4.2.2 pgoyette ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 224 1.4.2.2 pgoyette "CS4227 EEPROM did not load successfully."); 225 1.4.2.2 pgoyette return IXGBE_ERR_PHY; 226 1.4.2.2 pgoyette } 227 1.4.2.2 pgoyette 228 1.4.2.2 pgoyette return IXGBE_SUCCESS; 229 1.4.2.2 pgoyette } 230 1.4.2.2 pgoyette 231 1.4.2.2 pgoyette /** 232 1.4.2.2 pgoyette * ixgbe_check_cs4227 - Check CS4227 and reset as needed 233 1.4.2.2 pgoyette * @hw: pointer to hardware structure 234 1.4.2.2 pgoyette **/ 235 1.4.2.2 pgoyette static void ixgbe_check_cs4227(struct ixgbe_hw *hw) 236 1.4.2.2 pgoyette { 237 1.4.2.2 pgoyette s32 status = IXGBE_SUCCESS; 238 1.4.2.2 pgoyette u32 swfw_mask = hw->phy.phy_semaphore_mask; 239 1.4.2.2 pgoyette u16 value = 0; 240 1.4.2.2 pgoyette u8 retry; 241 1.4.2.2 pgoyette 242 1.4.2.2 pgoyette for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 243 1.4.2.2 pgoyette status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 244 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) { 245 1.4.2.2 pgoyette ERROR_REPORT2(IXGBE_ERROR_CAUTION, 246 1.4.2.2 pgoyette "semaphore failed with %d", status); 247 1.4.2.2 pgoyette msec_delay(IXGBE_CS4227_CHECK_DELAY); 248 1.4.2.2 pgoyette continue; 249 1.4.2.2 pgoyette } 250 1.4.2.2 pgoyette 251 1.4.2.2 pgoyette /* Get status of reset flow. */ 252 1.4.2.2 pgoyette status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); 253 1.4.2.2 pgoyette 254 1.4.2.2 pgoyette if (status == IXGBE_SUCCESS && 255 1.4.2.2 pgoyette value == IXGBE_CS4227_RESET_COMPLETE) 256 1.4.2.2 pgoyette goto out; 257 1.4.2.2 pgoyette 258 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS || 259 1.4.2.2 pgoyette value != IXGBE_CS4227_RESET_PENDING) 260 1.4.2.2 pgoyette break; 261 1.4.2.2 pgoyette 262 1.4.2.2 pgoyette /* Reset is pending. Wait and check again. */ 263 1.4.2.2 pgoyette hw->mac.ops.release_swfw_sync(hw, swfw_mask); 264 1.4.2.2 pgoyette msec_delay(IXGBE_CS4227_CHECK_DELAY); 265 1.4.2.2 pgoyette } 266 1.4.2.2 pgoyette 267 1.4.2.2 pgoyette /* If still pending, assume other instance failed. */ 268 1.4.2.2 pgoyette if (retry == IXGBE_CS4227_RETRIES) { 269 1.4.2.2 pgoyette status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 270 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) { 271 1.4.2.2 pgoyette ERROR_REPORT2(IXGBE_ERROR_CAUTION, 272 1.4.2.2 pgoyette "semaphore failed with %d", status); 273 1.4.2.2 pgoyette return; 274 1.4.2.2 pgoyette } 275 1.4.2.2 pgoyette } 276 1.4.2.2 pgoyette 277 1.4.2.2 pgoyette /* Reset the CS4227. */ 278 1.4.2.2 pgoyette status = ixgbe_reset_cs4227(hw); 279 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) { 280 1.4.2.2 pgoyette ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 281 1.4.2.2 pgoyette "CS4227 reset failed: %d", status); 282 1.4.2.2 pgoyette goto out; 283 1.4.2.2 pgoyette } 284 1.4.2.2 pgoyette 285 1.4.2.2 pgoyette /* Reset takes so long, temporarily release semaphore in case the 286 1.4.2.2 pgoyette * other driver instance is waiting for the reset indication. 287 1.4.2.2 pgoyette */ 288 1.4.2.2 pgoyette ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 289 1.4.2.2 pgoyette IXGBE_CS4227_RESET_PENDING); 290 1.4.2.2 pgoyette hw->mac.ops.release_swfw_sync(hw, swfw_mask); 291 1.4.2.2 pgoyette msec_delay(10); 292 1.4.2.2 pgoyette status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 293 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) { 294 1.4.2.2 pgoyette ERROR_REPORT2(IXGBE_ERROR_CAUTION, 295 1.4.2.2 pgoyette "semaphore failed with %d", status); 296 1.4.2.2 pgoyette return; 297 1.4.2.2 pgoyette } 298 1.4.2.2 pgoyette 299 1.4.2.2 pgoyette /* Record completion for next time. */ 300 1.4.2.2 pgoyette status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 301 1.4.2.2 pgoyette IXGBE_CS4227_RESET_COMPLETE); 302 1.4.2.2 pgoyette 303 1.4.2.2 pgoyette out: 304 1.4.2.2 pgoyette hw->mac.ops.release_swfw_sync(hw, swfw_mask); 305 1.4.2.2 pgoyette msec_delay(hw->eeprom.semaphore_delay); 306 1.4.2.2 pgoyette } 307 1.4.2.2 pgoyette 308 1.4.2.2 pgoyette /** 309 1.4.2.2 pgoyette * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control 310 1.4.2.2 pgoyette * @hw: pointer to hardware structure 311 1.4.2.2 pgoyette **/ 312 1.4.2.2 pgoyette static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) 313 1.4.2.2 pgoyette { 314 1.4.2.2 pgoyette u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 315 1.4.2.2 pgoyette 316 1.4.2.2 pgoyette if (hw->bus.lan_id) { 317 1.4.2.2 pgoyette esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); 318 1.4.2.2 pgoyette esdp |= IXGBE_ESDP_SDP1_DIR; 319 1.4.2.2 pgoyette } 320 1.4.2.2 pgoyette esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); 321 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 322 1.4.2.2 pgoyette IXGBE_WRITE_FLUSH(hw); 323 1.4.2.2 pgoyette } 324 1.4.2.2 pgoyette 325 1.4.2.2 pgoyette /** 326 1.4.2.2 pgoyette * ixgbe_identify_phy_x550em - Get PHY type based on device id 327 1.4.2.2 pgoyette * @hw: pointer to hardware structure 328 1.4.2.2 pgoyette * 329 1.4.2.2 pgoyette * Returns error code 330 1.4.2.2 pgoyette */ 331 1.4.2.2 pgoyette static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) 332 1.4.2.2 pgoyette { 333 1.4.2.2 pgoyette switch (hw->device_id) { 334 1.4.2.2 pgoyette case IXGBE_DEV_ID_X550EM_X_SFP: 335 1.4.2.2 pgoyette /* set up for CS4227 usage */ 336 1.4.2.2 pgoyette hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 337 1.4.2.2 pgoyette ixgbe_setup_mux_ctl(hw); 338 1.4.2.2 pgoyette ixgbe_check_cs4227(hw); 339 1.4.2.2 pgoyette 340 1.4.2.2 pgoyette return ixgbe_identify_module_generic(hw); 341 1.4.2.2 pgoyette break; 342 1.4.2.2 pgoyette case IXGBE_DEV_ID_X550EM_X_KX4: 343 1.4.2.2 pgoyette hw->phy.type = ixgbe_phy_x550em_kx4; 344 1.4.2.2 pgoyette break; 345 1.4.2.2 pgoyette case IXGBE_DEV_ID_X550EM_X_KR: 346 1.4.2.2 pgoyette hw->phy.type = ixgbe_phy_x550em_kr; 347 1.4.2.2 pgoyette break; 348 1.4.2.2 pgoyette case IXGBE_DEV_ID_X550EM_X_1G_T: 349 1.4.2.2 pgoyette case IXGBE_DEV_ID_X550EM_X_10G_T: 350 1.4.2.2 pgoyette return ixgbe_identify_phy_generic(hw); 351 1.4.2.2 pgoyette default: 352 1.4.2.2 pgoyette break; 353 1.4.2.2 pgoyette } 354 1.4.2.2 pgoyette return IXGBE_SUCCESS; 355 1.4.2.2 pgoyette } 356 1.4.2.2 pgoyette 357 1.4.2.2 pgoyette static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 358 1.4.2.2 pgoyette u32 device_type, u16 *phy_data) 359 1.4.2.2 pgoyette { 360 1.4.2.2 pgoyette UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data); 361 1.4.2.2 pgoyette return IXGBE_NOT_IMPLEMENTED; 362 1.4.2.2 pgoyette } 363 1.4.2.2 pgoyette 364 1.4.2.2 pgoyette static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 365 1.4.2.2 pgoyette u32 device_type, u16 phy_data) 366 1.4.2.2 pgoyette { 367 1.4.2.2 pgoyette UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data); 368 1.4.2.2 pgoyette return IXGBE_NOT_IMPLEMENTED; 369 1.4.2.2 pgoyette } 370 1.4.2.2 pgoyette 371 1.4.2.2 pgoyette /** 372 1.4.2.2 pgoyette * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type 373 1.4.2.2 pgoyette * @hw: pointer to hardware structure 374 1.4.2.2 pgoyette * 375 1.4.2.2 pgoyette * Initialize the function pointers and for MAC type X550EM. 376 1.4.2.2 pgoyette * Does not touch the hardware. 377 1.4.2.2 pgoyette **/ 378 1.4.2.2 pgoyette s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw) 379 1.4.2.2 pgoyette { 380 1.4.2.2 pgoyette struct ixgbe_mac_info *mac = &hw->mac; 381 1.4.2.2 pgoyette struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 382 1.4.2.2 pgoyette struct ixgbe_phy_info *phy = &hw->phy; 383 1.4.2.2 pgoyette s32 ret_val; 384 1.4.2.2 pgoyette 385 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_init_ops_X550EM"); 386 1.4.2.2 pgoyette 387 1.4.2.2 pgoyette /* Similar to X550 so start there. */ 388 1.4.2.2 pgoyette ret_val = ixgbe_init_ops_X550(hw); 389 1.4.2.2 pgoyette 390 1.4.2.2 pgoyette /* Since this function eventually calls 391 1.4.2.2 pgoyette * ixgbe_init_ops_540 by design, we are setting 392 1.4.2.2 pgoyette * the pointers to NULL explicitly here to overwrite 393 1.4.2.2 pgoyette * the values being set in the x540 function. 394 1.4.2.2 pgoyette */ 395 1.4.2.2 pgoyette 396 1.4.2.2 pgoyette /* FCOE not supported in x550EM */ 397 1.4.2.2 pgoyette mac->ops.get_san_mac_addr = NULL; 398 1.4.2.2 pgoyette mac->ops.set_san_mac_addr = NULL; 399 1.4.2.2 pgoyette mac->ops.get_wwn_prefix = NULL; 400 1.4.2.2 pgoyette mac->ops.get_fcoe_boot_status = NULL; 401 1.4.2.2 pgoyette 402 1.4.2.2 pgoyette /* IPsec not supported in x550EM */ 403 1.4.2.2 pgoyette mac->ops.disable_sec_rx_path = NULL; 404 1.4.2.2 pgoyette mac->ops.enable_sec_rx_path = NULL; 405 1.4.2.2 pgoyette 406 1.4.2.2 pgoyette /* AUTOC register is not present in x550EM. */ 407 1.4.2.2 pgoyette mac->ops.prot_autoc_read = NULL; 408 1.4.2.2 pgoyette mac->ops.prot_autoc_write = NULL; 409 1.4.2.2 pgoyette 410 1.4.2.2 pgoyette /* X550EM bus type is internal*/ 411 1.4.2.2 pgoyette hw->bus.type = ixgbe_bus_type_internal; 412 1.4.2.2 pgoyette mac->ops.get_bus_info = ixgbe_get_bus_info_X550em; 413 1.4.2.2 pgoyette 414 1.4.2.2 pgoyette if (hw->mac.type == ixgbe_mac_X550EM_x) { 415 1.4.2.2 pgoyette mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550; 416 1.4.2.2 pgoyette mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550; 417 1.4.2.2 pgoyette } 418 1.4.2.2 pgoyette 419 1.4.2.2 pgoyette mac->ops.get_media_type = ixgbe_get_media_type_X550em; 420 1.4.2.2 pgoyette mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em; 421 1.4.2.2 pgoyette mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em; 422 1.4.2.2 pgoyette mac->ops.reset_hw = ixgbe_reset_hw_X550em; 423 1.4.2.2 pgoyette mac->ops.get_supported_physical_layer = 424 1.4.2.2 pgoyette ixgbe_get_supported_physical_layer_X550em; 425 1.4.2.2 pgoyette 426 1.4.2.2 pgoyette if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) 427 1.4.2.2 pgoyette mac->ops.setup_fc = ixgbe_setup_fc_generic; 428 1.4.2.2 pgoyette else 429 1.4.2.2 pgoyette mac->ops.setup_fc = ixgbe_setup_fc_X550em; 430 1.4.2.2 pgoyette 431 1.4.2.2 pgoyette mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em; 432 1.4.2.2 pgoyette mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em; 433 1.4.2.2 pgoyette 434 1.4.2.2 pgoyette if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR) 435 1.4.2.2 pgoyette mac->ops.setup_eee = NULL; 436 1.4.2.2 pgoyette 437 1.4.2.2 pgoyette /* PHY */ 438 1.4.2.2 pgoyette phy->ops.init = ixgbe_init_phy_ops_X550em; 439 1.4.2.2 pgoyette phy->ops.identify = ixgbe_identify_phy_x550em; 440 1.4.2.2 pgoyette if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 441 1.4.2.2 pgoyette phy->ops.set_phy_power = NULL; 442 1.4.2.2 pgoyette 443 1.4.2.2 pgoyette 444 1.4.2.2 pgoyette /* EEPROM */ 445 1.4.2.2 pgoyette eeprom->ops.init_params = ixgbe_init_eeprom_params_X540; 446 1.4.2.2 pgoyette eeprom->ops.read = ixgbe_read_ee_hostif_X550; 447 1.4.2.2 pgoyette eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550; 448 1.4.2.2 pgoyette eeprom->ops.write = ixgbe_write_ee_hostif_X550; 449 1.4.2.2 pgoyette eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550; 450 1.4.2.2 pgoyette eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550; 451 1.4.2.2 pgoyette eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550; 452 1.4.2.2 pgoyette eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550; 453 1.4.2.2 pgoyette 454 1.4.2.2 pgoyette return ret_val; 455 1.4.2.2 pgoyette } 456 1.4.2.2 pgoyette 457 1.4.2.2 pgoyette /** 458 1.4.2.2 pgoyette * ixgbe_dmac_config_X550 459 1.4.2.2 pgoyette * @hw: pointer to hardware structure 460 1.4.2.2 pgoyette * 461 1.4.2.2 pgoyette * Configure DMA coalescing. If enabling dmac, dmac is activated. 462 1.4.2.2 pgoyette * When disabling dmac, dmac enable dmac bit is cleared. 463 1.4.2.2 pgoyette **/ 464 1.4.2.2 pgoyette s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw) 465 1.4.2.2 pgoyette { 466 1.4.2.2 pgoyette u32 reg, high_pri_tc; 467 1.4.2.2 pgoyette 468 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_dmac_config_X550"); 469 1.4.2.2 pgoyette 470 1.4.2.2 pgoyette /* Disable DMA coalescing before configuring */ 471 1.4.2.2 pgoyette reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 472 1.4.2.2 pgoyette reg &= ~IXGBE_DMACR_DMAC_EN; 473 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 474 1.4.2.2 pgoyette 475 1.4.2.2 pgoyette /* Disable DMA Coalescing if the watchdog timer is 0 */ 476 1.4.2.2 pgoyette if (!hw->mac.dmac_config.watchdog_timer) 477 1.4.2.2 pgoyette goto out; 478 1.4.2.2 pgoyette 479 1.4.2.2 pgoyette ixgbe_dmac_config_tcs_X550(hw); 480 1.4.2.2 pgoyette 481 1.4.2.2 pgoyette /* Configure DMA Coalescing Control Register */ 482 1.4.2.2 pgoyette reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 483 1.4.2.2 pgoyette 484 1.4.2.2 pgoyette /* Set the watchdog timer in units of 40.96 usec */ 485 1.4.2.2 pgoyette reg &= ~IXGBE_DMACR_DMACWT_MASK; 486 1.4.2.2 pgoyette reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096; 487 1.4.2.2 pgoyette 488 1.4.2.2 pgoyette reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK; 489 1.4.2.2 pgoyette /* If fcoe is enabled, set high priority traffic class */ 490 1.4.2.2 pgoyette if (hw->mac.dmac_config.fcoe_en) { 491 1.4.2.2 pgoyette high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc; 492 1.4.2.2 pgoyette reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) & 493 1.4.2.2 pgoyette IXGBE_DMACR_HIGH_PRI_TC_MASK); 494 1.4.2.2 pgoyette } 495 1.4.2.2 pgoyette reg |= IXGBE_DMACR_EN_MNG_IND; 496 1.4.2.2 pgoyette 497 1.4.2.2 pgoyette /* Enable DMA coalescing after configuration */ 498 1.4.2.2 pgoyette reg |= IXGBE_DMACR_DMAC_EN; 499 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 500 1.4.2.2 pgoyette 501 1.4.2.2 pgoyette out: 502 1.4.2.2 pgoyette return IXGBE_SUCCESS; 503 1.4.2.2 pgoyette } 504 1.4.2.2 pgoyette 505 1.4.2.2 pgoyette /** 506 1.4.2.2 pgoyette * ixgbe_dmac_config_tcs_X550 507 1.4.2.2 pgoyette * @hw: pointer to hardware structure 508 1.4.2.2 pgoyette * 509 1.4.2.2 pgoyette * Configure DMA coalescing threshold per TC. The dmac enable bit must 510 1.4.2.2 pgoyette * be cleared before configuring. 511 1.4.2.2 pgoyette **/ 512 1.4.2.2 pgoyette s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw) 513 1.4.2.2 pgoyette { 514 1.4.2.2 pgoyette u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb; 515 1.4.2.2 pgoyette 516 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_dmac_config_tcs_X550"); 517 1.4.2.2 pgoyette 518 1.4.2.2 pgoyette /* Configure DMA coalescing enabled */ 519 1.4.2.2 pgoyette switch (hw->mac.dmac_config.link_speed) { 520 1.4.2.2 pgoyette case IXGBE_LINK_SPEED_100_FULL: 521 1.4.2.2 pgoyette pb_headroom = IXGBE_DMACRXT_100M; 522 1.4.2.2 pgoyette break; 523 1.4.2.2 pgoyette case IXGBE_LINK_SPEED_1GB_FULL: 524 1.4.2.2 pgoyette pb_headroom = IXGBE_DMACRXT_1G; 525 1.4.2.2 pgoyette break; 526 1.4.2.2 pgoyette default: 527 1.4.2.2 pgoyette pb_headroom = IXGBE_DMACRXT_10G; 528 1.4.2.2 pgoyette break; 529 1.4.2.2 pgoyette } 530 1.4.2.2 pgoyette 531 1.4.2.2 pgoyette maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >> 532 1.4.2.2 pgoyette IXGBE_MHADD_MFS_SHIFT) / 1024); 533 1.4.2.2 pgoyette 534 1.4.2.2 pgoyette /* Set the per Rx packet buffer receive threshold */ 535 1.4.2.2 pgoyette for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) { 536 1.4.2.2 pgoyette reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc)); 537 1.4.2.2 pgoyette reg &= ~IXGBE_DMCTH_DMACRXT_MASK; 538 1.4.2.2 pgoyette 539 1.4.2.2 pgoyette if (tc < hw->mac.dmac_config.num_tcs) { 540 1.4.2.2 pgoyette /* Get Rx PB size */ 541 1.4.2.2 pgoyette rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc)); 542 1.4.2.2 pgoyette rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >> 543 1.4.2.2 pgoyette IXGBE_RXPBSIZE_SHIFT; 544 1.4.2.2 pgoyette 545 1.4.2.2 pgoyette /* Calculate receive buffer threshold in kilobytes */ 546 1.4.2.2 pgoyette if (rx_pb_size > pb_headroom) 547 1.4.2.2 pgoyette rx_pb_size = rx_pb_size - pb_headroom; 548 1.4.2.2 pgoyette else 549 1.4.2.2 pgoyette rx_pb_size = 0; 550 1.4.2.2 pgoyette 551 1.4.2.2 pgoyette /* Minimum of MFS shall be set for DMCTH */ 552 1.4.2.2 pgoyette reg |= (rx_pb_size > maxframe_size_kb) ? 553 1.4.2.2 pgoyette rx_pb_size : maxframe_size_kb; 554 1.4.2.2 pgoyette } 555 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg); 556 1.4.2.2 pgoyette } 557 1.4.2.2 pgoyette return IXGBE_SUCCESS; 558 1.4.2.2 pgoyette } 559 1.4.2.2 pgoyette 560 1.4.2.2 pgoyette /** 561 1.4.2.2 pgoyette * ixgbe_dmac_update_tcs_X550 562 1.4.2.2 pgoyette * @hw: pointer to hardware structure 563 1.4.2.2 pgoyette * 564 1.4.2.2 pgoyette * Disables dmac, updates per TC settings, and then enables dmac. 565 1.4.2.2 pgoyette **/ 566 1.4.2.2 pgoyette s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw) 567 1.4.2.2 pgoyette { 568 1.4.2.2 pgoyette u32 reg; 569 1.4.2.2 pgoyette 570 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_dmac_update_tcs_X550"); 571 1.4.2.2 pgoyette 572 1.4.2.2 pgoyette /* Disable DMA coalescing before configuring */ 573 1.4.2.2 pgoyette reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 574 1.4.2.2 pgoyette reg &= ~IXGBE_DMACR_DMAC_EN; 575 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 576 1.4.2.2 pgoyette 577 1.4.2.2 pgoyette ixgbe_dmac_config_tcs_X550(hw); 578 1.4.2.2 pgoyette 579 1.4.2.2 pgoyette /* Enable DMA coalescing after configuration */ 580 1.4.2.2 pgoyette reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 581 1.4.2.2 pgoyette reg |= IXGBE_DMACR_DMAC_EN; 582 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 583 1.4.2.2 pgoyette 584 1.4.2.2 pgoyette return IXGBE_SUCCESS; 585 1.4.2.2 pgoyette } 586 1.4.2.2 pgoyette 587 1.4.2.2 pgoyette /** 588 1.4.2.2 pgoyette * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params 589 1.4.2.2 pgoyette * @hw: pointer to hardware structure 590 1.4.2.2 pgoyette * 591 1.4.2.2 pgoyette * Initializes the EEPROM parameters ixgbe_eeprom_info within the 592 1.4.2.2 pgoyette * ixgbe_hw struct in order to set up EEPROM access. 593 1.4.2.2 pgoyette **/ 594 1.4.2.2 pgoyette s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) 595 1.4.2.2 pgoyette { 596 1.4.2.2 pgoyette struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 597 1.4.2.2 pgoyette u32 eec; 598 1.4.2.2 pgoyette u16 eeprom_size; 599 1.4.2.2 pgoyette 600 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_init_eeprom_params_X550"); 601 1.4.2.2 pgoyette 602 1.4.2.2 pgoyette if (eeprom->type == ixgbe_eeprom_uninitialized) { 603 1.4.2.2 pgoyette eeprom->semaphore_delay = 10; 604 1.4.2.2 pgoyette eeprom->type = ixgbe_flash; 605 1.4.2.2 pgoyette 606 1.4.2.2 pgoyette eec = IXGBE_READ_REG(hw, IXGBE_EEC); 607 1.4.2.2 pgoyette eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 608 1.4.2.2 pgoyette IXGBE_EEC_SIZE_SHIFT); 609 1.4.2.2 pgoyette eeprom->word_size = 1 << (eeprom_size + 610 1.4.2.2 pgoyette IXGBE_EEPROM_WORD_SIZE_SHIFT); 611 1.4.2.2 pgoyette 612 1.4.2.2 pgoyette DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 613 1.4.2.2 pgoyette eeprom->type, eeprom->word_size); 614 1.4.2.2 pgoyette } 615 1.4.2.2 pgoyette 616 1.4.2.2 pgoyette return IXGBE_SUCCESS; 617 1.4.2.2 pgoyette } 618 1.4.2.2 pgoyette 619 1.4.2.2 pgoyette /** 620 1.4.2.2 pgoyette * ixgbe_setup_eee_X550 - Enable/disable EEE support 621 1.4.2.2 pgoyette * @hw: pointer to the HW structure 622 1.4.2.2 pgoyette * @enable_eee: boolean flag to enable EEE 623 1.4.2.2 pgoyette * 624 1.4.2.2 pgoyette * Enable/disable EEE based on enable_eee flag. 625 1.4.2.2 pgoyette * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 626 1.4.2.2 pgoyette * are modified. 627 1.4.2.2 pgoyette * 628 1.4.2.2 pgoyette **/ 629 1.4.2.2 pgoyette s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee) 630 1.4.2.2 pgoyette { 631 1.4.2.2 pgoyette u32 eeer; 632 1.4.2.2 pgoyette u16 autoneg_eee_reg; 633 1.4.2.2 pgoyette u32 link_reg; 634 1.4.2.2 pgoyette s32 status; 635 1.4.2.2 pgoyette u32 fuse; 636 1.4.2.2 pgoyette 637 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_setup_eee_X550"); 638 1.4.2.2 pgoyette 639 1.4.2.2 pgoyette eeer = IXGBE_READ_REG(hw, IXGBE_EEER); 640 1.4.2.2 pgoyette /* Enable or disable EEE per flag */ 641 1.4.2.2 pgoyette if (enable_eee) { 642 1.4.2.2 pgoyette eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN); 643 1.4.2.2 pgoyette 644 1.4.2.2 pgoyette if (hw->mac.type == ixgbe_mac_X550) { 645 1.4.2.2 pgoyette /* Advertise EEE capability */ 646 1.4.2.2 pgoyette hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, 647 1.4.2.2 pgoyette IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg); 648 1.4.2.2 pgoyette 649 1.4.2.2 pgoyette autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT | 650 1.4.2.2 pgoyette IXGBE_AUTO_NEG_1000BASE_EEE_ADVT | 651 1.4.2.2 pgoyette IXGBE_AUTO_NEG_100BASE_EEE_ADVT); 652 1.4.2.2 pgoyette 653 1.4.2.2 pgoyette hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, 654 1.4.2.2 pgoyette IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg); 655 1.4.2.2 pgoyette } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) { 656 1.4.2.2 pgoyette /* Not supported on first revision. */ 657 1.4.2.2 pgoyette fuse = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)); 658 1.4.2.2 pgoyette if (!(fuse & IXGBE_FUSES0_REV1)) 659 1.4.2.2 pgoyette return IXGBE_SUCCESS; 660 1.4.2.2 pgoyette 661 1.4.2.2 pgoyette status = ixgbe_read_iosf_sb_reg_x550(hw, 662 1.4.2.2 pgoyette IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 663 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg); 664 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 665 1.4.2.2 pgoyette return status; 666 1.4.2.2 pgoyette 667 1.4.2.2 pgoyette link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR | 668 1.4.2.2 pgoyette IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX; 669 1.4.2.2 pgoyette 670 1.4.2.2 pgoyette /* Don't advertise FEC capability when EEE enabled. */ 671 1.4.2.2 pgoyette link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC; 672 1.4.2.2 pgoyette 673 1.4.2.2 pgoyette status = ixgbe_write_iosf_sb_reg_x550(hw, 674 1.4.2.2 pgoyette IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 675 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg); 676 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 677 1.4.2.2 pgoyette return status; 678 1.4.2.2 pgoyette } 679 1.4.2.2 pgoyette } else { 680 1.4.2.2 pgoyette eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN); 681 1.4.2.2 pgoyette 682 1.4.2.2 pgoyette if (hw->mac.type == ixgbe_mac_X550) { 683 1.4.2.2 pgoyette /* Disable advertised EEE capability */ 684 1.4.2.2 pgoyette hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, 685 1.4.2.2 pgoyette IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg); 686 1.4.2.2 pgoyette 687 1.4.2.2 pgoyette autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT | 688 1.4.2.2 pgoyette IXGBE_AUTO_NEG_1000BASE_EEE_ADVT | 689 1.4.2.2 pgoyette IXGBE_AUTO_NEG_100BASE_EEE_ADVT); 690 1.4.2.2 pgoyette 691 1.4.2.2 pgoyette hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, 692 1.4.2.2 pgoyette IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg); 693 1.4.2.2 pgoyette } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) { 694 1.4.2.2 pgoyette status = ixgbe_read_iosf_sb_reg_x550(hw, 695 1.4.2.2 pgoyette IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 696 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg); 697 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 698 1.4.2.2 pgoyette return status; 699 1.4.2.2 pgoyette 700 1.4.2.2 pgoyette link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR | 701 1.4.2.2 pgoyette IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX); 702 1.4.2.2 pgoyette 703 1.4.2.2 pgoyette /* Advertise FEC capability when EEE is disabled. */ 704 1.4.2.2 pgoyette link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC; 705 1.4.2.2 pgoyette 706 1.4.2.2 pgoyette status = ixgbe_write_iosf_sb_reg_x550(hw, 707 1.4.2.2 pgoyette IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 708 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg); 709 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 710 1.4.2.2 pgoyette return status; 711 1.4.2.2 pgoyette } 712 1.4.2.2 pgoyette } 713 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer); 714 1.4.2.2 pgoyette 715 1.4.2.2 pgoyette return IXGBE_SUCCESS; 716 1.4.2.2 pgoyette } 717 1.4.2.2 pgoyette 718 1.4.2.2 pgoyette /** 719 1.4.2.2 pgoyette * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning 720 1.4.2.2 pgoyette * @hw: pointer to hardware structure 721 1.4.2.2 pgoyette * @enable: enable or disable source address pruning 722 1.4.2.2 pgoyette * @pool: Rx pool to set source address pruning for 723 1.4.2.2 pgoyette **/ 724 1.4.2.2 pgoyette void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable, 725 1.4.2.2 pgoyette unsigned int pool) 726 1.4.2.2 pgoyette { 727 1.4.2.2 pgoyette u64 pfflp; 728 1.4.2.2 pgoyette 729 1.4.2.2 pgoyette /* max rx pool is 63 */ 730 1.4.2.2 pgoyette if (pool > 63) 731 1.4.2.2 pgoyette return; 732 1.4.2.2 pgoyette 733 1.4.2.2 pgoyette pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL); 734 1.4.2.2 pgoyette pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32; 735 1.4.2.2 pgoyette 736 1.4.2.2 pgoyette if (enable) 737 1.4.2.2 pgoyette pfflp |= (1ULL << pool); 738 1.4.2.2 pgoyette else 739 1.4.2.2 pgoyette pfflp &= ~(1ULL << pool); 740 1.4.2.2 pgoyette 741 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); 742 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); 743 1.4.2.2 pgoyette } 744 1.4.2.2 pgoyette 745 1.4.2.2 pgoyette /** 746 1.4.2.2 pgoyette * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing 747 1.4.2.2 pgoyette * @hw: pointer to hardware structure 748 1.4.2.2 pgoyette * @enable: enable or disable switch for Ethertype anti-spoofing 749 1.4.2.2 pgoyette * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 750 1.4.2.2 pgoyette * 751 1.4.2.2 pgoyette **/ 752 1.4.2.2 pgoyette void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, 753 1.4.2.2 pgoyette bool enable, int vf) 754 1.4.2.2 pgoyette { 755 1.4.2.2 pgoyette int vf_target_reg = vf >> 3; 756 1.4.2.2 pgoyette int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT; 757 1.4.2.2 pgoyette u32 pfvfspoof; 758 1.4.2.2 pgoyette 759 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550"); 760 1.4.2.2 pgoyette 761 1.4.2.2 pgoyette pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 762 1.4.2.2 pgoyette if (enable) 763 1.4.2.2 pgoyette pfvfspoof |= (1 << vf_target_shift); 764 1.4.2.2 pgoyette else 765 1.4.2.2 pgoyette pfvfspoof &= ~(1 << vf_target_shift); 766 1.4.2.2 pgoyette 767 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 768 1.4.2.2 pgoyette } 769 1.4.2.2 pgoyette 770 1.4.2.2 pgoyette /** 771 1.4.2.2 pgoyette * ixgbe_iosf_wait - Wait for IOSF command completion 772 1.4.2.2 pgoyette * @hw: pointer to hardware structure 773 1.4.2.2 pgoyette * @ctrl: pointer to location to receive final IOSF control value 774 1.4.2.2 pgoyette * 775 1.4.2.2 pgoyette * Returns failing status on timeout 776 1.4.2.2 pgoyette * 777 1.4.2.2 pgoyette * Note: ctrl can be NULL if the IOSF control register value is not needed 778 1.4.2.2 pgoyette **/ 779 1.4.2.2 pgoyette static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) 780 1.4.2.2 pgoyette { 781 1.4.2.2 pgoyette u32 i, command = 0; 782 1.4.2.2 pgoyette 783 1.4.2.2 pgoyette /* Check every 10 usec to see if the address cycle completed. 784 1.4.2.2 pgoyette * The SB IOSF BUSY bit will clear when the operation is 785 1.4.2.2 pgoyette * complete 786 1.4.2.2 pgoyette */ 787 1.4.2.2 pgoyette for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 788 1.4.2.2 pgoyette command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); 789 1.4.2.2 pgoyette if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0) 790 1.4.2.2 pgoyette break; 791 1.4.2.2 pgoyette usec_delay(10); 792 1.4.2.2 pgoyette } 793 1.4.2.2 pgoyette if (ctrl) 794 1.4.2.2 pgoyette *ctrl = command; 795 1.4.2.2 pgoyette if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { 796 1.4.2.2 pgoyette ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n"); 797 1.4.2.2 pgoyette return IXGBE_ERR_PHY; 798 1.4.2.2 pgoyette } 799 1.4.2.2 pgoyette 800 1.4.2.2 pgoyette return IXGBE_SUCCESS; 801 1.4.2.2 pgoyette } 802 1.4.2.2 pgoyette 803 1.4.2.2 pgoyette /** 804 1.4.2.2 pgoyette * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF 805 1.4.2.2 pgoyette * device 806 1.4.2.2 pgoyette * @hw: pointer to hardware structure 807 1.4.2.2 pgoyette * @reg_addr: 32 bit PHY register to write 808 1.4.2.2 pgoyette * @device_type: 3 bit device type 809 1.4.2.2 pgoyette * @data: Data to write to the register 810 1.4.2.2 pgoyette **/ 811 1.4.2.2 pgoyette s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 812 1.4.2.2 pgoyette u32 device_type, u32 data) 813 1.4.2.2 pgoyette { 814 1.4.2.2 pgoyette u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 815 1.4.2.2 pgoyette u32 command, error __unused; 816 1.4.2.2 pgoyette s32 ret; 817 1.4.2.2 pgoyette 818 1.4.2.2 pgoyette ret = ixgbe_acquire_swfw_semaphore(hw, gssr); 819 1.4.2.2 pgoyette if (ret != IXGBE_SUCCESS) 820 1.4.2.2 pgoyette return ret; 821 1.4.2.2 pgoyette 822 1.4.2.2 pgoyette ret = ixgbe_iosf_wait(hw, NULL); 823 1.4.2.2 pgoyette if (ret != IXGBE_SUCCESS) 824 1.4.2.2 pgoyette goto out; 825 1.4.2.2 pgoyette 826 1.4.2.2 pgoyette command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 827 1.4.2.2 pgoyette (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 828 1.4.2.2 pgoyette 829 1.4.2.2 pgoyette /* Write IOSF control register */ 830 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 831 1.4.2.2 pgoyette 832 1.4.2.2 pgoyette /* Write IOSF data register */ 833 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); 834 1.4.2.2 pgoyette 835 1.4.2.2 pgoyette ret = ixgbe_iosf_wait(hw, &command); 836 1.4.2.2 pgoyette 837 1.4.2.2 pgoyette if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 838 1.4.2.2 pgoyette error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 839 1.4.2.2 pgoyette IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 840 1.4.2.2 pgoyette ERROR_REPORT2(IXGBE_ERROR_POLLING, 841 1.4.2.2 pgoyette "Failed to write, error %x\n", error); 842 1.4.2.2 pgoyette ret = IXGBE_ERR_PHY; 843 1.4.2.2 pgoyette } 844 1.4.2.2 pgoyette 845 1.4.2.2 pgoyette out: 846 1.4.2.2 pgoyette ixgbe_release_swfw_semaphore(hw, gssr); 847 1.4.2.2 pgoyette return ret; 848 1.4.2.2 pgoyette } 849 1.4.2.2 pgoyette 850 1.4.2.2 pgoyette /** 851 1.4.2.2 pgoyette * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF 852 1.4.2.2 pgoyette * device 853 1.4.2.2 pgoyette * @hw: pointer to hardware structure 854 1.4.2.2 pgoyette * @reg_addr: 32 bit PHY register to write 855 1.4.2.2 pgoyette * @device_type: 3 bit device type 856 1.4.2.2 pgoyette * @phy_data: Pointer to read data from the register 857 1.4.2.2 pgoyette **/ 858 1.4.2.2 pgoyette s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 859 1.4.2.2 pgoyette u32 device_type, u32 *data) 860 1.4.2.2 pgoyette { 861 1.4.2.2 pgoyette u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 862 1.4.2.2 pgoyette u32 command, error __unused; 863 1.4.2.2 pgoyette s32 ret; 864 1.4.2.2 pgoyette 865 1.4.2.2 pgoyette ret = ixgbe_acquire_swfw_semaphore(hw, gssr); 866 1.4.2.2 pgoyette if (ret != IXGBE_SUCCESS) 867 1.4.2.2 pgoyette return ret; 868 1.4.2.2 pgoyette 869 1.4.2.2 pgoyette ret = ixgbe_iosf_wait(hw, NULL); 870 1.4.2.2 pgoyette if (ret != IXGBE_SUCCESS) 871 1.4.2.2 pgoyette goto out; 872 1.4.2.2 pgoyette 873 1.4.2.2 pgoyette command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 874 1.4.2.2 pgoyette (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 875 1.4.2.2 pgoyette 876 1.4.2.2 pgoyette /* Write IOSF control register */ 877 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 878 1.4.2.2 pgoyette 879 1.4.2.2 pgoyette ret = ixgbe_iosf_wait(hw, &command); 880 1.4.2.2 pgoyette 881 1.4.2.2 pgoyette if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 882 1.4.2.2 pgoyette error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 883 1.4.2.2 pgoyette IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 884 1.4.2.2 pgoyette ERROR_REPORT2(IXGBE_ERROR_POLLING, 885 1.4.2.2 pgoyette "Failed to read, error %x\n", error); 886 1.4.2.2 pgoyette ret = IXGBE_ERR_PHY; 887 1.4.2.2 pgoyette } 888 1.4.2.2 pgoyette 889 1.4.2.2 pgoyette if (ret == IXGBE_SUCCESS) 890 1.4.2.2 pgoyette *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); 891 1.4.2.2 pgoyette 892 1.4.2.2 pgoyette out: 893 1.4.2.2 pgoyette ixgbe_release_swfw_semaphore(hw, gssr); 894 1.4.2.2 pgoyette return ret; 895 1.4.2.2 pgoyette } 896 1.4.2.2 pgoyette 897 1.4.2.2 pgoyette /** 898 1.4.2.2 pgoyette * ixgbe_disable_mdd_X550 899 1.4.2.2 pgoyette * @hw: pointer to hardware structure 900 1.4.2.2 pgoyette * 901 1.4.2.2 pgoyette * Disable malicious driver detection 902 1.4.2.2 pgoyette **/ 903 1.4.2.2 pgoyette void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw) 904 1.4.2.2 pgoyette { 905 1.4.2.2 pgoyette u32 reg; 906 1.4.2.2 pgoyette 907 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_disable_mdd_X550"); 908 1.4.2.2 pgoyette 909 1.4.2.2 pgoyette /* Disable MDD for TX DMA and interrupt */ 910 1.4.2.2 pgoyette reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 911 1.4.2.2 pgoyette reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN); 912 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 913 1.4.2.2 pgoyette 914 1.4.2.2 pgoyette /* Disable MDD for RX and interrupt */ 915 1.4.2.2 pgoyette reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 916 1.4.2.2 pgoyette reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN); 917 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 918 1.4.2.2 pgoyette } 919 1.4.2.2 pgoyette 920 1.4.2.2 pgoyette /** 921 1.4.2.2 pgoyette * ixgbe_enable_mdd_X550 922 1.4.2.2 pgoyette * @hw: pointer to hardware structure 923 1.4.2.2 pgoyette * 924 1.4.2.2 pgoyette * Enable malicious driver detection 925 1.4.2.2 pgoyette **/ 926 1.4.2.2 pgoyette void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw) 927 1.4.2.2 pgoyette { 928 1.4.2.2 pgoyette u32 reg; 929 1.4.2.2 pgoyette 930 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_enable_mdd_X550"); 931 1.4.2.2 pgoyette 932 1.4.2.2 pgoyette /* Enable MDD for TX DMA and interrupt */ 933 1.4.2.2 pgoyette reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 934 1.4.2.2 pgoyette reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN); 935 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 936 1.4.2.2 pgoyette 937 1.4.2.2 pgoyette /* Enable MDD for RX and interrupt */ 938 1.4.2.2 pgoyette reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 939 1.4.2.2 pgoyette reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN); 940 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 941 1.4.2.2 pgoyette } 942 1.4.2.2 pgoyette 943 1.4.2.2 pgoyette /** 944 1.4.2.2 pgoyette * ixgbe_restore_mdd_vf_X550 945 1.4.2.2 pgoyette * @hw: pointer to hardware structure 946 1.4.2.2 pgoyette * @vf: vf index 947 1.4.2.2 pgoyette * 948 1.4.2.2 pgoyette * Restore VF that was disabled during malicious driver detection event 949 1.4.2.2 pgoyette **/ 950 1.4.2.2 pgoyette void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf) 951 1.4.2.2 pgoyette { 952 1.4.2.2 pgoyette u32 idx, reg, num_qs, start_q, bitmask; 953 1.4.2.2 pgoyette 954 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_restore_mdd_vf_X550"); 955 1.4.2.2 pgoyette 956 1.4.2.2 pgoyette /* Map VF to queues */ 957 1.4.2.2 pgoyette reg = IXGBE_READ_REG(hw, IXGBE_MRQC); 958 1.4.2.2 pgoyette switch (reg & IXGBE_MRQC_MRQE_MASK) { 959 1.4.2.2 pgoyette case IXGBE_MRQC_VMDQRT8TCEN: 960 1.4.2.2 pgoyette num_qs = 8; /* 16 VFs / pools */ 961 1.4.2.2 pgoyette bitmask = 0x000000FF; 962 1.4.2.2 pgoyette break; 963 1.4.2.2 pgoyette case IXGBE_MRQC_VMDQRSS32EN: 964 1.4.2.2 pgoyette case IXGBE_MRQC_VMDQRT4TCEN: 965 1.4.2.2 pgoyette num_qs = 4; /* 32 VFs / pools */ 966 1.4.2.2 pgoyette bitmask = 0x0000000F; 967 1.4.2.2 pgoyette break; 968 1.4.2.3 pgoyette default: /* 64 VFs / pools */ 969 1.4.2.2 pgoyette num_qs = 2; 970 1.4.2.2 pgoyette bitmask = 0x00000003; 971 1.4.2.2 pgoyette break; 972 1.4.2.2 pgoyette } 973 1.4.2.2 pgoyette start_q = vf * num_qs; 974 1.4.2.2 pgoyette 975 1.4.2.2 pgoyette /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */ 976 1.4.2.2 pgoyette idx = start_q / 32; 977 1.4.2.2 pgoyette reg = 0; 978 1.4.2.2 pgoyette reg |= (bitmask << (start_q % 32)); 979 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg); 980 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg); 981 1.4.2.2 pgoyette } 982 1.4.2.2 pgoyette 983 1.4.2.2 pgoyette /** 984 1.4.2.2 pgoyette * ixgbe_mdd_event_X550 985 1.4.2.2 pgoyette * @hw: pointer to hardware structure 986 1.4.2.2 pgoyette * @vf_bitmap: vf bitmap of malicious vfs 987 1.4.2.2 pgoyette * 988 1.4.2.2 pgoyette * Handle malicious driver detection event. 989 1.4.2.2 pgoyette **/ 990 1.4.2.2 pgoyette void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap) 991 1.4.2.2 pgoyette { 992 1.4.2.2 pgoyette u32 wqbr; 993 1.4.2.2 pgoyette u32 i, j, reg, q, shift, vf, idx; 994 1.4.2.2 pgoyette 995 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_mdd_event_X550"); 996 1.4.2.2 pgoyette 997 1.4.2.2 pgoyette /* figure out pool size for mapping to vf's */ 998 1.4.2.2 pgoyette reg = IXGBE_READ_REG(hw, IXGBE_MRQC); 999 1.4.2.2 pgoyette switch (reg & IXGBE_MRQC_MRQE_MASK) { 1000 1.4.2.2 pgoyette case IXGBE_MRQC_VMDQRT8TCEN: 1001 1.4.2.2 pgoyette shift = 3; /* 16 VFs / pools */ 1002 1.4.2.2 pgoyette break; 1003 1.4.2.2 pgoyette case IXGBE_MRQC_VMDQRSS32EN: 1004 1.4.2.2 pgoyette case IXGBE_MRQC_VMDQRT4TCEN: 1005 1.4.2.2 pgoyette shift = 2; /* 32 VFs / pools */ 1006 1.4.2.2 pgoyette break; 1007 1.4.2.2 pgoyette default: 1008 1.4.2.2 pgoyette shift = 1; /* 64 VFs / pools */ 1009 1.4.2.2 pgoyette break; 1010 1.4.2.2 pgoyette } 1011 1.4.2.2 pgoyette 1012 1.4.2.2 pgoyette /* Read WQBR_TX and WQBR_RX and check for malicious queues */ 1013 1.4.2.2 pgoyette for (i = 0; i < 4; i++) { 1014 1.4.2.2 pgoyette wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i)); 1015 1.4.2.2 pgoyette wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i)); 1016 1.4.2.2 pgoyette 1017 1.4.2.2 pgoyette if (!wqbr) 1018 1.4.2.2 pgoyette continue; 1019 1.4.2.2 pgoyette 1020 1.4.2.2 pgoyette /* Get malicious queue */ 1021 1.4.2.2 pgoyette for (j = 0; j < 32 && wqbr; j++) { 1022 1.4.2.2 pgoyette 1023 1.4.2.2 pgoyette if (!(wqbr & (1 << j))) 1024 1.4.2.2 pgoyette continue; 1025 1.4.2.2 pgoyette 1026 1.4.2.2 pgoyette /* Get queue from bitmask */ 1027 1.4.2.2 pgoyette q = j + (i * 32); 1028 1.4.2.2 pgoyette 1029 1.4.2.2 pgoyette /* Map queue to vf */ 1030 1.4.2.2 pgoyette vf = (q >> shift); 1031 1.4.2.2 pgoyette 1032 1.4.2.2 pgoyette /* Set vf bit in vf_bitmap */ 1033 1.4.2.2 pgoyette idx = vf / 32; 1034 1.4.2.2 pgoyette vf_bitmap[idx] |= (1 << (vf % 32)); 1035 1.4.2.2 pgoyette wqbr &= ~(1 << j); 1036 1.4.2.2 pgoyette } 1037 1.4.2.2 pgoyette } 1038 1.4.2.2 pgoyette } 1039 1.4.2.2 pgoyette 1040 1.4.2.2 pgoyette /** 1041 1.4.2.2 pgoyette * ixgbe_get_media_type_X550em - Get media type 1042 1.4.2.2 pgoyette * @hw: pointer to hardware structure 1043 1.4.2.2 pgoyette * 1044 1.4.2.2 pgoyette * Returns the media type (fiber, copper, backplane) 1045 1.4.2.2 pgoyette */ 1046 1.4.2.2 pgoyette enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) 1047 1.4.2.2 pgoyette { 1048 1.4.2.2 pgoyette enum ixgbe_media_type media_type; 1049 1.4.2.2 pgoyette 1050 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_get_media_type_X550em"); 1051 1.4.2.2 pgoyette 1052 1.4.2.2 pgoyette /* Detect if there is a copper PHY attached. */ 1053 1.4.2.2 pgoyette switch (hw->device_id) { 1054 1.4.2.2 pgoyette case IXGBE_DEV_ID_X550EM_X_KR: 1055 1.4.2.2 pgoyette case IXGBE_DEV_ID_X550EM_X_KX4: 1056 1.4.2.2 pgoyette media_type = ixgbe_media_type_backplane; 1057 1.4.2.2 pgoyette break; 1058 1.4.2.2 pgoyette case IXGBE_DEV_ID_X550EM_X_SFP: 1059 1.4.2.2 pgoyette media_type = ixgbe_media_type_fiber; 1060 1.4.2.2 pgoyette break; 1061 1.4.2.2 pgoyette case IXGBE_DEV_ID_X550EM_X_1G_T: 1062 1.4.2.2 pgoyette case IXGBE_DEV_ID_X550EM_X_10G_T: 1063 1.4.2.2 pgoyette media_type = ixgbe_media_type_copper; 1064 1.4.2.2 pgoyette break; 1065 1.4.2.2 pgoyette default: 1066 1.4.2.2 pgoyette media_type = ixgbe_media_type_unknown; 1067 1.4.2.2 pgoyette break; 1068 1.4.2.2 pgoyette } 1069 1.4.2.2 pgoyette return media_type; 1070 1.4.2.2 pgoyette } 1071 1.4.2.2 pgoyette 1072 1.4.2.2 pgoyette /** 1073 1.4.2.2 pgoyette * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported 1074 1.4.2.2 pgoyette * @hw: pointer to hardware structure 1075 1.4.2.2 pgoyette * @linear: TRUE if SFP module is linear 1076 1.4.2.2 pgoyette */ 1077 1.4.2.2 pgoyette static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear) 1078 1.4.2.2 pgoyette { 1079 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_supported_sfp_modules_X550em"); 1080 1.4.2.2 pgoyette 1081 1.4.2.2 pgoyette switch (hw->phy.sfp_type) { 1082 1.4.2.2 pgoyette case ixgbe_sfp_type_not_present: 1083 1.4.2.2 pgoyette return IXGBE_ERR_SFP_NOT_PRESENT; 1084 1.4.2.2 pgoyette case ixgbe_sfp_type_da_cu_core0: 1085 1.4.2.2 pgoyette case ixgbe_sfp_type_da_cu_core1: 1086 1.4.2.2 pgoyette *linear = TRUE; 1087 1.4.2.2 pgoyette break; 1088 1.4.2.2 pgoyette case ixgbe_sfp_type_srlr_core0: 1089 1.4.2.2 pgoyette case ixgbe_sfp_type_srlr_core1: 1090 1.4.2.2 pgoyette case ixgbe_sfp_type_da_act_lmt_core0: 1091 1.4.2.2 pgoyette case ixgbe_sfp_type_da_act_lmt_core1: 1092 1.4.2.2 pgoyette case ixgbe_sfp_type_1g_sx_core0: 1093 1.4.2.2 pgoyette case ixgbe_sfp_type_1g_sx_core1: 1094 1.4.2.2 pgoyette case ixgbe_sfp_type_1g_lx_core0: 1095 1.4.2.2 pgoyette case ixgbe_sfp_type_1g_lx_core1: 1096 1.4.2.2 pgoyette *linear = FALSE; 1097 1.4.2.2 pgoyette break; 1098 1.4.2.2 pgoyette case ixgbe_sfp_type_unknown: 1099 1.4.2.2 pgoyette case ixgbe_sfp_type_1g_cu_core0: 1100 1.4.2.2 pgoyette case ixgbe_sfp_type_1g_cu_core1: 1101 1.4.2.2 pgoyette default: 1102 1.4.2.2 pgoyette return IXGBE_ERR_SFP_NOT_SUPPORTED; 1103 1.4.2.2 pgoyette } 1104 1.4.2.2 pgoyette 1105 1.4.2.2 pgoyette return IXGBE_SUCCESS; 1106 1.4.2.2 pgoyette } 1107 1.4.2.2 pgoyette 1108 1.4.2.2 pgoyette /** 1109 1.4.2.2 pgoyette * ixgbe_identify_sfp_module_X550em - Identifies SFP modules 1110 1.4.2.2 pgoyette * @hw: pointer to hardware structure 1111 1.4.2.2 pgoyette * 1112 1.4.2.2 pgoyette * Searches for and identifies the SFP module and assigns appropriate PHY type. 1113 1.4.2.2 pgoyette **/ 1114 1.4.2.2 pgoyette s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw) 1115 1.4.2.2 pgoyette { 1116 1.4.2.2 pgoyette s32 status; 1117 1.4.2.2 pgoyette bool linear; 1118 1.4.2.2 pgoyette 1119 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_identify_sfp_module_X550em"); 1120 1.4.2.2 pgoyette 1121 1.4.2.2 pgoyette status = ixgbe_identify_module_generic(hw); 1122 1.4.2.2 pgoyette 1123 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1124 1.4.2.2 pgoyette return status; 1125 1.4.2.2 pgoyette 1126 1.4.2.2 pgoyette /* Check if SFP module is supported */ 1127 1.4.2.2 pgoyette status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 1128 1.4.2.2 pgoyette 1129 1.4.2.2 pgoyette return status; 1130 1.4.2.2 pgoyette } 1131 1.4.2.2 pgoyette 1132 1.4.2.2 pgoyette /** 1133 1.4.2.2 pgoyette * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops 1134 1.4.2.2 pgoyette * @hw: pointer to hardware structure 1135 1.4.2.2 pgoyette */ 1136 1.4.2.2 pgoyette s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) 1137 1.4.2.2 pgoyette { 1138 1.4.2.2 pgoyette s32 status; 1139 1.4.2.2 pgoyette bool linear; 1140 1.4.2.2 pgoyette 1141 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_setup_sfp_modules_X550em"); 1142 1.4.2.2 pgoyette 1143 1.4.2.2 pgoyette /* Check if SFP module is supported */ 1144 1.4.2.2 pgoyette status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 1145 1.4.2.2 pgoyette 1146 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1147 1.4.2.2 pgoyette return status; 1148 1.4.2.2 pgoyette 1149 1.4.2.2 pgoyette ixgbe_init_mac_link_ops_X550em(hw); 1150 1.4.2.2 pgoyette hw->phy.ops.reset = NULL; 1151 1.4.2.2 pgoyette 1152 1.4.2.2 pgoyette return IXGBE_SUCCESS; 1153 1.4.2.2 pgoyette } 1154 1.4.2.2 pgoyette 1155 1.4.2.2 pgoyette /** 1156 1.4.2.2 pgoyette * ixgbe_init_mac_link_ops_X550em - init mac link function pointers 1157 1.4.2.2 pgoyette * @hw: pointer to hardware structure 1158 1.4.2.2 pgoyette */ 1159 1.4.2.2 pgoyette void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) 1160 1.4.2.2 pgoyette { 1161 1.4.2.2 pgoyette struct ixgbe_mac_info *mac = &hw->mac; 1162 1.4.2.2 pgoyette 1163 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_init_mac_link_ops_X550em"); 1164 1.4.2.2 pgoyette 1165 1.4.2.2 pgoyette switch (hw->mac.ops.get_media_type(hw)) { 1166 1.4.2.2 pgoyette case ixgbe_media_type_fiber: 1167 1.4.2.2 pgoyette /* CS4227 does not support autoneg, so disable the laser control 1168 1.4.2.2 pgoyette * functions for SFP+ fiber 1169 1.4.2.2 pgoyette */ 1170 1.4.2.2 pgoyette mac->ops.disable_tx_laser = NULL; 1171 1.4.2.2 pgoyette mac->ops.enable_tx_laser = NULL; 1172 1.4.2.2 pgoyette mac->ops.flap_tx_laser = NULL; 1173 1.4.2.2 pgoyette mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 1174 1.4.2.2 pgoyette mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em; 1175 1.4.2.2 pgoyette mac->ops.set_rate_select_speed = 1176 1.4.2.2 pgoyette ixgbe_set_soft_rate_select_speed; 1177 1.4.2.2 pgoyette break; 1178 1.4.2.2 pgoyette case ixgbe_media_type_copper: 1179 1.4.2.2 pgoyette mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 1180 1.4.2.2 pgoyette mac->ops.check_link = ixgbe_check_link_t_X550em; 1181 1.4.2.2 pgoyette break; 1182 1.4.2.2 pgoyette default: 1183 1.4.2.2 pgoyette break; 1184 1.4.2.2 pgoyette } 1185 1.4.2.2 pgoyette } 1186 1.4.2.2 pgoyette 1187 1.4.2.2 pgoyette /** 1188 1.4.2.2 pgoyette * ixgbe_get_link_capabilities_x550em - Determines link capabilities 1189 1.4.2.2 pgoyette * @hw: pointer to hardware structure 1190 1.4.2.2 pgoyette * @speed: pointer to link speed 1191 1.4.2.2 pgoyette * @autoneg: TRUE when autoneg or autotry is enabled 1192 1.4.2.2 pgoyette */ 1193 1.4.2.2 pgoyette s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, 1194 1.4.2.2 pgoyette ixgbe_link_speed *speed, 1195 1.4.2.2 pgoyette bool *autoneg) 1196 1.4.2.2 pgoyette { 1197 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_get_link_capabilities_X550em"); 1198 1.4.2.2 pgoyette 1199 1.4.2.2 pgoyette /* SFP */ 1200 1.4.2.2 pgoyette if (hw->phy.media_type == ixgbe_media_type_fiber) { 1201 1.4.2.2 pgoyette 1202 1.4.2.2 pgoyette /* CS4227 SFP must not enable auto-negotiation */ 1203 1.4.2.2 pgoyette *autoneg = FALSE; 1204 1.4.2.2 pgoyette 1205 1.4.2.2 pgoyette /* Check if 1G SFP module. */ 1206 1.4.2.2 pgoyette if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1207 1.4.2.2 pgoyette hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 1208 1.4.2.2 pgoyette || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1209 1.4.2.2 pgoyette hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) { 1210 1.4.2.2 pgoyette *speed = IXGBE_LINK_SPEED_1GB_FULL; 1211 1.4.2.2 pgoyette return IXGBE_SUCCESS; 1212 1.4.2.2 pgoyette } 1213 1.4.2.2 pgoyette 1214 1.4.2.2 pgoyette /* Link capabilities are based on SFP */ 1215 1.4.2.2 pgoyette if (hw->phy.multispeed_fiber) 1216 1.4.2.2 pgoyette *speed = IXGBE_LINK_SPEED_10GB_FULL | 1217 1.4.2.2 pgoyette IXGBE_LINK_SPEED_1GB_FULL; 1218 1.4.2.2 pgoyette else 1219 1.4.2.2 pgoyette *speed = IXGBE_LINK_SPEED_10GB_FULL; 1220 1.4.2.2 pgoyette } else { 1221 1.4.2.2 pgoyette *speed = IXGBE_LINK_SPEED_10GB_FULL | 1222 1.4.2.2 pgoyette IXGBE_LINK_SPEED_1GB_FULL; 1223 1.4.2.2 pgoyette *autoneg = TRUE; 1224 1.4.2.2 pgoyette } 1225 1.4.2.2 pgoyette 1226 1.4.2.2 pgoyette return IXGBE_SUCCESS; 1227 1.4.2.2 pgoyette } 1228 1.4.2.2 pgoyette 1229 1.4.2.2 pgoyette /** 1230 1.4.2.2 pgoyette * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause 1231 1.4.2.2 pgoyette * @hw: pointer to hardware structure 1232 1.4.2.2 pgoyette * @lsc: pointer to boolean flag which indicates whether external Base T 1233 1.4.2.2 pgoyette * PHY interrupt is lsc 1234 1.4.2.2 pgoyette * 1235 1.4.2.2 pgoyette * Determime if external Base T PHY interrupt cause is high temperature 1236 1.4.2.2 pgoyette * failure alarm or link status change. 1237 1.4.2.2 pgoyette * 1238 1.4.2.2 pgoyette * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1239 1.4.2.2 pgoyette * failure alarm, else return PHY access status. 1240 1.4.2.2 pgoyette */ 1241 1.4.2.2 pgoyette static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc) 1242 1.4.2.2 pgoyette { 1243 1.4.2.2 pgoyette u32 status; 1244 1.4.2.2 pgoyette u16 reg; 1245 1.4.2.2 pgoyette 1246 1.4.2.2 pgoyette *lsc = FALSE; 1247 1.4.2.2 pgoyette 1248 1.4.2.2 pgoyette /* Vendor alarm triggered */ 1249 1.4.2.2 pgoyette status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 1250 1.4.2.2 pgoyette IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1251 1.4.2.2 pgoyette ®); 1252 1.4.2.2 pgoyette 1253 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS || 1254 1.4.2.2 pgoyette !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN)) 1255 1.4.2.2 pgoyette return status; 1256 1.4.2.2 pgoyette 1257 1.4.2.2 pgoyette /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */ 1258 1.4.2.2 pgoyette status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, 1259 1.4.2.2 pgoyette IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1260 1.4.2.2 pgoyette ®); 1261 1.4.2.2 pgoyette 1262 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS || 1263 1.4.2.2 pgoyette !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 1264 1.4.2.2 pgoyette IXGBE_MDIO_GLOBAL_ALARM_1_INT))) 1265 1.4.2.2 pgoyette return status; 1266 1.4.2.2 pgoyette 1267 1.4.2.2 pgoyette /* Global alarm triggered */ 1268 1.4.2.2 pgoyette status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, 1269 1.4.2.2 pgoyette IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1270 1.4.2.2 pgoyette ®); 1271 1.4.2.2 pgoyette 1272 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1273 1.4.2.2 pgoyette return status; 1274 1.4.2.2 pgoyette 1275 1.4.2.2 pgoyette /* If high temperature failure, then return over temp error and exit */ 1276 1.4.2.2 pgoyette if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) { 1277 1.4.2.2 pgoyette /* power down the PHY in case the PHY FW didn't already */ 1278 1.4.2.2 pgoyette ixgbe_set_copper_phy_power(hw, FALSE); 1279 1.4.2.2 pgoyette return IXGBE_ERR_OVERTEMP; 1280 1.4.2.2 pgoyette } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) { 1281 1.4.2.2 pgoyette /* device fault alarm triggered */ 1282 1.4.2.2 pgoyette status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG, 1283 1.4.2.2 pgoyette IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1284 1.4.2.2 pgoyette ®); 1285 1.4.2.2 pgoyette 1286 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1287 1.4.2.2 pgoyette return status; 1288 1.4.2.2 pgoyette 1289 1.4.2.2 pgoyette /* if device fault was due to high temp alarm handle and exit */ 1290 1.4.2.2 pgoyette if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) { 1291 1.4.2.2 pgoyette /* power down the PHY in case the PHY FW didn't */ 1292 1.4.2.2 pgoyette ixgbe_set_copper_phy_power(hw, FALSE); 1293 1.4.2.2 pgoyette return IXGBE_ERR_OVERTEMP; 1294 1.4.2.2 pgoyette } 1295 1.4.2.2 pgoyette } 1296 1.4.2.2 pgoyette 1297 1.4.2.2 pgoyette /* Vendor alarm 2 triggered */ 1298 1.4.2.2 pgoyette status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 1299 1.4.2.2 pgoyette IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 1300 1.4.2.2 pgoyette 1301 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS || 1302 1.4.2.2 pgoyette !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT)) 1303 1.4.2.2 pgoyette return status; 1304 1.4.2.2 pgoyette 1305 1.4.2.2 pgoyette /* link connect/disconnect event occurred */ 1306 1.4.2.2 pgoyette status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2, 1307 1.4.2.2 pgoyette IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 1308 1.4.2.2 pgoyette 1309 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1310 1.4.2.2 pgoyette return status; 1311 1.4.2.2 pgoyette 1312 1.4.2.2 pgoyette /* Indicate LSC */ 1313 1.4.2.2 pgoyette if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC) 1314 1.4.2.2 pgoyette *lsc = TRUE; 1315 1.4.2.2 pgoyette 1316 1.4.2.2 pgoyette return IXGBE_SUCCESS; 1317 1.4.2.2 pgoyette } 1318 1.4.2.2 pgoyette 1319 1.4.2.2 pgoyette /** 1320 1.4.2.2 pgoyette * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts 1321 1.4.2.2 pgoyette * @hw: pointer to hardware structure 1322 1.4.2.2 pgoyette * 1323 1.4.2.2 pgoyette * Enable link status change and temperature failure alarm for the external 1324 1.4.2.2 pgoyette * Base T PHY 1325 1.4.2.2 pgoyette * 1326 1.4.2.2 pgoyette * Returns PHY access status 1327 1.4.2.2 pgoyette */ 1328 1.4.2.2 pgoyette static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw) 1329 1.4.2.2 pgoyette { 1330 1.4.2.2 pgoyette u32 status; 1331 1.4.2.2 pgoyette u16 reg; 1332 1.4.2.2 pgoyette bool lsc; 1333 1.4.2.2 pgoyette 1334 1.4.2.2 pgoyette /* Clear interrupt flags */ 1335 1.4.2.2 pgoyette status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 1336 1.4.2.2 pgoyette 1337 1.4.2.2 pgoyette /* Enable link status change alarm */ 1338 1.4.2.2 pgoyette status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 1339 1.4.2.2 pgoyette IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 1340 1.4.2.2 pgoyette 1341 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1342 1.4.2.2 pgoyette return status; 1343 1.4.2.2 pgoyette 1344 1.4.2.2 pgoyette reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN; 1345 1.4.2.2 pgoyette 1346 1.4.2.2 pgoyette status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 1347 1.4.2.2 pgoyette IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg); 1348 1.4.2.2 pgoyette 1349 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1350 1.4.2.2 pgoyette return status; 1351 1.4.2.2 pgoyette 1352 1.4.2.2 pgoyette /* Enables high temperature failure alarm */ 1353 1.4.2.2 pgoyette status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 1354 1.4.2.2 pgoyette IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1355 1.4.2.2 pgoyette ®); 1356 1.4.2.2 pgoyette 1357 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1358 1.4.2.2 pgoyette return status; 1359 1.4.2.2 pgoyette 1360 1.4.2.2 pgoyette reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN; 1361 1.4.2.2 pgoyette 1362 1.4.2.2 pgoyette status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 1363 1.4.2.2 pgoyette IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1364 1.4.2.2 pgoyette reg); 1365 1.4.2.2 pgoyette 1366 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1367 1.4.2.2 pgoyette return status; 1368 1.4.2.2 pgoyette 1369 1.4.2.2 pgoyette /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */ 1370 1.4.2.2 pgoyette status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 1371 1.4.2.2 pgoyette IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1372 1.4.2.2 pgoyette ®); 1373 1.4.2.2 pgoyette 1374 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1375 1.4.2.2 pgoyette return status; 1376 1.4.2.2 pgoyette 1377 1.4.2.2 pgoyette reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 1378 1.4.2.2 pgoyette IXGBE_MDIO_GLOBAL_ALARM_1_INT); 1379 1.4.2.2 pgoyette 1380 1.4.2.2 pgoyette status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 1381 1.4.2.2 pgoyette IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1382 1.4.2.2 pgoyette reg); 1383 1.4.2.2 pgoyette 1384 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1385 1.4.2.2 pgoyette return status; 1386 1.4.2.2 pgoyette 1387 1.4.2.2 pgoyette /* Enable chip-wide vendor alarm */ 1388 1.4.2.2 pgoyette status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 1389 1.4.2.2 pgoyette IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1390 1.4.2.2 pgoyette ®); 1391 1.4.2.2 pgoyette 1392 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1393 1.4.2.2 pgoyette return status; 1394 1.4.2.2 pgoyette 1395 1.4.2.2 pgoyette reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN; 1396 1.4.2.2 pgoyette 1397 1.4.2.2 pgoyette status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 1398 1.4.2.2 pgoyette IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1399 1.4.2.2 pgoyette reg); 1400 1.4.2.2 pgoyette 1401 1.4.2.2 pgoyette return status; 1402 1.4.2.2 pgoyette } 1403 1.4.2.2 pgoyette 1404 1.4.2.2 pgoyette /** 1405 1.4.2.2 pgoyette * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed. 1406 1.4.2.2 pgoyette * @hw: pointer to hardware structure 1407 1.4.2.2 pgoyette * @speed: link speed 1408 1.4.2.2 pgoyette * 1409 1.4.2.2 pgoyette * Configures the integrated KR PHY. 1410 1.4.2.2 pgoyette **/ 1411 1.4.2.2 pgoyette static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, 1412 1.4.2.2 pgoyette ixgbe_link_speed speed) 1413 1.4.2.2 pgoyette { 1414 1.4.2.2 pgoyette s32 status; 1415 1.4.2.2 pgoyette u32 reg_val; 1416 1.4.2.2 pgoyette 1417 1.4.2.2 pgoyette status = ixgbe_read_iosf_sb_reg_x550(hw, 1418 1.4.2.2 pgoyette IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1419 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1420 1.4.2.2 pgoyette if (status) 1421 1.4.2.2 pgoyette return status; 1422 1.4.2.2 pgoyette 1423 1.4.2.2 pgoyette reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1424 1.4.2.2 pgoyette reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | 1425 1.4.2.2 pgoyette IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); 1426 1.4.2.2 pgoyette 1427 1.4.2.2 pgoyette /* Advertise 10G support. */ 1428 1.4.2.2 pgoyette if (speed & IXGBE_LINK_SPEED_10GB_FULL) 1429 1.4.2.2 pgoyette reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; 1430 1.4.2.2 pgoyette 1431 1.4.2.2 pgoyette /* Advertise 1G support. */ 1432 1.4.2.2 pgoyette if (speed & IXGBE_LINK_SPEED_1GB_FULL) 1433 1.4.2.2 pgoyette reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; 1434 1.4.2.2 pgoyette 1435 1.4.2.2 pgoyette /* Restart auto-negotiation. */ 1436 1.4.2.2 pgoyette reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1437 1.4.2.2 pgoyette status = ixgbe_write_iosf_sb_reg_x550(hw, 1438 1.4.2.2 pgoyette IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1439 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1440 1.4.2.2 pgoyette 1441 1.4.2.2 pgoyette return status; 1442 1.4.2.2 pgoyette } 1443 1.4.2.2 pgoyette 1444 1.4.2.2 pgoyette /** 1445 1.4.2.2 pgoyette * ixgbe_init_phy_ops_X550em - PHY/SFP specific init 1446 1.4.2.2 pgoyette * @hw: pointer to hardware structure 1447 1.4.2.2 pgoyette * 1448 1.4.2.2 pgoyette * Initialize any function pointers that were not able to be 1449 1.4.2.2 pgoyette * set during init_shared_code because the PHY/SFP type was 1450 1.4.2.2 pgoyette * not known. Perform the SFP init if necessary. 1451 1.4.2.2 pgoyette */ 1452 1.4.2.2 pgoyette s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) 1453 1.4.2.2 pgoyette { 1454 1.4.2.2 pgoyette struct ixgbe_phy_info *phy = &hw->phy; 1455 1.4.2.2 pgoyette ixgbe_link_speed speed; 1456 1.4.2.2 pgoyette s32 ret_val; 1457 1.4.2.2 pgoyette 1458 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_init_phy_ops_X550em"); 1459 1.4.2.2 pgoyette 1460 1.4.2.2 pgoyette hw->mac.ops.set_lan_id(hw); 1461 1.4.2.2 pgoyette 1462 1.4.2.2 pgoyette if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { 1463 1.4.2.2 pgoyette phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 1464 1.4.2.2 pgoyette ixgbe_setup_mux_ctl(hw); 1465 1.4.2.2 pgoyette 1466 1.4.2.2 pgoyette /* Save NW management interface connected on board. This is used 1467 1.4.2.2 pgoyette * to determine internal PHY mode. 1468 1.4.2.2 pgoyette */ 1469 1.4.2.2 pgoyette phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 1470 1.4.2.2 pgoyette if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) { 1471 1.4.2.2 pgoyette speed = IXGBE_LINK_SPEED_10GB_FULL | 1472 1.4.2.2 pgoyette IXGBE_LINK_SPEED_1GB_FULL; 1473 1.4.2.2 pgoyette } 1474 1.4.2.2 pgoyette phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em; 1475 1.4.2.2 pgoyette } 1476 1.4.2.2 pgoyette 1477 1.4.2.2 pgoyette /* Identify the PHY or SFP module */ 1478 1.4.2.2 pgoyette ret_val = phy->ops.identify(hw); 1479 1.4.2.2 pgoyette if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) 1480 1.4.2.2 pgoyette return ret_val; 1481 1.4.2.2 pgoyette 1482 1.4.2.2 pgoyette /* Setup function pointers based on detected hardware */ 1483 1.4.2.2 pgoyette ixgbe_init_mac_link_ops_X550em(hw); 1484 1.4.2.2 pgoyette if (phy->sfp_type != ixgbe_sfp_type_unknown) 1485 1.4.2.2 pgoyette phy->ops.reset = NULL; 1486 1.4.2.2 pgoyette 1487 1.4.2.2 pgoyette /* Set functions pointers based on phy type */ 1488 1.4.2.2 pgoyette switch (hw->phy.type) { 1489 1.4.2.2 pgoyette case ixgbe_phy_x550em_kx4: 1490 1.4.2.2 pgoyette phy->ops.setup_link = NULL; 1491 1.4.2.2 pgoyette phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 1492 1.4.2.2 pgoyette phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 1493 1.4.2.2 pgoyette break; 1494 1.4.2.2 pgoyette case ixgbe_phy_x550em_kr: 1495 1.4.2.2 pgoyette phy->ops.setup_link = ixgbe_setup_kr_x550em; 1496 1.4.2.2 pgoyette phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 1497 1.4.2.2 pgoyette phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 1498 1.4.2.2 pgoyette break; 1499 1.4.2.2 pgoyette case ixgbe_phy_x550em_ext_t: 1500 1.4.2.2 pgoyette /* Save NW management interface connected on board. This is used 1501 1.4.2.2 pgoyette * to determine internal PHY mode 1502 1.4.2.2 pgoyette */ 1503 1.4.2.2 pgoyette phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 1504 1.4.2.2 pgoyette 1505 1.4.2.2 pgoyette /* If internal link mode is XFI, then setup iXFI internal link, 1506 1.4.2.2 pgoyette * else setup KR now. 1507 1.4.2.2 pgoyette */ 1508 1.4.2.2 pgoyette if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 1509 1.4.2.2 pgoyette phy->ops.setup_internal_link = 1510 1.4.2.2 pgoyette ixgbe_setup_internal_phy_t_x550em; 1511 1.4.2.2 pgoyette } else { 1512 1.4.2.2 pgoyette speed = IXGBE_LINK_SPEED_10GB_FULL | 1513 1.4.2.2 pgoyette IXGBE_LINK_SPEED_1GB_FULL; 1514 1.4.2.2 pgoyette ret_val = ixgbe_setup_kr_speed_x550em(hw, speed); 1515 1.4.2.2 pgoyette } 1516 1.4.2.2 pgoyette 1517 1.4.2.2 pgoyette /* setup SW LPLU only for first revision */ 1518 1.4.2.2 pgoyette if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, 1519 1.4.2.2 pgoyette IXGBE_FUSES0_GROUP(0)))) 1520 1.4.2.2 pgoyette phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em; 1521 1.4.2.2 pgoyette 1522 1.4.2.2 pgoyette phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; 1523 1.4.2.2 pgoyette phy->ops.reset = ixgbe_reset_phy_t_X550em; 1524 1.4.2.2 pgoyette break; 1525 1.4.2.2 pgoyette default: 1526 1.4.2.2 pgoyette break; 1527 1.4.2.2 pgoyette } 1528 1.4.2.2 pgoyette return ret_val; 1529 1.4.2.2 pgoyette } 1530 1.4.2.2 pgoyette 1531 1.4.2.2 pgoyette /** 1532 1.4.2.2 pgoyette * ixgbe_reset_hw_X550em - Perform hardware reset 1533 1.4.2.2 pgoyette * @hw: pointer to hardware structure 1534 1.4.2.2 pgoyette * 1535 1.4.2.2 pgoyette * Resets the hardware by resetting the transmit and receive units, masks 1536 1.4.2.2 pgoyette * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 1537 1.4.2.2 pgoyette * reset. 1538 1.4.2.2 pgoyette */ 1539 1.4.2.2 pgoyette s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) 1540 1.4.2.2 pgoyette { 1541 1.4.2.2 pgoyette ixgbe_link_speed link_speed; 1542 1.4.2.2 pgoyette s32 status; 1543 1.4.2.2 pgoyette u32 ctrl = 0; 1544 1.4.2.2 pgoyette u32 i; 1545 1.4.2.2 pgoyette u32 hlreg0; 1546 1.4.2.2 pgoyette bool link_up = FALSE; 1547 1.4.2.2 pgoyette 1548 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_reset_hw_X550em"); 1549 1.4.2.2 pgoyette 1550 1.4.2.2 pgoyette /* Call adapter stop to disable Tx/Rx and clear interrupts */ 1551 1.4.2.2 pgoyette status = hw->mac.ops.stop_adapter(hw); 1552 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1553 1.4.2.2 pgoyette return status; 1554 1.4.2.2 pgoyette 1555 1.4.2.2 pgoyette /* flush pending Tx transactions */ 1556 1.4.2.2 pgoyette ixgbe_clear_tx_pending(hw); 1557 1.4.2.2 pgoyette 1558 1.4.2.2 pgoyette if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) { 1559 1.4.2.2 pgoyette /* Config MDIO clock speed before the first MDIO PHY access */ 1560 1.4.2.2 pgoyette hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 1561 1.4.2.2 pgoyette hlreg0 &= ~IXGBE_HLREG0_MDCSPD; 1562 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 1563 1.4.2.2 pgoyette } 1564 1.4.2.2 pgoyette 1565 1.4.2.2 pgoyette /* PHY ops must be identified and initialized prior to reset */ 1566 1.4.2.2 pgoyette status = hw->phy.ops.init(hw); 1567 1.4.2.2 pgoyette 1568 1.4.2.2 pgoyette if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1569 1.4.2.2 pgoyette return status; 1570 1.4.2.2 pgoyette 1571 1.4.2.2 pgoyette /* start the external PHY */ 1572 1.4.2.2 pgoyette if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 1573 1.4.2.2 pgoyette status = ixgbe_init_ext_t_x550em(hw); 1574 1.4.2.2 pgoyette if (status) 1575 1.4.2.2 pgoyette return status; 1576 1.4.2.2 pgoyette } 1577 1.4.2.2 pgoyette 1578 1.4.2.2 pgoyette /* Setup SFP module if there is one present. */ 1579 1.4.2.2 pgoyette if (hw->phy.sfp_setup_needed) { 1580 1.4.2.2 pgoyette status = hw->mac.ops.setup_sfp(hw); 1581 1.4.2.2 pgoyette hw->phy.sfp_setup_needed = FALSE; 1582 1.4.2.2 pgoyette } 1583 1.4.2.2 pgoyette 1584 1.4.2.2 pgoyette if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1585 1.4.2.2 pgoyette return status; 1586 1.4.2.2 pgoyette 1587 1.4.2.2 pgoyette /* Reset PHY */ 1588 1.4.2.2 pgoyette if (!hw->phy.reset_disable && hw->phy.ops.reset) 1589 1.4.2.2 pgoyette hw->phy.ops.reset(hw); 1590 1.4.2.2 pgoyette 1591 1.4.2.2 pgoyette mac_reset_top: 1592 1.4.2.2 pgoyette /* Issue global reset to the MAC. Needs to be SW reset if link is up. 1593 1.4.2.2 pgoyette * If link reset is used when link is up, it might reset the PHY when 1594 1.4.2.2 pgoyette * mng is using it. If link is down or the flag to force full link 1595 1.4.2.2 pgoyette * reset is set, then perform link reset. 1596 1.4.2.2 pgoyette */ 1597 1.4.2.2 pgoyette ctrl = IXGBE_CTRL_LNK_RST; 1598 1.4.2.2 pgoyette if (!hw->force_full_reset) { 1599 1.4.2.2 pgoyette hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE); 1600 1.4.2.2 pgoyette if (link_up) 1601 1.4.2.2 pgoyette ctrl = IXGBE_CTRL_RST; 1602 1.4.2.2 pgoyette } 1603 1.4.2.2 pgoyette 1604 1.4.2.2 pgoyette ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 1605 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 1606 1.4.2.2 pgoyette IXGBE_WRITE_FLUSH(hw); 1607 1.4.2.2 pgoyette 1608 1.4.2.2 pgoyette /* Poll for reset bit to self-clear meaning reset is complete */ 1609 1.4.2.2 pgoyette for (i = 0; i < 10; i++) { 1610 1.4.2.2 pgoyette usec_delay(1); 1611 1.4.2.2 pgoyette ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1612 1.4.2.2 pgoyette if (!(ctrl & IXGBE_CTRL_RST_MASK)) 1613 1.4.2.2 pgoyette break; 1614 1.4.2.2 pgoyette } 1615 1.4.2.2 pgoyette 1616 1.4.2.2 pgoyette if (ctrl & IXGBE_CTRL_RST_MASK) { 1617 1.4.2.2 pgoyette status = IXGBE_ERR_RESET_FAILED; 1618 1.4.2.2 pgoyette DEBUGOUT("Reset polling failed to complete.\n"); 1619 1.4.2.2 pgoyette } 1620 1.4.2.2 pgoyette 1621 1.4.2.2 pgoyette msec_delay(50); 1622 1.4.2.2 pgoyette 1623 1.4.2.2 pgoyette /* Double resets are required for recovery from certain error 1624 1.4.2.2 pgoyette * conditions. Between resets, it is necessary to stall to 1625 1.4.2.2 pgoyette * allow time for any pending HW events to complete. 1626 1.4.2.2 pgoyette */ 1627 1.4.2.2 pgoyette if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1628 1.4.2.2 pgoyette hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1629 1.4.2.2 pgoyette goto mac_reset_top; 1630 1.4.2.2 pgoyette } 1631 1.4.2.2 pgoyette 1632 1.4.2.2 pgoyette /* Store the permanent mac address */ 1633 1.4.2.2 pgoyette hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1634 1.4.2.2 pgoyette 1635 1.4.2.2 pgoyette /* Store MAC address from RAR0, clear receive address registers, and 1636 1.4.2.2 pgoyette * clear the multicast table. Also reset num_rar_entries to 128, 1637 1.4.2.2 pgoyette * since we modify this value when programming the SAN MAC address. 1638 1.4.2.2 pgoyette */ 1639 1.4.2.2 pgoyette hw->mac.num_rar_entries = 128; 1640 1.4.2.2 pgoyette hw->mac.ops.init_rx_addrs(hw); 1641 1.4.2.2 pgoyette 1642 1.4.2.2 pgoyette if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) 1643 1.4.2.2 pgoyette ixgbe_setup_mux_ctl(hw); 1644 1.4.2.2 pgoyette 1645 1.4.2.2 pgoyette return status; 1646 1.4.2.2 pgoyette } 1647 1.4.2.2 pgoyette 1648 1.4.2.2 pgoyette /** 1649 1.4.2.2 pgoyette * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. 1650 1.4.2.2 pgoyette * @hw: pointer to hardware structure 1651 1.4.2.2 pgoyette */ 1652 1.4.2.2 pgoyette s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) 1653 1.4.2.2 pgoyette { 1654 1.4.2.2 pgoyette u32 status; 1655 1.4.2.2 pgoyette u16 reg; 1656 1.4.2.2 pgoyette 1657 1.4.2.2 pgoyette status = hw->phy.ops.read_reg(hw, 1658 1.4.2.2 pgoyette IXGBE_MDIO_TX_VENDOR_ALARMS_3, 1659 1.4.2.2 pgoyette IXGBE_MDIO_PMA_PMD_DEV_TYPE, 1660 1.4.2.2 pgoyette ®); 1661 1.4.2.2 pgoyette 1662 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1663 1.4.2.2 pgoyette return status; 1664 1.4.2.2 pgoyette 1665 1.4.2.2 pgoyette /* If PHY FW reset completed bit is set then this is the first 1666 1.4.2.2 pgoyette * SW instance after a power on so the PHY FW must be un-stalled. 1667 1.4.2.2 pgoyette */ 1668 1.4.2.2 pgoyette if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 1669 1.4.2.2 pgoyette status = hw->phy.ops.read_reg(hw, 1670 1.4.2.2 pgoyette IXGBE_MDIO_GLOBAL_RES_PR_10, 1671 1.4.2.2 pgoyette IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1672 1.4.2.2 pgoyette ®); 1673 1.4.2.2 pgoyette 1674 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1675 1.4.2.2 pgoyette return status; 1676 1.4.2.2 pgoyette 1677 1.4.2.2 pgoyette reg &= ~IXGBE_MDIO_POWER_UP_STALL; 1678 1.4.2.2 pgoyette 1679 1.4.2.2 pgoyette status = hw->phy.ops.write_reg(hw, 1680 1.4.2.2 pgoyette IXGBE_MDIO_GLOBAL_RES_PR_10, 1681 1.4.2.2 pgoyette IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1682 1.4.2.2 pgoyette reg); 1683 1.4.2.2 pgoyette 1684 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1685 1.4.2.2 pgoyette return status; 1686 1.4.2.2 pgoyette } 1687 1.4.2.2 pgoyette 1688 1.4.2.2 pgoyette return status; 1689 1.4.2.2 pgoyette } 1690 1.4.2.2 pgoyette 1691 1.4.2.2 pgoyette /** 1692 1.4.2.2 pgoyette * ixgbe_setup_kr_x550em - Configure the KR PHY. 1693 1.4.2.2 pgoyette * @hw: pointer to hardware structure 1694 1.4.2.2 pgoyette * 1695 1.4.2.2 pgoyette * Configures the integrated KR PHY. 1696 1.4.2.2 pgoyette **/ 1697 1.4.2.2 pgoyette s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) 1698 1.4.2.2 pgoyette { 1699 1.4.2.2 pgoyette return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); 1700 1.4.2.2 pgoyette } 1701 1.4.2.2 pgoyette 1702 1.4.2.2 pgoyette /** 1703 1.4.2.2 pgoyette * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP 1704 1.4.2.2 pgoyette * @hw: pointer to hardware structure 1705 1.4.2.2 pgoyette * 1706 1.4.2.2 pgoyette * Configure the external PHY and the integrated KR PHY for SFP support. 1707 1.4.2.2 pgoyette **/ 1708 1.4.2.2 pgoyette s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, 1709 1.4.2.2 pgoyette ixgbe_link_speed speed, 1710 1.4.2.2 pgoyette bool autoneg_wait_to_complete) 1711 1.4.2.2 pgoyette { 1712 1.4.2.2 pgoyette s32 ret_val; 1713 1.4.2.2 pgoyette u16 reg_slice, reg_val; 1714 1.4.2.2 pgoyette bool setup_linear = FALSE; 1715 1.4.2.2 pgoyette UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 1716 1.4.2.2 pgoyette 1717 1.4.2.2 pgoyette /* Check if SFP module is supported and linear */ 1718 1.4.2.2 pgoyette ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1719 1.4.2.2 pgoyette 1720 1.4.2.2 pgoyette /* If no SFP module present, then return success. Return success since 1721 1.4.2.2 pgoyette * there is no reason to configure CS4227 and SFP not present error is 1722 1.4.2.2 pgoyette * not excepted in the setup MAC link flow. 1723 1.4.2.2 pgoyette */ 1724 1.4.2.2 pgoyette if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 1725 1.4.2.2 pgoyette return IXGBE_SUCCESS; 1726 1.4.2.2 pgoyette 1727 1.4.2.2 pgoyette if (ret_val != IXGBE_SUCCESS) 1728 1.4.2.2 pgoyette return ret_val; 1729 1.4.2.2 pgoyette 1730 1.4.2.2 pgoyette if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 1731 1.4.2.2 pgoyette /* Configure CS4227 LINE side to 10G SR. */ 1732 1.4.2.2 pgoyette reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + 1733 1.4.2.2 pgoyette (hw->bus.lan_id << 12); 1734 1.4.2.2 pgoyette reg_val = IXGBE_CS4227_SPEED_10G; 1735 1.4.2.2 pgoyette ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1736 1.4.2.2 pgoyette reg_val); 1737 1.4.2.2 pgoyette 1738 1.4.2.2 pgoyette reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + 1739 1.4.2.2 pgoyette (hw->bus.lan_id << 12); 1740 1.4.2.2 pgoyette reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1741 1.4.2.2 pgoyette ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1742 1.4.2.2 pgoyette reg_val); 1743 1.4.2.2 pgoyette 1744 1.4.2.2 pgoyette /* Configure CS4227 for HOST connection rate then type. */ 1745 1.4.2.2 pgoyette reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + 1746 1.4.2.2 pgoyette (hw->bus.lan_id << 12); 1747 1.4.2.2 pgoyette reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 1748 1.4.2.2 pgoyette IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G; 1749 1.4.2.2 pgoyette ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1750 1.4.2.2 pgoyette reg_val); 1751 1.4.2.2 pgoyette 1752 1.4.2.2 pgoyette reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + 1753 1.4.2.2 pgoyette (hw->bus.lan_id << 12); 1754 1.4.2.2 pgoyette if (setup_linear) 1755 1.4.2.2 pgoyette reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 1756 1.4.2.2 pgoyette else 1757 1.4.2.2 pgoyette reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1758 1.4.2.2 pgoyette ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1759 1.4.2.2 pgoyette reg_val); 1760 1.4.2.2 pgoyette 1761 1.4.2.2 pgoyette /* Setup XFI internal link. */ 1762 1.4.2.2 pgoyette ret_val = ixgbe_setup_ixfi_x550em(hw, &speed); 1763 1.4.2.2 pgoyette } else { 1764 1.4.2.2 pgoyette /* Configure internal PHY for KR/KX. */ 1765 1.4.2.2 pgoyette ixgbe_setup_kr_speed_x550em(hw, speed); 1766 1.4.2.2 pgoyette 1767 1.4.2.2 pgoyette /* Configure CS4227 LINE side to proper mode. */ 1768 1.4.2.2 pgoyette reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + 1769 1.4.2.2 pgoyette (hw->bus.lan_id << 12); 1770 1.4.2.2 pgoyette if (setup_linear) 1771 1.4.2.2 pgoyette reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 1772 1.4.2.2 pgoyette else 1773 1.4.2.2 pgoyette reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1774 1.4.2.2 pgoyette ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1775 1.4.2.2 pgoyette reg_val); 1776 1.4.2.2 pgoyette } 1777 1.4.2.2 pgoyette return ret_val; 1778 1.4.2.2 pgoyette } 1779 1.4.2.2 pgoyette 1780 1.4.2.2 pgoyette /** 1781 1.4.2.2 pgoyette * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. 1782 1.4.2.2 pgoyette * @hw: pointer to hardware structure 1783 1.4.2.2 pgoyette * @speed: the link speed to force 1784 1.4.2.2 pgoyette * 1785 1.4.2.2 pgoyette * Configures the integrated KR PHY to use iXFI mode. Used to connect an 1786 1.4.2.2 pgoyette * internal and external PHY at a specific speed, without autonegotiation. 1787 1.4.2.2 pgoyette **/ 1788 1.4.2.2 pgoyette static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 1789 1.4.2.2 pgoyette { 1790 1.4.2.2 pgoyette s32 status; 1791 1.4.2.2 pgoyette u32 reg_val; 1792 1.4.2.2 pgoyette 1793 1.4.2.2 pgoyette /* Disable AN and force speed to 10G Serial. */ 1794 1.4.2.2 pgoyette status = ixgbe_read_iosf_sb_reg_x550(hw, 1795 1.4.2.2 pgoyette IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1796 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1797 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1798 1.4.2.2 pgoyette return status; 1799 1.4.2.2 pgoyette 1800 1.4.2.2 pgoyette reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1801 1.4.2.2 pgoyette reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1802 1.4.2.2 pgoyette 1803 1.4.2.2 pgoyette /* Select forced link speed for internal PHY. */ 1804 1.4.2.2 pgoyette switch (*speed) { 1805 1.4.2.2 pgoyette case IXGBE_LINK_SPEED_10GB_FULL: 1806 1.4.2.2 pgoyette reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 1807 1.4.2.2 pgoyette break; 1808 1.4.2.2 pgoyette case IXGBE_LINK_SPEED_1GB_FULL: 1809 1.4.2.2 pgoyette reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1810 1.4.2.2 pgoyette break; 1811 1.4.2.2 pgoyette default: 1812 1.4.2.2 pgoyette /* Other link speeds are not supported by internal KR PHY. */ 1813 1.4.2.2 pgoyette return IXGBE_ERR_LINK_SETUP; 1814 1.4.2.2 pgoyette } 1815 1.4.2.2 pgoyette 1816 1.4.2.2 pgoyette status = ixgbe_write_iosf_sb_reg_x550(hw, 1817 1.4.2.2 pgoyette IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1818 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1819 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1820 1.4.2.2 pgoyette return status; 1821 1.4.2.2 pgoyette 1822 1.4.2.2 pgoyette /* Disable training protocol FSM. */ 1823 1.4.2.2 pgoyette status = ixgbe_read_iosf_sb_reg_x550(hw, 1824 1.4.2.2 pgoyette IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1825 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1826 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1827 1.4.2.2 pgoyette return status; 1828 1.4.2.2 pgoyette reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; 1829 1.4.2.2 pgoyette status = ixgbe_write_iosf_sb_reg_x550(hw, 1830 1.4.2.2 pgoyette IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1831 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1832 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1833 1.4.2.2 pgoyette return status; 1834 1.4.2.2 pgoyette 1835 1.4.2.2 pgoyette /* Disable Flex from training TXFFE. */ 1836 1.4.2.2 pgoyette status = ixgbe_read_iosf_sb_reg_x550(hw, 1837 1.4.2.2 pgoyette IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1838 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1839 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1840 1.4.2.2 pgoyette return status; 1841 1.4.2.2 pgoyette reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1842 1.4.2.2 pgoyette reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1843 1.4.2.2 pgoyette reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1844 1.4.2.2 pgoyette status = ixgbe_write_iosf_sb_reg_x550(hw, 1845 1.4.2.2 pgoyette IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1846 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1847 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1848 1.4.2.2 pgoyette return status; 1849 1.4.2.2 pgoyette status = ixgbe_read_iosf_sb_reg_x550(hw, 1850 1.4.2.2 pgoyette IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1851 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1852 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1853 1.4.2.2 pgoyette return status; 1854 1.4.2.2 pgoyette reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1855 1.4.2.2 pgoyette reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1856 1.4.2.2 pgoyette reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1857 1.4.2.2 pgoyette status = ixgbe_write_iosf_sb_reg_x550(hw, 1858 1.4.2.2 pgoyette IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1859 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1860 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1861 1.4.2.2 pgoyette return status; 1862 1.4.2.2 pgoyette 1863 1.4.2.2 pgoyette /* Enable override for coefficients. */ 1864 1.4.2.2 pgoyette status = ixgbe_read_iosf_sb_reg_x550(hw, 1865 1.4.2.2 pgoyette IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1866 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1867 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1868 1.4.2.2 pgoyette return status; 1869 1.4.2.2 pgoyette reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; 1870 1.4.2.2 pgoyette reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; 1871 1.4.2.2 pgoyette reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; 1872 1.4.2.2 pgoyette reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; 1873 1.4.2.2 pgoyette status = ixgbe_write_iosf_sb_reg_x550(hw, 1874 1.4.2.2 pgoyette IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1875 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1876 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1877 1.4.2.2 pgoyette return status; 1878 1.4.2.2 pgoyette 1879 1.4.2.2 pgoyette /* Toggle port SW reset by AN reset. */ 1880 1.4.2.2 pgoyette status = ixgbe_read_iosf_sb_reg_x550(hw, 1881 1.4.2.2 pgoyette IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1882 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1883 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1884 1.4.2.2 pgoyette return status; 1885 1.4.2.2 pgoyette reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1886 1.4.2.2 pgoyette status = ixgbe_write_iosf_sb_reg_x550(hw, 1887 1.4.2.2 pgoyette IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1888 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1889 1.4.2.2 pgoyette 1890 1.4.2.2 pgoyette return status; 1891 1.4.2.2 pgoyette } 1892 1.4.2.2 pgoyette 1893 1.4.2.2 pgoyette /** 1894 1.4.2.2 pgoyette * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status 1895 1.4.2.2 pgoyette * @hw: address of hardware structure 1896 1.4.2.2 pgoyette * @link_up: address of boolean to indicate link status 1897 1.4.2.2 pgoyette * 1898 1.4.2.2 pgoyette * Returns error code if unable to get link status. 1899 1.4.2.2 pgoyette */ 1900 1.4.2.2 pgoyette static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up) 1901 1.4.2.2 pgoyette { 1902 1.4.2.2 pgoyette u32 ret; 1903 1.4.2.2 pgoyette u16 autoneg_status; 1904 1.4.2.2 pgoyette 1905 1.4.2.2 pgoyette *link_up = FALSE; 1906 1.4.2.2 pgoyette 1907 1.4.2.2 pgoyette /* read this twice back to back to indicate current status */ 1908 1.4.2.2 pgoyette ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 1909 1.4.2.2 pgoyette IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1910 1.4.2.2 pgoyette &autoneg_status); 1911 1.4.2.2 pgoyette if (ret != IXGBE_SUCCESS) 1912 1.4.2.2 pgoyette return ret; 1913 1.4.2.2 pgoyette 1914 1.4.2.2 pgoyette ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 1915 1.4.2.2 pgoyette IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1916 1.4.2.2 pgoyette &autoneg_status); 1917 1.4.2.2 pgoyette if (ret != IXGBE_SUCCESS) 1918 1.4.2.2 pgoyette return ret; 1919 1.4.2.2 pgoyette 1920 1.4.2.2 pgoyette *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS); 1921 1.4.2.2 pgoyette 1922 1.4.2.2 pgoyette return IXGBE_SUCCESS; 1923 1.4.2.2 pgoyette } 1924 1.4.2.2 pgoyette 1925 1.4.2.2 pgoyette /** 1926 1.4.2.2 pgoyette * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link 1927 1.4.2.2 pgoyette * @hw: point to hardware structure 1928 1.4.2.2 pgoyette * 1929 1.4.2.2 pgoyette * Configures the link between the integrated KR PHY and the external X557 PHY 1930 1.4.2.2 pgoyette * The driver will call this function when it gets a link status change 1931 1.4.2.2 pgoyette * interrupt from the X557 PHY. This function configures the link speed 1932 1.4.2.2 pgoyette * between the PHYs to match the link speed of the BASE-T link. 1933 1.4.2.2 pgoyette * 1934 1.4.2.2 pgoyette * A return of a non-zero value indicates an error, and the base driver should 1935 1.4.2.2 pgoyette * not report link up. 1936 1.4.2.2 pgoyette */ 1937 1.4.2.2 pgoyette s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw) 1938 1.4.2.2 pgoyette { 1939 1.4.2.2 pgoyette ixgbe_link_speed force_speed; 1940 1.4.2.2 pgoyette bool link_up; 1941 1.4.2.2 pgoyette u32 status; 1942 1.4.2.2 pgoyette u16 speed; 1943 1.4.2.2 pgoyette 1944 1.4.2.2 pgoyette if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 1945 1.4.2.2 pgoyette return IXGBE_ERR_CONFIG; 1946 1.4.2.2 pgoyette 1947 1.4.2.2 pgoyette /* If link is not up, then there is no setup necessary so return */ 1948 1.4.2.2 pgoyette status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 1949 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1950 1.4.2.2 pgoyette return status; 1951 1.4.2.2 pgoyette 1952 1.4.2.2 pgoyette if (!link_up) 1953 1.4.2.2 pgoyette return IXGBE_SUCCESS; 1954 1.4.2.2 pgoyette 1955 1.4.2.2 pgoyette status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 1956 1.4.2.2 pgoyette IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1957 1.4.2.2 pgoyette &speed); 1958 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1959 1.4.2.2 pgoyette return status; 1960 1.4.2.2 pgoyette 1961 1.4.2.2 pgoyette /* If link is not still up, then no setup is necessary so return */ 1962 1.4.2.2 pgoyette status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 1963 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 1964 1.4.2.2 pgoyette return status; 1965 1.4.2.2 pgoyette if (!link_up) 1966 1.4.2.2 pgoyette return IXGBE_SUCCESS; 1967 1.4.2.2 pgoyette 1968 1.4.2.2 pgoyette /* clear everything but the speed and duplex bits */ 1969 1.4.2.2 pgoyette speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK; 1970 1.4.2.2 pgoyette 1971 1.4.2.2 pgoyette switch (speed) { 1972 1.4.2.2 pgoyette case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL: 1973 1.4.2.2 pgoyette force_speed = IXGBE_LINK_SPEED_10GB_FULL; 1974 1.4.2.2 pgoyette break; 1975 1.4.2.2 pgoyette case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL: 1976 1.4.2.2 pgoyette force_speed = IXGBE_LINK_SPEED_1GB_FULL; 1977 1.4.2.2 pgoyette break; 1978 1.4.2.2 pgoyette default: 1979 1.4.2.2 pgoyette /* Internal PHY does not support anything else */ 1980 1.4.2.2 pgoyette return IXGBE_ERR_INVALID_LINK_SETTINGS; 1981 1.4.2.2 pgoyette } 1982 1.4.2.2 pgoyette 1983 1.4.2.2 pgoyette return ixgbe_setup_ixfi_x550em(hw, &force_speed); 1984 1.4.2.2 pgoyette } 1985 1.4.2.2 pgoyette 1986 1.4.2.2 pgoyette /** 1987 1.4.2.2 pgoyette * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback. 1988 1.4.2.2 pgoyette * @hw: pointer to hardware structure 1989 1.4.2.2 pgoyette * 1990 1.4.2.2 pgoyette * Configures the integrated KR PHY to use internal loopback mode. 1991 1.4.2.2 pgoyette **/ 1992 1.4.2.2 pgoyette s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw) 1993 1.4.2.2 pgoyette { 1994 1.4.2.2 pgoyette s32 status; 1995 1.4.2.2 pgoyette u32 reg_val; 1996 1.4.2.2 pgoyette 1997 1.4.2.2 pgoyette /* Disable AN and force speed to 10G Serial. */ 1998 1.4.2.2 pgoyette status = ixgbe_read_iosf_sb_reg_x550(hw, 1999 1.4.2.2 pgoyette IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2000 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2001 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 2002 1.4.2.2 pgoyette return status; 2003 1.4.2.2 pgoyette reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2004 1.4.2.2 pgoyette reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 2005 1.4.2.2 pgoyette reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 2006 1.4.2.2 pgoyette status = ixgbe_write_iosf_sb_reg_x550(hw, 2007 1.4.2.2 pgoyette IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2008 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2009 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 2010 1.4.2.2 pgoyette return status; 2011 1.4.2.2 pgoyette 2012 1.4.2.2 pgoyette /* Set near-end loopback clocks. */ 2013 1.4.2.2 pgoyette status = ixgbe_read_iosf_sb_reg_x550(hw, 2014 1.4.2.2 pgoyette IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id), 2015 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2016 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 2017 1.4.2.2 pgoyette return status; 2018 1.4.2.2 pgoyette reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B; 2019 1.4.2.2 pgoyette reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS; 2020 1.4.2.2 pgoyette status = ixgbe_write_iosf_sb_reg_x550(hw, 2021 1.4.2.2 pgoyette IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id), 2022 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2023 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 2024 1.4.2.2 pgoyette return status; 2025 1.4.2.2 pgoyette 2026 1.4.2.2 pgoyette /* Set loopback enable. */ 2027 1.4.2.2 pgoyette status = ixgbe_read_iosf_sb_reg_x550(hw, 2028 1.4.2.2 pgoyette IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id), 2029 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2030 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 2031 1.4.2.2 pgoyette return status; 2032 1.4.2.2 pgoyette reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK; 2033 1.4.2.2 pgoyette status = ixgbe_write_iosf_sb_reg_x550(hw, 2034 1.4.2.2 pgoyette IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id), 2035 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2036 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 2037 1.4.2.2 pgoyette return status; 2038 1.4.2.2 pgoyette 2039 1.4.2.2 pgoyette /* Training bypass. */ 2040 1.4.2.2 pgoyette status = ixgbe_read_iosf_sb_reg_x550(hw, 2041 1.4.2.2 pgoyette IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 2042 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2043 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 2044 1.4.2.2 pgoyette return status; 2045 1.4.2.2 pgoyette reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS; 2046 1.4.2.2 pgoyette status = ixgbe_write_iosf_sb_reg_x550(hw, 2047 1.4.2.2 pgoyette IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 2048 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2049 1.4.2.2 pgoyette 2050 1.4.2.2 pgoyette return status; 2051 1.4.2.2 pgoyette } 2052 1.4.2.2 pgoyette 2053 1.4.2.2 pgoyette /** 2054 1.4.2.2 pgoyette * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 2055 1.4.2.2 pgoyette * assuming that the semaphore is already obtained. 2056 1.4.2.2 pgoyette * @hw: pointer to hardware structure 2057 1.4.2.2 pgoyette * @offset: offset of word in the EEPROM to read 2058 1.4.2.2 pgoyette * @data: word read from the EEPROM 2059 1.4.2.2 pgoyette * 2060 1.4.2.2 pgoyette * Reads a 16 bit word from the EEPROM using the hostif. 2061 1.4.2.2 pgoyette **/ 2062 1.4.2.2 pgoyette s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 2063 1.4.2.2 pgoyette u16 *data) 2064 1.4.2.2 pgoyette { 2065 1.4.2.2 pgoyette s32 status; 2066 1.4.2.2 pgoyette struct ixgbe_hic_read_shadow_ram buffer; 2067 1.4.2.2 pgoyette 2068 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_read_ee_hostif_data_X550"); 2069 1.4.2.2 pgoyette buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 2070 1.4.2.2 pgoyette buffer.hdr.req.buf_lenh = 0; 2071 1.4.2.2 pgoyette buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 2072 1.4.2.2 pgoyette buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 2073 1.4.2.2 pgoyette 2074 1.4.2.2 pgoyette /* convert offset from words to bytes */ 2075 1.4.2.2 pgoyette buffer.address = IXGBE_CPU_TO_BE32(offset * 2); 2076 1.4.2.2 pgoyette /* one word */ 2077 1.4.2.2 pgoyette buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16)); 2078 1.4.2.2 pgoyette 2079 1.4.2.2 pgoyette status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 2080 1.4.2.2 pgoyette sizeof(buffer), 2081 1.4.2.2 pgoyette IXGBE_HI_COMMAND_TIMEOUT, FALSE); 2082 1.4.2.2 pgoyette 2083 1.4.2.2 pgoyette if (status) 2084 1.4.2.2 pgoyette return status; 2085 1.4.2.2 pgoyette 2086 1.4.2.2 pgoyette *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 2087 1.4.2.2 pgoyette FW_NVM_DATA_OFFSET); 2088 1.4.2.2 pgoyette 2089 1.4.2.2 pgoyette return 0; 2090 1.4.2.2 pgoyette } 2091 1.4.2.2 pgoyette 2092 1.4.2.2 pgoyette /** 2093 1.4.2.2 pgoyette * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 2094 1.4.2.2 pgoyette * @hw: pointer to hardware structure 2095 1.4.2.2 pgoyette * @offset: offset of word in the EEPROM to read 2096 1.4.2.2 pgoyette * @data: word read from the EEPROM 2097 1.4.2.2 pgoyette * 2098 1.4.2.2 pgoyette * Reads a 16 bit word from the EEPROM using the hostif. 2099 1.4.2.2 pgoyette **/ 2100 1.4.2.2 pgoyette s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, 2101 1.4.2.2 pgoyette u16 *data) 2102 1.4.2.2 pgoyette { 2103 1.4.2.2 pgoyette s32 status = IXGBE_SUCCESS; 2104 1.4.2.2 pgoyette 2105 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_read_ee_hostif_X550"); 2106 1.4.2.2 pgoyette 2107 1.4.2.2 pgoyette if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 2108 1.4.2.2 pgoyette IXGBE_SUCCESS) { 2109 1.4.2.2 pgoyette status = ixgbe_read_ee_hostif_data_X550(hw, offset, data); 2110 1.4.2.2 pgoyette hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2111 1.4.2.2 pgoyette } else { 2112 1.4.2.2 pgoyette status = IXGBE_ERR_SWFW_SYNC; 2113 1.4.2.2 pgoyette } 2114 1.4.2.2 pgoyette 2115 1.4.2.2 pgoyette return status; 2116 1.4.2.2 pgoyette } 2117 1.4.2.2 pgoyette 2118 1.4.2.2 pgoyette /** 2119 1.4.2.2 pgoyette * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif 2120 1.4.2.2 pgoyette * @hw: pointer to hardware structure 2121 1.4.2.2 pgoyette * @offset: offset of word in the EEPROM to read 2122 1.4.2.2 pgoyette * @words: number of words 2123 1.4.2.2 pgoyette * @data: word(s) read from the EEPROM 2124 1.4.2.2 pgoyette * 2125 1.4.2.2 pgoyette * Reads a 16 bit word(s) from the EEPROM using the hostif. 2126 1.4.2.2 pgoyette **/ 2127 1.4.2.2 pgoyette s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 2128 1.4.2.2 pgoyette u16 offset, u16 words, u16 *data) 2129 1.4.2.2 pgoyette { 2130 1.4.2.2 pgoyette struct ixgbe_hic_read_shadow_ram buffer; 2131 1.4.2.2 pgoyette u32 current_word = 0; 2132 1.4.2.2 pgoyette u16 words_to_read; 2133 1.4.2.2 pgoyette s32 status; 2134 1.4.2.2 pgoyette u32 i; 2135 1.4.2.2 pgoyette 2136 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550"); 2137 1.4.2.2 pgoyette 2138 1.4.2.2 pgoyette /* Take semaphore for the entire operation. */ 2139 1.4.2.2 pgoyette status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2140 1.4.2.2 pgoyette if (status) { 2141 1.4.2.2 pgoyette DEBUGOUT("EEPROM read buffer - semaphore failed\n"); 2142 1.4.2.2 pgoyette return status; 2143 1.4.2.2 pgoyette } 2144 1.4.2.2 pgoyette while (words) { 2145 1.4.2.2 pgoyette if (words > FW_MAX_READ_BUFFER_SIZE / 2) 2146 1.4.2.2 pgoyette words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 2147 1.4.2.2 pgoyette else 2148 1.4.2.2 pgoyette words_to_read = words; 2149 1.4.2.2 pgoyette 2150 1.4.2.2 pgoyette buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 2151 1.4.2.2 pgoyette buffer.hdr.req.buf_lenh = 0; 2152 1.4.2.2 pgoyette buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 2153 1.4.2.2 pgoyette buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 2154 1.4.2.2 pgoyette 2155 1.4.2.2 pgoyette /* convert offset from words to bytes */ 2156 1.4.2.2 pgoyette buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2); 2157 1.4.2.2 pgoyette buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2); 2158 1.4.2.2 pgoyette 2159 1.4.2.2 pgoyette status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 2160 1.4.2.2 pgoyette sizeof(buffer), 2161 1.4.2.2 pgoyette IXGBE_HI_COMMAND_TIMEOUT, 2162 1.4.2.2 pgoyette FALSE); 2163 1.4.2.2 pgoyette 2164 1.4.2.2 pgoyette if (status) { 2165 1.4.2.2 pgoyette DEBUGOUT("Host interface command failed\n"); 2166 1.4.2.2 pgoyette goto out; 2167 1.4.2.2 pgoyette } 2168 1.4.2.2 pgoyette 2169 1.4.2.2 pgoyette for (i = 0; i < words_to_read; i++) { 2170 1.4.2.2 pgoyette u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + 2171 1.4.2.2 pgoyette 2 * i; 2172 1.4.2.2 pgoyette u32 value = IXGBE_READ_REG(hw, reg); 2173 1.4.2.2 pgoyette 2174 1.4.2.2 pgoyette data[current_word] = (u16)(value & 0xffff); 2175 1.4.2.2 pgoyette current_word++; 2176 1.4.2.2 pgoyette i++; 2177 1.4.2.2 pgoyette if (i < words_to_read) { 2178 1.4.2.2 pgoyette value >>= 16; 2179 1.4.2.2 pgoyette data[current_word] = (u16)(value & 0xffff); 2180 1.4.2.2 pgoyette current_word++; 2181 1.4.2.2 pgoyette } 2182 1.4.2.2 pgoyette } 2183 1.4.2.2 pgoyette words -= words_to_read; 2184 1.4.2.2 pgoyette } 2185 1.4.2.2 pgoyette 2186 1.4.2.2 pgoyette out: 2187 1.4.2.2 pgoyette hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2188 1.4.2.2 pgoyette return status; 2189 1.4.2.2 pgoyette } 2190 1.4.2.2 pgoyette 2191 1.4.2.2 pgoyette /** 2192 1.4.2.2 pgoyette * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 2193 1.4.2.2 pgoyette * @hw: pointer to hardware structure 2194 1.4.2.2 pgoyette * @offset: offset of word in the EEPROM to write 2195 1.4.2.2 pgoyette * @data: word write to the EEPROM 2196 1.4.2.2 pgoyette * 2197 1.4.2.2 pgoyette * Write a 16 bit word to the EEPROM using the hostif. 2198 1.4.2.2 pgoyette **/ 2199 1.4.2.2 pgoyette s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 2200 1.4.2.2 pgoyette u16 data) 2201 1.4.2.2 pgoyette { 2202 1.4.2.2 pgoyette s32 status; 2203 1.4.2.2 pgoyette struct ixgbe_hic_write_shadow_ram buffer; 2204 1.4.2.2 pgoyette 2205 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_write_ee_hostif_data_X550"); 2206 1.4.2.2 pgoyette 2207 1.4.2.2 pgoyette buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; 2208 1.4.2.2 pgoyette buffer.hdr.req.buf_lenh = 0; 2209 1.4.2.2 pgoyette buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; 2210 1.4.2.2 pgoyette buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 2211 1.4.2.2 pgoyette 2212 1.4.2.2 pgoyette /* one word */ 2213 1.4.2.2 pgoyette buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16)); 2214 1.4.2.2 pgoyette buffer.data = data; 2215 1.4.2.2 pgoyette buffer.address = IXGBE_CPU_TO_BE32(offset * 2); 2216 1.4.2.2 pgoyette 2217 1.4.2.2 pgoyette status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 2218 1.4.2.2 pgoyette sizeof(buffer), 2219 1.4.2.2 pgoyette IXGBE_HI_COMMAND_TIMEOUT, FALSE); 2220 1.4.2.2 pgoyette 2221 1.4.2.2 pgoyette return status; 2222 1.4.2.2 pgoyette } 2223 1.4.2.2 pgoyette 2224 1.4.2.2 pgoyette /** 2225 1.4.2.2 pgoyette * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 2226 1.4.2.2 pgoyette * @hw: pointer to hardware structure 2227 1.4.2.2 pgoyette * @offset: offset of word in the EEPROM to write 2228 1.4.2.2 pgoyette * @data: word write to the EEPROM 2229 1.4.2.2 pgoyette * 2230 1.4.2.2 pgoyette * Write a 16 bit word to the EEPROM using the hostif. 2231 1.4.2.2 pgoyette **/ 2232 1.4.2.2 pgoyette s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, 2233 1.4.2.2 pgoyette u16 data) 2234 1.4.2.2 pgoyette { 2235 1.4.2.2 pgoyette s32 status = IXGBE_SUCCESS; 2236 1.4.2.2 pgoyette 2237 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_write_ee_hostif_X550"); 2238 1.4.2.2 pgoyette 2239 1.4.2.2 pgoyette if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 2240 1.4.2.2 pgoyette IXGBE_SUCCESS) { 2241 1.4.2.2 pgoyette status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); 2242 1.4.2.2 pgoyette hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2243 1.4.2.2 pgoyette } else { 2244 1.4.2.2 pgoyette DEBUGOUT("write ee hostif failed to get semaphore"); 2245 1.4.2.2 pgoyette status = IXGBE_ERR_SWFW_SYNC; 2246 1.4.2.2 pgoyette } 2247 1.4.2.2 pgoyette 2248 1.4.2.2 pgoyette return status; 2249 1.4.2.2 pgoyette } 2250 1.4.2.2 pgoyette 2251 1.4.2.2 pgoyette /** 2252 1.4.2.2 pgoyette * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif 2253 1.4.2.2 pgoyette * @hw: pointer to hardware structure 2254 1.4.2.2 pgoyette * @offset: offset of word in the EEPROM to write 2255 1.4.2.2 pgoyette * @words: number of words 2256 1.4.2.2 pgoyette * @data: word(s) write to the EEPROM 2257 1.4.2.2 pgoyette * 2258 1.4.2.2 pgoyette * Write a 16 bit word(s) to the EEPROM using the hostif. 2259 1.4.2.2 pgoyette **/ 2260 1.4.2.2 pgoyette s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 2261 1.4.2.2 pgoyette u16 offset, u16 words, u16 *data) 2262 1.4.2.2 pgoyette { 2263 1.4.2.2 pgoyette s32 status = IXGBE_SUCCESS; 2264 1.4.2.2 pgoyette u32 i = 0; 2265 1.4.2.2 pgoyette 2266 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550"); 2267 1.4.2.2 pgoyette 2268 1.4.2.2 pgoyette /* Take semaphore for the entire operation. */ 2269 1.4.2.2 pgoyette status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2270 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) { 2271 1.4.2.2 pgoyette DEBUGOUT("EEPROM write buffer - semaphore failed\n"); 2272 1.4.2.2 pgoyette goto out; 2273 1.4.2.2 pgoyette } 2274 1.4.2.2 pgoyette 2275 1.4.2.2 pgoyette for (i = 0; i < words; i++) { 2276 1.4.2.2 pgoyette status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, 2277 1.4.2.2 pgoyette data[i]); 2278 1.4.2.2 pgoyette 2279 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) { 2280 1.4.2.2 pgoyette DEBUGOUT("Eeprom buffered write failed\n"); 2281 1.4.2.2 pgoyette break; 2282 1.4.2.2 pgoyette } 2283 1.4.2.2 pgoyette } 2284 1.4.2.2 pgoyette 2285 1.4.2.2 pgoyette hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2286 1.4.2.2 pgoyette out: 2287 1.4.2.2 pgoyette 2288 1.4.2.2 pgoyette return status; 2289 1.4.2.2 pgoyette } 2290 1.4.2.2 pgoyette 2291 1.4.2.2 pgoyette /** 2292 1.4.2.2 pgoyette * ixgbe_checksum_ptr_x550 - Checksum one pointer region 2293 1.4.2.2 pgoyette * @hw: pointer to hardware structure 2294 1.4.2.2 pgoyette * @ptr: pointer offset in eeprom 2295 1.4.2.2 pgoyette * @size: size of section pointed by ptr, if 0 first word will be used as size 2296 1.4.2.2 pgoyette * @csum: address of checksum to update 2297 1.4.2.2 pgoyette * 2298 1.4.2.2 pgoyette * Returns error status for any failure 2299 1.4.2.2 pgoyette */ 2300 1.4.2.2 pgoyette static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, 2301 1.4.2.2 pgoyette u16 size, u16 *csum, u16 *buffer, 2302 1.4.2.2 pgoyette u32 buffer_size) 2303 1.4.2.2 pgoyette { 2304 1.4.2.2 pgoyette u16 buf[256]; 2305 1.4.2.2 pgoyette s32 status; 2306 1.4.2.2 pgoyette u16 length, bufsz, i, start; 2307 1.4.2.2 pgoyette u16 *local_buffer; 2308 1.4.2.2 pgoyette 2309 1.4.2.2 pgoyette bufsz = sizeof(buf) / sizeof(buf[0]); 2310 1.4.2.2 pgoyette 2311 1.4.2.2 pgoyette /* Read a chunk at the pointer location */ 2312 1.4.2.2 pgoyette if (!buffer) { 2313 1.4.2.2 pgoyette status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); 2314 1.4.2.2 pgoyette if (status) { 2315 1.4.2.2 pgoyette DEBUGOUT("Failed to read EEPROM image\n"); 2316 1.4.2.2 pgoyette return status; 2317 1.4.2.2 pgoyette } 2318 1.4.2.2 pgoyette local_buffer = buf; 2319 1.4.2.2 pgoyette } else { 2320 1.4.2.2 pgoyette if (buffer_size < ptr) 2321 1.4.2.2 pgoyette return IXGBE_ERR_PARAM; 2322 1.4.2.2 pgoyette local_buffer = &buffer[ptr]; 2323 1.4.2.2 pgoyette } 2324 1.4.2.2 pgoyette 2325 1.4.2.2 pgoyette if (size) { 2326 1.4.2.2 pgoyette start = 0; 2327 1.4.2.2 pgoyette length = size; 2328 1.4.2.2 pgoyette } else { 2329 1.4.2.2 pgoyette start = 1; 2330 1.4.2.2 pgoyette length = local_buffer[0]; 2331 1.4.2.2 pgoyette 2332 1.4.2.2 pgoyette /* Skip pointer section if length is invalid. */ 2333 1.4.2.2 pgoyette if (length == 0xFFFF || length == 0 || 2334 1.4.2.2 pgoyette (ptr + length) >= hw->eeprom.word_size) 2335 1.4.2.2 pgoyette return IXGBE_SUCCESS; 2336 1.4.2.2 pgoyette } 2337 1.4.2.2 pgoyette 2338 1.4.2.2 pgoyette if (buffer && ((u32)start + (u32)length > buffer_size)) 2339 1.4.2.2 pgoyette return IXGBE_ERR_PARAM; 2340 1.4.2.2 pgoyette 2341 1.4.2.2 pgoyette for (i = start; length; i++, length--) { 2342 1.4.2.2 pgoyette if (i == bufsz && !buffer) { 2343 1.4.2.2 pgoyette ptr += bufsz; 2344 1.4.2.2 pgoyette i = 0; 2345 1.4.2.2 pgoyette if (length < bufsz) 2346 1.4.2.2 pgoyette bufsz = length; 2347 1.4.2.2 pgoyette 2348 1.4.2.2 pgoyette /* Read a chunk at the pointer location */ 2349 1.4.2.2 pgoyette status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, 2350 1.4.2.2 pgoyette bufsz, buf); 2351 1.4.2.2 pgoyette if (status) { 2352 1.4.2.2 pgoyette DEBUGOUT("Failed to read EEPROM image\n"); 2353 1.4.2.2 pgoyette return status; 2354 1.4.2.2 pgoyette } 2355 1.4.2.2 pgoyette } 2356 1.4.2.2 pgoyette *csum += local_buffer[i]; 2357 1.4.2.2 pgoyette } 2358 1.4.2.2 pgoyette return IXGBE_SUCCESS; 2359 1.4.2.2 pgoyette } 2360 1.4.2.2 pgoyette 2361 1.4.2.2 pgoyette /** 2362 1.4.2.2 pgoyette * ixgbe_calc_checksum_X550 - Calculates and returns the checksum 2363 1.4.2.2 pgoyette * @hw: pointer to hardware structure 2364 1.4.2.2 pgoyette * @buffer: pointer to buffer containing calculated checksum 2365 1.4.2.2 pgoyette * @buffer_size: size of buffer 2366 1.4.2.2 pgoyette * 2367 1.4.2.2 pgoyette * Returns a negative error code on error, or the 16-bit checksum 2368 1.4.2.2 pgoyette **/ 2369 1.4.2.2 pgoyette s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size) 2370 1.4.2.2 pgoyette { 2371 1.4.2.2 pgoyette u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1]; 2372 1.4.2.2 pgoyette u16 *local_buffer; 2373 1.4.2.2 pgoyette s32 status; 2374 1.4.2.2 pgoyette u16 checksum = 0; 2375 1.4.2.2 pgoyette u16 pointer, i, size; 2376 1.4.2.2 pgoyette 2377 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550"); 2378 1.4.2.2 pgoyette 2379 1.4.2.2 pgoyette hw->eeprom.ops.init_params(hw); 2380 1.4.2.2 pgoyette 2381 1.4.2.2 pgoyette if (!buffer) { 2382 1.4.2.2 pgoyette /* Read pointer area */ 2383 1.4.2.2 pgoyette status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, 2384 1.4.2.2 pgoyette IXGBE_EEPROM_LAST_WORD + 1, 2385 1.4.2.2 pgoyette eeprom_ptrs); 2386 1.4.2.2 pgoyette if (status) { 2387 1.4.2.2 pgoyette DEBUGOUT("Failed to read EEPROM image\n"); 2388 1.4.2.2 pgoyette return status; 2389 1.4.2.2 pgoyette } 2390 1.4.2.2 pgoyette local_buffer = eeprom_ptrs; 2391 1.4.2.2 pgoyette } else { 2392 1.4.2.2 pgoyette if (buffer_size < IXGBE_EEPROM_LAST_WORD) 2393 1.4.2.2 pgoyette return IXGBE_ERR_PARAM; 2394 1.4.2.2 pgoyette local_buffer = buffer; 2395 1.4.2.2 pgoyette } 2396 1.4.2.2 pgoyette 2397 1.4.2.2 pgoyette /* 2398 1.4.2.2 pgoyette * For X550 hardware include 0x0-0x41 in the checksum, skip the 2399 1.4.2.2 pgoyette * checksum word itself 2400 1.4.2.2 pgoyette */ 2401 1.4.2.2 pgoyette for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++) 2402 1.4.2.2 pgoyette if (i != IXGBE_EEPROM_CHECKSUM) 2403 1.4.2.2 pgoyette checksum += local_buffer[i]; 2404 1.4.2.2 pgoyette 2405 1.4.2.2 pgoyette /* 2406 1.4.2.2 pgoyette * Include all data from pointers 0x3, 0x6-0xE. This excludes the 2407 1.4.2.2 pgoyette * FW, PHY module, and PCIe Expansion/Option ROM pointers. 2408 1.4.2.2 pgoyette */ 2409 1.4.2.2 pgoyette for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) { 2410 1.4.2.2 pgoyette if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 2411 1.4.2.2 pgoyette continue; 2412 1.4.2.2 pgoyette 2413 1.4.2.2 pgoyette pointer = local_buffer[i]; 2414 1.4.2.2 pgoyette 2415 1.4.2.2 pgoyette /* Skip pointer section if the pointer is invalid. */ 2416 1.4.2.2 pgoyette if (pointer == 0xFFFF || pointer == 0 || 2417 1.4.2.2 pgoyette pointer >= hw->eeprom.word_size) 2418 1.4.2.2 pgoyette continue; 2419 1.4.2.2 pgoyette 2420 1.4.2.2 pgoyette switch (i) { 2421 1.4.2.2 pgoyette case IXGBE_PCIE_GENERAL_PTR: 2422 1.4.2.2 pgoyette size = IXGBE_IXGBE_PCIE_GENERAL_SIZE; 2423 1.4.2.2 pgoyette break; 2424 1.4.2.2 pgoyette case IXGBE_PCIE_CONFIG0_PTR: 2425 1.4.2.2 pgoyette case IXGBE_PCIE_CONFIG1_PTR: 2426 1.4.2.2 pgoyette size = IXGBE_PCIE_CONFIG_SIZE; 2427 1.4.2.2 pgoyette break; 2428 1.4.2.2 pgoyette default: 2429 1.4.2.2 pgoyette size = 0; 2430 1.4.2.2 pgoyette break; 2431 1.4.2.2 pgoyette } 2432 1.4.2.2 pgoyette 2433 1.4.2.2 pgoyette status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, 2434 1.4.2.2 pgoyette buffer, buffer_size); 2435 1.4.2.2 pgoyette if (status) 2436 1.4.2.2 pgoyette return status; 2437 1.4.2.2 pgoyette } 2438 1.4.2.2 pgoyette 2439 1.4.2.2 pgoyette checksum = (u16)IXGBE_EEPROM_SUM - checksum; 2440 1.4.2.2 pgoyette 2441 1.4.2.2 pgoyette return (s32)checksum; 2442 1.4.2.2 pgoyette } 2443 1.4.2.2 pgoyette 2444 1.4.2.2 pgoyette /** 2445 1.4.2.2 pgoyette * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum 2446 1.4.2.2 pgoyette * @hw: pointer to hardware structure 2447 1.4.2.2 pgoyette * 2448 1.4.2.2 pgoyette * Returns a negative error code on error, or the 16-bit checksum 2449 1.4.2.2 pgoyette **/ 2450 1.4.2.2 pgoyette s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) 2451 1.4.2.2 pgoyette { 2452 1.4.2.2 pgoyette return ixgbe_calc_checksum_X550(hw, NULL, 0); 2453 1.4.2.2 pgoyette } 2454 1.4.2.2 pgoyette 2455 1.4.2.2 pgoyette /** 2456 1.4.2.2 pgoyette * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum 2457 1.4.2.2 pgoyette * @hw: pointer to hardware structure 2458 1.4.2.2 pgoyette * @checksum_val: calculated checksum 2459 1.4.2.2 pgoyette * 2460 1.4.2.2 pgoyette * Performs checksum calculation and validates the EEPROM checksum. If the 2461 1.4.2.2 pgoyette * caller does not need checksum_val, the value can be NULL. 2462 1.4.2.2 pgoyette **/ 2463 1.4.2.2 pgoyette s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val) 2464 1.4.2.2 pgoyette { 2465 1.4.2.2 pgoyette s32 status; 2466 1.4.2.2 pgoyette u16 checksum; 2467 1.4.2.2 pgoyette u16 read_checksum = 0; 2468 1.4.2.2 pgoyette 2469 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550"); 2470 1.4.2.2 pgoyette 2471 1.4.2.2 pgoyette /* Read the first word from the EEPROM. If this times out or fails, do 2472 1.4.2.2 pgoyette * not continue or we could be in for a very long wait while every 2473 1.4.2.2 pgoyette * EEPROM read fails 2474 1.4.2.2 pgoyette */ 2475 1.4.2.2 pgoyette status = hw->eeprom.ops.read(hw, 0, &checksum); 2476 1.4.2.2 pgoyette if (status) { 2477 1.4.2.2 pgoyette DEBUGOUT("EEPROM read failed\n"); 2478 1.4.2.2 pgoyette return status; 2479 1.4.2.2 pgoyette } 2480 1.4.2.2 pgoyette 2481 1.4.2.2 pgoyette status = hw->eeprom.ops.calc_checksum(hw); 2482 1.4.2.2 pgoyette if (status < 0) 2483 1.4.2.2 pgoyette return status; 2484 1.4.2.2 pgoyette 2485 1.4.2.2 pgoyette checksum = (u16)(status & 0xffff); 2486 1.4.2.2 pgoyette 2487 1.4.2.2 pgoyette status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 2488 1.4.2.2 pgoyette &read_checksum); 2489 1.4.2.2 pgoyette if (status) 2490 1.4.2.2 pgoyette return status; 2491 1.4.2.2 pgoyette 2492 1.4.2.2 pgoyette /* Verify read checksum from EEPROM is the same as 2493 1.4.2.2 pgoyette * calculated checksum 2494 1.4.2.2 pgoyette */ 2495 1.4.2.2 pgoyette if (read_checksum != checksum) { 2496 1.4.2.2 pgoyette status = IXGBE_ERR_EEPROM_CHECKSUM; 2497 1.4.2.2 pgoyette ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 2498 1.4.2.2 pgoyette "Invalid EEPROM checksum"); 2499 1.4.2.2 pgoyette } 2500 1.4.2.2 pgoyette 2501 1.4.2.2 pgoyette /* If the user cares, return the calculated checksum */ 2502 1.4.2.2 pgoyette if (checksum_val) 2503 1.4.2.2 pgoyette *checksum_val = checksum; 2504 1.4.2.2 pgoyette 2505 1.4.2.2 pgoyette return status; 2506 1.4.2.2 pgoyette } 2507 1.4.2.2 pgoyette 2508 1.4.2.2 pgoyette /** 2509 1.4.2.2 pgoyette * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash 2510 1.4.2.2 pgoyette * @hw: pointer to hardware structure 2511 1.4.2.2 pgoyette * 2512 1.4.2.2 pgoyette * After writing EEPROM to shadow RAM using EEWR register, software calculates 2513 1.4.2.2 pgoyette * checksum and updates the EEPROM and instructs the hardware to update 2514 1.4.2.2 pgoyette * the flash. 2515 1.4.2.2 pgoyette **/ 2516 1.4.2.2 pgoyette s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) 2517 1.4.2.2 pgoyette { 2518 1.4.2.2 pgoyette s32 status; 2519 1.4.2.2 pgoyette u16 checksum = 0; 2520 1.4.2.2 pgoyette 2521 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_update_eeprom_checksum_X550"); 2522 1.4.2.2 pgoyette 2523 1.4.2.2 pgoyette /* Read the first word from the EEPROM. If this times out or fails, do 2524 1.4.2.2 pgoyette * not continue or we could be in for a very long wait while every 2525 1.4.2.2 pgoyette * EEPROM read fails 2526 1.4.2.2 pgoyette */ 2527 1.4.2.2 pgoyette status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); 2528 1.4.2.2 pgoyette if (status) { 2529 1.4.2.2 pgoyette DEBUGOUT("EEPROM read failed\n"); 2530 1.4.2.2 pgoyette return status; 2531 1.4.2.2 pgoyette } 2532 1.4.2.2 pgoyette 2533 1.4.2.2 pgoyette status = ixgbe_calc_eeprom_checksum_X550(hw); 2534 1.4.2.2 pgoyette if (status < 0) 2535 1.4.2.2 pgoyette return status; 2536 1.4.2.2 pgoyette 2537 1.4.2.2 pgoyette checksum = (u16)(status & 0xffff); 2538 1.4.2.2 pgoyette 2539 1.4.2.2 pgoyette status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 2540 1.4.2.2 pgoyette checksum); 2541 1.4.2.2 pgoyette if (status) 2542 1.4.2.2 pgoyette return status; 2543 1.4.2.2 pgoyette 2544 1.4.2.2 pgoyette status = ixgbe_update_flash_X550(hw); 2545 1.4.2.2 pgoyette 2546 1.4.2.2 pgoyette return status; 2547 1.4.2.2 pgoyette } 2548 1.4.2.2 pgoyette 2549 1.4.2.2 pgoyette /** 2550 1.4.2.2 pgoyette * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device 2551 1.4.2.2 pgoyette * @hw: pointer to hardware structure 2552 1.4.2.2 pgoyette * 2553 1.4.2.2 pgoyette * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash. 2554 1.4.2.2 pgoyette **/ 2555 1.4.2.2 pgoyette s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) 2556 1.4.2.2 pgoyette { 2557 1.4.2.2 pgoyette s32 status = IXGBE_SUCCESS; 2558 1.4.2.2 pgoyette union ixgbe_hic_hdr2 buffer; 2559 1.4.2.2 pgoyette 2560 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_update_flash_X550"); 2561 1.4.2.2 pgoyette 2562 1.4.2.2 pgoyette buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; 2563 1.4.2.2 pgoyette buffer.req.buf_lenh = 0; 2564 1.4.2.2 pgoyette buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; 2565 1.4.2.2 pgoyette buffer.req.checksum = FW_DEFAULT_CHECKSUM; 2566 1.4.2.2 pgoyette 2567 1.4.2.2 pgoyette status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 2568 1.4.2.2 pgoyette sizeof(buffer), 2569 1.4.2.2 pgoyette IXGBE_HI_COMMAND_TIMEOUT, FALSE); 2570 1.4.2.2 pgoyette 2571 1.4.2.2 pgoyette return status; 2572 1.4.2.2 pgoyette } 2573 1.4.2.2 pgoyette 2574 1.4.2.2 pgoyette /** 2575 1.4.2.2 pgoyette * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type 2576 1.4.2.2 pgoyette * @hw: pointer to hardware structure 2577 1.4.2.2 pgoyette * 2578 1.4.2.2 pgoyette * Determines physical layer capabilities of the current configuration. 2579 1.4.2.2 pgoyette **/ 2580 1.4.2.2 pgoyette u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw) 2581 1.4.2.2 pgoyette { 2582 1.4.2.2 pgoyette u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 2583 1.4.2.2 pgoyette u16 ext_ability = 0; 2584 1.4.2.2 pgoyette 2585 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em"); 2586 1.4.2.2 pgoyette 2587 1.4.2.2 pgoyette hw->phy.ops.identify(hw); 2588 1.4.2.2 pgoyette 2589 1.4.2.2 pgoyette switch (hw->phy.type) { 2590 1.4.2.2 pgoyette case ixgbe_phy_x550em_kr: 2591 1.4.2.2 pgoyette physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR | 2592 1.4.2.2 pgoyette IXGBE_PHYSICAL_LAYER_1000BASE_KX; 2593 1.4.2.2 pgoyette break; 2594 1.4.2.2 pgoyette case ixgbe_phy_x550em_kx4: 2595 1.4.2.2 pgoyette physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 | 2596 1.4.2.2 pgoyette IXGBE_PHYSICAL_LAYER_1000BASE_KX; 2597 1.4.2.2 pgoyette break; 2598 1.4.2.2 pgoyette case ixgbe_phy_x550em_ext_t: 2599 1.4.2.2 pgoyette hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 2600 1.4.2.2 pgoyette IXGBE_MDIO_PMA_PMD_DEV_TYPE, 2601 1.4.2.2 pgoyette &ext_ability); 2602 1.4.2.2 pgoyette if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 2603 1.4.2.2 pgoyette physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 2604 1.4.2.2 pgoyette if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 2605 1.4.2.2 pgoyette physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 2606 1.4.2.2 pgoyette break; 2607 1.4.2.2 pgoyette default: 2608 1.4.2.2 pgoyette break; 2609 1.4.2.2 pgoyette } 2610 1.4.2.2 pgoyette 2611 1.4.2.2 pgoyette if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) 2612 1.4.2.2 pgoyette physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw); 2613 1.4.2.2 pgoyette 2614 1.4.2.2 pgoyette return physical_layer; 2615 1.4.2.2 pgoyette } 2616 1.4.2.2 pgoyette 2617 1.4.2.2 pgoyette /** 2618 1.4.2.2 pgoyette * ixgbe_get_bus_info_x550em - Set PCI bus info 2619 1.4.2.2 pgoyette * @hw: pointer to hardware structure 2620 1.4.2.2 pgoyette * 2621 1.4.2.2 pgoyette * Sets bus link width and speed to unknown because X550em is 2622 1.4.2.2 pgoyette * not a PCI device. 2623 1.4.2.2 pgoyette **/ 2624 1.4.2.2 pgoyette s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw) 2625 1.4.2.2 pgoyette { 2626 1.4.2.2 pgoyette 2627 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_get_bus_info_x550em"); 2628 1.4.2.2 pgoyette 2629 1.4.2.2 pgoyette hw->bus.width = ixgbe_bus_width_unknown; 2630 1.4.2.2 pgoyette hw->bus.speed = ixgbe_bus_speed_unknown; 2631 1.4.2.2 pgoyette 2632 1.4.2.2 pgoyette hw->mac.ops.set_lan_id(hw); 2633 1.4.2.2 pgoyette 2634 1.4.2.2 pgoyette return IXGBE_SUCCESS; 2635 1.4.2.2 pgoyette } 2636 1.4.2.2 pgoyette 2637 1.4.2.2 pgoyette /** 2638 1.4.2.2 pgoyette * ixgbe_disable_rx_x550 - Disable RX unit 2639 1.4.2.2 pgoyette * 2640 1.4.2.2 pgoyette * Enables the Rx DMA unit for x550 2641 1.4.2.2 pgoyette **/ 2642 1.4.2.2 pgoyette void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) 2643 1.4.2.2 pgoyette { 2644 1.4.2.2 pgoyette u32 rxctrl, pfdtxgswc; 2645 1.4.2.2 pgoyette s32 status; 2646 1.4.2.2 pgoyette struct ixgbe_hic_disable_rxen fw_cmd; 2647 1.4.2.2 pgoyette 2648 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_disable_rx_dma_x550"); 2649 1.4.2.2 pgoyette 2650 1.4.2.2 pgoyette rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 2651 1.4.2.2 pgoyette if (rxctrl & IXGBE_RXCTRL_RXEN) { 2652 1.4.2.2 pgoyette pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 2653 1.4.2.2 pgoyette if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 2654 1.4.2.2 pgoyette pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 2655 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 2656 1.4.2.2 pgoyette hw->mac.set_lben = TRUE; 2657 1.4.2.2 pgoyette } else { 2658 1.4.2.2 pgoyette hw->mac.set_lben = FALSE; 2659 1.4.2.2 pgoyette } 2660 1.4.2.2 pgoyette 2661 1.4.2.2 pgoyette fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD; 2662 1.4.2.2 pgoyette fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN; 2663 1.4.2.2 pgoyette fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 2664 1.4.2.2 pgoyette fw_cmd.port_number = (u8)hw->bus.lan_id; 2665 1.4.2.2 pgoyette 2666 1.4.2.2 pgoyette status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 2667 1.4.2.2 pgoyette sizeof(struct ixgbe_hic_disable_rxen), 2668 1.4.2.2 pgoyette IXGBE_HI_COMMAND_TIMEOUT, TRUE); 2669 1.4.2.2 pgoyette 2670 1.4.2.2 pgoyette /* If we fail - disable RX using register write */ 2671 1.4.2.2 pgoyette if (status) { 2672 1.4.2.2 pgoyette rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 2673 1.4.2.2 pgoyette if (rxctrl & IXGBE_RXCTRL_RXEN) { 2674 1.4.2.2 pgoyette rxctrl &= ~IXGBE_RXCTRL_RXEN; 2675 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 2676 1.4.2.2 pgoyette } 2677 1.4.2.2 pgoyette } 2678 1.4.2.2 pgoyette } 2679 1.4.2.2 pgoyette } 2680 1.4.2.2 pgoyette 2681 1.4.2.2 pgoyette /** 2682 1.4.2.2 pgoyette * ixgbe_enter_lplu_x550em - Transition to low power states 2683 1.4.2.2 pgoyette * @hw: pointer to hardware structure 2684 1.4.2.2 pgoyette * 2685 1.4.2.2 pgoyette * Configures Low Power Link Up on transition to low power states 2686 1.4.2.2 pgoyette * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the 2687 1.4.2.2 pgoyette * X557 PHY immediately prior to entering LPLU. 2688 1.4.2.2 pgoyette **/ 2689 1.4.2.2 pgoyette s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) 2690 1.4.2.2 pgoyette { 2691 1.4.2.2 pgoyette u16 an_10g_cntl_reg, autoneg_reg, speed; 2692 1.4.2.2 pgoyette s32 status; 2693 1.4.2.2 pgoyette ixgbe_link_speed lcd_speed; 2694 1.4.2.2 pgoyette u32 save_autoneg; 2695 1.4.2.2 pgoyette bool link_up; 2696 1.4.2.2 pgoyette 2697 1.4.2.2 pgoyette /* SW LPLU not required on later HW revisions. */ 2698 1.4.2.2 pgoyette if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))) 2699 1.4.2.2 pgoyette return IXGBE_SUCCESS; 2700 1.4.2.2 pgoyette 2701 1.4.2.2 pgoyette /* If blocked by MNG FW, then don't restart AN */ 2702 1.4.2.2 pgoyette if (ixgbe_check_reset_blocked(hw)) 2703 1.4.2.2 pgoyette return IXGBE_SUCCESS; 2704 1.4.2.2 pgoyette 2705 1.4.2.2 pgoyette status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2706 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 2707 1.4.2.2 pgoyette return status; 2708 1.4.2.2 pgoyette 2709 1.4.2.2 pgoyette status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3); 2710 1.4.2.2 pgoyette 2711 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 2712 1.4.2.2 pgoyette return status; 2713 1.4.2.2 pgoyette 2714 1.4.2.2 pgoyette /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability 2715 1.4.2.2 pgoyette * disabled, then force link down by entering low power mode. 2716 1.4.2.2 pgoyette */ 2717 1.4.2.2 pgoyette if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) || 2718 1.4.2.2 pgoyette !(hw->wol_enabled || ixgbe_mng_present(hw))) 2719 1.4.2.2 pgoyette return ixgbe_set_copper_phy_power(hw, FALSE); 2720 1.4.2.2 pgoyette 2721 1.4.2.2 pgoyette /* Determine LCD */ 2722 1.4.2.2 pgoyette status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed); 2723 1.4.2.2 pgoyette 2724 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 2725 1.4.2.2 pgoyette return status; 2726 1.4.2.2 pgoyette 2727 1.4.2.2 pgoyette /* If no valid LCD link speed, then force link down and exit. */ 2728 1.4.2.2 pgoyette if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN) 2729 1.4.2.2 pgoyette return ixgbe_set_copper_phy_power(hw, FALSE); 2730 1.4.2.2 pgoyette 2731 1.4.2.2 pgoyette status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 2732 1.4.2.2 pgoyette IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2733 1.4.2.2 pgoyette &speed); 2734 1.4.2.2 pgoyette 2735 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 2736 1.4.2.2 pgoyette return status; 2737 1.4.2.2 pgoyette 2738 1.4.2.2 pgoyette /* If no link now, speed is invalid so take link down */ 2739 1.4.2.2 pgoyette status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2740 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 2741 1.4.2.2 pgoyette return ixgbe_set_copper_phy_power(hw, FALSE); 2742 1.4.2.2 pgoyette 2743 1.4.2.2 pgoyette /* clear everything but the speed bits */ 2744 1.4.2.2 pgoyette speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK; 2745 1.4.2.2 pgoyette 2746 1.4.2.2 pgoyette /* If current speed is already LCD, then exit. */ 2747 1.4.2.2 pgoyette if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) && 2748 1.4.2.2 pgoyette (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) || 2749 1.4.2.2 pgoyette ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) && 2750 1.4.2.2 pgoyette (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL))) 2751 1.4.2.2 pgoyette return status; 2752 1.4.2.2 pgoyette 2753 1.4.2.2 pgoyette /* Clear AN completed indication */ 2754 1.4.2.2 pgoyette status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM, 2755 1.4.2.2 pgoyette IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2756 1.4.2.2 pgoyette &autoneg_reg); 2757 1.4.2.2 pgoyette 2758 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 2759 1.4.2.2 pgoyette return status; 2760 1.4.2.2 pgoyette 2761 1.4.2.2 pgoyette status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 2762 1.4.2.2 pgoyette IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2763 1.4.2.2 pgoyette &an_10g_cntl_reg); 2764 1.4.2.2 pgoyette 2765 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 2766 1.4.2.2 pgoyette return status; 2767 1.4.2.2 pgoyette 2768 1.4.2.2 pgoyette status = hw->phy.ops.read_reg(hw, 2769 1.4.2.2 pgoyette IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 2770 1.4.2.2 pgoyette IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2771 1.4.2.2 pgoyette &autoneg_reg); 2772 1.4.2.2 pgoyette 2773 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 2774 1.4.2.2 pgoyette return status; 2775 1.4.2.2 pgoyette 2776 1.4.2.2 pgoyette save_autoneg = hw->phy.autoneg_advertised; 2777 1.4.2.2 pgoyette 2778 1.4.2.2 pgoyette /* Setup link at least common link speed */ 2779 1.4.2.2 pgoyette status = hw->mac.ops.setup_link(hw, lcd_speed, FALSE); 2780 1.4.2.2 pgoyette 2781 1.4.2.2 pgoyette /* restore autoneg from before setting lplu speed */ 2782 1.4.2.2 pgoyette hw->phy.autoneg_advertised = save_autoneg; 2783 1.4.2.2 pgoyette 2784 1.4.2.2 pgoyette return status; 2785 1.4.2.2 pgoyette } 2786 1.4.2.2 pgoyette 2787 1.4.2.2 pgoyette /** 2788 1.4.2.2 pgoyette * ixgbe_get_lcd_x550em - Determine lowest common denominator 2789 1.4.2.2 pgoyette * @hw: pointer to hardware structure 2790 1.4.2.2 pgoyette * @lcd_speed: pointer to lowest common link speed 2791 1.4.2.2 pgoyette * 2792 1.4.2.2 pgoyette * Determine lowest common link speed with link partner. 2793 1.4.2.2 pgoyette **/ 2794 1.4.2.2 pgoyette s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed) 2795 1.4.2.2 pgoyette { 2796 1.4.2.2 pgoyette u16 an_lp_status; 2797 1.4.2.2 pgoyette s32 status; 2798 1.4.2.2 pgoyette u16 word = hw->eeprom.ctrl_word_3; 2799 1.4.2.2 pgoyette 2800 1.4.2.2 pgoyette *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN; 2801 1.4.2.2 pgoyette 2802 1.4.2.2 pgoyette status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS, 2803 1.4.2.2 pgoyette IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2804 1.4.2.2 pgoyette &an_lp_status); 2805 1.4.2.2 pgoyette 2806 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 2807 1.4.2.2 pgoyette return status; 2808 1.4.2.2 pgoyette 2809 1.4.2.2 pgoyette /* If link partner advertised 1G, return 1G */ 2810 1.4.2.2 pgoyette if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) { 2811 1.4.2.2 pgoyette *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL; 2812 1.4.2.2 pgoyette return status; 2813 1.4.2.2 pgoyette } 2814 1.4.2.2 pgoyette 2815 1.4.2.2 pgoyette /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */ 2816 1.4.2.2 pgoyette if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) || 2817 1.4.2.2 pgoyette (word & NVM_INIT_CTRL_3_D10GMP_PORT0)) 2818 1.4.2.2 pgoyette return status; 2819 1.4.2.2 pgoyette 2820 1.4.2.2 pgoyette /* Link partner not capable of lower speeds, return 10G */ 2821 1.4.2.2 pgoyette *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL; 2822 1.4.2.2 pgoyette return status; 2823 1.4.2.2 pgoyette } 2824 1.4.2.2 pgoyette 2825 1.4.2.2 pgoyette /** 2826 1.4.2.2 pgoyette * ixgbe_setup_fc_X550em - Set up flow control 2827 1.4.2.2 pgoyette * @hw: pointer to hardware structure 2828 1.4.2.2 pgoyette * 2829 1.4.2.2 pgoyette * Called at init time to set up flow control. 2830 1.4.2.2 pgoyette **/ 2831 1.4.2.2 pgoyette s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw) 2832 1.4.2.2 pgoyette { 2833 1.4.2.2 pgoyette s32 ret_val = IXGBE_SUCCESS; 2834 1.4.2.2 pgoyette u32 pause, asm_dir, reg_val; 2835 1.4.2.2 pgoyette 2836 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_setup_fc_X550em"); 2837 1.4.2.2 pgoyette 2838 1.4.2.2 pgoyette /* Validate the requested mode */ 2839 1.4.2.2 pgoyette if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 2840 1.4.2.2 pgoyette ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 2841 1.4.2.2 pgoyette "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 2842 1.4.2.2 pgoyette ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2843 1.4.2.2 pgoyette goto out; 2844 1.4.2.2 pgoyette } 2845 1.4.2.2 pgoyette 2846 1.4.2.2 pgoyette /* 10gig parts do not have a word in the EEPROM to determine the 2847 1.4.2.2 pgoyette * default flow control setting, so we explicitly set it to full. 2848 1.4.2.2 pgoyette */ 2849 1.4.2.2 pgoyette if (hw->fc.requested_mode == ixgbe_fc_default) 2850 1.4.2.2 pgoyette hw->fc.requested_mode = ixgbe_fc_full; 2851 1.4.2.2 pgoyette 2852 1.4.2.2 pgoyette /* Determine PAUSE and ASM_DIR bits. */ 2853 1.4.2.2 pgoyette switch (hw->fc.requested_mode) { 2854 1.4.2.2 pgoyette case ixgbe_fc_none: 2855 1.4.2.2 pgoyette pause = 0; 2856 1.4.2.2 pgoyette asm_dir = 0; 2857 1.4.2.2 pgoyette break; 2858 1.4.2.2 pgoyette case ixgbe_fc_tx_pause: 2859 1.4.2.2 pgoyette pause = 0; 2860 1.4.2.2 pgoyette asm_dir = 1; 2861 1.4.2.2 pgoyette break; 2862 1.4.2.2 pgoyette case ixgbe_fc_rx_pause: 2863 1.4.2.2 pgoyette /* Rx Flow control is enabled and Tx Flow control is 2864 1.4.2.2 pgoyette * disabled by software override. Since there really 2865 1.4.2.2 pgoyette * isn't a way to advertise that we are capable of RX 2866 1.4.2.2 pgoyette * Pause ONLY, we will advertise that we support both 2867 1.4.2.2 pgoyette * symmetric and asymmetric Rx PAUSE, as such we fall 2868 1.4.2.2 pgoyette * through to the fc_full statement. Later, we will 2869 1.4.2.2 pgoyette * disable the adapter's ability to send PAUSE frames. 2870 1.4.2.2 pgoyette */ 2871 1.4.2.2 pgoyette case ixgbe_fc_full: 2872 1.4.2.2 pgoyette pause = 1; 2873 1.4.2.2 pgoyette asm_dir = 1; 2874 1.4.2.2 pgoyette break; 2875 1.4.2.2 pgoyette default: 2876 1.4.2.2 pgoyette ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 2877 1.4.2.2 pgoyette "Flow control param set incorrectly\n"); 2878 1.4.2.2 pgoyette ret_val = IXGBE_ERR_CONFIG; 2879 1.4.2.2 pgoyette goto out; 2880 1.4.2.2 pgoyette } 2881 1.4.2.2 pgoyette 2882 1.4.2.2 pgoyette if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) { 2883 1.4.2.2 pgoyette ret_val = ixgbe_read_iosf_sb_reg_x550(hw, 2884 1.4.2.2 pgoyette IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2885 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2886 1.4.2.2 pgoyette if (ret_val != IXGBE_SUCCESS) 2887 1.4.2.2 pgoyette goto out; 2888 1.4.2.2 pgoyette reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 2889 1.4.2.2 pgoyette IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 2890 1.4.2.2 pgoyette if (pause) 2891 1.4.2.2 pgoyette reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 2892 1.4.2.2 pgoyette if (asm_dir) 2893 1.4.2.2 pgoyette reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 2894 1.4.2.2 pgoyette ret_val = ixgbe_write_iosf_sb_reg_x550(hw, 2895 1.4.2.2 pgoyette IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2896 1.4.2.2 pgoyette IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2897 1.4.2.2 pgoyette 2898 1.4.2.2 pgoyette /* This device does not fully support AN. */ 2899 1.4.2.2 pgoyette hw->fc.disable_fc_autoneg = TRUE; 2900 1.4.2.2 pgoyette } 2901 1.4.2.2 pgoyette 2902 1.4.2.2 pgoyette out: 2903 1.4.2.2 pgoyette return ret_val; 2904 1.4.2.2 pgoyette } 2905 1.4.2.2 pgoyette 2906 1.4.2.2 pgoyette /** 2907 1.4.2.2 pgoyette * ixgbe_set_mux - Set mux for port 1 access with CS4227 2908 1.4.2.2 pgoyette * @hw: pointer to hardware structure 2909 1.4.2.2 pgoyette * @state: set mux if 1, clear if 0 2910 1.4.2.2 pgoyette */ 2911 1.4.2.2 pgoyette static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state) 2912 1.4.2.2 pgoyette { 2913 1.4.2.2 pgoyette u32 esdp; 2914 1.4.2.2 pgoyette 2915 1.4.2.2 pgoyette if (!hw->bus.lan_id) 2916 1.4.2.2 pgoyette return; 2917 1.4.2.2 pgoyette esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2918 1.4.2.2 pgoyette if (state) 2919 1.4.2.2 pgoyette esdp |= IXGBE_ESDP_SDP1; 2920 1.4.2.2 pgoyette else 2921 1.4.2.2 pgoyette esdp &= ~IXGBE_ESDP_SDP1; 2922 1.4.2.2 pgoyette IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2923 1.4.2.2 pgoyette IXGBE_WRITE_FLUSH(hw); 2924 1.4.2.2 pgoyette } 2925 1.4.2.2 pgoyette 2926 1.4.2.2 pgoyette /** 2927 1.4.2.2 pgoyette * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore 2928 1.4.2.2 pgoyette * @hw: pointer to hardware structure 2929 1.4.2.2 pgoyette * @mask: Mask to specify which semaphore to acquire 2930 1.4.2.2 pgoyette * 2931 1.4.2.2 pgoyette * Acquires the SWFW semaphore and sets the I2C MUX 2932 1.4.2.2 pgoyette **/ 2933 1.4.2.2 pgoyette s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 2934 1.4.2.2 pgoyette { 2935 1.4.2.2 pgoyette s32 status; 2936 1.4.2.2 pgoyette 2937 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em"); 2938 1.4.2.2 pgoyette 2939 1.4.2.2 pgoyette status = ixgbe_acquire_swfw_sync_X540(hw, mask); 2940 1.4.2.2 pgoyette if (status) 2941 1.4.2.2 pgoyette return status; 2942 1.4.2.2 pgoyette 2943 1.4.2.2 pgoyette if (mask & IXGBE_GSSR_I2C_MASK) 2944 1.4.2.2 pgoyette ixgbe_set_mux(hw, 1); 2945 1.4.2.2 pgoyette 2946 1.4.2.2 pgoyette return IXGBE_SUCCESS; 2947 1.4.2.2 pgoyette } 2948 1.4.2.2 pgoyette 2949 1.4.2.2 pgoyette /** 2950 1.4.2.2 pgoyette * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore 2951 1.4.2.2 pgoyette * @hw: pointer to hardware structure 2952 1.4.2.2 pgoyette * @mask: Mask to specify which semaphore to release 2953 1.4.2.2 pgoyette * 2954 1.4.2.2 pgoyette * Releases the SWFW semaphore and sets the I2C MUX 2955 1.4.2.2 pgoyette **/ 2956 1.4.2.2 pgoyette void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 2957 1.4.2.2 pgoyette { 2958 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_release_swfw_sync_X550em"); 2959 1.4.2.2 pgoyette 2960 1.4.2.2 pgoyette if (mask & IXGBE_GSSR_I2C_MASK) 2961 1.4.2.2 pgoyette ixgbe_set_mux(hw, 0); 2962 1.4.2.2 pgoyette 2963 1.4.2.2 pgoyette ixgbe_release_swfw_sync_X540(hw, mask); 2964 1.4.2.2 pgoyette } 2965 1.4.2.2 pgoyette 2966 1.4.2.2 pgoyette /** 2967 1.4.2.2 pgoyette * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt 2968 1.4.2.2 pgoyette * @hw: pointer to hardware structure 2969 1.4.2.2 pgoyette * 2970 1.4.2.2 pgoyette * Handle external Base T PHY interrupt. If high temperature 2971 1.4.2.2 pgoyette * failure alarm then return error, else if link status change 2972 1.4.2.2 pgoyette * then setup internal/external PHY link 2973 1.4.2.2 pgoyette * 2974 1.4.2.2 pgoyette * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 2975 1.4.2.2 pgoyette * failure alarm, else return PHY access status. 2976 1.4.2.2 pgoyette */ 2977 1.4.2.2 pgoyette s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw) 2978 1.4.2.2 pgoyette { 2979 1.4.2.2 pgoyette bool lsc; 2980 1.4.2.2 pgoyette u32 status; 2981 1.4.2.2 pgoyette 2982 1.4.2.2 pgoyette status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 2983 1.4.2.2 pgoyette 2984 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 2985 1.4.2.2 pgoyette return status; 2986 1.4.2.2 pgoyette 2987 1.4.2.2 pgoyette if (lsc) 2988 1.4.2.2 pgoyette return ixgbe_setup_internal_phy(hw); 2989 1.4.2.2 pgoyette 2990 1.4.2.2 pgoyette return IXGBE_SUCCESS; 2991 1.4.2.2 pgoyette } 2992 1.4.2.2 pgoyette 2993 1.4.2.2 pgoyette /** 2994 1.4.2.2 pgoyette * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed 2995 1.4.2.2 pgoyette * @hw: pointer to hardware structure 2996 1.4.2.2 pgoyette * @speed: new link speed 2997 1.4.2.2 pgoyette * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 2998 1.4.2.2 pgoyette * 2999 1.4.2.2 pgoyette * Setup internal/external PHY link speed based on link speed, then set 3000 1.4.2.2 pgoyette * external PHY auto advertised link speed. 3001 1.4.2.2 pgoyette * 3002 1.4.2.2 pgoyette * Returns error status for any failure 3003 1.4.2.2 pgoyette **/ 3004 1.4.2.2 pgoyette s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, 3005 1.4.2.2 pgoyette ixgbe_link_speed speed, 3006 1.4.2.2 pgoyette bool autoneg_wait_to_complete) 3007 1.4.2.2 pgoyette { 3008 1.4.2.2 pgoyette s32 status; 3009 1.4.2.2 pgoyette ixgbe_link_speed force_speed; 3010 1.4.2.2 pgoyette 3011 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_setup_mac_link_t_X550em"); 3012 1.4.2.2 pgoyette 3013 1.4.2.2 pgoyette /* Setup internal/external PHY link speed to iXFI (10G), unless 3014 1.4.2.2 pgoyette * only 1G is auto advertised then setup KX link. 3015 1.4.2.2 pgoyette */ 3016 1.4.2.2 pgoyette if (speed & IXGBE_LINK_SPEED_10GB_FULL) 3017 1.4.2.2 pgoyette force_speed = IXGBE_LINK_SPEED_10GB_FULL; 3018 1.4.2.2 pgoyette else 3019 1.4.2.2 pgoyette force_speed = IXGBE_LINK_SPEED_1GB_FULL; 3020 1.4.2.2 pgoyette 3021 1.4.2.2 pgoyette /* If internal link mode is XFI, then setup XFI internal link. */ 3022 1.4.2.2 pgoyette if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 3023 1.4.2.2 pgoyette status = ixgbe_setup_ixfi_x550em(hw, &force_speed); 3024 1.4.2.2 pgoyette 3025 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 3026 1.4.2.2 pgoyette return status; 3027 1.4.2.2 pgoyette } 3028 1.4.2.2 pgoyette 3029 1.4.2.2 pgoyette return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); 3030 1.4.2.2 pgoyette } 3031 1.4.2.2 pgoyette 3032 1.4.2.2 pgoyette /** 3033 1.4.2.2 pgoyette * ixgbe_check_link_t_X550em - Determine link and speed status 3034 1.4.2.2 pgoyette * @hw: pointer to hardware structure 3035 1.4.2.2 pgoyette * @speed: pointer to link speed 3036 1.4.2.2 pgoyette * @link_up: TRUE when link is up 3037 1.4.2.2 pgoyette * @link_up_wait_to_complete: bool used to wait for link up or not 3038 1.4.2.2 pgoyette * 3039 1.4.2.2 pgoyette * Check that both the MAC and X557 external PHY have link. 3040 1.4.2.2 pgoyette **/ 3041 1.4.2.2 pgoyette s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3042 1.4.2.2 pgoyette bool *link_up, bool link_up_wait_to_complete) 3043 1.4.2.2 pgoyette { 3044 1.4.2.2 pgoyette u32 status; 3045 1.4.2.2 pgoyette u16 autoneg_status; 3046 1.4.2.2 pgoyette 3047 1.4.2.2 pgoyette if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 3048 1.4.2.2 pgoyette return IXGBE_ERR_CONFIG; 3049 1.4.2.2 pgoyette 3050 1.4.2.2 pgoyette status = ixgbe_check_mac_link_generic(hw, speed, link_up, 3051 1.4.2.2 pgoyette link_up_wait_to_complete); 3052 1.4.2.2 pgoyette 3053 1.4.2.2 pgoyette /* If check link fails or MAC link is not up, then return */ 3054 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS || !(*link_up)) 3055 1.4.2.2 pgoyette return status; 3056 1.4.2.2 pgoyette 3057 1.4.2.2 pgoyette /* MAC link is up, so check external PHY link. 3058 1.4.2.2 pgoyette * Read this twice back to back to indicate current status. 3059 1.4.2.2 pgoyette */ 3060 1.4.2.2 pgoyette status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 3061 1.4.2.2 pgoyette IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3062 1.4.2.2 pgoyette &autoneg_status); 3063 1.4.2.2 pgoyette 3064 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 3065 1.4.2.2 pgoyette return status; 3066 1.4.2.2 pgoyette 3067 1.4.2.2 pgoyette status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 3068 1.4.2.2 pgoyette IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3069 1.4.2.2 pgoyette &autoneg_status); 3070 1.4.2.2 pgoyette 3071 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 3072 1.4.2.2 pgoyette return status; 3073 1.4.2.2 pgoyette 3074 1.4.2.2 pgoyette /* If external PHY link is not up, then indicate link not up */ 3075 1.4.2.2 pgoyette if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) 3076 1.4.2.2 pgoyette *link_up = FALSE; 3077 1.4.2.2 pgoyette 3078 1.4.2.2 pgoyette return IXGBE_SUCCESS; 3079 1.4.2.2 pgoyette } 3080 1.4.2.2 pgoyette 3081 1.4.2.2 pgoyette /** 3082 1.4.2.2 pgoyette * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI 3083 1.4.2.2 pgoyette * @hw: pointer to hardware structure 3084 1.4.2.2 pgoyette **/ 3085 1.4.2.2 pgoyette s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw) 3086 1.4.2.2 pgoyette { 3087 1.4.2.2 pgoyette s32 status; 3088 1.4.2.2 pgoyette 3089 1.4.2.2 pgoyette status = ixgbe_reset_phy_generic(hw); 3090 1.4.2.2 pgoyette 3091 1.4.2.2 pgoyette if (status != IXGBE_SUCCESS) 3092 1.4.2.2 pgoyette return status; 3093 1.4.2.2 pgoyette 3094 1.4.2.2 pgoyette /* Configure Link Status Alarm and Temperature Threshold interrupts */ 3095 1.4.2.2 pgoyette return ixgbe_enable_lasi_ext_t_x550em(hw); 3096 1.4.2.2 pgoyette } 3097 1.4.2.2 pgoyette 3098 1.4.2.2 pgoyette /** 3099 1.4.2.2 pgoyette * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs. 3100 1.4.2.2 pgoyette * @hw: pointer to hardware structure 3101 1.4.2.2 pgoyette * @led_idx: led number to turn on 3102 1.4.2.2 pgoyette **/ 3103 1.4.2.2 pgoyette s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx) 3104 1.4.2.2 pgoyette { 3105 1.4.2.2 pgoyette u16 phy_data; 3106 1.4.2.2 pgoyette 3107 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_led_on_t_X550em"); 3108 1.4.2.2 pgoyette 3109 1.4.2.2 pgoyette if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 3110 1.4.2.2 pgoyette return IXGBE_ERR_PARAM; 3111 1.4.2.2 pgoyette 3112 1.4.2.2 pgoyette /* To turn on the LED, set mode to ON. */ 3113 1.4.2.2 pgoyette ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 3114 1.4.2.2 pgoyette IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data); 3115 1.4.2.2 pgoyette phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK; 3116 1.4.2.2 pgoyette ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 3117 1.4.2.2 pgoyette IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data); 3118 1.4.2.2 pgoyette 3119 1.4.2.2 pgoyette return IXGBE_SUCCESS; 3120 1.4.2.2 pgoyette } 3121 1.4.2.2 pgoyette 3122 1.4.2.2 pgoyette /** 3123 1.4.2.2 pgoyette * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs. 3124 1.4.2.2 pgoyette * @hw: pointer to hardware structure 3125 1.4.2.2 pgoyette * @led_idx: led number to turn off 3126 1.4.2.2 pgoyette **/ 3127 1.4.2.2 pgoyette s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx) 3128 1.4.2.2 pgoyette { 3129 1.4.2.2 pgoyette u16 phy_data; 3130 1.4.2.2 pgoyette 3131 1.4.2.2 pgoyette DEBUGFUNC("ixgbe_led_off_t_X550em"); 3132 1.4.2.2 pgoyette 3133 1.4.2.2 pgoyette if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 3134 1.4.2.2 pgoyette return IXGBE_ERR_PARAM; 3135 1.4.2.2 pgoyette 3136 1.4.2.2 pgoyette /* To turn on the LED, set mode to ON. */ 3137 1.4.2.2 pgoyette ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 3138 1.4.2.2 pgoyette IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data); 3139 1.4.2.2 pgoyette phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK; 3140 1.4.2.2 pgoyette ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 3141 1.4.2.2 pgoyette IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data); 3142 1.4.2.2 pgoyette 3143 1.4.2.2 pgoyette return IXGBE_SUCCESS; 3144 1.4.2.2 pgoyette } 3145 1.4.2.2 pgoyette 3146
Indexes created Wed Oct 22 13:09:56 GMT 2025