ixgbe_x550.c revision 1.10
1 /****************************************************************************** 2 3 Copyright (c) 2001-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x550.c 320688 2017-07-05 17:27:03Z erj $*/ 34 35 #include "ixgbe_x550.h" 36 #include "ixgbe_x540.h" 37 #include "ixgbe_type.h" 38 #include "ixgbe_api.h" 39 #include "ixgbe_common.h" 40 #include "ixgbe_phy.h" 41 #include <dev/mii/mii.h> 42 43 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed); 44 static s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, 45 ixgbe_link_speed speed, 46 bool autoneg_wait_to_complete); 47 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask); 48 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask); 49 static s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw); 50 51 /** 52 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type 53 * @hw: pointer to hardware structure 54 * 55 * Initialize the function pointers and assign the MAC type for X550. 56 * Does not touch the hardware. 57 **/ 58 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw) 59 { 60 struct ixgbe_mac_info *mac = &hw->mac; 61 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 62 s32 ret_val; 63 64 DEBUGFUNC("ixgbe_init_ops_X550"); 65 66 ret_val = ixgbe_init_ops_X540(hw); 67 mac->ops.dmac_config = ixgbe_dmac_config_X550; 68 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550; 69 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550; 70 mac->ops.setup_eee = NULL; 71 mac->ops.set_source_address_pruning = 72 ixgbe_set_source_address_pruning_X550; 73 mac->ops.set_ethertype_anti_spoofing = 74 ixgbe_set_ethertype_anti_spoofing_X550; 75 76 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; 77 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550; 78 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550; 79 eeprom->ops.read = ixgbe_read_ee_hostif_X550; 80 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550; 81 eeprom->ops.write = ixgbe_write_ee_hostif_X550; 82 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550; 83 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550; 84 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550; 85 86 mac->ops.disable_mdd = ixgbe_disable_mdd_X550; 87 mac->ops.enable_mdd = ixgbe_enable_mdd_X550; 88 mac->ops.mdd_event = ixgbe_mdd_event_X550; 89 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550; 90 mac->ops.disable_rx = ixgbe_disable_rx_x550; 91 /* Manageability interface */ 92 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550; 93 switch (hw->device_id) { 94 case IXGBE_DEV_ID_X550EM_X_1G_T: 95 hw->mac.ops.led_on = NULL; 96 hw->mac.ops.led_off = NULL; 97 break; 98 case IXGBE_DEV_ID_X550EM_X_10G_T: 99 case IXGBE_DEV_ID_X550EM_A_10G_T: 100 hw->mac.ops.led_on = ixgbe_led_on_t_X550em; 101 hw->mac.ops.led_off = ixgbe_led_off_t_X550em; 102 break; 103 default: 104 break; 105 } 106 return ret_val; 107 } 108 109 /** 110 * ixgbe_read_cs4227 - Read CS4227 register 111 * @hw: pointer to hardware structure 112 * @reg: register number to write 113 * @value: pointer to receive value read 114 * 115 * Returns status code 116 **/ 117 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value) 118 { 119 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value); 120 } 121 122 /** 123 * ixgbe_write_cs4227 - Write CS4227 register 124 * @hw: pointer to hardware structure 125 * @reg: register number to write 126 * @value: value to write to register 127 * 128 * Returns status code 129 **/ 130 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) 131 { 132 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value); 133 } 134 135 /** 136 * ixgbe_read_pe - Read register from port expander 137 * @hw: pointer to hardware structure 138 * @reg: register number to read 139 * @value: pointer to receive read value 140 * 141 * Returns status code 142 **/ 143 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) 144 { 145 s32 status; 146 147 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value); 148 if (status != IXGBE_SUCCESS) 149 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 150 "port expander access failed with %d\n", status); 151 return status; 152 } 153 154 /** 155 * ixgbe_write_pe - Write register to port expander 156 * @hw: pointer to hardware structure 157 * @reg: register number to write 158 * @value: value to write 159 * 160 * Returns status code 161 **/ 162 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value) 163 { 164 s32 status; 165 166 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value); 167 if (status != IXGBE_SUCCESS) 168 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 169 "port expander access failed with %d\n", status); 170 return status; 171 } 172 173 /** 174 * ixgbe_reset_cs4227 - Reset CS4227 using port expander 175 * @hw: pointer to hardware structure 176 * 177 * This function assumes that the caller has acquired the proper semaphore. 178 * Returns error code 179 **/ 180 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw) 181 { 182 s32 status; 183 u32 retry; 184 u16 value; 185 u8 reg; 186 187 /* Trigger hard reset. */ 188 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 189 if (status != IXGBE_SUCCESS) 190 return status; 191 reg |= IXGBE_PE_BIT1; 192 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 193 if (status != IXGBE_SUCCESS) 194 return status; 195 196 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®); 197 if (status != IXGBE_SUCCESS) 198 return status; 199 reg &= ~IXGBE_PE_BIT1; 200 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg); 201 if (status != IXGBE_SUCCESS) 202 return status; 203 204 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 205 if (status != IXGBE_SUCCESS) 206 return status; 207 reg &= ~IXGBE_PE_BIT1; 208 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 209 if (status != IXGBE_SUCCESS) 210 return status; 211 212 usec_delay(IXGBE_CS4227_RESET_HOLD); 213 214 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 215 if (status != IXGBE_SUCCESS) 216 return status; 217 reg |= IXGBE_PE_BIT1; 218 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 219 if (status != IXGBE_SUCCESS) 220 return status; 221 222 /* Wait for the reset to complete. */ 223 msec_delay(IXGBE_CS4227_RESET_DELAY); 224 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 225 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS, 226 &value); 227 if (status == IXGBE_SUCCESS && 228 value == IXGBE_CS4227_EEPROM_LOAD_OK) 229 break; 230 msec_delay(IXGBE_CS4227_CHECK_DELAY); 231 } 232 if (retry == IXGBE_CS4227_RETRIES) { 233 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 234 "CS4227 reset did not complete."); 235 return IXGBE_ERR_PHY; 236 } 237 238 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value); 239 if (status != IXGBE_SUCCESS || 240 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) { 241 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 242 "CS4227 EEPROM did not load successfully."); 243 return IXGBE_ERR_PHY; 244 } 245 246 return IXGBE_SUCCESS; 247 } 248 249 /** 250 * ixgbe_check_cs4227 - Check CS4227 and reset as needed 251 * @hw: pointer to hardware structure 252 **/ 253 static void ixgbe_check_cs4227(struct ixgbe_hw *hw) 254 { 255 s32 status = IXGBE_SUCCESS; 256 u32 swfw_mask = hw->phy.phy_semaphore_mask; 257 u16 value = 0; 258 u8 retry; 259 260 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 261 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 262 if (status != IXGBE_SUCCESS) { 263 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 264 "semaphore failed with %d", status); 265 msec_delay(IXGBE_CS4227_CHECK_DELAY); 266 continue; 267 } 268 269 /* Get status of reset flow. */ 270 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); 271 272 if (status == IXGBE_SUCCESS && 273 value == IXGBE_CS4227_RESET_COMPLETE) 274 goto out; 275 276 if (status != IXGBE_SUCCESS || 277 value != IXGBE_CS4227_RESET_PENDING) 278 break; 279 280 /* Reset is pending. Wait and check again. */ 281 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 282 msec_delay(IXGBE_CS4227_CHECK_DELAY); 283 } 284 285 /* If still pending, assume other instance failed. */ 286 if (retry == IXGBE_CS4227_RETRIES) { 287 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 288 if (status != IXGBE_SUCCESS) { 289 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 290 "semaphore failed with %d", status); 291 return; 292 } 293 } 294 295 /* Reset the CS4227. */ 296 status = ixgbe_reset_cs4227(hw); 297 if (status != IXGBE_SUCCESS) { 298 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 299 "CS4227 reset failed: %d", status); 300 goto out; 301 } 302 303 /* Reset takes so long, temporarily release semaphore in case the 304 * other driver instance is waiting for the reset indication. 305 */ 306 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 307 IXGBE_CS4227_RESET_PENDING); 308 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 309 msec_delay(10); 310 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 311 if (status != IXGBE_SUCCESS) { 312 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 313 "semaphore failed with %d", status); 314 return; 315 } 316 317 /* Record completion for next time. */ 318 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 319 IXGBE_CS4227_RESET_COMPLETE); 320 321 out: 322 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 323 msec_delay(hw->eeprom.semaphore_delay); 324 } 325 326 /** 327 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control 328 * @hw: pointer to hardware structure 329 **/ 330 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) 331 { 332 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 333 334 if (hw->bus.lan_id) { 335 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); 336 esdp |= IXGBE_ESDP_SDP1_DIR; 337 } 338 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); 339 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 340 IXGBE_WRITE_FLUSH(hw); 341 } 342 343 /** 344 * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock 345 * @hw: pointer to hardware structure 346 * @reg_addr: 32 bit address of PHY register to read 347 * @dev_type: always unused 348 * @phy_data: Pointer to read data from PHY register 349 */ 350 static s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr, 351 u32 dev_type, u16 *phy_data) 352 { 353 u32 i, data, command; 354 UNREFERENCED_1PARAMETER(dev_type); 355 356 /* Setup and write the read command */ 357 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) | 358 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 359 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC | 360 IXGBE_MSCA_MDI_COMMAND; 361 362 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 363 364 /* Check every 10 usec to see if the access completed. 365 * The MDI Command bit will clear when the operation is 366 * complete 367 */ 368 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 369 usec_delay(10); 370 371 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 372 if (!(command & IXGBE_MSCA_MDI_COMMAND)) 373 break; 374 } 375 376 if (command & IXGBE_MSCA_MDI_COMMAND) { 377 ERROR_REPORT1(IXGBE_ERROR_POLLING, 378 "PHY read command did not complete.\n"); 379 return IXGBE_ERR_PHY; 380 } 381 382 /* Read operation is complete. Get the data from MSRWD */ 383 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 384 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 385 *phy_data = (u16)data; 386 387 return IXGBE_SUCCESS; 388 } 389 390 /** 391 * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock 392 * @hw: pointer to hardware structure 393 * @reg_addr: 32 bit PHY register to write 394 * @dev_type: always unused 395 * @phy_data: Data to write to the PHY register 396 */ 397 static s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr, 398 u32 dev_type, u16 phy_data) 399 { 400 u32 i, command; 401 UNREFERENCED_1PARAMETER(dev_type); 402 403 /* Put the data in the MDI single read and write data register*/ 404 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 405 406 /* Setup and write the write command */ 407 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) | 408 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 409 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE | 410 IXGBE_MSCA_MDI_COMMAND; 411 412 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 413 414 /* Check every 10 usec to see if the access completed. 415 * The MDI Command bit will clear when the operation is 416 * complete 417 */ 418 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 419 usec_delay(10); 420 421 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 422 if (!(command & IXGBE_MSCA_MDI_COMMAND)) 423 break; 424 } 425 426 if (command & IXGBE_MSCA_MDI_COMMAND) { 427 ERROR_REPORT1(IXGBE_ERROR_POLLING, 428 "PHY write cmd didn't complete\n"); 429 return IXGBE_ERR_PHY; 430 } 431 432 return IXGBE_SUCCESS; 433 } 434 435 /** 436 * ixgbe_identify_phy_x550em - Get PHY type based on device id 437 * @hw: pointer to hardware structure 438 * 439 * Returns error code 440 */ 441 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) 442 { 443 hw->mac.ops.set_lan_id(hw); 444 445 ixgbe_read_mng_if_sel_x550em(hw); 446 447 switch (hw->device_id) { 448 case IXGBE_DEV_ID_X550EM_A_SFP: 449 return ixgbe_identify_module_generic(hw); 450 case IXGBE_DEV_ID_X550EM_X_SFP: 451 /* set up for CS4227 usage */ 452 ixgbe_setup_mux_ctl(hw); 453 ixgbe_check_cs4227(hw); 454 /* Fallthrough */ 455 456 case IXGBE_DEV_ID_X550EM_A_SFP_N: 457 return ixgbe_identify_module_generic(hw); 458 break; 459 case IXGBE_DEV_ID_X550EM_X_KX4: 460 hw->phy.type = ixgbe_phy_x550em_kx4; 461 break; 462 case IXGBE_DEV_ID_X550EM_X_XFI: 463 hw->phy.type = ixgbe_phy_x550em_xfi; 464 break; 465 case IXGBE_DEV_ID_X550EM_X_KR: 466 case IXGBE_DEV_ID_X550EM_A_KR: 467 case IXGBE_DEV_ID_X550EM_A_KR_L: 468 hw->phy.type = ixgbe_phy_x550em_kr; 469 break; 470 case IXGBE_DEV_ID_X550EM_A_10G_T: 471 case IXGBE_DEV_ID_X550EM_X_10G_T: 472 return ixgbe_identify_phy_generic(hw); 473 case IXGBE_DEV_ID_X550EM_X_1G_T: 474 hw->phy.type = ixgbe_phy_ext_1g_t; 475 break; 476 case IXGBE_DEV_ID_X550EM_A_1G_T: 477 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 478 hw->phy.type = ixgbe_phy_fw; 479 if (hw->bus.lan_id) 480 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; 481 else 482 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; 483 break; 484 default: 485 break; 486 } 487 return IXGBE_SUCCESS; 488 } 489 490 /** 491 * ixgbe_fw_phy_activity - Perform an activity on a PHY 492 * @hw: pointer to hardware structure 493 * @activity: activity to perform 494 * @data: Pointer to 4 32-bit words of data 495 */ 496 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity, 497 u32 (*data)[FW_PHY_ACT_DATA_COUNT]) 498 { 499 union { 500 struct ixgbe_hic_phy_activity_req cmd; 501 struct ixgbe_hic_phy_activity_resp rsp; 502 } hic; 503 u16 retries = FW_PHY_ACT_RETRIES; 504 s32 rc; 505 u16 i; 506 507 do { 508 memset(&hic, 0, sizeof(hic)); 509 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD; 510 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN; 511 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 512 hic.cmd.port_number = hw->bus.lan_id; 513 hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity); 514 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i) 515 hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]); 516 517 rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd, 518 sizeof(hic.cmd), 519 IXGBE_HI_COMMAND_TIMEOUT, 520 TRUE); 521 if (rc != IXGBE_SUCCESS) 522 return rc; 523 if (hic.rsp.hdr.cmd_or_resp.ret_status == 524 FW_CEM_RESP_STATUS_SUCCESS) { 525 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i) 526 (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]); 527 return IXGBE_SUCCESS; 528 } 529 usec_delay(20); 530 --retries; 531 } while (retries > 0); 532 533 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 534 } 535 536 static const struct { 537 u16 fw_speed; 538 ixgbe_link_speed phy_speed; 539 } ixgbe_fw_map[] = { 540 { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL }, 541 { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL }, 542 { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL }, 543 { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL }, 544 { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL }, 545 { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL }, 546 }; 547 548 /** 549 * ixgbe_get_phy_id_fw - Get the phy ID via firmware command 550 * @hw: pointer to hardware structure 551 * 552 * Returns error code 553 */ 554 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw) 555 { 556 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 557 u16 phy_speeds; 558 u16 phy_id_lo; 559 s32 rc; 560 u16 i; 561 562 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info); 563 if (rc) 564 return rc; 565 566 hw->phy.speeds_supported = 0; 567 phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK; 568 for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) { 569 if (phy_speeds & ixgbe_fw_map[i].fw_speed) 570 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed; 571 } 572 if (!hw->phy.autoneg_advertised) 573 hw->phy.autoneg_advertised = hw->phy.speeds_supported; 574 575 hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK; 576 phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK; 577 hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK; 578 hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK; 579 if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK) 580 return IXGBE_ERR_PHY_ADDR_INVALID; 581 return IXGBE_SUCCESS; 582 } 583 584 /** 585 * ixgbe_identify_phy_fw - Get PHY type based on firmware command 586 * @hw: pointer to hardware structure 587 * 588 * Returns error code 589 */ 590 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw) 591 { 592 if (hw->bus.lan_id) 593 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 594 else 595 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 596 597 hw->phy.type = ixgbe_phy_fw; 598 hw->phy.ops.read_reg = NULL; 599 hw->phy.ops.write_reg = NULL; 600 return ixgbe_get_phy_id_fw(hw); 601 } 602 603 /** 604 * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY 605 * @hw: pointer to hardware structure 606 * 607 * Returns error code 608 */ 609 s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw) 610 { 611 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 612 613 setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF; 614 return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup); 615 } 616 617 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 618 u32 device_type, u16 *phy_data) 619 { 620 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data); 621 return IXGBE_NOT_IMPLEMENTED; 622 } 623 624 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 625 u32 device_type, u16 phy_data) 626 { 627 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data); 628 return IXGBE_NOT_IMPLEMENTED; 629 } 630 631 /** 632 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 633 * @hw: pointer to the hardware structure 634 * @addr: I2C bus address to read from 635 * @reg: I2C device register to read from 636 * @val: pointer to location to receive read value 637 * 638 * Returns an error code on error. 639 **/ 640 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 641 u16 reg, u16 *val) 642 { 643 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, TRUE); 644 } 645 646 /** 647 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation 648 * @hw: pointer to the hardware structure 649 * @addr: I2C bus address to read from 650 * @reg: I2C device register to read from 651 * @val: pointer to location to receive read value 652 * 653 * Returns an error code on error. 654 **/ 655 static s32 656 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, 657 u16 reg, u16 *val) 658 { 659 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, FALSE); 660 } 661 662 /** 663 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 664 * @hw: pointer to the hardware structure 665 * @addr: I2C bus address to write to 666 * @reg: I2C device register to write to 667 * @val: value to write 668 * 669 * Returns an error code on error. 670 **/ 671 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 672 u8 addr, u16 reg, u16 val) 673 { 674 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, TRUE); 675 } 676 677 /** 678 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation 679 * @hw: pointer to the hardware structure 680 * @addr: I2C bus address to write to 681 * @reg: I2C device register to write to 682 * @val: value to write 683 * 684 * Returns an error code on error. 685 **/ 686 static s32 687 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, 688 u8 addr, u16 reg, u16 val) 689 { 690 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, FALSE); 691 } 692 693 /** 694 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type 695 * @hw: pointer to hardware structure 696 * 697 * Initialize the function pointers and for MAC type X550EM. 698 * Does not touch the hardware. 699 **/ 700 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw) 701 { 702 struct ixgbe_mac_info *mac = &hw->mac; 703 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 704 struct ixgbe_phy_info *phy = &hw->phy; 705 s32 ret_val; 706 707 DEBUGFUNC("ixgbe_init_ops_X550EM"); 708 709 /* Similar to X550 so start there. */ 710 ret_val = ixgbe_init_ops_X550(hw); 711 712 /* Since this function eventually calls 713 * ixgbe_init_ops_540 by design, we are setting 714 * the pointers to NULL explicitly here to overwrite 715 * the values being set in the x540 function. 716 */ 717 718 /* Bypass not supported in x550EM */ 719 mac->ops.bypass_rw = NULL; 720 mac->ops.bypass_valid_rd = NULL; 721 mac->ops.bypass_set = NULL; 722 mac->ops.bypass_rd_eep = NULL; 723 724 /* FCOE not supported in x550EM */ 725 mac->ops.get_san_mac_addr = NULL; 726 mac->ops.set_san_mac_addr = NULL; 727 mac->ops.get_wwn_prefix = NULL; 728 mac->ops.get_fcoe_boot_status = NULL; 729 730 /* IPsec not supported in x550EM */ 731 mac->ops.disable_sec_rx_path = NULL; 732 mac->ops.enable_sec_rx_path = NULL; 733 734 /* AUTOC register is not present in x550EM. */ 735 mac->ops.prot_autoc_read = NULL; 736 mac->ops.prot_autoc_write = NULL; 737 738 /* X550EM bus type is internal*/ 739 hw->bus.type = ixgbe_bus_type_internal; 740 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em; 741 742 743 mac->ops.get_media_type = ixgbe_get_media_type_X550em; 744 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em; 745 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em; 746 mac->ops.reset_hw = ixgbe_reset_hw_X550em; 747 mac->ops.get_supported_physical_layer = 748 ixgbe_get_supported_physical_layer_X550em; 749 750 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) 751 mac->ops.setup_fc = ixgbe_setup_fc_generic; 752 else 753 mac->ops.setup_fc = ixgbe_setup_fc_X550em; 754 755 /* PHY */ 756 phy->ops.init = ixgbe_init_phy_ops_X550em; 757 switch (hw->device_id) { 758 case IXGBE_DEV_ID_X550EM_A_1G_T: 759 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 760 mac->ops.setup_fc = NULL; 761 phy->ops.identify = ixgbe_identify_phy_fw; 762 phy->ops.set_phy_power = NULL; 763 phy->ops.get_firmware_version = NULL; 764 break; 765 case IXGBE_DEV_ID_X550EM_X_1G_T: 766 mac->ops.setup_fc = NULL; 767 phy->ops.identify = ixgbe_identify_phy_x550em; 768 phy->ops.set_phy_power = NULL; 769 break; 770 default: 771 phy->ops.identify = ixgbe_identify_phy_x550em; 772 } 773 774 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 775 phy->ops.set_phy_power = NULL; 776 777 778 /* EEPROM */ 779 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540; 780 eeprom->ops.read = ixgbe_read_ee_hostif_X550; 781 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550; 782 eeprom->ops.write = ixgbe_write_ee_hostif_X550; 783 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550; 784 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550; 785 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550; 786 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550; 787 788 return ret_val; 789 } 790 791 #define IXGBE_DENVERTON_WA 1 792 793 /** 794 * ixgbe_setup_fw_link - Setup firmware-controlled PHYs 795 * @hw: pointer to hardware structure 796 */ 797 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw) 798 { 799 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 800 s32 rc; 801 #ifdef IXGBE_DENVERTON_WA 802 s32 ret_val; 803 u16 phydata; 804 #endif 805 u16 i; 806 807 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 808 return 0; 809 810 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 811 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 812 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 813 return IXGBE_ERR_INVALID_LINK_SETTINGS; 814 } 815 816 switch (hw->fc.requested_mode) { 817 case ixgbe_fc_full: 818 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX << 819 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 820 break; 821 case ixgbe_fc_rx_pause: 822 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX << 823 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 824 break; 825 case ixgbe_fc_tx_pause: 826 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX << 827 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 828 break; 829 default: 830 break; 831 } 832 833 for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) { 834 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed) 835 setup[0] |= ixgbe_fw_map[i].fw_speed; 836 } 837 setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN; 838 839 if (hw->phy.eee_speeds_advertised) 840 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE; 841 842 #ifdef IXGBE_DENVERTON_WA 843 /* Don't use auto-nego for 10/100Mbps */ 844 if ((hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_100_FULL) 845 || (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_10_FULL)) { 846 setup[0] &= ~FW_PHY_ACT_SETUP_LINK_AN; 847 setup[0] &= ~FW_PHY_ACT_SETUP_LINK_EEE; 848 setup[0] &= ~(FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX 849 << FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT); 850 } 851 #endif 852 853 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup); 854 if (rc) 855 return rc; 856 857 #ifdef IXGBE_DENVERTON_WA 858 ret_val = ixgbe_read_phy_reg_x550a(hw, MII_BMCR, 0, &phydata); 859 if (ret_val != 0) 860 goto out; 861 862 /* 863 * Broken firmware sets BMCR register incorrectly if 864 * FW_PHY_ACT_SETUP_LINK_AN isn't set. 865 * a) FDX may not be set. 866 * b) BMCR_SPEED1 (bit 6) is always cleard. 867 * + -------+------+-----------+-----+--------------------------+ 868 * |request | BMCR | BMCR spd | BMCR | | 869 * | | (HEX)| (in bits)| FDX | | 870 * +--------+------+----------+------+--------------------------+ 871 * | 10M | 0000 | 10M(00) | 0 | | 872 * | 10M | 2000 | 100M(01) | 0 |(I've never observed this)| 873 * | 10M | 2100 | 100M(01) | 1 | | 874 * | 100M | 0000 | 10M(00) | 0 | | 875 * | 100M | 0100 | 10M(00) | 1 | | 876 * +--------------------------+------+--------------------------+ 877 */ 878 if (((hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_100_FULL) 879 && (((phydata & BMCR_FDX) == 0) || (BMCR_SPEED(phydata) == 0))) 880 || ((hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_10_FULL) 881 && (((phydata & BMCR_FDX) == 0) 882 || (BMCR_SPEED(phydata) != BMCR_S10)))) { 883 phydata = BMCR_FDX; 884 switch (hw->phy.autoneg_advertised) { 885 case IXGBE_LINK_SPEED_10_FULL: 886 phydata |= BMCR_S10; 887 break; 888 case IXGBE_LINK_SPEED_100_FULL: 889 phydata |= BMCR_S100; 890 break; 891 case IXGBE_LINK_SPEED_1GB_FULL: 892 panic("%s: 1GB_FULL is set", __func__); 893 break; 894 default: 895 break; 896 } 897 ret_val = ixgbe_write_phy_reg_x550a(hw, MII_BMCR, 0, phydata); 898 if (ret_val != 0) 899 return ret_val; 900 } 901 out: 902 #endif 903 if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN) 904 return IXGBE_ERR_OVERTEMP; 905 return IXGBE_SUCCESS; 906 } 907 908 /** 909 * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs 910 * @hw: pointer to hardware structure 911 * 912 * Called at init time to set up flow control. 913 */ 914 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw) 915 { 916 if (hw->fc.requested_mode == ixgbe_fc_default) 917 hw->fc.requested_mode = ixgbe_fc_full; 918 919 return ixgbe_setup_fw_link(hw); 920 } 921 922 /** 923 * ixgbe_setup_eee_fw - Enable/disable EEE support 924 * @hw: pointer to the HW structure 925 * @enable_eee: boolean flag to enable EEE 926 * 927 * Enable/disable EEE based on enable_eee flag. 928 * This function controls EEE for firmware-based PHY implementations. 929 */ 930 static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee) 931 { 932 if (!!hw->phy.eee_speeds_advertised == enable_eee) 933 return IXGBE_SUCCESS; 934 if (enable_eee) 935 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported; 936 else 937 hw->phy.eee_speeds_advertised = 0; 938 return hw->phy.ops.setup_link(hw); 939 } 940 941 /** 942 * ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type 943 * @hw: pointer to hardware structure 944 * 945 * Initialize the function pointers and for MAC type X550EM_a. 946 * Does not touch the hardware. 947 **/ 948 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw) 949 { 950 struct ixgbe_mac_info *mac = &hw->mac; 951 s32 ret_val; 952 953 DEBUGFUNC("ixgbe_init_ops_X550EM_a"); 954 955 /* Start with generic X550EM init */ 956 ret_val = ixgbe_init_ops_X550EM(hw); 957 958 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII || 959 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) { 960 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550; 961 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550; 962 } else { 963 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a; 964 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a; 965 } 966 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a; 967 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a; 968 969 switch (mac->ops.get_media_type(hw)) { 970 case ixgbe_media_type_fiber: 971 mac->ops.setup_fc = NULL; 972 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a; 973 break; 974 case ixgbe_media_type_backplane: 975 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a; 976 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a; 977 break; 978 default: 979 break; 980 } 981 982 switch (hw->device_id) { 983 case IXGBE_DEV_ID_X550EM_A_1G_T: 984 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 985 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a; 986 mac->ops.setup_fc = ixgbe_fc_autoneg_fw; 987 mac->ops.setup_eee = ixgbe_setup_eee_fw; 988 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL | 989 IXGBE_LINK_SPEED_1GB_FULL; 990 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported; 991 break; 992 default: 993 break; 994 } 995 996 return ret_val; 997 } 998 999 /** 1000 * ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type 1001 * @hw: pointer to hardware structure 1002 * 1003 * Initialize the function pointers and for MAC type X550EM_x. 1004 * Does not touch the hardware. 1005 **/ 1006 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw) 1007 { 1008 struct ixgbe_mac_info *mac = &hw->mac; 1009 struct ixgbe_link_info *link = &hw->link; 1010 s32 ret_val; 1011 1012 DEBUGFUNC("ixgbe_init_ops_X550EM_x"); 1013 1014 /* Start with generic X550EM init */ 1015 ret_val = ixgbe_init_ops_X550EM(hw); 1016 1017 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550; 1018 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550; 1019 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em; 1020 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em; 1021 link->ops.read_link = ixgbe_read_i2c_combined_generic; 1022 link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked; 1023 link->ops.write_link = ixgbe_write_i2c_combined_generic; 1024 link->ops.write_link_unlocked = 1025 ixgbe_write_i2c_combined_generic_unlocked; 1026 link->addr = IXGBE_CS4227; 1027 1028 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) { 1029 mac->ops.setup_fc = NULL; 1030 mac->ops.setup_eee = NULL; 1031 mac->ops.init_led_link_act = NULL; 1032 } 1033 1034 return ret_val; 1035 } 1036 1037 /** 1038 * ixgbe_dmac_config_X550 1039 * @hw: pointer to hardware structure 1040 * 1041 * Configure DMA coalescing. If enabling dmac, dmac is activated. 1042 * When disabling dmac, dmac enable dmac bit is cleared. 1043 **/ 1044 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw) 1045 { 1046 u32 reg, high_pri_tc; 1047 1048 DEBUGFUNC("ixgbe_dmac_config_X550"); 1049 1050 /* Disable DMA coalescing before configuring */ 1051 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 1052 reg &= ~IXGBE_DMACR_DMAC_EN; 1053 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 1054 1055 /* Disable DMA Coalescing if the watchdog timer is 0 */ 1056 if (!hw->mac.dmac_config.watchdog_timer) 1057 goto out; 1058 1059 ixgbe_dmac_config_tcs_X550(hw); 1060 1061 /* Configure DMA Coalescing Control Register */ 1062 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 1063 1064 /* Set the watchdog timer in units of 40.96 usec */ 1065 reg &= ~IXGBE_DMACR_DMACWT_MASK; 1066 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096; 1067 1068 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK; 1069 /* If fcoe is enabled, set high priority traffic class */ 1070 if (hw->mac.dmac_config.fcoe_en) { 1071 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc; 1072 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) & 1073 IXGBE_DMACR_HIGH_PRI_TC_MASK); 1074 } 1075 reg |= IXGBE_DMACR_EN_MNG_IND; 1076 1077 /* Enable DMA coalescing after configuration */ 1078 reg |= IXGBE_DMACR_DMAC_EN; 1079 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 1080 1081 out: 1082 return IXGBE_SUCCESS; 1083 } 1084 1085 /** 1086 * ixgbe_dmac_config_tcs_X550 1087 * @hw: pointer to hardware structure 1088 * 1089 * Configure DMA coalescing threshold per TC. The dmac enable bit must 1090 * be cleared before configuring. 1091 **/ 1092 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw) 1093 { 1094 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb; 1095 1096 DEBUGFUNC("ixgbe_dmac_config_tcs_X550"); 1097 1098 /* Configure DMA coalescing enabled */ 1099 switch (hw->mac.dmac_config.link_speed) { 1100 case IXGBE_LINK_SPEED_10_FULL: 1101 case IXGBE_LINK_SPEED_100_FULL: 1102 pb_headroom = IXGBE_DMACRXT_100M; 1103 break; 1104 case IXGBE_LINK_SPEED_1GB_FULL: 1105 pb_headroom = IXGBE_DMACRXT_1G; 1106 break; 1107 default: 1108 pb_headroom = IXGBE_DMACRXT_10G; 1109 break; 1110 } 1111 1112 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >> 1113 IXGBE_MHADD_MFS_SHIFT) / 1024); 1114 1115 /* Set the per Rx packet buffer receive threshold */ 1116 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) { 1117 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc)); 1118 reg &= ~IXGBE_DMCTH_DMACRXT_MASK; 1119 1120 if (tc < hw->mac.dmac_config.num_tcs) { 1121 /* Get Rx PB size */ 1122 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc)); 1123 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >> 1124 IXGBE_RXPBSIZE_SHIFT; 1125 1126 /* Calculate receive buffer threshold in kilobytes */ 1127 if (rx_pb_size > pb_headroom) 1128 rx_pb_size = rx_pb_size - pb_headroom; 1129 else 1130 rx_pb_size = 0; 1131 1132 /* Minimum of MFS shall be set for DMCTH */ 1133 reg |= (rx_pb_size > maxframe_size_kb) ? 1134 rx_pb_size : maxframe_size_kb; 1135 } 1136 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg); 1137 } 1138 return IXGBE_SUCCESS; 1139 } 1140 1141 /** 1142 * ixgbe_dmac_update_tcs_X550 1143 * @hw: pointer to hardware structure 1144 * 1145 * Disables dmac, updates per TC settings, and then enables dmac. 1146 **/ 1147 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw) 1148 { 1149 u32 reg; 1150 1151 DEBUGFUNC("ixgbe_dmac_update_tcs_X550"); 1152 1153 /* Disable DMA coalescing before configuring */ 1154 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 1155 reg &= ~IXGBE_DMACR_DMAC_EN; 1156 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 1157 1158 ixgbe_dmac_config_tcs_X550(hw); 1159 1160 /* Enable DMA coalescing after configuration */ 1161 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 1162 reg |= IXGBE_DMACR_DMAC_EN; 1163 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 1164 1165 return IXGBE_SUCCESS; 1166 } 1167 1168 /** 1169 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params 1170 * @hw: pointer to hardware structure 1171 * 1172 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 1173 * ixgbe_hw struct in order to set up EEPROM access. 1174 **/ 1175 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) 1176 { 1177 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1178 u32 eec; 1179 u16 eeprom_size; 1180 1181 DEBUGFUNC("ixgbe_init_eeprom_params_X550"); 1182 1183 if (eeprom->type == ixgbe_eeprom_uninitialized) { 1184 eeprom->semaphore_delay = 10; 1185 eeprom->type = ixgbe_flash; 1186 1187 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1188 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 1189 IXGBE_EEC_SIZE_SHIFT); 1190 eeprom->word_size = 1 << (eeprom_size + 1191 IXGBE_EEPROM_WORD_SIZE_SHIFT); 1192 1193 DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 1194 eeprom->type, eeprom->word_size); 1195 } 1196 1197 return IXGBE_SUCCESS; 1198 } 1199 1200 /** 1201 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning 1202 * @hw: pointer to hardware structure 1203 * @enable: enable or disable source address pruning 1204 * @pool: Rx pool to set source address pruning for 1205 **/ 1206 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable, 1207 unsigned int pool) 1208 { 1209 u64 pfflp; 1210 1211 /* max rx pool is 63 */ 1212 if (pool > 63) 1213 return; 1214 1215 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL); 1216 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32; 1217 1218 if (enable) 1219 pfflp |= (1ULL << pool); 1220 else 1221 pfflp &= ~(1ULL << pool); 1222 1223 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); 1224 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); 1225 } 1226 1227 /** 1228 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing 1229 * @hw: pointer to hardware structure 1230 * @enable: enable or disable switch for Ethertype anti-spoofing 1231 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1232 * 1233 **/ 1234 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, 1235 bool enable, int vf) 1236 { 1237 int vf_target_reg = vf >> 3; 1238 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT; 1239 u32 pfvfspoof; 1240 1241 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550"); 1242 1243 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 1244 if (enable) 1245 pfvfspoof |= (1 << vf_target_shift); 1246 else 1247 pfvfspoof &= ~(1 << vf_target_shift); 1248 1249 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 1250 } 1251 1252 /** 1253 * ixgbe_iosf_wait - Wait for IOSF command completion 1254 * @hw: pointer to hardware structure 1255 * @ctrl: pointer to location to receive final IOSF control value 1256 * 1257 * Returns failing status on timeout 1258 * 1259 * Note: ctrl can be NULL if the IOSF control register value is not needed 1260 **/ 1261 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) 1262 { 1263 u32 i, command = 0; 1264 1265 /* Check every 10 usec to see if the address cycle completed. 1266 * The SB IOSF BUSY bit will clear when the operation is 1267 * complete 1268 */ 1269 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 1270 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); 1271 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0) 1272 break; 1273 usec_delay(10); 1274 } 1275 if (ctrl) 1276 *ctrl = command; 1277 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { 1278 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n"); 1279 return IXGBE_ERR_PHY; 1280 } 1281 1282 return IXGBE_SUCCESS; 1283 } 1284 1285 /** 1286 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register 1287 * of the IOSF device 1288 * @hw: pointer to hardware structure 1289 * @reg_addr: 32 bit PHY register to write 1290 * @device_type: 3 bit device type 1291 * @data: Data to write to the register 1292 **/ 1293 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 1294 u32 device_type, u32 data) 1295 { 1296 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 1297 u32 command, error __unused; 1298 s32 ret; 1299 1300 ret = ixgbe_acquire_swfw_semaphore(hw, gssr); 1301 if (ret != IXGBE_SUCCESS) 1302 return ret; 1303 1304 ret = ixgbe_iosf_wait(hw, NULL); 1305 if (ret != IXGBE_SUCCESS) 1306 goto out; 1307 1308 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 1309 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 1310 1311 /* Write IOSF control register */ 1312 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 1313 1314 /* Write IOSF data register */ 1315 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); 1316 1317 ret = ixgbe_iosf_wait(hw, &command); 1318 1319 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 1320 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 1321 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 1322 ERROR_REPORT2(IXGBE_ERROR_POLLING, 1323 "Failed to write, error %x\n", error); 1324 ret = IXGBE_ERR_PHY; 1325 } 1326 1327 out: 1328 ixgbe_release_swfw_semaphore(hw, gssr); 1329 return ret; 1330 } 1331 1332 /** 1333 * ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device 1334 * @hw: pointer to hardware structure 1335 * @reg_addr: 32 bit PHY register to write 1336 * @device_type: 3 bit device type 1337 * @data: Pointer to read data from the register 1338 **/ 1339 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 1340 u32 device_type, u32 *data) 1341 { 1342 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 1343 u32 command, error __unused; 1344 s32 ret; 1345 1346 ret = ixgbe_acquire_swfw_semaphore(hw, gssr); 1347 if (ret != IXGBE_SUCCESS) 1348 return ret; 1349 1350 ret = ixgbe_iosf_wait(hw, NULL); 1351 if (ret != IXGBE_SUCCESS) 1352 goto out; 1353 1354 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 1355 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 1356 1357 /* Write IOSF control register */ 1358 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 1359 1360 ret = ixgbe_iosf_wait(hw, &command); 1361 1362 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 1363 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 1364 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 1365 ERROR_REPORT2(IXGBE_ERROR_POLLING, 1366 "Failed to read, error %x\n", error); 1367 ret = IXGBE_ERR_PHY; 1368 } 1369 1370 if (ret == IXGBE_SUCCESS) 1371 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); 1372 1373 out: 1374 ixgbe_release_swfw_semaphore(hw, gssr); 1375 return ret; 1376 } 1377 1378 /** 1379 * ixgbe_get_phy_token - Get the token for shared phy access 1380 * @hw: Pointer to hardware structure 1381 */ 1382 1383 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw) 1384 { 1385 struct ixgbe_hic_phy_token_req token_cmd; 1386 s32 status; 1387 1388 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 1389 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 1390 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 1391 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1392 token_cmd.port_number = hw->bus.lan_id; 1393 token_cmd.command_type = FW_PHY_TOKEN_REQ; 1394 token_cmd.pad = 0; 1395 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd, 1396 sizeof(token_cmd), 1397 IXGBE_HI_COMMAND_TIMEOUT, 1398 TRUE); 1399 if (status) { 1400 DEBUGOUT1("Issuing host interface command failed with Status = %d\n", 1401 status); 1402 return status; 1403 } 1404 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 1405 return IXGBE_SUCCESS; 1406 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) { 1407 DEBUGOUT1("Host interface command returned 0x%08x , returning IXGBE_ERR_FW_RESP_INVALID\n", 1408 token_cmd.hdr.cmd_or_resp.ret_status); 1409 return IXGBE_ERR_FW_RESP_INVALID; 1410 } 1411 1412 DEBUGOUT("Returning IXGBE_ERR_TOKEN_RETRY\n"); 1413 return IXGBE_ERR_TOKEN_RETRY; 1414 } 1415 1416 /** 1417 * ixgbe_put_phy_token - Put the token for shared phy access 1418 * @hw: Pointer to hardware structure 1419 */ 1420 1421 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw) 1422 { 1423 struct ixgbe_hic_phy_token_req token_cmd; 1424 s32 status; 1425 1426 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 1427 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 1428 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 1429 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1430 token_cmd.port_number = hw->bus.lan_id; 1431 token_cmd.command_type = FW_PHY_TOKEN_REL; 1432 token_cmd.pad = 0; 1433 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd, 1434 sizeof(token_cmd), 1435 IXGBE_HI_COMMAND_TIMEOUT, 1436 TRUE); 1437 if (status) 1438 return status; 1439 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 1440 return IXGBE_SUCCESS; 1441 1442 DEBUGOUT("Put PHY Token host interface command failed"); 1443 return IXGBE_ERR_FW_RESP_INVALID; 1444 } 1445 1446 /** 1447 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register 1448 * of the IOSF device 1449 * @hw: pointer to hardware structure 1450 * @reg_addr: 32 bit PHY register to write 1451 * @device_type: 3 bit device type 1452 * @data: Data to write to the register 1453 **/ 1454 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 1455 u32 device_type, u32 data) 1456 { 1457 struct ixgbe_hic_internal_phy_req write_cmd; 1458 s32 status; 1459 UNREFERENCED_1PARAMETER(device_type); 1460 1461 memset(&write_cmd, 0, sizeof(write_cmd)); 1462 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 1463 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 1464 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1465 write_cmd.port_number = hw->bus.lan_id; 1466 write_cmd.command_type = FW_INT_PHY_REQ_WRITE; 1467 write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr); 1468 write_cmd.write_data = IXGBE_CPU_TO_BE32(data); 1469 1470 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd, 1471 sizeof(write_cmd), 1472 IXGBE_HI_COMMAND_TIMEOUT, FALSE); 1473 1474 return status; 1475 } 1476 1477 /** 1478 * ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device 1479 * @hw: pointer to hardware structure 1480 * @reg_addr: 32 bit PHY register to write 1481 * @device_type: 3 bit device type 1482 * @data: Pointer to read data from the register 1483 **/ 1484 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 1485 u32 device_type, u32 *data) 1486 { 1487 union { 1488 struct ixgbe_hic_internal_phy_req cmd; 1489 struct ixgbe_hic_internal_phy_resp rsp; 1490 } hic; 1491 s32 status; 1492 UNREFERENCED_1PARAMETER(device_type); 1493 1494 memset(&hic, 0, sizeof(hic)); 1495 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 1496 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 1497 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1498 hic.cmd.port_number = hw->bus.lan_id; 1499 hic.cmd.command_type = FW_INT_PHY_REQ_READ; 1500 hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr); 1501 1502 status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd, 1503 sizeof(hic.cmd), 1504 IXGBE_HI_COMMAND_TIMEOUT, TRUE); 1505 1506 /* Extract the register value from the response. */ 1507 *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data); 1508 1509 return status; 1510 } 1511 1512 /** 1513 * ixgbe_disable_mdd_X550 1514 * @hw: pointer to hardware structure 1515 * 1516 * Disable malicious driver detection 1517 **/ 1518 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw) 1519 { 1520 u32 reg; 1521 1522 DEBUGFUNC("ixgbe_disable_mdd_X550"); 1523 1524 /* Disable MDD for TX DMA and interrupt */ 1525 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1526 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN); 1527 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1528 1529 /* Disable MDD for RX and interrupt */ 1530 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 1531 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN); 1532 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 1533 } 1534 1535 /** 1536 * ixgbe_enable_mdd_X550 1537 * @hw: pointer to hardware structure 1538 * 1539 * Enable malicious driver detection 1540 **/ 1541 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw) 1542 { 1543 u32 reg; 1544 1545 DEBUGFUNC("ixgbe_enable_mdd_X550"); 1546 1547 /* Enable MDD for TX DMA and interrupt */ 1548 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1549 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN); 1550 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1551 1552 /* Enable MDD for RX and interrupt */ 1553 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 1554 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN); 1555 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 1556 } 1557 1558 /** 1559 * ixgbe_restore_mdd_vf_X550 1560 * @hw: pointer to hardware structure 1561 * @vf: vf index 1562 * 1563 * Restore VF that was disabled during malicious driver detection event 1564 **/ 1565 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf) 1566 { 1567 u32 idx, reg, num_qs, start_q, bitmask; 1568 1569 DEBUGFUNC("ixgbe_restore_mdd_vf_X550"); 1570 1571 /* Map VF to queues */ 1572 reg = IXGBE_READ_REG(hw, IXGBE_MRQC); 1573 switch (reg & IXGBE_MRQC_MRQE_MASK) { 1574 case IXGBE_MRQC_VMDQRT8TCEN: 1575 num_qs = 8; /* 16 VFs / pools */ 1576 bitmask = 0x000000FF; 1577 break; 1578 case IXGBE_MRQC_VMDQRSS32EN: 1579 case IXGBE_MRQC_VMDQRT4TCEN: 1580 num_qs = 4; /* 32 VFs / pools */ 1581 bitmask = 0x0000000F; 1582 break; 1583 default: /* 64 VFs / pools */ 1584 num_qs = 2; 1585 bitmask = 0x00000003; 1586 break; 1587 } 1588 start_q = vf * num_qs; 1589 1590 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */ 1591 idx = start_q / 32; 1592 reg = 0; 1593 reg |= (bitmask << (start_q % 32)); 1594 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg); 1595 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg); 1596 } 1597 1598 /** 1599 * ixgbe_mdd_event_X550 1600 * @hw: pointer to hardware structure 1601 * @vf_bitmap: vf bitmap of malicious vfs 1602 * 1603 * Handle malicious driver detection event. 1604 **/ 1605 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap) 1606 { 1607 u32 wqbr; 1608 u32 i, j, reg, q, shift, vf, idx; 1609 1610 DEBUGFUNC("ixgbe_mdd_event_X550"); 1611 1612 /* figure out pool size for mapping to vf's */ 1613 reg = IXGBE_READ_REG(hw, IXGBE_MRQC); 1614 switch (reg & IXGBE_MRQC_MRQE_MASK) { 1615 case IXGBE_MRQC_VMDQRT8TCEN: 1616 shift = 3; /* 16 VFs / pools */ 1617 break; 1618 case IXGBE_MRQC_VMDQRSS32EN: 1619 case IXGBE_MRQC_VMDQRT4TCEN: 1620 shift = 2; /* 32 VFs / pools */ 1621 break; 1622 default: 1623 shift = 1; /* 64 VFs / pools */ 1624 break; 1625 } 1626 1627 /* Read WQBR_TX and WQBR_RX and check for malicious queues */ 1628 for (i = 0; i < 4; i++) { 1629 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i)); 1630 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i)); 1631 1632 if (!wqbr) 1633 continue; 1634 1635 /* Get malicious queue */ 1636 for (j = 0; j < 32 && wqbr; j++) { 1637 1638 if (!(wqbr & (1 << j))) 1639 continue; 1640 1641 /* Get queue from bitmask */ 1642 q = j + (i * 32); 1643 1644 /* Map queue to vf */ 1645 vf = (q >> shift); 1646 1647 /* Set vf bit in vf_bitmap */ 1648 idx = vf / 32; 1649 vf_bitmap[idx] |= (1 << (vf % 32)); 1650 wqbr &= ~(1 << j); 1651 } 1652 } 1653 } 1654 1655 /** 1656 * ixgbe_get_media_type_X550em - Get media type 1657 * @hw: pointer to hardware structure 1658 * 1659 * Returns the media type (fiber, copper, backplane) 1660 */ 1661 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) 1662 { 1663 enum ixgbe_media_type media_type; 1664 1665 DEBUGFUNC("ixgbe_get_media_type_X550em"); 1666 1667 /* Detect if there is a copper PHY attached. */ 1668 switch (hw->device_id) { 1669 case IXGBE_DEV_ID_X550EM_X_KR: 1670 case IXGBE_DEV_ID_X550EM_X_KX4: 1671 case IXGBE_DEV_ID_X550EM_X_XFI: 1672 case IXGBE_DEV_ID_X550EM_A_KR: 1673 case IXGBE_DEV_ID_X550EM_A_KR_L: 1674 media_type = ixgbe_media_type_backplane; 1675 break; 1676 case IXGBE_DEV_ID_X550EM_X_SFP: 1677 case IXGBE_DEV_ID_X550EM_A_SFP: 1678 case IXGBE_DEV_ID_X550EM_A_SFP_N: 1679 case IXGBE_DEV_ID_X550EM_A_QSFP: 1680 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 1681 media_type = ixgbe_media_type_fiber; 1682 break; 1683 case IXGBE_DEV_ID_X550EM_X_1G_T: 1684 case IXGBE_DEV_ID_X550EM_X_10G_T: 1685 case IXGBE_DEV_ID_X550EM_A_10G_T: 1686 media_type = ixgbe_media_type_copper; 1687 break; 1688 case IXGBE_DEV_ID_X550EM_A_SGMII: 1689 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 1690 media_type = ixgbe_media_type_backplane; 1691 hw->phy.type = ixgbe_phy_sgmii; 1692 break; 1693 case IXGBE_DEV_ID_X550EM_A_1G_T: 1694 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 1695 media_type = ixgbe_media_type_copper; 1696 break; 1697 default: 1698 media_type = ixgbe_media_type_unknown; 1699 break; 1700 } 1701 return media_type; 1702 } 1703 1704 /** 1705 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported 1706 * @hw: pointer to hardware structure 1707 * @linear: TRUE if SFP module is linear 1708 */ 1709 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear) 1710 { 1711 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em"); 1712 1713 switch (hw->phy.sfp_type) { 1714 case ixgbe_sfp_type_not_present: 1715 return IXGBE_ERR_SFP_NOT_PRESENT; 1716 case ixgbe_sfp_type_da_cu_core0: 1717 case ixgbe_sfp_type_da_cu_core1: 1718 *linear = TRUE; 1719 break; 1720 case ixgbe_sfp_type_srlr_core0: 1721 case ixgbe_sfp_type_srlr_core1: 1722 case ixgbe_sfp_type_da_act_lmt_core0: 1723 case ixgbe_sfp_type_da_act_lmt_core1: 1724 case ixgbe_sfp_type_1g_sx_core0: 1725 case ixgbe_sfp_type_1g_sx_core1: 1726 case ixgbe_sfp_type_1g_lx_core0: 1727 case ixgbe_sfp_type_1g_lx_core1: 1728 *linear = FALSE; 1729 break; 1730 case ixgbe_sfp_type_unknown: 1731 case ixgbe_sfp_type_1g_cu_core0: 1732 case ixgbe_sfp_type_1g_cu_core1: 1733 default: 1734 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1735 } 1736 1737 return IXGBE_SUCCESS; 1738 } 1739 1740 /** 1741 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules 1742 * @hw: pointer to hardware structure 1743 * 1744 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1745 **/ 1746 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw) 1747 { 1748 s32 status; 1749 bool linear; 1750 1751 DEBUGFUNC("ixgbe_identify_sfp_module_X550em"); 1752 1753 status = ixgbe_identify_module_generic(hw); 1754 1755 if (status != IXGBE_SUCCESS) 1756 return status; 1757 1758 /* Check if SFP module is supported */ 1759 status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 1760 1761 return status; 1762 } 1763 1764 /** 1765 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops 1766 * @hw: pointer to hardware structure 1767 */ 1768 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) 1769 { 1770 s32 status; 1771 bool linear; 1772 1773 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em"); 1774 1775 /* Check if SFP module is supported */ 1776 status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 1777 1778 if (status != IXGBE_SUCCESS) 1779 return status; 1780 1781 ixgbe_init_mac_link_ops_X550em(hw); 1782 hw->phy.ops.reset = NULL; 1783 1784 return IXGBE_SUCCESS; 1785 } 1786 1787 /** 1788 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the 1789 * internal PHY 1790 * @hw: pointer to hardware structure 1791 **/ 1792 static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw) 1793 { 1794 s32 status; 1795 u32 link_ctrl; 1796 1797 /* Restart auto-negotiation. */ 1798 status = hw->mac.ops.read_iosf_sb_reg(hw, 1799 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1800 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl); 1801 1802 if (status) { 1803 DEBUGOUT("Auto-negotiation did not complete\n"); 1804 return status; 1805 } 1806 1807 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1808 status = hw->mac.ops.write_iosf_sb_reg(hw, 1809 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1810 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl); 1811 1812 if (hw->mac.type == ixgbe_mac_X550EM_a) { 1813 u32 flx_mask_st20; 1814 1815 /* Indicate to FW that AN restart has been asserted */ 1816 status = hw->mac.ops.read_iosf_sb_reg(hw, 1817 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1818 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20); 1819 1820 if (status) { 1821 DEBUGOUT("Auto-negotiation did not complete\n"); 1822 return status; 1823 } 1824 1825 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART; 1826 status = hw->mac.ops.write_iosf_sb_reg(hw, 1827 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1828 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20); 1829 } 1830 1831 return status; 1832 } 1833 1834 /** 1835 * ixgbe_setup_sgmii - Set up link for sgmii 1836 * @hw: pointer to hardware structure 1837 */ 1838 static s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1839 bool autoneg_wait) 1840 { 1841 struct ixgbe_mac_info *mac = &hw->mac; 1842 u32 lval, sval, flx_val; 1843 s32 rc; 1844 1845 rc = mac->ops.read_iosf_sb_reg(hw, 1846 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1847 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 1848 if (rc) 1849 return rc; 1850 1851 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1852 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1853 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 1854 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 1855 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1856 rc = mac->ops.write_iosf_sb_reg(hw, 1857 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1858 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 1859 if (rc) 1860 return rc; 1861 1862 rc = mac->ops.read_iosf_sb_reg(hw, 1863 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1864 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 1865 if (rc) 1866 return rc; 1867 1868 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 1869 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 1870 rc = mac->ops.write_iosf_sb_reg(hw, 1871 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1872 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 1873 if (rc) 1874 return rc; 1875 1876 rc = mac->ops.read_iosf_sb_reg(hw, 1877 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1878 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 1879 if (rc) 1880 return rc; 1881 1882 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 1883 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 1884 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 1885 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 1886 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 1887 1888 rc = mac->ops.write_iosf_sb_reg(hw, 1889 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1890 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 1891 if (rc) 1892 return rc; 1893 1894 rc = ixgbe_restart_an_internal_phy_x550em(hw); 1895 if (rc) 1896 return rc; 1897 1898 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 1899 } 1900 1901 /** 1902 * ixgbe_setup_sgmii_fw - Set up link for internal PHY SGMII auto-negotiation 1903 * @hw: pointer to hardware structure 1904 */ 1905 static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1906 bool autoneg_wait) 1907 { 1908 struct ixgbe_mac_info *mac = &hw->mac; 1909 u32 lval, sval, flx_val; 1910 s32 rc; 1911 1912 rc = mac->ops.read_iosf_sb_reg(hw, 1913 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1914 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 1915 if (rc) 1916 return rc; 1917 1918 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1919 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1920 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 1921 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 1922 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1923 rc = mac->ops.write_iosf_sb_reg(hw, 1924 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1925 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 1926 if (rc) 1927 return rc; 1928 1929 rc = mac->ops.read_iosf_sb_reg(hw, 1930 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1931 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 1932 if (rc) 1933 return rc; 1934 1935 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 1936 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 1937 rc = mac->ops.write_iosf_sb_reg(hw, 1938 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1939 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 1940 if (rc) 1941 return rc; 1942 1943 rc = mac->ops.write_iosf_sb_reg(hw, 1944 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1945 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 1946 if (rc) 1947 return rc; 1948 1949 rc = mac->ops.read_iosf_sb_reg(hw, 1950 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1951 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 1952 if (rc) 1953 return rc; 1954 1955 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 1956 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 1957 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 1958 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 1959 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 1960 1961 rc = mac->ops.write_iosf_sb_reg(hw, 1962 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1963 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 1964 if (rc) 1965 return rc; 1966 1967 rc = ixgbe_restart_an_internal_phy_x550em(hw); 1968 1969 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 1970 } 1971 1972 /** 1973 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers 1974 * @hw: pointer to hardware structure 1975 */ 1976 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) 1977 { 1978 struct ixgbe_mac_info *mac = &hw->mac; 1979 1980 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em"); 1981 1982 switch (hw->mac.ops.get_media_type(hw)) { 1983 case ixgbe_media_type_fiber: 1984 /* CS4227 does not support autoneg, so disable the laser control 1985 * functions for SFP+ fiber 1986 */ 1987 mac->ops.disable_tx_laser = NULL; 1988 mac->ops.enable_tx_laser = NULL; 1989 mac->ops.flap_tx_laser = NULL; 1990 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 1991 mac->ops.set_rate_select_speed = 1992 ixgbe_set_soft_rate_select_speed; 1993 1994 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) || 1995 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP)) 1996 mac->ops.setup_mac_link = 1997 ixgbe_setup_mac_link_sfp_x550a; 1998 else 1999 mac->ops.setup_mac_link = 2000 ixgbe_setup_mac_link_sfp_x550em; 2001 break; 2002 case ixgbe_media_type_copper: 2003 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) 2004 break; 2005 if (hw->mac.type == ixgbe_mac_X550EM_a) { 2006 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 2007 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) { 2008 mac->ops.setup_link = ixgbe_setup_sgmii_fw; 2009 mac->ops.check_link = 2010 ixgbe_check_mac_link_generic; 2011 } else { 2012 mac->ops.setup_link = 2013 ixgbe_setup_mac_link_t_X550em; 2014 } 2015 } else { 2016 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 2017 mac->ops.check_link = ixgbe_check_link_t_X550em; 2018 } 2019 break; 2020 case ixgbe_media_type_backplane: 2021 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII || 2022 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) 2023 mac->ops.setup_link = ixgbe_setup_sgmii; 2024 break; 2025 default: 2026 break; 2027 } 2028 } 2029 2030 /** 2031 * ixgbe_get_link_capabilities_x550em - Determines link capabilities 2032 * @hw: pointer to hardware structure 2033 * @speed: pointer to link speed 2034 * @autoneg: TRUE when autoneg or autotry is enabled 2035 */ 2036 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, 2037 ixgbe_link_speed *speed, 2038 bool *autoneg) 2039 { 2040 DEBUGFUNC("ixgbe_get_link_capabilities_X550em"); 2041 2042 2043 if (hw->phy.type == ixgbe_phy_fw) { 2044 *autoneg = TRUE; 2045 *speed = hw->phy.speeds_supported; 2046 return 0; 2047 } 2048 2049 /* SFP */ 2050 if (hw->phy.media_type == ixgbe_media_type_fiber) { 2051 2052 /* CS4227 SFP must not enable auto-negotiation */ 2053 *autoneg = FALSE; 2054 2055 /* Check if 1G SFP module. */ 2056 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 2057 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 2058 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 2059 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) { 2060 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2061 return IXGBE_SUCCESS; 2062 } 2063 2064 /* Link capabilities are based on SFP */ 2065 if (hw->phy.multispeed_fiber) 2066 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2067 IXGBE_LINK_SPEED_1GB_FULL; 2068 else 2069 *speed = IXGBE_LINK_SPEED_10GB_FULL; 2070 } else { 2071 switch (hw->phy.type) { 2072 case ixgbe_phy_ext_1g_t: 2073 case ixgbe_phy_sgmii: 2074 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2075 break; 2076 case ixgbe_phy_x550em_kr: 2077 if (hw->mac.type == ixgbe_mac_X550EM_a) { 2078 /* check different backplane modes */ 2079 if (hw->phy.nw_mng_if_sel & 2080 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) { 2081 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 2082 break; 2083 } else if (hw->device_id == 2084 IXGBE_DEV_ID_X550EM_A_KR_L) { 2085 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2086 break; 2087 } 2088 } 2089 /* fall through */ 2090 default: 2091 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2092 IXGBE_LINK_SPEED_1GB_FULL; 2093 break; 2094 } 2095 *autoneg = TRUE; 2096 } 2097 2098 return IXGBE_SUCCESS; 2099 } 2100 2101 /** 2102 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause 2103 * @hw: pointer to hardware structure 2104 * @lsc: pointer to boolean flag which indicates whether external Base T 2105 * PHY interrupt is lsc 2106 * 2107 * Determime if external Base T PHY interrupt cause is high temperature 2108 * failure alarm or link status change. 2109 * 2110 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 2111 * failure alarm, else return PHY access status. 2112 */ 2113 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc) 2114 { 2115 u32 status; 2116 u16 reg; 2117 2118 *lsc = FALSE; 2119 2120 /* Vendor alarm triggered */ 2121 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2122 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2123 ®); 2124 2125 if (status != IXGBE_SUCCESS || 2126 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN)) 2127 return status; 2128 2129 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */ 2130 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, 2131 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2132 ®); 2133 2134 if (status != IXGBE_SUCCESS || 2135 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2136 IXGBE_MDIO_GLOBAL_ALARM_1_INT))) 2137 return status; 2138 2139 /* Global alarm triggered */ 2140 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, 2141 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2142 ®); 2143 2144 if (status != IXGBE_SUCCESS) 2145 return status; 2146 2147 /* If high temperature failure, then return over temp error and exit */ 2148 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) { 2149 /* power down the PHY in case the PHY FW didn't already */ 2150 ixgbe_set_copper_phy_power(hw, FALSE); 2151 return IXGBE_ERR_OVERTEMP; 2152 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) { 2153 /* device fault alarm triggered */ 2154 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG, 2155 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2156 ®); 2157 2158 if (status != IXGBE_SUCCESS) 2159 return status; 2160 2161 /* if device fault was due to high temp alarm handle and exit */ 2162 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) { 2163 /* power down the PHY in case the PHY FW didn't */ 2164 ixgbe_set_copper_phy_power(hw, FALSE); 2165 return IXGBE_ERR_OVERTEMP; 2166 } 2167 } 2168 2169 /* Vendor alarm 2 triggered */ 2170 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2171 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 2172 2173 if (status != IXGBE_SUCCESS || 2174 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT)) 2175 return status; 2176 2177 /* link connect/disconnect event occurred */ 2178 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2, 2179 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 2180 2181 if (status != IXGBE_SUCCESS) 2182 return status; 2183 2184 /* Indicate LSC */ 2185 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC) 2186 *lsc = TRUE; 2187 2188 return IXGBE_SUCCESS; 2189 } 2190 2191 /** 2192 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts 2193 * @hw: pointer to hardware structure 2194 * 2195 * Enable link status change and temperature failure alarm for the external 2196 * Base T PHY 2197 * 2198 * Returns PHY access status 2199 */ 2200 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw) 2201 { 2202 u32 status; 2203 u16 reg; 2204 bool lsc; 2205 2206 /* Clear interrupt flags */ 2207 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 2208 2209 /* Enable link status change alarm */ 2210 2211 /* Enable the LASI interrupts on X552 devices to receive notifications 2212 * of the link configurations of the external PHY and correspondingly 2213 * support the configuration of the internal iXFI link, since iXFI does 2214 * not support auto-negotiation. This is not required for X553 devices 2215 * having KR support, which performs auto-negotiations and which is used 2216 * as the internal link to the external PHY. Hence adding a check here 2217 * to avoid enabling LASI interrupts for X553 devices. 2218 */ 2219 if (hw->mac.type != ixgbe_mac_X550EM_a) { 2220 status = hw->phy.ops.read_reg(hw, 2221 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2222 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 2223 2224 if (status != IXGBE_SUCCESS) 2225 return status; 2226 2227 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN; 2228 2229 status = hw->phy.ops.write_reg(hw, 2230 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2231 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg); 2232 2233 if (status != IXGBE_SUCCESS) 2234 return status; 2235 } 2236 2237 /* Enable high temperature failure and global fault alarms */ 2238 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2239 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2240 ®); 2241 2242 if (status != IXGBE_SUCCESS) 2243 return status; 2244 2245 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN | 2246 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN); 2247 2248 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2249 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2250 reg); 2251 2252 if (status != IXGBE_SUCCESS) 2253 return status; 2254 2255 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */ 2256 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2257 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2258 ®); 2259 2260 if (status != IXGBE_SUCCESS) 2261 return status; 2262 2263 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2264 IXGBE_MDIO_GLOBAL_ALARM_1_INT); 2265 2266 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2267 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2268 reg); 2269 2270 if (status != IXGBE_SUCCESS) 2271 return status; 2272 2273 /* Enable chip-wide vendor alarm */ 2274 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2275 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2276 ®); 2277 2278 if (status != IXGBE_SUCCESS) 2279 return status; 2280 2281 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN; 2282 2283 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2284 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2285 reg); 2286 2287 return status; 2288 } 2289 2290 /** 2291 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed. 2292 * @hw: pointer to hardware structure 2293 * @speed: link speed 2294 * 2295 * Configures the integrated KR PHY. 2296 **/ 2297 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, 2298 ixgbe_link_speed speed) 2299 { 2300 s32 status; 2301 u32 reg_val; 2302 2303 status = hw->mac.ops.read_iosf_sb_reg(hw, 2304 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2305 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2306 if (status) 2307 return status; 2308 2309 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2310 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | 2311 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); 2312 2313 /* Advertise 10G support. */ 2314 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 2315 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; 2316 2317 /* Advertise 1G support. */ 2318 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 2319 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; 2320 2321 status = hw->mac.ops.write_iosf_sb_reg(hw, 2322 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2323 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2324 2325 if (hw->mac.type == ixgbe_mac_X550EM_a) { 2326 /* Set lane mode to KR auto negotiation */ 2327 status = hw->mac.ops.read_iosf_sb_reg(hw, 2328 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2329 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2330 2331 if (status) 2332 return status; 2333 2334 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2335 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 2336 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2337 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2338 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2339 2340 status = hw->mac.ops.write_iosf_sb_reg(hw, 2341 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2342 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2343 } 2344 2345 return ixgbe_restart_an_internal_phy_x550em(hw); 2346 } 2347 2348 /** 2349 * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs 2350 * @hw: pointer to hardware structure 2351 */ 2352 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw) 2353 { 2354 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 2355 s32 rc; 2356 2357 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 2358 return IXGBE_SUCCESS; 2359 2360 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store); 2361 if (rc) 2362 return rc; 2363 memset(store, 0, sizeof(store)); 2364 2365 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store); 2366 if (rc) 2367 return rc; 2368 2369 return ixgbe_setup_fw_link(hw); 2370 } 2371 2372 /** 2373 * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp 2374 * @hw: pointer to hardware structure 2375 */ 2376 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw) 2377 { 2378 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 2379 s32 rc; 2380 2381 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store); 2382 if (rc) 2383 return rc; 2384 2385 if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) { 2386 ixgbe_shutdown_fw_phy(hw); 2387 return IXGBE_ERR_OVERTEMP; 2388 } 2389 return IXGBE_SUCCESS; 2390 } 2391 2392 /** 2393 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register 2394 * @hw: pointer to hardware structure 2395 * 2396 * Read NW_MNG_IF_SEL register and save field values, and check for valid field 2397 * values. 2398 **/ 2399 static s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw) 2400 { 2401 /* Save NW management interface connected on board. This is used 2402 * to determine internal PHY mode. 2403 */ 2404 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 2405 2406 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set 2407 * PHY address. This register field was has only been used for X552. 2408 */ 2409 if (hw->mac.type == ixgbe_mac_X550EM_a && 2410 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) { 2411 hw->phy.addr = (hw->phy.nw_mng_if_sel & 2412 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 2413 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 2414 } 2415 2416 return IXGBE_SUCCESS; 2417 } 2418 2419 /** 2420 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init 2421 * @hw: pointer to hardware structure 2422 * 2423 * Initialize any function pointers that were not able to be 2424 * set during init_shared_code because the PHY/SFP type was 2425 * not known. Perform the SFP init if necessary. 2426 */ 2427 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) 2428 { 2429 struct ixgbe_phy_info *phy = &hw->phy; 2430 s32 ret_val; 2431 2432 DEBUGFUNC("ixgbe_init_phy_ops_X550em"); 2433 2434 hw->mac.ops.set_lan_id(hw); 2435 ixgbe_read_mng_if_sel_x550em(hw); 2436 2437 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { 2438 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 2439 ixgbe_setup_mux_ctl(hw); 2440 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em; 2441 } 2442 2443 switch (hw->device_id) { 2444 case IXGBE_DEV_ID_X550EM_A_1G_T: 2445 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2446 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22; 2447 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22; 2448 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a; 2449 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a; 2450 phy->ops.check_overtemp = ixgbe_check_overtemp_fw; 2451 if (hw->bus.lan_id) 2452 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; 2453 else 2454 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; 2455 2456 break; 2457 case IXGBE_DEV_ID_X550EM_A_10G_T: 2458 case IXGBE_DEV_ID_X550EM_A_SFP: 2459 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a; 2460 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a; 2461 if (hw->bus.lan_id) 2462 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; 2463 else 2464 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; 2465 break; 2466 case IXGBE_DEV_ID_X550EM_X_SFP: 2467 /* set up for CS4227 usage */ 2468 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 2469 break; 2470 case IXGBE_DEV_ID_X550EM_X_1G_T: 2471 phy->ops.read_reg_mdi = NULL; 2472 phy->ops.write_reg_mdi = NULL; 2473 break; 2474 default: 2475 break; 2476 } 2477 2478 /* Identify the PHY or SFP module */ 2479 ret_val = phy->ops.identify(hw); 2480 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED || 2481 ret_val == IXGBE_ERR_PHY_ADDR_INVALID) 2482 return ret_val; 2483 2484 /* Setup function pointers based on detected hardware */ 2485 ixgbe_init_mac_link_ops_X550em(hw); 2486 if (phy->sfp_type != ixgbe_sfp_type_unknown) 2487 phy->ops.reset = NULL; 2488 2489 /* Set functions pointers based on phy type */ 2490 switch (hw->phy.type) { 2491 case ixgbe_phy_x550em_kx4: 2492 phy->ops.setup_link = NULL; 2493 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 2494 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 2495 break; 2496 case ixgbe_phy_x550em_kr: 2497 phy->ops.setup_link = ixgbe_setup_kr_x550em; 2498 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 2499 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 2500 break; 2501 case ixgbe_phy_ext_1g_t: 2502 /* link is managed by FW */ 2503 phy->ops.setup_link = NULL; 2504 phy->ops.reset = NULL; 2505 break; 2506 case ixgbe_phy_x550em_xfi: 2507 /* link is managed by HW */ 2508 phy->ops.setup_link = NULL; 2509 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 2510 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 2511 break; 2512 case ixgbe_phy_x550em_ext_t: 2513 /* If internal link mode is XFI, then setup iXFI internal link, 2514 * else setup KR now. 2515 */ 2516 phy->ops.setup_internal_link = 2517 ixgbe_setup_internal_phy_t_x550em; 2518 2519 /* setup SW LPLU only for first revision of X550EM_x */ 2520 if ((hw->mac.type == ixgbe_mac_X550EM_x) && 2521 !(IXGBE_FUSES0_REV_MASK & 2522 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))) 2523 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em; 2524 2525 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; 2526 phy->ops.reset = ixgbe_reset_phy_t_X550em; 2527 break; 2528 case ixgbe_phy_sgmii: 2529 phy->ops.setup_link = NULL; 2530 break; 2531 case ixgbe_phy_fw: 2532 phy->ops.setup_link = ixgbe_setup_fw_link; 2533 phy->ops.reset = ixgbe_reset_phy_fw; 2534 break; 2535 default: 2536 break; 2537 } 2538 return ret_val; 2539 } 2540 2541 /** 2542 * ixgbe_set_mdio_speed - Set MDIO clock speed 2543 * @hw: pointer to hardware structure 2544 */ 2545 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw) 2546 { 2547 u32 hlreg0; 2548 2549 switch (hw->device_id) { 2550 case IXGBE_DEV_ID_X550EM_X_10G_T: 2551 case IXGBE_DEV_ID_X550EM_A_SGMII: 2552 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 2553 case IXGBE_DEV_ID_X550EM_A_10G_T: 2554 case IXGBE_DEV_ID_X550EM_A_SFP: 2555 case IXGBE_DEV_ID_X550EM_A_QSFP: 2556 /* Config MDIO clock speed before the first MDIO PHY access */ 2557 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 2558 hlreg0 &= ~IXGBE_HLREG0_MDCSPD; 2559 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 2560 break; 2561 case IXGBE_DEV_ID_X550EM_A_1G_T: 2562 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2563 /* Select fast MDIO clock speed for these devices */ 2564 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 2565 hlreg0 |= IXGBE_HLREG0_MDCSPD; 2566 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 2567 break; 2568 default: 2569 break; 2570 } 2571 } 2572 2573 /** 2574 * ixgbe_reset_hw_X550em - Perform hardware reset 2575 * @hw: pointer to hardware structure 2576 * 2577 * Resets the hardware by resetting the transmit and receive units, masks 2578 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 2579 * reset. 2580 */ 2581 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) 2582 { 2583 ixgbe_link_speed link_speed; 2584 s32 status; 2585 u32 ctrl = 0; 2586 u32 i; 2587 bool link_up = FALSE; 2588 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2589 2590 DEBUGFUNC("ixgbe_reset_hw_X550em"); 2591 2592 /* Call adapter stop to disable Tx/Rx and clear interrupts */ 2593 status = hw->mac.ops.stop_adapter(hw); 2594 if (status != IXGBE_SUCCESS) { 2595 DEBUGOUT1("Failed to stop adapter, STATUS = %d\n", status); 2596 return status; 2597 } 2598 /* flush pending Tx transactions */ 2599 ixgbe_clear_tx_pending(hw); 2600 2601 ixgbe_set_mdio_speed(hw); 2602 2603 /* PHY ops must be identified and initialized prior to reset */ 2604 status = hw->phy.ops.init(hw); 2605 2606 if (status) 2607 DEBUGOUT1("Failed to initialize PHY ops, STATUS = %d\n", 2608 status); 2609 2610 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED || 2611 status == IXGBE_ERR_PHY_ADDR_INVALID) { 2612 DEBUGOUT("Returning from reset HW due to PHY init failure\n"); 2613 return status; 2614 } 2615 2616 /* start the external PHY */ 2617 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 2618 status = ixgbe_init_ext_t_x550em(hw); 2619 if (status) { 2620 DEBUGOUT1("Failed to start the external PHY, STATUS = %d\n", 2621 status); 2622 return status; 2623 } 2624 } 2625 2626 /* Setup SFP module if there is one present. */ 2627 if (hw->phy.sfp_setup_needed) { 2628 status = hw->mac.ops.setup_sfp(hw); 2629 hw->phy.sfp_setup_needed = FALSE; 2630 } 2631 2632 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 2633 return status; 2634 2635 /* Reset PHY */ 2636 if (!hw->phy.reset_disable && hw->phy.ops.reset) { 2637 if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP) 2638 return IXGBE_ERR_OVERTEMP; 2639 } 2640 2641 mac_reset_top: 2642 /* Issue global reset to the MAC. Needs to be SW reset if link is up. 2643 * If link reset is used when link is up, it might reset the PHY when 2644 * mng is using it. If link is down or the flag to force full link 2645 * reset is set, then perform link reset. 2646 */ 2647 ctrl = IXGBE_CTRL_LNK_RST; 2648 if (!hw->force_full_reset) { 2649 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE); 2650 if (link_up) 2651 ctrl = IXGBE_CTRL_RST; 2652 } 2653 2654 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 2655 if (status != IXGBE_SUCCESS) { 2656 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 2657 "semaphore failed with %d", status); 2658 return IXGBE_ERR_SWFW_SYNC; 2659 } 2660 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 2661 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 2662 IXGBE_WRITE_FLUSH(hw); 2663 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2664 2665 /* Poll for reset bit to self-clear meaning reset is complete */ 2666 for (i = 0; i < 10; i++) { 2667 usec_delay(1); 2668 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 2669 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 2670 break; 2671 } 2672 2673 if (ctrl & IXGBE_CTRL_RST_MASK) { 2674 status = IXGBE_ERR_RESET_FAILED; 2675 DEBUGOUT("Reset polling failed to complete.\n"); 2676 } 2677 2678 msec_delay(50); 2679 2680 /* Double resets are required for recovery from certain error 2681 * conditions. Between resets, it is necessary to stall to 2682 * allow time for any pending HW events to complete. 2683 */ 2684 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 2685 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 2686 goto mac_reset_top; 2687 } 2688 2689 /* Store the permanent mac address */ 2690 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 2691 2692 /* Store MAC address from RAR0, clear receive address registers, and 2693 * clear the multicast table. Also reset num_rar_entries to 128, 2694 * since we modify this value when programming the SAN MAC address. 2695 */ 2696 hw->mac.num_rar_entries = 128; 2697 hw->mac.ops.init_rx_addrs(hw); 2698 2699 ixgbe_set_mdio_speed(hw); 2700 2701 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) 2702 ixgbe_setup_mux_ctl(hw); 2703 2704 if (status != IXGBE_SUCCESS) 2705 DEBUGOUT1("Reset HW failed, STATUS = %d\n", status); 2706 2707 return status; 2708 } 2709 2710 /** 2711 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. 2712 * @hw: pointer to hardware structure 2713 */ 2714 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) 2715 { 2716 u32 status; 2717 u16 reg; 2718 2719 status = hw->phy.ops.read_reg(hw, 2720 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 2721 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 2722 ®); 2723 2724 if (status != IXGBE_SUCCESS) 2725 return status; 2726 2727 /* If PHY FW reset completed bit is set then this is the first 2728 * SW instance after a power on so the PHY FW must be un-stalled. 2729 */ 2730 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 2731 status = hw->phy.ops.read_reg(hw, 2732 IXGBE_MDIO_GLOBAL_RES_PR_10, 2733 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2734 ®); 2735 2736 if (status != IXGBE_SUCCESS) 2737 return status; 2738 2739 reg &= ~IXGBE_MDIO_POWER_UP_STALL; 2740 2741 status = hw->phy.ops.write_reg(hw, 2742 IXGBE_MDIO_GLOBAL_RES_PR_10, 2743 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2744 reg); 2745 2746 if (status != IXGBE_SUCCESS) 2747 return status; 2748 } 2749 2750 return status; 2751 } 2752 2753 /** 2754 * ixgbe_setup_kr_x550em - Configure the KR PHY. 2755 * @hw: pointer to hardware structure 2756 **/ 2757 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) 2758 { 2759 /* leave link alone for 2.5G */ 2760 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL) 2761 return IXGBE_SUCCESS; 2762 2763 if (ixgbe_check_reset_blocked(hw)) 2764 return 0; 2765 2766 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); 2767 } 2768 2769 /** 2770 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP 2771 * @hw: pointer to hardware structure 2772 * 2773 * Configure the external PHY and the integrated KR PHY for SFP support. 2774 **/ 2775 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, 2776 ixgbe_link_speed speed, 2777 bool autoneg_wait_to_complete) 2778 { 2779 s32 ret_val; 2780 u16 reg_slice, reg_val; 2781 bool setup_linear = FALSE; 2782 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 2783 2784 /* Check if SFP module is supported and linear */ 2785 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 2786 2787 /* If no SFP module present, then return success. Return success since 2788 * there is no reason to configure CS4227 and SFP not present error is 2789 * not excepted in the setup MAC link flow. 2790 */ 2791 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 2792 return IXGBE_SUCCESS; 2793 2794 if (ret_val != IXGBE_SUCCESS) 2795 return ret_val; 2796 2797 /* Configure internal PHY for KR/KX. */ 2798 ixgbe_setup_kr_speed_x550em(hw, speed); 2799 2800 /* Configure CS4227 LINE side to proper mode. */ 2801 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + 2802 (hw->bus.lan_id << 12); 2803 if (setup_linear) 2804 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 2805 else 2806 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 2807 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice, 2808 reg_val); 2809 return ret_val; 2810 } 2811 2812 /** 2813 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode 2814 * @hw: pointer to hardware structure 2815 * @speed: the link speed to force 2816 * 2817 * Configures the integrated PHY for native SFI mode. Used to connect the 2818 * internal PHY directly to an SFP cage, without autonegotiation. 2819 **/ 2820 static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 2821 { 2822 struct ixgbe_mac_info *mac = &hw->mac; 2823 s32 status; 2824 u32 reg_val; 2825 2826 /* Disable all AN and force speed to 10G Serial. */ 2827 status = mac->ops.read_iosf_sb_reg(hw, 2828 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2829 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2830 if (status != IXGBE_SUCCESS) 2831 return status; 2832 2833 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2834 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2835 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2836 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2837 2838 /* Select forced link speed for internal PHY. */ 2839 switch (*speed) { 2840 case IXGBE_LINK_SPEED_10GB_FULL: 2841 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G; 2842 break; 2843 case IXGBE_LINK_SPEED_1GB_FULL: 2844 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 2845 break; 2846 case 0: 2847 /* media none (linkdown) */ 2848 break; 2849 default: 2850 /* Other link speeds are not supported by internal PHY. */ 2851 return IXGBE_ERR_LINK_SETUP; 2852 } 2853 2854 status = mac->ops.write_iosf_sb_reg(hw, 2855 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2856 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2857 2858 /* Toggle port SW reset by AN reset. */ 2859 status = ixgbe_restart_an_internal_phy_x550em(hw); 2860 2861 return status; 2862 } 2863 2864 /** 2865 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP 2866 * @hw: pointer to hardware structure 2867 * 2868 * Configure the the integrated PHY for SFP support. 2869 **/ 2870 static s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, 2871 ixgbe_link_speed speed, 2872 bool autoneg_wait_to_complete) 2873 { 2874 s32 ret_val; 2875 u16 reg_phy_ext; 2876 bool setup_linear = FALSE; 2877 u32 reg_slice, reg_phy_int, slice_offset; 2878 2879 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 2880 2881 /* Check if SFP module is supported and linear */ 2882 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 2883 2884 /* If no SFP module present, then return success. Return success since 2885 * SFP not present error is not excepted in the setup MAC link flow. 2886 */ 2887 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 2888 return IXGBE_SUCCESS; 2889 2890 if (ret_val != IXGBE_SUCCESS) 2891 return ret_val; 2892 2893 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) { 2894 /* Configure internal PHY for native SFI based on module type */ 2895 ret_val = hw->mac.ops.read_iosf_sb_reg(hw, 2896 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2897 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int); 2898 2899 if (ret_val != IXGBE_SUCCESS) 2900 return ret_val; 2901 2902 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA; 2903 if (!setup_linear) 2904 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR; 2905 2906 ret_val = hw->mac.ops.write_iosf_sb_reg(hw, 2907 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2908 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int); 2909 2910 if (ret_val != IXGBE_SUCCESS) 2911 return ret_val; 2912 2913 /* Setup SFI internal link. */ 2914 ret_val = ixgbe_setup_sfi_x550a(hw, &speed); 2915 } else { 2916 /* Configure internal PHY for KR/KX. */ 2917 ixgbe_setup_kr_speed_x550em(hw, speed); 2918 2919 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) { 2920 /* Find Address */ 2921 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n"); 2922 return IXGBE_ERR_PHY_ADDR_INVALID; 2923 } 2924 2925 /* Get external PHY SKU id */ 2926 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU, 2927 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 2928 2929 if (ret_val != IXGBE_SUCCESS) 2930 return ret_val; 2931 2932 /* When configuring quad port CS4223, the MAC instance is part 2933 * of the slice offset. 2934 */ 2935 if (reg_phy_ext == IXGBE_CS4223_SKU_ID) 2936 slice_offset = (hw->bus.lan_id + 2937 (hw->bus.instance_id << 1)) << 12; 2938 else 2939 slice_offset = hw->bus.lan_id << 12; 2940 2941 /* Configure CS4227/CS4223 LINE side to proper mode. */ 2942 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset; 2943 2944 ret_val = hw->phy.ops.read_reg(hw, reg_slice, 2945 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 2946 2947 if (ret_val != IXGBE_SUCCESS) 2948 return ret_val; 2949 2950 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) | 2951 (IXGBE_CS4227_EDC_MODE_SR << 1)); 2952 2953 if (setup_linear) 2954 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 2955 else 2956 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 2957 ret_val = hw->phy.ops.write_reg(hw, reg_slice, 2958 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext); 2959 2960 /* Flush previous write with a read */ 2961 ret_val = hw->phy.ops.read_reg(hw, reg_slice, 2962 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 2963 } 2964 return ret_val; 2965 } 2966 2967 /** 2968 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration 2969 * @hw: pointer to hardware structure 2970 * 2971 * iXfI configuration needed for ixgbe_mac_X550EM_x devices. 2972 **/ 2973 static s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw) 2974 { 2975 struct ixgbe_mac_info *mac = &hw->mac; 2976 s32 status; 2977 u32 reg_val; 2978 2979 /* Disable training protocol FSM. */ 2980 status = mac->ops.read_iosf_sb_reg(hw, 2981 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 2982 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2983 if (status != IXGBE_SUCCESS) 2984 return status; 2985 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; 2986 status = mac->ops.write_iosf_sb_reg(hw, 2987 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 2988 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2989 if (status != IXGBE_SUCCESS) 2990 return status; 2991 2992 /* Disable Flex from training TXFFE. */ 2993 status = mac->ops.read_iosf_sb_reg(hw, 2994 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 2995 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2996 if (status != IXGBE_SUCCESS) 2997 return status; 2998 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 2999 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 3000 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 3001 status = mac->ops.write_iosf_sb_reg(hw, 3002 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 3003 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3004 if (status != IXGBE_SUCCESS) 3005 return status; 3006 status = mac->ops.read_iosf_sb_reg(hw, 3007 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 3008 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3009 if (status != IXGBE_SUCCESS) 3010 return status; 3011 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 3012 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 3013 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 3014 status = mac->ops.write_iosf_sb_reg(hw, 3015 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 3016 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3017 if (status != IXGBE_SUCCESS) 3018 return status; 3019 3020 /* Enable override for coefficients. */ 3021 status = mac->ops.read_iosf_sb_reg(hw, 3022 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 3023 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3024 if (status != IXGBE_SUCCESS) 3025 return status; 3026 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; 3027 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; 3028 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; 3029 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; 3030 status = mac->ops.write_iosf_sb_reg(hw, 3031 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 3032 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3033 return status; 3034 } 3035 3036 /** 3037 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. 3038 * @hw: pointer to hardware structure 3039 * @speed: the link speed to force 3040 * 3041 * Configures the integrated KR PHY to use iXFI mode. Used to connect an 3042 * internal and external PHY at a specific speed, without autonegotiation. 3043 **/ 3044 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 3045 { 3046 struct ixgbe_mac_info *mac = &hw->mac; 3047 s32 status; 3048 u32 reg_val; 3049 3050 /* iXFI is only supported with X552 */ 3051 if (mac->type != ixgbe_mac_X550EM_x) 3052 return IXGBE_ERR_LINK_SETUP; 3053 3054 /* Disable AN and force speed to 10G Serial. */ 3055 status = mac->ops.read_iosf_sb_reg(hw, 3056 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 3057 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3058 if (status != IXGBE_SUCCESS) 3059 return status; 3060 3061 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 3062 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 3063 3064 /* Select forced link speed for internal PHY. */ 3065 switch (*speed) { 3066 case IXGBE_LINK_SPEED_10GB_FULL: 3067 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 3068 break; 3069 case IXGBE_LINK_SPEED_1GB_FULL: 3070 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 3071 break; 3072 default: 3073 /* Other link speeds are not supported by internal KR PHY. */ 3074 return IXGBE_ERR_LINK_SETUP; 3075 } 3076 3077 status = mac->ops.write_iosf_sb_reg(hw, 3078 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 3079 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3080 if (status != IXGBE_SUCCESS) 3081 return status; 3082 3083 /* Additional configuration needed for x550em_x */ 3084 if (hw->mac.type == ixgbe_mac_X550EM_x) { 3085 status = ixgbe_setup_ixfi_x550em_x(hw); 3086 if (status != IXGBE_SUCCESS) 3087 return status; 3088 } 3089 3090 /* Toggle port SW reset by AN reset. */ 3091 status = ixgbe_restart_an_internal_phy_x550em(hw); 3092 3093 return status; 3094 } 3095 3096 /** 3097 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status 3098 * @hw: address of hardware structure 3099 * @link_up: address of boolean to indicate link status 3100 * 3101 * Returns error code if unable to get link status. 3102 */ 3103 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up) 3104 { 3105 u32 ret; 3106 u16 autoneg_status; 3107 3108 *link_up = FALSE; 3109 3110 /* read this twice back to back to indicate current status */ 3111 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 3112 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3113 &autoneg_status); 3114 if (ret != IXGBE_SUCCESS) 3115 return ret; 3116 3117 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 3118 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3119 &autoneg_status); 3120 if (ret != IXGBE_SUCCESS) 3121 return ret; 3122 3123 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS); 3124 3125 return IXGBE_SUCCESS; 3126 } 3127 3128 /** 3129 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link 3130 * @hw: point to hardware structure 3131 * 3132 * Configures the link between the integrated KR PHY and the external X557 PHY 3133 * The driver will call this function when it gets a link status change 3134 * interrupt from the X557 PHY. This function configures the link speed 3135 * between the PHYs to match the link speed of the BASE-T link. 3136 * 3137 * A return of a non-zero value indicates an error, and the base driver should 3138 * not report link up. 3139 */ 3140 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw) 3141 { 3142 ixgbe_link_speed force_speed; 3143 bool link_up; 3144 u32 status; 3145 u16 speed; 3146 3147 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 3148 return IXGBE_ERR_CONFIG; 3149 3150 if (hw->mac.type == ixgbe_mac_X550EM_x && 3151 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 3152 /* If link is down, there is no setup necessary so return */ 3153 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3154 if (status != IXGBE_SUCCESS) 3155 return status; 3156 3157 if (!link_up) 3158 return IXGBE_SUCCESS; 3159 3160 status = hw->phy.ops.read_reg(hw, 3161 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 3162 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3163 &speed); 3164 if (status != IXGBE_SUCCESS) 3165 return status; 3166 3167 /* If link is still down - no setup is required so return */ 3168 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3169 if (status != IXGBE_SUCCESS) 3170 return status; 3171 if (!link_up) 3172 return IXGBE_SUCCESS; 3173 3174 /* clear everything but the speed and duplex bits */ 3175 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK; 3176 3177 switch (speed) { 3178 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL: 3179 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 3180 break; 3181 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL: 3182 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 3183 break; 3184 default: 3185 /* Internal PHY does not support anything else */ 3186 return IXGBE_ERR_INVALID_LINK_SETTINGS; 3187 } 3188 3189 return ixgbe_setup_ixfi_x550em(hw, &force_speed); 3190 } else { 3191 speed = IXGBE_LINK_SPEED_10GB_FULL | 3192 IXGBE_LINK_SPEED_1GB_FULL; 3193 return ixgbe_setup_kr_speed_x550em(hw, speed); 3194 } 3195 } 3196 3197 /** 3198 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback. 3199 * @hw: pointer to hardware structure 3200 * 3201 * Configures the integrated KR PHY to use internal loopback mode. 3202 **/ 3203 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw) 3204 { 3205 s32 status; 3206 u32 reg_val; 3207 3208 /* Disable AN and force speed to 10G Serial. */ 3209 status = hw->mac.ops.read_iosf_sb_reg(hw, 3210 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 3211 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3212 if (status != IXGBE_SUCCESS) 3213 return status; 3214 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 3215 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 3216 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 3217 status = hw->mac.ops.write_iosf_sb_reg(hw, 3218 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 3219 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3220 if (status != IXGBE_SUCCESS) 3221 return status; 3222 3223 /* Set near-end loopback clocks. */ 3224 status = hw->mac.ops.read_iosf_sb_reg(hw, 3225 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id), 3226 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3227 if (status != IXGBE_SUCCESS) 3228 return status; 3229 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B; 3230 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS; 3231 status = hw->mac.ops.write_iosf_sb_reg(hw, 3232 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id), 3233 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3234 if (status != IXGBE_SUCCESS) 3235 return status; 3236 3237 /* Set loopback enable. */ 3238 status = hw->mac.ops.read_iosf_sb_reg(hw, 3239 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id), 3240 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3241 if (status != IXGBE_SUCCESS) 3242 return status; 3243 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK; 3244 status = hw->mac.ops.write_iosf_sb_reg(hw, 3245 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id), 3246 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3247 if (status != IXGBE_SUCCESS) 3248 return status; 3249 3250 /* Training bypass. */ 3251 status = hw->mac.ops.read_iosf_sb_reg(hw, 3252 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 3253 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3254 if (status != IXGBE_SUCCESS) 3255 return status; 3256 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS; 3257 status = hw->mac.ops.write_iosf_sb_reg(hw, 3258 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 3259 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3260 3261 return status; 3262 } 3263 3264 /** 3265 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 3266 * assuming that the semaphore is already obtained. 3267 * @hw: pointer to hardware structure 3268 * @offset: offset of word in the EEPROM to read 3269 * @data: word read from the EEPROM 3270 * 3271 * Reads a 16 bit word from the EEPROM using the hostif. 3272 **/ 3273 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data) 3274 { 3275 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 3276 struct ixgbe_hic_read_shadow_ram buffer; 3277 s32 status; 3278 3279 DEBUGFUNC("ixgbe_read_ee_hostif_X550"); 3280 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 3281 buffer.hdr.req.buf_lenh = 0; 3282 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 3283 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 3284 3285 /* convert offset from words to bytes */ 3286 buffer.address = IXGBE_CPU_TO_BE32(offset * 2); 3287 /* one word */ 3288 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16)); 3289 buffer.pad2 = 0; 3290 buffer.pad3 = 0; 3291 3292 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 3293 if (status) 3294 return status; 3295 3296 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 3297 IXGBE_HI_COMMAND_TIMEOUT); 3298 if (!status) { 3299 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 3300 FW_NVM_DATA_OFFSET); 3301 } 3302 3303 hw->mac.ops.release_swfw_sync(hw, mask); 3304 return status; 3305 } 3306 3307 /** 3308 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif 3309 * @hw: pointer to hardware structure 3310 * @offset: offset of word in the EEPROM to read 3311 * @words: number of words 3312 * @data: word(s) read from the EEPROM 3313 * 3314 * Reads a 16 bit word(s) from the EEPROM using the hostif. 3315 **/ 3316 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 3317 u16 offset, u16 words, u16 *data) 3318 { 3319 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 3320 struct ixgbe_hic_read_shadow_ram buffer; 3321 u32 current_word = 0; 3322 u16 words_to_read; 3323 s32 status; 3324 u32 i; 3325 3326 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550"); 3327 3328 /* Take semaphore for the entire operation. */ 3329 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 3330 if (status) { 3331 DEBUGOUT("EEPROM read buffer - semaphore failed\n"); 3332 return status; 3333 } 3334 3335 while (words) { 3336 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 3337 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 3338 else 3339 words_to_read = words; 3340 3341 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 3342 buffer.hdr.req.buf_lenh = 0; 3343 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 3344 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 3345 3346 /* convert offset from words to bytes */ 3347 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2); 3348 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2); 3349 buffer.pad2 = 0; 3350 buffer.pad3 = 0; 3351 3352 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 3353 IXGBE_HI_COMMAND_TIMEOUT); 3354 3355 if (status) { 3356 DEBUGOUT("Host interface command failed\n"); 3357 goto out; 3358 } 3359 3360 for (i = 0; i < words_to_read; i++) { 3361 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + 3362 2 * i; 3363 u32 value = IXGBE_READ_REG(hw, reg); 3364 3365 data[current_word] = (u16)(value & 0xffff); 3366 current_word++; 3367 i++; 3368 if (i < words_to_read) { 3369 value >>= 16; 3370 data[current_word] = (u16)(value & 0xffff); 3371 current_word++; 3372 } 3373 } 3374 words -= words_to_read; 3375 } 3376 3377 out: 3378 hw->mac.ops.release_swfw_sync(hw, mask); 3379 return status; 3380 } 3381 3382 /** 3383 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 3384 * @hw: pointer to hardware structure 3385 * @offset: offset of word in the EEPROM to write 3386 * @data: word write to the EEPROM 3387 * 3388 * Write a 16 bit word to the EEPROM using the hostif. 3389 **/ 3390 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 3391 u16 data) 3392 { 3393 s32 status; 3394 struct ixgbe_hic_write_shadow_ram buffer; 3395 3396 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550"); 3397 3398 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; 3399 buffer.hdr.req.buf_lenh = 0; 3400 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; 3401 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 3402 3403 /* one word */ 3404 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16)); 3405 buffer.data = data; 3406 buffer.address = IXGBE_CPU_TO_BE32(offset * 2); 3407 3408 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 3409 sizeof(buffer), 3410 IXGBE_HI_COMMAND_TIMEOUT, FALSE); 3411 3412 return status; 3413 } 3414 3415 /** 3416 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 3417 * @hw: pointer to hardware structure 3418 * @offset: offset of word in the EEPROM to write 3419 * @data: word write to the EEPROM 3420 * 3421 * Write a 16 bit word to the EEPROM using the hostif. 3422 **/ 3423 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, 3424 u16 data) 3425 { 3426 s32 status = IXGBE_SUCCESS; 3427 3428 DEBUGFUNC("ixgbe_write_ee_hostif_X550"); 3429 3430 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 3431 IXGBE_SUCCESS) { 3432 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); 3433 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 3434 } else { 3435 DEBUGOUT("write ee hostif failed to get semaphore"); 3436 status = IXGBE_ERR_SWFW_SYNC; 3437 } 3438 3439 return status; 3440 } 3441 3442 /** 3443 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif 3444 * @hw: pointer to hardware structure 3445 * @offset: offset of word in the EEPROM to write 3446 * @words: number of words 3447 * @data: word(s) write to the EEPROM 3448 * 3449 * Write a 16 bit word(s) to the EEPROM using the hostif. 3450 **/ 3451 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 3452 u16 offset, u16 words, u16 *data) 3453 { 3454 s32 status = IXGBE_SUCCESS; 3455 u32 i = 0; 3456 3457 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550"); 3458 3459 /* Take semaphore for the entire operation. */ 3460 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 3461 if (status != IXGBE_SUCCESS) { 3462 DEBUGOUT("EEPROM write buffer - semaphore failed\n"); 3463 goto out; 3464 } 3465 3466 for (i = 0; i < words; i++) { 3467 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, 3468 data[i]); 3469 3470 if (status != IXGBE_SUCCESS) { 3471 DEBUGOUT("Eeprom buffered write failed\n"); 3472 break; 3473 } 3474 } 3475 3476 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 3477 out: 3478 3479 return status; 3480 } 3481 3482 /** 3483 * ixgbe_checksum_ptr_x550 - Checksum one pointer region 3484 * @hw: pointer to hardware structure 3485 * @ptr: pointer offset in eeprom 3486 * @size: size of section pointed by ptr, if 0 first word will be used as size 3487 * @csum: address of checksum to update 3488 * 3489 * Returns error status for any failure 3490 */ 3491 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, 3492 u16 size, u16 *csum, u16 *buffer, 3493 u32 buffer_size) 3494 { 3495 u16 buf[256]; 3496 s32 status; 3497 u16 length, bufsz, i, start; 3498 u16 *local_buffer; 3499 3500 bufsz = sizeof(buf) / sizeof(buf[0]); 3501 3502 /* Read a chunk at the pointer location */ 3503 if (!buffer) { 3504 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); 3505 if (status) { 3506 DEBUGOUT("Failed to read EEPROM image\n"); 3507 return status; 3508 } 3509 local_buffer = buf; 3510 } else { 3511 if (buffer_size < ptr) 3512 return IXGBE_ERR_PARAM; 3513 local_buffer = &buffer[ptr]; 3514 } 3515 3516 if (size) { 3517 start = 0; 3518 length = size; 3519 } else { 3520 start = 1; 3521 length = local_buffer[0]; 3522 3523 /* Skip pointer section if length is invalid. */ 3524 if (length == 0xFFFF || length == 0 || 3525 (ptr + length) >= hw->eeprom.word_size) 3526 return IXGBE_SUCCESS; 3527 } 3528 3529 if (buffer && ((u32)start + (u32)length > buffer_size)) 3530 return IXGBE_ERR_PARAM; 3531 3532 for (i = start; length; i++, length--) { 3533 if (i == bufsz && !buffer) { 3534 ptr += bufsz; 3535 i = 0; 3536 if (length < bufsz) 3537 bufsz = length; 3538 3539 /* Read a chunk at the pointer location */ 3540 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, 3541 bufsz, buf); 3542 if (status) { 3543 DEBUGOUT("Failed to read EEPROM image\n"); 3544 return status; 3545 } 3546 } 3547 *csum += local_buffer[i]; 3548 } 3549 return IXGBE_SUCCESS; 3550 } 3551 3552 /** 3553 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum 3554 * @hw: pointer to hardware structure 3555 * @buffer: pointer to buffer containing calculated checksum 3556 * @buffer_size: size of buffer 3557 * 3558 * Returns a negative error code on error, or the 16-bit checksum 3559 **/ 3560 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size) 3561 { 3562 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1]; 3563 u16 *local_buffer; 3564 s32 status; 3565 u16 checksum = 0; 3566 u16 pointer, i, size; 3567 3568 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550"); 3569 3570 hw->eeprom.ops.init_params(hw); 3571 3572 if (!buffer) { 3573 /* Read pointer area */ 3574 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, 3575 IXGBE_EEPROM_LAST_WORD + 1, 3576 eeprom_ptrs); 3577 if (status) { 3578 DEBUGOUT("Failed to read EEPROM image\n"); 3579 return status; 3580 } 3581 local_buffer = eeprom_ptrs; 3582 } else { 3583 if (buffer_size < IXGBE_EEPROM_LAST_WORD) 3584 return IXGBE_ERR_PARAM; 3585 local_buffer = buffer; 3586 } 3587 3588 /* 3589 * For X550 hardware include 0x0-0x41 in the checksum, skip the 3590 * checksum word itself 3591 */ 3592 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++) 3593 if (i != IXGBE_EEPROM_CHECKSUM) 3594 checksum += local_buffer[i]; 3595 3596 /* 3597 * Include all data from pointers 0x3, 0x6-0xE. This excludes the 3598 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 3599 */ 3600 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) { 3601 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 3602 continue; 3603 3604 pointer = local_buffer[i]; 3605 3606 /* Skip pointer section if the pointer is invalid. */ 3607 if (pointer == 0xFFFF || pointer == 0 || 3608 pointer >= hw->eeprom.word_size) 3609 continue; 3610 3611 switch (i) { 3612 case IXGBE_PCIE_GENERAL_PTR: 3613 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE; 3614 break; 3615 case IXGBE_PCIE_CONFIG0_PTR: 3616 case IXGBE_PCIE_CONFIG1_PTR: 3617 size = IXGBE_PCIE_CONFIG_SIZE; 3618 break; 3619 default: 3620 size = 0; 3621 break; 3622 } 3623 3624 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, 3625 buffer, buffer_size); 3626 if (status) 3627 return status; 3628 } 3629 3630 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 3631 3632 return (s32)checksum; 3633 } 3634 3635 /** 3636 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum 3637 * @hw: pointer to hardware structure 3638 * 3639 * Returns a negative error code on error, or the 16-bit checksum 3640 **/ 3641 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) 3642 { 3643 return ixgbe_calc_checksum_X550(hw, NULL, 0); 3644 } 3645 3646 /** 3647 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum 3648 * @hw: pointer to hardware structure 3649 * @checksum_val: calculated checksum 3650 * 3651 * Performs checksum calculation and validates the EEPROM checksum. If the 3652 * caller does not need checksum_val, the value can be NULL. 3653 **/ 3654 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val) 3655 { 3656 s32 status; 3657 u16 checksum; 3658 u16 read_checksum = 0; 3659 3660 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550"); 3661 3662 /* Read the first word from the EEPROM. If this times out or fails, do 3663 * not continue or we could be in for a very long wait while every 3664 * EEPROM read fails 3665 */ 3666 status = hw->eeprom.ops.read(hw, 0, &checksum); 3667 if (status) { 3668 DEBUGOUT("EEPROM read failed\n"); 3669 return status; 3670 } 3671 3672 status = hw->eeprom.ops.calc_checksum(hw); 3673 if (status < 0) 3674 return status; 3675 3676 checksum = (u16)(status & 0xffff); 3677 3678 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 3679 &read_checksum); 3680 if (status) 3681 return status; 3682 3683 /* Verify read checksum from EEPROM is the same as 3684 * calculated checksum 3685 */ 3686 if (read_checksum != checksum) { 3687 status = IXGBE_ERR_EEPROM_CHECKSUM; 3688 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 3689 "Invalid EEPROM checksum"); 3690 } 3691 3692 /* If the user cares, return the calculated checksum */ 3693 if (checksum_val) 3694 *checksum_val = checksum; 3695 3696 return status; 3697 } 3698 3699 /** 3700 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash 3701 * @hw: pointer to hardware structure 3702 * 3703 * After writing EEPROM to shadow RAM using EEWR register, software calculates 3704 * checksum and updates the EEPROM and instructs the hardware to update 3705 * the flash. 3706 **/ 3707 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) 3708 { 3709 s32 status; 3710 u16 checksum = 0; 3711 3712 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550"); 3713 3714 /* Read the first word from the EEPROM. If this times out or fails, do 3715 * not continue or we could be in for a very long wait while every 3716 * EEPROM read fails 3717 */ 3718 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); 3719 if (status) { 3720 DEBUGOUT("EEPROM read failed\n"); 3721 return status; 3722 } 3723 3724 status = ixgbe_calc_eeprom_checksum_X550(hw); 3725 if (status < 0) 3726 return status; 3727 3728 checksum = (u16)(status & 0xffff); 3729 3730 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 3731 checksum); 3732 if (status) 3733 return status; 3734 3735 status = ixgbe_update_flash_X550(hw); 3736 3737 return status; 3738 } 3739 3740 /** 3741 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device 3742 * @hw: pointer to hardware structure 3743 * 3744 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash. 3745 **/ 3746 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) 3747 { 3748 s32 status = IXGBE_SUCCESS; 3749 union ixgbe_hic_hdr2 buffer; 3750 3751 DEBUGFUNC("ixgbe_update_flash_X550"); 3752 3753 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; 3754 buffer.req.buf_lenh = 0; 3755 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; 3756 buffer.req.checksum = FW_DEFAULT_CHECKSUM; 3757 3758 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 3759 sizeof(buffer), 3760 IXGBE_HI_COMMAND_TIMEOUT, FALSE); 3761 3762 return status; 3763 } 3764 3765 /** 3766 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type 3767 * @hw: pointer to hardware structure 3768 * 3769 * Determines physical layer capabilities of the current configuration. 3770 **/ 3771 u64 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw) 3772 { 3773 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 3774 u16 ext_ability = 0; 3775 3776 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em"); 3777 3778 hw->phy.ops.identify(hw); 3779 3780 switch (hw->phy.type) { 3781 case ixgbe_phy_x550em_kr: 3782 if (hw->mac.type == ixgbe_mac_X550EM_a) { 3783 if (hw->phy.nw_mng_if_sel & 3784 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) { 3785 physical_layer = 3786 IXGBE_PHYSICAL_LAYER_2500BASE_KX; 3787 break; 3788 } else if (hw->device_id == 3789 IXGBE_DEV_ID_X550EM_A_KR_L) { 3790 physical_layer = 3791 IXGBE_PHYSICAL_LAYER_1000BASE_KX; 3792 break; 3793 } 3794 } 3795 /* fall through */ 3796 case ixgbe_phy_x550em_xfi: 3797 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR | 3798 IXGBE_PHYSICAL_LAYER_1000BASE_KX; 3799 break; 3800 case ixgbe_phy_x550em_kx4: 3801 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 | 3802 IXGBE_PHYSICAL_LAYER_1000BASE_KX; 3803 break; 3804 case ixgbe_phy_x550em_ext_t: 3805 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 3806 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 3807 &ext_ability); 3808 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 3809 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 3810 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 3811 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 3812 break; 3813 case ixgbe_phy_fw: 3814 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_1GB_FULL) 3815 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 3816 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_100_FULL) 3817 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 3818 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_10_FULL) 3819 physical_layer |= IXGBE_PHYSICAL_LAYER_10BASE_T; 3820 break; 3821 case ixgbe_phy_sgmii: 3822 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; 3823 break; 3824 case ixgbe_phy_ext_1g_t: 3825 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 3826 break; 3827 default: 3828 break; 3829 } 3830 3831 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) 3832 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw); 3833 3834 return physical_layer; 3835 } 3836 3837 /** 3838 * ixgbe_get_bus_info_x550em - Set PCI bus info 3839 * @hw: pointer to hardware structure 3840 * 3841 * Sets bus link width and speed to unknown because X550em is 3842 * not a PCI device. 3843 **/ 3844 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw) 3845 { 3846 3847 DEBUGFUNC("ixgbe_get_bus_info_x550em"); 3848 3849 hw->bus.width = ixgbe_bus_width_unknown; 3850 hw->bus.speed = ixgbe_bus_speed_unknown; 3851 3852 hw->mac.ops.set_lan_id(hw); 3853 3854 return IXGBE_SUCCESS; 3855 } 3856 3857 /** 3858 * ixgbe_disable_rx_x550 - Disable RX unit 3859 * 3860 * Enables the Rx DMA unit for x550 3861 **/ 3862 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) 3863 { 3864 u32 rxctrl, pfdtxgswc; 3865 s32 status; 3866 struct ixgbe_hic_disable_rxen fw_cmd; 3867 3868 DEBUGFUNC("ixgbe_disable_rx_dma_x550"); 3869 3870 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 3871 if (rxctrl & IXGBE_RXCTRL_RXEN) { 3872 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 3873 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 3874 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 3875 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 3876 hw->mac.set_lben = TRUE; 3877 } else { 3878 hw->mac.set_lben = FALSE; 3879 } 3880 3881 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD; 3882 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN; 3883 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 3884 fw_cmd.port_number = (u8)hw->bus.lan_id; 3885 3886 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 3887 sizeof(struct ixgbe_hic_disable_rxen), 3888 IXGBE_HI_COMMAND_TIMEOUT, TRUE); 3889 3890 /* If we fail - disable RX using register write */ 3891 if (status) { 3892 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 3893 if (rxctrl & IXGBE_RXCTRL_RXEN) { 3894 rxctrl &= ~IXGBE_RXCTRL_RXEN; 3895 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 3896 } 3897 } 3898 } 3899 } 3900 3901 /** 3902 * ixgbe_enter_lplu_x550em - Transition to low power states 3903 * @hw: pointer to hardware structure 3904 * 3905 * Configures Low Power Link Up on transition to low power states 3906 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the 3907 * X557 PHY immediately prior to entering LPLU. 3908 **/ 3909 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) 3910 { 3911 u16 an_10g_cntl_reg, autoneg_reg, speed; 3912 s32 status; 3913 ixgbe_link_speed lcd_speed; 3914 u32 save_autoneg; 3915 bool link_up; 3916 3917 /* SW LPLU not required on later HW revisions. */ 3918 if ((hw->mac.type == ixgbe_mac_X550EM_x) && 3919 (IXGBE_FUSES0_REV_MASK & 3920 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))) 3921 return IXGBE_SUCCESS; 3922 3923 /* If blocked by MNG FW, then don't restart AN */ 3924 if (ixgbe_check_reset_blocked(hw)) 3925 return IXGBE_SUCCESS; 3926 3927 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3928 if (status != IXGBE_SUCCESS) 3929 return status; 3930 3931 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3); 3932 3933 if (status != IXGBE_SUCCESS) 3934 return status; 3935 3936 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability 3937 * disabled, then force link down by entering low power mode. 3938 */ 3939 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) || 3940 !(hw->wol_enabled || ixgbe_mng_present(hw))) 3941 return ixgbe_set_copper_phy_power(hw, FALSE); 3942 3943 /* Determine LCD */ 3944 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed); 3945 3946 if (status != IXGBE_SUCCESS) 3947 return status; 3948 3949 /* If no valid LCD link speed, then force link down and exit. */ 3950 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN) 3951 return ixgbe_set_copper_phy_power(hw, FALSE); 3952 3953 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 3954 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3955 &speed); 3956 3957 if (status != IXGBE_SUCCESS) 3958 return status; 3959 3960 /* If no link now, speed is invalid so take link down */ 3961 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3962 if (status != IXGBE_SUCCESS) 3963 return ixgbe_set_copper_phy_power(hw, FALSE); 3964 3965 /* clear everything but the speed bits */ 3966 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK; 3967 3968 /* If current speed is already LCD, then exit. */ 3969 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) && 3970 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) || 3971 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) && 3972 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL))) 3973 return status; 3974 3975 /* Clear AN completed indication */ 3976 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM, 3977 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3978 &autoneg_reg); 3979 3980 if (status != IXGBE_SUCCESS) 3981 return status; 3982 3983 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 3984 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3985 &an_10g_cntl_reg); 3986 3987 if (status != IXGBE_SUCCESS) 3988 return status; 3989 3990 status = hw->phy.ops.read_reg(hw, 3991 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 3992 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3993 &autoneg_reg); 3994 3995 if (status != IXGBE_SUCCESS) 3996 return status; 3997 3998 save_autoneg = hw->phy.autoneg_advertised; 3999 4000 /* Setup link at least common link speed */ 4001 status = hw->mac.ops.setup_link(hw, lcd_speed, FALSE); 4002 4003 /* restore autoneg from before setting lplu speed */ 4004 hw->phy.autoneg_advertised = save_autoneg; 4005 4006 return status; 4007 } 4008 4009 /** 4010 * ixgbe_get_lcd_x550em - Determine lowest common denominator 4011 * @hw: pointer to hardware structure 4012 * @lcd_speed: pointer to lowest common link speed 4013 * 4014 * Determine lowest common link speed with link partner. 4015 **/ 4016 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed) 4017 { 4018 u16 an_lp_status; 4019 s32 status; 4020 u16 word = hw->eeprom.ctrl_word_3; 4021 4022 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN; 4023 4024 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS, 4025 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 4026 &an_lp_status); 4027 4028 if (status != IXGBE_SUCCESS) 4029 return status; 4030 4031 /* If link partner advertised 1G, return 1G */ 4032 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) { 4033 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL; 4034 return status; 4035 } 4036 4037 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */ 4038 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) || 4039 (word & NVM_INIT_CTRL_3_D10GMP_PORT0)) 4040 return status; 4041 4042 /* Link partner not capable of lower speeds, return 10G */ 4043 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL; 4044 return status; 4045 } 4046 4047 /** 4048 * ixgbe_setup_fc_X550em - Set up flow control 4049 * @hw: pointer to hardware structure 4050 * 4051 * Called at init time to set up flow control. 4052 **/ 4053 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw) 4054 { 4055 s32 ret_val = IXGBE_SUCCESS; 4056 u32 pause, asm_dir, reg_val; 4057 4058 DEBUGFUNC("ixgbe_setup_fc_X550em"); 4059 4060 /* Validate the requested mode */ 4061 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 4062 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 4063 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 4064 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4065 goto out; 4066 } 4067 4068 /* 10gig parts do not have a word in the EEPROM to determine the 4069 * default flow control setting, so we explicitly set it to full. 4070 */ 4071 if (hw->fc.requested_mode == ixgbe_fc_default) 4072 hw->fc.requested_mode = ixgbe_fc_full; 4073 4074 /* Determine PAUSE and ASM_DIR bits. */ 4075 switch (hw->fc.requested_mode) { 4076 case ixgbe_fc_none: 4077 pause = 0; 4078 asm_dir = 0; 4079 break; 4080 case ixgbe_fc_tx_pause: 4081 pause = 0; 4082 asm_dir = 1; 4083 break; 4084 case ixgbe_fc_rx_pause: 4085 /* Rx Flow control is enabled and Tx Flow control is 4086 * disabled by software override. Since there really 4087 * isn't a way to advertise that we are capable of RX 4088 * Pause ONLY, we will advertise that we support both 4089 * symmetric and asymmetric Rx PAUSE, as such we fall 4090 * through to the fc_full statement. Later, we will 4091 * disable the adapter's ability to send PAUSE frames. 4092 */ 4093 case ixgbe_fc_full: 4094 pause = 1; 4095 asm_dir = 1; 4096 break; 4097 default: 4098 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 4099 "Flow control param set incorrectly\n"); 4100 ret_val = IXGBE_ERR_CONFIG; 4101 goto out; 4102 } 4103 4104 switch (hw->device_id) { 4105 case IXGBE_DEV_ID_X550EM_X_KR: 4106 case IXGBE_DEV_ID_X550EM_A_KR: 4107 case IXGBE_DEV_ID_X550EM_A_KR_L: 4108 ret_val = hw->mac.ops.read_iosf_sb_reg(hw, 4109 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 4110 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 4111 if (ret_val != IXGBE_SUCCESS) 4112 goto out; 4113 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 4114 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 4115 if (pause) 4116 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 4117 if (asm_dir) 4118 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 4119 ret_val = hw->mac.ops.write_iosf_sb_reg(hw, 4120 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 4121 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 4122 4123 /* This device does not fully support AN. */ 4124 hw->fc.disable_fc_autoneg = TRUE; 4125 break; 4126 case IXGBE_DEV_ID_X550EM_X_XFI: 4127 hw->fc.disable_fc_autoneg = TRUE; 4128 break; 4129 default: 4130 break; 4131 } 4132 4133 out: 4134 return ret_val; 4135 } 4136 4137 /** 4138 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37 4139 * @hw: pointer to hardware structure 4140 * 4141 * Enable flow control according to IEEE clause 37. 4142 **/ 4143 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw) 4144 { 4145 u32 link_s1, lp_an_page_low, an_cntl_1; 4146 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 4147 ixgbe_link_speed speed; 4148 bool link_up; 4149 4150 /* AN should have completed when the cable was plugged in. 4151 * Look for reasons to bail out. Bail out if: 4152 * - FC autoneg is disabled, or if 4153 * - link is not up. 4154 */ 4155 if (hw->fc.disable_fc_autoneg) { 4156 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 4157 "Flow control autoneg is disabled"); 4158 goto out; 4159 } 4160 4161 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 4162 if (!link_up) { 4163 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); 4164 goto out; 4165 } 4166 4167 /* Check at auto-negotiation has completed */ 4168 status = hw->mac.ops.read_iosf_sb_reg(hw, 4169 IXGBE_KRM_LINK_S1(hw->bus.lan_id), 4170 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1); 4171 4172 if (status != IXGBE_SUCCESS || 4173 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) { 4174 DEBUGOUT("Auto-Negotiation did not complete\n"); 4175 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 4176 goto out; 4177 } 4178 4179 /* Read the 10g AN autoc and LP ability registers and resolve 4180 * local flow control settings accordingly 4181 */ 4182 status = hw->mac.ops.read_iosf_sb_reg(hw, 4183 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 4184 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1); 4185 4186 if (status != IXGBE_SUCCESS) { 4187 DEBUGOUT("Auto-Negotiation did not complete\n"); 4188 goto out; 4189 } 4190 4191 status = hw->mac.ops.read_iosf_sb_reg(hw, 4192 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id), 4193 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low); 4194 4195 if (status != IXGBE_SUCCESS) { 4196 DEBUGOUT("Auto-Negotiation did not complete\n"); 4197 goto out; 4198 } 4199 4200 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low, 4201 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE, 4202 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE, 4203 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE, 4204 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE); 4205 4206 out: 4207 if (status == IXGBE_SUCCESS) { 4208 hw->fc.fc_was_autonegged = TRUE; 4209 } else { 4210 hw->fc.fc_was_autonegged = FALSE; 4211 hw->fc.current_mode = hw->fc.requested_mode; 4212 } 4213 } 4214 4215 /** 4216 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings 4217 * @hw: pointer to hardware structure 4218 * 4219 **/ 4220 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw) 4221 { 4222 hw->fc.fc_was_autonegged = FALSE; 4223 hw->fc.current_mode = hw->fc.requested_mode; 4224 } 4225 4226 /** 4227 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37 4228 * @hw: pointer to hardware structure 4229 * 4230 * Enable flow control according to IEEE clause 37. 4231 **/ 4232 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw) 4233 { 4234 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 4235 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 4236 ixgbe_link_speed speed; 4237 bool link_up; 4238 4239 /* AN should have completed when the cable was plugged in. 4240 * Look for reasons to bail out. Bail out if: 4241 * - FC autoneg is disabled, or if 4242 * - link is not up. 4243 */ 4244 if (hw->fc.disable_fc_autoneg) { 4245 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 4246 "Flow control autoneg is disabled"); 4247 goto out; 4248 } 4249 4250 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 4251 if (!link_up) { 4252 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); 4253 goto out; 4254 } 4255 4256 /* Check if auto-negotiation has completed */ 4257 status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info); 4258 if (status != IXGBE_SUCCESS || 4259 !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) { 4260 DEBUGOUT("Auto-Negotiation did not complete\n"); 4261 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 4262 goto out; 4263 } 4264 4265 /* Negotiate the flow control */ 4266 status = ixgbe_negotiate_fc(hw, info[0], info[0], 4267 FW_PHY_ACT_GET_LINK_INFO_FC_RX, 4268 FW_PHY_ACT_GET_LINK_INFO_FC_TX, 4269 FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX, 4270 FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX); 4271 4272 out: 4273 if (status == IXGBE_SUCCESS) { 4274 hw->fc.fc_was_autonegged = TRUE; 4275 } else { 4276 hw->fc.fc_was_autonegged = FALSE; 4277 hw->fc.current_mode = hw->fc.requested_mode; 4278 } 4279 } 4280 4281 /** 4282 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control 4283 * @hw: pointer to hardware structure 4284 * 4285 * Called at init time to set up flow control. 4286 **/ 4287 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw) 4288 { 4289 s32 status = IXGBE_SUCCESS; 4290 u32 an_cntl = 0; 4291 4292 DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a"); 4293 4294 /* Validate the requested mode */ 4295 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 4296 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 4297 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 4298 return IXGBE_ERR_INVALID_LINK_SETTINGS; 4299 } 4300 4301 if (hw->fc.requested_mode == ixgbe_fc_default) 4302 hw->fc.requested_mode = ixgbe_fc_full; 4303 4304 /* Set up the 1G and 10G flow control advertisement registers so the 4305 * HW will be able to do FC autoneg once the cable is plugged in. If 4306 * we link at 10G, the 1G advertisement is harmless and vice versa. 4307 */ 4308 status = hw->mac.ops.read_iosf_sb_reg(hw, 4309 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 4310 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl); 4311 4312 if (status != IXGBE_SUCCESS) { 4313 DEBUGOUT("Auto-Negotiation did not complete\n"); 4314 return status; 4315 } 4316 4317 /* The possible values of fc.requested_mode are: 4318 * 0: Flow control is completely disabled 4319 * 1: Rx flow control is enabled (we can receive pause frames, 4320 * but not send pause frames). 4321 * 2: Tx flow control is enabled (we can send pause frames but 4322 * we do not support receiving pause frames). 4323 * 3: Both Rx and Tx flow control (symmetric) are enabled. 4324 * other: Invalid. 4325 */ 4326 switch (hw->fc.requested_mode) { 4327 case ixgbe_fc_none: 4328 /* Flow control completely disabled by software override. */ 4329 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 4330 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 4331 break; 4332 case ixgbe_fc_tx_pause: 4333 /* Tx Flow control is enabled, and Rx Flow control is 4334 * disabled by software override. 4335 */ 4336 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 4337 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 4338 break; 4339 case ixgbe_fc_rx_pause: 4340 /* Rx Flow control is enabled and Tx Flow control is 4341 * disabled by software override. Since there really 4342 * isn't a way to advertise that we are capable of RX 4343 * Pause ONLY, we will advertise that we support both 4344 * symmetric and asymmetric Rx PAUSE, as such we fall 4345 * through to the fc_full statement. Later, we will 4346 * disable the adapter's ability to send PAUSE frames. 4347 */ 4348 case ixgbe_fc_full: 4349 /* Flow control (both Rx and Tx) is enabled by SW override. */ 4350 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 4351 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 4352 break; 4353 default: 4354 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 4355 "Flow control param set incorrectly\n"); 4356 return IXGBE_ERR_CONFIG; 4357 } 4358 4359 status = hw->mac.ops.write_iosf_sb_reg(hw, 4360 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 4361 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl); 4362 4363 /* Restart auto-negotiation. */ 4364 status = ixgbe_restart_an_internal_phy_x550em(hw); 4365 4366 return status; 4367 } 4368 4369 /** 4370 * ixgbe_set_mux - Set mux for port 1 access with CS4227 4371 * @hw: pointer to hardware structure 4372 * @state: set mux if 1, clear if 0 4373 */ 4374 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state) 4375 { 4376 u32 esdp; 4377 4378 if (!hw->bus.lan_id) 4379 return; 4380 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 4381 if (state) 4382 esdp |= IXGBE_ESDP_SDP1; 4383 else 4384 esdp &= ~IXGBE_ESDP_SDP1; 4385 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4386 IXGBE_WRITE_FLUSH(hw); 4387 } 4388 4389 /** 4390 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore 4391 * @hw: pointer to hardware structure 4392 * @mask: Mask to specify which semaphore to acquire 4393 * 4394 * Acquires the SWFW semaphore and sets the I2C MUX 4395 **/ 4396 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 4397 { 4398 s32 status; 4399 4400 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em"); 4401 4402 status = ixgbe_acquire_swfw_sync_X540(hw, mask); 4403 if (status) 4404 return status; 4405 4406 if (mask & IXGBE_GSSR_I2C_MASK) 4407 ixgbe_set_mux(hw, 1); 4408 4409 return IXGBE_SUCCESS; 4410 } 4411 4412 /** 4413 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore 4414 * @hw: pointer to hardware structure 4415 * @mask: Mask to specify which semaphore to release 4416 * 4417 * Releases the SWFW semaphore and sets the I2C MUX 4418 **/ 4419 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 4420 { 4421 DEBUGFUNC("ixgbe_release_swfw_sync_X550em"); 4422 4423 if (mask & IXGBE_GSSR_I2C_MASK) 4424 ixgbe_set_mux(hw, 0); 4425 4426 ixgbe_release_swfw_sync_X540(hw, mask); 4427 } 4428 4429 /** 4430 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore 4431 * @hw: pointer to hardware structure 4432 * @mask: Mask to specify which semaphore to acquire 4433 * 4434 * Acquires the SWFW semaphore and get the shared phy token as needed 4435 */ 4436 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask) 4437 { 4438 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 4439 int retries = FW_PHY_TOKEN_RETRIES; 4440 s32 status = IXGBE_SUCCESS; 4441 4442 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a"); 4443 4444 while (--retries) { 4445 status = IXGBE_SUCCESS; 4446 if (hmask) 4447 status = ixgbe_acquire_swfw_sync_X540(hw, hmask); 4448 if (status) { 4449 DEBUGOUT1("Could not acquire SWFW semaphore, Status = %d\n", 4450 status); 4451 return status; 4452 } 4453 if (!(mask & IXGBE_GSSR_TOKEN_SM)) 4454 return IXGBE_SUCCESS; 4455 4456 status = ixgbe_get_phy_token(hw); 4457 if (status == IXGBE_ERR_TOKEN_RETRY) 4458 DEBUGOUT1("Could not acquire PHY token, Status = %d\n", 4459 status); 4460 4461 if (status == IXGBE_SUCCESS) 4462 return IXGBE_SUCCESS; 4463 4464 if (hmask) 4465 ixgbe_release_swfw_sync_X540(hw, hmask); 4466 4467 if (status != IXGBE_ERR_TOKEN_RETRY) { 4468 DEBUGOUT1("Unable to retry acquiring the PHY token, Status = %d\n", 4469 status); 4470 return status; 4471 } 4472 } 4473 4474 DEBUGOUT1("Semaphore acquisition retries failed!: PHY ID = 0x%08X\n", 4475 hw->phy.id); 4476 return status; 4477 } 4478 4479 /** 4480 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore 4481 * @hw: pointer to hardware structure 4482 * @mask: Mask to specify which semaphore to release 4483 * 4484 * Releases the SWFW semaphore and puts the shared phy token as needed 4485 */ 4486 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask) 4487 { 4488 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 4489 4490 DEBUGFUNC("ixgbe_release_swfw_sync_X550a"); 4491 4492 if (mask & IXGBE_GSSR_TOKEN_SM) 4493 ixgbe_put_phy_token(hw); 4494 4495 if (hmask) 4496 ixgbe_release_swfw_sync_X540(hw, hmask); 4497 } 4498 4499 /** 4500 * ixgbe_read_phy_reg_x550a - Reads specified PHY register 4501 * @hw: pointer to hardware structure 4502 * @reg_addr: 32 bit address of PHY register to read 4503 * @phy_data: Pointer to read data from PHY register 4504 * 4505 * Reads a value from a specified PHY register using the SWFW lock and PHY 4506 * Token. The PHY Token is needed since the MDIO is shared between to MAC 4507 * instances. 4508 **/ 4509 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 4510 u32 device_type, u16 *phy_data) 4511 { 4512 s32 status; 4513 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 4514 4515 DEBUGFUNC("ixgbe_read_phy_reg_x550a"); 4516 4517 if (hw->mac.ops.acquire_swfw_sync(hw, mask)) 4518 return IXGBE_ERR_SWFW_SYNC; 4519 4520 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 4521 4522 hw->mac.ops.release_swfw_sync(hw, mask); 4523 4524 return status; 4525 } 4526 4527 /** 4528 * ixgbe_write_phy_reg_x550a - Writes specified PHY register 4529 * @hw: pointer to hardware structure 4530 * @reg_addr: 32 bit PHY register to write 4531 * @device_type: 5 bit device type 4532 * @phy_data: Data to write to the PHY register 4533 * 4534 * Writes a value to specified PHY register using the SWFW lock and PHY Token. 4535 * The PHY Token is needed since the MDIO is shared between to MAC instances. 4536 **/ 4537 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 4538 u32 device_type, u16 phy_data) 4539 { 4540 s32 status; 4541 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 4542 4543 DEBUGFUNC("ixgbe_write_phy_reg_x550a"); 4544 4545 if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) { 4546 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, 4547 phy_data); 4548 hw->mac.ops.release_swfw_sync(hw, mask); 4549 } else { 4550 status = IXGBE_ERR_SWFW_SYNC; 4551 } 4552 4553 return status; 4554 } 4555 4556 /** 4557 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt 4558 * @hw: pointer to hardware structure 4559 * 4560 * Handle external Base T PHY interrupt. If high temperature 4561 * failure alarm then return error, else if link status change 4562 * then setup internal/external PHY link 4563 * 4564 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 4565 * failure alarm, else return PHY access status. 4566 */ 4567 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw) 4568 { 4569 bool lsc; 4570 u32 status; 4571 4572 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 4573 4574 if (status != IXGBE_SUCCESS) 4575 return status; 4576 4577 if (lsc) 4578 return ixgbe_setup_internal_phy(hw); 4579 4580 return IXGBE_SUCCESS; 4581 } 4582 4583 /** 4584 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed 4585 * @hw: pointer to hardware structure 4586 * @speed: new link speed 4587 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 4588 * 4589 * Setup internal/external PHY link speed based on link speed, then set 4590 * external PHY auto advertised link speed. 4591 * 4592 * Returns error status for any failure 4593 **/ 4594 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, 4595 ixgbe_link_speed speed, 4596 bool autoneg_wait_to_complete) 4597 { 4598 s32 status; 4599 ixgbe_link_speed force_speed; 4600 4601 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em"); 4602 4603 /* Setup internal/external PHY link speed to iXFI (10G), unless 4604 * only 1G is auto advertised then setup KX link. 4605 */ 4606 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 4607 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 4608 else 4609 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 4610 4611 /* If X552 and internal link mode is XFI, then setup XFI internal link. 4612 */ 4613 if (hw->mac.type == ixgbe_mac_X550EM_x && 4614 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 4615 status = ixgbe_setup_ixfi_x550em(hw, &force_speed); 4616 4617 if (status != IXGBE_SUCCESS) 4618 return status; 4619 } 4620 4621 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); 4622 } 4623 4624 /** 4625 * ixgbe_check_link_t_X550em - Determine link and speed status 4626 * @hw: pointer to hardware structure 4627 * @speed: pointer to link speed 4628 * @link_up: TRUE when link is up 4629 * @link_up_wait_to_complete: bool used to wait for link up or not 4630 * 4631 * Check that both the MAC and X557 external PHY have link. 4632 **/ 4633 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4634 bool *link_up, bool link_up_wait_to_complete) 4635 { 4636 u32 status; 4637 u16 i, autoneg_status = 0; 4638 4639 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 4640 return IXGBE_ERR_CONFIG; 4641 4642 status = ixgbe_check_mac_link_generic(hw, speed, link_up, 4643 link_up_wait_to_complete); 4644 4645 /* If check link fails or MAC link is not up, then return */ 4646 if (status != IXGBE_SUCCESS || !(*link_up)) 4647 return status; 4648 4649 /* MAC link is up, so check external PHY link. 4650 * X557 PHY. Link status is latching low, and can only be used to detect 4651 * link drop, and not the current status of the link without performing 4652 * back-to-back reads. 4653 */ 4654 for (i = 0; i < 2; i++) { 4655 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 4656 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 4657 &autoneg_status); 4658 4659 if (status != IXGBE_SUCCESS) 4660 return status; 4661 } 4662 4663 /* If external PHY link is not up, then indicate link not up */ 4664 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) 4665 *link_up = FALSE; 4666 4667 return IXGBE_SUCCESS; 4668 } 4669 4670 /** 4671 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI 4672 * @hw: pointer to hardware structure 4673 **/ 4674 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw) 4675 { 4676 s32 status; 4677 4678 status = ixgbe_reset_phy_generic(hw); 4679 4680 if (status != IXGBE_SUCCESS) 4681 return status; 4682 4683 /* Configure Link Status Alarm and Temperature Threshold interrupts */ 4684 return ixgbe_enable_lasi_ext_t_x550em(hw); 4685 } 4686 4687 /** 4688 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs. 4689 * @hw: pointer to hardware structure 4690 * @led_idx: led number to turn on 4691 **/ 4692 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx) 4693 { 4694 u16 phy_data; 4695 4696 DEBUGFUNC("ixgbe_led_on_t_X550em"); 4697 4698 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 4699 return IXGBE_ERR_PARAM; 4700 4701 /* To turn on the LED, set mode to ON. */ 4702 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 4703 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data); 4704 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK; 4705 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 4706 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data); 4707 4708 /* Some designs have the LEDs wired to the MAC */ 4709 return ixgbe_led_on_generic(hw, led_idx); 4710 } 4711 4712 /** 4713 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs. 4714 * @hw: pointer to hardware structure 4715 * @led_idx: led number to turn off 4716 **/ 4717 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx) 4718 { 4719 u16 phy_data; 4720 4721 DEBUGFUNC("ixgbe_led_off_t_X550em"); 4722 4723 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 4724 return IXGBE_ERR_PARAM; 4725 4726 /* To turn on the LED, set mode to ON. */ 4727 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 4728 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data); 4729 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK; 4730 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 4731 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data); 4732 4733 /* Some designs have the LEDs wired to the MAC */ 4734 return ixgbe_led_off_generic(hw, led_idx); 4735 } 4736 4737 /** 4738 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware 4739 * @hw: pointer to the HW structure 4740 * @maj: driver version major number 4741 * @min: driver version minor number 4742 * @build: driver version build number 4743 * @sub: driver version sub build number 4744 * @len: length of driver_ver string 4745 * @driver_ver: driver string 4746 * 4747 * Sends driver version number to firmware through the manageability 4748 * block. On success return IXGBE_SUCCESS 4749 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 4750 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4751 **/ 4752 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min, 4753 u8 build, u8 sub, u16 len, const char *driver_ver) 4754 { 4755 struct ixgbe_hic_drv_info2 fw_cmd; 4756 s32 ret_val = IXGBE_SUCCESS; 4757 int i; 4758 4759 DEBUGFUNC("ixgbe_set_fw_drv_ver_x550"); 4760 4761 if ((len == 0) || (driver_ver == NULL) || 4762 (len > sizeof(fw_cmd.driver_string))) 4763 return IXGBE_ERR_INVALID_ARGUMENT; 4764 4765 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 4766 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len; 4767 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 4768 fw_cmd.port_num = (u8)hw->bus.func; 4769 fw_cmd.ver_maj = maj; 4770 fw_cmd.ver_min = min; 4771 fw_cmd.ver_build = build; 4772 fw_cmd.ver_sub = sub; 4773 fw_cmd.hdr.checksum = 0; 4774 memcpy(fw_cmd.driver_string, driver_ver, len); 4775 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 4776 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 4777 4778 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 4779 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 4780 sizeof(fw_cmd), 4781 IXGBE_HI_COMMAND_TIMEOUT, 4782 TRUE); 4783 if (ret_val != IXGBE_SUCCESS) 4784 continue; 4785 4786 if (fw_cmd.hdr.cmd_or_resp.ret_status == 4787 FW_CEM_RESP_STATUS_SUCCESS) 4788 ret_val = IXGBE_SUCCESS; 4789 else 4790 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4791 4792 break; 4793 } 4794 4795 return ret_val; 4796 } 4797
Indexes created Tue Sep 30 11:09:46 GMT 2025