ixgbe_x550.c revision 1.11
1 /****************************************************************************** 2 3 Copyright (c) 2001-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x550.c 320688 2017-07-05 17:27:03Z erj $*/ 34 35 #include "ixgbe_x550.h" 36 #include "ixgbe_x540.h" 37 #include "ixgbe_type.h" 38 #include "ixgbe_api.h" 39 #include "ixgbe_common.h" 40 #include "ixgbe_phy.h" 41 #include <dev/mii/mii.h> 42 43 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed); 44 static s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, 45 ixgbe_link_speed speed, 46 bool autoneg_wait_to_complete); 47 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask); 48 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask); 49 static s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw); 50 51 /** 52 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type 53 * @hw: pointer to hardware structure 54 * 55 * Initialize the function pointers and assign the MAC type for X550. 56 * Does not touch the hardware. 57 **/ 58 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw) 59 { 60 struct ixgbe_mac_info *mac = &hw->mac; 61 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 62 s32 ret_val; 63 64 DEBUGFUNC("ixgbe_init_ops_X550"); 65 66 ret_val = ixgbe_init_ops_X540(hw); 67 mac->ops.dmac_config = ixgbe_dmac_config_X550; 68 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550; 69 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550; 70 mac->ops.setup_eee = NULL; 71 mac->ops.set_source_address_pruning = 72 ixgbe_set_source_address_pruning_X550; 73 mac->ops.set_ethertype_anti_spoofing = 74 ixgbe_set_ethertype_anti_spoofing_X550; 75 76 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; 77 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550; 78 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550; 79 eeprom->ops.read = ixgbe_read_ee_hostif_X550; 80 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550; 81 eeprom->ops.write = ixgbe_write_ee_hostif_X550; 82 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550; 83 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550; 84 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550; 85 86 mac->ops.disable_mdd = ixgbe_disable_mdd_X550; 87 mac->ops.enable_mdd = ixgbe_enable_mdd_X550; 88 mac->ops.mdd_event = ixgbe_mdd_event_X550; 89 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550; 90 mac->ops.disable_rx = ixgbe_disable_rx_x550; 91 /* Manageability interface */ 92 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550; 93 switch (hw->device_id) { 94 case IXGBE_DEV_ID_X550EM_X_1G_T: 95 hw->mac.ops.led_on = NULL; 96 hw->mac.ops.led_off = NULL; 97 break; 98 case IXGBE_DEV_ID_X550EM_X_10G_T: 99 case IXGBE_DEV_ID_X550EM_A_10G_T: 100 hw->mac.ops.led_on = ixgbe_led_on_t_X550em; 101 hw->mac.ops.led_off = ixgbe_led_off_t_X550em; 102 break; 103 default: 104 break; 105 } 106 return ret_val; 107 } 108 109 /** 110 * ixgbe_read_cs4227 - Read CS4227 register 111 * @hw: pointer to hardware structure 112 * @reg: register number to write 113 * @value: pointer to receive value read 114 * 115 * Returns status code 116 **/ 117 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value) 118 { 119 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value); 120 } 121 122 /** 123 * ixgbe_write_cs4227 - Write CS4227 register 124 * @hw: pointer to hardware structure 125 * @reg: register number to write 126 * @value: value to write to register 127 * 128 * Returns status code 129 **/ 130 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) 131 { 132 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value); 133 } 134 135 /** 136 * ixgbe_read_pe - Read register from port expander 137 * @hw: pointer to hardware structure 138 * @reg: register number to read 139 * @value: pointer to receive read value 140 * 141 * Returns status code 142 **/ 143 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) 144 { 145 s32 status; 146 147 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value); 148 if (status != IXGBE_SUCCESS) 149 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 150 "port expander access failed with %d\n", status); 151 return status; 152 } 153 154 /** 155 * ixgbe_write_pe - Write register to port expander 156 * @hw: pointer to hardware structure 157 * @reg: register number to write 158 * @value: value to write 159 * 160 * Returns status code 161 **/ 162 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value) 163 { 164 s32 status; 165 166 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value); 167 if (status != IXGBE_SUCCESS) 168 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 169 "port expander access failed with %d\n", status); 170 return status; 171 } 172 173 /** 174 * ixgbe_reset_cs4227 - Reset CS4227 using port expander 175 * @hw: pointer to hardware structure 176 * 177 * This function assumes that the caller has acquired the proper semaphore. 178 * Returns error code 179 **/ 180 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw) 181 { 182 s32 status; 183 u32 retry; 184 u16 value; 185 u8 reg; 186 187 /* Trigger hard reset. */ 188 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 189 if (status != IXGBE_SUCCESS) 190 return status; 191 reg |= IXGBE_PE_BIT1; 192 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 193 if (status != IXGBE_SUCCESS) 194 return status; 195 196 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®); 197 if (status != IXGBE_SUCCESS) 198 return status; 199 reg &= ~IXGBE_PE_BIT1; 200 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg); 201 if (status != IXGBE_SUCCESS) 202 return status; 203 204 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 205 if (status != IXGBE_SUCCESS) 206 return status; 207 reg &= ~IXGBE_PE_BIT1; 208 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 209 if (status != IXGBE_SUCCESS) 210 return status; 211 212 usec_delay(IXGBE_CS4227_RESET_HOLD); 213 214 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 215 if (status != IXGBE_SUCCESS) 216 return status; 217 reg |= IXGBE_PE_BIT1; 218 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 219 if (status != IXGBE_SUCCESS) 220 return status; 221 222 /* Wait for the reset to complete. */ 223 msec_delay(IXGBE_CS4227_RESET_DELAY); 224 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 225 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS, 226 &value); 227 if (status == IXGBE_SUCCESS && 228 value == IXGBE_CS4227_EEPROM_LOAD_OK) 229 break; 230 msec_delay(IXGBE_CS4227_CHECK_DELAY); 231 } 232 if (retry == IXGBE_CS4227_RETRIES) { 233 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 234 "CS4227 reset did not complete."); 235 return IXGBE_ERR_PHY; 236 } 237 238 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value); 239 if (status != IXGBE_SUCCESS || 240 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) { 241 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 242 "CS4227 EEPROM did not load successfully."); 243 return IXGBE_ERR_PHY; 244 } 245 246 return IXGBE_SUCCESS; 247 } 248 249 /** 250 * ixgbe_check_cs4227 - Check CS4227 and reset as needed 251 * @hw: pointer to hardware structure 252 **/ 253 static void ixgbe_check_cs4227(struct ixgbe_hw *hw) 254 { 255 s32 status = IXGBE_SUCCESS; 256 u32 swfw_mask = hw->phy.phy_semaphore_mask; 257 u16 value = 0; 258 u8 retry; 259 260 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 261 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 262 if (status != IXGBE_SUCCESS) { 263 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 264 "semaphore failed with %d", status); 265 msec_delay(IXGBE_CS4227_CHECK_DELAY); 266 continue; 267 } 268 269 /* Get status of reset flow. */ 270 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); 271 272 if (status == IXGBE_SUCCESS && 273 value == IXGBE_CS4227_RESET_COMPLETE) 274 goto out; 275 276 if (status != IXGBE_SUCCESS || 277 value != IXGBE_CS4227_RESET_PENDING) 278 break; 279 280 /* Reset is pending. Wait and check again. */ 281 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 282 msec_delay(IXGBE_CS4227_CHECK_DELAY); 283 } 284 285 /* If still pending, assume other instance failed. */ 286 if (retry == IXGBE_CS4227_RETRIES) { 287 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 288 if (status != IXGBE_SUCCESS) { 289 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 290 "semaphore failed with %d", status); 291 return; 292 } 293 } 294 295 /* Reset the CS4227. */ 296 status = ixgbe_reset_cs4227(hw); 297 if (status != IXGBE_SUCCESS) { 298 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 299 "CS4227 reset failed: %d", status); 300 goto out; 301 } 302 303 /* Reset takes so long, temporarily release semaphore in case the 304 * other driver instance is waiting for the reset indication. 305 */ 306 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 307 IXGBE_CS4227_RESET_PENDING); 308 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 309 msec_delay(10); 310 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 311 if (status != IXGBE_SUCCESS) { 312 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 313 "semaphore failed with %d", status); 314 return; 315 } 316 317 /* Record completion for next time. */ 318 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 319 IXGBE_CS4227_RESET_COMPLETE); 320 321 out: 322 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 323 msec_delay(hw->eeprom.semaphore_delay); 324 } 325 326 /** 327 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control 328 * @hw: pointer to hardware structure 329 **/ 330 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) 331 { 332 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 333 334 if (hw->bus.lan_id) { 335 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); 336 esdp |= IXGBE_ESDP_SDP1_DIR; 337 } 338 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); 339 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 340 IXGBE_WRITE_FLUSH(hw); 341 } 342 343 /** 344 * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock 345 * @hw: pointer to hardware structure 346 * @reg_addr: 32 bit address of PHY register to read 347 * @dev_type: always unused 348 * @phy_data: Pointer to read data from PHY register 349 */ 350 static s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr, 351 u32 dev_type, u16 *phy_data) 352 { 353 u32 i, data, command; 354 UNREFERENCED_1PARAMETER(dev_type); 355 356 /* Setup and write the read command */ 357 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) | 358 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 359 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC | 360 IXGBE_MSCA_MDI_COMMAND; 361 362 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 363 364 /* Check every 10 usec to see if the access completed. 365 * The MDI Command bit will clear when the operation is 366 * complete 367 */ 368 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 369 usec_delay(10); 370 371 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 372 if (!(command & IXGBE_MSCA_MDI_COMMAND)) 373 break; 374 } 375 376 if (command & IXGBE_MSCA_MDI_COMMAND) { 377 ERROR_REPORT1(IXGBE_ERROR_POLLING, 378 "PHY read command did not complete.\n"); 379 return IXGBE_ERR_PHY; 380 } 381 382 /* Read operation is complete. Get the data from MSRWD */ 383 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 384 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 385 *phy_data = (u16)data; 386 387 return IXGBE_SUCCESS; 388 } 389 390 /** 391 * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock 392 * @hw: pointer to hardware structure 393 * @reg_addr: 32 bit PHY register to write 394 * @dev_type: always unused 395 * @phy_data: Data to write to the PHY register 396 */ 397 static s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr, 398 u32 dev_type, u16 phy_data) 399 { 400 u32 i, command; 401 UNREFERENCED_1PARAMETER(dev_type); 402 403 /* Put the data in the MDI single read and write data register*/ 404 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 405 406 /* Setup and write the write command */ 407 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) | 408 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 409 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE | 410 IXGBE_MSCA_MDI_COMMAND; 411 412 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 413 414 /* Check every 10 usec to see if the access completed. 415 * The MDI Command bit will clear when the operation is 416 * complete 417 */ 418 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 419 usec_delay(10); 420 421 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 422 if (!(command & IXGBE_MSCA_MDI_COMMAND)) 423 break; 424 } 425 426 if (command & IXGBE_MSCA_MDI_COMMAND) { 427 ERROR_REPORT1(IXGBE_ERROR_POLLING, 428 "PHY write cmd didn't complete\n"); 429 return IXGBE_ERR_PHY; 430 } 431 432 return IXGBE_SUCCESS; 433 } 434 435 /** 436 * ixgbe_identify_phy_x550em - Get PHY type based on device id 437 * @hw: pointer to hardware structure 438 * 439 * Returns error code 440 */ 441 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) 442 { 443 hw->mac.ops.set_lan_id(hw); 444 445 ixgbe_read_mng_if_sel_x550em(hw); 446 447 switch (hw->device_id) { 448 case IXGBE_DEV_ID_X550EM_A_SFP: 449 return ixgbe_identify_module_generic(hw); 450 case IXGBE_DEV_ID_X550EM_X_SFP: 451 /* set up for CS4227 usage */ 452 ixgbe_setup_mux_ctl(hw); 453 ixgbe_check_cs4227(hw); 454 /* Fallthrough */ 455 456 case IXGBE_DEV_ID_X550EM_A_SFP_N: 457 return ixgbe_identify_module_generic(hw); 458 break; 459 case IXGBE_DEV_ID_X550EM_X_KX4: 460 hw->phy.type = ixgbe_phy_x550em_kx4; 461 break; 462 case IXGBE_DEV_ID_X550EM_X_XFI: 463 hw->phy.type = ixgbe_phy_x550em_xfi; 464 break; 465 case IXGBE_DEV_ID_X550EM_X_KR: 466 case IXGBE_DEV_ID_X550EM_A_KR: 467 case IXGBE_DEV_ID_X550EM_A_KR_L: 468 hw->phy.type = ixgbe_phy_x550em_kr; 469 break; 470 case IXGBE_DEV_ID_X550EM_A_10G_T: 471 case IXGBE_DEV_ID_X550EM_X_10G_T: 472 return ixgbe_identify_phy_generic(hw); 473 case IXGBE_DEV_ID_X550EM_X_1G_T: 474 hw->phy.type = ixgbe_phy_ext_1g_t; 475 break; 476 case IXGBE_DEV_ID_X550EM_A_1G_T: 477 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 478 hw->phy.type = ixgbe_phy_fw; 479 if (hw->bus.lan_id) 480 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; 481 else 482 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; 483 break; 484 default: 485 break; 486 } 487 return IXGBE_SUCCESS; 488 } 489 490 /** 491 * ixgbe_fw_phy_activity - Perform an activity on a PHY 492 * @hw: pointer to hardware structure 493 * @activity: activity to perform 494 * @data: Pointer to 4 32-bit words of data 495 */ 496 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity, 497 u32 (*data)[FW_PHY_ACT_DATA_COUNT]) 498 { 499 union { 500 struct ixgbe_hic_phy_activity_req cmd; 501 struct ixgbe_hic_phy_activity_resp rsp; 502 } hic; 503 u16 retries = FW_PHY_ACT_RETRIES; 504 s32 rc; 505 u16 i; 506 507 do { 508 memset(&hic, 0, sizeof(hic)); 509 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD; 510 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN; 511 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 512 hic.cmd.port_number = hw->bus.lan_id; 513 hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity); 514 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i) 515 hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]); 516 517 rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd, 518 sizeof(hic.cmd), 519 IXGBE_HI_COMMAND_TIMEOUT, 520 TRUE); 521 if (rc != IXGBE_SUCCESS) 522 return rc; 523 if (hic.rsp.hdr.cmd_or_resp.ret_status == 524 FW_CEM_RESP_STATUS_SUCCESS) { 525 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i) 526 (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]); 527 return IXGBE_SUCCESS; 528 } 529 usec_delay(20); 530 --retries; 531 } while (retries > 0); 532 533 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 534 } 535 536 static const struct { 537 u16 fw_speed; 538 ixgbe_link_speed phy_speed; 539 } ixgbe_fw_map[] = { 540 { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL }, 541 { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL }, 542 { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL }, 543 { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL }, 544 { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL }, 545 { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL }, 546 }; 547 548 /** 549 * ixgbe_get_phy_id_fw - Get the phy ID via firmware command 550 * @hw: pointer to hardware structure 551 * 552 * Returns error code 553 */ 554 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw) 555 { 556 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 557 u16 phy_speeds; 558 u16 phy_id_lo; 559 s32 rc; 560 u16 i; 561 562 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info); 563 if (rc) 564 return rc; 565 566 hw->phy.speeds_supported = 0; 567 phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK; 568 for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) { 569 if (phy_speeds & ixgbe_fw_map[i].fw_speed) 570 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed; 571 } 572 573 #if 0 574 /* 575 * Don't set autoneg_advertised here to not to be inconsistent with 576 * if_media value. 577 */ 578 if (!hw->phy.autoneg_advertised) 579 hw->phy.autoneg_advertised = hw->phy.speeds_supported; 580 #endif 581 582 hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK; 583 phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK; 584 hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK; 585 hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK; 586 if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK) 587 return IXGBE_ERR_PHY_ADDR_INVALID; 588 return IXGBE_SUCCESS; 589 } 590 591 /** 592 * ixgbe_identify_phy_fw - Get PHY type based on firmware command 593 * @hw: pointer to hardware structure 594 * 595 * Returns error code 596 */ 597 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw) 598 { 599 if (hw->bus.lan_id) 600 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 601 else 602 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 603 604 hw->phy.type = ixgbe_phy_fw; 605 hw->phy.ops.read_reg = NULL; 606 hw->phy.ops.write_reg = NULL; 607 return ixgbe_get_phy_id_fw(hw); 608 } 609 610 /** 611 * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY 612 * @hw: pointer to hardware structure 613 * 614 * Returns error code 615 */ 616 s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw) 617 { 618 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 619 620 setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF; 621 return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup); 622 } 623 624 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 625 u32 device_type, u16 *phy_data) 626 { 627 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data); 628 return IXGBE_NOT_IMPLEMENTED; 629 } 630 631 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 632 u32 device_type, u16 phy_data) 633 { 634 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data); 635 return IXGBE_NOT_IMPLEMENTED; 636 } 637 638 /** 639 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 640 * @hw: pointer to the hardware structure 641 * @addr: I2C bus address to read from 642 * @reg: I2C device register to read from 643 * @val: pointer to location to receive read value 644 * 645 * Returns an error code on error. 646 **/ 647 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 648 u16 reg, u16 *val) 649 { 650 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, TRUE); 651 } 652 653 /** 654 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation 655 * @hw: pointer to the hardware structure 656 * @addr: I2C bus address to read from 657 * @reg: I2C device register to read from 658 * @val: pointer to location to receive read value 659 * 660 * Returns an error code on error. 661 **/ 662 static s32 663 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, 664 u16 reg, u16 *val) 665 { 666 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, FALSE); 667 } 668 669 /** 670 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 671 * @hw: pointer to the hardware structure 672 * @addr: I2C bus address to write to 673 * @reg: I2C device register to write to 674 * @val: value to write 675 * 676 * Returns an error code on error. 677 **/ 678 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 679 u8 addr, u16 reg, u16 val) 680 { 681 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, TRUE); 682 } 683 684 /** 685 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation 686 * @hw: pointer to the hardware structure 687 * @addr: I2C bus address to write to 688 * @reg: I2C device register to write to 689 * @val: value to write 690 * 691 * Returns an error code on error. 692 **/ 693 static s32 694 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, 695 u8 addr, u16 reg, u16 val) 696 { 697 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, FALSE); 698 } 699 700 /** 701 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type 702 * @hw: pointer to hardware structure 703 * 704 * Initialize the function pointers and for MAC type X550EM. 705 * Does not touch the hardware. 706 **/ 707 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw) 708 { 709 struct ixgbe_mac_info *mac = &hw->mac; 710 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 711 struct ixgbe_phy_info *phy = &hw->phy; 712 s32 ret_val; 713 714 DEBUGFUNC("ixgbe_init_ops_X550EM"); 715 716 /* Similar to X550 so start there. */ 717 ret_val = ixgbe_init_ops_X550(hw); 718 719 /* Since this function eventually calls 720 * ixgbe_init_ops_540 by design, we are setting 721 * the pointers to NULL explicitly here to overwrite 722 * the values being set in the x540 function. 723 */ 724 725 /* Bypass not supported in x550EM */ 726 mac->ops.bypass_rw = NULL; 727 mac->ops.bypass_valid_rd = NULL; 728 mac->ops.bypass_set = NULL; 729 mac->ops.bypass_rd_eep = NULL; 730 731 /* FCOE not supported in x550EM */ 732 mac->ops.get_san_mac_addr = NULL; 733 mac->ops.set_san_mac_addr = NULL; 734 mac->ops.get_wwn_prefix = NULL; 735 mac->ops.get_fcoe_boot_status = NULL; 736 737 /* IPsec not supported in x550EM */ 738 mac->ops.disable_sec_rx_path = NULL; 739 mac->ops.enable_sec_rx_path = NULL; 740 741 /* AUTOC register is not present in x550EM. */ 742 mac->ops.prot_autoc_read = NULL; 743 mac->ops.prot_autoc_write = NULL; 744 745 /* X550EM bus type is internal*/ 746 hw->bus.type = ixgbe_bus_type_internal; 747 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em; 748 749 750 mac->ops.get_media_type = ixgbe_get_media_type_X550em; 751 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em; 752 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em; 753 mac->ops.reset_hw = ixgbe_reset_hw_X550em; 754 mac->ops.get_supported_physical_layer = 755 ixgbe_get_supported_physical_layer_X550em; 756 757 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) 758 mac->ops.setup_fc = ixgbe_setup_fc_generic; 759 else 760 mac->ops.setup_fc = ixgbe_setup_fc_X550em; 761 762 /* PHY */ 763 phy->ops.init = ixgbe_init_phy_ops_X550em; 764 switch (hw->device_id) { 765 case IXGBE_DEV_ID_X550EM_A_1G_T: 766 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 767 mac->ops.setup_fc = NULL; 768 phy->ops.identify = ixgbe_identify_phy_fw; 769 phy->ops.set_phy_power = NULL; 770 phy->ops.get_firmware_version = NULL; 771 break; 772 case IXGBE_DEV_ID_X550EM_X_1G_T: 773 mac->ops.setup_fc = NULL; 774 phy->ops.identify = ixgbe_identify_phy_x550em; 775 phy->ops.set_phy_power = NULL; 776 break; 777 default: 778 phy->ops.identify = ixgbe_identify_phy_x550em; 779 } 780 781 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 782 phy->ops.set_phy_power = NULL; 783 784 785 /* EEPROM */ 786 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540; 787 eeprom->ops.read = ixgbe_read_ee_hostif_X550; 788 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550; 789 eeprom->ops.write = ixgbe_write_ee_hostif_X550; 790 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550; 791 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550; 792 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550; 793 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550; 794 795 return ret_val; 796 } 797 798 #define IXGBE_DENVERTON_WA 1 799 800 /** 801 * ixgbe_setup_fw_link - Setup firmware-controlled PHYs 802 * @hw: pointer to hardware structure 803 */ 804 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw) 805 { 806 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 807 s32 rc; 808 #ifdef IXGBE_DENVERTON_WA 809 s32 ret_val; 810 u16 phydata; 811 #endif 812 u16 i; 813 814 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 815 return 0; 816 817 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 818 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 819 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 820 return IXGBE_ERR_INVALID_LINK_SETTINGS; 821 } 822 823 switch (hw->fc.requested_mode) { 824 case ixgbe_fc_full: 825 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX << 826 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 827 break; 828 case ixgbe_fc_rx_pause: 829 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX << 830 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 831 break; 832 case ixgbe_fc_tx_pause: 833 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX << 834 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 835 break; 836 default: 837 break; 838 } 839 840 for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) { 841 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed) 842 setup[0] |= ixgbe_fw_map[i].fw_speed; 843 } 844 setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN; 845 846 if (hw->phy.eee_speeds_advertised) 847 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE; 848 849 #ifdef IXGBE_DENVERTON_WA 850 /* Don't use auto-nego for 10/100Mbps */ 851 if ((hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_100_FULL) 852 || (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_10_FULL)) { 853 setup[0] &= ~FW_PHY_ACT_SETUP_LINK_AN; 854 setup[0] &= ~FW_PHY_ACT_SETUP_LINK_EEE; 855 setup[0] &= ~(FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX 856 << FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT); 857 } 858 #endif 859 860 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup); 861 if (rc) 862 return rc; 863 864 #ifdef IXGBE_DENVERTON_WA 865 ret_val = ixgbe_read_phy_reg_x550a(hw, MII_BMCR, 0, &phydata); 866 if (ret_val != 0) 867 goto out; 868 869 /* 870 * Broken firmware sets BMCR register incorrectly if 871 * FW_PHY_ACT_SETUP_LINK_AN isn't set. 872 * a) FDX may not be set. 873 * b) BMCR_SPEED1 (bit 6) is always cleard. 874 * + -------+------+-----------+-----+--------------------------+ 875 * |request | BMCR | BMCR spd | BMCR | | 876 * | | (HEX)| (in bits)| FDX | | 877 * +--------+------+----------+------+--------------------------+ 878 * | 10M | 0000 | 10M(00) | 0 | | 879 * | 10M | 2000 | 100M(01) | 0 |(I've never observed this)| 880 * | 10M | 2100 | 100M(01) | 1 | | 881 * | 100M | 0000 | 10M(00) | 0 | | 882 * | 100M | 0100 | 10M(00) | 1 | | 883 * +--------------------------+------+--------------------------+ 884 */ 885 if (((hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_100_FULL) 886 && (((phydata & BMCR_FDX) == 0) || (BMCR_SPEED(phydata) == 0))) 887 || ((hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_10_FULL) 888 && (((phydata & BMCR_FDX) == 0) 889 || (BMCR_SPEED(phydata) != BMCR_S10)))) { 890 phydata = BMCR_FDX; 891 switch (hw->phy.autoneg_advertised) { 892 case IXGBE_LINK_SPEED_10_FULL: 893 phydata |= BMCR_S10; 894 break; 895 case IXGBE_LINK_SPEED_100_FULL: 896 phydata |= BMCR_S100; 897 break; 898 case IXGBE_LINK_SPEED_1GB_FULL: 899 panic("%s: 1GB_FULL is set", __func__); 900 break; 901 default: 902 break; 903 } 904 ret_val = ixgbe_write_phy_reg_x550a(hw, MII_BMCR, 0, phydata); 905 if (ret_val != 0) 906 return ret_val; 907 } 908 out: 909 #endif 910 if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN) 911 return IXGBE_ERR_OVERTEMP; 912 return IXGBE_SUCCESS; 913 } 914 915 /** 916 * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs 917 * @hw: pointer to hardware structure 918 * 919 * Called at init time to set up flow control. 920 */ 921 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw) 922 { 923 if (hw->fc.requested_mode == ixgbe_fc_default) 924 hw->fc.requested_mode = ixgbe_fc_full; 925 926 return ixgbe_setup_fw_link(hw); 927 } 928 929 /** 930 * ixgbe_setup_eee_fw - Enable/disable EEE support 931 * @hw: pointer to the HW structure 932 * @enable_eee: boolean flag to enable EEE 933 * 934 * Enable/disable EEE based on enable_eee flag. 935 * This function controls EEE for firmware-based PHY implementations. 936 */ 937 static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee) 938 { 939 if (!!hw->phy.eee_speeds_advertised == enable_eee) 940 return IXGBE_SUCCESS; 941 if (enable_eee) 942 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported; 943 else 944 hw->phy.eee_speeds_advertised = 0; 945 return hw->phy.ops.setup_link(hw); 946 } 947 948 /** 949 * ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type 950 * @hw: pointer to hardware structure 951 * 952 * Initialize the function pointers and for MAC type X550EM_a. 953 * Does not touch the hardware. 954 **/ 955 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw) 956 { 957 struct ixgbe_mac_info *mac = &hw->mac; 958 s32 ret_val; 959 960 DEBUGFUNC("ixgbe_init_ops_X550EM_a"); 961 962 /* Start with generic X550EM init */ 963 ret_val = ixgbe_init_ops_X550EM(hw); 964 965 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII || 966 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) { 967 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550; 968 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550; 969 } else { 970 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a; 971 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a; 972 } 973 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a; 974 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a; 975 976 switch (mac->ops.get_media_type(hw)) { 977 case ixgbe_media_type_fiber: 978 mac->ops.setup_fc = NULL; 979 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a; 980 break; 981 case ixgbe_media_type_backplane: 982 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a; 983 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a; 984 break; 985 default: 986 break; 987 } 988 989 switch (hw->device_id) { 990 case IXGBE_DEV_ID_X550EM_A_1G_T: 991 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 992 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a; 993 mac->ops.setup_fc = ixgbe_fc_autoneg_fw; 994 mac->ops.setup_eee = ixgbe_setup_eee_fw; 995 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL | 996 IXGBE_LINK_SPEED_1GB_FULL; 997 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported; 998 break; 999 default: 1000 break; 1001 } 1002 1003 return ret_val; 1004 } 1005 1006 /** 1007 * ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type 1008 * @hw: pointer to hardware structure 1009 * 1010 * Initialize the function pointers and for MAC type X550EM_x. 1011 * Does not touch the hardware. 1012 **/ 1013 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw) 1014 { 1015 struct ixgbe_mac_info *mac = &hw->mac; 1016 struct ixgbe_link_info *link = &hw->link; 1017 s32 ret_val; 1018 1019 DEBUGFUNC("ixgbe_init_ops_X550EM_x"); 1020 1021 /* Start with generic X550EM init */ 1022 ret_val = ixgbe_init_ops_X550EM(hw); 1023 1024 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550; 1025 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550; 1026 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em; 1027 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em; 1028 link->ops.read_link = ixgbe_read_i2c_combined_generic; 1029 link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked; 1030 link->ops.write_link = ixgbe_write_i2c_combined_generic; 1031 link->ops.write_link_unlocked = 1032 ixgbe_write_i2c_combined_generic_unlocked; 1033 link->addr = IXGBE_CS4227; 1034 1035 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) { 1036 mac->ops.setup_fc = NULL; 1037 mac->ops.setup_eee = NULL; 1038 mac->ops.init_led_link_act = NULL; 1039 } 1040 1041 return ret_val; 1042 } 1043 1044 /** 1045 * ixgbe_dmac_config_X550 1046 * @hw: pointer to hardware structure 1047 * 1048 * Configure DMA coalescing. If enabling dmac, dmac is activated. 1049 * When disabling dmac, dmac enable dmac bit is cleared. 1050 **/ 1051 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw) 1052 { 1053 u32 reg, high_pri_tc; 1054 1055 DEBUGFUNC("ixgbe_dmac_config_X550"); 1056 1057 /* Disable DMA coalescing before configuring */ 1058 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 1059 reg &= ~IXGBE_DMACR_DMAC_EN; 1060 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 1061 1062 /* Disable DMA Coalescing if the watchdog timer is 0 */ 1063 if (!hw->mac.dmac_config.watchdog_timer) 1064 goto out; 1065 1066 ixgbe_dmac_config_tcs_X550(hw); 1067 1068 /* Configure DMA Coalescing Control Register */ 1069 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 1070 1071 /* Set the watchdog timer in units of 40.96 usec */ 1072 reg &= ~IXGBE_DMACR_DMACWT_MASK; 1073 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096; 1074 1075 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK; 1076 /* If fcoe is enabled, set high priority traffic class */ 1077 if (hw->mac.dmac_config.fcoe_en) { 1078 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc; 1079 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) & 1080 IXGBE_DMACR_HIGH_PRI_TC_MASK); 1081 } 1082 reg |= IXGBE_DMACR_EN_MNG_IND; 1083 1084 /* Enable DMA coalescing after configuration */ 1085 reg |= IXGBE_DMACR_DMAC_EN; 1086 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 1087 1088 out: 1089 return IXGBE_SUCCESS; 1090 } 1091 1092 /** 1093 * ixgbe_dmac_config_tcs_X550 1094 * @hw: pointer to hardware structure 1095 * 1096 * Configure DMA coalescing threshold per TC. The dmac enable bit must 1097 * be cleared before configuring. 1098 **/ 1099 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw) 1100 { 1101 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb; 1102 1103 DEBUGFUNC("ixgbe_dmac_config_tcs_X550"); 1104 1105 /* Configure DMA coalescing enabled */ 1106 switch (hw->mac.dmac_config.link_speed) { 1107 case IXGBE_LINK_SPEED_10_FULL: 1108 case IXGBE_LINK_SPEED_100_FULL: 1109 pb_headroom = IXGBE_DMACRXT_100M; 1110 break; 1111 case IXGBE_LINK_SPEED_1GB_FULL: 1112 pb_headroom = IXGBE_DMACRXT_1G; 1113 break; 1114 default: 1115 pb_headroom = IXGBE_DMACRXT_10G; 1116 break; 1117 } 1118 1119 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >> 1120 IXGBE_MHADD_MFS_SHIFT) / 1024); 1121 1122 /* Set the per Rx packet buffer receive threshold */ 1123 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) { 1124 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc)); 1125 reg &= ~IXGBE_DMCTH_DMACRXT_MASK; 1126 1127 if (tc < hw->mac.dmac_config.num_tcs) { 1128 /* Get Rx PB size */ 1129 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc)); 1130 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >> 1131 IXGBE_RXPBSIZE_SHIFT; 1132 1133 /* Calculate receive buffer threshold in kilobytes */ 1134 if (rx_pb_size > pb_headroom) 1135 rx_pb_size = rx_pb_size - pb_headroom; 1136 else 1137 rx_pb_size = 0; 1138 1139 /* Minimum of MFS shall be set for DMCTH */ 1140 reg |= (rx_pb_size > maxframe_size_kb) ? 1141 rx_pb_size : maxframe_size_kb; 1142 } 1143 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg); 1144 } 1145 return IXGBE_SUCCESS; 1146 } 1147 1148 /** 1149 * ixgbe_dmac_update_tcs_X550 1150 * @hw: pointer to hardware structure 1151 * 1152 * Disables dmac, updates per TC settings, and then enables dmac. 1153 **/ 1154 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw) 1155 { 1156 u32 reg; 1157 1158 DEBUGFUNC("ixgbe_dmac_update_tcs_X550"); 1159 1160 /* Disable DMA coalescing before configuring */ 1161 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 1162 reg &= ~IXGBE_DMACR_DMAC_EN; 1163 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 1164 1165 ixgbe_dmac_config_tcs_X550(hw); 1166 1167 /* Enable DMA coalescing after configuration */ 1168 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 1169 reg |= IXGBE_DMACR_DMAC_EN; 1170 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 1171 1172 return IXGBE_SUCCESS; 1173 } 1174 1175 /** 1176 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params 1177 * @hw: pointer to hardware structure 1178 * 1179 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 1180 * ixgbe_hw struct in order to set up EEPROM access. 1181 **/ 1182 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) 1183 { 1184 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1185 u32 eec; 1186 u16 eeprom_size; 1187 1188 DEBUGFUNC("ixgbe_init_eeprom_params_X550"); 1189 1190 if (eeprom->type == ixgbe_eeprom_uninitialized) { 1191 eeprom->semaphore_delay = 10; 1192 eeprom->type = ixgbe_flash; 1193 1194 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1195 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 1196 IXGBE_EEC_SIZE_SHIFT); 1197 eeprom->word_size = 1 << (eeprom_size + 1198 IXGBE_EEPROM_WORD_SIZE_SHIFT); 1199 1200 DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 1201 eeprom->type, eeprom->word_size); 1202 } 1203 1204 return IXGBE_SUCCESS; 1205 } 1206 1207 /** 1208 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning 1209 * @hw: pointer to hardware structure 1210 * @enable: enable or disable source address pruning 1211 * @pool: Rx pool to set source address pruning for 1212 **/ 1213 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable, 1214 unsigned int pool) 1215 { 1216 u64 pfflp; 1217 1218 /* max rx pool is 63 */ 1219 if (pool > 63) 1220 return; 1221 1222 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL); 1223 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32; 1224 1225 if (enable) 1226 pfflp |= (1ULL << pool); 1227 else 1228 pfflp &= ~(1ULL << pool); 1229 1230 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); 1231 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); 1232 } 1233 1234 /** 1235 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing 1236 * @hw: pointer to hardware structure 1237 * @enable: enable or disable switch for Ethertype anti-spoofing 1238 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1239 * 1240 **/ 1241 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, 1242 bool enable, int vf) 1243 { 1244 int vf_target_reg = vf >> 3; 1245 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT; 1246 u32 pfvfspoof; 1247 1248 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550"); 1249 1250 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 1251 if (enable) 1252 pfvfspoof |= (1 << vf_target_shift); 1253 else 1254 pfvfspoof &= ~(1 << vf_target_shift); 1255 1256 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 1257 } 1258 1259 /** 1260 * ixgbe_iosf_wait - Wait for IOSF command completion 1261 * @hw: pointer to hardware structure 1262 * @ctrl: pointer to location to receive final IOSF control value 1263 * 1264 * Returns failing status on timeout 1265 * 1266 * Note: ctrl can be NULL if the IOSF control register value is not needed 1267 **/ 1268 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) 1269 { 1270 u32 i, command = 0; 1271 1272 /* Check every 10 usec to see if the address cycle completed. 1273 * The SB IOSF BUSY bit will clear when the operation is 1274 * complete 1275 */ 1276 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 1277 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); 1278 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0) 1279 break; 1280 usec_delay(10); 1281 } 1282 if (ctrl) 1283 *ctrl = command; 1284 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { 1285 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n"); 1286 return IXGBE_ERR_PHY; 1287 } 1288 1289 return IXGBE_SUCCESS; 1290 } 1291 1292 /** 1293 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register 1294 * of the IOSF device 1295 * @hw: pointer to hardware structure 1296 * @reg_addr: 32 bit PHY register to write 1297 * @device_type: 3 bit device type 1298 * @data: Data to write to the register 1299 **/ 1300 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 1301 u32 device_type, u32 data) 1302 { 1303 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 1304 u32 command, error __unused; 1305 s32 ret; 1306 1307 ret = ixgbe_acquire_swfw_semaphore(hw, gssr); 1308 if (ret != IXGBE_SUCCESS) 1309 return ret; 1310 1311 ret = ixgbe_iosf_wait(hw, NULL); 1312 if (ret != IXGBE_SUCCESS) 1313 goto out; 1314 1315 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 1316 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 1317 1318 /* Write IOSF control register */ 1319 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 1320 1321 /* Write IOSF data register */ 1322 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); 1323 1324 ret = ixgbe_iosf_wait(hw, &command); 1325 1326 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 1327 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 1328 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 1329 ERROR_REPORT2(IXGBE_ERROR_POLLING, 1330 "Failed to write, error %x\n", error); 1331 ret = IXGBE_ERR_PHY; 1332 } 1333 1334 out: 1335 ixgbe_release_swfw_semaphore(hw, gssr); 1336 return ret; 1337 } 1338 1339 /** 1340 * ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device 1341 * @hw: pointer to hardware structure 1342 * @reg_addr: 32 bit PHY register to write 1343 * @device_type: 3 bit device type 1344 * @data: Pointer to read data from the register 1345 **/ 1346 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 1347 u32 device_type, u32 *data) 1348 { 1349 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 1350 u32 command, error __unused; 1351 s32 ret; 1352 1353 ret = ixgbe_acquire_swfw_semaphore(hw, gssr); 1354 if (ret != IXGBE_SUCCESS) 1355 return ret; 1356 1357 ret = ixgbe_iosf_wait(hw, NULL); 1358 if (ret != IXGBE_SUCCESS) 1359 goto out; 1360 1361 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 1362 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 1363 1364 /* Write IOSF control register */ 1365 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 1366 1367 ret = ixgbe_iosf_wait(hw, &command); 1368 1369 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 1370 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 1371 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 1372 ERROR_REPORT2(IXGBE_ERROR_POLLING, 1373 "Failed to read, error %x\n", error); 1374 ret = IXGBE_ERR_PHY; 1375 } 1376 1377 if (ret == IXGBE_SUCCESS) 1378 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); 1379 1380 out: 1381 ixgbe_release_swfw_semaphore(hw, gssr); 1382 return ret; 1383 } 1384 1385 /** 1386 * ixgbe_get_phy_token - Get the token for shared phy access 1387 * @hw: Pointer to hardware structure 1388 */ 1389 1390 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw) 1391 { 1392 struct ixgbe_hic_phy_token_req token_cmd; 1393 s32 status; 1394 1395 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 1396 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 1397 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 1398 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1399 token_cmd.port_number = hw->bus.lan_id; 1400 token_cmd.command_type = FW_PHY_TOKEN_REQ; 1401 token_cmd.pad = 0; 1402 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd, 1403 sizeof(token_cmd), 1404 IXGBE_HI_COMMAND_TIMEOUT, 1405 TRUE); 1406 if (status) { 1407 DEBUGOUT1("Issuing host interface command failed with Status = %d\n", 1408 status); 1409 return status; 1410 } 1411 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 1412 return IXGBE_SUCCESS; 1413 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) { 1414 DEBUGOUT1("Host interface command returned 0x%08x , returning IXGBE_ERR_FW_RESP_INVALID\n", 1415 token_cmd.hdr.cmd_or_resp.ret_status); 1416 return IXGBE_ERR_FW_RESP_INVALID; 1417 } 1418 1419 DEBUGOUT("Returning IXGBE_ERR_TOKEN_RETRY\n"); 1420 return IXGBE_ERR_TOKEN_RETRY; 1421 } 1422 1423 /** 1424 * ixgbe_put_phy_token - Put the token for shared phy access 1425 * @hw: Pointer to hardware structure 1426 */ 1427 1428 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw) 1429 { 1430 struct ixgbe_hic_phy_token_req token_cmd; 1431 s32 status; 1432 1433 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 1434 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 1435 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 1436 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1437 token_cmd.port_number = hw->bus.lan_id; 1438 token_cmd.command_type = FW_PHY_TOKEN_REL; 1439 token_cmd.pad = 0; 1440 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd, 1441 sizeof(token_cmd), 1442 IXGBE_HI_COMMAND_TIMEOUT, 1443 TRUE); 1444 if (status) 1445 return status; 1446 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 1447 return IXGBE_SUCCESS; 1448 1449 DEBUGOUT("Put PHY Token host interface command failed"); 1450 return IXGBE_ERR_FW_RESP_INVALID; 1451 } 1452 1453 /** 1454 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register 1455 * of the IOSF device 1456 * @hw: pointer to hardware structure 1457 * @reg_addr: 32 bit PHY register to write 1458 * @device_type: 3 bit device type 1459 * @data: Data to write to the register 1460 **/ 1461 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 1462 u32 device_type, u32 data) 1463 { 1464 struct ixgbe_hic_internal_phy_req write_cmd; 1465 s32 status; 1466 UNREFERENCED_1PARAMETER(device_type); 1467 1468 memset(&write_cmd, 0, sizeof(write_cmd)); 1469 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 1470 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 1471 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1472 write_cmd.port_number = hw->bus.lan_id; 1473 write_cmd.command_type = FW_INT_PHY_REQ_WRITE; 1474 write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr); 1475 write_cmd.write_data = IXGBE_CPU_TO_BE32(data); 1476 1477 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd, 1478 sizeof(write_cmd), 1479 IXGBE_HI_COMMAND_TIMEOUT, FALSE); 1480 1481 return status; 1482 } 1483 1484 /** 1485 * ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device 1486 * @hw: pointer to hardware structure 1487 * @reg_addr: 32 bit PHY register to write 1488 * @device_type: 3 bit device type 1489 * @data: Pointer to read data from the register 1490 **/ 1491 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 1492 u32 device_type, u32 *data) 1493 { 1494 union { 1495 struct ixgbe_hic_internal_phy_req cmd; 1496 struct ixgbe_hic_internal_phy_resp rsp; 1497 } hic; 1498 s32 status; 1499 UNREFERENCED_1PARAMETER(device_type); 1500 1501 memset(&hic, 0, sizeof(hic)); 1502 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 1503 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 1504 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1505 hic.cmd.port_number = hw->bus.lan_id; 1506 hic.cmd.command_type = FW_INT_PHY_REQ_READ; 1507 hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr); 1508 1509 status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd, 1510 sizeof(hic.cmd), 1511 IXGBE_HI_COMMAND_TIMEOUT, TRUE); 1512 1513 /* Extract the register value from the response. */ 1514 *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data); 1515 1516 return status; 1517 } 1518 1519 /** 1520 * ixgbe_disable_mdd_X550 1521 * @hw: pointer to hardware structure 1522 * 1523 * Disable malicious driver detection 1524 **/ 1525 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw) 1526 { 1527 u32 reg; 1528 1529 DEBUGFUNC("ixgbe_disable_mdd_X550"); 1530 1531 /* Disable MDD for TX DMA and interrupt */ 1532 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1533 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN); 1534 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1535 1536 /* Disable MDD for RX and interrupt */ 1537 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 1538 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN); 1539 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 1540 } 1541 1542 /** 1543 * ixgbe_enable_mdd_X550 1544 * @hw: pointer to hardware structure 1545 * 1546 * Enable malicious driver detection 1547 **/ 1548 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw) 1549 { 1550 u32 reg; 1551 1552 DEBUGFUNC("ixgbe_enable_mdd_X550"); 1553 1554 /* Enable MDD for TX DMA and interrupt */ 1555 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1556 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN); 1557 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1558 1559 /* Enable MDD for RX and interrupt */ 1560 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 1561 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN); 1562 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 1563 } 1564 1565 /** 1566 * ixgbe_restore_mdd_vf_X550 1567 * @hw: pointer to hardware structure 1568 * @vf: vf index 1569 * 1570 * Restore VF that was disabled during malicious driver detection event 1571 **/ 1572 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf) 1573 { 1574 u32 idx, reg, num_qs, start_q, bitmask; 1575 1576 DEBUGFUNC("ixgbe_restore_mdd_vf_X550"); 1577 1578 /* Map VF to queues */ 1579 reg = IXGBE_READ_REG(hw, IXGBE_MRQC); 1580 switch (reg & IXGBE_MRQC_MRQE_MASK) { 1581 case IXGBE_MRQC_VMDQRT8TCEN: 1582 num_qs = 8; /* 16 VFs / pools */ 1583 bitmask = 0x000000FF; 1584 break; 1585 case IXGBE_MRQC_VMDQRSS32EN: 1586 case IXGBE_MRQC_VMDQRT4TCEN: 1587 num_qs = 4; /* 32 VFs / pools */ 1588 bitmask = 0x0000000F; 1589 break; 1590 default: /* 64 VFs / pools */ 1591 num_qs = 2; 1592 bitmask = 0x00000003; 1593 break; 1594 } 1595 start_q = vf * num_qs; 1596 1597 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */ 1598 idx = start_q / 32; 1599 reg = 0; 1600 reg |= (bitmask << (start_q % 32)); 1601 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg); 1602 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg); 1603 } 1604 1605 /** 1606 * ixgbe_mdd_event_X550 1607 * @hw: pointer to hardware structure 1608 * @vf_bitmap: vf bitmap of malicious vfs 1609 * 1610 * Handle malicious driver detection event. 1611 **/ 1612 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap) 1613 { 1614 u32 wqbr; 1615 u32 i, j, reg, q, shift, vf, idx; 1616 1617 DEBUGFUNC("ixgbe_mdd_event_X550"); 1618 1619 /* figure out pool size for mapping to vf's */ 1620 reg = IXGBE_READ_REG(hw, IXGBE_MRQC); 1621 switch (reg & IXGBE_MRQC_MRQE_MASK) { 1622 case IXGBE_MRQC_VMDQRT8TCEN: 1623 shift = 3; /* 16 VFs / pools */ 1624 break; 1625 case IXGBE_MRQC_VMDQRSS32EN: 1626 case IXGBE_MRQC_VMDQRT4TCEN: 1627 shift = 2; /* 32 VFs / pools */ 1628 break; 1629 default: 1630 shift = 1; /* 64 VFs / pools */ 1631 break; 1632 } 1633 1634 /* Read WQBR_TX and WQBR_RX and check for malicious queues */ 1635 for (i = 0; i < 4; i++) { 1636 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i)); 1637 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i)); 1638 1639 if (!wqbr) 1640 continue; 1641 1642 /* Get malicious queue */ 1643 for (j = 0; j < 32 && wqbr; j++) { 1644 1645 if (!(wqbr & (1 << j))) 1646 continue; 1647 1648 /* Get queue from bitmask */ 1649 q = j + (i * 32); 1650 1651 /* Map queue to vf */ 1652 vf = (q >> shift); 1653 1654 /* Set vf bit in vf_bitmap */ 1655 idx = vf / 32; 1656 vf_bitmap[idx] |= (1 << (vf % 32)); 1657 wqbr &= ~(1 << j); 1658 } 1659 } 1660 } 1661 1662 /** 1663 * ixgbe_get_media_type_X550em - Get media type 1664 * @hw: pointer to hardware structure 1665 * 1666 * Returns the media type (fiber, copper, backplane) 1667 */ 1668 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) 1669 { 1670 enum ixgbe_media_type media_type; 1671 1672 DEBUGFUNC("ixgbe_get_media_type_X550em"); 1673 1674 /* Detect if there is a copper PHY attached. */ 1675 switch (hw->device_id) { 1676 case IXGBE_DEV_ID_X550EM_X_KR: 1677 case IXGBE_DEV_ID_X550EM_X_KX4: 1678 case IXGBE_DEV_ID_X550EM_X_XFI: 1679 case IXGBE_DEV_ID_X550EM_A_KR: 1680 case IXGBE_DEV_ID_X550EM_A_KR_L: 1681 media_type = ixgbe_media_type_backplane; 1682 break; 1683 case IXGBE_DEV_ID_X550EM_X_SFP: 1684 case IXGBE_DEV_ID_X550EM_A_SFP: 1685 case IXGBE_DEV_ID_X550EM_A_SFP_N: 1686 case IXGBE_DEV_ID_X550EM_A_QSFP: 1687 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 1688 media_type = ixgbe_media_type_fiber; 1689 break; 1690 case IXGBE_DEV_ID_X550EM_X_1G_T: 1691 case IXGBE_DEV_ID_X550EM_X_10G_T: 1692 case IXGBE_DEV_ID_X550EM_A_10G_T: 1693 media_type = ixgbe_media_type_copper; 1694 break; 1695 case IXGBE_DEV_ID_X550EM_A_SGMII: 1696 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 1697 media_type = ixgbe_media_type_backplane; 1698 hw->phy.type = ixgbe_phy_sgmii; 1699 break; 1700 case IXGBE_DEV_ID_X550EM_A_1G_T: 1701 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 1702 media_type = ixgbe_media_type_copper; 1703 break; 1704 default: 1705 media_type = ixgbe_media_type_unknown; 1706 break; 1707 } 1708 return media_type; 1709 } 1710 1711 /** 1712 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported 1713 * @hw: pointer to hardware structure 1714 * @linear: TRUE if SFP module is linear 1715 */ 1716 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear) 1717 { 1718 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em"); 1719 1720 switch (hw->phy.sfp_type) { 1721 case ixgbe_sfp_type_not_present: 1722 return IXGBE_ERR_SFP_NOT_PRESENT; 1723 case ixgbe_sfp_type_da_cu_core0: 1724 case ixgbe_sfp_type_da_cu_core1: 1725 *linear = TRUE; 1726 break; 1727 case ixgbe_sfp_type_srlr_core0: 1728 case ixgbe_sfp_type_srlr_core1: 1729 case ixgbe_sfp_type_da_act_lmt_core0: 1730 case ixgbe_sfp_type_da_act_lmt_core1: 1731 case ixgbe_sfp_type_1g_sx_core0: 1732 case ixgbe_sfp_type_1g_sx_core1: 1733 case ixgbe_sfp_type_1g_lx_core0: 1734 case ixgbe_sfp_type_1g_lx_core1: 1735 *linear = FALSE; 1736 break; 1737 case ixgbe_sfp_type_unknown: 1738 case ixgbe_sfp_type_1g_cu_core0: 1739 case ixgbe_sfp_type_1g_cu_core1: 1740 default: 1741 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1742 } 1743 1744 return IXGBE_SUCCESS; 1745 } 1746 1747 /** 1748 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules 1749 * @hw: pointer to hardware structure 1750 * 1751 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1752 **/ 1753 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw) 1754 { 1755 s32 status; 1756 bool linear; 1757 1758 DEBUGFUNC("ixgbe_identify_sfp_module_X550em"); 1759 1760 status = ixgbe_identify_module_generic(hw); 1761 1762 if (status != IXGBE_SUCCESS) 1763 return status; 1764 1765 /* Check if SFP module is supported */ 1766 status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 1767 1768 return status; 1769 } 1770 1771 /** 1772 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops 1773 * @hw: pointer to hardware structure 1774 */ 1775 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) 1776 { 1777 s32 status; 1778 bool linear; 1779 1780 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em"); 1781 1782 /* Check if SFP module is supported */ 1783 status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 1784 1785 if (status != IXGBE_SUCCESS) 1786 return status; 1787 1788 ixgbe_init_mac_link_ops_X550em(hw); 1789 hw->phy.ops.reset = NULL; 1790 1791 return IXGBE_SUCCESS; 1792 } 1793 1794 /** 1795 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the 1796 * internal PHY 1797 * @hw: pointer to hardware structure 1798 **/ 1799 static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw) 1800 { 1801 s32 status; 1802 u32 link_ctrl; 1803 1804 /* Restart auto-negotiation. */ 1805 status = hw->mac.ops.read_iosf_sb_reg(hw, 1806 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1807 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl); 1808 1809 if (status) { 1810 DEBUGOUT("Auto-negotiation did not complete\n"); 1811 return status; 1812 } 1813 1814 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1815 status = hw->mac.ops.write_iosf_sb_reg(hw, 1816 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1817 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl); 1818 1819 if (hw->mac.type == ixgbe_mac_X550EM_a) { 1820 u32 flx_mask_st20; 1821 1822 /* Indicate to FW that AN restart has been asserted */ 1823 status = hw->mac.ops.read_iosf_sb_reg(hw, 1824 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1825 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20); 1826 1827 if (status) { 1828 DEBUGOUT("Auto-negotiation did not complete\n"); 1829 return status; 1830 } 1831 1832 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART; 1833 status = hw->mac.ops.write_iosf_sb_reg(hw, 1834 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1835 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20); 1836 } 1837 1838 return status; 1839 } 1840 1841 /** 1842 * ixgbe_setup_sgmii - Set up link for sgmii 1843 * @hw: pointer to hardware structure 1844 */ 1845 static s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1846 bool autoneg_wait) 1847 { 1848 struct ixgbe_mac_info *mac = &hw->mac; 1849 u32 lval, sval, flx_val; 1850 s32 rc; 1851 1852 rc = mac->ops.read_iosf_sb_reg(hw, 1853 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1854 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 1855 if (rc) 1856 return rc; 1857 1858 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1859 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1860 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 1861 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 1862 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1863 rc = mac->ops.write_iosf_sb_reg(hw, 1864 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1865 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 1866 if (rc) 1867 return rc; 1868 1869 rc = mac->ops.read_iosf_sb_reg(hw, 1870 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1871 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 1872 if (rc) 1873 return rc; 1874 1875 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 1876 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 1877 rc = mac->ops.write_iosf_sb_reg(hw, 1878 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1879 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 1880 if (rc) 1881 return rc; 1882 1883 rc = mac->ops.read_iosf_sb_reg(hw, 1884 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1885 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 1886 if (rc) 1887 return rc; 1888 1889 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 1890 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 1891 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 1892 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 1893 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 1894 1895 rc = mac->ops.write_iosf_sb_reg(hw, 1896 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1897 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 1898 if (rc) 1899 return rc; 1900 1901 rc = ixgbe_restart_an_internal_phy_x550em(hw); 1902 if (rc) 1903 return rc; 1904 1905 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 1906 } 1907 1908 /** 1909 * ixgbe_setup_sgmii_fw - Set up link for internal PHY SGMII auto-negotiation 1910 * @hw: pointer to hardware structure 1911 */ 1912 static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1913 bool autoneg_wait) 1914 { 1915 struct ixgbe_mac_info *mac = &hw->mac; 1916 u32 lval, sval, flx_val; 1917 s32 rc; 1918 1919 rc = mac->ops.read_iosf_sb_reg(hw, 1920 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1921 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 1922 if (rc) 1923 return rc; 1924 1925 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1926 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1927 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 1928 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 1929 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1930 rc = mac->ops.write_iosf_sb_reg(hw, 1931 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1932 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 1933 if (rc) 1934 return rc; 1935 1936 rc = mac->ops.read_iosf_sb_reg(hw, 1937 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1938 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 1939 if (rc) 1940 return rc; 1941 1942 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 1943 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 1944 rc = mac->ops.write_iosf_sb_reg(hw, 1945 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1946 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 1947 if (rc) 1948 return rc; 1949 1950 rc = mac->ops.write_iosf_sb_reg(hw, 1951 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1952 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 1953 if (rc) 1954 return rc; 1955 1956 rc = mac->ops.read_iosf_sb_reg(hw, 1957 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1958 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 1959 if (rc) 1960 return rc; 1961 1962 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 1963 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 1964 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 1965 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 1966 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 1967 1968 rc = mac->ops.write_iosf_sb_reg(hw, 1969 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1970 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 1971 if (rc) 1972 return rc; 1973 1974 rc = ixgbe_restart_an_internal_phy_x550em(hw); 1975 1976 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 1977 } 1978 1979 /** 1980 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers 1981 * @hw: pointer to hardware structure 1982 */ 1983 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) 1984 { 1985 struct ixgbe_mac_info *mac = &hw->mac; 1986 1987 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em"); 1988 1989 switch (hw->mac.ops.get_media_type(hw)) { 1990 case ixgbe_media_type_fiber: 1991 /* CS4227 does not support autoneg, so disable the laser control 1992 * functions for SFP+ fiber 1993 */ 1994 mac->ops.disable_tx_laser = NULL; 1995 mac->ops.enable_tx_laser = NULL; 1996 mac->ops.flap_tx_laser = NULL; 1997 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 1998 mac->ops.set_rate_select_speed = 1999 ixgbe_set_soft_rate_select_speed; 2000 2001 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) || 2002 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP)) 2003 mac->ops.setup_mac_link = 2004 ixgbe_setup_mac_link_sfp_x550a; 2005 else 2006 mac->ops.setup_mac_link = 2007 ixgbe_setup_mac_link_sfp_x550em; 2008 break; 2009 case ixgbe_media_type_copper: 2010 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) 2011 break; 2012 if (hw->mac.type == ixgbe_mac_X550EM_a) { 2013 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 2014 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) { 2015 mac->ops.setup_link = ixgbe_setup_sgmii_fw; 2016 mac->ops.check_link = 2017 ixgbe_check_mac_link_generic; 2018 } else { 2019 mac->ops.setup_link = 2020 ixgbe_setup_mac_link_t_X550em; 2021 } 2022 } else { 2023 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 2024 mac->ops.check_link = ixgbe_check_link_t_X550em; 2025 } 2026 break; 2027 case ixgbe_media_type_backplane: 2028 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII || 2029 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) 2030 mac->ops.setup_link = ixgbe_setup_sgmii; 2031 break; 2032 default: 2033 break; 2034 } 2035 } 2036 2037 /** 2038 * ixgbe_get_link_capabilities_x550em - Determines link capabilities 2039 * @hw: pointer to hardware structure 2040 * @speed: pointer to link speed 2041 * @autoneg: TRUE when autoneg or autotry is enabled 2042 */ 2043 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, 2044 ixgbe_link_speed *speed, 2045 bool *autoneg) 2046 { 2047 DEBUGFUNC("ixgbe_get_link_capabilities_X550em"); 2048 2049 2050 if (hw->phy.type == ixgbe_phy_fw) { 2051 *autoneg = TRUE; 2052 *speed = hw->phy.speeds_supported; 2053 return 0; 2054 } 2055 2056 /* SFP */ 2057 if (hw->phy.media_type == ixgbe_media_type_fiber) { 2058 2059 /* CS4227 SFP must not enable auto-negotiation */ 2060 *autoneg = FALSE; 2061 2062 /* Check if 1G SFP module. */ 2063 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 2064 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 2065 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 2066 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) { 2067 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2068 return IXGBE_SUCCESS; 2069 } 2070 2071 /* Link capabilities are based on SFP */ 2072 if (hw->phy.multispeed_fiber) 2073 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2074 IXGBE_LINK_SPEED_1GB_FULL; 2075 else 2076 *speed = IXGBE_LINK_SPEED_10GB_FULL; 2077 } else { 2078 switch (hw->phy.type) { 2079 case ixgbe_phy_ext_1g_t: 2080 case ixgbe_phy_sgmii: 2081 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2082 break; 2083 case ixgbe_phy_x550em_kr: 2084 if (hw->mac.type == ixgbe_mac_X550EM_a) { 2085 /* check different backplane modes */ 2086 if (hw->phy.nw_mng_if_sel & 2087 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) { 2088 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 2089 break; 2090 } else if (hw->device_id == 2091 IXGBE_DEV_ID_X550EM_A_KR_L) { 2092 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2093 break; 2094 } 2095 } 2096 /* fall through */ 2097 default: 2098 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2099 IXGBE_LINK_SPEED_1GB_FULL; 2100 break; 2101 } 2102 *autoneg = TRUE; 2103 } 2104 2105 return IXGBE_SUCCESS; 2106 } 2107 2108 /** 2109 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause 2110 * @hw: pointer to hardware structure 2111 * @lsc: pointer to boolean flag which indicates whether external Base T 2112 * PHY interrupt is lsc 2113 * 2114 * Determime if external Base T PHY interrupt cause is high temperature 2115 * failure alarm or link status change. 2116 * 2117 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 2118 * failure alarm, else return PHY access status. 2119 */ 2120 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc) 2121 { 2122 u32 status; 2123 u16 reg; 2124 2125 *lsc = FALSE; 2126 2127 /* Vendor alarm triggered */ 2128 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2129 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2130 ®); 2131 2132 if (status != IXGBE_SUCCESS || 2133 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN)) 2134 return status; 2135 2136 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */ 2137 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, 2138 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2139 ®); 2140 2141 if (status != IXGBE_SUCCESS || 2142 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2143 IXGBE_MDIO_GLOBAL_ALARM_1_INT))) 2144 return status; 2145 2146 /* Global alarm triggered */ 2147 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, 2148 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2149 ®); 2150 2151 if (status != IXGBE_SUCCESS) 2152 return status; 2153 2154 /* If high temperature failure, then return over temp error and exit */ 2155 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) { 2156 /* power down the PHY in case the PHY FW didn't already */ 2157 ixgbe_set_copper_phy_power(hw, FALSE); 2158 return IXGBE_ERR_OVERTEMP; 2159 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) { 2160 /* device fault alarm triggered */ 2161 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG, 2162 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2163 ®); 2164 2165 if (status != IXGBE_SUCCESS) 2166 return status; 2167 2168 /* if device fault was due to high temp alarm handle and exit */ 2169 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) { 2170 /* power down the PHY in case the PHY FW didn't */ 2171 ixgbe_set_copper_phy_power(hw, FALSE); 2172 return IXGBE_ERR_OVERTEMP; 2173 } 2174 } 2175 2176 /* Vendor alarm 2 triggered */ 2177 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2178 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 2179 2180 if (status != IXGBE_SUCCESS || 2181 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT)) 2182 return status; 2183 2184 /* link connect/disconnect event occurred */ 2185 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2, 2186 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 2187 2188 if (status != IXGBE_SUCCESS) 2189 return status; 2190 2191 /* Indicate LSC */ 2192 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC) 2193 *lsc = TRUE; 2194 2195 return IXGBE_SUCCESS; 2196 } 2197 2198 /** 2199 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts 2200 * @hw: pointer to hardware structure 2201 * 2202 * Enable link status change and temperature failure alarm for the external 2203 * Base T PHY 2204 * 2205 * Returns PHY access status 2206 */ 2207 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw) 2208 { 2209 u32 status; 2210 u16 reg; 2211 bool lsc; 2212 2213 /* Clear interrupt flags */ 2214 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 2215 2216 /* Enable link status change alarm */ 2217 2218 /* Enable the LASI interrupts on X552 devices to receive notifications 2219 * of the link configurations of the external PHY and correspondingly 2220 * support the configuration of the internal iXFI link, since iXFI does 2221 * not support auto-negotiation. This is not required for X553 devices 2222 * having KR support, which performs auto-negotiations and which is used 2223 * as the internal link to the external PHY. Hence adding a check here 2224 * to avoid enabling LASI interrupts for X553 devices. 2225 */ 2226 if (hw->mac.type != ixgbe_mac_X550EM_a) { 2227 status = hw->phy.ops.read_reg(hw, 2228 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2229 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 2230 2231 if (status != IXGBE_SUCCESS) 2232 return status; 2233 2234 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN; 2235 2236 status = hw->phy.ops.write_reg(hw, 2237 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2238 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg); 2239 2240 if (status != IXGBE_SUCCESS) 2241 return status; 2242 } 2243 2244 /* Enable high temperature failure and global fault alarms */ 2245 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2246 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2247 ®); 2248 2249 if (status != IXGBE_SUCCESS) 2250 return status; 2251 2252 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN | 2253 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN); 2254 2255 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2256 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2257 reg); 2258 2259 if (status != IXGBE_SUCCESS) 2260 return status; 2261 2262 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */ 2263 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2264 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2265 ®); 2266 2267 if (status != IXGBE_SUCCESS) 2268 return status; 2269 2270 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2271 IXGBE_MDIO_GLOBAL_ALARM_1_INT); 2272 2273 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2274 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2275 reg); 2276 2277 if (status != IXGBE_SUCCESS) 2278 return status; 2279 2280 /* Enable chip-wide vendor alarm */ 2281 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2282 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2283 ®); 2284 2285 if (status != IXGBE_SUCCESS) 2286 return status; 2287 2288 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN; 2289 2290 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2291 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2292 reg); 2293 2294 return status; 2295 } 2296 2297 /** 2298 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed. 2299 * @hw: pointer to hardware structure 2300 * @speed: link speed 2301 * 2302 * Configures the integrated KR PHY. 2303 **/ 2304 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, 2305 ixgbe_link_speed speed) 2306 { 2307 s32 status; 2308 u32 reg_val; 2309 2310 status = hw->mac.ops.read_iosf_sb_reg(hw, 2311 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2312 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2313 if (status) 2314 return status; 2315 2316 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2317 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | 2318 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); 2319 2320 /* Advertise 10G support. */ 2321 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 2322 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; 2323 2324 /* Advertise 1G support. */ 2325 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 2326 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; 2327 2328 status = hw->mac.ops.write_iosf_sb_reg(hw, 2329 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2330 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2331 2332 if (hw->mac.type == ixgbe_mac_X550EM_a) { 2333 /* Set lane mode to KR auto negotiation */ 2334 status = hw->mac.ops.read_iosf_sb_reg(hw, 2335 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2336 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2337 2338 if (status) 2339 return status; 2340 2341 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2342 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 2343 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2344 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2345 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2346 2347 status = hw->mac.ops.write_iosf_sb_reg(hw, 2348 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2349 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2350 } 2351 2352 return ixgbe_restart_an_internal_phy_x550em(hw); 2353 } 2354 2355 /** 2356 * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs 2357 * @hw: pointer to hardware structure 2358 */ 2359 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw) 2360 { 2361 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 2362 s32 rc; 2363 2364 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 2365 return IXGBE_SUCCESS; 2366 2367 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store); 2368 if (rc) 2369 return rc; 2370 memset(store, 0, sizeof(store)); 2371 2372 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store); 2373 if (rc) 2374 return rc; 2375 2376 return ixgbe_setup_fw_link(hw); 2377 } 2378 2379 /** 2380 * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp 2381 * @hw: pointer to hardware structure 2382 */ 2383 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw) 2384 { 2385 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 2386 s32 rc; 2387 2388 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store); 2389 if (rc) 2390 return rc; 2391 2392 if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) { 2393 ixgbe_shutdown_fw_phy(hw); 2394 return IXGBE_ERR_OVERTEMP; 2395 } 2396 return IXGBE_SUCCESS; 2397 } 2398 2399 /** 2400 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register 2401 * @hw: pointer to hardware structure 2402 * 2403 * Read NW_MNG_IF_SEL register and save field values, and check for valid field 2404 * values. 2405 **/ 2406 static s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw) 2407 { 2408 /* Save NW management interface connected on board. This is used 2409 * to determine internal PHY mode. 2410 */ 2411 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 2412 2413 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set 2414 * PHY address. This register field was has only been used for X552. 2415 */ 2416 if (hw->mac.type == ixgbe_mac_X550EM_a && 2417 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) { 2418 hw->phy.addr = (hw->phy.nw_mng_if_sel & 2419 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 2420 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 2421 } 2422 2423 return IXGBE_SUCCESS; 2424 } 2425 2426 /** 2427 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init 2428 * @hw: pointer to hardware structure 2429 * 2430 * Initialize any function pointers that were not able to be 2431 * set during init_shared_code because the PHY/SFP type was 2432 * not known. Perform the SFP init if necessary. 2433 */ 2434 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) 2435 { 2436 struct ixgbe_phy_info *phy = &hw->phy; 2437 s32 ret_val; 2438 2439 DEBUGFUNC("ixgbe_init_phy_ops_X550em"); 2440 2441 hw->mac.ops.set_lan_id(hw); 2442 ixgbe_read_mng_if_sel_x550em(hw); 2443 2444 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { 2445 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 2446 ixgbe_setup_mux_ctl(hw); 2447 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em; 2448 } 2449 2450 switch (hw->device_id) { 2451 case IXGBE_DEV_ID_X550EM_A_1G_T: 2452 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2453 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22; 2454 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22; 2455 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a; 2456 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a; 2457 phy->ops.check_overtemp = ixgbe_check_overtemp_fw; 2458 if (hw->bus.lan_id) 2459 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; 2460 else 2461 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; 2462 2463 break; 2464 case IXGBE_DEV_ID_X550EM_A_10G_T: 2465 case IXGBE_DEV_ID_X550EM_A_SFP: 2466 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a; 2467 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a; 2468 if (hw->bus.lan_id) 2469 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; 2470 else 2471 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; 2472 break; 2473 case IXGBE_DEV_ID_X550EM_X_SFP: 2474 /* set up for CS4227 usage */ 2475 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 2476 break; 2477 case IXGBE_DEV_ID_X550EM_X_1G_T: 2478 phy->ops.read_reg_mdi = NULL; 2479 phy->ops.write_reg_mdi = NULL; 2480 break; 2481 default: 2482 break; 2483 } 2484 2485 /* Identify the PHY or SFP module */ 2486 ret_val = phy->ops.identify(hw); 2487 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED || 2488 ret_val == IXGBE_ERR_PHY_ADDR_INVALID) 2489 return ret_val; 2490 2491 /* Setup function pointers based on detected hardware */ 2492 ixgbe_init_mac_link_ops_X550em(hw); 2493 if (phy->sfp_type != ixgbe_sfp_type_unknown) 2494 phy->ops.reset = NULL; 2495 2496 /* Set functions pointers based on phy type */ 2497 switch (hw->phy.type) { 2498 case ixgbe_phy_x550em_kx4: 2499 phy->ops.setup_link = NULL; 2500 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 2501 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 2502 break; 2503 case ixgbe_phy_x550em_kr: 2504 phy->ops.setup_link = ixgbe_setup_kr_x550em; 2505 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 2506 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 2507 break; 2508 case ixgbe_phy_ext_1g_t: 2509 /* link is managed by FW */ 2510 phy->ops.setup_link = NULL; 2511 phy->ops.reset = NULL; 2512 break; 2513 case ixgbe_phy_x550em_xfi: 2514 /* link is managed by HW */ 2515 phy->ops.setup_link = NULL; 2516 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 2517 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 2518 break; 2519 case ixgbe_phy_x550em_ext_t: 2520 /* If internal link mode is XFI, then setup iXFI internal link, 2521 * else setup KR now. 2522 */ 2523 phy->ops.setup_internal_link = 2524 ixgbe_setup_internal_phy_t_x550em; 2525 2526 /* setup SW LPLU only for first revision of X550EM_x */ 2527 if ((hw->mac.type == ixgbe_mac_X550EM_x) && 2528 !(IXGBE_FUSES0_REV_MASK & 2529 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))) 2530 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em; 2531 2532 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; 2533 phy->ops.reset = ixgbe_reset_phy_t_X550em; 2534 break; 2535 case ixgbe_phy_sgmii: 2536 phy->ops.setup_link = NULL; 2537 break; 2538 case ixgbe_phy_fw: 2539 phy->ops.setup_link = ixgbe_setup_fw_link; 2540 phy->ops.reset = ixgbe_reset_phy_fw; 2541 break; 2542 default: 2543 break; 2544 } 2545 return ret_val; 2546 } 2547 2548 /** 2549 * ixgbe_set_mdio_speed - Set MDIO clock speed 2550 * @hw: pointer to hardware structure 2551 */ 2552 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw) 2553 { 2554 u32 hlreg0; 2555 2556 switch (hw->device_id) { 2557 case IXGBE_DEV_ID_X550EM_X_10G_T: 2558 case IXGBE_DEV_ID_X550EM_A_SGMII: 2559 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 2560 case IXGBE_DEV_ID_X550EM_A_10G_T: 2561 case IXGBE_DEV_ID_X550EM_A_SFP: 2562 case IXGBE_DEV_ID_X550EM_A_QSFP: 2563 /* Config MDIO clock speed before the first MDIO PHY access */ 2564 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 2565 hlreg0 &= ~IXGBE_HLREG0_MDCSPD; 2566 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 2567 break; 2568 case IXGBE_DEV_ID_X550EM_A_1G_T: 2569 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2570 /* Select fast MDIO clock speed for these devices */ 2571 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 2572 hlreg0 |= IXGBE_HLREG0_MDCSPD; 2573 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 2574 break; 2575 default: 2576 break; 2577 } 2578 } 2579 2580 /** 2581 * ixgbe_reset_hw_X550em - Perform hardware reset 2582 * @hw: pointer to hardware structure 2583 * 2584 * Resets the hardware by resetting the transmit and receive units, masks 2585 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 2586 * reset. 2587 */ 2588 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) 2589 { 2590 ixgbe_link_speed link_speed; 2591 s32 status; 2592 u32 ctrl = 0; 2593 u32 i; 2594 bool link_up = FALSE; 2595 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2596 2597 DEBUGFUNC("ixgbe_reset_hw_X550em"); 2598 2599 /* Call adapter stop to disable Tx/Rx and clear interrupts */ 2600 status = hw->mac.ops.stop_adapter(hw); 2601 if (status != IXGBE_SUCCESS) { 2602 DEBUGOUT1("Failed to stop adapter, STATUS = %d\n", status); 2603 return status; 2604 } 2605 /* flush pending Tx transactions */ 2606 ixgbe_clear_tx_pending(hw); 2607 2608 ixgbe_set_mdio_speed(hw); 2609 2610 /* PHY ops must be identified and initialized prior to reset */ 2611 status = hw->phy.ops.init(hw); 2612 2613 if (status) 2614 DEBUGOUT1("Failed to initialize PHY ops, STATUS = %d\n", 2615 status); 2616 2617 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED || 2618 status == IXGBE_ERR_PHY_ADDR_INVALID) { 2619 DEBUGOUT("Returning from reset HW due to PHY init failure\n"); 2620 return status; 2621 } 2622 2623 /* start the external PHY */ 2624 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 2625 status = ixgbe_init_ext_t_x550em(hw); 2626 if (status) { 2627 DEBUGOUT1("Failed to start the external PHY, STATUS = %d\n", 2628 status); 2629 return status; 2630 } 2631 } 2632 2633 /* Setup SFP module if there is one present. */ 2634 if (hw->phy.sfp_setup_needed) { 2635 status = hw->mac.ops.setup_sfp(hw); 2636 hw->phy.sfp_setup_needed = FALSE; 2637 } 2638 2639 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 2640 return status; 2641 2642 /* Reset PHY */ 2643 if (!hw->phy.reset_disable && hw->phy.ops.reset) { 2644 if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP) 2645 return IXGBE_ERR_OVERTEMP; 2646 } 2647 2648 mac_reset_top: 2649 /* Issue global reset to the MAC. Needs to be SW reset if link is up. 2650 * If link reset is used when link is up, it might reset the PHY when 2651 * mng is using it. If link is down or the flag to force full link 2652 * reset is set, then perform link reset. 2653 */ 2654 ctrl = IXGBE_CTRL_LNK_RST; 2655 if (!hw->force_full_reset) { 2656 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE); 2657 if (link_up) 2658 ctrl = IXGBE_CTRL_RST; 2659 } 2660 2661 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 2662 if (status != IXGBE_SUCCESS) { 2663 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 2664 "semaphore failed with %d", status); 2665 return IXGBE_ERR_SWFW_SYNC; 2666 } 2667 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 2668 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 2669 IXGBE_WRITE_FLUSH(hw); 2670 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2671 2672 /* Poll for reset bit to self-clear meaning reset is complete */ 2673 for (i = 0; i < 10; i++) { 2674 usec_delay(1); 2675 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 2676 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 2677 break; 2678 } 2679 2680 if (ctrl & IXGBE_CTRL_RST_MASK) { 2681 status = IXGBE_ERR_RESET_FAILED; 2682 DEBUGOUT("Reset polling failed to complete.\n"); 2683 } 2684 2685 msec_delay(50); 2686 2687 /* Double resets are required for recovery from certain error 2688 * conditions. Between resets, it is necessary to stall to 2689 * allow time for any pending HW events to complete. 2690 */ 2691 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 2692 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 2693 goto mac_reset_top; 2694 } 2695 2696 /* Store the permanent mac address */ 2697 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 2698 2699 /* Store MAC address from RAR0, clear receive address registers, and 2700 * clear the multicast table. Also reset num_rar_entries to 128, 2701 * since we modify this value when programming the SAN MAC address. 2702 */ 2703 hw->mac.num_rar_entries = 128; 2704 hw->mac.ops.init_rx_addrs(hw); 2705 2706 ixgbe_set_mdio_speed(hw); 2707 2708 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) 2709 ixgbe_setup_mux_ctl(hw); 2710 2711 if (status != IXGBE_SUCCESS) 2712 DEBUGOUT1("Reset HW failed, STATUS = %d\n", status); 2713 2714 return status; 2715 } 2716 2717 /** 2718 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. 2719 * @hw: pointer to hardware structure 2720 */ 2721 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) 2722 { 2723 u32 status; 2724 u16 reg; 2725 2726 status = hw->phy.ops.read_reg(hw, 2727 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 2728 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 2729 ®); 2730 2731 if (status != IXGBE_SUCCESS) 2732 return status; 2733 2734 /* If PHY FW reset completed bit is set then this is the first 2735 * SW instance after a power on so the PHY FW must be un-stalled. 2736 */ 2737 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 2738 status = hw->phy.ops.read_reg(hw, 2739 IXGBE_MDIO_GLOBAL_RES_PR_10, 2740 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2741 ®); 2742 2743 if (status != IXGBE_SUCCESS) 2744 return status; 2745 2746 reg &= ~IXGBE_MDIO_POWER_UP_STALL; 2747 2748 status = hw->phy.ops.write_reg(hw, 2749 IXGBE_MDIO_GLOBAL_RES_PR_10, 2750 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2751 reg); 2752 2753 if (status != IXGBE_SUCCESS) 2754 return status; 2755 } 2756 2757 return status; 2758 } 2759 2760 /** 2761 * ixgbe_setup_kr_x550em - Configure the KR PHY. 2762 * @hw: pointer to hardware structure 2763 **/ 2764 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) 2765 { 2766 /* leave link alone for 2.5G */ 2767 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL) 2768 return IXGBE_SUCCESS; 2769 2770 if (ixgbe_check_reset_blocked(hw)) 2771 return 0; 2772 2773 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); 2774 } 2775 2776 /** 2777 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP 2778 * @hw: pointer to hardware structure 2779 * 2780 * Configure the external PHY and the integrated KR PHY for SFP support. 2781 **/ 2782 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, 2783 ixgbe_link_speed speed, 2784 bool autoneg_wait_to_complete) 2785 { 2786 s32 ret_val; 2787 u16 reg_slice, reg_val; 2788 bool setup_linear = FALSE; 2789 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 2790 2791 /* Check if SFP module is supported and linear */ 2792 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 2793 2794 /* If no SFP module present, then return success. Return success since 2795 * there is no reason to configure CS4227 and SFP not present error is 2796 * not excepted in the setup MAC link flow. 2797 */ 2798 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 2799 return IXGBE_SUCCESS; 2800 2801 if (ret_val != IXGBE_SUCCESS) 2802 return ret_val; 2803 2804 /* Configure internal PHY for KR/KX. */ 2805 ixgbe_setup_kr_speed_x550em(hw, speed); 2806 2807 /* Configure CS4227 LINE side to proper mode. */ 2808 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + 2809 (hw->bus.lan_id << 12); 2810 if (setup_linear) 2811 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 2812 else 2813 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 2814 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice, 2815 reg_val); 2816 return ret_val; 2817 } 2818 2819 /** 2820 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode 2821 * @hw: pointer to hardware structure 2822 * @speed: the link speed to force 2823 * 2824 * Configures the integrated PHY for native SFI mode. Used to connect the 2825 * internal PHY directly to an SFP cage, without autonegotiation. 2826 **/ 2827 static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 2828 { 2829 struct ixgbe_mac_info *mac = &hw->mac; 2830 s32 status; 2831 u32 reg_val; 2832 2833 /* Disable all AN and force speed to 10G Serial. */ 2834 status = mac->ops.read_iosf_sb_reg(hw, 2835 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2836 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2837 if (status != IXGBE_SUCCESS) 2838 return status; 2839 2840 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2841 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2842 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2843 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2844 2845 /* Select forced link speed for internal PHY. */ 2846 switch (*speed) { 2847 case IXGBE_LINK_SPEED_10GB_FULL: 2848 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G; 2849 break; 2850 case IXGBE_LINK_SPEED_1GB_FULL: 2851 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 2852 break; 2853 case 0: 2854 /* media none (linkdown) */ 2855 break; 2856 default: 2857 /* Other link speeds are not supported by internal PHY. */ 2858 return IXGBE_ERR_LINK_SETUP; 2859 } 2860 2861 status = mac->ops.write_iosf_sb_reg(hw, 2862 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2863 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2864 2865 /* Toggle port SW reset by AN reset. */ 2866 status = ixgbe_restart_an_internal_phy_x550em(hw); 2867 2868 return status; 2869 } 2870 2871 /** 2872 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP 2873 * @hw: pointer to hardware structure 2874 * 2875 * Configure the the integrated PHY for SFP support. 2876 **/ 2877 static s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, 2878 ixgbe_link_speed speed, 2879 bool autoneg_wait_to_complete) 2880 { 2881 s32 ret_val; 2882 u16 reg_phy_ext; 2883 bool setup_linear = FALSE; 2884 u32 reg_slice, reg_phy_int, slice_offset; 2885 2886 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 2887 2888 /* Check if SFP module is supported and linear */ 2889 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 2890 2891 /* If no SFP module present, then return success. Return success since 2892 * SFP not present error is not excepted in the setup MAC link flow. 2893 */ 2894 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 2895 return IXGBE_SUCCESS; 2896 2897 if (ret_val != IXGBE_SUCCESS) 2898 return ret_val; 2899 2900 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) { 2901 /* Configure internal PHY for native SFI based on module type */ 2902 ret_val = hw->mac.ops.read_iosf_sb_reg(hw, 2903 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2904 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int); 2905 2906 if (ret_val != IXGBE_SUCCESS) 2907 return ret_val; 2908 2909 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA; 2910 if (!setup_linear) 2911 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR; 2912 2913 ret_val = hw->mac.ops.write_iosf_sb_reg(hw, 2914 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2915 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int); 2916 2917 if (ret_val != IXGBE_SUCCESS) 2918 return ret_val; 2919 2920 /* Setup SFI internal link. */ 2921 ret_val = ixgbe_setup_sfi_x550a(hw, &speed); 2922 } else { 2923 /* Configure internal PHY for KR/KX. */ 2924 ixgbe_setup_kr_speed_x550em(hw, speed); 2925 2926 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) { 2927 /* Find Address */ 2928 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n"); 2929 return IXGBE_ERR_PHY_ADDR_INVALID; 2930 } 2931 2932 /* Get external PHY SKU id */ 2933 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU, 2934 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 2935 2936 if (ret_val != IXGBE_SUCCESS) 2937 return ret_val; 2938 2939 /* When configuring quad port CS4223, the MAC instance is part 2940 * of the slice offset. 2941 */ 2942 if (reg_phy_ext == IXGBE_CS4223_SKU_ID) 2943 slice_offset = (hw->bus.lan_id + 2944 (hw->bus.instance_id << 1)) << 12; 2945 else 2946 slice_offset = hw->bus.lan_id << 12; 2947 2948 /* Configure CS4227/CS4223 LINE side to proper mode. */ 2949 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset; 2950 2951 ret_val = hw->phy.ops.read_reg(hw, reg_slice, 2952 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 2953 2954 if (ret_val != IXGBE_SUCCESS) 2955 return ret_val; 2956 2957 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) | 2958 (IXGBE_CS4227_EDC_MODE_SR << 1)); 2959 2960 if (setup_linear) 2961 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 2962 else 2963 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 2964 ret_val = hw->phy.ops.write_reg(hw, reg_slice, 2965 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext); 2966 2967 /* Flush previous write with a read */ 2968 ret_val = hw->phy.ops.read_reg(hw, reg_slice, 2969 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 2970 } 2971 return ret_val; 2972 } 2973 2974 /** 2975 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration 2976 * @hw: pointer to hardware structure 2977 * 2978 * iXfI configuration needed for ixgbe_mac_X550EM_x devices. 2979 **/ 2980 static s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw) 2981 { 2982 struct ixgbe_mac_info *mac = &hw->mac; 2983 s32 status; 2984 u32 reg_val; 2985 2986 /* Disable training protocol FSM. */ 2987 status = mac->ops.read_iosf_sb_reg(hw, 2988 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 2989 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2990 if (status != IXGBE_SUCCESS) 2991 return status; 2992 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; 2993 status = mac->ops.write_iosf_sb_reg(hw, 2994 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 2995 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2996 if (status != IXGBE_SUCCESS) 2997 return status; 2998 2999 /* Disable Flex from training TXFFE. */ 3000 status = mac->ops.read_iosf_sb_reg(hw, 3001 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 3002 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3003 if (status != IXGBE_SUCCESS) 3004 return status; 3005 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 3006 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 3007 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 3008 status = mac->ops.write_iosf_sb_reg(hw, 3009 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 3010 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3011 if (status != IXGBE_SUCCESS) 3012 return status; 3013 status = mac->ops.read_iosf_sb_reg(hw, 3014 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 3015 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3016 if (status != IXGBE_SUCCESS) 3017 return status; 3018 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 3019 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 3020 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 3021 status = mac->ops.write_iosf_sb_reg(hw, 3022 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 3023 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3024 if (status != IXGBE_SUCCESS) 3025 return status; 3026 3027 /* Enable override for coefficients. */ 3028 status = mac->ops.read_iosf_sb_reg(hw, 3029 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 3030 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3031 if (status != IXGBE_SUCCESS) 3032 return status; 3033 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; 3034 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; 3035 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; 3036 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; 3037 status = mac->ops.write_iosf_sb_reg(hw, 3038 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 3039 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3040 return status; 3041 } 3042 3043 /** 3044 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. 3045 * @hw: pointer to hardware structure 3046 * @speed: the link speed to force 3047 * 3048 * Configures the integrated KR PHY to use iXFI mode. Used to connect an 3049 * internal and external PHY at a specific speed, without autonegotiation. 3050 **/ 3051 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 3052 { 3053 struct ixgbe_mac_info *mac = &hw->mac; 3054 s32 status; 3055 u32 reg_val; 3056 3057 /* iXFI is only supported with X552 */ 3058 if (mac->type != ixgbe_mac_X550EM_x) 3059 return IXGBE_ERR_LINK_SETUP; 3060 3061 /* Disable AN and force speed to 10G Serial. */ 3062 status = mac->ops.read_iosf_sb_reg(hw, 3063 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 3064 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3065 if (status != IXGBE_SUCCESS) 3066 return status; 3067 3068 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 3069 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 3070 3071 /* Select forced link speed for internal PHY. */ 3072 switch (*speed) { 3073 case IXGBE_LINK_SPEED_10GB_FULL: 3074 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 3075 break; 3076 case IXGBE_LINK_SPEED_1GB_FULL: 3077 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 3078 break; 3079 default: 3080 /* Other link speeds are not supported by internal KR PHY. */ 3081 return IXGBE_ERR_LINK_SETUP; 3082 } 3083 3084 status = mac->ops.write_iosf_sb_reg(hw, 3085 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 3086 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3087 if (status != IXGBE_SUCCESS) 3088 return status; 3089 3090 /* Additional configuration needed for x550em_x */ 3091 if (hw->mac.type == ixgbe_mac_X550EM_x) { 3092 status = ixgbe_setup_ixfi_x550em_x(hw); 3093 if (status != IXGBE_SUCCESS) 3094 return status; 3095 } 3096 3097 /* Toggle port SW reset by AN reset. */ 3098 status = ixgbe_restart_an_internal_phy_x550em(hw); 3099 3100 return status; 3101 } 3102 3103 /** 3104 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status 3105 * @hw: address of hardware structure 3106 * @link_up: address of boolean to indicate link status 3107 * 3108 * Returns error code if unable to get link status. 3109 */ 3110 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up) 3111 { 3112 u32 ret; 3113 u16 autoneg_status; 3114 3115 *link_up = FALSE; 3116 3117 /* read this twice back to back to indicate current status */ 3118 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 3119 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3120 &autoneg_status); 3121 if (ret != IXGBE_SUCCESS) 3122 return ret; 3123 3124 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 3125 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3126 &autoneg_status); 3127 if (ret != IXGBE_SUCCESS) 3128 return ret; 3129 3130 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS); 3131 3132 return IXGBE_SUCCESS; 3133 } 3134 3135 /** 3136 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link 3137 * @hw: point to hardware structure 3138 * 3139 * Configures the link between the integrated KR PHY and the external X557 PHY 3140 * The driver will call this function when it gets a link status change 3141 * interrupt from the X557 PHY. This function configures the link speed 3142 * between the PHYs to match the link speed of the BASE-T link. 3143 * 3144 * A return of a non-zero value indicates an error, and the base driver should 3145 * not report link up. 3146 */ 3147 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw) 3148 { 3149 ixgbe_link_speed force_speed; 3150 bool link_up; 3151 u32 status; 3152 u16 speed; 3153 3154 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 3155 return IXGBE_ERR_CONFIG; 3156 3157 if (hw->mac.type == ixgbe_mac_X550EM_x && 3158 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 3159 /* If link is down, there is no setup necessary so return */ 3160 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3161 if (status != IXGBE_SUCCESS) 3162 return status; 3163 3164 if (!link_up) 3165 return IXGBE_SUCCESS; 3166 3167 status = hw->phy.ops.read_reg(hw, 3168 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 3169 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3170 &speed); 3171 if (status != IXGBE_SUCCESS) 3172 return status; 3173 3174 /* If link is still down - no setup is required so return */ 3175 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3176 if (status != IXGBE_SUCCESS) 3177 return status; 3178 if (!link_up) 3179 return IXGBE_SUCCESS; 3180 3181 /* clear everything but the speed and duplex bits */ 3182 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK; 3183 3184 switch (speed) { 3185 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL: 3186 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 3187 break; 3188 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL: 3189 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 3190 break; 3191 default: 3192 /* Internal PHY does not support anything else */ 3193 return IXGBE_ERR_INVALID_LINK_SETTINGS; 3194 } 3195 3196 return ixgbe_setup_ixfi_x550em(hw, &force_speed); 3197 } else { 3198 speed = IXGBE_LINK_SPEED_10GB_FULL | 3199 IXGBE_LINK_SPEED_1GB_FULL; 3200 return ixgbe_setup_kr_speed_x550em(hw, speed); 3201 } 3202 } 3203 3204 /** 3205 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback. 3206 * @hw: pointer to hardware structure 3207 * 3208 * Configures the integrated KR PHY to use internal loopback mode. 3209 **/ 3210 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw) 3211 { 3212 s32 status; 3213 u32 reg_val; 3214 3215 /* Disable AN and force speed to 10G Serial. */ 3216 status = hw->mac.ops.read_iosf_sb_reg(hw, 3217 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 3218 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3219 if (status != IXGBE_SUCCESS) 3220 return status; 3221 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 3222 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 3223 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 3224 status = hw->mac.ops.write_iosf_sb_reg(hw, 3225 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 3226 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3227 if (status != IXGBE_SUCCESS) 3228 return status; 3229 3230 /* Set near-end loopback clocks. */ 3231 status = hw->mac.ops.read_iosf_sb_reg(hw, 3232 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id), 3233 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3234 if (status != IXGBE_SUCCESS) 3235 return status; 3236 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B; 3237 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS; 3238 status = hw->mac.ops.write_iosf_sb_reg(hw, 3239 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id), 3240 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3241 if (status != IXGBE_SUCCESS) 3242 return status; 3243 3244 /* Set loopback enable. */ 3245 status = hw->mac.ops.read_iosf_sb_reg(hw, 3246 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id), 3247 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3248 if (status != IXGBE_SUCCESS) 3249 return status; 3250 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK; 3251 status = hw->mac.ops.write_iosf_sb_reg(hw, 3252 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id), 3253 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3254 if (status != IXGBE_SUCCESS) 3255 return status; 3256 3257 /* Training bypass. */ 3258 status = hw->mac.ops.read_iosf_sb_reg(hw, 3259 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 3260 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3261 if (status != IXGBE_SUCCESS) 3262 return status; 3263 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS; 3264 status = hw->mac.ops.write_iosf_sb_reg(hw, 3265 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 3266 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3267 3268 return status; 3269 } 3270 3271 /** 3272 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 3273 * assuming that the semaphore is already obtained. 3274 * @hw: pointer to hardware structure 3275 * @offset: offset of word in the EEPROM to read 3276 * @data: word read from the EEPROM 3277 * 3278 * Reads a 16 bit word from the EEPROM using the hostif. 3279 **/ 3280 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data) 3281 { 3282 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 3283 struct ixgbe_hic_read_shadow_ram buffer; 3284 s32 status; 3285 3286 DEBUGFUNC("ixgbe_read_ee_hostif_X550"); 3287 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 3288 buffer.hdr.req.buf_lenh = 0; 3289 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 3290 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 3291 3292 /* convert offset from words to bytes */ 3293 buffer.address = IXGBE_CPU_TO_BE32(offset * 2); 3294 /* one word */ 3295 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16)); 3296 buffer.pad2 = 0; 3297 buffer.pad3 = 0; 3298 3299 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 3300 if (status) 3301 return status; 3302 3303 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 3304 IXGBE_HI_COMMAND_TIMEOUT); 3305 if (!status) { 3306 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 3307 FW_NVM_DATA_OFFSET); 3308 } 3309 3310 hw->mac.ops.release_swfw_sync(hw, mask); 3311 return status; 3312 } 3313 3314 /** 3315 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif 3316 * @hw: pointer to hardware structure 3317 * @offset: offset of word in the EEPROM to read 3318 * @words: number of words 3319 * @data: word(s) read from the EEPROM 3320 * 3321 * Reads a 16 bit word(s) from the EEPROM using the hostif. 3322 **/ 3323 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 3324 u16 offset, u16 words, u16 *data) 3325 { 3326 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 3327 struct ixgbe_hic_read_shadow_ram buffer; 3328 u32 current_word = 0; 3329 u16 words_to_read; 3330 s32 status; 3331 u32 i; 3332 3333 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550"); 3334 3335 /* Take semaphore for the entire operation. */ 3336 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 3337 if (status) { 3338 DEBUGOUT("EEPROM read buffer - semaphore failed\n"); 3339 return status; 3340 } 3341 3342 while (words) { 3343 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 3344 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 3345 else 3346 words_to_read = words; 3347 3348 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 3349 buffer.hdr.req.buf_lenh = 0; 3350 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 3351 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 3352 3353 /* convert offset from words to bytes */ 3354 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2); 3355 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2); 3356 buffer.pad2 = 0; 3357 buffer.pad3 = 0; 3358 3359 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 3360 IXGBE_HI_COMMAND_TIMEOUT); 3361 3362 if (status) { 3363 DEBUGOUT("Host interface command failed\n"); 3364 goto out; 3365 } 3366 3367 for (i = 0; i < words_to_read; i++) { 3368 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + 3369 2 * i; 3370 u32 value = IXGBE_READ_REG(hw, reg); 3371 3372 data[current_word] = (u16)(value & 0xffff); 3373 current_word++; 3374 i++; 3375 if (i < words_to_read) { 3376 value >>= 16; 3377 data[current_word] = (u16)(value & 0xffff); 3378 current_word++; 3379 } 3380 } 3381 words -= words_to_read; 3382 } 3383 3384 out: 3385 hw->mac.ops.release_swfw_sync(hw, mask); 3386 return status; 3387 } 3388 3389 /** 3390 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 3391 * @hw: pointer to hardware structure 3392 * @offset: offset of word in the EEPROM to write 3393 * @data: word write to the EEPROM 3394 * 3395 * Write a 16 bit word to the EEPROM using the hostif. 3396 **/ 3397 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 3398 u16 data) 3399 { 3400 s32 status; 3401 struct ixgbe_hic_write_shadow_ram buffer; 3402 3403 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550"); 3404 3405 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; 3406 buffer.hdr.req.buf_lenh = 0; 3407 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; 3408 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 3409 3410 /* one word */ 3411 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16)); 3412 buffer.data = data; 3413 buffer.address = IXGBE_CPU_TO_BE32(offset * 2); 3414 3415 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 3416 sizeof(buffer), 3417 IXGBE_HI_COMMAND_TIMEOUT, FALSE); 3418 3419 return status; 3420 } 3421 3422 /** 3423 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 3424 * @hw: pointer to hardware structure 3425 * @offset: offset of word in the EEPROM to write 3426 * @data: word write to the EEPROM 3427 * 3428 * Write a 16 bit word to the EEPROM using the hostif. 3429 **/ 3430 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, 3431 u16 data) 3432 { 3433 s32 status = IXGBE_SUCCESS; 3434 3435 DEBUGFUNC("ixgbe_write_ee_hostif_X550"); 3436 3437 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 3438 IXGBE_SUCCESS) { 3439 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); 3440 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 3441 } else { 3442 DEBUGOUT("write ee hostif failed to get semaphore"); 3443 status = IXGBE_ERR_SWFW_SYNC; 3444 } 3445 3446 return status; 3447 } 3448 3449 /** 3450 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif 3451 * @hw: pointer to hardware structure 3452 * @offset: offset of word in the EEPROM to write 3453 * @words: number of words 3454 * @data: word(s) write to the EEPROM 3455 * 3456 * Write a 16 bit word(s) to the EEPROM using the hostif. 3457 **/ 3458 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 3459 u16 offset, u16 words, u16 *data) 3460 { 3461 s32 status = IXGBE_SUCCESS; 3462 u32 i = 0; 3463 3464 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550"); 3465 3466 /* Take semaphore for the entire operation. */ 3467 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 3468 if (status != IXGBE_SUCCESS) { 3469 DEBUGOUT("EEPROM write buffer - semaphore failed\n"); 3470 goto out; 3471 } 3472 3473 for (i = 0; i < words; i++) { 3474 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, 3475 data[i]); 3476 3477 if (status != IXGBE_SUCCESS) { 3478 DEBUGOUT("Eeprom buffered write failed\n"); 3479 break; 3480 } 3481 } 3482 3483 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 3484 out: 3485 3486 return status; 3487 } 3488 3489 /** 3490 * ixgbe_checksum_ptr_x550 - Checksum one pointer region 3491 * @hw: pointer to hardware structure 3492 * @ptr: pointer offset in eeprom 3493 * @size: size of section pointed by ptr, if 0 first word will be used as size 3494 * @csum: address of checksum to update 3495 * 3496 * Returns error status for any failure 3497 */ 3498 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, 3499 u16 size, u16 *csum, u16 *buffer, 3500 u32 buffer_size) 3501 { 3502 u16 buf[256]; 3503 s32 status; 3504 u16 length, bufsz, i, start; 3505 u16 *local_buffer; 3506 3507 bufsz = sizeof(buf) / sizeof(buf[0]); 3508 3509 /* Read a chunk at the pointer location */ 3510 if (!buffer) { 3511 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); 3512 if (status) { 3513 DEBUGOUT("Failed to read EEPROM image\n"); 3514 return status; 3515 } 3516 local_buffer = buf; 3517 } else { 3518 if (buffer_size < ptr) 3519 return IXGBE_ERR_PARAM; 3520 local_buffer = &buffer[ptr]; 3521 } 3522 3523 if (size) { 3524 start = 0; 3525 length = size; 3526 } else { 3527 start = 1; 3528 length = local_buffer[0]; 3529 3530 /* Skip pointer section if length is invalid. */ 3531 if (length == 0xFFFF || length == 0 || 3532 (ptr + length) >= hw->eeprom.word_size) 3533 return IXGBE_SUCCESS; 3534 } 3535 3536 if (buffer && ((u32)start + (u32)length > buffer_size)) 3537 return IXGBE_ERR_PARAM; 3538 3539 for (i = start; length; i++, length--) { 3540 if (i == bufsz && !buffer) { 3541 ptr += bufsz; 3542 i = 0; 3543 if (length < bufsz) 3544 bufsz = length; 3545 3546 /* Read a chunk at the pointer location */ 3547 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, 3548 bufsz, buf); 3549 if (status) { 3550 DEBUGOUT("Failed to read EEPROM image\n"); 3551 return status; 3552 } 3553 } 3554 *csum += local_buffer[i]; 3555 } 3556 return IXGBE_SUCCESS; 3557 } 3558 3559 /** 3560 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum 3561 * @hw: pointer to hardware structure 3562 * @buffer: pointer to buffer containing calculated checksum 3563 * @buffer_size: size of buffer 3564 * 3565 * Returns a negative error code on error, or the 16-bit checksum 3566 **/ 3567 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size) 3568 { 3569 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1]; 3570 u16 *local_buffer; 3571 s32 status; 3572 u16 checksum = 0; 3573 u16 pointer, i, size; 3574 3575 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550"); 3576 3577 hw->eeprom.ops.init_params(hw); 3578 3579 if (!buffer) { 3580 /* Read pointer area */ 3581 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, 3582 IXGBE_EEPROM_LAST_WORD + 1, 3583 eeprom_ptrs); 3584 if (status) { 3585 DEBUGOUT("Failed to read EEPROM image\n"); 3586 return status; 3587 } 3588 local_buffer = eeprom_ptrs; 3589 } else { 3590 if (buffer_size < IXGBE_EEPROM_LAST_WORD) 3591 return IXGBE_ERR_PARAM; 3592 local_buffer = buffer; 3593 } 3594 3595 /* 3596 * For X550 hardware include 0x0-0x41 in the checksum, skip the 3597 * checksum word itself 3598 */ 3599 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++) 3600 if (i != IXGBE_EEPROM_CHECKSUM) 3601 checksum += local_buffer[i]; 3602 3603 /* 3604 * Include all data from pointers 0x3, 0x6-0xE. This excludes the 3605 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 3606 */ 3607 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) { 3608 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 3609 continue; 3610 3611 pointer = local_buffer[i]; 3612 3613 /* Skip pointer section if the pointer is invalid. */ 3614 if (pointer == 0xFFFF || pointer == 0 || 3615 pointer >= hw->eeprom.word_size) 3616 continue; 3617 3618 switch (i) { 3619 case IXGBE_PCIE_GENERAL_PTR: 3620 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE; 3621 break; 3622 case IXGBE_PCIE_CONFIG0_PTR: 3623 case IXGBE_PCIE_CONFIG1_PTR: 3624 size = IXGBE_PCIE_CONFIG_SIZE; 3625 break; 3626 default: 3627 size = 0; 3628 break; 3629 } 3630 3631 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, 3632 buffer, buffer_size); 3633 if (status) 3634 return status; 3635 } 3636 3637 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 3638 3639 return (s32)checksum; 3640 } 3641 3642 /** 3643 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum 3644 * @hw: pointer to hardware structure 3645 * 3646 * Returns a negative error code on error, or the 16-bit checksum 3647 **/ 3648 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) 3649 { 3650 return ixgbe_calc_checksum_X550(hw, NULL, 0); 3651 } 3652 3653 /** 3654 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum 3655 * @hw: pointer to hardware structure 3656 * @checksum_val: calculated checksum 3657 * 3658 * Performs checksum calculation and validates the EEPROM checksum. If the 3659 * caller does not need checksum_val, the value can be NULL. 3660 **/ 3661 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val) 3662 { 3663 s32 status; 3664 u16 checksum; 3665 u16 read_checksum = 0; 3666 3667 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550"); 3668 3669 /* Read the first word from the EEPROM. If this times out or fails, do 3670 * not continue or we could be in for a very long wait while every 3671 * EEPROM read fails 3672 */ 3673 status = hw->eeprom.ops.read(hw, 0, &checksum); 3674 if (status) { 3675 DEBUGOUT("EEPROM read failed\n"); 3676 return status; 3677 } 3678 3679 status = hw->eeprom.ops.calc_checksum(hw); 3680 if (status < 0) 3681 return status; 3682 3683 checksum = (u16)(status & 0xffff); 3684 3685 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 3686 &read_checksum); 3687 if (status) 3688 return status; 3689 3690 /* Verify read checksum from EEPROM is the same as 3691 * calculated checksum 3692 */ 3693 if (read_checksum != checksum) { 3694 status = IXGBE_ERR_EEPROM_CHECKSUM; 3695 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 3696 "Invalid EEPROM checksum"); 3697 } 3698 3699 /* If the user cares, return the calculated checksum */ 3700 if (checksum_val) 3701 *checksum_val = checksum; 3702 3703 return status; 3704 } 3705 3706 /** 3707 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash 3708 * @hw: pointer to hardware structure 3709 * 3710 * After writing EEPROM to shadow RAM using EEWR register, software calculates 3711 * checksum and updates the EEPROM and instructs the hardware to update 3712 * the flash. 3713 **/ 3714 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) 3715 { 3716 s32 status; 3717 u16 checksum = 0; 3718 3719 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550"); 3720 3721 /* Read the first word from the EEPROM. If this times out or fails, do 3722 * not continue or we could be in for a very long wait while every 3723 * EEPROM read fails 3724 */ 3725 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); 3726 if (status) { 3727 DEBUGOUT("EEPROM read failed\n"); 3728 return status; 3729 } 3730 3731 status = ixgbe_calc_eeprom_checksum_X550(hw); 3732 if (status < 0) 3733 return status; 3734 3735 checksum = (u16)(status & 0xffff); 3736 3737 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 3738 checksum); 3739 if (status) 3740 return status; 3741 3742 status = ixgbe_update_flash_X550(hw); 3743 3744 return status; 3745 } 3746 3747 /** 3748 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device 3749 * @hw: pointer to hardware structure 3750 * 3751 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash. 3752 **/ 3753 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) 3754 { 3755 s32 status = IXGBE_SUCCESS; 3756 union ixgbe_hic_hdr2 buffer; 3757 3758 DEBUGFUNC("ixgbe_update_flash_X550"); 3759 3760 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; 3761 buffer.req.buf_lenh = 0; 3762 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; 3763 buffer.req.checksum = FW_DEFAULT_CHECKSUM; 3764 3765 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 3766 sizeof(buffer), 3767 IXGBE_HI_COMMAND_TIMEOUT, FALSE); 3768 3769 return status; 3770 } 3771 3772 /** 3773 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type 3774 * @hw: pointer to hardware structure 3775 * 3776 * Determines physical layer capabilities of the current configuration. 3777 **/ 3778 u64 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw) 3779 { 3780 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 3781 u16 ext_ability = 0; 3782 3783 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em"); 3784 3785 hw->phy.ops.identify(hw); 3786 3787 switch (hw->phy.type) { 3788 case ixgbe_phy_x550em_kr: 3789 if (hw->mac.type == ixgbe_mac_X550EM_a) { 3790 if (hw->phy.nw_mng_if_sel & 3791 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) { 3792 physical_layer = 3793 IXGBE_PHYSICAL_LAYER_2500BASE_KX; 3794 break; 3795 } else if (hw->device_id == 3796 IXGBE_DEV_ID_X550EM_A_KR_L) { 3797 physical_layer = 3798 IXGBE_PHYSICAL_LAYER_1000BASE_KX; 3799 break; 3800 } 3801 } 3802 /* fall through */ 3803 case ixgbe_phy_x550em_xfi: 3804 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR | 3805 IXGBE_PHYSICAL_LAYER_1000BASE_KX; 3806 break; 3807 case ixgbe_phy_x550em_kx4: 3808 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 | 3809 IXGBE_PHYSICAL_LAYER_1000BASE_KX; 3810 break; 3811 case ixgbe_phy_x550em_ext_t: 3812 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 3813 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 3814 &ext_ability); 3815 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 3816 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 3817 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 3818 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 3819 break; 3820 case ixgbe_phy_fw: 3821 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_1GB_FULL) 3822 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 3823 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_100_FULL) 3824 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 3825 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_10_FULL) 3826 physical_layer |= IXGBE_PHYSICAL_LAYER_10BASE_T; 3827 break; 3828 case ixgbe_phy_sgmii: 3829 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; 3830 break; 3831 case ixgbe_phy_ext_1g_t: 3832 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 3833 break; 3834 default: 3835 break; 3836 } 3837 3838 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) 3839 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw); 3840 3841 return physical_layer; 3842 } 3843 3844 /** 3845 * ixgbe_get_bus_info_x550em - Set PCI bus info 3846 * @hw: pointer to hardware structure 3847 * 3848 * Sets bus link width and speed to unknown because X550em is 3849 * not a PCI device. 3850 **/ 3851 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw) 3852 { 3853 3854 DEBUGFUNC("ixgbe_get_bus_info_x550em"); 3855 3856 hw->bus.width = ixgbe_bus_width_unknown; 3857 hw->bus.speed = ixgbe_bus_speed_unknown; 3858 3859 hw->mac.ops.set_lan_id(hw); 3860 3861 return IXGBE_SUCCESS; 3862 } 3863 3864 /** 3865 * ixgbe_disable_rx_x550 - Disable RX unit 3866 * 3867 * Enables the Rx DMA unit for x550 3868 **/ 3869 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) 3870 { 3871 u32 rxctrl, pfdtxgswc; 3872 s32 status; 3873 struct ixgbe_hic_disable_rxen fw_cmd; 3874 3875 DEBUGFUNC("ixgbe_disable_rx_dma_x550"); 3876 3877 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 3878 if (rxctrl & IXGBE_RXCTRL_RXEN) { 3879 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 3880 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 3881 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 3882 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 3883 hw->mac.set_lben = TRUE; 3884 } else { 3885 hw->mac.set_lben = FALSE; 3886 } 3887 3888 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD; 3889 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN; 3890 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 3891 fw_cmd.port_number = (u8)hw->bus.lan_id; 3892 3893 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 3894 sizeof(struct ixgbe_hic_disable_rxen), 3895 IXGBE_HI_COMMAND_TIMEOUT, TRUE); 3896 3897 /* If we fail - disable RX using register write */ 3898 if (status) { 3899 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 3900 if (rxctrl & IXGBE_RXCTRL_RXEN) { 3901 rxctrl &= ~IXGBE_RXCTRL_RXEN; 3902 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 3903 } 3904 } 3905 } 3906 } 3907 3908 /** 3909 * ixgbe_enter_lplu_x550em - Transition to low power states 3910 * @hw: pointer to hardware structure 3911 * 3912 * Configures Low Power Link Up on transition to low power states 3913 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the 3914 * X557 PHY immediately prior to entering LPLU. 3915 **/ 3916 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) 3917 { 3918 u16 an_10g_cntl_reg, autoneg_reg, speed; 3919 s32 status; 3920 ixgbe_link_speed lcd_speed; 3921 u32 save_autoneg; 3922 bool link_up; 3923 3924 /* SW LPLU not required on later HW revisions. */ 3925 if ((hw->mac.type == ixgbe_mac_X550EM_x) && 3926 (IXGBE_FUSES0_REV_MASK & 3927 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))) 3928 return IXGBE_SUCCESS; 3929 3930 /* If blocked by MNG FW, then don't restart AN */ 3931 if (ixgbe_check_reset_blocked(hw)) 3932 return IXGBE_SUCCESS; 3933 3934 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3935 if (status != IXGBE_SUCCESS) 3936 return status; 3937 3938 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3); 3939 3940 if (status != IXGBE_SUCCESS) 3941 return status; 3942 3943 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability 3944 * disabled, then force link down by entering low power mode. 3945 */ 3946 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) || 3947 !(hw->wol_enabled || ixgbe_mng_present(hw))) 3948 return ixgbe_set_copper_phy_power(hw, FALSE); 3949 3950 /* Determine LCD */ 3951 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed); 3952 3953 if (status != IXGBE_SUCCESS) 3954 return status; 3955 3956 /* If no valid LCD link speed, then force link down and exit. */ 3957 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN) 3958 return ixgbe_set_copper_phy_power(hw, FALSE); 3959 3960 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 3961 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3962 &speed); 3963 3964 if (status != IXGBE_SUCCESS) 3965 return status; 3966 3967 /* If no link now, speed is invalid so take link down */ 3968 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3969 if (status != IXGBE_SUCCESS) 3970 return ixgbe_set_copper_phy_power(hw, FALSE); 3971 3972 /* clear everything but the speed bits */ 3973 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK; 3974 3975 /* If current speed is already LCD, then exit. */ 3976 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) && 3977 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) || 3978 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) && 3979 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL))) 3980 return status; 3981 3982 /* Clear AN completed indication */ 3983 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM, 3984 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3985 &autoneg_reg); 3986 3987 if (status != IXGBE_SUCCESS) 3988 return status; 3989 3990 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 3991 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3992 &an_10g_cntl_reg); 3993 3994 if (status != IXGBE_SUCCESS) 3995 return status; 3996 3997 status = hw->phy.ops.read_reg(hw, 3998 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 3999 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 4000 &autoneg_reg); 4001 4002 if (status != IXGBE_SUCCESS) 4003 return status; 4004 4005 save_autoneg = hw->phy.autoneg_advertised; 4006 4007 /* Setup link at least common link speed */ 4008 status = hw->mac.ops.setup_link(hw, lcd_speed, FALSE); 4009 4010 /* restore autoneg from before setting lplu speed */ 4011 hw->phy.autoneg_advertised = save_autoneg; 4012 4013 return status; 4014 } 4015 4016 /** 4017 * ixgbe_get_lcd_x550em - Determine lowest common denominator 4018 * @hw: pointer to hardware structure 4019 * @lcd_speed: pointer to lowest common link speed 4020 * 4021 * Determine lowest common link speed with link partner. 4022 **/ 4023 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed) 4024 { 4025 u16 an_lp_status; 4026 s32 status; 4027 u16 word = hw->eeprom.ctrl_word_3; 4028 4029 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN; 4030 4031 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS, 4032 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 4033 &an_lp_status); 4034 4035 if (status != IXGBE_SUCCESS) 4036 return status; 4037 4038 /* If link partner advertised 1G, return 1G */ 4039 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) { 4040 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL; 4041 return status; 4042 } 4043 4044 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */ 4045 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) || 4046 (word & NVM_INIT_CTRL_3_D10GMP_PORT0)) 4047 return status; 4048 4049 /* Link partner not capable of lower speeds, return 10G */ 4050 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL; 4051 return status; 4052 } 4053 4054 /** 4055 * ixgbe_setup_fc_X550em - Set up flow control 4056 * @hw: pointer to hardware structure 4057 * 4058 * Called at init time to set up flow control. 4059 **/ 4060 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw) 4061 { 4062 s32 ret_val = IXGBE_SUCCESS; 4063 u32 pause, asm_dir, reg_val; 4064 4065 DEBUGFUNC("ixgbe_setup_fc_X550em"); 4066 4067 /* Validate the requested mode */ 4068 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 4069 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 4070 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 4071 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4072 goto out; 4073 } 4074 4075 /* 10gig parts do not have a word in the EEPROM to determine the 4076 * default flow control setting, so we explicitly set it to full. 4077 */ 4078 if (hw->fc.requested_mode == ixgbe_fc_default) 4079 hw->fc.requested_mode = ixgbe_fc_full; 4080 4081 /* Determine PAUSE and ASM_DIR bits. */ 4082 switch (hw->fc.requested_mode) { 4083 case ixgbe_fc_none: 4084 pause = 0; 4085 asm_dir = 0; 4086 break; 4087 case ixgbe_fc_tx_pause: 4088 pause = 0; 4089 asm_dir = 1; 4090 break; 4091 case ixgbe_fc_rx_pause: 4092 /* Rx Flow control is enabled and Tx Flow control is 4093 * disabled by software override. Since there really 4094 * isn't a way to advertise that we are capable of RX 4095 * Pause ONLY, we will advertise that we support both 4096 * symmetric and asymmetric Rx PAUSE, as such we fall 4097 * through to the fc_full statement. Later, we will 4098 * disable the adapter's ability to send PAUSE frames. 4099 */ 4100 case ixgbe_fc_full: 4101 pause = 1; 4102 asm_dir = 1; 4103 break; 4104 default: 4105 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 4106 "Flow control param set incorrectly\n"); 4107 ret_val = IXGBE_ERR_CONFIG; 4108 goto out; 4109 } 4110 4111 switch (hw->device_id) { 4112 case IXGBE_DEV_ID_X550EM_X_KR: 4113 case IXGBE_DEV_ID_X550EM_A_KR: 4114 case IXGBE_DEV_ID_X550EM_A_KR_L: 4115 ret_val = hw->mac.ops.read_iosf_sb_reg(hw, 4116 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 4117 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 4118 if (ret_val != IXGBE_SUCCESS) 4119 goto out; 4120 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 4121 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 4122 if (pause) 4123 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 4124 if (asm_dir) 4125 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 4126 ret_val = hw->mac.ops.write_iosf_sb_reg(hw, 4127 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 4128 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 4129 4130 /* This device does not fully support AN. */ 4131 hw->fc.disable_fc_autoneg = TRUE; 4132 break; 4133 case IXGBE_DEV_ID_X550EM_X_XFI: 4134 hw->fc.disable_fc_autoneg = TRUE; 4135 break; 4136 default: 4137 break; 4138 } 4139 4140 out: 4141 return ret_val; 4142 } 4143 4144 /** 4145 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37 4146 * @hw: pointer to hardware structure 4147 * 4148 * Enable flow control according to IEEE clause 37. 4149 **/ 4150 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw) 4151 { 4152 u32 link_s1, lp_an_page_low, an_cntl_1; 4153 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 4154 ixgbe_link_speed speed; 4155 bool link_up; 4156 4157 /* AN should have completed when the cable was plugged in. 4158 * Look for reasons to bail out. Bail out if: 4159 * - FC autoneg is disabled, or if 4160 * - link is not up. 4161 */ 4162 if (hw->fc.disable_fc_autoneg) { 4163 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 4164 "Flow control autoneg is disabled"); 4165 goto out; 4166 } 4167 4168 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 4169 if (!link_up) { 4170 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); 4171 goto out; 4172 } 4173 4174 /* Check at auto-negotiation has completed */ 4175 status = hw->mac.ops.read_iosf_sb_reg(hw, 4176 IXGBE_KRM_LINK_S1(hw->bus.lan_id), 4177 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1); 4178 4179 if (status != IXGBE_SUCCESS || 4180 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) { 4181 DEBUGOUT("Auto-Negotiation did not complete\n"); 4182 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 4183 goto out; 4184 } 4185 4186 /* Read the 10g AN autoc and LP ability registers and resolve 4187 * local flow control settings accordingly 4188 */ 4189 status = hw->mac.ops.read_iosf_sb_reg(hw, 4190 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 4191 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1); 4192 4193 if (status != IXGBE_SUCCESS) { 4194 DEBUGOUT("Auto-Negotiation did not complete\n"); 4195 goto out; 4196 } 4197 4198 status = hw->mac.ops.read_iosf_sb_reg(hw, 4199 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id), 4200 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low); 4201 4202 if (status != IXGBE_SUCCESS) { 4203 DEBUGOUT("Auto-Negotiation did not complete\n"); 4204 goto out; 4205 } 4206 4207 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low, 4208 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE, 4209 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE, 4210 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE, 4211 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE); 4212 4213 out: 4214 if (status == IXGBE_SUCCESS) { 4215 hw->fc.fc_was_autonegged = TRUE; 4216 } else { 4217 hw->fc.fc_was_autonegged = FALSE; 4218 hw->fc.current_mode = hw->fc.requested_mode; 4219 } 4220 } 4221 4222 /** 4223 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings 4224 * @hw: pointer to hardware structure 4225 * 4226 **/ 4227 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw) 4228 { 4229 hw->fc.fc_was_autonegged = FALSE; 4230 hw->fc.current_mode = hw->fc.requested_mode; 4231 } 4232 4233 /** 4234 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37 4235 * @hw: pointer to hardware structure 4236 * 4237 * Enable flow control according to IEEE clause 37. 4238 **/ 4239 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw) 4240 { 4241 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 4242 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 4243 ixgbe_link_speed speed; 4244 bool link_up; 4245 4246 /* AN should have completed when the cable was plugged in. 4247 * Look for reasons to bail out. Bail out if: 4248 * - FC autoneg is disabled, or if 4249 * - link is not up. 4250 */ 4251 if (hw->fc.disable_fc_autoneg) { 4252 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 4253 "Flow control autoneg is disabled"); 4254 goto out; 4255 } 4256 4257 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 4258 if (!link_up) { 4259 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); 4260 goto out; 4261 } 4262 4263 /* Check if auto-negotiation has completed */ 4264 status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info); 4265 if (status != IXGBE_SUCCESS || 4266 !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) { 4267 DEBUGOUT("Auto-Negotiation did not complete\n"); 4268 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 4269 goto out; 4270 } 4271 4272 /* Negotiate the flow control */ 4273 status = ixgbe_negotiate_fc(hw, info[0], info[0], 4274 FW_PHY_ACT_GET_LINK_INFO_FC_RX, 4275 FW_PHY_ACT_GET_LINK_INFO_FC_TX, 4276 FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX, 4277 FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX); 4278 4279 out: 4280 if (status == IXGBE_SUCCESS) { 4281 hw->fc.fc_was_autonegged = TRUE; 4282 } else { 4283 hw->fc.fc_was_autonegged = FALSE; 4284 hw->fc.current_mode = hw->fc.requested_mode; 4285 } 4286 } 4287 4288 /** 4289 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control 4290 * @hw: pointer to hardware structure 4291 * 4292 * Called at init time to set up flow control. 4293 **/ 4294 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw) 4295 { 4296 s32 status = IXGBE_SUCCESS; 4297 u32 an_cntl = 0; 4298 4299 DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a"); 4300 4301 /* Validate the requested mode */ 4302 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 4303 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 4304 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 4305 return IXGBE_ERR_INVALID_LINK_SETTINGS; 4306 } 4307 4308 if (hw->fc.requested_mode == ixgbe_fc_default) 4309 hw->fc.requested_mode = ixgbe_fc_full; 4310 4311 /* Set up the 1G and 10G flow control advertisement registers so the 4312 * HW will be able to do FC autoneg once the cable is plugged in. If 4313 * we link at 10G, the 1G advertisement is harmless and vice versa. 4314 */ 4315 status = hw->mac.ops.read_iosf_sb_reg(hw, 4316 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 4317 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl); 4318 4319 if (status != IXGBE_SUCCESS) { 4320 DEBUGOUT("Auto-Negotiation did not complete\n"); 4321 return status; 4322 } 4323 4324 /* The possible values of fc.requested_mode are: 4325 * 0: Flow control is completely disabled 4326 * 1: Rx flow control is enabled (we can receive pause frames, 4327 * but not send pause frames). 4328 * 2: Tx flow control is enabled (we can send pause frames but 4329 * we do not support receiving pause frames). 4330 * 3: Both Rx and Tx flow control (symmetric) are enabled. 4331 * other: Invalid. 4332 */ 4333 switch (hw->fc.requested_mode) { 4334 case ixgbe_fc_none: 4335 /* Flow control completely disabled by software override. */ 4336 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 4337 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 4338 break; 4339 case ixgbe_fc_tx_pause: 4340 /* Tx Flow control is enabled, and Rx Flow control is 4341 * disabled by software override. 4342 */ 4343 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 4344 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 4345 break; 4346 case ixgbe_fc_rx_pause: 4347 /* Rx Flow control is enabled and Tx Flow control is 4348 * disabled by software override. Since there really 4349 * isn't a way to advertise that we are capable of RX 4350 * Pause ONLY, we will advertise that we support both 4351 * symmetric and asymmetric Rx PAUSE, as such we fall 4352 * through to the fc_full statement. Later, we will 4353 * disable the adapter's ability to send PAUSE frames. 4354 */ 4355 case ixgbe_fc_full: 4356 /* Flow control (both Rx and Tx) is enabled by SW override. */ 4357 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 4358 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 4359 break; 4360 default: 4361 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 4362 "Flow control param set incorrectly\n"); 4363 return IXGBE_ERR_CONFIG; 4364 } 4365 4366 status = hw->mac.ops.write_iosf_sb_reg(hw, 4367 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 4368 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl); 4369 4370 /* Restart auto-negotiation. */ 4371 status = ixgbe_restart_an_internal_phy_x550em(hw); 4372 4373 return status; 4374 } 4375 4376 /** 4377 * ixgbe_set_mux - Set mux for port 1 access with CS4227 4378 * @hw: pointer to hardware structure 4379 * @state: set mux if 1, clear if 0 4380 */ 4381 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state) 4382 { 4383 u32 esdp; 4384 4385 if (!hw->bus.lan_id) 4386 return; 4387 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 4388 if (state) 4389 esdp |= IXGBE_ESDP_SDP1; 4390 else 4391 esdp &= ~IXGBE_ESDP_SDP1; 4392 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4393 IXGBE_WRITE_FLUSH(hw); 4394 } 4395 4396 /** 4397 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore 4398 * @hw: pointer to hardware structure 4399 * @mask: Mask to specify which semaphore to acquire 4400 * 4401 * Acquires the SWFW semaphore and sets the I2C MUX 4402 **/ 4403 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 4404 { 4405 s32 status; 4406 4407 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em"); 4408 4409 status = ixgbe_acquire_swfw_sync_X540(hw, mask); 4410 if (status) 4411 return status; 4412 4413 if (mask & IXGBE_GSSR_I2C_MASK) 4414 ixgbe_set_mux(hw, 1); 4415 4416 return IXGBE_SUCCESS; 4417 } 4418 4419 /** 4420 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore 4421 * @hw: pointer to hardware structure 4422 * @mask: Mask to specify which semaphore to release 4423 * 4424 * Releases the SWFW semaphore and sets the I2C MUX 4425 **/ 4426 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 4427 { 4428 DEBUGFUNC("ixgbe_release_swfw_sync_X550em"); 4429 4430 if (mask & IXGBE_GSSR_I2C_MASK) 4431 ixgbe_set_mux(hw, 0); 4432 4433 ixgbe_release_swfw_sync_X540(hw, mask); 4434 } 4435 4436 /** 4437 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore 4438 * @hw: pointer to hardware structure 4439 * @mask: Mask to specify which semaphore to acquire 4440 * 4441 * Acquires the SWFW semaphore and get the shared phy token as needed 4442 */ 4443 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask) 4444 { 4445 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 4446 int retries = FW_PHY_TOKEN_RETRIES; 4447 s32 status = IXGBE_SUCCESS; 4448 4449 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a"); 4450 4451 while (--retries) { 4452 status = IXGBE_SUCCESS; 4453 if (hmask) 4454 status = ixgbe_acquire_swfw_sync_X540(hw, hmask); 4455 if (status) { 4456 DEBUGOUT1("Could not acquire SWFW semaphore, Status = %d\n", 4457 status); 4458 return status; 4459 } 4460 if (!(mask & IXGBE_GSSR_TOKEN_SM)) 4461 return IXGBE_SUCCESS; 4462 4463 status = ixgbe_get_phy_token(hw); 4464 if (status == IXGBE_ERR_TOKEN_RETRY) 4465 DEBUGOUT1("Could not acquire PHY token, Status = %d\n", 4466 status); 4467 4468 if (status == IXGBE_SUCCESS) 4469 return IXGBE_SUCCESS; 4470 4471 if (hmask) 4472 ixgbe_release_swfw_sync_X540(hw, hmask); 4473 4474 if (status != IXGBE_ERR_TOKEN_RETRY) { 4475 DEBUGOUT1("Unable to retry acquiring the PHY token, Status = %d\n", 4476 status); 4477 return status; 4478 } 4479 } 4480 4481 DEBUGOUT1("Semaphore acquisition retries failed!: PHY ID = 0x%08X\n", 4482 hw->phy.id); 4483 return status; 4484 } 4485 4486 /** 4487 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore 4488 * @hw: pointer to hardware structure 4489 * @mask: Mask to specify which semaphore to release 4490 * 4491 * Releases the SWFW semaphore and puts the shared phy token as needed 4492 */ 4493 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask) 4494 { 4495 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 4496 4497 DEBUGFUNC("ixgbe_release_swfw_sync_X550a"); 4498 4499 if (mask & IXGBE_GSSR_TOKEN_SM) 4500 ixgbe_put_phy_token(hw); 4501 4502 if (hmask) 4503 ixgbe_release_swfw_sync_X540(hw, hmask); 4504 } 4505 4506 /** 4507 * ixgbe_read_phy_reg_x550a - Reads specified PHY register 4508 * @hw: pointer to hardware structure 4509 * @reg_addr: 32 bit address of PHY register to read 4510 * @phy_data: Pointer to read data from PHY register 4511 * 4512 * Reads a value from a specified PHY register using the SWFW lock and PHY 4513 * Token. The PHY Token is needed since the MDIO is shared between to MAC 4514 * instances. 4515 **/ 4516 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 4517 u32 device_type, u16 *phy_data) 4518 { 4519 s32 status; 4520 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 4521 4522 DEBUGFUNC("ixgbe_read_phy_reg_x550a"); 4523 4524 if (hw->mac.ops.acquire_swfw_sync(hw, mask)) 4525 return IXGBE_ERR_SWFW_SYNC; 4526 4527 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 4528 4529 hw->mac.ops.release_swfw_sync(hw, mask); 4530 4531 return status; 4532 } 4533 4534 /** 4535 * ixgbe_write_phy_reg_x550a - Writes specified PHY register 4536 * @hw: pointer to hardware structure 4537 * @reg_addr: 32 bit PHY register to write 4538 * @device_type: 5 bit device type 4539 * @phy_data: Data to write to the PHY register 4540 * 4541 * Writes a value to specified PHY register using the SWFW lock and PHY Token. 4542 * The PHY Token is needed since the MDIO is shared between to MAC instances. 4543 **/ 4544 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 4545 u32 device_type, u16 phy_data) 4546 { 4547 s32 status; 4548 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 4549 4550 DEBUGFUNC("ixgbe_write_phy_reg_x550a"); 4551 4552 if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) { 4553 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, 4554 phy_data); 4555 hw->mac.ops.release_swfw_sync(hw, mask); 4556 } else { 4557 status = IXGBE_ERR_SWFW_SYNC; 4558 } 4559 4560 return status; 4561 } 4562 4563 /** 4564 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt 4565 * @hw: pointer to hardware structure 4566 * 4567 * Handle external Base T PHY interrupt. If high temperature 4568 * failure alarm then return error, else if link status change 4569 * then setup internal/external PHY link 4570 * 4571 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 4572 * failure alarm, else return PHY access status. 4573 */ 4574 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw) 4575 { 4576 bool lsc; 4577 u32 status; 4578 4579 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 4580 4581 if (status != IXGBE_SUCCESS) 4582 return status; 4583 4584 if (lsc) 4585 return ixgbe_setup_internal_phy(hw); 4586 4587 return IXGBE_SUCCESS; 4588 } 4589 4590 /** 4591 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed 4592 * @hw: pointer to hardware structure 4593 * @speed: new link speed 4594 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 4595 * 4596 * Setup internal/external PHY link speed based on link speed, then set 4597 * external PHY auto advertised link speed. 4598 * 4599 * Returns error status for any failure 4600 **/ 4601 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, 4602 ixgbe_link_speed speed, 4603 bool autoneg_wait_to_complete) 4604 { 4605 s32 status; 4606 ixgbe_link_speed force_speed; 4607 4608 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em"); 4609 4610 /* Setup internal/external PHY link speed to iXFI (10G), unless 4611 * only 1G is auto advertised then setup KX link. 4612 */ 4613 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 4614 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 4615 else 4616 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 4617 4618 /* If X552 and internal link mode is XFI, then setup XFI internal link. 4619 */ 4620 if (hw->mac.type == ixgbe_mac_X550EM_x && 4621 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 4622 status = ixgbe_setup_ixfi_x550em(hw, &force_speed); 4623 4624 if (status != IXGBE_SUCCESS) 4625 return status; 4626 } 4627 4628 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); 4629 } 4630 4631 /** 4632 * ixgbe_check_link_t_X550em - Determine link and speed status 4633 * @hw: pointer to hardware structure 4634 * @speed: pointer to link speed 4635 * @link_up: TRUE when link is up 4636 * @link_up_wait_to_complete: bool used to wait for link up or not 4637 * 4638 * Check that both the MAC and X557 external PHY have link. 4639 **/ 4640 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4641 bool *link_up, bool link_up_wait_to_complete) 4642 { 4643 u32 status; 4644 u16 i, autoneg_status = 0; 4645 4646 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 4647 return IXGBE_ERR_CONFIG; 4648 4649 status = ixgbe_check_mac_link_generic(hw, speed, link_up, 4650 link_up_wait_to_complete); 4651 4652 /* If check link fails or MAC link is not up, then return */ 4653 if (status != IXGBE_SUCCESS || !(*link_up)) 4654 return status; 4655 4656 /* MAC link is up, so check external PHY link. 4657 * X557 PHY. Link status is latching low, and can only be used to detect 4658 * link drop, and not the current status of the link without performing 4659 * back-to-back reads. 4660 */ 4661 for (i = 0; i < 2; i++) { 4662 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 4663 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 4664 &autoneg_status); 4665 4666 if (status != IXGBE_SUCCESS) 4667 return status; 4668 } 4669 4670 /* If external PHY link is not up, then indicate link not up */ 4671 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) 4672 *link_up = FALSE; 4673 4674 return IXGBE_SUCCESS; 4675 } 4676 4677 /** 4678 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI 4679 * @hw: pointer to hardware structure 4680 **/ 4681 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw) 4682 { 4683 s32 status; 4684 4685 status = ixgbe_reset_phy_generic(hw); 4686 4687 if (status != IXGBE_SUCCESS) 4688 return status; 4689 4690 /* Configure Link Status Alarm and Temperature Threshold interrupts */ 4691 return ixgbe_enable_lasi_ext_t_x550em(hw); 4692 } 4693 4694 /** 4695 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs. 4696 * @hw: pointer to hardware structure 4697 * @led_idx: led number to turn on 4698 **/ 4699 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx) 4700 { 4701 u16 phy_data; 4702 4703 DEBUGFUNC("ixgbe_led_on_t_X550em"); 4704 4705 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 4706 return IXGBE_ERR_PARAM; 4707 4708 /* To turn on the LED, set mode to ON. */ 4709 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 4710 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data); 4711 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK; 4712 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 4713 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data); 4714 4715 /* Some designs have the LEDs wired to the MAC */ 4716 return ixgbe_led_on_generic(hw, led_idx); 4717 } 4718 4719 /** 4720 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs. 4721 * @hw: pointer to hardware structure 4722 * @led_idx: led number to turn off 4723 **/ 4724 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx) 4725 { 4726 u16 phy_data; 4727 4728 DEBUGFUNC("ixgbe_led_off_t_X550em"); 4729 4730 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 4731 return IXGBE_ERR_PARAM; 4732 4733 /* To turn on the LED, set mode to ON. */ 4734 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 4735 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data); 4736 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK; 4737 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 4738 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data); 4739 4740 /* Some designs have the LEDs wired to the MAC */ 4741 return ixgbe_led_off_generic(hw, led_idx); 4742 } 4743 4744 /** 4745 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware 4746 * @hw: pointer to the HW structure 4747 * @maj: driver version major number 4748 * @min: driver version minor number 4749 * @build: driver version build number 4750 * @sub: driver version sub build number 4751 * @len: length of driver_ver string 4752 * @driver_ver: driver string 4753 * 4754 * Sends driver version number to firmware through the manageability 4755 * block. On success return IXGBE_SUCCESS 4756 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 4757 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4758 **/ 4759 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min, 4760 u8 build, u8 sub, u16 len, const char *driver_ver) 4761 { 4762 struct ixgbe_hic_drv_info2 fw_cmd; 4763 s32 ret_val = IXGBE_SUCCESS; 4764 int i; 4765 4766 DEBUGFUNC("ixgbe_set_fw_drv_ver_x550"); 4767 4768 if ((len == 0) || (driver_ver == NULL) || 4769 (len > sizeof(fw_cmd.driver_string))) 4770 return IXGBE_ERR_INVALID_ARGUMENT; 4771 4772 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 4773 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len; 4774 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 4775 fw_cmd.port_num = (u8)hw->bus.func; 4776 fw_cmd.ver_maj = maj; 4777 fw_cmd.ver_min = min; 4778 fw_cmd.ver_build = build; 4779 fw_cmd.ver_sub = sub; 4780 fw_cmd.hdr.checksum = 0; 4781 memcpy(fw_cmd.driver_string, driver_ver, len); 4782 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 4783 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 4784 4785 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 4786 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 4787 sizeof(fw_cmd), 4788 IXGBE_HI_COMMAND_TIMEOUT, 4789 TRUE); 4790 if (ret_val != IXGBE_SUCCESS) 4791 continue; 4792 4793 if (fw_cmd.hdr.cmd_or_resp.ret_status == 4794 FW_CEM_RESP_STATUS_SUCCESS) 4795 ret_val = IXGBE_SUCCESS; 4796 else 4797 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4798 4799 break; 4800 } 4801 4802 return ret_val; 4803 } 4804
Indexes created Tue Sep 30 07:10:03 GMT 2025