ixgbe_x550.c revision 1.7
1 /****************************************************************************** 2 3 Copyright (c) 2001-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x550.c 320688 2017-07-05 17:27:03Z erj $*/ 34 35 #include "ixgbe_x550.h" 36 #include "ixgbe_x540.h" 37 #include "ixgbe_type.h" 38 #include "ixgbe_api.h" 39 #include "ixgbe_common.h" 40 #include "ixgbe_phy.h" 41 #include <dev/mii/mii.h> 42 43 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed); 44 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask); 45 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask); 46 static s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw); 47 48 /** 49 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type 50 * @hw: pointer to hardware structure 51 * 52 * Initialize the function pointers and assign the MAC type for X550. 53 * Does not touch the hardware. 54 **/ 55 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw) 56 { 57 struct ixgbe_mac_info *mac = &hw->mac; 58 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 59 s32 ret_val; 60 61 DEBUGFUNC("ixgbe_init_ops_X550"); 62 63 ret_val = ixgbe_init_ops_X540(hw); 64 mac->ops.dmac_config = ixgbe_dmac_config_X550; 65 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550; 66 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550; 67 mac->ops.setup_eee = NULL; 68 mac->ops.set_source_address_pruning = 69 ixgbe_set_source_address_pruning_X550; 70 mac->ops.set_ethertype_anti_spoofing = 71 ixgbe_set_ethertype_anti_spoofing_X550; 72 73 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; 74 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550; 75 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550; 76 eeprom->ops.read = ixgbe_read_ee_hostif_X550; 77 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550; 78 eeprom->ops.write = ixgbe_write_ee_hostif_X550; 79 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550; 80 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550; 81 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550; 82 83 mac->ops.disable_mdd = ixgbe_disable_mdd_X550; 84 mac->ops.enable_mdd = ixgbe_enable_mdd_X550; 85 mac->ops.mdd_event = ixgbe_mdd_event_X550; 86 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550; 87 mac->ops.disable_rx = ixgbe_disable_rx_x550; 88 /* Manageability interface */ 89 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550; 90 switch (hw->device_id) { 91 case IXGBE_DEV_ID_X550EM_X_1G_T: 92 hw->mac.ops.led_on = NULL; 93 hw->mac.ops.led_off = NULL; 94 break; 95 case IXGBE_DEV_ID_X550EM_X_10G_T: 96 case IXGBE_DEV_ID_X550EM_A_10G_T: 97 hw->mac.ops.led_on = ixgbe_led_on_t_X550em; 98 hw->mac.ops.led_off = ixgbe_led_off_t_X550em; 99 break; 100 default: 101 break; 102 } 103 return ret_val; 104 } 105 106 /** 107 * ixgbe_read_cs4227 - Read CS4227 register 108 * @hw: pointer to hardware structure 109 * @reg: register number to write 110 * @value: pointer to receive value read 111 * 112 * Returns status code 113 **/ 114 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value) 115 { 116 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value); 117 } 118 119 /** 120 * ixgbe_write_cs4227 - Write CS4227 register 121 * @hw: pointer to hardware structure 122 * @reg: register number to write 123 * @value: value to write to register 124 * 125 * Returns status code 126 **/ 127 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) 128 { 129 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value); 130 } 131 132 /** 133 * ixgbe_read_pe - Read register from port expander 134 * @hw: pointer to hardware structure 135 * @reg: register number to read 136 * @value: pointer to receive read value 137 * 138 * Returns status code 139 **/ 140 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) 141 { 142 s32 status; 143 144 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value); 145 if (status != IXGBE_SUCCESS) 146 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 147 "port expander access failed with %d\n", status); 148 return status; 149 } 150 151 /** 152 * ixgbe_write_pe - Write register to port expander 153 * @hw: pointer to hardware structure 154 * @reg: register number to write 155 * @value: value to write 156 * 157 * Returns status code 158 **/ 159 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value) 160 { 161 s32 status; 162 163 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value); 164 if (status != IXGBE_SUCCESS) 165 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 166 "port expander access failed with %d\n", status); 167 return status; 168 } 169 170 /** 171 * ixgbe_reset_cs4227 - Reset CS4227 using port expander 172 * @hw: pointer to hardware structure 173 * 174 * This function assumes that the caller has acquired the proper semaphore. 175 * Returns error code 176 **/ 177 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw) 178 { 179 s32 status; 180 u32 retry; 181 u16 value; 182 u8 reg; 183 184 /* Trigger hard reset. */ 185 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 186 if (status != IXGBE_SUCCESS) 187 return status; 188 reg |= IXGBE_PE_BIT1; 189 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 190 if (status != IXGBE_SUCCESS) 191 return status; 192 193 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®); 194 if (status != IXGBE_SUCCESS) 195 return status; 196 reg &= ~IXGBE_PE_BIT1; 197 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg); 198 if (status != IXGBE_SUCCESS) 199 return status; 200 201 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 202 if (status != IXGBE_SUCCESS) 203 return status; 204 reg &= ~IXGBE_PE_BIT1; 205 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 206 if (status != IXGBE_SUCCESS) 207 return status; 208 209 usec_delay(IXGBE_CS4227_RESET_HOLD); 210 211 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 212 if (status != IXGBE_SUCCESS) 213 return status; 214 reg |= IXGBE_PE_BIT1; 215 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 216 if (status != IXGBE_SUCCESS) 217 return status; 218 219 /* Wait for the reset to complete. */ 220 msec_delay(IXGBE_CS4227_RESET_DELAY); 221 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 222 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS, 223 &value); 224 if (status == IXGBE_SUCCESS && 225 value == IXGBE_CS4227_EEPROM_LOAD_OK) 226 break; 227 msec_delay(IXGBE_CS4227_CHECK_DELAY); 228 } 229 if (retry == IXGBE_CS4227_RETRIES) { 230 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 231 "CS4227 reset did not complete."); 232 return IXGBE_ERR_PHY; 233 } 234 235 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value); 236 if (status != IXGBE_SUCCESS || 237 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) { 238 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 239 "CS4227 EEPROM did not load successfully."); 240 return IXGBE_ERR_PHY; 241 } 242 243 return IXGBE_SUCCESS; 244 } 245 246 /** 247 * ixgbe_check_cs4227 - Check CS4227 and reset as needed 248 * @hw: pointer to hardware structure 249 **/ 250 static void ixgbe_check_cs4227(struct ixgbe_hw *hw) 251 { 252 s32 status = IXGBE_SUCCESS; 253 u32 swfw_mask = hw->phy.phy_semaphore_mask; 254 u16 value = 0; 255 u8 retry; 256 257 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 258 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 259 if (status != IXGBE_SUCCESS) { 260 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 261 "semaphore failed with %d", status); 262 msec_delay(IXGBE_CS4227_CHECK_DELAY); 263 continue; 264 } 265 266 /* Get status of reset flow. */ 267 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); 268 269 if (status == IXGBE_SUCCESS && 270 value == IXGBE_CS4227_RESET_COMPLETE) 271 goto out; 272 273 if (status != IXGBE_SUCCESS || 274 value != IXGBE_CS4227_RESET_PENDING) 275 break; 276 277 /* Reset is pending. Wait and check again. */ 278 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 279 msec_delay(IXGBE_CS4227_CHECK_DELAY); 280 } 281 282 /* If still pending, assume other instance failed. */ 283 if (retry == IXGBE_CS4227_RETRIES) { 284 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 285 if (status != IXGBE_SUCCESS) { 286 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 287 "semaphore failed with %d", status); 288 return; 289 } 290 } 291 292 /* Reset the CS4227. */ 293 status = ixgbe_reset_cs4227(hw); 294 if (status != IXGBE_SUCCESS) { 295 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 296 "CS4227 reset failed: %d", status); 297 goto out; 298 } 299 300 /* Reset takes so long, temporarily release semaphore in case the 301 * other driver instance is waiting for the reset indication. 302 */ 303 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 304 IXGBE_CS4227_RESET_PENDING); 305 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 306 msec_delay(10); 307 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 308 if (status != IXGBE_SUCCESS) { 309 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 310 "semaphore failed with %d", status); 311 return; 312 } 313 314 /* Record completion for next time. */ 315 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 316 IXGBE_CS4227_RESET_COMPLETE); 317 318 out: 319 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 320 msec_delay(hw->eeprom.semaphore_delay); 321 } 322 323 /** 324 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control 325 * @hw: pointer to hardware structure 326 **/ 327 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) 328 { 329 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 330 331 if (hw->bus.lan_id) { 332 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); 333 esdp |= IXGBE_ESDP_SDP1_DIR; 334 } 335 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); 336 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 337 IXGBE_WRITE_FLUSH(hw); 338 } 339 340 /** 341 * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock 342 * @hw: pointer to hardware structure 343 * @reg_addr: 32 bit address of PHY register to read 344 * @dev_type: always unused 345 * @phy_data: Pointer to read data from PHY register 346 */ 347 static s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr, 348 u32 dev_type, u16 *phy_data) 349 { 350 u32 i, data, command; 351 UNREFERENCED_1PARAMETER(dev_type); 352 353 /* Setup and write the read command */ 354 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) | 355 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 356 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC | 357 IXGBE_MSCA_MDI_COMMAND; 358 359 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 360 361 /* Check every 10 usec to see if the access completed. 362 * The MDI Command bit will clear when the operation is 363 * complete 364 */ 365 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 366 usec_delay(10); 367 368 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 369 if (!(command & IXGBE_MSCA_MDI_COMMAND)) 370 break; 371 } 372 373 if (command & IXGBE_MSCA_MDI_COMMAND) { 374 ERROR_REPORT1(IXGBE_ERROR_POLLING, 375 "PHY read command did not complete.\n"); 376 return IXGBE_ERR_PHY; 377 } 378 379 /* Read operation is complete. Get the data from MSRWD */ 380 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 381 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 382 *phy_data = (u16)data; 383 384 return IXGBE_SUCCESS; 385 } 386 387 /** 388 * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock 389 * @hw: pointer to hardware structure 390 * @reg_addr: 32 bit PHY register to write 391 * @dev_type: always unused 392 * @phy_data: Data to write to the PHY register 393 */ 394 static s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr, 395 u32 dev_type, u16 phy_data) 396 { 397 u32 i, command; 398 UNREFERENCED_1PARAMETER(dev_type); 399 400 /* Put the data in the MDI single read and write data register*/ 401 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 402 403 /* Setup and write the write command */ 404 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) | 405 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 406 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE | 407 IXGBE_MSCA_MDI_COMMAND; 408 409 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 410 411 /* Check every 10 usec to see if the access completed. 412 * The MDI Command bit will clear when the operation is 413 * complete 414 */ 415 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 416 usec_delay(10); 417 418 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 419 if (!(command & IXGBE_MSCA_MDI_COMMAND)) 420 break; 421 } 422 423 if (command & IXGBE_MSCA_MDI_COMMAND) { 424 ERROR_REPORT1(IXGBE_ERROR_POLLING, 425 "PHY write cmd didn't complete\n"); 426 return IXGBE_ERR_PHY; 427 } 428 429 return IXGBE_SUCCESS; 430 } 431 432 /** 433 * ixgbe_identify_phy_x550em - Get PHY type based on device id 434 * @hw: pointer to hardware structure 435 * 436 * Returns error code 437 */ 438 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) 439 { 440 hw->mac.ops.set_lan_id(hw); 441 442 ixgbe_read_mng_if_sel_x550em(hw); 443 444 switch (hw->device_id) { 445 case IXGBE_DEV_ID_X550EM_A_SFP: 446 return ixgbe_identify_module_generic(hw); 447 case IXGBE_DEV_ID_X550EM_X_SFP: 448 /* set up for CS4227 usage */ 449 ixgbe_setup_mux_ctl(hw); 450 ixgbe_check_cs4227(hw); 451 /* Fallthrough */ 452 453 case IXGBE_DEV_ID_X550EM_A_SFP_N: 454 return ixgbe_identify_module_generic(hw); 455 break; 456 case IXGBE_DEV_ID_X550EM_X_KX4: 457 hw->phy.type = ixgbe_phy_x550em_kx4; 458 break; 459 case IXGBE_DEV_ID_X550EM_X_XFI: 460 hw->phy.type = ixgbe_phy_x550em_xfi; 461 break; 462 case IXGBE_DEV_ID_X550EM_X_KR: 463 case IXGBE_DEV_ID_X550EM_A_KR: 464 case IXGBE_DEV_ID_X550EM_A_KR_L: 465 hw->phy.type = ixgbe_phy_x550em_kr; 466 break; 467 case IXGBE_DEV_ID_X550EM_A_10G_T: 468 case IXGBE_DEV_ID_X550EM_X_10G_T: 469 return ixgbe_identify_phy_generic(hw); 470 case IXGBE_DEV_ID_X550EM_X_1G_T: 471 hw->phy.type = ixgbe_phy_ext_1g_t; 472 hw->phy.ops.read_reg = NULL; 473 hw->phy.ops.write_reg = NULL; 474 break; 475 case IXGBE_DEV_ID_X550EM_A_1G_T: 476 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 477 hw->phy.type = ixgbe_phy_fw; 478 hw->phy.ops.read_reg = NULL; 479 hw->phy.ops.write_reg = NULL; 480 if (hw->bus.lan_id) 481 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; 482 else 483 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; 484 break; 485 default: 486 break; 487 } 488 return IXGBE_SUCCESS; 489 } 490 491 /** 492 * ixgbe_fw_phy_activity - Perform an activity on a PHY 493 * @hw: pointer to hardware structure 494 * @activity: activity to perform 495 * @data: Pointer to 4 32-bit words of data 496 */ 497 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity, 498 u32 (*data)[FW_PHY_ACT_DATA_COUNT]) 499 { 500 union { 501 struct ixgbe_hic_phy_activity_req cmd; 502 struct ixgbe_hic_phy_activity_resp rsp; 503 } hic; 504 u16 retries = FW_PHY_ACT_RETRIES; 505 s32 rc; 506 u16 i; 507 508 do { 509 memset(&hic, 0, sizeof(hic)); 510 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD; 511 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN; 512 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 513 hic.cmd.port_number = hw->bus.lan_id; 514 hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity); 515 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i) 516 hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]); 517 518 rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd, 519 sizeof(hic.cmd), 520 IXGBE_HI_COMMAND_TIMEOUT, 521 TRUE); 522 if (rc != IXGBE_SUCCESS) 523 return rc; 524 if (hic.rsp.hdr.cmd_or_resp.ret_status == 525 FW_CEM_RESP_STATUS_SUCCESS) { 526 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i) 527 (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]); 528 return IXGBE_SUCCESS; 529 } 530 usec_delay(20); 531 --retries; 532 } while (retries > 0); 533 534 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 535 } 536 537 static const struct { 538 u16 fw_speed; 539 ixgbe_link_speed phy_speed; 540 } ixgbe_fw_map[] = { 541 { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL }, 542 { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL }, 543 { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL }, 544 { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL }, 545 { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL }, 546 { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL }, 547 }; 548 549 /** 550 * ixgbe_get_phy_id_fw - Get the phy ID via firmware command 551 * @hw: pointer to hardware structure 552 * 553 * Returns error code 554 */ 555 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw) 556 { 557 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 558 u16 phy_speeds; 559 u16 phy_id_lo; 560 s32 rc; 561 u16 i; 562 563 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info); 564 if (rc) 565 return rc; 566 567 hw->phy.speeds_supported = 0; 568 phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK; 569 for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) { 570 if (phy_speeds & ixgbe_fw_map[i].fw_speed) 571 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed; 572 } 573 if (!hw->phy.autoneg_advertised) 574 hw->phy.autoneg_advertised = hw->phy.speeds_supported; 575 576 hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK; 577 phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK; 578 hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK; 579 hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK; 580 if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK) 581 return IXGBE_ERR_PHY_ADDR_INVALID; 582 return IXGBE_SUCCESS; 583 } 584 585 /** 586 * ixgbe_identify_phy_fw - Get PHY type based on firmware command 587 * @hw: pointer to hardware structure 588 * 589 * Returns error code 590 */ 591 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw) 592 { 593 if (hw->bus.lan_id) 594 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 595 else 596 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 597 598 hw->phy.type = ixgbe_phy_fw; 599 hw->phy.ops.read_reg = NULL; 600 hw->phy.ops.write_reg = NULL; 601 return ixgbe_get_phy_id_fw(hw); 602 } 603 604 /** 605 * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY 606 * @hw: pointer to hardware structure 607 * 608 * Returns error code 609 */ 610 s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw) 611 { 612 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 613 614 setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF; 615 return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup); 616 } 617 618 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 619 u32 device_type, u16 *phy_data) 620 { 621 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data); 622 return IXGBE_NOT_IMPLEMENTED; 623 } 624 625 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 626 u32 device_type, u16 phy_data) 627 { 628 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data); 629 return IXGBE_NOT_IMPLEMENTED; 630 } 631 632 /** 633 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 634 * @hw: pointer to the hardware structure 635 * @addr: I2C bus address to read from 636 * @reg: I2C device register to read from 637 * @val: pointer to location to receive read value 638 * 639 * Returns an error code on error. 640 **/ 641 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 642 u16 reg, u16 *val) 643 { 644 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, TRUE); 645 } 646 647 /** 648 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation 649 * @hw: pointer to the hardware structure 650 * @addr: I2C bus address to read from 651 * @reg: I2C device register to read from 652 * @val: pointer to location to receive read value 653 * 654 * Returns an error code on error. 655 **/ 656 static s32 657 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, 658 u16 reg, u16 *val) 659 { 660 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, FALSE); 661 } 662 663 /** 664 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 665 * @hw: pointer to the hardware structure 666 * @addr: I2C bus address to write to 667 * @reg: I2C device register to write to 668 * @val: value to write 669 * 670 * Returns an error code on error. 671 **/ 672 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 673 u8 addr, u16 reg, u16 val) 674 { 675 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, TRUE); 676 } 677 678 /** 679 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation 680 * @hw: pointer to the hardware structure 681 * @addr: I2C bus address to write to 682 * @reg: I2C device register to write to 683 * @val: value to write 684 * 685 * Returns an error code on error. 686 **/ 687 static s32 688 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, 689 u8 addr, u16 reg, u16 val) 690 { 691 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, FALSE); 692 } 693 694 /** 695 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type 696 * @hw: pointer to hardware structure 697 * 698 * Initialize the function pointers and for MAC type X550EM. 699 * Does not touch the hardware. 700 **/ 701 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw) 702 { 703 struct ixgbe_mac_info *mac = &hw->mac; 704 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 705 struct ixgbe_phy_info *phy = &hw->phy; 706 s32 ret_val; 707 708 DEBUGFUNC("ixgbe_init_ops_X550EM"); 709 710 /* Similar to X550 so start there. */ 711 ret_val = ixgbe_init_ops_X550(hw); 712 713 /* Since this function eventually calls 714 * ixgbe_init_ops_540 by design, we are setting 715 * the pointers to NULL explicitly here to overwrite 716 * the values being set in the x540 function. 717 */ 718 719 /* Bypass not supported in x550EM */ 720 mac->ops.bypass_rw = NULL; 721 mac->ops.bypass_valid_rd = NULL; 722 mac->ops.bypass_set = NULL; 723 mac->ops.bypass_rd_eep = NULL; 724 725 /* FCOE not supported in x550EM */ 726 mac->ops.get_san_mac_addr = NULL; 727 mac->ops.set_san_mac_addr = NULL; 728 mac->ops.get_wwn_prefix = NULL; 729 mac->ops.get_fcoe_boot_status = NULL; 730 731 /* IPsec not supported in x550EM */ 732 mac->ops.disable_sec_rx_path = NULL; 733 mac->ops.enable_sec_rx_path = NULL; 734 735 /* AUTOC register is not present in x550EM. */ 736 mac->ops.prot_autoc_read = NULL; 737 mac->ops.prot_autoc_write = NULL; 738 739 /* X550EM bus type is internal*/ 740 hw->bus.type = ixgbe_bus_type_internal; 741 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em; 742 743 744 mac->ops.get_media_type = ixgbe_get_media_type_X550em; 745 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em; 746 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em; 747 mac->ops.reset_hw = ixgbe_reset_hw_X550em; 748 mac->ops.get_supported_physical_layer = 749 ixgbe_get_supported_physical_layer_X550em; 750 751 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) 752 mac->ops.setup_fc = ixgbe_setup_fc_generic; 753 else 754 mac->ops.setup_fc = ixgbe_setup_fc_X550em; 755 756 /* PHY */ 757 phy->ops.init = ixgbe_init_phy_ops_X550em; 758 switch (hw->device_id) { 759 case IXGBE_DEV_ID_X550EM_A_1G_T: 760 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 761 mac->ops.setup_fc = NULL; 762 phy->ops.identify = ixgbe_identify_phy_fw; 763 phy->ops.set_phy_power = NULL; 764 phy->ops.get_firmware_version = NULL; 765 break; 766 case IXGBE_DEV_ID_X550EM_X_1G_T: 767 mac->ops.setup_fc = NULL; 768 phy->ops.identify = ixgbe_identify_phy_x550em; 769 phy->ops.set_phy_power = NULL; 770 break; 771 default: 772 phy->ops.identify = ixgbe_identify_phy_x550em; 773 } 774 775 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 776 phy->ops.set_phy_power = NULL; 777 778 779 /* EEPROM */ 780 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540; 781 eeprom->ops.read = ixgbe_read_ee_hostif_X550; 782 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550; 783 eeprom->ops.write = ixgbe_write_ee_hostif_X550; 784 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550; 785 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550; 786 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550; 787 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550; 788 789 return ret_val; 790 } 791 792 #define IXGBE_DENVERTON_WA 1 793 794 /** 795 * ixgbe_setup_fw_link - Setup firmware-controlled PHYs 796 * @hw: pointer to hardware structure 797 */ 798 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw) 799 { 800 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 801 s32 rc; 802 #ifdef IXGBE_DENVERTON_WA 803 s32 ret_val; 804 u16 phydata; 805 #endif 806 u16 i; 807 808 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 809 return 0; 810 811 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 812 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 813 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 814 return IXGBE_ERR_INVALID_LINK_SETTINGS; 815 } 816 817 switch (hw->fc.requested_mode) { 818 case ixgbe_fc_full: 819 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX << 820 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 821 break; 822 case ixgbe_fc_rx_pause: 823 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX << 824 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 825 break; 826 case ixgbe_fc_tx_pause: 827 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX << 828 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 829 break; 830 default: 831 break; 832 } 833 834 for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) { 835 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed) 836 setup[0] |= ixgbe_fw_map[i].fw_speed; 837 } 838 setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN; 839 840 if (hw->phy.eee_speeds_advertised) 841 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE; 842 843 #ifdef IXGBE_DENVERTON_WA 844 /* Don't use auto-nego for 10/100Mbps */ 845 if ((hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_100_FULL) 846 || (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_10_FULL)) { 847 setup[0] &= ~FW_PHY_ACT_SETUP_LINK_AN; 848 setup[0] &= ~FW_PHY_ACT_SETUP_LINK_EEE; 849 setup[0] &= ~(FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX 850 << FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT); 851 } 852 #endif 853 854 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup); 855 if (rc) 856 return rc; 857 858 #ifdef IXGBE_DENVERTON_WA 859 ret_val = ixgbe_read_phy_reg_x550a(hw, MII_BMCR, 0, &phydata); 860 if (ret_val != 0) 861 goto out; 862 863 /* 864 * Broken firmware sets BMCR register incorrectly if 865 * FW_PHY_ACT_SETUP_LINK_AN isn't set. 866 * a) FDX may not be set. 867 * b) BMCR_SPEED1 (bit 6) is always cleard. 868 * + -------+------+-----------+-----+--------------------------+ 869 * |request | BMCR | BMCR spd | BMCR | | 870 * | | (HEX)| (in bits)| FDX | | 871 * +--------+------+----------+------+--------------------------+ 872 * | 10M | 0000 | 10M(00) | 0 | | 873 * | 10M | 2000 | 100M(01) | 0 |(I've never observed this)| 874 * | 10M | 2100 | 100M(01) | 1 | | 875 * | 100M | 0000 | 10M(00) | 0 | | 876 * | 100M | 0100 | 10M(00) | 1 | | 877 * +--------------------------+------+--------------------------+ 878 */ 879 if (((hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_100_FULL) 880 && (((phydata & BMCR_FDX) == 0) || (BMCR_SPEED(phydata) == 0))) 881 || ((hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_10_FULL) 882 && (((phydata & BMCR_FDX) == 0) 883 || (BMCR_SPEED(phydata) != BMCR_S10)))) { 884 phydata = BMCR_FDX; 885 switch (hw->phy.autoneg_advertised) { 886 case IXGBE_LINK_SPEED_10_FULL: 887 phydata |= BMCR_S10; 888 break; 889 case IXGBE_LINK_SPEED_100_FULL: 890 phydata |= BMCR_S100; 891 break; 892 case IXGBE_LINK_SPEED_1GB_FULL: 893 panic("%s: 1GB_FULL is set", __func__); 894 break; 895 default: 896 break; 897 } 898 ret_val = ixgbe_write_phy_reg_x550a(hw, MII_BMCR, 0, phydata); 899 if (ret_val != 0) 900 return ret_val; 901 } 902 out: 903 #endif 904 if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN) 905 return IXGBE_ERR_OVERTEMP; 906 return IXGBE_SUCCESS; 907 } 908 909 /** 910 * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs 911 * @hw: pointer to hardware structure 912 * 913 * Called at init time to set up flow control. 914 */ 915 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw) 916 { 917 if (hw->fc.requested_mode == ixgbe_fc_default) 918 hw->fc.requested_mode = ixgbe_fc_full; 919 920 return ixgbe_setup_fw_link(hw); 921 } 922 923 /** 924 * ixgbe_setup_eee_fw - Enable/disable EEE support 925 * @hw: pointer to the HW structure 926 * @enable_eee: boolean flag to enable EEE 927 * 928 * Enable/disable EEE based on enable_eee flag. 929 * This function controls EEE for firmware-based PHY implementations. 930 */ 931 static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee) 932 { 933 if (!!hw->phy.eee_speeds_advertised == enable_eee) 934 return IXGBE_SUCCESS; 935 if (enable_eee) 936 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported; 937 else 938 hw->phy.eee_speeds_advertised = 0; 939 return hw->phy.ops.setup_link(hw); 940 } 941 942 /** 943 * ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type 944 * @hw: pointer to hardware structure 945 * 946 * Initialize the function pointers and for MAC type X550EM_a. 947 * Does not touch the hardware. 948 **/ 949 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw) 950 { 951 struct ixgbe_mac_info *mac = &hw->mac; 952 s32 ret_val; 953 954 DEBUGFUNC("ixgbe_init_ops_X550EM_a"); 955 956 /* Start with generic X550EM init */ 957 ret_val = ixgbe_init_ops_X550EM(hw); 958 959 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII || 960 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) { 961 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550; 962 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550; 963 } else { 964 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a; 965 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a; 966 } 967 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a; 968 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a; 969 970 switch (mac->ops.get_media_type(hw)) { 971 case ixgbe_media_type_fiber: 972 mac->ops.setup_fc = NULL; 973 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a; 974 break; 975 case ixgbe_media_type_backplane: 976 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a; 977 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a; 978 break; 979 default: 980 break; 981 } 982 983 switch (hw->device_id) { 984 case IXGBE_DEV_ID_X550EM_A_1G_T: 985 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 986 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a; 987 mac->ops.setup_fc = ixgbe_fc_autoneg_fw; 988 mac->ops.setup_eee = ixgbe_setup_eee_fw; 989 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL | 990 IXGBE_LINK_SPEED_1GB_FULL; 991 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported; 992 break; 993 default: 994 break; 995 } 996 997 return ret_val; 998 } 999 1000 /** 1001 * ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type 1002 * @hw: pointer to hardware structure 1003 * 1004 * Initialize the function pointers and for MAC type X550EM_x. 1005 * Does not touch the hardware. 1006 **/ 1007 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw) 1008 { 1009 struct ixgbe_mac_info *mac = &hw->mac; 1010 struct ixgbe_link_info *link = &hw->link; 1011 s32 ret_val; 1012 1013 DEBUGFUNC("ixgbe_init_ops_X550EM_x"); 1014 1015 /* Start with generic X550EM init */ 1016 ret_val = ixgbe_init_ops_X550EM(hw); 1017 1018 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550; 1019 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550; 1020 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em; 1021 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em; 1022 link->ops.read_link = ixgbe_read_i2c_combined_generic; 1023 link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked; 1024 link->ops.write_link = ixgbe_write_i2c_combined_generic; 1025 link->ops.write_link_unlocked = 1026 ixgbe_write_i2c_combined_generic_unlocked; 1027 link->addr = IXGBE_CS4227; 1028 1029 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) { 1030 mac->ops.setup_fc = NULL; 1031 mac->ops.setup_eee = NULL; 1032 mac->ops.init_led_link_act = NULL; 1033 } 1034 1035 return ret_val; 1036 } 1037 1038 /** 1039 * ixgbe_dmac_config_X550 1040 * @hw: pointer to hardware structure 1041 * 1042 * Configure DMA coalescing. If enabling dmac, dmac is activated. 1043 * When disabling dmac, dmac enable dmac bit is cleared. 1044 **/ 1045 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw) 1046 { 1047 u32 reg, high_pri_tc; 1048 1049 DEBUGFUNC("ixgbe_dmac_config_X550"); 1050 1051 /* Disable DMA coalescing before configuring */ 1052 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 1053 reg &= ~IXGBE_DMACR_DMAC_EN; 1054 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 1055 1056 /* Disable DMA Coalescing if the watchdog timer is 0 */ 1057 if (!hw->mac.dmac_config.watchdog_timer) 1058 goto out; 1059 1060 ixgbe_dmac_config_tcs_X550(hw); 1061 1062 /* Configure DMA Coalescing Control Register */ 1063 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 1064 1065 /* Set the watchdog timer in units of 40.96 usec */ 1066 reg &= ~IXGBE_DMACR_DMACWT_MASK; 1067 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096; 1068 1069 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK; 1070 /* If fcoe is enabled, set high priority traffic class */ 1071 if (hw->mac.dmac_config.fcoe_en) { 1072 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc; 1073 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) & 1074 IXGBE_DMACR_HIGH_PRI_TC_MASK); 1075 } 1076 reg |= IXGBE_DMACR_EN_MNG_IND; 1077 1078 /* Enable DMA coalescing after configuration */ 1079 reg |= IXGBE_DMACR_DMAC_EN; 1080 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 1081 1082 out: 1083 return IXGBE_SUCCESS; 1084 } 1085 1086 /** 1087 * ixgbe_dmac_config_tcs_X550 1088 * @hw: pointer to hardware structure 1089 * 1090 * Configure DMA coalescing threshold per TC. The dmac enable bit must 1091 * be cleared before configuring. 1092 **/ 1093 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw) 1094 { 1095 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb; 1096 1097 DEBUGFUNC("ixgbe_dmac_config_tcs_X550"); 1098 1099 /* Configure DMA coalescing enabled */ 1100 switch (hw->mac.dmac_config.link_speed) { 1101 case IXGBE_LINK_SPEED_10_FULL: 1102 case IXGBE_LINK_SPEED_100_FULL: 1103 pb_headroom = IXGBE_DMACRXT_100M; 1104 break; 1105 case IXGBE_LINK_SPEED_1GB_FULL: 1106 pb_headroom = IXGBE_DMACRXT_1G; 1107 break; 1108 default: 1109 pb_headroom = IXGBE_DMACRXT_10G; 1110 break; 1111 } 1112 1113 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >> 1114 IXGBE_MHADD_MFS_SHIFT) / 1024); 1115 1116 /* Set the per Rx packet buffer receive threshold */ 1117 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) { 1118 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc)); 1119 reg &= ~IXGBE_DMCTH_DMACRXT_MASK; 1120 1121 if (tc < hw->mac.dmac_config.num_tcs) { 1122 /* Get Rx PB size */ 1123 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc)); 1124 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >> 1125 IXGBE_RXPBSIZE_SHIFT; 1126 1127 /* Calculate receive buffer threshold in kilobytes */ 1128 if (rx_pb_size > pb_headroom) 1129 rx_pb_size = rx_pb_size - pb_headroom; 1130 else 1131 rx_pb_size = 0; 1132 1133 /* Minimum of MFS shall be set for DMCTH */ 1134 reg |= (rx_pb_size > maxframe_size_kb) ? 1135 rx_pb_size : maxframe_size_kb; 1136 } 1137 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg); 1138 } 1139 return IXGBE_SUCCESS; 1140 } 1141 1142 /** 1143 * ixgbe_dmac_update_tcs_X550 1144 * @hw: pointer to hardware structure 1145 * 1146 * Disables dmac, updates per TC settings, and then enables dmac. 1147 **/ 1148 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw) 1149 { 1150 u32 reg; 1151 1152 DEBUGFUNC("ixgbe_dmac_update_tcs_X550"); 1153 1154 /* Disable DMA coalescing before configuring */ 1155 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 1156 reg &= ~IXGBE_DMACR_DMAC_EN; 1157 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 1158 1159 ixgbe_dmac_config_tcs_X550(hw); 1160 1161 /* Enable DMA coalescing after configuration */ 1162 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 1163 reg |= IXGBE_DMACR_DMAC_EN; 1164 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 1165 1166 return IXGBE_SUCCESS; 1167 } 1168 1169 /** 1170 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params 1171 * @hw: pointer to hardware structure 1172 * 1173 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 1174 * ixgbe_hw struct in order to set up EEPROM access. 1175 **/ 1176 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) 1177 { 1178 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1179 u32 eec; 1180 u16 eeprom_size; 1181 1182 DEBUGFUNC("ixgbe_init_eeprom_params_X550"); 1183 1184 if (eeprom->type == ixgbe_eeprom_uninitialized) { 1185 eeprom->semaphore_delay = 10; 1186 eeprom->type = ixgbe_flash; 1187 1188 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1189 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 1190 IXGBE_EEC_SIZE_SHIFT); 1191 eeprom->word_size = 1 << (eeprom_size + 1192 IXGBE_EEPROM_WORD_SIZE_SHIFT); 1193 1194 DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 1195 eeprom->type, eeprom->word_size); 1196 } 1197 1198 return IXGBE_SUCCESS; 1199 } 1200 1201 /** 1202 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning 1203 * @hw: pointer to hardware structure 1204 * @enable: enable or disable source address pruning 1205 * @pool: Rx pool to set source address pruning for 1206 **/ 1207 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable, 1208 unsigned int pool) 1209 { 1210 u64 pfflp; 1211 1212 /* max rx pool is 63 */ 1213 if (pool > 63) 1214 return; 1215 1216 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL); 1217 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32; 1218 1219 if (enable) 1220 pfflp |= (1ULL << pool); 1221 else 1222 pfflp &= ~(1ULL << pool); 1223 1224 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); 1225 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); 1226 } 1227 1228 /** 1229 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing 1230 * @hw: pointer to hardware structure 1231 * @enable: enable or disable switch for Ethertype anti-spoofing 1232 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1233 * 1234 **/ 1235 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, 1236 bool enable, int vf) 1237 { 1238 int vf_target_reg = vf >> 3; 1239 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT; 1240 u32 pfvfspoof; 1241 1242 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550"); 1243 1244 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 1245 if (enable) 1246 pfvfspoof |= (1 << vf_target_shift); 1247 else 1248 pfvfspoof &= ~(1 << vf_target_shift); 1249 1250 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 1251 } 1252 1253 /** 1254 * ixgbe_iosf_wait - Wait for IOSF command completion 1255 * @hw: pointer to hardware structure 1256 * @ctrl: pointer to location to receive final IOSF control value 1257 * 1258 * Returns failing status on timeout 1259 * 1260 * Note: ctrl can be NULL if the IOSF control register value is not needed 1261 **/ 1262 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) 1263 { 1264 u32 i, command = 0; 1265 1266 /* Check every 10 usec to see if the address cycle completed. 1267 * The SB IOSF BUSY bit will clear when the operation is 1268 * complete 1269 */ 1270 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 1271 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); 1272 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0) 1273 break; 1274 usec_delay(10); 1275 } 1276 if (ctrl) 1277 *ctrl = command; 1278 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { 1279 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n"); 1280 return IXGBE_ERR_PHY; 1281 } 1282 1283 return IXGBE_SUCCESS; 1284 } 1285 1286 /** 1287 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register 1288 * of the IOSF device 1289 * @hw: pointer to hardware structure 1290 * @reg_addr: 32 bit PHY register to write 1291 * @device_type: 3 bit device type 1292 * @data: Data to write to the register 1293 **/ 1294 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 1295 u32 device_type, u32 data) 1296 { 1297 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 1298 u32 command, error __unused; 1299 s32 ret; 1300 1301 ret = ixgbe_acquire_swfw_semaphore(hw, gssr); 1302 if (ret != IXGBE_SUCCESS) 1303 return ret; 1304 1305 ret = ixgbe_iosf_wait(hw, NULL); 1306 if (ret != IXGBE_SUCCESS) 1307 goto out; 1308 1309 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 1310 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 1311 1312 /* Write IOSF control register */ 1313 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 1314 1315 /* Write IOSF data register */ 1316 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); 1317 1318 ret = ixgbe_iosf_wait(hw, &command); 1319 1320 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 1321 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 1322 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 1323 ERROR_REPORT2(IXGBE_ERROR_POLLING, 1324 "Failed to write, error %x\n", error); 1325 ret = IXGBE_ERR_PHY; 1326 } 1327 1328 out: 1329 ixgbe_release_swfw_semaphore(hw, gssr); 1330 return ret; 1331 } 1332 1333 /** 1334 * ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device 1335 * @hw: pointer to hardware structure 1336 * @reg_addr: 32 bit PHY register to write 1337 * @device_type: 3 bit device type 1338 * @data: Pointer to read data from the register 1339 **/ 1340 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 1341 u32 device_type, u32 *data) 1342 { 1343 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 1344 u32 command, error __unused; 1345 s32 ret; 1346 1347 ret = ixgbe_acquire_swfw_semaphore(hw, gssr); 1348 if (ret != IXGBE_SUCCESS) 1349 return ret; 1350 1351 ret = ixgbe_iosf_wait(hw, NULL); 1352 if (ret != IXGBE_SUCCESS) 1353 goto out; 1354 1355 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 1356 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 1357 1358 /* Write IOSF control register */ 1359 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 1360 1361 ret = ixgbe_iosf_wait(hw, &command); 1362 1363 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 1364 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 1365 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 1366 ERROR_REPORT2(IXGBE_ERROR_POLLING, 1367 "Failed to read, error %x\n", error); 1368 ret = IXGBE_ERR_PHY; 1369 } 1370 1371 if (ret == IXGBE_SUCCESS) 1372 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); 1373 1374 out: 1375 ixgbe_release_swfw_semaphore(hw, gssr); 1376 return ret; 1377 } 1378 1379 /** 1380 * ixgbe_get_phy_token - Get the token for shared phy access 1381 * @hw: Pointer to hardware structure 1382 */ 1383 1384 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw) 1385 { 1386 struct ixgbe_hic_phy_token_req token_cmd; 1387 s32 status; 1388 1389 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 1390 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 1391 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 1392 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1393 token_cmd.port_number = hw->bus.lan_id; 1394 token_cmd.command_type = FW_PHY_TOKEN_REQ; 1395 token_cmd.pad = 0; 1396 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd, 1397 sizeof(token_cmd), 1398 IXGBE_HI_COMMAND_TIMEOUT, 1399 TRUE); 1400 if (status) { 1401 DEBUGOUT1("Issuing host interface command failed with Status = %d\n", 1402 status); 1403 return status; 1404 } 1405 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 1406 return IXGBE_SUCCESS; 1407 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) { 1408 DEBUGOUT1("Host interface command returned 0x%08x , returning IXGBE_ERR_FW_RESP_INVALID\n", 1409 token_cmd.hdr.cmd_or_resp.ret_status); 1410 return IXGBE_ERR_FW_RESP_INVALID; 1411 } 1412 1413 DEBUGOUT("Returning IXGBE_ERR_TOKEN_RETRY\n"); 1414 return IXGBE_ERR_TOKEN_RETRY; 1415 } 1416 1417 /** 1418 * ixgbe_put_phy_token - Put the token for shared phy access 1419 * @hw: Pointer to hardware structure 1420 */ 1421 1422 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw) 1423 { 1424 struct ixgbe_hic_phy_token_req token_cmd; 1425 s32 status; 1426 1427 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 1428 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 1429 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 1430 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1431 token_cmd.port_number = hw->bus.lan_id; 1432 token_cmd.command_type = FW_PHY_TOKEN_REL; 1433 token_cmd.pad = 0; 1434 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd, 1435 sizeof(token_cmd), 1436 IXGBE_HI_COMMAND_TIMEOUT, 1437 TRUE); 1438 if (status) 1439 return status; 1440 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 1441 return IXGBE_SUCCESS; 1442 1443 DEBUGOUT("Put PHY Token host interface command failed"); 1444 return IXGBE_ERR_FW_RESP_INVALID; 1445 } 1446 1447 /** 1448 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register 1449 * of the IOSF device 1450 * @hw: pointer to hardware structure 1451 * @reg_addr: 32 bit PHY register to write 1452 * @device_type: 3 bit device type 1453 * @data: Data to write to the register 1454 **/ 1455 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 1456 u32 device_type, u32 data) 1457 { 1458 struct ixgbe_hic_internal_phy_req write_cmd; 1459 s32 status; 1460 UNREFERENCED_1PARAMETER(device_type); 1461 1462 memset(&write_cmd, 0, sizeof(write_cmd)); 1463 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 1464 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 1465 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1466 write_cmd.port_number = hw->bus.lan_id; 1467 write_cmd.command_type = FW_INT_PHY_REQ_WRITE; 1468 write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr); 1469 write_cmd.write_data = IXGBE_CPU_TO_BE32(data); 1470 1471 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd, 1472 sizeof(write_cmd), 1473 IXGBE_HI_COMMAND_TIMEOUT, FALSE); 1474 1475 return status; 1476 } 1477 1478 /** 1479 * ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device 1480 * @hw: pointer to hardware structure 1481 * @reg_addr: 32 bit PHY register to write 1482 * @device_type: 3 bit device type 1483 * @data: Pointer to read data from the register 1484 **/ 1485 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 1486 u32 device_type, u32 *data) 1487 { 1488 union { 1489 struct ixgbe_hic_internal_phy_req cmd; 1490 struct ixgbe_hic_internal_phy_resp rsp; 1491 } hic; 1492 s32 status; 1493 UNREFERENCED_1PARAMETER(device_type); 1494 1495 memset(&hic, 0, sizeof(hic)); 1496 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 1497 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 1498 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1499 hic.cmd.port_number = hw->bus.lan_id; 1500 hic.cmd.command_type = FW_INT_PHY_REQ_READ; 1501 hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr); 1502 1503 status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd, 1504 sizeof(hic.cmd), 1505 IXGBE_HI_COMMAND_TIMEOUT, TRUE); 1506 1507 /* Extract the register value from the response. */ 1508 *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data); 1509 1510 return status; 1511 } 1512 1513 /** 1514 * ixgbe_disable_mdd_X550 1515 * @hw: pointer to hardware structure 1516 * 1517 * Disable malicious driver detection 1518 **/ 1519 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw) 1520 { 1521 u32 reg; 1522 1523 DEBUGFUNC("ixgbe_disable_mdd_X550"); 1524 1525 /* Disable MDD for TX DMA and interrupt */ 1526 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1527 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN); 1528 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1529 1530 /* Disable MDD for RX and interrupt */ 1531 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 1532 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN); 1533 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 1534 } 1535 1536 /** 1537 * ixgbe_enable_mdd_X550 1538 * @hw: pointer to hardware structure 1539 * 1540 * Enable malicious driver detection 1541 **/ 1542 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw) 1543 { 1544 u32 reg; 1545 1546 DEBUGFUNC("ixgbe_enable_mdd_X550"); 1547 1548 /* Enable MDD for TX DMA and interrupt */ 1549 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1550 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN); 1551 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1552 1553 /* Enable MDD for RX and interrupt */ 1554 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 1555 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN); 1556 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 1557 } 1558 1559 /** 1560 * ixgbe_restore_mdd_vf_X550 1561 * @hw: pointer to hardware structure 1562 * @vf: vf index 1563 * 1564 * Restore VF that was disabled during malicious driver detection event 1565 **/ 1566 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf) 1567 { 1568 u32 idx, reg, num_qs, start_q, bitmask; 1569 1570 DEBUGFUNC("ixgbe_restore_mdd_vf_X550"); 1571 1572 /* Map VF to queues */ 1573 reg = IXGBE_READ_REG(hw, IXGBE_MRQC); 1574 switch (reg & IXGBE_MRQC_MRQE_MASK) { 1575 case IXGBE_MRQC_VMDQRT8TCEN: 1576 num_qs = 8; /* 16 VFs / pools */ 1577 bitmask = 0x000000FF; 1578 break; 1579 case IXGBE_MRQC_VMDQRSS32EN: 1580 case IXGBE_MRQC_VMDQRT4TCEN: 1581 num_qs = 4; /* 32 VFs / pools */ 1582 bitmask = 0x0000000F; 1583 break; 1584 default: /* 64 VFs / pools */ 1585 num_qs = 2; 1586 bitmask = 0x00000003; 1587 break; 1588 } 1589 start_q = vf * num_qs; 1590 1591 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */ 1592 idx = start_q / 32; 1593 reg = 0; 1594 reg |= (bitmask << (start_q % 32)); 1595 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg); 1596 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg); 1597 } 1598 1599 /** 1600 * ixgbe_mdd_event_X550 1601 * @hw: pointer to hardware structure 1602 * @vf_bitmap: vf bitmap of malicious vfs 1603 * 1604 * Handle malicious driver detection event. 1605 **/ 1606 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap) 1607 { 1608 u32 wqbr; 1609 u32 i, j, reg, q, shift, vf, idx; 1610 1611 DEBUGFUNC("ixgbe_mdd_event_X550"); 1612 1613 /* figure out pool size for mapping to vf's */ 1614 reg = IXGBE_READ_REG(hw, IXGBE_MRQC); 1615 switch (reg & IXGBE_MRQC_MRQE_MASK) { 1616 case IXGBE_MRQC_VMDQRT8TCEN: 1617 shift = 3; /* 16 VFs / pools */ 1618 break; 1619 case IXGBE_MRQC_VMDQRSS32EN: 1620 case IXGBE_MRQC_VMDQRT4TCEN: 1621 shift = 2; /* 32 VFs / pools */ 1622 break; 1623 default: 1624 shift = 1; /* 64 VFs / pools */ 1625 break; 1626 } 1627 1628 /* Read WQBR_TX and WQBR_RX and check for malicious queues */ 1629 for (i = 0; i < 4; i++) { 1630 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i)); 1631 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i)); 1632 1633 if (!wqbr) 1634 continue; 1635 1636 /* Get malicious queue */ 1637 for (j = 0; j < 32 && wqbr; j++) { 1638 1639 if (!(wqbr & (1 << j))) 1640 continue; 1641 1642 /* Get queue from bitmask */ 1643 q = j + (i * 32); 1644 1645 /* Map queue to vf */ 1646 vf = (q >> shift); 1647 1648 /* Set vf bit in vf_bitmap */ 1649 idx = vf / 32; 1650 vf_bitmap[idx] |= (1 << (vf % 32)); 1651 wqbr &= ~(1 << j); 1652 } 1653 } 1654 } 1655 1656 /** 1657 * ixgbe_get_media_type_X550em - Get media type 1658 * @hw: pointer to hardware structure 1659 * 1660 * Returns the media type (fiber, copper, backplane) 1661 */ 1662 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) 1663 { 1664 enum ixgbe_media_type media_type; 1665 1666 DEBUGFUNC("ixgbe_get_media_type_X550em"); 1667 1668 /* Detect if there is a copper PHY attached. */ 1669 switch (hw->device_id) { 1670 case IXGBE_DEV_ID_X550EM_X_KR: 1671 case IXGBE_DEV_ID_X550EM_X_KX4: 1672 case IXGBE_DEV_ID_X550EM_X_XFI: 1673 case IXGBE_DEV_ID_X550EM_A_KR: 1674 case IXGBE_DEV_ID_X550EM_A_KR_L: 1675 media_type = ixgbe_media_type_backplane; 1676 break; 1677 case IXGBE_DEV_ID_X550EM_X_SFP: 1678 case IXGBE_DEV_ID_X550EM_A_SFP: 1679 case IXGBE_DEV_ID_X550EM_A_SFP_N: 1680 case IXGBE_DEV_ID_X550EM_A_QSFP: 1681 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 1682 media_type = ixgbe_media_type_fiber; 1683 break; 1684 case IXGBE_DEV_ID_X550EM_X_1G_T: 1685 case IXGBE_DEV_ID_X550EM_X_10G_T: 1686 case IXGBE_DEV_ID_X550EM_A_10G_T: 1687 media_type = ixgbe_media_type_copper; 1688 break; 1689 case IXGBE_DEV_ID_X550EM_A_SGMII: 1690 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 1691 media_type = ixgbe_media_type_backplane; 1692 hw->phy.type = ixgbe_phy_sgmii; 1693 break; 1694 case IXGBE_DEV_ID_X550EM_A_1G_T: 1695 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 1696 media_type = ixgbe_media_type_copper; 1697 break; 1698 default: 1699 media_type = ixgbe_media_type_unknown; 1700 break; 1701 } 1702 return media_type; 1703 } 1704 1705 /** 1706 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported 1707 * @hw: pointer to hardware structure 1708 * @linear: TRUE if SFP module is linear 1709 */ 1710 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear) 1711 { 1712 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em"); 1713 1714 switch (hw->phy.sfp_type) { 1715 case ixgbe_sfp_type_not_present: 1716 return IXGBE_ERR_SFP_NOT_PRESENT; 1717 case ixgbe_sfp_type_da_cu_core0: 1718 case ixgbe_sfp_type_da_cu_core1: 1719 *linear = TRUE; 1720 break; 1721 case ixgbe_sfp_type_srlr_core0: 1722 case ixgbe_sfp_type_srlr_core1: 1723 case ixgbe_sfp_type_da_act_lmt_core0: 1724 case ixgbe_sfp_type_da_act_lmt_core1: 1725 case ixgbe_sfp_type_1g_sx_core0: 1726 case ixgbe_sfp_type_1g_sx_core1: 1727 case ixgbe_sfp_type_1g_lx_core0: 1728 case ixgbe_sfp_type_1g_lx_core1: 1729 *linear = FALSE; 1730 break; 1731 case ixgbe_sfp_type_unknown: 1732 case ixgbe_sfp_type_1g_cu_core0: 1733 case ixgbe_sfp_type_1g_cu_core1: 1734 default: 1735 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1736 } 1737 1738 return IXGBE_SUCCESS; 1739 } 1740 1741 /** 1742 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules 1743 * @hw: pointer to hardware structure 1744 * 1745 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1746 **/ 1747 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw) 1748 { 1749 s32 status; 1750 bool linear; 1751 1752 DEBUGFUNC("ixgbe_identify_sfp_module_X550em"); 1753 1754 status = ixgbe_identify_module_generic(hw); 1755 1756 if (status != IXGBE_SUCCESS) 1757 return status; 1758 1759 /* Check if SFP module is supported */ 1760 status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 1761 1762 return status; 1763 } 1764 1765 /** 1766 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops 1767 * @hw: pointer to hardware structure 1768 */ 1769 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) 1770 { 1771 s32 status; 1772 bool linear; 1773 1774 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em"); 1775 1776 /* Check if SFP module is supported */ 1777 status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 1778 1779 if (status != IXGBE_SUCCESS) 1780 return status; 1781 1782 ixgbe_init_mac_link_ops_X550em(hw); 1783 hw->phy.ops.reset = NULL; 1784 1785 return IXGBE_SUCCESS; 1786 } 1787 1788 /** 1789 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the 1790 * internal PHY 1791 * @hw: pointer to hardware structure 1792 **/ 1793 static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw) 1794 { 1795 s32 status; 1796 u32 link_ctrl; 1797 1798 /* Restart auto-negotiation. */ 1799 status = hw->mac.ops.read_iosf_sb_reg(hw, 1800 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1801 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl); 1802 1803 if (status) { 1804 DEBUGOUT("Auto-negotiation did not complete\n"); 1805 return status; 1806 } 1807 1808 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1809 status = hw->mac.ops.write_iosf_sb_reg(hw, 1810 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1811 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl); 1812 1813 if (hw->mac.type == ixgbe_mac_X550EM_a) { 1814 u32 flx_mask_st20; 1815 1816 /* Indicate to FW that AN restart has been asserted */ 1817 status = hw->mac.ops.read_iosf_sb_reg(hw, 1818 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1819 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20); 1820 1821 if (status) { 1822 DEBUGOUT("Auto-negotiation did not complete\n"); 1823 return status; 1824 } 1825 1826 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART; 1827 status = hw->mac.ops.write_iosf_sb_reg(hw, 1828 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1829 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20); 1830 } 1831 1832 return status; 1833 } 1834 1835 /** 1836 * ixgbe_setup_sgmii - Set up link for sgmii 1837 * @hw: pointer to hardware structure 1838 */ 1839 static s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1840 bool autoneg_wait) 1841 { 1842 struct ixgbe_mac_info *mac = &hw->mac; 1843 u32 lval, sval, flx_val; 1844 s32 rc; 1845 1846 rc = mac->ops.read_iosf_sb_reg(hw, 1847 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1848 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 1849 if (rc) 1850 return rc; 1851 1852 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1853 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1854 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 1855 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 1856 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1857 rc = mac->ops.write_iosf_sb_reg(hw, 1858 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1859 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 1860 if (rc) 1861 return rc; 1862 1863 rc = mac->ops.read_iosf_sb_reg(hw, 1864 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1865 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 1866 if (rc) 1867 return rc; 1868 1869 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 1870 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 1871 rc = mac->ops.write_iosf_sb_reg(hw, 1872 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1873 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 1874 if (rc) 1875 return rc; 1876 1877 rc = mac->ops.read_iosf_sb_reg(hw, 1878 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1879 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 1880 if (rc) 1881 return rc; 1882 1883 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 1884 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 1885 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 1886 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 1887 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 1888 1889 rc = mac->ops.write_iosf_sb_reg(hw, 1890 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1891 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 1892 if (rc) 1893 return rc; 1894 1895 rc = ixgbe_restart_an_internal_phy_x550em(hw); 1896 if (rc) 1897 return rc; 1898 1899 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 1900 } 1901 1902 /** 1903 * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs 1904 * @hw: pointer to hardware structure 1905 */ 1906 static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1907 bool autoneg_wait) 1908 { 1909 struct ixgbe_mac_info *mac = &hw->mac; 1910 u32 lval, sval, flx_val; 1911 s32 rc; 1912 1913 rc = mac->ops.read_iosf_sb_reg(hw, 1914 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1915 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 1916 if (rc) 1917 return rc; 1918 1919 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1920 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1921 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 1922 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 1923 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1924 rc = mac->ops.write_iosf_sb_reg(hw, 1925 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1926 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 1927 if (rc) 1928 return rc; 1929 1930 rc = mac->ops.read_iosf_sb_reg(hw, 1931 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1932 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 1933 if (rc) 1934 return rc; 1935 1936 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 1937 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 1938 rc = mac->ops.write_iosf_sb_reg(hw, 1939 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1940 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 1941 if (rc) 1942 return rc; 1943 1944 rc = mac->ops.write_iosf_sb_reg(hw, 1945 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1946 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 1947 if (rc) 1948 return rc; 1949 1950 rc = mac->ops.read_iosf_sb_reg(hw, 1951 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1952 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 1953 if (rc) 1954 return rc; 1955 1956 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 1957 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 1958 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 1959 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 1960 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 1961 1962 rc = mac->ops.write_iosf_sb_reg(hw, 1963 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1964 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 1965 if (rc) 1966 return rc; 1967 1968 rc = ixgbe_restart_an_internal_phy_x550em(hw); 1969 1970 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 1971 } 1972 1973 /** 1974 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers 1975 * @hw: pointer to hardware structure 1976 */ 1977 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) 1978 { 1979 struct ixgbe_mac_info *mac = &hw->mac; 1980 1981 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em"); 1982 1983 switch (hw->mac.ops.get_media_type(hw)) { 1984 case ixgbe_media_type_fiber: 1985 /* CS4227 does not support autoneg, so disable the laser control 1986 * functions for SFP+ fiber 1987 */ 1988 mac->ops.disable_tx_laser = NULL; 1989 mac->ops.enable_tx_laser = NULL; 1990 mac->ops.flap_tx_laser = NULL; 1991 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 1992 mac->ops.set_rate_select_speed = 1993 ixgbe_set_soft_rate_select_speed; 1994 1995 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) || 1996 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP)) 1997 mac->ops.setup_mac_link = 1998 ixgbe_setup_mac_link_sfp_x550a; 1999 else 2000 mac->ops.setup_mac_link = 2001 ixgbe_setup_mac_link_sfp_x550em; 2002 break; 2003 case ixgbe_media_type_copper: 2004 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) 2005 break; 2006 if (hw->mac.type == ixgbe_mac_X550EM_a) { 2007 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 2008 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) { 2009 mac->ops.setup_link = ixgbe_setup_sgmii_fw; 2010 mac->ops.check_link = 2011 ixgbe_check_mac_link_generic; 2012 } else { 2013 mac->ops.setup_link = 2014 ixgbe_setup_mac_link_t_X550em; 2015 } 2016 } else { 2017 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 2018 mac->ops.check_link = ixgbe_check_link_t_X550em; 2019 } 2020 break; 2021 case ixgbe_media_type_backplane: 2022 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII || 2023 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) 2024 mac->ops.setup_link = ixgbe_setup_sgmii; 2025 break; 2026 default: 2027 break; 2028 } 2029 } 2030 2031 /** 2032 * ixgbe_get_link_capabilities_x550em - Determines link capabilities 2033 * @hw: pointer to hardware structure 2034 * @speed: pointer to link speed 2035 * @autoneg: TRUE when autoneg or autotry is enabled 2036 */ 2037 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, 2038 ixgbe_link_speed *speed, 2039 bool *autoneg) 2040 { 2041 DEBUGFUNC("ixgbe_get_link_capabilities_X550em"); 2042 2043 2044 if (hw->phy.type == ixgbe_phy_fw) { 2045 *autoneg = TRUE; 2046 *speed = hw->phy.speeds_supported; 2047 return 0; 2048 } 2049 2050 /* SFP */ 2051 if (hw->phy.media_type == ixgbe_media_type_fiber) { 2052 2053 /* CS4227 SFP must not enable auto-negotiation */ 2054 *autoneg = FALSE; 2055 2056 /* Check if 1G SFP module. */ 2057 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 2058 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 2059 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 2060 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) { 2061 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2062 return IXGBE_SUCCESS; 2063 } 2064 2065 /* Link capabilities are based on SFP */ 2066 if (hw->phy.multispeed_fiber) 2067 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2068 IXGBE_LINK_SPEED_1GB_FULL; 2069 else 2070 *speed = IXGBE_LINK_SPEED_10GB_FULL; 2071 } else { 2072 switch (hw->phy.type) { 2073 case ixgbe_phy_ext_1g_t: 2074 case ixgbe_phy_sgmii: 2075 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2076 break; 2077 case ixgbe_phy_x550em_kr: 2078 if (hw->mac.type == ixgbe_mac_X550EM_a) { 2079 /* check different backplane modes */ 2080 if (hw->phy.nw_mng_if_sel & 2081 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) { 2082 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 2083 break; 2084 } else if (hw->device_id == 2085 IXGBE_DEV_ID_X550EM_A_KR_L) { 2086 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2087 break; 2088 } 2089 } 2090 /* fall through */ 2091 default: 2092 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2093 IXGBE_LINK_SPEED_1GB_FULL; 2094 break; 2095 } 2096 *autoneg = TRUE; 2097 } 2098 2099 return IXGBE_SUCCESS; 2100 } 2101 2102 /** 2103 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause 2104 * @hw: pointer to hardware structure 2105 * @lsc: pointer to boolean flag which indicates whether external Base T 2106 * PHY interrupt is lsc 2107 * 2108 * Determime if external Base T PHY interrupt cause is high temperature 2109 * failure alarm or link status change. 2110 * 2111 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 2112 * failure alarm, else return PHY access status. 2113 */ 2114 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc) 2115 { 2116 u32 status; 2117 u16 reg; 2118 2119 *lsc = FALSE; 2120 2121 /* Vendor alarm triggered */ 2122 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2123 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2124 ®); 2125 2126 if (status != IXGBE_SUCCESS || 2127 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN)) 2128 return status; 2129 2130 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */ 2131 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, 2132 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2133 ®); 2134 2135 if (status != IXGBE_SUCCESS || 2136 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2137 IXGBE_MDIO_GLOBAL_ALARM_1_INT))) 2138 return status; 2139 2140 /* Global alarm triggered */ 2141 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, 2142 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2143 ®); 2144 2145 if (status != IXGBE_SUCCESS) 2146 return status; 2147 2148 /* If high temperature failure, then return over temp error and exit */ 2149 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) { 2150 /* power down the PHY in case the PHY FW didn't already */ 2151 ixgbe_set_copper_phy_power(hw, FALSE); 2152 return IXGBE_ERR_OVERTEMP; 2153 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) { 2154 /* device fault alarm triggered */ 2155 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG, 2156 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2157 ®); 2158 2159 if (status != IXGBE_SUCCESS) 2160 return status; 2161 2162 /* if device fault was due to high temp alarm handle and exit */ 2163 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) { 2164 /* power down the PHY in case the PHY FW didn't */ 2165 ixgbe_set_copper_phy_power(hw, FALSE); 2166 return IXGBE_ERR_OVERTEMP; 2167 } 2168 } 2169 2170 /* Vendor alarm 2 triggered */ 2171 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2172 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 2173 2174 if (status != IXGBE_SUCCESS || 2175 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT)) 2176 return status; 2177 2178 /* link connect/disconnect event occurred */ 2179 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2, 2180 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 2181 2182 if (status != IXGBE_SUCCESS) 2183 return status; 2184 2185 /* Indicate LSC */ 2186 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC) 2187 *lsc = TRUE; 2188 2189 return IXGBE_SUCCESS; 2190 } 2191 2192 /** 2193 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts 2194 * @hw: pointer to hardware structure 2195 * 2196 * Enable link status change and temperature failure alarm for the external 2197 * Base T PHY 2198 * 2199 * Returns PHY access status 2200 */ 2201 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw) 2202 { 2203 u32 status; 2204 u16 reg; 2205 bool lsc; 2206 2207 /* Clear interrupt flags */ 2208 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 2209 2210 /* Enable link status change alarm */ 2211 2212 /* Enable the LASI interrupts on X552 devices to receive notifications 2213 * of the link configurations of the external PHY and correspondingly 2214 * support the configuration of the internal iXFI link, since iXFI does 2215 * not support auto-negotiation. This is not required for X553 devices 2216 * having KR support, which performs auto-negotiations and which is used 2217 * as the internal link to the external PHY. Hence adding a check here 2218 * to avoid enabling LASI interrupts for X553 devices. 2219 */ 2220 if (hw->mac.type != ixgbe_mac_X550EM_a) { 2221 status = hw->phy.ops.read_reg(hw, 2222 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2223 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 2224 2225 if (status != IXGBE_SUCCESS) 2226 return status; 2227 2228 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN; 2229 2230 status = hw->phy.ops.write_reg(hw, 2231 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2232 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg); 2233 2234 if (status != IXGBE_SUCCESS) 2235 return status; 2236 } 2237 2238 /* Enable high temperature failure and global fault alarms */ 2239 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2240 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2241 ®); 2242 2243 if (status != IXGBE_SUCCESS) 2244 return status; 2245 2246 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN | 2247 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN); 2248 2249 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2250 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2251 reg); 2252 2253 if (status != IXGBE_SUCCESS) 2254 return status; 2255 2256 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */ 2257 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2258 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2259 ®); 2260 2261 if (status != IXGBE_SUCCESS) 2262 return status; 2263 2264 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2265 IXGBE_MDIO_GLOBAL_ALARM_1_INT); 2266 2267 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2268 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2269 reg); 2270 2271 if (status != IXGBE_SUCCESS) 2272 return status; 2273 2274 /* Enable chip-wide vendor alarm */ 2275 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2276 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2277 ®); 2278 2279 if (status != IXGBE_SUCCESS) 2280 return status; 2281 2282 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN; 2283 2284 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2285 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2286 reg); 2287 2288 return status; 2289 } 2290 2291 /** 2292 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed. 2293 * @hw: pointer to hardware structure 2294 * @speed: link speed 2295 * 2296 * Configures the integrated KR PHY. 2297 **/ 2298 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, 2299 ixgbe_link_speed speed) 2300 { 2301 s32 status; 2302 u32 reg_val; 2303 2304 status = hw->mac.ops.read_iosf_sb_reg(hw, 2305 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2306 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2307 if (status) 2308 return status; 2309 2310 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2311 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | 2312 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); 2313 2314 /* Advertise 10G support. */ 2315 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 2316 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; 2317 2318 /* Advertise 1G support. */ 2319 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 2320 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; 2321 2322 status = hw->mac.ops.write_iosf_sb_reg(hw, 2323 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2324 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2325 2326 if (hw->mac.type == ixgbe_mac_X550EM_a) { 2327 /* Set lane mode to KR auto negotiation */ 2328 status = hw->mac.ops.read_iosf_sb_reg(hw, 2329 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2330 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2331 2332 if (status) 2333 return status; 2334 2335 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2336 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 2337 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2338 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2339 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2340 2341 status = hw->mac.ops.write_iosf_sb_reg(hw, 2342 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2343 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2344 } 2345 2346 return ixgbe_restart_an_internal_phy_x550em(hw); 2347 } 2348 2349 /** 2350 * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs 2351 * @hw: pointer to hardware structure 2352 */ 2353 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw) 2354 { 2355 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 2356 s32 rc; 2357 2358 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 2359 return IXGBE_SUCCESS; 2360 2361 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store); 2362 if (rc) 2363 return rc; 2364 memset(store, 0, sizeof(store)); 2365 2366 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store); 2367 if (rc) 2368 return rc; 2369 2370 return ixgbe_setup_fw_link(hw); 2371 } 2372 2373 /** 2374 * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp 2375 * @hw: pointer to hardware structure 2376 */ 2377 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw) 2378 { 2379 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 2380 s32 rc; 2381 2382 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store); 2383 if (rc) 2384 return rc; 2385 2386 if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) { 2387 ixgbe_shutdown_fw_phy(hw); 2388 return IXGBE_ERR_OVERTEMP; 2389 } 2390 return IXGBE_SUCCESS; 2391 } 2392 2393 /** 2394 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register 2395 * @hw: pointer to hardware structure 2396 * 2397 * Read NW_MNG_IF_SEL register and save field values, and check for valid field 2398 * values. 2399 **/ 2400 static s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw) 2401 { 2402 /* Save NW management interface connected on board. This is used 2403 * to determine internal PHY mode. 2404 */ 2405 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 2406 2407 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set 2408 * PHY address. This register field was has only been used for X552. 2409 */ 2410 if (hw->mac.type == ixgbe_mac_X550EM_a && 2411 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) { 2412 hw->phy.addr = (hw->phy.nw_mng_if_sel & 2413 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 2414 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 2415 } 2416 2417 return IXGBE_SUCCESS; 2418 } 2419 2420 /** 2421 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init 2422 * @hw: pointer to hardware structure 2423 * 2424 * Initialize any function pointers that were not able to be 2425 * set during init_shared_code because the PHY/SFP type was 2426 * not known. Perform the SFP init if necessary. 2427 */ 2428 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) 2429 { 2430 struct ixgbe_phy_info *phy = &hw->phy; 2431 s32 ret_val; 2432 2433 DEBUGFUNC("ixgbe_init_phy_ops_X550em"); 2434 2435 hw->mac.ops.set_lan_id(hw); 2436 ixgbe_read_mng_if_sel_x550em(hw); 2437 2438 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { 2439 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 2440 ixgbe_setup_mux_ctl(hw); 2441 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em; 2442 } 2443 2444 switch (hw->device_id) { 2445 case IXGBE_DEV_ID_X550EM_A_1G_T: 2446 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2447 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22; 2448 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22; 2449 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a; 2450 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a; 2451 phy->ops.check_overtemp = ixgbe_check_overtemp_fw; 2452 if (hw->bus.lan_id) 2453 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; 2454 else 2455 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; 2456 2457 break; 2458 case IXGBE_DEV_ID_X550EM_A_10G_T: 2459 case IXGBE_DEV_ID_X550EM_A_SFP: 2460 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a; 2461 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a; 2462 if (hw->bus.lan_id) 2463 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; 2464 else 2465 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; 2466 break; 2467 case IXGBE_DEV_ID_X550EM_X_SFP: 2468 /* set up for CS4227 usage */ 2469 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 2470 break; 2471 default: 2472 break; 2473 } 2474 2475 /* Identify the PHY or SFP module */ 2476 ret_val = phy->ops.identify(hw); 2477 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED || 2478 ret_val == IXGBE_ERR_PHY_ADDR_INVALID) 2479 return ret_val; 2480 2481 /* Setup function pointers based on detected hardware */ 2482 ixgbe_init_mac_link_ops_X550em(hw); 2483 if (phy->sfp_type != ixgbe_sfp_type_unknown) 2484 phy->ops.reset = NULL; 2485 2486 /* Set functions pointers based on phy type */ 2487 switch (hw->phy.type) { 2488 case ixgbe_phy_x550em_kx4: 2489 phy->ops.setup_link = NULL; 2490 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 2491 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 2492 break; 2493 case ixgbe_phy_x550em_kr: 2494 phy->ops.setup_link = ixgbe_setup_kr_x550em; 2495 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 2496 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 2497 break; 2498 case ixgbe_phy_ext_1g_t: 2499 /* link is managed by FW */ 2500 phy->ops.setup_link = NULL; 2501 phy->ops.reset = NULL; 2502 break; 2503 case ixgbe_phy_x550em_xfi: 2504 /* link is managed by HW */ 2505 phy->ops.setup_link = NULL; 2506 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 2507 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 2508 break; 2509 case ixgbe_phy_x550em_ext_t: 2510 /* If internal link mode is XFI, then setup iXFI internal link, 2511 * else setup KR now. 2512 */ 2513 phy->ops.setup_internal_link = 2514 ixgbe_setup_internal_phy_t_x550em; 2515 2516 /* setup SW LPLU only for first revision of X550EM_x */ 2517 if ((hw->mac.type == ixgbe_mac_X550EM_x) && 2518 !(IXGBE_FUSES0_REV_MASK & 2519 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))) 2520 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em; 2521 2522 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; 2523 phy->ops.reset = ixgbe_reset_phy_t_X550em; 2524 break; 2525 case ixgbe_phy_sgmii: 2526 phy->ops.setup_link = NULL; 2527 break; 2528 case ixgbe_phy_fw: 2529 phy->ops.setup_link = ixgbe_setup_fw_link; 2530 phy->ops.reset = ixgbe_reset_phy_fw; 2531 break; 2532 default: 2533 break; 2534 } 2535 return ret_val; 2536 } 2537 2538 /** 2539 * ixgbe_set_mdio_speed - Set MDIO clock speed 2540 * @hw: pointer to hardware structure 2541 */ 2542 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw) 2543 { 2544 u32 hlreg0; 2545 2546 switch (hw->device_id) { 2547 case IXGBE_DEV_ID_X550EM_X_10G_T: 2548 case IXGBE_DEV_ID_X550EM_A_SGMII: 2549 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 2550 case IXGBE_DEV_ID_X550EM_A_10G_T: 2551 case IXGBE_DEV_ID_X550EM_A_SFP: 2552 case IXGBE_DEV_ID_X550EM_A_QSFP: 2553 /* Config MDIO clock speed before the first MDIO PHY access */ 2554 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 2555 hlreg0 &= ~IXGBE_HLREG0_MDCSPD; 2556 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 2557 break; 2558 case IXGBE_DEV_ID_X550EM_A_1G_T: 2559 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2560 /* Select fast MDIO clock speed for these devices */ 2561 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 2562 hlreg0 |= IXGBE_HLREG0_MDCSPD; 2563 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 2564 break; 2565 default: 2566 break; 2567 } 2568 } 2569 2570 /** 2571 * ixgbe_reset_hw_X550em - Perform hardware reset 2572 * @hw: pointer to hardware structure 2573 * 2574 * Resets the hardware by resetting the transmit and receive units, masks 2575 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 2576 * reset. 2577 */ 2578 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) 2579 { 2580 ixgbe_link_speed link_speed; 2581 s32 status; 2582 u32 ctrl = 0; 2583 u32 i; 2584 bool link_up = FALSE; 2585 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2586 2587 DEBUGFUNC("ixgbe_reset_hw_X550em"); 2588 2589 /* Call adapter stop to disable Tx/Rx and clear interrupts */ 2590 status = hw->mac.ops.stop_adapter(hw); 2591 if (status != IXGBE_SUCCESS) { 2592 DEBUGOUT1("Failed to stop adapter, STATUS = %d\n", status); 2593 return status; 2594 } 2595 /* flush pending Tx transactions */ 2596 ixgbe_clear_tx_pending(hw); 2597 2598 ixgbe_set_mdio_speed(hw); 2599 2600 /* PHY ops must be identified and initialized prior to reset */ 2601 status = hw->phy.ops.init(hw); 2602 2603 if (status) 2604 DEBUGOUT1("Failed to initialize PHY ops, STATUS = %d\n", 2605 status); 2606 2607 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) { 2608 DEBUGOUT("Returning from reset HW due to PHY init failure\n"); 2609 return status; 2610 } 2611 2612 /* start the external PHY */ 2613 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 2614 status = ixgbe_init_ext_t_x550em(hw); 2615 if (status) { 2616 DEBUGOUT1("Failed to start the external PHY, STATUS = %d\n", 2617 status); 2618 return status; 2619 } 2620 } 2621 2622 /* Setup SFP module if there is one present. */ 2623 if (hw->phy.sfp_setup_needed) { 2624 status = hw->mac.ops.setup_sfp(hw); 2625 hw->phy.sfp_setup_needed = FALSE; 2626 } 2627 2628 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 2629 return status; 2630 2631 /* Reset PHY */ 2632 if (!hw->phy.reset_disable && hw->phy.ops.reset) { 2633 if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP) 2634 return IXGBE_ERR_OVERTEMP; 2635 } 2636 2637 mac_reset_top: 2638 /* Issue global reset to the MAC. Needs to be SW reset if link is up. 2639 * If link reset is used when link is up, it might reset the PHY when 2640 * mng is using it. If link is down or the flag to force full link 2641 * reset is set, then perform link reset. 2642 */ 2643 ctrl = IXGBE_CTRL_LNK_RST; 2644 if (!hw->force_full_reset) { 2645 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE); 2646 if (link_up) 2647 ctrl = IXGBE_CTRL_RST; 2648 } 2649 2650 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 2651 if (status != IXGBE_SUCCESS) { 2652 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 2653 "semaphore failed with %d", status); 2654 return IXGBE_ERR_SWFW_SYNC; 2655 } 2656 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 2657 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 2658 IXGBE_WRITE_FLUSH(hw); 2659 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2660 2661 /* Poll for reset bit to self-clear meaning reset is complete */ 2662 for (i = 0; i < 10; i++) { 2663 usec_delay(1); 2664 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 2665 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 2666 break; 2667 } 2668 2669 if (ctrl & IXGBE_CTRL_RST_MASK) { 2670 status = IXGBE_ERR_RESET_FAILED; 2671 DEBUGOUT("Reset polling failed to complete.\n"); 2672 } 2673 2674 msec_delay(50); 2675 2676 /* Double resets are required for recovery from certain error 2677 * conditions. Between resets, it is necessary to stall to 2678 * allow time for any pending HW events to complete. 2679 */ 2680 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 2681 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 2682 goto mac_reset_top; 2683 } 2684 2685 /* Store the permanent mac address */ 2686 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 2687 2688 /* Store MAC address from RAR0, clear receive address registers, and 2689 * clear the multicast table. Also reset num_rar_entries to 128, 2690 * since we modify this value when programming the SAN MAC address. 2691 */ 2692 hw->mac.num_rar_entries = 128; 2693 hw->mac.ops.init_rx_addrs(hw); 2694 2695 ixgbe_set_mdio_speed(hw); 2696 2697 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) 2698 ixgbe_setup_mux_ctl(hw); 2699 2700 if (status != IXGBE_SUCCESS) 2701 DEBUGOUT1("Reset HW failed, STATUS = %d\n", status); 2702 2703 return status; 2704 } 2705 2706 /** 2707 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. 2708 * @hw: pointer to hardware structure 2709 */ 2710 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) 2711 { 2712 u32 status; 2713 u16 reg; 2714 2715 status = hw->phy.ops.read_reg(hw, 2716 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 2717 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 2718 ®); 2719 2720 if (status != IXGBE_SUCCESS) 2721 return status; 2722 2723 /* If PHY FW reset completed bit is set then this is the first 2724 * SW instance after a power on so the PHY FW must be un-stalled. 2725 */ 2726 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 2727 status = hw->phy.ops.read_reg(hw, 2728 IXGBE_MDIO_GLOBAL_RES_PR_10, 2729 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2730 ®); 2731 2732 if (status != IXGBE_SUCCESS) 2733 return status; 2734 2735 reg &= ~IXGBE_MDIO_POWER_UP_STALL; 2736 2737 status = hw->phy.ops.write_reg(hw, 2738 IXGBE_MDIO_GLOBAL_RES_PR_10, 2739 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2740 reg); 2741 2742 if (status != IXGBE_SUCCESS) 2743 return status; 2744 } 2745 2746 return status; 2747 } 2748 2749 /** 2750 * ixgbe_setup_kr_x550em - Configure the KR PHY. 2751 * @hw: pointer to hardware structure 2752 **/ 2753 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) 2754 { 2755 /* leave link alone for 2.5G */ 2756 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL) 2757 return IXGBE_SUCCESS; 2758 2759 if (ixgbe_check_reset_blocked(hw)) 2760 return 0; 2761 2762 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); 2763 } 2764 2765 /** 2766 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP 2767 * @hw: pointer to hardware structure 2768 * 2769 * Configure the external PHY and the integrated KR PHY for SFP support. 2770 **/ 2771 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, 2772 ixgbe_link_speed speed, 2773 bool autoneg_wait_to_complete) 2774 { 2775 s32 ret_val; 2776 u16 reg_slice, reg_val; 2777 bool setup_linear = FALSE; 2778 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 2779 2780 /* Check if SFP module is supported and linear */ 2781 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 2782 2783 /* If no SFP module present, then return success. Return success since 2784 * there is no reason to configure CS4227 and SFP not present error is 2785 * not excepted in the setup MAC link flow. 2786 */ 2787 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 2788 return IXGBE_SUCCESS; 2789 2790 if (ret_val != IXGBE_SUCCESS) 2791 return ret_val; 2792 2793 /* Configure internal PHY for KR/KX. */ 2794 ixgbe_setup_kr_speed_x550em(hw, speed); 2795 2796 /* Configure CS4227 LINE side to proper mode. */ 2797 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + 2798 (hw->bus.lan_id << 12); 2799 if (setup_linear) 2800 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 2801 else 2802 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 2803 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice, 2804 reg_val); 2805 return ret_val; 2806 } 2807 2808 /** 2809 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode 2810 * @hw: pointer to hardware structure 2811 * @speed: the link speed to force 2812 * 2813 * Configures the integrated PHY for native SFI mode. Used to connect the 2814 * internal PHY directly to an SFP cage, without autonegotiation. 2815 **/ 2816 static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 2817 { 2818 struct ixgbe_mac_info *mac = &hw->mac; 2819 s32 status; 2820 u32 reg_val; 2821 2822 /* Disable all AN and force speed to 10G Serial. */ 2823 status = mac->ops.read_iosf_sb_reg(hw, 2824 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2825 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2826 if (status != IXGBE_SUCCESS) 2827 return status; 2828 2829 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2830 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2831 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2832 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2833 2834 /* Select forced link speed for internal PHY. */ 2835 switch (*speed) { 2836 case IXGBE_LINK_SPEED_10GB_FULL: 2837 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G; 2838 break; 2839 case IXGBE_LINK_SPEED_1GB_FULL: 2840 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 2841 break; 2842 default: 2843 /* Other link speeds are not supported by internal PHY. */ 2844 return IXGBE_ERR_LINK_SETUP; 2845 } 2846 2847 status = mac->ops.write_iosf_sb_reg(hw, 2848 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2849 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2850 2851 /* Toggle port SW reset by AN reset. */ 2852 status = ixgbe_restart_an_internal_phy_x550em(hw); 2853 2854 return status; 2855 } 2856 2857 /** 2858 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP 2859 * @hw: pointer to hardware structure 2860 * 2861 * Configure the the integrated PHY for SFP support. 2862 **/ 2863 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, 2864 ixgbe_link_speed speed, 2865 bool autoneg_wait_to_complete) 2866 { 2867 s32 ret_val; 2868 u16 reg_phy_ext; 2869 bool setup_linear = FALSE; 2870 u32 reg_slice, reg_phy_int, slice_offset; 2871 2872 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 2873 2874 /* Check if SFP module is supported and linear */ 2875 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 2876 2877 /* If no SFP module present, then return success. Return success since 2878 * SFP not present error is not excepted in the setup MAC link flow. 2879 */ 2880 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 2881 return IXGBE_SUCCESS; 2882 2883 if (ret_val != IXGBE_SUCCESS) 2884 return ret_val; 2885 2886 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) { 2887 /* Configure internal PHY for native SFI based on module type */ 2888 ret_val = hw->mac.ops.read_iosf_sb_reg(hw, 2889 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2890 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int); 2891 2892 if (ret_val != IXGBE_SUCCESS) 2893 return ret_val; 2894 2895 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA; 2896 if (!setup_linear) 2897 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR; 2898 2899 ret_val = hw->mac.ops.write_iosf_sb_reg(hw, 2900 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2901 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int); 2902 2903 if (ret_val != IXGBE_SUCCESS) 2904 return ret_val; 2905 2906 /* Setup SFI internal link. */ 2907 ret_val = ixgbe_setup_sfi_x550a(hw, &speed); 2908 } else { 2909 /* Configure internal PHY for KR/KX. */ 2910 ixgbe_setup_kr_speed_x550em(hw, speed); 2911 2912 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) { 2913 /* Find Address */ 2914 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n"); 2915 return IXGBE_ERR_PHY_ADDR_INVALID; 2916 } 2917 2918 /* Get external PHY SKU id */ 2919 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU, 2920 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 2921 2922 if (ret_val != IXGBE_SUCCESS) 2923 return ret_val; 2924 2925 /* When configuring quad port CS4223, the MAC instance is part 2926 * of the slice offset. 2927 */ 2928 if (reg_phy_ext == IXGBE_CS4223_SKU_ID) 2929 slice_offset = (hw->bus.lan_id + 2930 (hw->bus.instance_id << 1)) << 12; 2931 else 2932 slice_offset = hw->bus.lan_id << 12; 2933 2934 /* Configure CS4227/CS4223 LINE side to proper mode. */ 2935 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset; 2936 2937 ret_val = hw->phy.ops.read_reg(hw, reg_slice, 2938 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 2939 2940 if (ret_val != IXGBE_SUCCESS) 2941 return ret_val; 2942 2943 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) | 2944 (IXGBE_CS4227_EDC_MODE_SR << 1)); 2945 2946 if (setup_linear) 2947 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 2948 else 2949 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 2950 ret_val = hw->phy.ops.write_reg(hw, reg_slice, 2951 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext); 2952 2953 /* Flush previous write with a read */ 2954 ret_val = hw->phy.ops.read_reg(hw, reg_slice, 2955 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 2956 } 2957 return ret_val; 2958 } 2959 2960 /** 2961 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration 2962 * @hw: pointer to hardware structure 2963 * 2964 * iXfI configuration needed for ixgbe_mac_X550EM_x devices. 2965 **/ 2966 static s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw) 2967 { 2968 struct ixgbe_mac_info *mac = &hw->mac; 2969 s32 status; 2970 u32 reg_val; 2971 2972 /* Disable training protocol FSM. */ 2973 status = mac->ops.read_iosf_sb_reg(hw, 2974 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 2975 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2976 if (status != IXGBE_SUCCESS) 2977 return status; 2978 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; 2979 status = mac->ops.write_iosf_sb_reg(hw, 2980 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 2981 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2982 if (status != IXGBE_SUCCESS) 2983 return status; 2984 2985 /* Disable Flex from training TXFFE. */ 2986 status = mac->ops.read_iosf_sb_reg(hw, 2987 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 2988 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2989 if (status != IXGBE_SUCCESS) 2990 return status; 2991 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 2992 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 2993 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 2994 status = mac->ops.write_iosf_sb_reg(hw, 2995 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 2996 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2997 if (status != IXGBE_SUCCESS) 2998 return status; 2999 status = mac->ops.read_iosf_sb_reg(hw, 3000 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 3001 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3002 if (status != IXGBE_SUCCESS) 3003 return status; 3004 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 3005 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 3006 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 3007 status = mac->ops.write_iosf_sb_reg(hw, 3008 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 3009 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3010 if (status != IXGBE_SUCCESS) 3011 return status; 3012 3013 /* Enable override for coefficients. */ 3014 status = mac->ops.read_iosf_sb_reg(hw, 3015 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 3016 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3017 if (status != IXGBE_SUCCESS) 3018 return status; 3019 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; 3020 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; 3021 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; 3022 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; 3023 status = mac->ops.write_iosf_sb_reg(hw, 3024 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 3025 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3026 return status; 3027 } 3028 3029 /** 3030 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. 3031 * @hw: pointer to hardware structure 3032 * @speed: the link speed to force 3033 * 3034 * Configures the integrated KR PHY to use iXFI mode. Used to connect an 3035 * internal and external PHY at a specific speed, without autonegotiation. 3036 **/ 3037 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 3038 { 3039 struct ixgbe_mac_info *mac = &hw->mac; 3040 s32 status; 3041 u32 reg_val; 3042 3043 /* iXFI is only supported with X552 */ 3044 if (mac->type != ixgbe_mac_X550EM_x) 3045 return IXGBE_ERR_LINK_SETUP; 3046 3047 /* Disable AN and force speed to 10G Serial. */ 3048 status = mac->ops.read_iosf_sb_reg(hw, 3049 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 3050 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3051 if (status != IXGBE_SUCCESS) 3052 return status; 3053 3054 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 3055 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 3056 3057 /* Select forced link speed for internal PHY. */ 3058 switch (*speed) { 3059 case IXGBE_LINK_SPEED_10GB_FULL: 3060 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 3061 break; 3062 case IXGBE_LINK_SPEED_1GB_FULL: 3063 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 3064 break; 3065 default: 3066 /* Other link speeds are not supported by internal KR PHY. */ 3067 return IXGBE_ERR_LINK_SETUP; 3068 } 3069 3070 status = mac->ops.write_iosf_sb_reg(hw, 3071 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 3072 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3073 if (status != IXGBE_SUCCESS) 3074 return status; 3075 3076 /* Additional configuration needed for x550em_x */ 3077 if (hw->mac.type == ixgbe_mac_X550EM_x) { 3078 status = ixgbe_setup_ixfi_x550em_x(hw); 3079 if (status != IXGBE_SUCCESS) 3080 return status; 3081 } 3082 3083 /* Toggle port SW reset by AN reset. */ 3084 status = ixgbe_restart_an_internal_phy_x550em(hw); 3085 3086 return status; 3087 } 3088 3089 /** 3090 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status 3091 * @hw: address of hardware structure 3092 * @link_up: address of boolean to indicate link status 3093 * 3094 * Returns error code if unable to get link status. 3095 */ 3096 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up) 3097 { 3098 u32 ret; 3099 u16 autoneg_status; 3100 3101 *link_up = FALSE; 3102 3103 /* read this twice back to back to indicate current status */ 3104 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 3105 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3106 &autoneg_status); 3107 if (ret != IXGBE_SUCCESS) 3108 return ret; 3109 3110 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 3111 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3112 &autoneg_status); 3113 if (ret != IXGBE_SUCCESS) 3114 return ret; 3115 3116 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS); 3117 3118 return IXGBE_SUCCESS; 3119 } 3120 3121 /** 3122 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link 3123 * @hw: point to hardware structure 3124 * 3125 * Configures the link between the integrated KR PHY and the external X557 PHY 3126 * The driver will call this function when it gets a link status change 3127 * interrupt from the X557 PHY. This function configures the link speed 3128 * between the PHYs to match the link speed of the BASE-T link. 3129 * 3130 * A return of a non-zero value indicates an error, and the base driver should 3131 * not report link up. 3132 */ 3133 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw) 3134 { 3135 ixgbe_link_speed force_speed; 3136 bool link_up; 3137 u32 status; 3138 u16 speed; 3139 3140 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 3141 return IXGBE_ERR_CONFIG; 3142 3143 if (hw->mac.type == ixgbe_mac_X550EM_x && 3144 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 3145 /* If link is down, there is no setup necessary so return */ 3146 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3147 if (status != IXGBE_SUCCESS) 3148 return status; 3149 3150 if (!link_up) 3151 return IXGBE_SUCCESS; 3152 3153 status = hw->phy.ops.read_reg(hw, 3154 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 3155 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3156 &speed); 3157 if (status != IXGBE_SUCCESS) 3158 return status; 3159 3160 /* If link is still down - no setup is required so return */ 3161 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3162 if (status != IXGBE_SUCCESS) 3163 return status; 3164 if (!link_up) 3165 return IXGBE_SUCCESS; 3166 3167 /* clear everything but the speed and duplex bits */ 3168 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK; 3169 3170 switch (speed) { 3171 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL: 3172 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 3173 break; 3174 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL: 3175 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 3176 break; 3177 default: 3178 /* Internal PHY does not support anything else */ 3179 return IXGBE_ERR_INVALID_LINK_SETTINGS; 3180 } 3181 3182 return ixgbe_setup_ixfi_x550em(hw, &force_speed); 3183 } else { 3184 speed = IXGBE_LINK_SPEED_10GB_FULL | 3185 IXGBE_LINK_SPEED_1GB_FULL; 3186 return ixgbe_setup_kr_speed_x550em(hw, speed); 3187 } 3188 } 3189 3190 /** 3191 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback. 3192 * @hw: pointer to hardware structure 3193 * 3194 * Configures the integrated KR PHY to use internal loopback mode. 3195 **/ 3196 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw) 3197 { 3198 s32 status; 3199 u32 reg_val; 3200 3201 /* Disable AN and force speed to 10G Serial. */ 3202 status = hw->mac.ops.read_iosf_sb_reg(hw, 3203 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 3204 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3205 if (status != IXGBE_SUCCESS) 3206 return status; 3207 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 3208 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 3209 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 3210 status = hw->mac.ops.write_iosf_sb_reg(hw, 3211 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 3212 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3213 if (status != IXGBE_SUCCESS) 3214 return status; 3215 3216 /* Set near-end loopback clocks. */ 3217 status = hw->mac.ops.read_iosf_sb_reg(hw, 3218 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id), 3219 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3220 if (status != IXGBE_SUCCESS) 3221 return status; 3222 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B; 3223 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS; 3224 status = hw->mac.ops.write_iosf_sb_reg(hw, 3225 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id), 3226 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3227 if (status != IXGBE_SUCCESS) 3228 return status; 3229 3230 /* Set loopback enable. */ 3231 status = hw->mac.ops.read_iosf_sb_reg(hw, 3232 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id), 3233 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3234 if (status != IXGBE_SUCCESS) 3235 return status; 3236 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK; 3237 status = hw->mac.ops.write_iosf_sb_reg(hw, 3238 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id), 3239 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3240 if (status != IXGBE_SUCCESS) 3241 return status; 3242 3243 /* Training bypass. */ 3244 status = hw->mac.ops.read_iosf_sb_reg(hw, 3245 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 3246 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3247 if (status != IXGBE_SUCCESS) 3248 return status; 3249 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS; 3250 status = hw->mac.ops.write_iosf_sb_reg(hw, 3251 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 3252 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3253 3254 return status; 3255 } 3256 3257 /** 3258 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 3259 * assuming that the semaphore is already obtained. 3260 * @hw: pointer to hardware structure 3261 * @offset: offset of word in the EEPROM to read 3262 * @data: word read from the EEPROM 3263 * 3264 * Reads a 16 bit word from the EEPROM using the hostif. 3265 **/ 3266 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data) 3267 { 3268 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 3269 struct ixgbe_hic_read_shadow_ram buffer; 3270 s32 status; 3271 3272 DEBUGFUNC("ixgbe_read_ee_hostif_X550"); 3273 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 3274 buffer.hdr.req.buf_lenh = 0; 3275 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 3276 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 3277 3278 /* convert offset from words to bytes */ 3279 buffer.address = IXGBE_CPU_TO_BE32(offset * 2); 3280 /* one word */ 3281 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16)); 3282 3283 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 3284 if (status) 3285 return status; 3286 3287 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 3288 IXGBE_HI_COMMAND_TIMEOUT); 3289 if (!status) { 3290 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 3291 FW_NVM_DATA_OFFSET); 3292 } 3293 3294 hw->mac.ops.release_swfw_sync(hw, mask); 3295 return status; 3296 } 3297 3298 /** 3299 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif 3300 * @hw: pointer to hardware structure 3301 * @offset: offset of word in the EEPROM to read 3302 * @words: number of words 3303 * @data: word(s) read from the EEPROM 3304 * 3305 * Reads a 16 bit word(s) from the EEPROM using the hostif. 3306 **/ 3307 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 3308 u16 offset, u16 words, u16 *data) 3309 { 3310 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 3311 struct ixgbe_hic_read_shadow_ram buffer; 3312 u32 current_word = 0; 3313 u16 words_to_read; 3314 s32 status; 3315 u32 i; 3316 3317 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550"); 3318 3319 /* Take semaphore for the entire operation. */ 3320 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 3321 if (status) { 3322 DEBUGOUT("EEPROM read buffer - semaphore failed\n"); 3323 return status; 3324 } 3325 3326 while (words) { 3327 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 3328 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 3329 else 3330 words_to_read = words; 3331 3332 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 3333 buffer.hdr.req.buf_lenh = 0; 3334 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 3335 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 3336 3337 /* convert offset from words to bytes */ 3338 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2); 3339 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2); 3340 3341 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 3342 IXGBE_HI_COMMAND_TIMEOUT); 3343 3344 if (status) { 3345 DEBUGOUT("Host interface command failed\n"); 3346 goto out; 3347 } 3348 3349 for (i = 0; i < words_to_read; i++) { 3350 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + 3351 2 * i; 3352 u32 value = IXGBE_READ_REG(hw, reg); 3353 3354 data[current_word] = (u16)(value & 0xffff); 3355 current_word++; 3356 i++; 3357 if (i < words_to_read) { 3358 value >>= 16; 3359 data[current_word] = (u16)(value & 0xffff); 3360 current_word++; 3361 } 3362 } 3363 words -= words_to_read; 3364 } 3365 3366 out: 3367 hw->mac.ops.release_swfw_sync(hw, mask); 3368 return status; 3369 } 3370 3371 /** 3372 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 3373 * @hw: pointer to hardware structure 3374 * @offset: offset of word in the EEPROM to write 3375 * @data: word write to the EEPROM 3376 * 3377 * Write a 16 bit word to the EEPROM using the hostif. 3378 **/ 3379 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 3380 u16 data) 3381 { 3382 s32 status; 3383 struct ixgbe_hic_write_shadow_ram buffer; 3384 3385 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550"); 3386 3387 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; 3388 buffer.hdr.req.buf_lenh = 0; 3389 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; 3390 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 3391 3392 /* one word */ 3393 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16)); 3394 buffer.data = data; 3395 buffer.address = IXGBE_CPU_TO_BE32(offset * 2); 3396 3397 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 3398 sizeof(buffer), 3399 IXGBE_HI_COMMAND_TIMEOUT, FALSE); 3400 3401 return status; 3402 } 3403 3404 /** 3405 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 3406 * @hw: pointer to hardware structure 3407 * @offset: offset of word in the EEPROM to write 3408 * @data: word write to the EEPROM 3409 * 3410 * Write a 16 bit word to the EEPROM using the hostif. 3411 **/ 3412 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, 3413 u16 data) 3414 { 3415 s32 status = IXGBE_SUCCESS; 3416 3417 DEBUGFUNC("ixgbe_write_ee_hostif_X550"); 3418 3419 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 3420 IXGBE_SUCCESS) { 3421 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); 3422 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 3423 } else { 3424 DEBUGOUT("write ee hostif failed to get semaphore"); 3425 status = IXGBE_ERR_SWFW_SYNC; 3426 } 3427 3428 return status; 3429 } 3430 3431 /** 3432 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif 3433 * @hw: pointer to hardware structure 3434 * @offset: offset of word in the EEPROM to write 3435 * @words: number of words 3436 * @data: word(s) write to the EEPROM 3437 * 3438 * Write a 16 bit word(s) to the EEPROM using the hostif. 3439 **/ 3440 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 3441 u16 offset, u16 words, u16 *data) 3442 { 3443 s32 status = IXGBE_SUCCESS; 3444 u32 i = 0; 3445 3446 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550"); 3447 3448 /* Take semaphore for the entire operation. */ 3449 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 3450 if (status != IXGBE_SUCCESS) { 3451 DEBUGOUT("EEPROM write buffer - semaphore failed\n"); 3452 goto out; 3453 } 3454 3455 for (i = 0; i < words; i++) { 3456 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, 3457 data[i]); 3458 3459 if (status != IXGBE_SUCCESS) { 3460 DEBUGOUT("Eeprom buffered write failed\n"); 3461 break; 3462 } 3463 } 3464 3465 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 3466 out: 3467 3468 return status; 3469 } 3470 3471 /** 3472 * ixgbe_checksum_ptr_x550 - Checksum one pointer region 3473 * @hw: pointer to hardware structure 3474 * @ptr: pointer offset in eeprom 3475 * @size: size of section pointed by ptr, if 0 first word will be used as size 3476 * @csum: address of checksum to update 3477 * 3478 * Returns error status for any failure 3479 */ 3480 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, 3481 u16 size, u16 *csum, u16 *buffer, 3482 u32 buffer_size) 3483 { 3484 u16 buf[256]; 3485 s32 status; 3486 u16 length, bufsz, i, start; 3487 u16 *local_buffer; 3488 3489 bufsz = sizeof(buf) / sizeof(buf[0]); 3490 3491 /* Read a chunk at the pointer location */ 3492 if (!buffer) { 3493 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); 3494 if (status) { 3495 DEBUGOUT("Failed to read EEPROM image\n"); 3496 return status; 3497 } 3498 local_buffer = buf; 3499 } else { 3500 if (buffer_size < ptr) 3501 return IXGBE_ERR_PARAM; 3502 local_buffer = &buffer[ptr]; 3503 } 3504 3505 if (size) { 3506 start = 0; 3507 length = size; 3508 } else { 3509 start = 1; 3510 length = local_buffer[0]; 3511 3512 /* Skip pointer section if length is invalid. */ 3513 if (length == 0xFFFF || length == 0 || 3514 (ptr + length) >= hw->eeprom.word_size) 3515 return IXGBE_SUCCESS; 3516 } 3517 3518 if (buffer && ((u32)start + (u32)length > buffer_size)) 3519 return IXGBE_ERR_PARAM; 3520 3521 for (i = start; length; i++, length--) { 3522 if (i == bufsz && !buffer) { 3523 ptr += bufsz; 3524 i = 0; 3525 if (length < bufsz) 3526 bufsz = length; 3527 3528 /* Read a chunk at the pointer location */ 3529 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, 3530 bufsz, buf); 3531 if (status) { 3532 DEBUGOUT("Failed to read EEPROM image\n"); 3533 return status; 3534 } 3535 } 3536 *csum += local_buffer[i]; 3537 } 3538 return IXGBE_SUCCESS; 3539 } 3540 3541 /** 3542 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum 3543 * @hw: pointer to hardware structure 3544 * @buffer: pointer to buffer containing calculated checksum 3545 * @buffer_size: size of buffer 3546 * 3547 * Returns a negative error code on error, or the 16-bit checksum 3548 **/ 3549 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size) 3550 { 3551 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1]; 3552 u16 *local_buffer; 3553 s32 status; 3554 u16 checksum = 0; 3555 u16 pointer, i, size; 3556 3557 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550"); 3558 3559 hw->eeprom.ops.init_params(hw); 3560 3561 if (!buffer) { 3562 /* Read pointer area */ 3563 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, 3564 IXGBE_EEPROM_LAST_WORD + 1, 3565 eeprom_ptrs); 3566 if (status) { 3567 DEBUGOUT("Failed to read EEPROM image\n"); 3568 return status; 3569 } 3570 local_buffer = eeprom_ptrs; 3571 } else { 3572 if (buffer_size < IXGBE_EEPROM_LAST_WORD) 3573 return IXGBE_ERR_PARAM; 3574 local_buffer = buffer; 3575 } 3576 3577 /* 3578 * For X550 hardware include 0x0-0x41 in the checksum, skip the 3579 * checksum word itself 3580 */ 3581 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++) 3582 if (i != IXGBE_EEPROM_CHECKSUM) 3583 checksum += local_buffer[i]; 3584 3585 /* 3586 * Include all data from pointers 0x3, 0x6-0xE. This excludes the 3587 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 3588 */ 3589 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) { 3590 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 3591 continue; 3592 3593 pointer = local_buffer[i]; 3594 3595 /* Skip pointer section if the pointer is invalid. */ 3596 if (pointer == 0xFFFF || pointer == 0 || 3597 pointer >= hw->eeprom.word_size) 3598 continue; 3599 3600 switch (i) { 3601 case IXGBE_PCIE_GENERAL_PTR: 3602 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE; 3603 break; 3604 case IXGBE_PCIE_CONFIG0_PTR: 3605 case IXGBE_PCIE_CONFIG1_PTR: 3606 size = IXGBE_PCIE_CONFIG_SIZE; 3607 break; 3608 default: 3609 size = 0; 3610 break; 3611 } 3612 3613 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, 3614 buffer, buffer_size); 3615 if (status) 3616 return status; 3617 } 3618 3619 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 3620 3621 return (s32)checksum; 3622 } 3623 3624 /** 3625 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum 3626 * @hw: pointer to hardware structure 3627 * 3628 * Returns a negative error code on error, or the 16-bit checksum 3629 **/ 3630 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) 3631 { 3632 return ixgbe_calc_checksum_X550(hw, NULL, 0); 3633 } 3634 3635 /** 3636 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum 3637 * @hw: pointer to hardware structure 3638 * @checksum_val: calculated checksum 3639 * 3640 * Performs checksum calculation and validates the EEPROM checksum. If the 3641 * caller does not need checksum_val, the value can be NULL. 3642 **/ 3643 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val) 3644 { 3645 s32 status; 3646 u16 checksum; 3647 u16 read_checksum = 0; 3648 3649 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550"); 3650 3651 /* Read the first word from the EEPROM. If this times out or fails, do 3652 * not continue or we could be in for a very long wait while every 3653 * EEPROM read fails 3654 */ 3655 status = hw->eeprom.ops.read(hw, 0, &checksum); 3656 if (status) { 3657 DEBUGOUT("EEPROM read failed\n"); 3658 return status; 3659 } 3660 3661 status = hw->eeprom.ops.calc_checksum(hw); 3662 if (status < 0) 3663 return status; 3664 3665 checksum = (u16)(status & 0xffff); 3666 3667 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 3668 &read_checksum); 3669 if (status) 3670 return status; 3671 3672 /* Verify read checksum from EEPROM is the same as 3673 * calculated checksum 3674 */ 3675 if (read_checksum != checksum) { 3676 status = IXGBE_ERR_EEPROM_CHECKSUM; 3677 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 3678 "Invalid EEPROM checksum"); 3679 } 3680 3681 /* If the user cares, return the calculated checksum */ 3682 if (checksum_val) 3683 *checksum_val = checksum; 3684 3685 return status; 3686 } 3687 3688 /** 3689 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash 3690 * @hw: pointer to hardware structure 3691 * 3692 * After writing EEPROM to shadow RAM using EEWR register, software calculates 3693 * checksum and updates the EEPROM and instructs the hardware to update 3694 * the flash. 3695 **/ 3696 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) 3697 { 3698 s32 status; 3699 u16 checksum = 0; 3700 3701 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550"); 3702 3703 /* Read the first word from the EEPROM. If this times out or fails, do 3704 * not continue or we could be in for a very long wait while every 3705 * EEPROM read fails 3706 */ 3707 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); 3708 if (status) { 3709 DEBUGOUT("EEPROM read failed\n"); 3710 return status; 3711 } 3712 3713 status = ixgbe_calc_eeprom_checksum_X550(hw); 3714 if (status < 0) 3715 return status; 3716 3717 checksum = (u16)(status & 0xffff); 3718 3719 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 3720 checksum); 3721 if (status) 3722 return status; 3723 3724 status = ixgbe_update_flash_X550(hw); 3725 3726 return status; 3727 } 3728 3729 /** 3730 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device 3731 * @hw: pointer to hardware structure 3732 * 3733 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash. 3734 **/ 3735 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) 3736 { 3737 s32 status = IXGBE_SUCCESS; 3738 union ixgbe_hic_hdr2 buffer; 3739 3740 DEBUGFUNC("ixgbe_update_flash_X550"); 3741 3742 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; 3743 buffer.req.buf_lenh = 0; 3744 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; 3745 buffer.req.checksum = FW_DEFAULT_CHECKSUM; 3746 3747 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 3748 sizeof(buffer), 3749 IXGBE_HI_COMMAND_TIMEOUT, FALSE); 3750 3751 return status; 3752 } 3753 3754 /** 3755 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type 3756 * @hw: pointer to hardware structure 3757 * 3758 * Determines physical layer capabilities of the current configuration. 3759 **/ 3760 u64 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw) 3761 { 3762 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 3763 u16 ext_ability = 0; 3764 3765 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em"); 3766 3767 hw->phy.ops.identify(hw); 3768 3769 switch (hw->phy.type) { 3770 case ixgbe_phy_x550em_kr: 3771 if (hw->mac.type == ixgbe_mac_X550EM_a) { 3772 if (hw->phy.nw_mng_if_sel & 3773 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) { 3774 physical_layer = 3775 IXGBE_PHYSICAL_LAYER_2500BASE_KX; 3776 break; 3777 } else if (hw->device_id == 3778 IXGBE_DEV_ID_X550EM_A_KR_L) { 3779 physical_layer = 3780 IXGBE_PHYSICAL_LAYER_1000BASE_KX; 3781 break; 3782 } 3783 } 3784 /* fall through */ 3785 case ixgbe_phy_x550em_xfi: 3786 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR | 3787 IXGBE_PHYSICAL_LAYER_1000BASE_KX; 3788 break; 3789 case ixgbe_phy_x550em_kx4: 3790 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 | 3791 IXGBE_PHYSICAL_LAYER_1000BASE_KX; 3792 break; 3793 case ixgbe_phy_x550em_ext_t: 3794 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 3795 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 3796 &ext_ability); 3797 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 3798 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 3799 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 3800 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 3801 break; 3802 case ixgbe_phy_fw: 3803 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_1GB_FULL) 3804 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 3805 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_100_FULL) 3806 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 3807 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_10_FULL) 3808 physical_layer |= IXGBE_PHYSICAL_LAYER_10BASE_T; 3809 break; 3810 case ixgbe_phy_sgmii: 3811 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; 3812 break; 3813 case ixgbe_phy_ext_1g_t: 3814 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 3815 break; 3816 default: 3817 break; 3818 } 3819 3820 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) 3821 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw); 3822 3823 return physical_layer; 3824 } 3825 3826 /** 3827 * ixgbe_get_bus_info_x550em - Set PCI bus info 3828 * @hw: pointer to hardware structure 3829 * 3830 * Sets bus link width and speed to unknown because X550em is 3831 * not a PCI device. 3832 **/ 3833 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw) 3834 { 3835 3836 DEBUGFUNC("ixgbe_get_bus_info_x550em"); 3837 3838 hw->bus.width = ixgbe_bus_width_unknown; 3839 hw->bus.speed = ixgbe_bus_speed_unknown; 3840 3841 hw->mac.ops.set_lan_id(hw); 3842 3843 return IXGBE_SUCCESS; 3844 } 3845 3846 /** 3847 * ixgbe_disable_rx_x550 - Disable RX unit 3848 * 3849 * Enables the Rx DMA unit for x550 3850 **/ 3851 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) 3852 { 3853 u32 rxctrl, pfdtxgswc; 3854 s32 status; 3855 struct ixgbe_hic_disable_rxen fw_cmd; 3856 3857 DEBUGFUNC("ixgbe_disable_rx_dma_x550"); 3858 3859 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 3860 if (rxctrl & IXGBE_RXCTRL_RXEN) { 3861 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 3862 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 3863 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 3864 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 3865 hw->mac.set_lben = TRUE; 3866 } else { 3867 hw->mac.set_lben = FALSE; 3868 } 3869 3870 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD; 3871 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN; 3872 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 3873 fw_cmd.port_number = (u8)hw->bus.lan_id; 3874 3875 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 3876 sizeof(struct ixgbe_hic_disable_rxen), 3877 IXGBE_HI_COMMAND_TIMEOUT, TRUE); 3878 3879 /* If we fail - disable RX using register write */ 3880 if (status) { 3881 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 3882 if (rxctrl & IXGBE_RXCTRL_RXEN) { 3883 rxctrl &= ~IXGBE_RXCTRL_RXEN; 3884 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 3885 } 3886 } 3887 } 3888 } 3889 3890 /** 3891 * ixgbe_enter_lplu_x550em - Transition to low power states 3892 * @hw: pointer to hardware structure 3893 * 3894 * Configures Low Power Link Up on transition to low power states 3895 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the 3896 * X557 PHY immediately prior to entering LPLU. 3897 **/ 3898 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) 3899 { 3900 u16 an_10g_cntl_reg, autoneg_reg, speed; 3901 s32 status; 3902 ixgbe_link_speed lcd_speed; 3903 u32 save_autoneg; 3904 bool link_up; 3905 3906 /* SW LPLU not required on later HW revisions. */ 3907 if ((hw->mac.type == ixgbe_mac_X550EM_x) && 3908 (IXGBE_FUSES0_REV_MASK & 3909 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))) 3910 return IXGBE_SUCCESS; 3911 3912 /* If blocked by MNG FW, then don't restart AN */ 3913 if (ixgbe_check_reset_blocked(hw)) 3914 return IXGBE_SUCCESS; 3915 3916 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3917 if (status != IXGBE_SUCCESS) 3918 return status; 3919 3920 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3); 3921 3922 if (status != IXGBE_SUCCESS) 3923 return status; 3924 3925 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability 3926 * disabled, then force link down by entering low power mode. 3927 */ 3928 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) || 3929 !(hw->wol_enabled || ixgbe_mng_present(hw))) 3930 return ixgbe_set_copper_phy_power(hw, FALSE); 3931 3932 /* Determine LCD */ 3933 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed); 3934 3935 if (status != IXGBE_SUCCESS) 3936 return status; 3937 3938 /* If no valid LCD link speed, then force link down and exit. */ 3939 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN) 3940 return ixgbe_set_copper_phy_power(hw, FALSE); 3941 3942 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 3943 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3944 &speed); 3945 3946 if (status != IXGBE_SUCCESS) 3947 return status; 3948 3949 /* If no link now, speed is invalid so take link down */ 3950 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3951 if (status != IXGBE_SUCCESS) 3952 return ixgbe_set_copper_phy_power(hw, FALSE); 3953 3954 /* clear everything but the speed bits */ 3955 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK; 3956 3957 /* If current speed is already LCD, then exit. */ 3958 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) && 3959 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) || 3960 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) && 3961 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL))) 3962 return status; 3963 3964 /* Clear AN completed indication */ 3965 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM, 3966 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3967 &autoneg_reg); 3968 3969 if (status != IXGBE_SUCCESS) 3970 return status; 3971 3972 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 3973 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3974 &an_10g_cntl_reg); 3975 3976 if (status != IXGBE_SUCCESS) 3977 return status; 3978 3979 status = hw->phy.ops.read_reg(hw, 3980 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 3981 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3982 &autoneg_reg); 3983 3984 if (status != IXGBE_SUCCESS) 3985 return status; 3986 3987 save_autoneg = hw->phy.autoneg_advertised; 3988 3989 /* Setup link at least common link speed */ 3990 status = hw->mac.ops.setup_link(hw, lcd_speed, FALSE); 3991 3992 /* restore autoneg from before setting lplu speed */ 3993 hw->phy.autoneg_advertised = save_autoneg; 3994 3995 return status; 3996 } 3997 3998 /** 3999 * ixgbe_get_lcd_x550em - Determine lowest common denominator 4000 * @hw: pointer to hardware structure 4001 * @lcd_speed: pointer to lowest common link speed 4002 * 4003 * Determine lowest common link speed with link partner. 4004 **/ 4005 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed) 4006 { 4007 u16 an_lp_status; 4008 s32 status; 4009 u16 word = hw->eeprom.ctrl_word_3; 4010 4011 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN; 4012 4013 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS, 4014 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 4015 &an_lp_status); 4016 4017 if (status != IXGBE_SUCCESS) 4018 return status; 4019 4020 /* If link partner advertised 1G, return 1G */ 4021 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) { 4022 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL; 4023 return status; 4024 } 4025 4026 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */ 4027 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) || 4028 (word & NVM_INIT_CTRL_3_D10GMP_PORT0)) 4029 return status; 4030 4031 /* Link partner not capable of lower speeds, return 10G */ 4032 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL; 4033 return status; 4034 } 4035 4036 /** 4037 * ixgbe_setup_fc_X550em - Set up flow control 4038 * @hw: pointer to hardware structure 4039 * 4040 * Called at init time to set up flow control. 4041 **/ 4042 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw) 4043 { 4044 s32 ret_val = IXGBE_SUCCESS; 4045 u32 pause, asm_dir, reg_val; 4046 4047 DEBUGFUNC("ixgbe_setup_fc_X550em"); 4048 4049 /* Validate the requested mode */ 4050 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 4051 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 4052 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 4053 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4054 goto out; 4055 } 4056 4057 /* 10gig parts do not have a word in the EEPROM to determine the 4058 * default flow control setting, so we explicitly set it to full. 4059 */ 4060 if (hw->fc.requested_mode == ixgbe_fc_default) 4061 hw->fc.requested_mode = ixgbe_fc_full; 4062 4063 /* Determine PAUSE and ASM_DIR bits. */ 4064 switch (hw->fc.requested_mode) { 4065 case ixgbe_fc_none: 4066 pause = 0; 4067 asm_dir = 0; 4068 break; 4069 case ixgbe_fc_tx_pause: 4070 pause = 0; 4071 asm_dir = 1; 4072 break; 4073 case ixgbe_fc_rx_pause: 4074 /* Rx Flow control is enabled and Tx Flow control is 4075 * disabled by software override. Since there really 4076 * isn't a way to advertise that we are capable of RX 4077 * Pause ONLY, we will advertise that we support both 4078 * symmetric and asymmetric Rx PAUSE, as such we fall 4079 * through to the fc_full statement. Later, we will 4080 * disable the adapter's ability to send PAUSE frames. 4081 */ 4082 case ixgbe_fc_full: 4083 pause = 1; 4084 asm_dir = 1; 4085 break; 4086 default: 4087 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 4088 "Flow control param set incorrectly\n"); 4089 ret_val = IXGBE_ERR_CONFIG; 4090 goto out; 4091 } 4092 4093 switch (hw->device_id) { 4094 case IXGBE_DEV_ID_X550EM_X_KR: 4095 case IXGBE_DEV_ID_X550EM_A_KR: 4096 case IXGBE_DEV_ID_X550EM_A_KR_L: 4097 ret_val = hw->mac.ops.read_iosf_sb_reg(hw, 4098 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 4099 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 4100 if (ret_val != IXGBE_SUCCESS) 4101 goto out; 4102 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 4103 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 4104 if (pause) 4105 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 4106 if (asm_dir) 4107 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 4108 ret_val = hw->mac.ops.write_iosf_sb_reg(hw, 4109 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 4110 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 4111 4112 /* This device does not fully support AN. */ 4113 hw->fc.disable_fc_autoneg = TRUE; 4114 break; 4115 case IXGBE_DEV_ID_X550EM_X_XFI: 4116 hw->fc.disable_fc_autoneg = TRUE; 4117 break; 4118 default: 4119 break; 4120 } 4121 4122 out: 4123 return ret_val; 4124 } 4125 4126 /** 4127 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37 4128 * @hw: pointer to hardware structure 4129 * 4130 * Enable flow control according to IEEE clause 37. 4131 **/ 4132 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw) 4133 { 4134 u32 link_s1, lp_an_page_low, an_cntl_1; 4135 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 4136 ixgbe_link_speed speed; 4137 bool link_up; 4138 4139 /* AN should have completed when the cable was plugged in. 4140 * Look for reasons to bail out. Bail out if: 4141 * - FC autoneg is disabled, or if 4142 * - link is not up. 4143 */ 4144 if (hw->fc.disable_fc_autoneg) { 4145 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 4146 "Flow control autoneg is disabled"); 4147 goto out; 4148 } 4149 4150 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 4151 if (!link_up) { 4152 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); 4153 goto out; 4154 } 4155 4156 /* Check at auto-negotiation has completed */ 4157 status = hw->mac.ops.read_iosf_sb_reg(hw, 4158 IXGBE_KRM_LINK_S1(hw->bus.lan_id), 4159 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1); 4160 4161 if (status != IXGBE_SUCCESS || 4162 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) { 4163 DEBUGOUT("Auto-Negotiation did not complete\n"); 4164 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 4165 goto out; 4166 } 4167 4168 /* Read the 10g AN autoc and LP ability registers and resolve 4169 * local flow control settings accordingly 4170 */ 4171 status = hw->mac.ops.read_iosf_sb_reg(hw, 4172 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 4173 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1); 4174 4175 if (status != IXGBE_SUCCESS) { 4176 DEBUGOUT("Auto-Negotiation did not complete\n"); 4177 goto out; 4178 } 4179 4180 status = hw->mac.ops.read_iosf_sb_reg(hw, 4181 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id), 4182 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low); 4183 4184 if (status != IXGBE_SUCCESS) { 4185 DEBUGOUT("Auto-Negotiation did not complete\n"); 4186 goto out; 4187 } 4188 4189 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low, 4190 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE, 4191 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE, 4192 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE, 4193 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE); 4194 4195 out: 4196 if (status == IXGBE_SUCCESS) { 4197 hw->fc.fc_was_autonegged = TRUE; 4198 } else { 4199 hw->fc.fc_was_autonegged = FALSE; 4200 hw->fc.current_mode = hw->fc.requested_mode; 4201 } 4202 } 4203 4204 /** 4205 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings 4206 * @hw: pointer to hardware structure 4207 * 4208 **/ 4209 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw) 4210 { 4211 hw->fc.fc_was_autonegged = FALSE; 4212 hw->fc.current_mode = hw->fc.requested_mode; 4213 } 4214 4215 /** 4216 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37 4217 * @hw: pointer to hardware structure 4218 * 4219 * Enable flow control according to IEEE clause 37. 4220 **/ 4221 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw) 4222 { 4223 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 4224 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 4225 ixgbe_link_speed speed; 4226 bool link_up; 4227 4228 /* AN should have completed when the cable was plugged in. 4229 * Look for reasons to bail out. Bail out if: 4230 * - FC autoneg is disabled, or if 4231 * - link is not up. 4232 */ 4233 if (hw->fc.disable_fc_autoneg) { 4234 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 4235 "Flow control autoneg is disabled"); 4236 goto out; 4237 } 4238 4239 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 4240 if (!link_up) { 4241 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); 4242 goto out; 4243 } 4244 4245 /* Check if auto-negotiation has completed */ 4246 status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info); 4247 if (status != IXGBE_SUCCESS || 4248 !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) { 4249 DEBUGOUT("Auto-Negotiation did not complete\n"); 4250 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 4251 goto out; 4252 } 4253 4254 /* Negotiate the flow control */ 4255 status = ixgbe_negotiate_fc(hw, info[0], info[0], 4256 FW_PHY_ACT_GET_LINK_INFO_FC_RX, 4257 FW_PHY_ACT_GET_LINK_INFO_FC_TX, 4258 FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX, 4259 FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX); 4260 4261 out: 4262 if (status == IXGBE_SUCCESS) { 4263 hw->fc.fc_was_autonegged = TRUE; 4264 } else { 4265 hw->fc.fc_was_autonegged = FALSE; 4266 hw->fc.current_mode = hw->fc.requested_mode; 4267 } 4268 } 4269 4270 /** 4271 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control 4272 * @hw: pointer to hardware structure 4273 * 4274 * Called at init time to set up flow control. 4275 **/ 4276 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw) 4277 { 4278 s32 status = IXGBE_SUCCESS; 4279 u32 an_cntl = 0; 4280 4281 DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a"); 4282 4283 /* Validate the requested mode */ 4284 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 4285 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 4286 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 4287 return IXGBE_ERR_INVALID_LINK_SETTINGS; 4288 } 4289 4290 if (hw->fc.requested_mode == ixgbe_fc_default) 4291 hw->fc.requested_mode = ixgbe_fc_full; 4292 4293 /* Set up the 1G and 10G flow control advertisement registers so the 4294 * HW will be able to do FC autoneg once the cable is plugged in. If 4295 * we link at 10G, the 1G advertisement is harmless and vice versa. 4296 */ 4297 status = hw->mac.ops.read_iosf_sb_reg(hw, 4298 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 4299 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl); 4300 4301 if (status != IXGBE_SUCCESS) { 4302 DEBUGOUT("Auto-Negotiation did not complete\n"); 4303 return status; 4304 } 4305 4306 /* The possible values of fc.requested_mode are: 4307 * 0: Flow control is completely disabled 4308 * 1: Rx flow control is enabled (we can receive pause frames, 4309 * but not send pause frames). 4310 * 2: Tx flow control is enabled (we can send pause frames but 4311 * we do not support receiving pause frames). 4312 * 3: Both Rx and Tx flow control (symmetric) are enabled. 4313 * other: Invalid. 4314 */ 4315 switch (hw->fc.requested_mode) { 4316 case ixgbe_fc_none: 4317 /* Flow control completely disabled by software override. */ 4318 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 4319 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 4320 break; 4321 case ixgbe_fc_tx_pause: 4322 /* Tx Flow control is enabled, and Rx Flow control is 4323 * disabled by software override. 4324 */ 4325 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 4326 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 4327 break; 4328 case ixgbe_fc_rx_pause: 4329 /* Rx Flow control is enabled and Tx Flow control is 4330 * disabled by software override. Since there really 4331 * isn't a way to advertise that we are capable of RX 4332 * Pause ONLY, we will advertise that we support both 4333 * symmetric and asymmetric Rx PAUSE, as such we fall 4334 * through to the fc_full statement. Later, we will 4335 * disable the adapter's ability to send PAUSE frames. 4336 */ 4337 case ixgbe_fc_full: 4338 /* Flow control (both Rx and Tx) is enabled by SW override. */ 4339 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 4340 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 4341 break; 4342 default: 4343 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 4344 "Flow control param set incorrectly\n"); 4345 return IXGBE_ERR_CONFIG; 4346 } 4347 4348 status = hw->mac.ops.write_iosf_sb_reg(hw, 4349 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 4350 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl); 4351 4352 /* Restart auto-negotiation. */ 4353 status = ixgbe_restart_an_internal_phy_x550em(hw); 4354 4355 return status; 4356 } 4357 4358 /** 4359 * ixgbe_set_mux - Set mux for port 1 access with CS4227 4360 * @hw: pointer to hardware structure 4361 * @state: set mux if 1, clear if 0 4362 */ 4363 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state) 4364 { 4365 u32 esdp; 4366 4367 if (!hw->bus.lan_id) 4368 return; 4369 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 4370 if (state) 4371 esdp |= IXGBE_ESDP_SDP1; 4372 else 4373 esdp &= ~IXGBE_ESDP_SDP1; 4374 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4375 IXGBE_WRITE_FLUSH(hw); 4376 } 4377 4378 /** 4379 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore 4380 * @hw: pointer to hardware structure 4381 * @mask: Mask to specify which semaphore to acquire 4382 * 4383 * Acquires the SWFW semaphore and sets the I2C MUX 4384 **/ 4385 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 4386 { 4387 s32 status; 4388 4389 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em"); 4390 4391 status = ixgbe_acquire_swfw_sync_X540(hw, mask); 4392 if (status) 4393 return status; 4394 4395 if (mask & IXGBE_GSSR_I2C_MASK) 4396 ixgbe_set_mux(hw, 1); 4397 4398 return IXGBE_SUCCESS; 4399 } 4400 4401 /** 4402 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore 4403 * @hw: pointer to hardware structure 4404 * @mask: Mask to specify which semaphore to release 4405 * 4406 * Releases the SWFW semaphore and sets the I2C MUX 4407 **/ 4408 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 4409 { 4410 DEBUGFUNC("ixgbe_release_swfw_sync_X550em"); 4411 4412 if (mask & IXGBE_GSSR_I2C_MASK) 4413 ixgbe_set_mux(hw, 0); 4414 4415 ixgbe_release_swfw_sync_X540(hw, mask); 4416 } 4417 4418 /** 4419 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore 4420 * @hw: pointer to hardware structure 4421 * @mask: Mask to specify which semaphore to acquire 4422 * 4423 * Acquires the SWFW semaphore and get the shared phy token as needed 4424 */ 4425 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask) 4426 { 4427 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 4428 int retries = FW_PHY_TOKEN_RETRIES; 4429 s32 status = IXGBE_SUCCESS; 4430 4431 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a"); 4432 4433 while (--retries) { 4434 status = IXGBE_SUCCESS; 4435 if (hmask) 4436 status = ixgbe_acquire_swfw_sync_X540(hw, hmask); 4437 if (status) { 4438 DEBUGOUT1("Could not acquire SWFW semaphore, Status = %d\n", 4439 status); 4440 return status; 4441 } 4442 if (!(mask & IXGBE_GSSR_TOKEN_SM)) 4443 return IXGBE_SUCCESS; 4444 4445 status = ixgbe_get_phy_token(hw); 4446 if (status == IXGBE_ERR_TOKEN_RETRY) 4447 DEBUGOUT1("Could not acquire PHY token, Status = %d\n", 4448 status); 4449 4450 if (status == IXGBE_SUCCESS) 4451 return IXGBE_SUCCESS; 4452 4453 if (hmask) 4454 ixgbe_release_swfw_sync_X540(hw, hmask); 4455 4456 if (status != IXGBE_ERR_TOKEN_RETRY) { 4457 DEBUGOUT1("Unable to retry acquiring the PHY token, Status = %d\n", 4458 status); 4459 return status; 4460 } 4461 } 4462 4463 DEBUGOUT1("Semaphore acquisition retries failed!: PHY ID = 0x%08X\n", 4464 hw->phy.id); 4465 return status; 4466 } 4467 4468 /** 4469 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore 4470 * @hw: pointer to hardware structure 4471 * @mask: Mask to specify which semaphore to release 4472 * 4473 * Releases the SWFW semaphore and puts the shared phy token as needed 4474 */ 4475 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask) 4476 { 4477 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 4478 4479 DEBUGFUNC("ixgbe_release_swfw_sync_X550a"); 4480 4481 if (mask & IXGBE_GSSR_TOKEN_SM) 4482 ixgbe_put_phy_token(hw); 4483 4484 if (hmask) 4485 ixgbe_release_swfw_sync_X540(hw, hmask); 4486 } 4487 4488 /** 4489 * ixgbe_read_phy_reg_x550a - Reads specified PHY register 4490 * @hw: pointer to hardware structure 4491 * @reg_addr: 32 bit address of PHY register to read 4492 * @phy_data: Pointer to read data from PHY register 4493 * 4494 * Reads a value from a specified PHY register using the SWFW lock and PHY 4495 * Token. The PHY Token is needed since the MDIO is shared between to MAC 4496 * instances. 4497 **/ 4498 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 4499 u32 device_type, u16 *phy_data) 4500 { 4501 s32 status; 4502 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 4503 4504 DEBUGFUNC("ixgbe_read_phy_reg_x550a"); 4505 4506 if (hw->mac.ops.acquire_swfw_sync(hw, mask)) 4507 return IXGBE_ERR_SWFW_SYNC; 4508 4509 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 4510 4511 hw->mac.ops.release_swfw_sync(hw, mask); 4512 4513 return status; 4514 } 4515 4516 /** 4517 * ixgbe_write_phy_reg_x550a - Writes specified PHY register 4518 * @hw: pointer to hardware structure 4519 * @reg_addr: 32 bit PHY register to write 4520 * @device_type: 5 bit device type 4521 * @phy_data: Data to write to the PHY register 4522 * 4523 * Writes a value to specified PHY register using the SWFW lock and PHY Token. 4524 * The PHY Token is needed since the MDIO is shared between to MAC instances. 4525 **/ 4526 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 4527 u32 device_type, u16 phy_data) 4528 { 4529 s32 status; 4530 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 4531 4532 DEBUGFUNC("ixgbe_write_phy_reg_x550a"); 4533 4534 if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) { 4535 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, 4536 phy_data); 4537 hw->mac.ops.release_swfw_sync(hw, mask); 4538 } else { 4539 status = IXGBE_ERR_SWFW_SYNC; 4540 } 4541 4542 return status; 4543 } 4544 4545 /** 4546 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt 4547 * @hw: pointer to hardware structure 4548 * 4549 * Handle external Base T PHY interrupt. If high temperature 4550 * failure alarm then return error, else if link status change 4551 * then setup internal/external PHY link 4552 * 4553 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 4554 * failure alarm, else return PHY access status. 4555 */ 4556 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw) 4557 { 4558 bool lsc; 4559 u32 status; 4560 4561 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 4562 4563 if (status != IXGBE_SUCCESS) 4564 return status; 4565 4566 if (lsc) 4567 return ixgbe_setup_internal_phy(hw); 4568 4569 return IXGBE_SUCCESS; 4570 } 4571 4572 /** 4573 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed 4574 * @hw: pointer to hardware structure 4575 * @speed: new link speed 4576 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 4577 * 4578 * Setup internal/external PHY link speed based on link speed, then set 4579 * external PHY auto advertised link speed. 4580 * 4581 * Returns error status for any failure 4582 **/ 4583 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, 4584 ixgbe_link_speed speed, 4585 bool autoneg_wait_to_complete) 4586 { 4587 s32 status; 4588 ixgbe_link_speed force_speed; 4589 4590 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em"); 4591 4592 /* Setup internal/external PHY link speed to iXFI (10G), unless 4593 * only 1G is auto advertised then setup KX link. 4594 */ 4595 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 4596 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 4597 else 4598 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 4599 4600 /* If X552 and internal link mode is XFI, then setup XFI internal link. 4601 */ 4602 if (hw->mac.type == ixgbe_mac_X550EM_x && 4603 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 4604 status = ixgbe_setup_ixfi_x550em(hw, &force_speed); 4605 4606 if (status != IXGBE_SUCCESS) 4607 return status; 4608 } 4609 4610 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); 4611 } 4612 4613 /** 4614 * ixgbe_check_link_t_X550em - Determine link and speed status 4615 * @hw: pointer to hardware structure 4616 * @speed: pointer to link speed 4617 * @link_up: TRUE when link is up 4618 * @link_up_wait_to_complete: bool used to wait for link up or not 4619 * 4620 * Check that both the MAC and X557 external PHY have link. 4621 **/ 4622 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4623 bool *link_up, bool link_up_wait_to_complete) 4624 { 4625 u32 status; 4626 u16 i, autoneg_status = 0; 4627 4628 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 4629 return IXGBE_ERR_CONFIG; 4630 4631 status = ixgbe_check_mac_link_generic(hw, speed, link_up, 4632 link_up_wait_to_complete); 4633 4634 /* If check link fails or MAC link is not up, then return */ 4635 if (status != IXGBE_SUCCESS || !(*link_up)) 4636 return status; 4637 4638 /* MAC link is up, so check external PHY link. 4639 * X557 PHY. Link status is latching low, and can only be used to detect 4640 * link drop, and not the current status of the link without performing 4641 * back-to-back reads. 4642 */ 4643 for (i = 0; i < 2; i++) { 4644 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 4645 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 4646 &autoneg_status); 4647 4648 if (status != IXGBE_SUCCESS) 4649 return status; 4650 } 4651 4652 /* If external PHY link is not up, then indicate link not up */ 4653 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) 4654 *link_up = FALSE; 4655 4656 return IXGBE_SUCCESS; 4657 } 4658 4659 /** 4660 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI 4661 * @hw: pointer to hardware structure 4662 **/ 4663 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw) 4664 { 4665 s32 status; 4666 4667 status = ixgbe_reset_phy_generic(hw); 4668 4669 if (status != IXGBE_SUCCESS) 4670 return status; 4671 4672 /* Configure Link Status Alarm and Temperature Threshold interrupts */ 4673 return ixgbe_enable_lasi_ext_t_x550em(hw); 4674 } 4675 4676 /** 4677 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs. 4678 * @hw: pointer to hardware structure 4679 * @led_idx: led number to turn on 4680 **/ 4681 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx) 4682 { 4683 u16 phy_data; 4684 4685 DEBUGFUNC("ixgbe_led_on_t_X550em"); 4686 4687 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 4688 return IXGBE_ERR_PARAM; 4689 4690 /* To turn on the LED, set mode to ON. */ 4691 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 4692 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data); 4693 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK; 4694 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 4695 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data); 4696 4697 /* Some designs have the LEDs wired to the MAC */ 4698 return ixgbe_led_on_generic(hw, led_idx); 4699 } 4700 4701 /** 4702 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs. 4703 * @hw: pointer to hardware structure 4704 * @led_idx: led number to turn off 4705 **/ 4706 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx) 4707 { 4708 u16 phy_data; 4709 4710 DEBUGFUNC("ixgbe_led_off_t_X550em"); 4711 4712 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 4713 return IXGBE_ERR_PARAM; 4714 4715 /* To turn on the LED, set mode to ON. */ 4716 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 4717 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data); 4718 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK; 4719 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 4720 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data); 4721 4722 /* Some designs have the LEDs wired to the MAC */ 4723 return ixgbe_led_off_generic(hw, led_idx); 4724 } 4725 4726 /** 4727 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware 4728 * @hw: pointer to the HW structure 4729 * @maj: driver version major number 4730 * @min: driver version minor number 4731 * @build: driver version build number 4732 * @sub: driver version sub build number 4733 * @len: length of driver_ver string 4734 * @driver_ver: driver string 4735 * 4736 * Sends driver version number to firmware through the manageability 4737 * block. On success return IXGBE_SUCCESS 4738 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 4739 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4740 **/ 4741 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min, 4742 u8 build, u8 sub, u16 len, const char *driver_ver) 4743 { 4744 struct ixgbe_hic_drv_info2 fw_cmd; 4745 s32 ret_val = IXGBE_SUCCESS; 4746 int i; 4747 4748 DEBUGFUNC("ixgbe_set_fw_drv_ver_x550"); 4749 4750 if ((len == 0) || (driver_ver == NULL) || 4751 (len > sizeof(fw_cmd.driver_string))) 4752 return IXGBE_ERR_INVALID_ARGUMENT; 4753 4754 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 4755 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len; 4756 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 4757 fw_cmd.port_num = (u8)hw->bus.func; 4758 fw_cmd.ver_maj = maj; 4759 fw_cmd.ver_min = min; 4760 fw_cmd.ver_build = build; 4761 fw_cmd.ver_sub = sub; 4762 fw_cmd.hdr.checksum = 0; 4763 memcpy(fw_cmd.driver_string, driver_ver, len); 4764 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 4765 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 4766 4767 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 4768 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 4769 sizeof(fw_cmd), 4770 IXGBE_HI_COMMAND_TIMEOUT, 4771 TRUE); 4772 if (ret_val != IXGBE_SUCCESS) 4773 continue; 4774 4775 if (fw_cmd.hdr.cmd_or_resp.ret_status == 4776 FW_CEM_RESP_STATUS_SUCCESS) 4777 ret_val = IXGBE_SUCCESS; 4778 else 4779 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4780 4781 break; 4782 } 4783 4784 return ret_val; 4785 } 4786
Indexes created Mon Sep 29 21:09:56 GMT 2025