ixgbe_x550.c revision 1.9
1 /****************************************************************************** 2 3 Copyright (c) 2001-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x550.c 320688 2017-07-05 17:27:03Z erj $*/ 34 35 #include "ixgbe_x550.h" 36 #include "ixgbe_x540.h" 37 #include "ixgbe_type.h" 38 #include "ixgbe_api.h" 39 #include "ixgbe_common.h" 40 #include "ixgbe_phy.h" 41 #include <dev/mii/mii.h> 42 43 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed); 44 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask); 45 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask); 46 static s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw); 47 48 /** 49 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type 50 * @hw: pointer to hardware structure 51 * 52 * Initialize the function pointers and assign the MAC type for X550. 53 * Does not touch the hardware. 54 **/ 55 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw) 56 { 57 struct ixgbe_mac_info *mac = &hw->mac; 58 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 59 s32 ret_val; 60 61 DEBUGFUNC("ixgbe_init_ops_X550"); 62 63 ret_val = ixgbe_init_ops_X540(hw); 64 mac->ops.dmac_config = ixgbe_dmac_config_X550; 65 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550; 66 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550; 67 mac->ops.setup_eee = NULL; 68 mac->ops.set_source_address_pruning = 69 ixgbe_set_source_address_pruning_X550; 70 mac->ops.set_ethertype_anti_spoofing = 71 ixgbe_set_ethertype_anti_spoofing_X550; 72 73 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; 74 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550; 75 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550; 76 eeprom->ops.read = ixgbe_read_ee_hostif_X550; 77 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550; 78 eeprom->ops.write = ixgbe_write_ee_hostif_X550; 79 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550; 80 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550; 81 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550; 82 83 mac->ops.disable_mdd = ixgbe_disable_mdd_X550; 84 mac->ops.enable_mdd = ixgbe_enable_mdd_X550; 85 mac->ops.mdd_event = ixgbe_mdd_event_X550; 86 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550; 87 mac->ops.disable_rx = ixgbe_disable_rx_x550; 88 /* Manageability interface */ 89 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550; 90 switch (hw->device_id) { 91 case IXGBE_DEV_ID_X550EM_X_1G_T: 92 hw->mac.ops.led_on = NULL; 93 hw->mac.ops.led_off = NULL; 94 break; 95 case IXGBE_DEV_ID_X550EM_X_10G_T: 96 case IXGBE_DEV_ID_X550EM_A_10G_T: 97 hw->mac.ops.led_on = ixgbe_led_on_t_X550em; 98 hw->mac.ops.led_off = ixgbe_led_off_t_X550em; 99 break; 100 default: 101 break; 102 } 103 return ret_val; 104 } 105 106 /** 107 * ixgbe_read_cs4227 - Read CS4227 register 108 * @hw: pointer to hardware structure 109 * @reg: register number to write 110 * @value: pointer to receive value read 111 * 112 * Returns status code 113 **/ 114 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value) 115 { 116 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value); 117 } 118 119 /** 120 * ixgbe_write_cs4227 - Write CS4227 register 121 * @hw: pointer to hardware structure 122 * @reg: register number to write 123 * @value: value to write to register 124 * 125 * Returns status code 126 **/ 127 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) 128 { 129 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value); 130 } 131 132 /** 133 * ixgbe_read_pe - Read register from port expander 134 * @hw: pointer to hardware structure 135 * @reg: register number to read 136 * @value: pointer to receive read value 137 * 138 * Returns status code 139 **/ 140 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) 141 { 142 s32 status; 143 144 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value); 145 if (status != IXGBE_SUCCESS) 146 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 147 "port expander access failed with %d\n", status); 148 return status; 149 } 150 151 /** 152 * ixgbe_write_pe - Write register to port expander 153 * @hw: pointer to hardware structure 154 * @reg: register number to write 155 * @value: value to write 156 * 157 * Returns status code 158 **/ 159 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value) 160 { 161 s32 status; 162 163 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value); 164 if (status != IXGBE_SUCCESS) 165 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 166 "port expander access failed with %d\n", status); 167 return status; 168 } 169 170 /** 171 * ixgbe_reset_cs4227 - Reset CS4227 using port expander 172 * @hw: pointer to hardware structure 173 * 174 * This function assumes that the caller has acquired the proper semaphore. 175 * Returns error code 176 **/ 177 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw) 178 { 179 s32 status; 180 u32 retry; 181 u16 value; 182 u8 reg; 183 184 /* Trigger hard reset. */ 185 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 186 if (status != IXGBE_SUCCESS) 187 return status; 188 reg |= IXGBE_PE_BIT1; 189 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 190 if (status != IXGBE_SUCCESS) 191 return status; 192 193 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®); 194 if (status != IXGBE_SUCCESS) 195 return status; 196 reg &= ~IXGBE_PE_BIT1; 197 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg); 198 if (status != IXGBE_SUCCESS) 199 return status; 200 201 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 202 if (status != IXGBE_SUCCESS) 203 return status; 204 reg &= ~IXGBE_PE_BIT1; 205 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 206 if (status != IXGBE_SUCCESS) 207 return status; 208 209 usec_delay(IXGBE_CS4227_RESET_HOLD); 210 211 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 212 if (status != IXGBE_SUCCESS) 213 return status; 214 reg |= IXGBE_PE_BIT1; 215 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 216 if (status != IXGBE_SUCCESS) 217 return status; 218 219 /* Wait for the reset to complete. */ 220 msec_delay(IXGBE_CS4227_RESET_DELAY); 221 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 222 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS, 223 &value); 224 if (status == IXGBE_SUCCESS && 225 value == IXGBE_CS4227_EEPROM_LOAD_OK) 226 break; 227 msec_delay(IXGBE_CS4227_CHECK_DELAY); 228 } 229 if (retry == IXGBE_CS4227_RETRIES) { 230 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 231 "CS4227 reset did not complete."); 232 return IXGBE_ERR_PHY; 233 } 234 235 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value); 236 if (status != IXGBE_SUCCESS || 237 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) { 238 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 239 "CS4227 EEPROM did not load successfully."); 240 return IXGBE_ERR_PHY; 241 } 242 243 return IXGBE_SUCCESS; 244 } 245 246 /** 247 * ixgbe_check_cs4227 - Check CS4227 and reset as needed 248 * @hw: pointer to hardware structure 249 **/ 250 static void ixgbe_check_cs4227(struct ixgbe_hw *hw) 251 { 252 s32 status = IXGBE_SUCCESS; 253 u32 swfw_mask = hw->phy.phy_semaphore_mask; 254 u16 value = 0; 255 u8 retry; 256 257 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 258 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 259 if (status != IXGBE_SUCCESS) { 260 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 261 "semaphore failed with %d", status); 262 msec_delay(IXGBE_CS4227_CHECK_DELAY); 263 continue; 264 } 265 266 /* Get status of reset flow. */ 267 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); 268 269 if (status == IXGBE_SUCCESS && 270 value == IXGBE_CS4227_RESET_COMPLETE) 271 goto out; 272 273 if (status != IXGBE_SUCCESS || 274 value != IXGBE_CS4227_RESET_PENDING) 275 break; 276 277 /* Reset is pending. Wait and check again. */ 278 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 279 msec_delay(IXGBE_CS4227_CHECK_DELAY); 280 } 281 282 /* If still pending, assume other instance failed. */ 283 if (retry == IXGBE_CS4227_RETRIES) { 284 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 285 if (status != IXGBE_SUCCESS) { 286 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 287 "semaphore failed with %d", status); 288 return; 289 } 290 } 291 292 /* Reset the CS4227. */ 293 status = ixgbe_reset_cs4227(hw); 294 if (status != IXGBE_SUCCESS) { 295 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 296 "CS4227 reset failed: %d", status); 297 goto out; 298 } 299 300 /* Reset takes so long, temporarily release semaphore in case the 301 * other driver instance is waiting for the reset indication. 302 */ 303 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 304 IXGBE_CS4227_RESET_PENDING); 305 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 306 msec_delay(10); 307 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 308 if (status != IXGBE_SUCCESS) { 309 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 310 "semaphore failed with %d", status); 311 return; 312 } 313 314 /* Record completion for next time. */ 315 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 316 IXGBE_CS4227_RESET_COMPLETE); 317 318 out: 319 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 320 msec_delay(hw->eeprom.semaphore_delay); 321 } 322 323 /** 324 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control 325 * @hw: pointer to hardware structure 326 **/ 327 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) 328 { 329 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 330 331 if (hw->bus.lan_id) { 332 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); 333 esdp |= IXGBE_ESDP_SDP1_DIR; 334 } 335 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); 336 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 337 IXGBE_WRITE_FLUSH(hw); 338 } 339 340 /** 341 * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock 342 * @hw: pointer to hardware structure 343 * @reg_addr: 32 bit address of PHY register to read 344 * @dev_type: always unused 345 * @phy_data: Pointer to read data from PHY register 346 */ 347 static s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr, 348 u32 dev_type, u16 *phy_data) 349 { 350 u32 i, data, command; 351 UNREFERENCED_1PARAMETER(dev_type); 352 353 /* Setup and write the read command */ 354 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) | 355 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 356 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC | 357 IXGBE_MSCA_MDI_COMMAND; 358 359 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 360 361 /* Check every 10 usec to see if the access completed. 362 * The MDI Command bit will clear when the operation is 363 * complete 364 */ 365 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 366 usec_delay(10); 367 368 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 369 if (!(command & IXGBE_MSCA_MDI_COMMAND)) 370 break; 371 } 372 373 if (command & IXGBE_MSCA_MDI_COMMAND) { 374 ERROR_REPORT1(IXGBE_ERROR_POLLING, 375 "PHY read command did not complete.\n"); 376 return IXGBE_ERR_PHY; 377 } 378 379 /* Read operation is complete. Get the data from MSRWD */ 380 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 381 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 382 *phy_data = (u16)data; 383 384 return IXGBE_SUCCESS; 385 } 386 387 /** 388 * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock 389 * @hw: pointer to hardware structure 390 * @reg_addr: 32 bit PHY register to write 391 * @dev_type: always unused 392 * @phy_data: Data to write to the PHY register 393 */ 394 static s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr, 395 u32 dev_type, u16 phy_data) 396 { 397 u32 i, command; 398 UNREFERENCED_1PARAMETER(dev_type); 399 400 /* Put the data in the MDI single read and write data register*/ 401 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 402 403 /* Setup and write the write command */ 404 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) | 405 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 406 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE | 407 IXGBE_MSCA_MDI_COMMAND; 408 409 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 410 411 /* Check every 10 usec to see if the access completed. 412 * The MDI Command bit will clear when the operation is 413 * complete 414 */ 415 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 416 usec_delay(10); 417 418 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 419 if (!(command & IXGBE_MSCA_MDI_COMMAND)) 420 break; 421 } 422 423 if (command & IXGBE_MSCA_MDI_COMMAND) { 424 ERROR_REPORT1(IXGBE_ERROR_POLLING, 425 "PHY write cmd didn't complete\n"); 426 return IXGBE_ERR_PHY; 427 } 428 429 return IXGBE_SUCCESS; 430 } 431 432 /** 433 * ixgbe_identify_phy_x550em - Get PHY type based on device id 434 * @hw: pointer to hardware structure 435 * 436 * Returns error code 437 */ 438 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) 439 { 440 hw->mac.ops.set_lan_id(hw); 441 442 ixgbe_read_mng_if_sel_x550em(hw); 443 444 switch (hw->device_id) { 445 case IXGBE_DEV_ID_X550EM_A_SFP: 446 return ixgbe_identify_module_generic(hw); 447 case IXGBE_DEV_ID_X550EM_X_SFP: 448 /* set up for CS4227 usage */ 449 ixgbe_setup_mux_ctl(hw); 450 ixgbe_check_cs4227(hw); 451 /* Fallthrough */ 452 453 case IXGBE_DEV_ID_X550EM_A_SFP_N: 454 return ixgbe_identify_module_generic(hw); 455 break; 456 case IXGBE_DEV_ID_X550EM_X_KX4: 457 hw->phy.type = ixgbe_phy_x550em_kx4; 458 break; 459 case IXGBE_DEV_ID_X550EM_X_XFI: 460 hw->phy.type = ixgbe_phy_x550em_xfi; 461 break; 462 case IXGBE_DEV_ID_X550EM_X_KR: 463 case IXGBE_DEV_ID_X550EM_A_KR: 464 case IXGBE_DEV_ID_X550EM_A_KR_L: 465 hw->phy.type = ixgbe_phy_x550em_kr; 466 break; 467 case IXGBE_DEV_ID_X550EM_A_10G_T: 468 case IXGBE_DEV_ID_X550EM_X_10G_T: 469 return ixgbe_identify_phy_generic(hw); 470 case IXGBE_DEV_ID_X550EM_X_1G_T: 471 hw->phy.type = ixgbe_phy_ext_1g_t; 472 break; 473 case IXGBE_DEV_ID_X550EM_A_1G_T: 474 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 475 hw->phy.type = ixgbe_phy_fw; 476 if (hw->bus.lan_id) 477 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; 478 else 479 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; 480 break; 481 default: 482 break; 483 } 484 return IXGBE_SUCCESS; 485 } 486 487 /** 488 * ixgbe_fw_phy_activity - Perform an activity on a PHY 489 * @hw: pointer to hardware structure 490 * @activity: activity to perform 491 * @data: Pointer to 4 32-bit words of data 492 */ 493 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity, 494 u32 (*data)[FW_PHY_ACT_DATA_COUNT]) 495 { 496 union { 497 struct ixgbe_hic_phy_activity_req cmd; 498 struct ixgbe_hic_phy_activity_resp rsp; 499 } hic; 500 u16 retries = FW_PHY_ACT_RETRIES; 501 s32 rc; 502 u16 i; 503 504 do { 505 memset(&hic, 0, sizeof(hic)); 506 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD; 507 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN; 508 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 509 hic.cmd.port_number = hw->bus.lan_id; 510 hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity); 511 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i) 512 hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]); 513 514 rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd, 515 sizeof(hic.cmd), 516 IXGBE_HI_COMMAND_TIMEOUT, 517 TRUE); 518 if (rc != IXGBE_SUCCESS) 519 return rc; 520 if (hic.rsp.hdr.cmd_or_resp.ret_status == 521 FW_CEM_RESP_STATUS_SUCCESS) { 522 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i) 523 (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]); 524 return IXGBE_SUCCESS; 525 } 526 usec_delay(20); 527 --retries; 528 } while (retries > 0); 529 530 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 531 } 532 533 static const struct { 534 u16 fw_speed; 535 ixgbe_link_speed phy_speed; 536 } ixgbe_fw_map[] = { 537 { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL }, 538 { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL }, 539 { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL }, 540 { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL }, 541 { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL }, 542 { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL }, 543 }; 544 545 /** 546 * ixgbe_get_phy_id_fw - Get the phy ID via firmware command 547 * @hw: pointer to hardware structure 548 * 549 * Returns error code 550 */ 551 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw) 552 { 553 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 554 u16 phy_speeds; 555 u16 phy_id_lo; 556 s32 rc; 557 u16 i; 558 559 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info); 560 if (rc) 561 return rc; 562 563 hw->phy.speeds_supported = 0; 564 phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK; 565 for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) { 566 if (phy_speeds & ixgbe_fw_map[i].fw_speed) 567 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed; 568 } 569 if (!hw->phy.autoneg_advertised) 570 hw->phy.autoneg_advertised = hw->phy.speeds_supported; 571 572 hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK; 573 phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK; 574 hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK; 575 hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK; 576 if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK) 577 return IXGBE_ERR_PHY_ADDR_INVALID; 578 return IXGBE_SUCCESS; 579 } 580 581 /** 582 * ixgbe_identify_phy_fw - Get PHY type based on firmware command 583 * @hw: pointer to hardware structure 584 * 585 * Returns error code 586 */ 587 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw) 588 { 589 if (hw->bus.lan_id) 590 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 591 else 592 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 593 594 hw->phy.type = ixgbe_phy_fw; 595 hw->phy.ops.read_reg = NULL; 596 hw->phy.ops.write_reg = NULL; 597 return ixgbe_get_phy_id_fw(hw); 598 } 599 600 /** 601 * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY 602 * @hw: pointer to hardware structure 603 * 604 * Returns error code 605 */ 606 s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw) 607 { 608 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 609 610 setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF; 611 return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup); 612 } 613 614 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 615 u32 device_type, u16 *phy_data) 616 { 617 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data); 618 return IXGBE_NOT_IMPLEMENTED; 619 } 620 621 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 622 u32 device_type, u16 phy_data) 623 { 624 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data); 625 return IXGBE_NOT_IMPLEMENTED; 626 } 627 628 /** 629 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 630 * @hw: pointer to the hardware structure 631 * @addr: I2C bus address to read from 632 * @reg: I2C device register to read from 633 * @val: pointer to location to receive read value 634 * 635 * Returns an error code on error. 636 **/ 637 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 638 u16 reg, u16 *val) 639 { 640 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, TRUE); 641 } 642 643 /** 644 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation 645 * @hw: pointer to the hardware structure 646 * @addr: I2C bus address to read from 647 * @reg: I2C device register to read from 648 * @val: pointer to location to receive read value 649 * 650 * Returns an error code on error. 651 **/ 652 static s32 653 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, 654 u16 reg, u16 *val) 655 { 656 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, FALSE); 657 } 658 659 /** 660 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 661 * @hw: pointer to the hardware structure 662 * @addr: I2C bus address to write to 663 * @reg: I2C device register to write to 664 * @val: value to write 665 * 666 * Returns an error code on error. 667 **/ 668 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 669 u8 addr, u16 reg, u16 val) 670 { 671 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, TRUE); 672 } 673 674 /** 675 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation 676 * @hw: pointer to the hardware structure 677 * @addr: I2C bus address to write to 678 * @reg: I2C device register to write to 679 * @val: value to write 680 * 681 * Returns an error code on error. 682 **/ 683 static s32 684 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, 685 u8 addr, u16 reg, u16 val) 686 { 687 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, FALSE); 688 } 689 690 /** 691 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type 692 * @hw: pointer to hardware structure 693 * 694 * Initialize the function pointers and for MAC type X550EM. 695 * Does not touch the hardware. 696 **/ 697 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw) 698 { 699 struct ixgbe_mac_info *mac = &hw->mac; 700 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 701 struct ixgbe_phy_info *phy = &hw->phy; 702 s32 ret_val; 703 704 DEBUGFUNC("ixgbe_init_ops_X550EM"); 705 706 /* Similar to X550 so start there. */ 707 ret_val = ixgbe_init_ops_X550(hw); 708 709 /* Since this function eventually calls 710 * ixgbe_init_ops_540 by design, we are setting 711 * the pointers to NULL explicitly here to overwrite 712 * the values being set in the x540 function. 713 */ 714 715 /* Bypass not supported in x550EM */ 716 mac->ops.bypass_rw = NULL; 717 mac->ops.bypass_valid_rd = NULL; 718 mac->ops.bypass_set = NULL; 719 mac->ops.bypass_rd_eep = NULL; 720 721 /* FCOE not supported in x550EM */ 722 mac->ops.get_san_mac_addr = NULL; 723 mac->ops.set_san_mac_addr = NULL; 724 mac->ops.get_wwn_prefix = NULL; 725 mac->ops.get_fcoe_boot_status = NULL; 726 727 /* IPsec not supported in x550EM */ 728 mac->ops.disable_sec_rx_path = NULL; 729 mac->ops.enable_sec_rx_path = NULL; 730 731 /* AUTOC register is not present in x550EM. */ 732 mac->ops.prot_autoc_read = NULL; 733 mac->ops.prot_autoc_write = NULL; 734 735 /* X550EM bus type is internal*/ 736 hw->bus.type = ixgbe_bus_type_internal; 737 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em; 738 739 740 mac->ops.get_media_type = ixgbe_get_media_type_X550em; 741 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em; 742 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em; 743 mac->ops.reset_hw = ixgbe_reset_hw_X550em; 744 mac->ops.get_supported_physical_layer = 745 ixgbe_get_supported_physical_layer_X550em; 746 747 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) 748 mac->ops.setup_fc = ixgbe_setup_fc_generic; 749 else 750 mac->ops.setup_fc = ixgbe_setup_fc_X550em; 751 752 /* PHY */ 753 phy->ops.init = ixgbe_init_phy_ops_X550em; 754 switch (hw->device_id) { 755 case IXGBE_DEV_ID_X550EM_A_1G_T: 756 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 757 mac->ops.setup_fc = NULL; 758 phy->ops.identify = ixgbe_identify_phy_fw; 759 phy->ops.set_phy_power = NULL; 760 phy->ops.get_firmware_version = NULL; 761 break; 762 case IXGBE_DEV_ID_X550EM_X_1G_T: 763 mac->ops.setup_fc = NULL; 764 phy->ops.identify = ixgbe_identify_phy_x550em; 765 phy->ops.set_phy_power = NULL; 766 break; 767 default: 768 phy->ops.identify = ixgbe_identify_phy_x550em; 769 } 770 771 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 772 phy->ops.set_phy_power = NULL; 773 774 775 /* EEPROM */ 776 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540; 777 eeprom->ops.read = ixgbe_read_ee_hostif_X550; 778 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550; 779 eeprom->ops.write = ixgbe_write_ee_hostif_X550; 780 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550; 781 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550; 782 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550; 783 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550; 784 785 return ret_val; 786 } 787 788 #define IXGBE_DENVERTON_WA 1 789 790 /** 791 * ixgbe_setup_fw_link - Setup firmware-controlled PHYs 792 * @hw: pointer to hardware structure 793 */ 794 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw) 795 { 796 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 797 s32 rc; 798 #ifdef IXGBE_DENVERTON_WA 799 s32 ret_val; 800 u16 phydata; 801 #endif 802 u16 i; 803 804 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 805 return 0; 806 807 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 808 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 809 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 810 return IXGBE_ERR_INVALID_LINK_SETTINGS; 811 } 812 813 switch (hw->fc.requested_mode) { 814 case ixgbe_fc_full: 815 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX << 816 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 817 break; 818 case ixgbe_fc_rx_pause: 819 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX << 820 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 821 break; 822 case ixgbe_fc_tx_pause: 823 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX << 824 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 825 break; 826 default: 827 break; 828 } 829 830 for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) { 831 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed) 832 setup[0] |= ixgbe_fw_map[i].fw_speed; 833 } 834 setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN; 835 836 if (hw->phy.eee_speeds_advertised) 837 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE; 838 839 #ifdef IXGBE_DENVERTON_WA 840 /* Don't use auto-nego for 10/100Mbps */ 841 if ((hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_100_FULL) 842 || (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_10_FULL)) { 843 setup[0] &= ~FW_PHY_ACT_SETUP_LINK_AN; 844 setup[0] &= ~FW_PHY_ACT_SETUP_LINK_EEE; 845 setup[0] &= ~(FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX 846 << FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT); 847 } 848 #endif 849 850 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup); 851 if (rc) 852 return rc; 853 854 #ifdef IXGBE_DENVERTON_WA 855 ret_val = ixgbe_read_phy_reg_x550a(hw, MII_BMCR, 0, &phydata); 856 if (ret_val != 0) 857 goto out; 858 859 /* 860 * Broken firmware sets BMCR register incorrectly if 861 * FW_PHY_ACT_SETUP_LINK_AN isn't set. 862 * a) FDX may not be set. 863 * b) BMCR_SPEED1 (bit 6) is always cleard. 864 * + -------+------+-----------+-----+--------------------------+ 865 * |request | BMCR | BMCR spd | BMCR | | 866 * | | (HEX)| (in bits)| FDX | | 867 * +--------+------+----------+------+--------------------------+ 868 * | 10M | 0000 | 10M(00) | 0 | | 869 * | 10M | 2000 | 100M(01) | 0 |(I've never observed this)| 870 * | 10M | 2100 | 100M(01) | 1 | | 871 * | 100M | 0000 | 10M(00) | 0 | | 872 * | 100M | 0100 | 10M(00) | 1 | | 873 * +--------------------------+------+--------------------------+ 874 */ 875 if (((hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_100_FULL) 876 && (((phydata & BMCR_FDX) == 0) || (BMCR_SPEED(phydata) == 0))) 877 || ((hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_10_FULL) 878 && (((phydata & BMCR_FDX) == 0) 879 || (BMCR_SPEED(phydata) != BMCR_S10)))) { 880 phydata = BMCR_FDX; 881 switch (hw->phy.autoneg_advertised) { 882 case IXGBE_LINK_SPEED_10_FULL: 883 phydata |= BMCR_S10; 884 break; 885 case IXGBE_LINK_SPEED_100_FULL: 886 phydata |= BMCR_S100; 887 break; 888 case IXGBE_LINK_SPEED_1GB_FULL: 889 panic("%s: 1GB_FULL is set", __func__); 890 break; 891 default: 892 break; 893 } 894 ret_val = ixgbe_write_phy_reg_x550a(hw, MII_BMCR, 0, phydata); 895 if (ret_val != 0) 896 return ret_val; 897 } 898 out: 899 #endif 900 if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN) 901 return IXGBE_ERR_OVERTEMP; 902 return IXGBE_SUCCESS; 903 } 904 905 /** 906 * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs 907 * @hw: pointer to hardware structure 908 * 909 * Called at init time to set up flow control. 910 */ 911 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw) 912 { 913 if (hw->fc.requested_mode == ixgbe_fc_default) 914 hw->fc.requested_mode = ixgbe_fc_full; 915 916 return ixgbe_setup_fw_link(hw); 917 } 918 919 /** 920 * ixgbe_setup_eee_fw - Enable/disable EEE support 921 * @hw: pointer to the HW structure 922 * @enable_eee: boolean flag to enable EEE 923 * 924 * Enable/disable EEE based on enable_eee flag. 925 * This function controls EEE for firmware-based PHY implementations. 926 */ 927 static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee) 928 { 929 if (!!hw->phy.eee_speeds_advertised == enable_eee) 930 return IXGBE_SUCCESS; 931 if (enable_eee) 932 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported; 933 else 934 hw->phy.eee_speeds_advertised = 0; 935 return hw->phy.ops.setup_link(hw); 936 } 937 938 /** 939 * ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type 940 * @hw: pointer to hardware structure 941 * 942 * Initialize the function pointers and for MAC type X550EM_a. 943 * Does not touch the hardware. 944 **/ 945 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw) 946 { 947 struct ixgbe_mac_info *mac = &hw->mac; 948 s32 ret_val; 949 950 DEBUGFUNC("ixgbe_init_ops_X550EM_a"); 951 952 /* Start with generic X550EM init */ 953 ret_val = ixgbe_init_ops_X550EM(hw); 954 955 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII || 956 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) { 957 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550; 958 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550; 959 } else { 960 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a; 961 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a; 962 } 963 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a; 964 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a; 965 966 switch (mac->ops.get_media_type(hw)) { 967 case ixgbe_media_type_fiber: 968 mac->ops.setup_fc = NULL; 969 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a; 970 break; 971 case ixgbe_media_type_backplane: 972 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a; 973 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a; 974 break; 975 default: 976 break; 977 } 978 979 switch (hw->device_id) { 980 case IXGBE_DEV_ID_X550EM_A_1G_T: 981 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 982 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a; 983 mac->ops.setup_fc = ixgbe_fc_autoneg_fw; 984 mac->ops.setup_eee = ixgbe_setup_eee_fw; 985 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL | 986 IXGBE_LINK_SPEED_1GB_FULL; 987 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported; 988 break; 989 default: 990 break; 991 } 992 993 return ret_val; 994 } 995 996 /** 997 * ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type 998 * @hw: pointer to hardware structure 999 * 1000 * Initialize the function pointers and for MAC type X550EM_x. 1001 * Does not touch the hardware. 1002 **/ 1003 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw) 1004 { 1005 struct ixgbe_mac_info *mac = &hw->mac; 1006 struct ixgbe_link_info *link = &hw->link; 1007 s32 ret_val; 1008 1009 DEBUGFUNC("ixgbe_init_ops_X550EM_x"); 1010 1011 /* Start with generic X550EM init */ 1012 ret_val = ixgbe_init_ops_X550EM(hw); 1013 1014 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550; 1015 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550; 1016 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em; 1017 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em; 1018 link->ops.read_link = ixgbe_read_i2c_combined_generic; 1019 link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked; 1020 link->ops.write_link = ixgbe_write_i2c_combined_generic; 1021 link->ops.write_link_unlocked = 1022 ixgbe_write_i2c_combined_generic_unlocked; 1023 link->addr = IXGBE_CS4227; 1024 1025 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) { 1026 mac->ops.setup_fc = NULL; 1027 mac->ops.setup_eee = NULL; 1028 mac->ops.init_led_link_act = NULL; 1029 } 1030 1031 return ret_val; 1032 } 1033 1034 /** 1035 * ixgbe_dmac_config_X550 1036 * @hw: pointer to hardware structure 1037 * 1038 * Configure DMA coalescing. If enabling dmac, dmac is activated. 1039 * When disabling dmac, dmac enable dmac bit is cleared. 1040 **/ 1041 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw) 1042 { 1043 u32 reg, high_pri_tc; 1044 1045 DEBUGFUNC("ixgbe_dmac_config_X550"); 1046 1047 /* Disable DMA coalescing before configuring */ 1048 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 1049 reg &= ~IXGBE_DMACR_DMAC_EN; 1050 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 1051 1052 /* Disable DMA Coalescing if the watchdog timer is 0 */ 1053 if (!hw->mac.dmac_config.watchdog_timer) 1054 goto out; 1055 1056 ixgbe_dmac_config_tcs_X550(hw); 1057 1058 /* Configure DMA Coalescing Control Register */ 1059 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 1060 1061 /* Set the watchdog timer in units of 40.96 usec */ 1062 reg &= ~IXGBE_DMACR_DMACWT_MASK; 1063 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096; 1064 1065 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK; 1066 /* If fcoe is enabled, set high priority traffic class */ 1067 if (hw->mac.dmac_config.fcoe_en) { 1068 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc; 1069 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) & 1070 IXGBE_DMACR_HIGH_PRI_TC_MASK); 1071 } 1072 reg |= IXGBE_DMACR_EN_MNG_IND; 1073 1074 /* Enable DMA coalescing after configuration */ 1075 reg |= IXGBE_DMACR_DMAC_EN; 1076 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 1077 1078 out: 1079 return IXGBE_SUCCESS; 1080 } 1081 1082 /** 1083 * ixgbe_dmac_config_tcs_X550 1084 * @hw: pointer to hardware structure 1085 * 1086 * Configure DMA coalescing threshold per TC. The dmac enable bit must 1087 * be cleared before configuring. 1088 **/ 1089 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw) 1090 { 1091 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb; 1092 1093 DEBUGFUNC("ixgbe_dmac_config_tcs_X550"); 1094 1095 /* Configure DMA coalescing enabled */ 1096 switch (hw->mac.dmac_config.link_speed) { 1097 case IXGBE_LINK_SPEED_10_FULL: 1098 case IXGBE_LINK_SPEED_100_FULL: 1099 pb_headroom = IXGBE_DMACRXT_100M; 1100 break; 1101 case IXGBE_LINK_SPEED_1GB_FULL: 1102 pb_headroom = IXGBE_DMACRXT_1G; 1103 break; 1104 default: 1105 pb_headroom = IXGBE_DMACRXT_10G; 1106 break; 1107 } 1108 1109 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >> 1110 IXGBE_MHADD_MFS_SHIFT) / 1024); 1111 1112 /* Set the per Rx packet buffer receive threshold */ 1113 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) { 1114 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc)); 1115 reg &= ~IXGBE_DMCTH_DMACRXT_MASK; 1116 1117 if (tc < hw->mac.dmac_config.num_tcs) { 1118 /* Get Rx PB size */ 1119 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc)); 1120 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >> 1121 IXGBE_RXPBSIZE_SHIFT; 1122 1123 /* Calculate receive buffer threshold in kilobytes */ 1124 if (rx_pb_size > pb_headroom) 1125 rx_pb_size = rx_pb_size - pb_headroom; 1126 else 1127 rx_pb_size = 0; 1128 1129 /* Minimum of MFS shall be set for DMCTH */ 1130 reg |= (rx_pb_size > maxframe_size_kb) ? 1131 rx_pb_size : maxframe_size_kb; 1132 } 1133 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg); 1134 } 1135 return IXGBE_SUCCESS; 1136 } 1137 1138 /** 1139 * ixgbe_dmac_update_tcs_X550 1140 * @hw: pointer to hardware structure 1141 * 1142 * Disables dmac, updates per TC settings, and then enables dmac. 1143 **/ 1144 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw) 1145 { 1146 u32 reg; 1147 1148 DEBUGFUNC("ixgbe_dmac_update_tcs_X550"); 1149 1150 /* Disable DMA coalescing before configuring */ 1151 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 1152 reg &= ~IXGBE_DMACR_DMAC_EN; 1153 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 1154 1155 ixgbe_dmac_config_tcs_X550(hw); 1156 1157 /* Enable DMA coalescing after configuration */ 1158 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 1159 reg |= IXGBE_DMACR_DMAC_EN; 1160 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 1161 1162 return IXGBE_SUCCESS; 1163 } 1164 1165 /** 1166 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params 1167 * @hw: pointer to hardware structure 1168 * 1169 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 1170 * ixgbe_hw struct in order to set up EEPROM access. 1171 **/ 1172 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) 1173 { 1174 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1175 u32 eec; 1176 u16 eeprom_size; 1177 1178 DEBUGFUNC("ixgbe_init_eeprom_params_X550"); 1179 1180 if (eeprom->type == ixgbe_eeprom_uninitialized) { 1181 eeprom->semaphore_delay = 10; 1182 eeprom->type = ixgbe_flash; 1183 1184 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1185 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 1186 IXGBE_EEC_SIZE_SHIFT); 1187 eeprom->word_size = 1 << (eeprom_size + 1188 IXGBE_EEPROM_WORD_SIZE_SHIFT); 1189 1190 DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 1191 eeprom->type, eeprom->word_size); 1192 } 1193 1194 return IXGBE_SUCCESS; 1195 } 1196 1197 /** 1198 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning 1199 * @hw: pointer to hardware structure 1200 * @enable: enable or disable source address pruning 1201 * @pool: Rx pool to set source address pruning for 1202 **/ 1203 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable, 1204 unsigned int pool) 1205 { 1206 u64 pfflp; 1207 1208 /* max rx pool is 63 */ 1209 if (pool > 63) 1210 return; 1211 1212 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL); 1213 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32; 1214 1215 if (enable) 1216 pfflp |= (1ULL << pool); 1217 else 1218 pfflp &= ~(1ULL << pool); 1219 1220 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); 1221 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); 1222 } 1223 1224 /** 1225 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing 1226 * @hw: pointer to hardware structure 1227 * @enable: enable or disable switch for Ethertype anti-spoofing 1228 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1229 * 1230 **/ 1231 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, 1232 bool enable, int vf) 1233 { 1234 int vf_target_reg = vf >> 3; 1235 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT; 1236 u32 pfvfspoof; 1237 1238 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550"); 1239 1240 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 1241 if (enable) 1242 pfvfspoof |= (1 << vf_target_shift); 1243 else 1244 pfvfspoof &= ~(1 << vf_target_shift); 1245 1246 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 1247 } 1248 1249 /** 1250 * ixgbe_iosf_wait - Wait for IOSF command completion 1251 * @hw: pointer to hardware structure 1252 * @ctrl: pointer to location to receive final IOSF control value 1253 * 1254 * Returns failing status on timeout 1255 * 1256 * Note: ctrl can be NULL if the IOSF control register value is not needed 1257 **/ 1258 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) 1259 { 1260 u32 i, command = 0; 1261 1262 /* Check every 10 usec to see if the address cycle completed. 1263 * The SB IOSF BUSY bit will clear when the operation is 1264 * complete 1265 */ 1266 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 1267 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); 1268 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0) 1269 break; 1270 usec_delay(10); 1271 } 1272 if (ctrl) 1273 *ctrl = command; 1274 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { 1275 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n"); 1276 return IXGBE_ERR_PHY; 1277 } 1278 1279 return IXGBE_SUCCESS; 1280 } 1281 1282 /** 1283 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register 1284 * of the IOSF device 1285 * @hw: pointer to hardware structure 1286 * @reg_addr: 32 bit PHY register to write 1287 * @device_type: 3 bit device type 1288 * @data: Data to write to the register 1289 **/ 1290 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 1291 u32 device_type, u32 data) 1292 { 1293 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 1294 u32 command, error __unused; 1295 s32 ret; 1296 1297 ret = ixgbe_acquire_swfw_semaphore(hw, gssr); 1298 if (ret != IXGBE_SUCCESS) 1299 return ret; 1300 1301 ret = ixgbe_iosf_wait(hw, NULL); 1302 if (ret != IXGBE_SUCCESS) 1303 goto out; 1304 1305 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 1306 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 1307 1308 /* Write IOSF control register */ 1309 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 1310 1311 /* Write IOSF data register */ 1312 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); 1313 1314 ret = ixgbe_iosf_wait(hw, &command); 1315 1316 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 1317 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 1318 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 1319 ERROR_REPORT2(IXGBE_ERROR_POLLING, 1320 "Failed to write, error %x\n", error); 1321 ret = IXGBE_ERR_PHY; 1322 } 1323 1324 out: 1325 ixgbe_release_swfw_semaphore(hw, gssr); 1326 return ret; 1327 } 1328 1329 /** 1330 * ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device 1331 * @hw: pointer to hardware structure 1332 * @reg_addr: 32 bit PHY register to write 1333 * @device_type: 3 bit device type 1334 * @data: Pointer to read data from the register 1335 **/ 1336 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 1337 u32 device_type, u32 *data) 1338 { 1339 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 1340 u32 command, error __unused; 1341 s32 ret; 1342 1343 ret = ixgbe_acquire_swfw_semaphore(hw, gssr); 1344 if (ret != IXGBE_SUCCESS) 1345 return ret; 1346 1347 ret = ixgbe_iosf_wait(hw, NULL); 1348 if (ret != IXGBE_SUCCESS) 1349 goto out; 1350 1351 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 1352 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 1353 1354 /* Write IOSF control register */ 1355 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 1356 1357 ret = ixgbe_iosf_wait(hw, &command); 1358 1359 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 1360 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 1361 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 1362 ERROR_REPORT2(IXGBE_ERROR_POLLING, 1363 "Failed to read, error %x\n", error); 1364 ret = IXGBE_ERR_PHY; 1365 } 1366 1367 if (ret == IXGBE_SUCCESS) 1368 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); 1369 1370 out: 1371 ixgbe_release_swfw_semaphore(hw, gssr); 1372 return ret; 1373 } 1374 1375 /** 1376 * ixgbe_get_phy_token - Get the token for shared phy access 1377 * @hw: Pointer to hardware structure 1378 */ 1379 1380 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw) 1381 { 1382 struct ixgbe_hic_phy_token_req token_cmd; 1383 s32 status; 1384 1385 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 1386 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 1387 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 1388 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1389 token_cmd.port_number = hw->bus.lan_id; 1390 token_cmd.command_type = FW_PHY_TOKEN_REQ; 1391 token_cmd.pad = 0; 1392 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd, 1393 sizeof(token_cmd), 1394 IXGBE_HI_COMMAND_TIMEOUT, 1395 TRUE); 1396 if (status) { 1397 DEBUGOUT1("Issuing host interface command failed with Status = %d\n", 1398 status); 1399 return status; 1400 } 1401 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 1402 return IXGBE_SUCCESS; 1403 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) { 1404 DEBUGOUT1("Host interface command returned 0x%08x , returning IXGBE_ERR_FW_RESP_INVALID\n", 1405 token_cmd.hdr.cmd_or_resp.ret_status); 1406 return IXGBE_ERR_FW_RESP_INVALID; 1407 } 1408 1409 DEBUGOUT("Returning IXGBE_ERR_TOKEN_RETRY\n"); 1410 return IXGBE_ERR_TOKEN_RETRY; 1411 } 1412 1413 /** 1414 * ixgbe_put_phy_token - Put the token for shared phy access 1415 * @hw: Pointer to hardware structure 1416 */ 1417 1418 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw) 1419 { 1420 struct ixgbe_hic_phy_token_req token_cmd; 1421 s32 status; 1422 1423 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 1424 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 1425 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 1426 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1427 token_cmd.port_number = hw->bus.lan_id; 1428 token_cmd.command_type = FW_PHY_TOKEN_REL; 1429 token_cmd.pad = 0; 1430 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd, 1431 sizeof(token_cmd), 1432 IXGBE_HI_COMMAND_TIMEOUT, 1433 TRUE); 1434 if (status) 1435 return status; 1436 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 1437 return IXGBE_SUCCESS; 1438 1439 DEBUGOUT("Put PHY Token host interface command failed"); 1440 return IXGBE_ERR_FW_RESP_INVALID; 1441 } 1442 1443 /** 1444 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register 1445 * of the IOSF device 1446 * @hw: pointer to hardware structure 1447 * @reg_addr: 32 bit PHY register to write 1448 * @device_type: 3 bit device type 1449 * @data: Data to write to the register 1450 **/ 1451 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 1452 u32 device_type, u32 data) 1453 { 1454 struct ixgbe_hic_internal_phy_req write_cmd; 1455 s32 status; 1456 UNREFERENCED_1PARAMETER(device_type); 1457 1458 memset(&write_cmd, 0, sizeof(write_cmd)); 1459 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 1460 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 1461 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1462 write_cmd.port_number = hw->bus.lan_id; 1463 write_cmd.command_type = FW_INT_PHY_REQ_WRITE; 1464 write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr); 1465 write_cmd.write_data = IXGBE_CPU_TO_BE32(data); 1466 1467 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd, 1468 sizeof(write_cmd), 1469 IXGBE_HI_COMMAND_TIMEOUT, FALSE); 1470 1471 return status; 1472 } 1473 1474 /** 1475 * ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device 1476 * @hw: pointer to hardware structure 1477 * @reg_addr: 32 bit PHY register to write 1478 * @device_type: 3 bit device type 1479 * @data: Pointer to read data from the register 1480 **/ 1481 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 1482 u32 device_type, u32 *data) 1483 { 1484 union { 1485 struct ixgbe_hic_internal_phy_req cmd; 1486 struct ixgbe_hic_internal_phy_resp rsp; 1487 } hic; 1488 s32 status; 1489 UNREFERENCED_1PARAMETER(device_type); 1490 1491 memset(&hic, 0, sizeof(hic)); 1492 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 1493 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 1494 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1495 hic.cmd.port_number = hw->bus.lan_id; 1496 hic.cmd.command_type = FW_INT_PHY_REQ_READ; 1497 hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr); 1498 1499 status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd, 1500 sizeof(hic.cmd), 1501 IXGBE_HI_COMMAND_TIMEOUT, TRUE); 1502 1503 /* Extract the register value from the response. */ 1504 *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data); 1505 1506 return status; 1507 } 1508 1509 /** 1510 * ixgbe_disable_mdd_X550 1511 * @hw: pointer to hardware structure 1512 * 1513 * Disable malicious driver detection 1514 **/ 1515 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw) 1516 { 1517 u32 reg; 1518 1519 DEBUGFUNC("ixgbe_disable_mdd_X550"); 1520 1521 /* Disable MDD for TX DMA and interrupt */ 1522 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1523 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN); 1524 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1525 1526 /* Disable MDD for RX and interrupt */ 1527 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 1528 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN); 1529 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 1530 } 1531 1532 /** 1533 * ixgbe_enable_mdd_X550 1534 * @hw: pointer to hardware structure 1535 * 1536 * Enable malicious driver detection 1537 **/ 1538 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw) 1539 { 1540 u32 reg; 1541 1542 DEBUGFUNC("ixgbe_enable_mdd_X550"); 1543 1544 /* Enable MDD for TX DMA and interrupt */ 1545 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1546 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN); 1547 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1548 1549 /* Enable MDD for RX and interrupt */ 1550 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 1551 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN); 1552 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 1553 } 1554 1555 /** 1556 * ixgbe_restore_mdd_vf_X550 1557 * @hw: pointer to hardware structure 1558 * @vf: vf index 1559 * 1560 * Restore VF that was disabled during malicious driver detection event 1561 **/ 1562 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf) 1563 { 1564 u32 idx, reg, num_qs, start_q, bitmask; 1565 1566 DEBUGFUNC("ixgbe_restore_mdd_vf_X550"); 1567 1568 /* Map VF to queues */ 1569 reg = IXGBE_READ_REG(hw, IXGBE_MRQC); 1570 switch (reg & IXGBE_MRQC_MRQE_MASK) { 1571 case IXGBE_MRQC_VMDQRT8TCEN: 1572 num_qs = 8; /* 16 VFs / pools */ 1573 bitmask = 0x000000FF; 1574 break; 1575 case IXGBE_MRQC_VMDQRSS32EN: 1576 case IXGBE_MRQC_VMDQRT4TCEN: 1577 num_qs = 4; /* 32 VFs / pools */ 1578 bitmask = 0x0000000F; 1579 break; 1580 default: /* 64 VFs / pools */ 1581 num_qs = 2; 1582 bitmask = 0x00000003; 1583 break; 1584 } 1585 start_q = vf * num_qs; 1586 1587 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */ 1588 idx = start_q / 32; 1589 reg = 0; 1590 reg |= (bitmask << (start_q % 32)); 1591 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg); 1592 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg); 1593 } 1594 1595 /** 1596 * ixgbe_mdd_event_X550 1597 * @hw: pointer to hardware structure 1598 * @vf_bitmap: vf bitmap of malicious vfs 1599 * 1600 * Handle malicious driver detection event. 1601 **/ 1602 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap) 1603 { 1604 u32 wqbr; 1605 u32 i, j, reg, q, shift, vf, idx; 1606 1607 DEBUGFUNC("ixgbe_mdd_event_X550"); 1608 1609 /* figure out pool size for mapping to vf's */ 1610 reg = IXGBE_READ_REG(hw, IXGBE_MRQC); 1611 switch (reg & IXGBE_MRQC_MRQE_MASK) { 1612 case IXGBE_MRQC_VMDQRT8TCEN: 1613 shift = 3; /* 16 VFs / pools */ 1614 break; 1615 case IXGBE_MRQC_VMDQRSS32EN: 1616 case IXGBE_MRQC_VMDQRT4TCEN: 1617 shift = 2; /* 32 VFs / pools */ 1618 break; 1619 default: 1620 shift = 1; /* 64 VFs / pools */ 1621 break; 1622 } 1623 1624 /* Read WQBR_TX and WQBR_RX and check for malicious queues */ 1625 for (i = 0; i < 4; i++) { 1626 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i)); 1627 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i)); 1628 1629 if (!wqbr) 1630 continue; 1631 1632 /* Get malicious queue */ 1633 for (j = 0; j < 32 && wqbr; j++) { 1634 1635 if (!(wqbr & (1 << j))) 1636 continue; 1637 1638 /* Get queue from bitmask */ 1639 q = j + (i * 32); 1640 1641 /* Map queue to vf */ 1642 vf = (q >> shift); 1643 1644 /* Set vf bit in vf_bitmap */ 1645 idx = vf / 32; 1646 vf_bitmap[idx] |= (1 << (vf % 32)); 1647 wqbr &= ~(1 << j); 1648 } 1649 } 1650 } 1651 1652 /** 1653 * ixgbe_get_media_type_X550em - Get media type 1654 * @hw: pointer to hardware structure 1655 * 1656 * Returns the media type (fiber, copper, backplane) 1657 */ 1658 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) 1659 { 1660 enum ixgbe_media_type media_type; 1661 1662 DEBUGFUNC("ixgbe_get_media_type_X550em"); 1663 1664 /* Detect if there is a copper PHY attached. */ 1665 switch (hw->device_id) { 1666 case IXGBE_DEV_ID_X550EM_X_KR: 1667 case IXGBE_DEV_ID_X550EM_X_KX4: 1668 case IXGBE_DEV_ID_X550EM_X_XFI: 1669 case IXGBE_DEV_ID_X550EM_A_KR: 1670 case IXGBE_DEV_ID_X550EM_A_KR_L: 1671 media_type = ixgbe_media_type_backplane; 1672 break; 1673 case IXGBE_DEV_ID_X550EM_X_SFP: 1674 case IXGBE_DEV_ID_X550EM_A_SFP: 1675 case IXGBE_DEV_ID_X550EM_A_SFP_N: 1676 case IXGBE_DEV_ID_X550EM_A_QSFP: 1677 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 1678 media_type = ixgbe_media_type_fiber; 1679 break; 1680 case IXGBE_DEV_ID_X550EM_X_1G_T: 1681 case IXGBE_DEV_ID_X550EM_X_10G_T: 1682 case IXGBE_DEV_ID_X550EM_A_10G_T: 1683 media_type = ixgbe_media_type_copper; 1684 break; 1685 case IXGBE_DEV_ID_X550EM_A_SGMII: 1686 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 1687 media_type = ixgbe_media_type_backplane; 1688 hw->phy.type = ixgbe_phy_sgmii; 1689 break; 1690 case IXGBE_DEV_ID_X550EM_A_1G_T: 1691 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 1692 media_type = ixgbe_media_type_copper; 1693 break; 1694 default: 1695 media_type = ixgbe_media_type_unknown; 1696 break; 1697 } 1698 return media_type; 1699 } 1700 1701 /** 1702 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported 1703 * @hw: pointer to hardware structure 1704 * @linear: TRUE if SFP module is linear 1705 */ 1706 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear) 1707 { 1708 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em"); 1709 1710 switch (hw->phy.sfp_type) { 1711 case ixgbe_sfp_type_not_present: 1712 return IXGBE_ERR_SFP_NOT_PRESENT; 1713 case ixgbe_sfp_type_da_cu_core0: 1714 case ixgbe_sfp_type_da_cu_core1: 1715 *linear = TRUE; 1716 break; 1717 case ixgbe_sfp_type_srlr_core0: 1718 case ixgbe_sfp_type_srlr_core1: 1719 case ixgbe_sfp_type_da_act_lmt_core0: 1720 case ixgbe_sfp_type_da_act_lmt_core1: 1721 case ixgbe_sfp_type_1g_sx_core0: 1722 case ixgbe_sfp_type_1g_sx_core1: 1723 case ixgbe_sfp_type_1g_lx_core0: 1724 case ixgbe_sfp_type_1g_lx_core1: 1725 *linear = FALSE; 1726 break; 1727 case ixgbe_sfp_type_unknown: 1728 case ixgbe_sfp_type_1g_cu_core0: 1729 case ixgbe_sfp_type_1g_cu_core1: 1730 default: 1731 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1732 } 1733 1734 return IXGBE_SUCCESS; 1735 } 1736 1737 /** 1738 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules 1739 * @hw: pointer to hardware structure 1740 * 1741 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1742 **/ 1743 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw) 1744 { 1745 s32 status; 1746 bool linear; 1747 1748 DEBUGFUNC("ixgbe_identify_sfp_module_X550em"); 1749 1750 status = ixgbe_identify_module_generic(hw); 1751 1752 if (status != IXGBE_SUCCESS) 1753 return status; 1754 1755 /* Check if SFP module is supported */ 1756 status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 1757 1758 return status; 1759 } 1760 1761 /** 1762 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops 1763 * @hw: pointer to hardware structure 1764 */ 1765 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) 1766 { 1767 s32 status; 1768 bool linear; 1769 1770 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em"); 1771 1772 /* Check if SFP module is supported */ 1773 status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 1774 1775 if (status != IXGBE_SUCCESS) 1776 return status; 1777 1778 ixgbe_init_mac_link_ops_X550em(hw); 1779 hw->phy.ops.reset = NULL; 1780 1781 return IXGBE_SUCCESS; 1782 } 1783 1784 /** 1785 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the 1786 * internal PHY 1787 * @hw: pointer to hardware structure 1788 **/ 1789 static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw) 1790 { 1791 s32 status; 1792 u32 link_ctrl; 1793 1794 /* Restart auto-negotiation. */ 1795 status = hw->mac.ops.read_iosf_sb_reg(hw, 1796 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1797 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl); 1798 1799 if (status) { 1800 DEBUGOUT("Auto-negotiation did not complete\n"); 1801 return status; 1802 } 1803 1804 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1805 status = hw->mac.ops.write_iosf_sb_reg(hw, 1806 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1807 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl); 1808 1809 if (hw->mac.type == ixgbe_mac_X550EM_a) { 1810 u32 flx_mask_st20; 1811 1812 /* Indicate to FW that AN restart has been asserted */ 1813 status = hw->mac.ops.read_iosf_sb_reg(hw, 1814 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1815 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20); 1816 1817 if (status) { 1818 DEBUGOUT("Auto-negotiation did not complete\n"); 1819 return status; 1820 } 1821 1822 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART; 1823 status = hw->mac.ops.write_iosf_sb_reg(hw, 1824 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1825 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20); 1826 } 1827 1828 return status; 1829 } 1830 1831 /** 1832 * ixgbe_setup_sgmii - Set up link for sgmii 1833 * @hw: pointer to hardware structure 1834 */ 1835 static s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1836 bool autoneg_wait) 1837 { 1838 struct ixgbe_mac_info *mac = &hw->mac; 1839 u32 lval, sval, flx_val; 1840 s32 rc; 1841 1842 rc = mac->ops.read_iosf_sb_reg(hw, 1843 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1844 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 1845 if (rc) 1846 return rc; 1847 1848 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1849 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1850 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 1851 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 1852 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1853 rc = mac->ops.write_iosf_sb_reg(hw, 1854 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1855 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 1856 if (rc) 1857 return rc; 1858 1859 rc = mac->ops.read_iosf_sb_reg(hw, 1860 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1861 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 1862 if (rc) 1863 return rc; 1864 1865 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 1866 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 1867 rc = mac->ops.write_iosf_sb_reg(hw, 1868 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1869 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 1870 if (rc) 1871 return rc; 1872 1873 rc = mac->ops.read_iosf_sb_reg(hw, 1874 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1875 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 1876 if (rc) 1877 return rc; 1878 1879 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 1880 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 1881 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 1882 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 1883 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 1884 1885 rc = mac->ops.write_iosf_sb_reg(hw, 1886 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1887 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 1888 if (rc) 1889 return rc; 1890 1891 rc = ixgbe_restart_an_internal_phy_x550em(hw); 1892 if (rc) 1893 return rc; 1894 1895 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 1896 } 1897 1898 /** 1899 * ixgbe_setup_sgmii_fw - Set up link for internal PHY SGMII auto-negotiation 1900 * @hw: pointer to hardware structure 1901 */ 1902 static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1903 bool autoneg_wait) 1904 { 1905 struct ixgbe_mac_info *mac = &hw->mac; 1906 u32 lval, sval, flx_val; 1907 s32 rc; 1908 1909 rc = mac->ops.read_iosf_sb_reg(hw, 1910 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1911 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 1912 if (rc) 1913 return rc; 1914 1915 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1916 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1917 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 1918 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 1919 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1920 rc = mac->ops.write_iosf_sb_reg(hw, 1921 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1922 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 1923 if (rc) 1924 return rc; 1925 1926 rc = mac->ops.read_iosf_sb_reg(hw, 1927 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1928 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 1929 if (rc) 1930 return rc; 1931 1932 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 1933 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 1934 rc = mac->ops.write_iosf_sb_reg(hw, 1935 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1936 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 1937 if (rc) 1938 return rc; 1939 1940 rc = mac->ops.write_iosf_sb_reg(hw, 1941 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1942 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 1943 if (rc) 1944 return rc; 1945 1946 rc = mac->ops.read_iosf_sb_reg(hw, 1947 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1948 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 1949 if (rc) 1950 return rc; 1951 1952 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 1953 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 1954 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 1955 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 1956 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 1957 1958 rc = mac->ops.write_iosf_sb_reg(hw, 1959 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1960 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 1961 if (rc) 1962 return rc; 1963 1964 rc = ixgbe_restart_an_internal_phy_x550em(hw); 1965 1966 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 1967 } 1968 1969 /** 1970 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers 1971 * @hw: pointer to hardware structure 1972 */ 1973 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) 1974 { 1975 struct ixgbe_mac_info *mac = &hw->mac; 1976 1977 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em"); 1978 1979 switch (hw->mac.ops.get_media_type(hw)) { 1980 case ixgbe_media_type_fiber: 1981 /* CS4227 does not support autoneg, so disable the laser control 1982 * functions for SFP+ fiber 1983 */ 1984 mac->ops.disable_tx_laser = NULL; 1985 mac->ops.enable_tx_laser = NULL; 1986 mac->ops.flap_tx_laser = NULL; 1987 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 1988 mac->ops.set_rate_select_speed = 1989 ixgbe_set_soft_rate_select_speed; 1990 1991 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) || 1992 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP)) 1993 mac->ops.setup_mac_link = 1994 ixgbe_setup_mac_link_sfp_x550a; 1995 else 1996 mac->ops.setup_mac_link = 1997 ixgbe_setup_mac_link_sfp_x550em; 1998 break; 1999 case ixgbe_media_type_copper: 2000 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) 2001 break; 2002 if (hw->mac.type == ixgbe_mac_X550EM_a) { 2003 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 2004 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) { 2005 mac->ops.setup_link = ixgbe_setup_sgmii_fw; 2006 mac->ops.check_link = 2007 ixgbe_check_mac_link_generic; 2008 } else { 2009 mac->ops.setup_link = 2010 ixgbe_setup_mac_link_t_X550em; 2011 } 2012 } else { 2013 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 2014 mac->ops.check_link = ixgbe_check_link_t_X550em; 2015 } 2016 break; 2017 case ixgbe_media_type_backplane: 2018 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII || 2019 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) 2020 mac->ops.setup_link = ixgbe_setup_sgmii; 2021 break; 2022 default: 2023 break; 2024 } 2025 } 2026 2027 /** 2028 * ixgbe_get_link_capabilities_x550em - Determines link capabilities 2029 * @hw: pointer to hardware structure 2030 * @speed: pointer to link speed 2031 * @autoneg: TRUE when autoneg or autotry is enabled 2032 */ 2033 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, 2034 ixgbe_link_speed *speed, 2035 bool *autoneg) 2036 { 2037 DEBUGFUNC("ixgbe_get_link_capabilities_X550em"); 2038 2039 2040 if (hw->phy.type == ixgbe_phy_fw) { 2041 *autoneg = TRUE; 2042 *speed = hw->phy.speeds_supported; 2043 return 0; 2044 } 2045 2046 /* SFP */ 2047 if (hw->phy.media_type == ixgbe_media_type_fiber) { 2048 2049 /* CS4227 SFP must not enable auto-negotiation */ 2050 *autoneg = FALSE; 2051 2052 /* Check if 1G SFP module. */ 2053 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 2054 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 2055 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 2056 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) { 2057 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2058 return IXGBE_SUCCESS; 2059 } 2060 2061 /* Link capabilities are based on SFP */ 2062 if (hw->phy.multispeed_fiber) 2063 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2064 IXGBE_LINK_SPEED_1GB_FULL; 2065 else 2066 *speed = IXGBE_LINK_SPEED_10GB_FULL; 2067 } else { 2068 switch (hw->phy.type) { 2069 case ixgbe_phy_ext_1g_t: 2070 case ixgbe_phy_sgmii: 2071 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2072 break; 2073 case ixgbe_phy_x550em_kr: 2074 if (hw->mac.type == ixgbe_mac_X550EM_a) { 2075 /* check different backplane modes */ 2076 if (hw->phy.nw_mng_if_sel & 2077 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) { 2078 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 2079 break; 2080 } else if (hw->device_id == 2081 IXGBE_DEV_ID_X550EM_A_KR_L) { 2082 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2083 break; 2084 } 2085 } 2086 /* fall through */ 2087 default: 2088 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2089 IXGBE_LINK_SPEED_1GB_FULL; 2090 break; 2091 } 2092 *autoneg = TRUE; 2093 } 2094 2095 return IXGBE_SUCCESS; 2096 } 2097 2098 /** 2099 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause 2100 * @hw: pointer to hardware structure 2101 * @lsc: pointer to boolean flag which indicates whether external Base T 2102 * PHY interrupt is lsc 2103 * 2104 * Determime if external Base T PHY interrupt cause is high temperature 2105 * failure alarm or link status change. 2106 * 2107 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 2108 * failure alarm, else return PHY access status. 2109 */ 2110 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc) 2111 { 2112 u32 status; 2113 u16 reg; 2114 2115 *lsc = FALSE; 2116 2117 /* Vendor alarm triggered */ 2118 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2119 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2120 ®); 2121 2122 if (status != IXGBE_SUCCESS || 2123 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN)) 2124 return status; 2125 2126 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */ 2127 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, 2128 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2129 ®); 2130 2131 if (status != IXGBE_SUCCESS || 2132 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2133 IXGBE_MDIO_GLOBAL_ALARM_1_INT))) 2134 return status; 2135 2136 /* Global alarm triggered */ 2137 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, 2138 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2139 ®); 2140 2141 if (status != IXGBE_SUCCESS) 2142 return status; 2143 2144 /* If high temperature failure, then return over temp error and exit */ 2145 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) { 2146 /* power down the PHY in case the PHY FW didn't already */ 2147 ixgbe_set_copper_phy_power(hw, FALSE); 2148 return IXGBE_ERR_OVERTEMP; 2149 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) { 2150 /* device fault alarm triggered */ 2151 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG, 2152 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2153 ®); 2154 2155 if (status != IXGBE_SUCCESS) 2156 return status; 2157 2158 /* if device fault was due to high temp alarm handle and exit */ 2159 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) { 2160 /* power down the PHY in case the PHY FW didn't */ 2161 ixgbe_set_copper_phy_power(hw, FALSE); 2162 return IXGBE_ERR_OVERTEMP; 2163 } 2164 } 2165 2166 /* Vendor alarm 2 triggered */ 2167 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2168 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 2169 2170 if (status != IXGBE_SUCCESS || 2171 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT)) 2172 return status; 2173 2174 /* link connect/disconnect event occurred */ 2175 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2, 2176 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 2177 2178 if (status != IXGBE_SUCCESS) 2179 return status; 2180 2181 /* Indicate LSC */ 2182 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC) 2183 *lsc = TRUE; 2184 2185 return IXGBE_SUCCESS; 2186 } 2187 2188 /** 2189 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts 2190 * @hw: pointer to hardware structure 2191 * 2192 * Enable link status change and temperature failure alarm for the external 2193 * Base T PHY 2194 * 2195 * Returns PHY access status 2196 */ 2197 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw) 2198 { 2199 u32 status; 2200 u16 reg; 2201 bool lsc; 2202 2203 /* Clear interrupt flags */ 2204 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 2205 2206 /* Enable link status change alarm */ 2207 2208 /* Enable the LASI interrupts on X552 devices to receive notifications 2209 * of the link configurations of the external PHY and correspondingly 2210 * support the configuration of the internal iXFI link, since iXFI does 2211 * not support auto-negotiation. This is not required for X553 devices 2212 * having KR support, which performs auto-negotiations and which is used 2213 * as the internal link to the external PHY. Hence adding a check here 2214 * to avoid enabling LASI interrupts for X553 devices. 2215 */ 2216 if (hw->mac.type != ixgbe_mac_X550EM_a) { 2217 status = hw->phy.ops.read_reg(hw, 2218 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2219 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 2220 2221 if (status != IXGBE_SUCCESS) 2222 return status; 2223 2224 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN; 2225 2226 status = hw->phy.ops.write_reg(hw, 2227 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2228 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg); 2229 2230 if (status != IXGBE_SUCCESS) 2231 return status; 2232 } 2233 2234 /* Enable high temperature failure and global fault alarms */ 2235 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2236 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2237 ®); 2238 2239 if (status != IXGBE_SUCCESS) 2240 return status; 2241 2242 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN | 2243 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN); 2244 2245 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2246 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2247 reg); 2248 2249 if (status != IXGBE_SUCCESS) 2250 return status; 2251 2252 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */ 2253 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2254 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2255 ®); 2256 2257 if (status != IXGBE_SUCCESS) 2258 return status; 2259 2260 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2261 IXGBE_MDIO_GLOBAL_ALARM_1_INT); 2262 2263 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2264 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2265 reg); 2266 2267 if (status != IXGBE_SUCCESS) 2268 return status; 2269 2270 /* Enable chip-wide vendor alarm */ 2271 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2272 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2273 ®); 2274 2275 if (status != IXGBE_SUCCESS) 2276 return status; 2277 2278 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN; 2279 2280 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2281 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2282 reg); 2283 2284 return status; 2285 } 2286 2287 /** 2288 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed. 2289 * @hw: pointer to hardware structure 2290 * @speed: link speed 2291 * 2292 * Configures the integrated KR PHY. 2293 **/ 2294 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, 2295 ixgbe_link_speed speed) 2296 { 2297 s32 status; 2298 u32 reg_val; 2299 2300 status = hw->mac.ops.read_iosf_sb_reg(hw, 2301 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2302 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2303 if (status) 2304 return status; 2305 2306 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2307 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | 2308 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); 2309 2310 /* Advertise 10G support. */ 2311 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 2312 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; 2313 2314 /* Advertise 1G support. */ 2315 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 2316 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; 2317 2318 status = hw->mac.ops.write_iosf_sb_reg(hw, 2319 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2320 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2321 2322 if (hw->mac.type == ixgbe_mac_X550EM_a) { 2323 /* Set lane mode to KR auto negotiation */ 2324 status = hw->mac.ops.read_iosf_sb_reg(hw, 2325 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2326 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2327 2328 if (status) 2329 return status; 2330 2331 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2332 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 2333 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2334 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2335 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2336 2337 status = hw->mac.ops.write_iosf_sb_reg(hw, 2338 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2339 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2340 } 2341 2342 return ixgbe_restart_an_internal_phy_x550em(hw); 2343 } 2344 2345 /** 2346 * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs 2347 * @hw: pointer to hardware structure 2348 */ 2349 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw) 2350 { 2351 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 2352 s32 rc; 2353 2354 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 2355 return IXGBE_SUCCESS; 2356 2357 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store); 2358 if (rc) 2359 return rc; 2360 memset(store, 0, sizeof(store)); 2361 2362 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store); 2363 if (rc) 2364 return rc; 2365 2366 return ixgbe_setup_fw_link(hw); 2367 } 2368 2369 /** 2370 * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp 2371 * @hw: pointer to hardware structure 2372 */ 2373 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw) 2374 { 2375 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 2376 s32 rc; 2377 2378 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store); 2379 if (rc) 2380 return rc; 2381 2382 if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) { 2383 ixgbe_shutdown_fw_phy(hw); 2384 return IXGBE_ERR_OVERTEMP; 2385 } 2386 return IXGBE_SUCCESS; 2387 } 2388 2389 /** 2390 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register 2391 * @hw: pointer to hardware structure 2392 * 2393 * Read NW_MNG_IF_SEL register and save field values, and check for valid field 2394 * values. 2395 **/ 2396 static s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw) 2397 { 2398 /* Save NW management interface connected on board. This is used 2399 * to determine internal PHY mode. 2400 */ 2401 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 2402 2403 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set 2404 * PHY address. This register field was has only been used for X552. 2405 */ 2406 if (hw->mac.type == ixgbe_mac_X550EM_a && 2407 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) { 2408 hw->phy.addr = (hw->phy.nw_mng_if_sel & 2409 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 2410 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 2411 } 2412 2413 return IXGBE_SUCCESS; 2414 } 2415 2416 /** 2417 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init 2418 * @hw: pointer to hardware structure 2419 * 2420 * Initialize any function pointers that were not able to be 2421 * set during init_shared_code because the PHY/SFP type was 2422 * not known. Perform the SFP init if necessary. 2423 */ 2424 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) 2425 { 2426 struct ixgbe_phy_info *phy = &hw->phy; 2427 s32 ret_val; 2428 2429 DEBUGFUNC("ixgbe_init_phy_ops_X550em"); 2430 2431 hw->mac.ops.set_lan_id(hw); 2432 ixgbe_read_mng_if_sel_x550em(hw); 2433 2434 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { 2435 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 2436 ixgbe_setup_mux_ctl(hw); 2437 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em; 2438 } 2439 2440 switch (hw->device_id) { 2441 case IXGBE_DEV_ID_X550EM_A_1G_T: 2442 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2443 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22; 2444 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22; 2445 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a; 2446 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a; 2447 phy->ops.check_overtemp = ixgbe_check_overtemp_fw; 2448 if (hw->bus.lan_id) 2449 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; 2450 else 2451 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; 2452 2453 break; 2454 case IXGBE_DEV_ID_X550EM_A_10G_T: 2455 case IXGBE_DEV_ID_X550EM_A_SFP: 2456 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a; 2457 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a; 2458 if (hw->bus.lan_id) 2459 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; 2460 else 2461 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; 2462 break; 2463 case IXGBE_DEV_ID_X550EM_X_SFP: 2464 /* set up for CS4227 usage */ 2465 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 2466 break; 2467 case IXGBE_DEV_ID_X550EM_X_1G_T: 2468 phy->ops.read_reg_mdi = NULL; 2469 phy->ops.write_reg_mdi = NULL; 2470 break; 2471 default: 2472 break; 2473 } 2474 2475 /* Identify the PHY or SFP module */ 2476 ret_val = phy->ops.identify(hw); 2477 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED || 2478 ret_val == IXGBE_ERR_PHY_ADDR_INVALID) 2479 return ret_val; 2480 2481 /* Setup function pointers based on detected hardware */ 2482 ixgbe_init_mac_link_ops_X550em(hw); 2483 if (phy->sfp_type != ixgbe_sfp_type_unknown) 2484 phy->ops.reset = NULL; 2485 2486 /* Set functions pointers based on phy type */ 2487 switch (hw->phy.type) { 2488 case ixgbe_phy_x550em_kx4: 2489 phy->ops.setup_link = NULL; 2490 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 2491 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 2492 break; 2493 case ixgbe_phy_x550em_kr: 2494 phy->ops.setup_link = ixgbe_setup_kr_x550em; 2495 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 2496 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 2497 break; 2498 case ixgbe_phy_ext_1g_t: 2499 /* link is managed by FW */ 2500 phy->ops.setup_link = NULL; 2501 phy->ops.reset = NULL; 2502 break; 2503 case ixgbe_phy_x550em_xfi: 2504 /* link is managed by HW */ 2505 phy->ops.setup_link = NULL; 2506 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 2507 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 2508 break; 2509 case ixgbe_phy_x550em_ext_t: 2510 /* If internal link mode is XFI, then setup iXFI internal link, 2511 * else setup KR now. 2512 */ 2513 phy->ops.setup_internal_link = 2514 ixgbe_setup_internal_phy_t_x550em; 2515 2516 /* setup SW LPLU only for first revision of X550EM_x */ 2517 if ((hw->mac.type == ixgbe_mac_X550EM_x) && 2518 !(IXGBE_FUSES0_REV_MASK & 2519 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))) 2520 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em; 2521 2522 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; 2523 phy->ops.reset = ixgbe_reset_phy_t_X550em; 2524 break; 2525 case ixgbe_phy_sgmii: 2526 phy->ops.setup_link = NULL; 2527 break; 2528 case ixgbe_phy_fw: 2529 phy->ops.setup_link = ixgbe_setup_fw_link; 2530 phy->ops.reset = ixgbe_reset_phy_fw; 2531 break; 2532 default: 2533 break; 2534 } 2535 return ret_val; 2536 } 2537 2538 /** 2539 * ixgbe_set_mdio_speed - Set MDIO clock speed 2540 * @hw: pointer to hardware structure 2541 */ 2542 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw) 2543 { 2544 u32 hlreg0; 2545 2546 switch (hw->device_id) { 2547 case IXGBE_DEV_ID_X550EM_X_10G_T: 2548 case IXGBE_DEV_ID_X550EM_A_SGMII: 2549 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 2550 case IXGBE_DEV_ID_X550EM_A_10G_T: 2551 case IXGBE_DEV_ID_X550EM_A_SFP: 2552 case IXGBE_DEV_ID_X550EM_A_QSFP: 2553 /* Config MDIO clock speed before the first MDIO PHY access */ 2554 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 2555 hlreg0 &= ~IXGBE_HLREG0_MDCSPD; 2556 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 2557 break; 2558 case IXGBE_DEV_ID_X550EM_A_1G_T: 2559 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2560 /* Select fast MDIO clock speed for these devices */ 2561 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 2562 hlreg0 |= IXGBE_HLREG0_MDCSPD; 2563 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 2564 break; 2565 default: 2566 break; 2567 } 2568 } 2569 2570 /** 2571 * ixgbe_reset_hw_X550em - Perform hardware reset 2572 * @hw: pointer to hardware structure 2573 * 2574 * Resets the hardware by resetting the transmit and receive units, masks 2575 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 2576 * reset. 2577 */ 2578 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) 2579 { 2580 ixgbe_link_speed link_speed; 2581 s32 status; 2582 u32 ctrl = 0; 2583 u32 i; 2584 bool link_up = FALSE; 2585 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2586 2587 DEBUGFUNC("ixgbe_reset_hw_X550em"); 2588 2589 /* Call adapter stop to disable Tx/Rx and clear interrupts */ 2590 status = hw->mac.ops.stop_adapter(hw); 2591 if (status != IXGBE_SUCCESS) { 2592 DEBUGOUT1("Failed to stop adapter, STATUS = %d\n", status); 2593 return status; 2594 } 2595 /* flush pending Tx transactions */ 2596 ixgbe_clear_tx_pending(hw); 2597 2598 ixgbe_set_mdio_speed(hw); 2599 2600 /* PHY ops must be identified and initialized prior to reset */ 2601 status = hw->phy.ops.init(hw); 2602 2603 if (status) 2604 DEBUGOUT1("Failed to initialize PHY ops, STATUS = %d\n", 2605 status); 2606 2607 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED || 2608 status == IXGBE_ERR_PHY_ADDR_INVALID) { 2609 DEBUGOUT("Returning from reset HW due to PHY init failure\n"); 2610 return status; 2611 } 2612 2613 /* start the external PHY */ 2614 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 2615 status = ixgbe_init_ext_t_x550em(hw); 2616 if (status) { 2617 DEBUGOUT1("Failed to start the external PHY, STATUS = %d\n", 2618 status); 2619 return status; 2620 } 2621 } 2622 2623 /* Setup SFP module if there is one present. */ 2624 if (hw->phy.sfp_setup_needed) { 2625 status = hw->mac.ops.setup_sfp(hw); 2626 hw->phy.sfp_setup_needed = FALSE; 2627 } 2628 2629 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 2630 return status; 2631 2632 /* Reset PHY */ 2633 if (!hw->phy.reset_disable && hw->phy.ops.reset) { 2634 if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP) 2635 return IXGBE_ERR_OVERTEMP; 2636 } 2637 2638 mac_reset_top: 2639 /* Issue global reset to the MAC. Needs to be SW reset if link is up. 2640 * If link reset is used when link is up, it might reset the PHY when 2641 * mng is using it. If link is down or the flag to force full link 2642 * reset is set, then perform link reset. 2643 */ 2644 ctrl = IXGBE_CTRL_LNK_RST; 2645 if (!hw->force_full_reset) { 2646 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE); 2647 if (link_up) 2648 ctrl = IXGBE_CTRL_RST; 2649 } 2650 2651 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 2652 if (status != IXGBE_SUCCESS) { 2653 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 2654 "semaphore failed with %d", status); 2655 return IXGBE_ERR_SWFW_SYNC; 2656 } 2657 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 2658 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 2659 IXGBE_WRITE_FLUSH(hw); 2660 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2661 2662 /* Poll for reset bit to self-clear meaning reset is complete */ 2663 for (i = 0; i < 10; i++) { 2664 usec_delay(1); 2665 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 2666 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 2667 break; 2668 } 2669 2670 if (ctrl & IXGBE_CTRL_RST_MASK) { 2671 status = IXGBE_ERR_RESET_FAILED; 2672 DEBUGOUT("Reset polling failed to complete.\n"); 2673 } 2674 2675 msec_delay(50); 2676 2677 /* Double resets are required for recovery from certain error 2678 * conditions. Between resets, it is necessary to stall to 2679 * allow time for any pending HW events to complete. 2680 */ 2681 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 2682 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 2683 goto mac_reset_top; 2684 } 2685 2686 /* Store the permanent mac address */ 2687 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 2688 2689 /* Store MAC address from RAR0, clear receive address registers, and 2690 * clear the multicast table. Also reset num_rar_entries to 128, 2691 * since we modify this value when programming the SAN MAC address. 2692 */ 2693 hw->mac.num_rar_entries = 128; 2694 hw->mac.ops.init_rx_addrs(hw); 2695 2696 ixgbe_set_mdio_speed(hw); 2697 2698 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) 2699 ixgbe_setup_mux_ctl(hw); 2700 2701 if (status != IXGBE_SUCCESS) 2702 DEBUGOUT1("Reset HW failed, STATUS = %d\n", status); 2703 2704 return status; 2705 } 2706 2707 /** 2708 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. 2709 * @hw: pointer to hardware structure 2710 */ 2711 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) 2712 { 2713 u32 status; 2714 u16 reg; 2715 2716 status = hw->phy.ops.read_reg(hw, 2717 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 2718 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 2719 ®); 2720 2721 if (status != IXGBE_SUCCESS) 2722 return status; 2723 2724 /* If PHY FW reset completed bit is set then this is the first 2725 * SW instance after a power on so the PHY FW must be un-stalled. 2726 */ 2727 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 2728 status = hw->phy.ops.read_reg(hw, 2729 IXGBE_MDIO_GLOBAL_RES_PR_10, 2730 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2731 ®); 2732 2733 if (status != IXGBE_SUCCESS) 2734 return status; 2735 2736 reg &= ~IXGBE_MDIO_POWER_UP_STALL; 2737 2738 status = hw->phy.ops.write_reg(hw, 2739 IXGBE_MDIO_GLOBAL_RES_PR_10, 2740 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2741 reg); 2742 2743 if (status != IXGBE_SUCCESS) 2744 return status; 2745 } 2746 2747 return status; 2748 } 2749 2750 /** 2751 * ixgbe_setup_kr_x550em - Configure the KR PHY. 2752 * @hw: pointer to hardware structure 2753 **/ 2754 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) 2755 { 2756 /* leave link alone for 2.5G */ 2757 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL) 2758 return IXGBE_SUCCESS; 2759 2760 if (ixgbe_check_reset_blocked(hw)) 2761 return 0; 2762 2763 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); 2764 } 2765 2766 /** 2767 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP 2768 * @hw: pointer to hardware structure 2769 * 2770 * Configure the external PHY and the integrated KR PHY for SFP support. 2771 **/ 2772 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, 2773 ixgbe_link_speed speed, 2774 bool autoneg_wait_to_complete) 2775 { 2776 s32 ret_val; 2777 u16 reg_slice, reg_val; 2778 bool setup_linear = FALSE; 2779 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 2780 2781 /* Check if SFP module is supported and linear */ 2782 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 2783 2784 /* If no SFP module present, then return success. Return success since 2785 * there is no reason to configure CS4227 and SFP not present error is 2786 * not excepted in the setup MAC link flow. 2787 */ 2788 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 2789 return IXGBE_SUCCESS; 2790 2791 if (ret_val != IXGBE_SUCCESS) 2792 return ret_val; 2793 2794 /* Configure internal PHY for KR/KX. */ 2795 ixgbe_setup_kr_speed_x550em(hw, speed); 2796 2797 /* Configure CS4227 LINE side to proper mode. */ 2798 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + 2799 (hw->bus.lan_id << 12); 2800 if (setup_linear) 2801 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 2802 else 2803 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 2804 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice, 2805 reg_val); 2806 return ret_val; 2807 } 2808 2809 /** 2810 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode 2811 * @hw: pointer to hardware structure 2812 * @speed: the link speed to force 2813 * 2814 * Configures the integrated PHY for native SFI mode. Used to connect the 2815 * internal PHY directly to an SFP cage, without autonegotiation. 2816 **/ 2817 static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 2818 { 2819 struct ixgbe_mac_info *mac = &hw->mac; 2820 s32 status; 2821 u32 reg_val; 2822 2823 /* Disable all AN and force speed to 10G Serial. */ 2824 status = mac->ops.read_iosf_sb_reg(hw, 2825 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2826 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2827 if (status != IXGBE_SUCCESS) 2828 return status; 2829 2830 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2831 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2832 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2833 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2834 2835 /* Select forced link speed for internal PHY. */ 2836 switch (*speed) { 2837 case IXGBE_LINK_SPEED_10GB_FULL: 2838 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G; 2839 break; 2840 case IXGBE_LINK_SPEED_1GB_FULL: 2841 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 2842 break; 2843 default: 2844 /* Other link speeds are not supported by internal PHY. */ 2845 return IXGBE_ERR_LINK_SETUP; 2846 } 2847 2848 status = mac->ops.write_iosf_sb_reg(hw, 2849 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2850 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2851 2852 /* Toggle port SW reset by AN reset. */ 2853 status = ixgbe_restart_an_internal_phy_x550em(hw); 2854 2855 return status; 2856 } 2857 2858 /** 2859 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP 2860 * @hw: pointer to hardware structure 2861 * 2862 * Configure the the integrated PHY for SFP support. 2863 **/ 2864 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, 2865 ixgbe_link_speed speed, 2866 bool autoneg_wait_to_complete) 2867 { 2868 s32 ret_val; 2869 u16 reg_phy_ext; 2870 bool setup_linear = FALSE; 2871 u32 reg_slice, reg_phy_int, slice_offset; 2872 2873 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 2874 2875 /* Check if SFP module is supported and linear */ 2876 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 2877 2878 /* If no SFP module present, then return success. Return success since 2879 * SFP not present error is not excepted in the setup MAC link flow. 2880 */ 2881 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 2882 return IXGBE_SUCCESS; 2883 2884 if (ret_val != IXGBE_SUCCESS) 2885 return ret_val; 2886 2887 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) { 2888 /* Configure internal PHY for native SFI based on module type */ 2889 ret_val = hw->mac.ops.read_iosf_sb_reg(hw, 2890 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2891 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int); 2892 2893 if (ret_val != IXGBE_SUCCESS) 2894 return ret_val; 2895 2896 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA; 2897 if (!setup_linear) 2898 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR; 2899 2900 ret_val = hw->mac.ops.write_iosf_sb_reg(hw, 2901 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2902 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int); 2903 2904 if (ret_val != IXGBE_SUCCESS) 2905 return ret_val; 2906 2907 /* Setup SFI internal link. */ 2908 ret_val = ixgbe_setup_sfi_x550a(hw, &speed); 2909 } else { 2910 /* Configure internal PHY for KR/KX. */ 2911 ixgbe_setup_kr_speed_x550em(hw, speed); 2912 2913 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) { 2914 /* Find Address */ 2915 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n"); 2916 return IXGBE_ERR_PHY_ADDR_INVALID; 2917 } 2918 2919 /* Get external PHY SKU id */ 2920 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU, 2921 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 2922 2923 if (ret_val != IXGBE_SUCCESS) 2924 return ret_val; 2925 2926 /* When configuring quad port CS4223, the MAC instance is part 2927 * of the slice offset. 2928 */ 2929 if (reg_phy_ext == IXGBE_CS4223_SKU_ID) 2930 slice_offset = (hw->bus.lan_id + 2931 (hw->bus.instance_id << 1)) << 12; 2932 else 2933 slice_offset = hw->bus.lan_id << 12; 2934 2935 /* Configure CS4227/CS4223 LINE side to proper mode. */ 2936 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset; 2937 2938 ret_val = hw->phy.ops.read_reg(hw, reg_slice, 2939 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 2940 2941 if (ret_val != IXGBE_SUCCESS) 2942 return ret_val; 2943 2944 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) | 2945 (IXGBE_CS4227_EDC_MODE_SR << 1)); 2946 2947 if (setup_linear) 2948 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 2949 else 2950 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 2951 ret_val = hw->phy.ops.write_reg(hw, reg_slice, 2952 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext); 2953 2954 /* Flush previous write with a read */ 2955 ret_val = hw->phy.ops.read_reg(hw, reg_slice, 2956 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 2957 } 2958 return ret_val; 2959 } 2960 2961 /** 2962 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration 2963 * @hw: pointer to hardware structure 2964 * 2965 * iXfI configuration needed for ixgbe_mac_X550EM_x devices. 2966 **/ 2967 static s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw) 2968 { 2969 struct ixgbe_mac_info *mac = &hw->mac; 2970 s32 status; 2971 u32 reg_val; 2972 2973 /* Disable training protocol FSM. */ 2974 status = mac->ops.read_iosf_sb_reg(hw, 2975 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 2976 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2977 if (status != IXGBE_SUCCESS) 2978 return status; 2979 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; 2980 status = mac->ops.write_iosf_sb_reg(hw, 2981 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 2982 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2983 if (status != IXGBE_SUCCESS) 2984 return status; 2985 2986 /* Disable Flex from training TXFFE. */ 2987 status = mac->ops.read_iosf_sb_reg(hw, 2988 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 2989 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2990 if (status != IXGBE_SUCCESS) 2991 return status; 2992 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 2993 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 2994 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 2995 status = mac->ops.write_iosf_sb_reg(hw, 2996 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 2997 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2998 if (status != IXGBE_SUCCESS) 2999 return status; 3000 status = mac->ops.read_iosf_sb_reg(hw, 3001 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 3002 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3003 if (status != IXGBE_SUCCESS) 3004 return status; 3005 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 3006 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 3007 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 3008 status = mac->ops.write_iosf_sb_reg(hw, 3009 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 3010 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3011 if (status != IXGBE_SUCCESS) 3012 return status; 3013 3014 /* Enable override for coefficients. */ 3015 status = mac->ops.read_iosf_sb_reg(hw, 3016 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 3017 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3018 if (status != IXGBE_SUCCESS) 3019 return status; 3020 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; 3021 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; 3022 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; 3023 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; 3024 status = mac->ops.write_iosf_sb_reg(hw, 3025 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 3026 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3027 return status; 3028 } 3029 3030 /** 3031 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. 3032 * @hw: pointer to hardware structure 3033 * @speed: the link speed to force 3034 * 3035 * Configures the integrated KR PHY to use iXFI mode. Used to connect an 3036 * internal and external PHY at a specific speed, without autonegotiation. 3037 **/ 3038 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 3039 { 3040 struct ixgbe_mac_info *mac = &hw->mac; 3041 s32 status; 3042 u32 reg_val; 3043 3044 /* iXFI is only supported with X552 */ 3045 if (mac->type != ixgbe_mac_X550EM_x) 3046 return IXGBE_ERR_LINK_SETUP; 3047 3048 /* Disable AN and force speed to 10G Serial. */ 3049 status = mac->ops.read_iosf_sb_reg(hw, 3050 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 3051 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3052 if (status != IXGBE_SUCCESS) 3053 return status; 3054 3055 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 3056 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 3057 3058 /* Select forced link speed for internal PHY. */ 3059 switch (*speed) { 3060 case IXGBE_LINK_SPEED_10GB_FULL: 3061 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 3062 break; 3063 case IXGBE_LINK_SPEED_1GB_FULL: 3064 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 3065 break; 3066 default: 3067 /* Other link speeds are not supported by internal KR PHY. */ 3068 return IXGBE_ERR_LINK_SETUP; 3069 } 3070 3071 status = mac->ops.write_iosf_sb_reg(hw, 3072 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 3073 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3074 if (status != IXGBE_SUCCESS) 3075 return status; 3076 3077 /* Additional configuration needed for x550em_x */ 3078 if (hw->mac.type == ixgbe_mac_X550EM_x) { 3079 status = ixgbe_setup_ixfi_x550em_x(hw); 3080 if (status != IXGBE_SUCCESS) 3081 return status; 3082 } 3083 3084 /* Toggle port SW reset by AN reset. */ 3085 status = ixgbe_restart_an_internal_phy_x550em(hw); 3086 3087 return status; 3088 } 3089 3090 /** 3091 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status 3092 * @hw: address of hardware structure 3093 * @link_up: address of boolean to indicate link status 3094 * 3095 * Returns error code if unable to get link status. 3096 */ 3097 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up) 3098 { 3099 u32 ret; 3100 u16 autoneg_status; 3101 3102 *link_up = FALSE; 3103 3104 /* read this twice back to back to indicate current status */ 3105 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 3106 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3107 &autoneg_status); 3108 if (ret != IXGBE_SUCCESS) 3109 return ret; 3110 3111 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 3112 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3113 &autoneg_status); 3114 if (ret != IXGBE_SUCCESS) 3115 return ret; 3116 3117 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS); 3118 3119 return IXGBE_SUCCESS; 3120 } 3121 3122 /** 3123 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link 3124 * @hw: point to hardware structure 3125 * 3126 * Configures the link between the integrated KR PHY and the external X557 PHY 3127 * The driver will call this function when it gets a link status change 3128 * interrupt from the X557 PHY. This function configures the link speed 3129 * between the PHYs to match the link speed of the BASE-T link. 3130 * 3131 * A return of a non-zero value indicates an error, and the base driver should 3132 * not report link up. 3133 */ 3134 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw) 3135 { 3136 ixgbe_link_speed force_speed; 3137 bool link_up; 3138 u32 status; 3139 u16 speed; 3140 3141 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 3142 return IXGBE_ERR_CONFIG; 3143 3144 if (hw->mac.type == ixgbe_mac_X550EM_x && 3145 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 3146 /* If link is down, there is no setup necessary so return */ 3147 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3148 if (status != IXGBE_SUCCESS) 3149 return status; 3150 3151 if (!link_up) 3152 return IXGBE_SUCCESS; 3153 3154 status = hw->phy.ops.read_reg(hw, 3155 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 3156 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3157 &speed); 3158 if (status != IXGBE_SUCCESS) 3159 return status; 3160 3161 /* If link is still down - no setup is required so return */ 3162 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3163 if (status != IXGBE_SUCCESS) 3164 return status; 3165 if (!link_up) 3166 return IXGBE_SUCCESS; 3167 3168 /* clear everything but the speed and duplex bits */ 3169 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK; 3170 3171 switch (speed) { 3172 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL: 3173 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 3174 break; 3175 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL: 3176 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 3177 break; 3178 default: 3179 /* Internal PHY does not support anything else */ 3180 return IXGBE_ERR_INVALID_LINK_SETTINGS; 3181 } 3182 3183 return ixgbe_setup_ixfi_x550em(hw, &force_speed); 3184 } else { 3185 speed = IXGBE_LINK_SPEED_10GB_FULL | 3186 IXGBE_LINK_SPEED_1GB_FULL; 3187 return ixgbe_setup_kr_speed_x550em(hw, speed); 3188 } 3189 } 3190 3191 /** 3192 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback. 3193 * @hw: pointer to hardware structure 3194 * 3195 * Configures the integrated KR PHY to use internal loopback mode. 3196 **/ 3197 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw) 3198 { 3199 s32 status; 3200 u32 reg_val; 3201 3202 /* Disable AN and force speed to 10G Serial. */ 3203 status = hw->mac.ops.read_iosf_sb_reg(hw, 3204 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 3205 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3206 if (status != IXGBE_SUCCESS) 3207 return status; 3208 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 3209 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 3210 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 3211 status = hw->mac.ops.write_iosf_sb_reg(hw, 3212 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 3213 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3214 if (status != IXGBE_SUCCESS) 3215 return status; 3216 3217 /* Set near-end loopback clocks. */ 3218 status = hw->mac.ops.read_iosf_sb_reg(hw, 3219 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id), 3220 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3221 if (status != IXGBE_SUCCESS) 3222 return status; 3223 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B; 3224 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS; 3225 status = hw->mac.ops.write_iosf_sb_reg(hw, 3226 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id), 3227 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3228 if (status != IXGBE_SUCCESS) 3229 return status; 3230 3231 /* Set loopback enable. */ 3232 status = hw->mac.ops.read_iosf_sb_reg(hw, 3233 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id), 3234 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3235 if (status != IXGBE_SUCCESS) 3236 return status; 3237 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK; 3238 status = hw->mac.ops.write_iosf_sb_reg(hw, 3239 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id), 3240 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3241 if (status != IXGBE_SUCCESS) 3242 return status; 3243 3244 /* Training bypass. */ 3245 status = hw->mac.ops.read_iosf_sb_reg(hw, 3246 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 3247 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 3248 if (status != IXGBE_SUCCESS) 3249 return status; 3250 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS; 3251 status = hw->mac.ops.write_iosf_sb_reg(hw, 3252 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 3253 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 3254 3255 return status; 3256 } 3257 3258 /** 3259 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 3260 * assuming that the semaphore is already obtained. 3261 * @hw: pointer to hardware structure 3262 * @offset: offset of word in the EEPROM to read 3263 * @data: word read from the EEPROM 3264 * 3265 * Reads a 16 bit word from the EEPROM using the hostif. 3266 **/ 3267 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data) 3268 { 3269 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 3270 struct ixgbe_hic_read_shadow_ram buffer; 3271 s32 status; 3272 3273 DEBUGFUNC("ixgbe_read_ee_hostif_X550"); 3274 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 3275 buffer.hdr.req.buf_lenh = 0; 3276 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 3277 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 3278 3279 /* convert offset from words to bytes */ 3280 buffer.address = IXGBE_CPU_TO_BE32(offset * 2); 3281 /* one word */ 3282 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16)); 3283 buffer.pad2 = 0; 3284 buffer.pad3 = 0; 3285 3286 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 3287 if (status) 3288 return status; 3289 3290 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 3291 IXGBE_HI_COMMAND_TIMEOUT); 3292 if (!status) { 3293 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 3294 FW_NVM_DATA_OFFSET); 3295 } 3296 3297 hw->mac.ops.release_swfw_sync(hw, mask); 3298 return status; 3299 } 3300 3301 /** 3302 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif 3303 * @hw: pointer to hardware structure 3304 * @offset: offset of word in the EEPROM to read 3305 * @words: number of words 3306 * @data: word(s) read from the EEPROM 3307 * 3308 * Reads a 16 bit word(s) from the EEPROM using the hostif. 3309 **/ 3310 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 3311 u16 offset, u16 words, u16 *data) 3312 { 3313 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 3314 struct ixgbe_hic_read_shadow_ram buffer; 3315 u32 current_word = 0; 3316 u16 words_to_read; 3317 s32 status; 3318 u32 i; 3319 3320 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550"); 3321 3322 /* Take semaphore for the entire operation. */ 3323 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 3324 if (status) { 3325 DEBUGOUT("EEPROM read buffer - semaphore failed\n"); 3326 return status; 3327 } 3328 3329 while (words) { 3330 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 3331 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 3332 else 3333 words_to_read = words; 3334 3335 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 3336 buffer.hdr.req.buf_lenh = 0; 3337 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 3338 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 3339 3340 /* convert offset from words to bytes */ 3341 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2); 3342 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2); 3343 buffer.pad2 = 0; 3344 buffer.pad3 = 0; 3345 3346 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 3347 IXGBE_HI_COMMAND_TIMEOUT); 3348 3349 if (status) { 3350 DEBUGOUT("Host interface command failed\n"); 3351 goto out; 3352 } 3353 3354 for (i = 0; i < words_to_read; i++) { 3355 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + 3356 2 * i; 3357 u32 value = IXGBE_READ_REG(hw, reg); 3358 3359 data[current_word] = (u16)(value & 0xffff); 3360 current_word++; 3361 i++; 3362 if (i < words_to_read) { 3363 value >>= 16; 3364 data[current_word] = (u16)(value & 0xffff); 3365 current_word++; 3366 } 3367 } 3368 words -= words_to_read; 3369 } 3370 3371 out: 3372 hw->mac.ops.release_swfw_sync(hw, mask); 3373 return status; 3374 } 3375 3376 /** 3377 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 3378 * @hw: pointer to hardware structure 3379 * @offset: offset of word in the EEPROM to write 3380 * @data: word write to the EEPROM 3381 * 3382 * Write a 16 bit word to the EEPROM using the hostif. 3383 **/ 3384 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 3385 u16 data) 3386 { 3387 s32 status; 3388 struct ixgbe_hic_write_shadow_ram buffer; 3389 3390 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550"); 3391 3392 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; 3393 buffer.hdr.req.buf_lenh = 0; 3394 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; 3395 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 3396 3397 /* one word */ 3398 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16)); 3399 buffer.data = data; 3400 buffer.address = IXGBE_CPU_TO_BE32(offset * 2); 3401 3402 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 3403 sizeof(buffer), 3404 IXGBE_HI_COMMAND_TIMEOUT, FALSE); 3405 3406 return status; 3407 } 3408 3409 /** 3410 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 3411 * @hw: pointer to hardware structure 3412 * @offset: offset of word in the EEPROM to write 3413 * @data: word write to the EEPROM 3414 * 3415 * Write a 16 bit word to the EEPROM using the hostif. 3416 **/ 3417 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, 3418 u16 data) 3419 { 3420 s32 status = IXGBE_SUCCESS; 3421 3422 DEBUGFUNC("ixgbe_write_ee_hostif_X550"); 3423 3424 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 3425 IXGBE_SUCCESS) { 3426 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); 3427 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 3428 } else { 3429 DEBUGOUT("write ee hostif failed to get semaphore"); 3430 status = IXGBE_ERR_SWFW_SYNC; 3431 } 3432 3433 return status; 3434 } 3435 3436 /** 3437 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif 3438 * @hw: pointer to hardware structure 3439 * @offset: offset of word in the EEPROM to write 3440 * @words: number of words 3441 * @data: word(s) write to the EEPROM 3442 * 3443 * Write a 16 bit word(s) to the EEPROM using the hostif. 3444 **/ 3445 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 3446 u16 offset, u16 words, u16 *data) 3447 { 3448 s32 status = IXGBE_SUCCESS; 3449 u32 i = 0; 3450 3451 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550"); 3452 3453 /* Take semaphore for the entire operation. */ 3454 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 3455 if (status != IXGBE_SUCCESS) { 3456 DEBUGOUT("EEPROM write buffer - semaphore failed\n"); 3457 goto out; 3458 } 3459 3460 for (i = 0; i < words; i++) { 3461 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, 3462 data[i]); 3463 3464 if (status != IXGBE_SUCCESS) { 3465 DEBUGOUT("Eeprom buffered write failed\n"); 3466 break; 3467 } 3468 } 3469 3470 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 3471 out: 3472 3473 return status; 3474 } 3475 3476 /** 3477 * ixgbe_checksum_ptr_x550 - Checksum one pointer region 3478 * @hw: pointer to hardware structure 3479 * @ptr: pointer offset in eeprom 3480 * @size: size of section pointed by ptr, if 0 first word will be used as size 3481 * @csum: address of checksum to update 3482 * 3483 * Returns error status for any failure 3484 */ 3485 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, 3486 u16 size, u16 *csum, u16 *buffer, 3487 u32 buffer_size) 3488 { 3489 u16 buf[256]; 3490 s32 status; 3491 u16 length, bufsz, i, start; 3492 u16 *local_buffer; 3493 3494 bufsz = sizeof(buf) / sizeof(buf[0]); 3495 3496 /* Read a chunk at the pointer location */ 3497 if (!buffer) { 3498 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); 3499 if (status) { 3500 DEBUGOUT("Failed to read EEPROM image\n"); 3501 return status; 3502 } 3503 local_buffer = buf; 3504 } else { 3505 if (buffer_size < ptr) 3506 return IXGBE_ERR_PARAM; 3507 local_buffer = &buffer[ptr]; 3508 } 3509 3510 if (size) { 3511 start = 0; 3512 length = size; 3513 } else { 3514 start = 1; 3515 length = local_buffer[0]; 3516 3517 /* Skip pointer section if length is invalid. */ 3518 if (length == 0xFFFF || length == 0 || 3519 (ptr + length) >= hw->eeprom.word_size) 3520 return IXGBE_SUCCESS; 3521 } 3522 3523 if (buffer && ((u32)start + (u32)length > buffer_size)) 3524 return IXGBE_ERR_PARAM; 3525 3526 for (i = start; length; i++, length--) { 3527 if (i == bufsz && !buffer) { 3528 ptr += bufsz; 3529 i = 0; 3530 if (length < bufsz) 3531 bufsz = length; 3532 3533 /* Read a chunk at the pointer location */ 3534 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, 3535 bufsz, buf); 3536 if (status) { 3537 DEBUGOUT("Failed to read EEPROM image\n"); 3538 return status; 3539 } 3540 } 3541 *csum += local_buffer[i]; 3542 } 3543 return IXGBE_SUCCESS; 3544 } 3545 3546 /** 3547 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum 3548 * @hw: pointer to hardware structure 3549 * @buffer: pointer to buffer containing calculated checksum 3550 * @buffer_size: size of buffer 3551 * 3552 * Returns a negative error code on error, or the 16-bit checksum 3553 **/ 3554 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size) 3555 { 3556 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1]; 3557 u16 *local_buffer; 3558 s32 status; 3559 u16 checksum = 0; 3560 u16 pointer, i, size; 3561 3562 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550"); 3563 3564 hw->eeprom.ops.init_params(hw); 3565 3566 if (!buffer) { 3567 /* Read pointer area */ 3568 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, 3569 IXGBE_EEPROM_LAST_WORD + 1, 3570 eeprom_ptrs); 3571 if (status) { 3572 DEBUGOUT("Failed to read EEPROM image\n"); 3573 return status; 3574 } 3575 local_buffer = eeprom_ptrs; 3576 } else { 3577 if (buffer_size < IXGBE_EEPROM_LAST_WORD) 3578 return IXGBE_ERR_PARAM; 3579 local_buffer = buffer; 3580 } 3581 3582 /* 3583 * For X550 hardware include 0x0-0x41 in the checksum, skip the 3584 * checksum word itself 3585 */ 3586 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++) 3587 if (i != IXGBE_EEPROM_CHECKSUM) 3588 checksum += local_buffer[i]; 3589 3590 /* 3591 * Include all data from pointers 0x3, 0x6-0xE. This excludes the 3592 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 3593 */ 3594 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) { 3595 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 3596 continue; 3597 3598 pointer = local_buffer[i]; 3599 3600 /* Skip pointer section if the pointer is invalid. */ 3601 if (pointer == 0xFFFF || pointer == 0 || 3602 pointer >= hw->eeprom.word_size) 3603 continue; 3604 3605 switch (i) { 3606 case IXGBE_PCIE_GENERAL_PTR: 3607 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE; 3608 break; 3609 case IXGBE_PCIE_CONFIG0_PTR: 3610 case IXGBE_PCIE_CONFIG1_PTR: 3611 size = IXGBE_PCIE_CONFIG_SIZE; 3612 break; 3613 default: 3614 size = 0; 3615 break; 3616 } 3617 3618 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, 3619 buffer, buffer_size); 3620 if (status) 3621 return status; 3622 } 3623 3624 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 3625 3626 return (s32)checksum; 3627 } 3628 3629 /** 3630 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum 3631 * @hw: pointer to hardware structure 3632 * 3633 * Returns a negative error code on error, or the 16-bit checksum 3634 **/ 3635 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) 3636 { 3637 return ixgbe_calc_checksum_X550(hw, NULL, 0); 3638 } 3639 3640 /** 3641 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum 3642 * @hw: pointer to hardware structure 3643 * @checksum_val: calculated checksum 3644 * 3645 * Performs checksum calculation and validates the EEPROM checksum. If the 3646 * caller does not need checksum_val, the value can be NULL. 3647 **/ 3648 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val) 3649 { 3650 s32 status; 3651 u16 checksum; 3652 u16 read_checksum = 0; 3653 3654 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550"); 3655 3656 /* Read the first word from the EEPROM. If this times out or fails, do 3657 * not continue or we could be in for a very long wait while every 3658 * EEPROM read fails 3659 */ 3660 status = hw->eeprom.ops.read(hw, 0, &checksum); 3661 if (status) { 3662 DEBUGOUT("EEPROM read failed\n"); 3663 return status; 3664 } 3665 3666 status = hw->eeprom.ops.calc_checksum(hw); 3667 if (status < 0) 3668 return status; 3669 3670 checksum = (u16)(status & 0xffff); 3671 3672 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 3673 &read_checksum); 3674 if (status) 3675 return status; 3676 3677 /* Verify read checksum from EEPROM is the same as 3678 * calculated checksum 3679 */ 3680 if (read_checksum != checksum) { 3681 status = IXGBE_ERR_EEPROM_CHECKSUM; 3682 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 3683 "Invalid EEPROM checksum"); 3684 } 3685 3686 /* If the user cares, return the calculated checksum */ 3687 if (checksum_val) 3688 *checksum_val = checksum; 3689 3690 return status; 3691 } 3692 3693 /** 3694 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash 3695 * @hw: pointer to hardware structure 3696 * 3697 * After writing EEPROM to shadow RAM using EEWR register, software calculates 3698 * checksum and updates the EEPROM and instructs the hardware to update 3699 * the flash. 3700 **/ 3701 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) 3702 { 3703 s32 status; 3704 u16 checksum = 0; 3705 3706 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550"); 3707 3708 /* Read the first word from the EEPROM. If this times out or fails, do 3709 * not continue or we could be in for a very long wait while every 3710 * EEPROM read fails 3711 */ 3712 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); 3713 if (status) { 3714 DEBUGOUT("EEPROM read failed\n"); 3715 return status; 3716 } 3717 3718 status = ixgbe_calc_eeprom_checksum_X550(hw); 3719 if (status < 0) 3720 return status; 3721 3722 checksum = (u16)(status & 0xffff); 3723 3724 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 3725 checksum); 3726 if (status) 3727 return status; 3728 3729 status = ixgbe_update_flash_X550(hw); 3730 3731 return status; 3732 } 3733 3734 /** 3735 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device 3736 * @hw: pointer to hardware structure 3737 * 3738 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash. 3739 **/ 3740 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) 3741 { 3742 s32 status = IXGBE_SUCCESS; 3743 union ixgbe_hic_hdr2 buffer; 3744 3745 DEBUGFUNC("ixgbe_update_flash_X550"); 3746 3747 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; 3748 buffer.req.buf_lenh = 0; 3749 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; 3750 buffer.req.checksum = FW_DEFAULT_CHECKSUM; 3751 3752 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 3753 sizeof(buffer), 3754 IXGBE_HI_COMMAND_TIMEOUT, FALSE); 3755 3756 return status; 3757 } 3758 3759 /** 3760 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type 3761 * @hw: pointer to hardware structure 3762 * 3763 * Determines physical layer capabilities of the current configuration. 3764 **/ 3765 u64 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw) 3766 { 3767 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 3768 u16 ext_ability = 0; 3769 3770 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em"); 3771 3772 hw->phy.ops.identify(hw); 3773 3774 switch (hw->phy.type) { 3775 case ixgbe_phy_x550em_kr: 3776 if (hw->mac.type == ixgbe_mac_X550EM_a) { 3777 if (hw->phy.nw_mng_if_sel & 3778 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) { 3779 physical_layer = 3780 IXGBE_PHYSICAL_LAYER_2500BASE_KX; 3781 break; 3782 } else if (hw->device_id == 3783 IXGBE_DEV_ID_X550EM_A_KR_L) { 3784 physical_layer = 3785 IXGBE_PHYSICAL_LAYER_1000BASE_KX; 3786 break; 3787 } 3788 } 3789 /* fall through */ 3790 case ixgbe_phy_x550em_xfi: 3791 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR | 3792 IXGBE_PHYSICAL_LAYER_1000BASE_KX; 3793 break; 3794 case ixgbe_phy_x550em_kx4: 3795 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 | 3796 IXGBE_PHYSICAL_LAYER_1000BASE_KX; 3797 break; 3798 case ixgbe_phy_x550em_ext_t: 3799 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 3800 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 3801 &ext_ability); 3802 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 3803 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 3804 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 3805 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 3806 break; 3807 case ixgbe_phy_fw: 3808 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_1GB_FULL) 3809 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 3810 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_100_FULL) 3811 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 3812 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_10_FULL) 3813 physical_layer |= IXGBE_PHYSICAL_LAYER_10BASE_T; 3814 break; 3815 case ixgbe_phy_sgmii: 3816 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; 3817 break; 3818 case ixgbe_phy_ext_1g_t: 3819 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 3820 break; 3821 default: 3822 break; 3823 } 3824 3825 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) 3826 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw); 3827 3828 return physical_layer; 3829 } 3830 3831 /** 3832 * ixgbe_get_bus_info_x550em - Set PCI bus info 3833 * @hw: pointer to hardware structure 3834 * 3835 * Sets bus link width and speed to unknown because X550em is 3836 * not a PCI device. 3837 **/ 3838 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw) 3839 { 3840 3841 DEBUGFUNC("ixgbe_get_bus_info_x550em"); 3842 3843 hw->bus.width = ixgbe_bus_width_unknown; 3844 hw->bus.speed = ixgbe_bus_speed_unknown; 3845 3846 hw->mac.ops.set_lan_id(hw); 3847 3848 return IXGBE_SUCCESS; 3849 } 3850 3851 /** 3852 * ixgbe_disable_rx_x550 - Disable RX unit 3853 * 3854 * Enables the Rx DMA unit for x550 3855 **/ 3856 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) 3857 { 3858 u32 rxctrl, pfdtxgswc; 3859 s32 status; 3860 struct ixgbe_hic_disable_rxen fw_cmd; 3861 3862 DEBUGFUNC("ixgbe_disable_rx_dma_x550"); 3863 3864 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 3865 if (rxctrl & IXGBE_RXCTRL_RXEN) { 3866 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 3867 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 3868 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 3869 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 3870 hw->mac.set_lben = TRUE; 3871 } else { 3872 hw->mac.set_lben = FALSE; 3873 } 3874 3875 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD; 3876 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN; 3877 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 3878 fw_cmd.port_number = (u8)hw->bus.lan_id; 3879 3880 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 3881 sizeof(struct ixgbe_hic_disable_rxen), 3882 IXGBE_HI_COMMAND_TIMEOUT, TRUE); 3883 3884 /* If we fail - disable RX using register write */ 3885 if (status) { 3886 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 3887 if (rxctrl & IXGBE_RXCTRL_RXEN) { 3888 rxctrl &= ~IXGBE_RXCTRL_RXEN; 3889 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 3890 } 3891 } 3892 } 3893 } 3894 3895 /** 3896 * ixgbe_enter_lplu_x550em - Transition to low power states 3897 * @hw: pointer to hardware structure 3898 * 3899 * Configures Low Power Link Up on transition to low power states 3900 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the 3901 * X557 PHY immediately prior to entering LPLU. 3902 **/ 3903 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) 3904 { 3905 u16 an_10g_cntl_reg, autoneg_reg, speed; 3906 s32 status; 3907 ixgbe_link_speed lcd_speed; 3908 u32 save_autoneg; 3909 bool link_up; 3910 3911 /* SW LPLU not required on later HW revisions. */ 3912 if ((hw->mac.type == ixgbe_mac_X550EM_x) && 3913 (IXGBE_FUSES0_REV_MASK & 3914 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))) 3915 return IXGBE_SUCCESS; 3916 3917 /* If blocked by MNG FW, then don't restart AN */ 3918 if (ixgbe_check_reset_blocked(hw)) 3919 return IXGBE_SUCCESS; 3920 3921 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3922 if (status != IXGBE_SUCCESS) 3923 return status; 3924 3925 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3); 3926 3927 if (status != IXGBE_SUCCESS) 3928 return status; 3929 3930 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability 3931 * disabled, then force link down by entering low power mode. 3932 */ 3933 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) || 3934 !(hw->wol_enabled || ixgbe_mng_present(hw))) 3935 return ixgbe_set_copper_phy_power(hw, FALSE); 3936 3937 /* Determine LCD */ 3938 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed); 3939 3940 if (status != IXGBE_SUCCESS) 3941 return status; 3942 3943 /* If no valid LCD link speed, then force link down and exit. */ 3944 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN) 3945 return ixgbe_set_copper_phy_power(hw, FALSE); 3946 3947 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 3948 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3949 &speed); 3950 3951 if (status != IXGBE_SUCCESS) 3952 return status; 3953 3954 /* If no link now, speed is invalid so take link down */ 3955 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3956 if (status != IXGBE_SUCCESS) 3957 return ixgbe_set_copper_phy_power(hw, FALSE); 3958 3959 /* clear everything but the speed bits */ 3960 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK; 3961 3962 /* If current speed is already LCD, then exit. */ 3963 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) && 3964 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) || 3965 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) && 3966 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL))) 3967 return status; 3968 3969 /* Clear AN completed indication */ 3970 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM, 3971 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3972 &autoneg_reg); 3973 3974 if (status != IXGBE_SUCCESS) 3975 return status; 3976 3977 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 3978 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3979 &an_10g_cntl_reg); 3980 3981 if (status != IXGBE_SUCCESS) 3982 return status; 3983 3984 status = hw->phy.ops.read_reg(hw, 3985 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 3986 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3987 &autoneg_reg); 3988 3989 if (status != IXGBE_SUCCESS) 3990 return status; 3991 3992 save_autoneg = hw->phy.autoneg_advertised; 3993 3994 /* Setup link at least common link speed */ 3995 status = hw->mac.ops.setup_link(hw, lcd_speed, FALSE); 3996 3997 /* restore autoneg from before setting lplu speed */ 3998 hw->phy.autoneg_advertised = save_autoneg; 3999 4000 return status; 4001 } 4002 4003 /** 4004 * ixgbe_get_lcd_x550em - Determine lowest common denominator 4005 * @hw: pointer to hardware structure 4006 * @lcd_speed: pointer to lowest common link speed 4007 * 4008 * Determine lowest common link speed with link partner. 4009 **/ 4010 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed) 4011 { 4012 u16 an_lp_status; 4013 s32 status; 4014 u16 word = hw->eeprom.ctrl_word_3; 4015 4016 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN; 4017 4018 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS, 4019 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 4020 &an_lp_status); 4021 4022 if (status != IXGBE_SUCCESS) 4023 return status; 4024 4025 /* If link partner advertised 1G, return 1G */ 4026 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) { 4027 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL; 4028 return status; 4029 } 4030 4031 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */ 4032 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) || 4033 (word & NVM_INIT_CTRL_3_D10GMP_PORT0)) 4034 return status; 4035 4036 /* Link partner not capable of lower speeds, return 10G */ 4037 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL; 4038 return status; 4039 } 4040 4041 /** 4042 * ixgbe_setup_fc_X550em - Set up flow control 4043 * @hw: pointer to hardware structure 4044 * 4045 * Called at init time to set up flow control. 4046 **/ 4047 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw) 4048 { 4049 s32 ret_val = IXGBE_SUCCESS; 4050 u32 pause, asm_dir, reg_val; 4051 4052 DEBUGFUNC("ixgbe_setup_fc_X550em"); 4053 4054 /* Validate the requested mode */ 4055 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 4056 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 4057 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 4058 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4059 goto out; 4060 } 4061 4062 /* 10gig parts do not have a word in the EEPROM to determine the 4063 * default flow control setting, so we explicitly set it to full. 4064 */ 4065 if (hw->fc.requested_mode == ixgbe_fc_default) 4066 hw->fc.requested_mode = ixgbe_fc_full; 4067 4068 /* Determine PAUSE and ASM_DIR bits. */ 4069 switch (hw->fc.requested_mode) { 4070 case ixgbe_fc_none: 4071 pause = 0; 4072 asm_dir = 0; 4073 break; 4074 case ixgbe_fc_tx_pause: 4075 pause = 0; 4076 asm_dir = 1; 4077 break; 4078 case ixgbe_fc_rx_pause: 4079 /* Rx Flow control is enabled and Tx Flow control is 4080 * disabled by software override. Since there really 4081 * isn't a way to advertise that we are capable of RX 4082 * Pause ONLY, we will advertise that we support both 4083 * symmetric and asymmetric Rx PAUSE, as such we fall 4084 * through to the fc_full statement. Later, we will 4085 * disable the adapter's ability to send PAUSE frames. 4086 */ 4087 case ixgbe_fc_full: 4088 pause = 1; 4089 asm_dir = 1; 4090 break; 4091 default: 4092 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 4093 "Flow control param set incorrectly\n"); 4094 ret_val = IXGBE_ERR_CONFIG; 4095 goto out; 4096 } 4097 4098 switch (hw->device_id) { 4099 case IXGBE_DEV_ID_X550EM_X_KR: 4100 case IXGBE_DEV_ID_X550EM_A_KR: 4101 case IXGBE_DEV_ID_X550EM_A_KR_L: 4102 ret_val = hw->mac.ops.read_iosf_sb_reg(hw, 4103 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 4104 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 4105 if (ret_val != IXGBE_SUCCESS) 4106 goto out; 4107 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 4108 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 4109 if (pause) 4110 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 4111 if (asm_dir) 4112 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 4113 ret_val = hw->mac.ops.write_iosf_sb_reg(hw, 4114 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 4115 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 4116 4117 /* This device does not fully support AN. */ 4118 hw->fc.disable_fc_autoneg = TRUE; 4119 break; 4120 case IXGBE_DEV_ID_X550EM_X_XFI: 4121 hw->fc.disable_fc_autoneg = TRUE; 4122 break; 4123 default: 4124 break; 4125 } 4126 4127 out: 4128 return ret_val; 4129 } 4130 4131 /** 4132 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37 4133 * @hw: pointer to hardware structure 4134 * 4135 * Enable flow control according to IEEE clause 37. 4136 **/ 4137 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw) 4138 { 4139 u32 link_s1, lp_an_page_low, an_cntl_1; 4140 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 4141 ixgbe_link_speed speed; 4142 bool link_up; 4143 4144 /* AN should have completed when the cable was plugged in. 4145 * Look for reasons to bail out. Bail out if: 4146 * - FC autoneg is disabled, or if 4147 * - link is not up. 4148 */ 4149 if (hw->fc.disable_fc_autoneg) { 4150 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 4151 "Flow control autoneg is disabled"); 4152 goto out; 4153 } 4154 4155 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 4156 if (!link_up) { 4157 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); 4158 goto out; 4159 } 4160 4161 /* Check at auto-negotiation has completed */ 4162 status = hw->mac.ops.read_iosf_sb_reg(hw, 4163 IXGBE_KRM_LINK_S1(hw->bus.lan_id), 4164 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1); 4165 4166 if (status != IXGBE_SUCCESS || 4167 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) { 4168 DEBUGOUT("Auto-Negotiation did not complete\n"); 4169 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 4170 goto out; 4171 } 4172 4173 /* Read the 10g AN autoc and LP ability registers and resolve 4174 * local flow control settings accordingly 4175 */ 4176 status = hw->mac.ops.read_iosf_sb_reg(hw, 4177 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 4178 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1); 4179 4180 if (status != IXGBE_SUCCESS) { 4181 DEBUGOUT("Auto-Negotiation did not complete\n"); 4182 goto out; 4183 } 4184 4185 status = hw->mac.ops.read_iosf_sb_reg(hw, 4186 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id), 4187 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low); 4188 4189 if (status != IXGBE_SUCCESS) { 4190 DEBUGOUT("Auto-Negotiation did not complete\n"); 4191 goto out; 4192 } 4193 4194 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low, 4195 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE, 4196 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE, 4197 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE, 4198 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE); 4199 4200 out: 4201 if (status == IXGBE_SUCCESS) { 4202 hw->fc.fc_was_autonegged = TRUE; 4203 } else { 4204 hw->fc.fc_was_autonegged = FALSE; 4205 hw->fc.current_mode = hw->fc.requested_mode; 4206 } 4207 } 4208 4209 /** 4210 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings 4211 * @hw: pointer to hardware structure 4212 * 4213 **/ 4214 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw) 4215 { 4216 hw->fc.fc_was_autonegged = FALSE; 4217 hw->fc.current_mode = hw->fc.requested_mode; 4218 } 4219 4220 /** 4221 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37 4222 * @hw: pointer to hardware structure 4223 * 4224 * Enable flow control according to IEEE clause 37. 4225 **/ 4226 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw) 4227 { 4228 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 4229 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 4230 ixgbe_link_speed speed; 4231 bool link_up; 4232 4233 /* AN should have completed when the cable was plugged in. 4234 * Look for reasons to bail out. Bail out if: 4235 * - FC autoneg is disabled, or if 4236 * - link is not up. 4237 */ 4238 if (hw->fc.disable_fc_autoneg) { 4239 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 4240 "Flow control autoneg is disabled"); 4241 goto out; 4242 } 4243 4244 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 4245 if (!link_up) { 4246 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); 4247 goto out; 4248 } 4249 4250 /* Check if auto-negotiation has completed */ 4251 status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info); 4252 if (status != IXGBE_SUCCESS || 4253 !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) { 4254 DEBUGOUT("Auto-Negotiation did not complete\n"); 4255 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 4256 goto out; 4257 } 4258 4259 /* Negotiate the flow control */ 4260 status = ixgbe_negotiate_fc(hw, info[0], info[0], 4261 FW_PHY_ACT_GET_LINK_INFO_FC_RX, 4262 FW_PHY_ACT_GET_LINK_INFO_FC_TX, 4263 FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX, 4264 FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX); 4265 4266 out: 4267 if (status == IXGBE_SUCCESS) { 4268 hw->fc.fc_was_autonegged = TRUE; 4269 } else { 4270 hw->fc.fc_was_autonegged = FALSE; 4271 hw->fc.current_mode = hw->fc.requested_mode; 4272 } 4273 } 4274 4275 /** 4276 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control 4277 * @hw: pointer to hardware structure 4278 * 4279 * Called at init time to set up flow control. 4280 **/ 4281 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw) 4282 { 4283 s32 status = IXGBE_SUCCESS; 4284 u32 an_cntl = 0; 4285 4286 DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a"); 4287 4288 /* Validate the requested mode */ 4289 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 4290 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 4291 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 4292 return IXGBE_ERR_INVALID_LINK_SETTINGS; 4293 } 4294 4295 if (hw->fc.requested_mode == ixgbe_fc_default) 4296 hw->fc.requested_mode = ixgbe_fc_full; 4297 4298 /* Set up the 1G and 10G flow control advertisement registers so the 4299 * HW will be able to do FC autoneg once the cable is plugged in. If 4300 * we link at 10G, the 1G advertisement is harmless and vice versa. 4301 */ 4302 status = hw->mac.ops.read_iosf_sb_reg(hw, 4303 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 4304 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl); 4305 4306 if (status != IXGBE_SUCCESS) { 4307 DEBUGOUT("Auto-Negotiation did not complete\n"); 4308 return status; 4309 } 4310 4311 /* The possible values of fc.requested_mode are: 4312 * 0: Flow control is completely disabled 4313 * 1: Rx flow control is enabled (we can receive pause frames, 4314 * but not send pause frames). 4315 * 2: Tx flow control is enabled (we can send pause frames but 4316 * we do not support receiving pause frames). 4317 * 3: Both Rx and Tx flow control (symmetric) are enabled. 4318 * other: Invalid. 4319 */ 4320 switch (hw->fc.requested_mode) { 4321 case ixgbe_fc_none: 4322 /* Flow control completely disabled by software override. */ 4323 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 4324 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 4325 break; 4326 case ixgbe_fc_tx_pause: 4327 /* Tx Flow control is enabled, and Rx Flow control is 4328 * disabled by software override. 4329 */ 4330 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 4331 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 4332 break; 4333 case ixgbe_fc_rx_pause: 4334 /* Rx Flow control is enabled and Tx Flow control is 4335 * disabled by software override. Since there really 4336 * isn't a way to advertise that we are capable of RX 4337 * Pause ONLY, we will advertise that we support both 4338 * symmetric and asymmetric Rx PAUSE, as such we fall 4339 * through to the fc_full statement. Later, we will 4340 * disable the adapter's ability to send PAUSE frames. 4341 */ 4342 case ixgbe_fc_full: 4343 /* Flow control (both Rx and Tx) is enabled by SW override. */ 4344 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 4345 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 4346 break; 4347 default: 4348 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 4349 "Flow control param set incorrectly\n"); 4350 return IXGBE_ERR_CONFIG; 4351 } 4352 4353 status = hw->mac.ops.write_iosf_sb_reg(hw, 4354 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 4355 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl); 4356 4357 /* Restart auto-negotiation. */ 4358 status = ixgbe_restart_an_internal_phy_x550em(hw); 4359 4360 return status; 4361 } 4362 4363 /** 4364 * ixgbe_set_mux - Set mux for port 1 access with CS4227 4365 * @hw: pointer to hardware structure 4366 * @state: set mux if 1, clear if 0 4367 */ 4368 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state) 4369 { 4370 u32 esdp; 4371 4372 if (!hw->bus.lan_id) 4373 return; 4374 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 4375 if (state) 4376 esdp |= IXGBE_ESDP_SDP1; 4377 else 4378 esdp &= ~IXGBE_ESDP_SDP1; 4379 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4380 IXGBE_WRITE_FLUSH(hw); 4381 } 4382 4383 /** 4384 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore 4385 * @hw: pointer to hardware structure 4386 * @mask: Mask to specify which semaphore to acquire 4387 * 4388 * Acquires the SWFW semaphore and sets the I2C MUX 4389 **/ 4390 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 4391 { 4392 s32 status; 4393 4394 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em"); 4395 4396 status = ixgbe_acquire_swfw_sync_X540(hw, mask); 4397 if (status) 4398 return status; 4399 4400 if (mask & IXGBE_GSSR_I2C_MASK) 4401 ixgbe_set_mux(hw, 1); 4402 4403 return IXGBE_SUCCESS; 4404 } 4405 4406 /** 4407 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore 4408 * @hw: pointer to hardware structure 4409 * @mask: Mask to specify which semaphore to release 4410 * 4411 * Releases the SWFW semaphore and sets the I2C MUX 4412 **/ 4413 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 4414 { 4415 DEBUGFUNC("ixgbe_release_swfw_sync_X550em"); 4416 4417 if (mask & IXGBE_GSSR_I2C_MASK) 4418 ixgbe_set_mux(hw, 0); 4419 4420 ixgbe_release_swfw_sync_X540(hw, mask); 4421 } 4422 4423 /** 4424 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore 4425 * @hw: pointer to hardware structure 4426 * @mask: Mask to specify which semaphore to acquire 4427 * 4428 * Acquires the SWFW semaphore and get the shared phy token as needed 4429 */ 4430 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask) 4431 { 4432 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 4433 int retries = FW_PHY_TOKEN_RETRIES; 4434 s32 status = IXGBE_SUCCESS; 4435 4436 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a"); 4437 4438 while (--retries) { 4439 status = IXGBE_SUCCESS; 4440 if (hmask) 4441 status = ixgbe_acquire_swfw_sync_X540(hw, hmask); 4442 if (status) { 4443 DEBUGOUT1("Could not acquire SWFW semaphore, Status = %d\n", 4444 status); 4445 return status; 4446 } 4447 if (!(mask & IXGBE_GSSR_TOKEN_SM)) 4448 return IXGBE_SUCCESS; 4449 4450 status = ixgbe_get_phy_token(hw); 4451 if (status == IXGBE_ERR_TOKEN_RETRY) 4452 DEBUGOUT1("Could not acquire PHY token, Status = %d\n", 4453 status); 4454 4455 if (status == IXGBE_SUCCESS) 4456 return IXGBE_SUCCESS; 4457 4458 if (hmask) 4459 ixgbe_release_swfw_sync_X540(hw, hmask); 4460 4461 if (status != IXGBE_ERR_TOKEN_RETRY) { 4462 DEBUGOUT1("Unable to retry acquiring the PHY token, Status = %d\n", 4463 status); 4464 return status; 4465 } 4466 } 4467 4468 DEBUGOUT1("Semaphore acquisition retries failed!: PHY ID = 0x%08X\n", 4469 hw->phy.id); 4470 return status; 4471 } 4472 4473 /** 4474 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore 4475 * @hw: pointer to hardware structure 4476 * @mask: Mask to specify which semaphore to release 4477 * 4478 * Releases the SWFW semaphore and puts the shared phy token as needed 4479 */ 4480 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask) 4481 { 4482 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 4483 4484 DEBUGFUNC("ixgbe_release_swfw_sync_X550a"); 4485 4486 if (mask & IXGBE_GSSR_TOKEN_SM) 4487 ixgbe_put_phy_token(hw); 4488 4489 if (hmask) 4490 ixgbe_release_swfw_sync_X540(hw, hmask); 4491 } 4492 4493 /** 4494 * ixgbe_read_phy_reg_x550a - Reads specified PHY register 4495 * @hw: pointer to hardware structure 4496 * @reg_addr: 32 bit address of PHY register to read 4497 * @phy_data: Pointer to read data from PHY register 4498 * 4499 * Reads a value from a specified PHY register using the SWFW lock and PHY 4500 * Token. The PHY Token is needed since the MDIO is shared between to MAC 4501 * instances. 4502 **/ 4503 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 4504 u32 device_type, u16 *phy_data) 4505 { 4506 s32 status; 4507 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 4508 4509 DEBUGFUNC("ixgbe_read_phy_reg_x550a"); 4510 4511 if (hw->mac.ops.acquire_swfw_sync(hw, mask)) 4512 return IXGBE_ERR_SWFW_SYNC; 4513 4514 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 4515 4516 hw->mac.ops.release_swfw_sync(hw, mask); 4517 4518 return status; 4519 } 4520 4521 /** 4522 * ixgbe_write_phy_reg_x550a - Writes specified PHY register 4523 * @hw: pointer to hardware structure 4524 * @reg_addr: 32 bit PHY register to write 4525 * @device_type: 5 bit device type 4526 * @phy_data: Data to write to the PHY register 4527 * 4528 * Writes a value to specified PHY register using the SWFW lock and PHY Token. 4529 * The PHY Token is needed since the MDIO is shared between to MAC instances. 4530 **/ 4531 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 4532 u32 device_type, u16 phy_data) 4533 { 4534 s32 status; 4535 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 4536 4537 DEBUGFUNC("ixgbe_write_phy_reg_x550a"); 4538 4539 if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) { 4540 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, 4541 phy_data); 4542 hw->mac.ops.release_swfw_sync(hw, mask); 4543 } else { 4544 status = IXGBE_ERR_SWFW_SYNC; 4545 } 4546 4547 return status; 4548 } 4549 4550 /** 4551 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt 4552 * @hw: pointer to hardware structure 4553 * 4554 * Handle external Base T PHY interrupt. If high temperature 4555 * failure alarm then return error, else if link status change 4556 * then setup internal/external PHY link 4557 * 4558 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 4559 * failure alarm, else return PHY access status. 4560 */ 4561 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw) 4562 { 4563 bool lsc; 4564 u32 status; 4565 4566 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 4567 4568 if (status != IXGBE_SUCCESS) 4569 return status; 4570 4571 if (lsc) 4572 return ixgbe_setup_internal_phy(hw); 4573 4574 return IXGBE_SUCCESS; 4575 } 4576 4577 /** 4578 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed 4579 * @hw: pointer to hardware structure 4580 * @speed: new link speed 4581 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 4582 * 4583 * Setup internal/external PHY link speed based on link speed, then set 4584 * external PHY auto advertised link speed. 4585 * 4586 * Returns error status for any failure 4587 **/ 4588 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, 4589 ixgbe_link_speed speed, 4590 bool autoneg_wait_to_complete) 4591 { 4592 s32 status; 4593 ixgbe_link_speed force_speed; 4594 4595 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em"); 4596 4597 /* Setup internal/external PHY link speed to iXFI (10G), unless 4598 * only 1G is auto advertised then setup KX link. 4599 */ 4600 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 4601 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 4602 else 4603 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 4604 4605 /* If X552 and internal link mode is XFI, then setup XFI internal link. 4606 */ 4607 if (hw->mac.type == ixgbe_mac_X550EM_x && 4608 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 4609 status = ixgbe_setup_ixfi_x550em(hw, &force_speed); 4610 4611 if (status != IXGBE_SUCCESS) 4612 return status; 4613 } 4614 4615 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); 4616 } 4617 4618 /** 4619 * ixgbe_check_link_t_X550em - Determine link and speed status 4620 * @hw: pointer to hardware structure 4621 * @speed: pointer to link speed 4622 * @link_up: TRUE when link is up 4623 * @link_up_wait_to_complete: bool used to wait for link up or not 4624 * 4625 * Check that both the MAC and X557 external PHY have link. 4626 **/ 4627 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4628 bool *link_up, bool link_up_wait_to_complete) 4629 { 4630 u32 status; 4631 u16 i, autoneg_status = 0; 4632 4633 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 4634 return IXGBE_ERR_CONFIG; 4635 4636 status = ixgbe_check_mac_link_generic(hw, speed, link_up, 4637 link_up_wait_to_complete); 4638 4639 /* If check link fails or MAC link is not up, then return */ 4640 if (status != IXGBE_SUCCESS || !(*link_up)) 4641 return status; 4642 4643 /* MAC link is up, so check external PHY link. 4644 * X557 PHY. Link status is latching low, and can only be used to detect 4645 * link drop, and not the current status of the link without performing 4646 * back-to-back reads. 4647 */ 4648 for (i = 0; i < 2; i++) { 4649 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 4650 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 4651 &autoneg_status); 4652 4653 if (status != IXGBE_SUCCESS) 4654 return status; 4655 } 4656 4657 /* If external PHY link is not up, then indicate link not up */ 4658 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) 4659 *link_up = FALSE; 4660 4661 return IXGBE_SUCCESS; 4662 } 4663 4664 /** 4665 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI 4666 * @hw: pointer to hardware structure 4667 **/ 4668 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw) 4669 { 4670 s32 status; 4671 4672 status = ixgbe_reset_phy_generic(hw); 4673 4674 if (status != IXGBE_SUCCESS) 4675 return status; 4676 4677 /* Configure Link Status Alarm and Temperature Threshold interrupts */ 4678 return ixgbe_enable_lasi_ext_t_x550em(hw); 4679 } 4680 4681 /** 4682 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs. 4683 * @hw: pointer to hardware structure 4684 * @led_idx: led number to turn on 4685 **/ 4686 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx) 4687 { 4688 u16 phy_data; 4689 4690 DEBUGFUNC("ixgbe_led_on_t_X550em"); 4691 4692 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 4693 return IXGBE_ERR_PARAM; 4694 4695 /* To turn on the LED, set mode to ON. */ 4696 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 4697 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data); 4698 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK; 4699 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 4700 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data); 4701 4702 /* Some designs have the LEDs wired to the MAC */ 4703 return ixgbe_led_on_generic(hw, led_idx); 4704 } 4705 4706 /** 4707 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs. 4708 * @hw: pointer to hardware structure 4709 * @led_idx: led number to turn off 4710 **/ 4711 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx) 4712 { 4713 u16 phy_data; 4714 4715 DEBUGFUNC("ixgbe_led_off_t_X550em"); 4716 4717 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 4718 return IXGBE_ERR_PARAM; 4719 4720 /* To turn on the LED, set mode to ON. */ 4721 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 4722 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data); 4723 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK; 4724 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 4725 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data); 4726 4727 /* Some designs have the LEDs wired to the MAC */ 4728 return ixgbe_led_off_generic(hw, led_idx); 4729 } 4730 4731 /** 4732 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware 4733 * @hw: pointer to the HW structure 4734 * @maj: driver version major number 4735 * @min: driver version minor number 4736 * @build: driver version build number 4737 * @sub: driver version sub build number 4738 * @len: length of driver_ver string 4739 * @driver_ver: driver string 4740 * 4741 * Sends driver version number to firmware through the manageability 4742 * block. On success return IXGBE_SUCCESS 4743 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 4744 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4745 **/ 4746 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min, 4747 u8 build, u8 sub, u16 len, const char *driver_ver) 4748 { 4749 struct ixgbe_hic_drv_info2 fw_cmd; 4750 s32 ret_val = IXGBE_SUCCESS; 4751 int i; 4752 4753 DEBUGFUNC("ixgbe_set_fw_drv_ver_x550"); 4754 4755 if ((len == 0) || (driver_ver == NULL) || 4756 (len > sizeof(fw_cmd.driver_string))) 4757 return IXGBE_ERR_INVALID_ARGUMENT; 4758 4759 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 4760 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len; 4761 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 4762 fw_cmd.port_num = (u8)hw->bus.func; 4763 fw_cmd.ver_maj = maj; 4764 fw_cmd.ver_min = min; 4765 fw_cmd.ver_build = build; 4766 fw_cmd.ver_sub = sub; 4767 fw_cmd.hdr.checksum = 0; 4768 memcpy(fw_cmd.driver_string, driver_ver, len); 4769 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 4770 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 4771 4772 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 4773 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 4774 sizeof(fw_cmd), 4775 IXGBE_HI_COMMAND_TIMEOUT, 4776 TRUE); 4777 if (ret_val != IXGBE_SUCCESS) 4778 continue; 4779 4780 if (fw_cmd.hdr.cmd_or_resp.ret_status == 4781 FW_CEM_RESP_STATUS_SUCCESS) 4782 ret_val = IXGBE_SUCCESS; 4783 else 4784 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4785 4786 break; 4787 } 4788 4789 return ret_val; 4790 } 4791
Indexes created Mon Sep 29 21:09:56 GMT 2025