1 /* $NetBSD: njs_pci.c,v 1.13 2018/12/09 11:14:02 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by ITOH Yasufumi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: njs_pci.c,v 1.13 2018/12/09 11:14:02 jdolecek Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 40 #include <sys/bus.h> 41 #include <sys/intr.h> 42 43 #include <dev/scsipi/scsi_all.h> 44 #include <dev/scsipi/scsipi_all.h> 45 #include <dev/scsipi/scsiconf.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcidevs.h> 49 50 #include <dev/ic/ninjascsi32reg.h> 51 #include <dev/ic/ninjascsi32var.h> 52 53 #define NJSC32_PCI_BASEADDR_IO PCI_MAPREG_START 54 #define NJSC32_PCI_BASEADDR_MEM (PCI_MAPREG_START + 4) 55 56 struct njsc32_pci_softc { 57 struct njsc32_softc sc_njsc32; 58 59 pci_chipset_tag_t sc_pc; 60 61 bus_space_handle_t sc_regmaph; 62 bus_size_t sc_regmap_size; 63 }; 64 65 static int njs_pci_match(device_t, cfdata_t, void *); 66 static void njs_pci_attach(device_t, device_t, void *); 67 static int njs_pci_detach(device_t, int); 68 69 CFATTACH_DECL_NEW(njs_pci, sizeof(struct njsc32_pci_softc), 70 njs_pci_match, njs_pci_attach, njs_pci_detach, NULL); 71 72 static const struct njsc32_pci_product { 73 pci_vendor_id_t p_vendor; 74 pci_product_id_t p_product; 75 njsc32_model_t p_model; 76 int p_clk; /* one of NJSC32_CLK_* */ 77 } njsc32_pci_products[] = { 78 { PCI_VENDOR_WORKBIT, PCI_PRODUCT_WORKBIT_NJSC32UDE_IODATA, 79 NJSC32_MODEL_32UDE | NJSC32_FLAG_DUALEDGE, NJSC32_CLK_40M }, 80 { PCI_VENDOR_WORKBIT, PCI_PRODUCT_WORKBIT_NJSC32UDE_LOGITEC, 81 NJSC32_MODEL_32UDE | NJSC32_FLAG_DUALEDGE, NJSC32_CLK_40M }, 82 { PCI_VENDOR_WORKBIT, PCI_PRODUCT_WORKBIT_NJSC32UDE_LOGITEC2, 83 NJSC32_MODEL_32UDE | NJSC32_FLAG_DUALEDGE, NJSC32_CLK_40M }, 84 { PCI_VENDOR_WORKBIT, PCI_PRODUCT_WORKBIT_NJSC32UDE_BUFFALO, 85 NJSC32_MODEL_32UDE | NJSC32_FLAG_DUALEDGE, NJSC32_CLK_40M }, 86 87 { 0, 0, 88 NJSC32_MODEL_INVALID, 0 }, 89 }; 90 91 static const struct njsc32_pci_product * 92 njs_pci_lookup(const struct pci_attach_args *pa) 93 { 94 const struct njsc32_pci_product *p; 95 96 for (p = njsc32_pci_products; 97 p->p_model != NJSC32_MODEL_INVALID; p++) { 98 if (PCI_VENDOR(pa->pa_id) == p->p_vendor && 99 PCI_PRODUCT(pa->pa_id) == p->p_product) 100 return p; 101 } 102 103 return NULL; 104 } 105 106 static int 107 njs_pci_match(device_t parent, cfdata_t match, void *aux) 108 { 109 struct pci_attach_args *pa = aux; 110 111 if (njs_pci_lookup(pa)) 112 return 1; 113 114 return 0; 115 } 116 117 static void 118 njs_pci_attach(device_t parent, device_t self, void *aux) 119 { 120 struct pci_attach_args *pa = aux; 121 struct njsc32_pci_softc *psc = device_private(self); 122 struct njsc32_softc *sc = &psc->sc_njsc32; 123 const struct njsc32_pci_product *prod; 124 pci_intr_handle_t ih; 125 pci_chipset_tag_t pc = pa->pa_pc; 126 pcireg_t reg; 127 const char *str_intr, *str_at; 128 char intrbuf[PCI_INTRSTR_LEN]; 129 130 aprint_naive(": SCSI controller\n"); 131 if ((prod = njs_pci_lookup(pa)) == NULL) 132 panic("njs_pci_attach"); 133 134 aprint_normal(": Workbit NinjaSCSI-32 SCSI adapter\n"); 135 sc->sc_dev = self; 136 sc->sc_model = prod->p_model; 137 sc->sc_clk = prod->p_clk; 138 139 psc->sc_pc = pc; 140 141 /* enable device and DMA */ 142 reg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 143 reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 144 PCI_COMMAND_MASTER_ENABLE; 145 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 146 147 /* 148 * Map registers. 149 * Try memory map first, and then try I/O. 150 */ 151 if (pci_mapreg_map(pa, NJSC32_PCI_BASEADDR_MEM, 152 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 153 &sc->sc_regt, &psc->sc_regmaph, NULL, &psc->sc_regmap_size) == 0) { 154 if (bus_space_subregion(sc->sc_regt, psc->sc_regmaph, 155 NJSC32_MEMOFFSET_REG, NJSC32_REGSIZE, &sc->sc_regh) != 0) { 156 /* failed -- undo map and try I/O */ 157 bus_space_unmap(sc->sc_regt, psc->sc_regmaph, 158 psc->sc_regmap_size); 159 goto try_io; 160 } 161 #ifdef NJSC32_DEBUG 162 printf("%s: memory space mapped\n", device_xname(self)); 163 #endif 164 sc->sc_flags = NJSC32_MEM_MAPPED; 165 } else { 166 try_io: 167 if (pci_mapreg_map(pa, NJSC32_PCI_BASEADDR_IO, 168 PCI_MAPREG_TYPE_IO, 0, &sc->sc_regt, &sc->sc_regh, 169 NULL, &psc->sc_regmap_size) == 0) { 170 #ifdef NJSC32_DEBUG 171 printf("%s: io space mapped\n", device_xname(self)); 172 #endif 173 sc->sc_flags = NJSC32_IO_MAPPED; 174 } else { 175 aprint_error_dev(self, 176 "unable to map device registers\n"); 177 return; 178 } 179 } 180 181 sc->sc_dmat = pa->pa_dmat; 182 183 /* map interrupt */ 184 if (pci_intr_map(pa, &ih)) { 185 aprint_error_dev(self, "couldn't map interrupt\n"); 186 return; 187 } 188 189 str_intr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 190 str_at = " at "; 191 if (str_intr == NULL) 192 str_at = str_intr = ""; 193 194 /* setup interrupt handler */ 195 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_BIO, njsc32_intr, sc, 196 device_xname(self)); 197 if (sc->sc_ih == NULL) { 198 aprint_error_dev(self, "unable to establish interrupt%s%s\n", 199 str_at, str_intr); 200 return; 201 } 202 aprint_normal_dev(self, "interrupting%s%s\n", str_at, str_intr); 203 204 /* attach */ 205 njsc32_attach(sc); 206 } 207 208 static int 209 njs_pci_detach(device_t self, int flags) 210 { 211 struct njsc32_pci_softc *psc = device_private(self); 212 struct njsc32_softc *sc = &psc->sc_njsc32; 213 int rv; 214 215 rv = njsc32_detach(sc, flags); 216 if (rv) 217 return rv; 218 219 if (sc->sc_ih) 220 pci_intr_disestablish(psc->sc_pc, sc->sc_ih); 221 222 if (sc->sc_flags & NJSC32_IO_MAPPED) 223 bus_space_unmap(sc->sc_regt, sc->sc_regh, psc->sc_regmap_size); 224 if (sc->sc_flags & NJSC32_MEM_MAPPED) 225 bus_space_unmap(sc->sc_regt, psc->sc_regmaph, 226 psc->sc_regmap_size); 227 228 return 0; 229 } 230
Indexes created Mon Sep 22 05:09:51 GMT 2025