njs_pci.c revision 1.1
1 /* $NetBSD: njs_pci.c,v 1.1 2004/08/26 14:13:46 itohy Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by ITOH Yasufumi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: njs_pci.c,v 1.1 2004/08/26 14:13:46 itohy Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 47 #include <machine/bus.h> 48 #include <machine/intr.h> 49 50 #include <dev/scsipi/scsi_all.h> 51 #include <dev/scsipi/scsipi_all.h> 52 #include <dev/scsipi/scsiconf.h> 53 54 #include <dev/pci/pcivar.h> 55 #include <dev/pci/pcidevs.h> 56 57 #include <dev/ic/ninjascsi32reg.h> 58 #include <dev/ic/ninjascsi32var.h> 59 60 #define NJSC32_PCI_BASEADDR_IO PCI_MAPREG_START 61 #define NJSC32_PCI_BASEADDR_MEM (PCI_MAPREG_START + 4) 62 63 struct njsc32_pci_softc { 64 struct njsc32_softc sc_njsc32; 65 66 pci_chipset_tag_t sc_pc; 67 68 bus_space_handle_t sc_regmaph; 69 bus_size_t sc_regmap_size; 70 }; 71 72 int njs_pci_match __P((struct device *, struct cfdata *, void *)); 73 void njs_pci_attach __P((struct device *, struct device *, void *)); 74 int njs_pci_detach __P((struct device *, int)); 75 76 CFATTACH_DECL(njs_pci, sizeof(struct njsc32_pci_softc), 77 njs_pci_match, njs_pci_attach, njs_pci_detach, NULL); 78 79 const struct njsc32_pci_product { 80 pci_vendor_id_t p_vendor; 81 pci_product_id_t p_product; 82 njsc32_model_t p_model; 83 int p_clk; /* one of NJSC32_CLK_* */ 84 } njsc32_pci_products[] = { 85 { PCI_VENDOR_WORKBIT, PCI_PRODUCT_WORKBIT_NJSC32UDE_IODATA, 86 NJSC32_MODEL_32UDE | NJSC32_FLAG_DUALEDGE, NJSC32_CLK_40M }, 87 { PCI_VENDOR_WORKBIT, PCI_PRODUCT_WORKBIT_NJSC32UDE_LOGITEC, 88 NJSC32_MODEL_32UDE | NJSC32_FLAG_DUALEDGE, NJSC32_CLK_40M }, 89 { PCI_VENDOR_WORKBIT, PCI_PRODUCT_WORKBIT_NJSC32UDE_LOGITEC2, 90 NJSC32_MODEL_32UDE | NJSC32_FLAG_DUALEDGE, NJSC32_CLK_40M }, 91 { PCI_VENDOR_WORKBIT, PCI_PRODUCT_WORKBIT_NJSC32UDE_BUFFALO, 92 NJSC32_MODEL_32UDE | NJSC32_FLAG_DUALEDGE, NJSC32_CLK_40M }, 93 94 { 0, 0, 95 NJSC32_MODEL_INVALID, 0 }, 96 }; 97 98 const struct njsc32_pci_product * njs_pci_lookup 99 __P((const struct pci_attach_args *)); 100 101 const struct njsc32_pci_product * 102 njs_pci_lookup(pa) 103 const struct pci_attach_args *pa; 104 { 105 const struct njsc32_pci_product *p; 106 107 for (p = njsc32_pci_products; 108 p->p_model != NJSC32_MODEL_INVALID; p++) { 109 if (PCI_VENDOR(pa->pa_id) == p->p_vendor && 110 PCI_PRODUCT(pa->pa_id) == p->p_product) 111 return p; 112 } 113 114 return NULL; 115 } 116 117 int 118 njs_pci_match(parent, match, aux) 119 struct device *parent; 120 struct cfdata *match; 121 void *aux; 122 { 123 struct pci_attach_args *pa = aux; 124 125 if (njs_pci_lookup(pa)) 126 return 1; 127 128 return 0; 129 } 130 131 void 132 njs_pci_attach(parent, self, aux) 133 struct device *parent, *self; 134 void *aux; 135 { 136 struct pci_attach_args *pa = aux; 137 struct njsc32_pci_softc *psc = (void *) self; 138 struct njsc32_softc *sc = &psc->sc_njsc32; 139 const struct njsc32_pci_product *prod; 140 pci_intr_handle_t ih; 141 pci_chipset_tag_t pc = pa->pa_pc; 142 pcireg_t reg; 143 const char *str_intr, *str_at; 144 145 aprint_naive(": SCSI controller\n"); 146 if ((prod = njs_pci_lookup(pa)) == NULL) 147 panic("njs_pci_attach"); 148 149 aprint_normal(": Workbit NinjaSCSI-32 SCSI adapter\n"); 150 sc->sc_model = prod->p_model; 151 sc->sc_clk = prod->p_clk; 152 153 psc->sc_pc = pc; 154 155 /* enable device and DMA */ 156 reg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 157 reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 158 PCI_COMMAND_MASTER_ENABLE; 159 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 160 161 /* 162 * Map registers. 163 * Try memory map first, and then try I/O. 164 */ 165 if (pci_mapreg_map(pa, NJSC32_PCI_BASEADDR_MEM, 166 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 167 &sc->sc_regt, &psc->sc_regmaph, NULL, &psc->sc_regmap_size) == 0) { 168 if (bus_space_subregion(sc->sc_regt, psc->sc_regmaph, 169 NJSC32_MEMOFFSET_REG, NJSC32_REGSIZE, &sc->sc_regh) != 0) { 170 /* failed -- undo map and try I/O */ 171 bus_space_unmap(sc->sc_regt, psc->sc_regmaph, 172 psc->sc_regmap_size); 173 goto try_io; 174 } 175 #ifdef NJSC32_DEBUG 176 printf("%s: memory space mapped\n", sc->sc_dev.dv_xname); 177 #endif 178 sc->sc_flags = NJSC32_MEM_MAPPED; 179 } else { 180 try_io: 181 if (pci_mapreg_map(pa, NJSC32_PCI_BASEADDR_IO, 182 PCI_MAPREG_TYPE_IO, 0, &sc->sc_regt, &sc->sc_regh, 183 NULL, &psc->sc_regmap_size) == 0) { 184 #ifdef NJSC32_DEBUG 185 printf("%s: io space mapped\n", sc->sc_dev.dv_xname); 186 #endif 187 sc->sc_flags = NJSC32_IO_MAPPED; 188 } else { 189 aprint_error("%s: unable to map device registers\n", 190 sc->sc_dev.dv_xname); 191 return; 192 } 193 } 194 195 sc->sc_dmat = pa->pa_dmat; 196 197 /* map interrupt */ 198 if (pci_intr_map(pa, &ih)) { 199 aprint_error("%s: couldn't map interrupt\n", 200 sc->sc_dev.dv_xname); 201 return; 202 } 203 204 str_intr = pci_intr_string(pa->pa_pc, ih); 205 str_at = " at "; 206 if (str_intr == NULL) 207 str_at = str_intr = ""; 208 209 /* setup interrupt handler */ 210 if ((sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, njsc32_intr, sc)) 211 == NULL) { 212 printf("%s: unable to establish interrupt%s%s\n", 213 sc->sc_dev.dv_xname, str_at, str_intr); 214 return; 215 } 216 printf("%s: interrupting%s%s\n", 217 sc->sc_dev.dv_xname, str_at, str_intr); 218 219 /* attach */ 220 njsc32_attach(sc); 221 } 222 223 int 224 njs_pci_detach(self, flags) 225 struct device *self; 226 int flags; 227 { 228 struct njsc32_pci_softc *psc = (void *) self; 229 struct njsc32_softc *sc = &psc->sc_njsc32; 230 int rv; 231 232 rv = njsc32_detach(sc, flags); 233 if (rv) 234 return rv; 235 236 if (sc->sc_ih) 237 pci_intr_disestablish(psc->sc_pc, sc->sc_ih); 238 239 if (sc->sc_flags & NJSC32_IO_MAPPED) 240 bus_space_unmap(sc->sc_regt, sc->sc_regh, psc->sc_regmap_size); 241 if (sc->sc_flags & NJSC32_MEM_MAPPED) 242 bus_space_unmap(sc->sc_regt, psc->sc_regmaph, 243 psc->sc_regmap_size); 244 245 return 0; 246 } 247
Indexes created Wed Sep 24 05:09:52 GMT 2025