1 /* $NetBSD: pccbbvar.h,v 1.41 2010/04/20 23:39:11 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1999 HAYAKAWA Koichi. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* require sys/device.h */ 28 /* require sys/queue.h */ 29 /* require sys/callout.h */ 30 /* require dev/ic/i82365reg.h */ 31 32 #ifndef _DEV_PCI_PCCBBVAR_H_ 33 #define _DEV_PCI_PCCBBVAR_H_ 34 35 #include <sys/mutex.h> 36 #include <sys/condvar.h> 37 38 #define PCIC_FLAG_SOCKETP 0x0001 39 #define PCIC_FLAG_CARDP 0x0002 40 41 /* Chipset ID */ 42 #define CB_UNKNOWN 0 /* NOT Cardbus-PCI bridge */ 43 #define CB_TI113X 1 /* TI PCI1130/1131 */ 44 #define CB_TI12XX 2 /* TI PCI12xx/14xx/44xx/15xx/45xx */ 45 #define CB_RX5C47X 3 /* RICOH RX5C475/476/477 */ 46 #define CB_RX5C46X 4 /* RICOH RX5C465/466/467 */ 47 #define CB_TOPIC95 5 /* Toshiba ToPIC95 */ 48 #define CB_TOPIC95B 6 /* Toshiba ToPIC95B */ 49 #define CB_TOPIC97 7 /* Toshiba ToPIC97 */ 50 #define CB_CIRRUS 8 /* Cirrus Logic CL-PD683X */ 51 #define CB_TI125X 9 /* TI PCI1250/1251(B)/1450 */ 52 #define CB_TI1420 10 /* TI PCI1420 */ 53 #define CB_O2MICRO 11 /* O2 Micro 67xx/68xx/69xx */ 54 55 struct pccbb_intrhand_list; 56 57 struct pccbb_win_chain { 58 bus_addr_t wc_start; /* Caution: region [start, end], */ 59 bus_addr_t wc_end; /* instead of [start, end). */ 60 int wc_flags; 61 bus_space_handle_t wc_handle; 62 TAILQ_ENTRY(pccbb_win_chain) wc_list; 63 }; 64 #define PCCBB_MEM_CACHABLE 1 65 66 TAILQ_HEAD(pccbb_win_chain_head, pccbb_win_chain); 67 68 struct pccbb_softc; /* forward */ 69 struct pcic_handle { 70 /* extracted from i82365var.h */ 71 int memalloc; 72 struct { 73 bus_addr_t addr; 74 bus_size_t size; 75 long offset; 76 int kind; 77 } mem[PCIC_MEM_WINS]; 78 int ioalloc; 79 struct { 80 bus_addr_t addr; 81 bus_size_t size; 82 int width; 83 } io[PCIC_IO_WINS]; 84 }; 85 86 struct pccbb_softc { 87 device_t sc_dev; 88 bus_space_tag_t sc_iot; 89 bus_space_tag_t sc_memt; 90 bus_dma_tag_t sc_dmat; 91 92 rbus_tag_t sc_rbus_iot; /* rbus for i/o donated from parent */ 93 rbus_tag_t sc_rbus_memt; /* rbus for mem donated from parent */ 94 95 bus_space_tag_t sc_base_memt; 96 bus_space_handle_t sc_base_memh; 97 bus_size_t sc_base_size; 98 99 struct callout sc_insert_ch; 100 101 void *sc_ih; /* interrupt handler */ 102 struct pci_attach_args sc_pa; /* copy of our attach args */ 103 u_int32_t sc_flags; 104 #define CBB_CARDEXIST 0x01 105 #define CBB_INSERTING 0x01000000 106 #define CBB_16BITCARD 0x04 107 #define CBB_32BITCARD 0x08 108 #define CBB_MEMHMAPPED 0x02000000 109 #define CBB_SPECMAPPED 0x04000000 /* "special" mapping */ 110 111 pci_chipset_tag_t sc_pc; 112 pcitag_t sc_tag; 113 int sc_chipset; /* chipset id */ 114 115 bus_addr_t sc_mem_start; /* CardBus/PCMCIA memory start */ 116 bus_addr_t sc_mem_end; /* CardBus/PCMCIA memory end */ 117 bus_addr_t sc_io_start; /* CardBus/PCMCIA io start */ 118 bus_addr_t sc_io_end; /* CardBus/PCMCIA io end */ 119 120 /* CardBus stuff */ 121 struct cardslot_softc *sc_csc; 122 123 struct pccbb_win_chain_head sc_memwindow; 124 struct pccbb_win_chain_head sc_iowindow; 125 126 /* pcmcia stuff */ 127 struct pcic_handle sc_pcmcia_h; 128 int sc_pcmcia_flags; 129 #define PCCBB_PCMCIA_IO_RELOC 0x01 /* IO addr relocatable stuff exists */ 130 #define PCCBB_PCMCIA_MEM_32 0x02 /* 32-bit memory address ready */ 131 132 volatile int sc_pwrcycle; 133 kcondvar_t sc_pwr_cv; 134 kmutex_t sc_pwr_mtx; 135 136 /* interrupt handler list on the bridge */ 137 LIST_HEAD(, pccbb_intrhand_list) sc_pil; 138 /* can i call intr handler for child device? */ 139 bool sc_pil_intr_enable; 140 }; 141 142 /* 143 * struct pccbb_intrhand_list holds interrupt handler and argument for 144 * child devices. 145 */ 146 147 struct pccbb_intrhand_list { 148 int (*pil_func)(void *); 149 void *pil_arg; 150 ipl_cookie_t pil_icookie; 151 LIST_ENTRY(pccbb_intrhand_list) pil_next; 152 }; 153 154 void pccbb_intr_route(struct pccbb_softc *sc); 155 156 157 #endif /* _DEV_PCI_PCCBBREG_H_ */ 158
Indexes created Sat Sep 20 22:09:52 GMT 2025