pccbbvar.h revision 1.2.2.2
1 1.2.2.2 bouyer /* $NetBSD: pccbbvar.h,v 1.2.2.2 2000/11/20 11:42:30 bouyer Exp $ */ 2 1.1 haya /* 3 1.1 haya * Copyright (c) 1999 HAYAKAWA Koichi. All rights reserved. 4 1.1 haya * 5 1.1 haya * Redistribution and use in source and binary forms, with or without 6 1.1 haya * modification, are permitted provided that the following conditions 7 1.1 haya * are met: 8 1.1 haya * 1. Redistributions of source code must retain the above copyright 9 1.1 haya * notice, this list of conditions and the following disclaimer. 10 1.1 haya * 2. Redistributions in binary form must reproduce the above copyright 11 1.1 haya * notice, this list of conditions and the following disclaimer in the 12 1.1 haya * documentation and/or other materials provided with the distribution. 13 1.1 haya * 3. All advertising materials mentioning features or use of this software 14 1.1 haya * must display the following acknowledgement: 15 1.1 haya * This product includes software developed by HAYAKAWA Koichi. 16 1.1 haya * 4. The name of the author may not be used to endorse or promote products 17 1.1 haya * derived from this software without specific prior written permission. 18 1.1 haya * 19 1.1 haya * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 1.1 haya * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 1.1 haya * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 1.1 haya * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 1.1 haya * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 1.1 haya * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 1.1 haya * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 1.1 haya * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 1.1 haya * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 1.1 haya * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 1.1 haya */ 30 1.1 haya 31 1.1 haya /* require sys/device.h */ 32 1.1 haya /* require sys/queue.h */ 33 1.2.2.2 bouyer /* require sys/callout.h */ 34 1.1 haya /* require dev/ic/i82365reg.h */ 35 1.1 haya /* require dev/ic/i82365var.h */ 36 1.1 haya 37 1.1 haya #ifndef _DEV_PCI_PCCBBVAR_H_ 38 1.1 haya #define _DEV_PCI_PCCBBVAR_H_ 39 1.1 haya 40 1.1 haya #define PCIC_FLAG_SOCKETP 0x0001 41 1.1 haya #define PCIC_FLAG_CARDP 0x0002 42 1.1 haya 43 1.1 haya /* Chipset ID */ 44 1.2.2.2 bouyer #define CB_UNKNOWN 0 /* NOT Cardbus-PCI bridge */ 45 1.2.2.2 bouyer #define CB_TI113X 1 /* TI PCI1130/1131 */ 46 1.2.2.2 bouyer #define CB_TI12XX 2 /* TI PCI1250/1220 */ 47 1.2.2.2 bouyer #define CB_RX5C47X 3 /* RICOH RX5C475/476/477 */ 48 1.2.2.2 bouyer #define CB_RX5C46X 4 /* RICOH RX5C465/466/467 */ 49 1.2.2.2 bouyer #define CB_TOPIC95 5 /* Toshiba ToPIC95 */ 50 1.2.2.2 bouyer #define CB_TOPIC95B 6 /* Toshiba ToPIC95B */ 51 1.2.2.2 bouyer #define CB_TOPIC97 7 /* Toshiba ToPIC97 */ 52 1.2.2.2 bouyer #define CB_CIRRUS 8 /* Cirrus Logic CL-PD683X */ 53 1.2.2.2 bouyer #define CB_CHIPS_LAST 9 /* Sentinel */ 54 1.1 haya 55 1.1 haya #if 0 56 1.1 haya static char *cb_chipset_name[CB_CHIPS_LAST] = { 57 1.2.2.2 bouyer "unknown", "TI 113X", "TI 12XX", "RF5C47X", "RF5C46X", "ToPIC95", 58 1.2.2.2 bouyer "ToPIC95B", "ToPIC97", "CL-PD 683X", 59 1.1 haya }; 60 1.1 haya #endif 61 1.1 haya 62 1.1 haya struct pccbb_softc; 63 1.2.2.2 bouyer struct pccbb_intrhand_list; 64 1.1 haya 65 1.1 haya 66 1.1 haya struct cbb_pcic_handle { 67 1.2.2.2 bouyer struct device *ph_parent; 68 1.2.2.2 bouyer bus_space_tag_t ph_base_t; 69 1.2.2.2 bouyer bus_space_handle_t ph_base_h; 70 1.2.2.2 bouyer u_int8_t (*ph_read) __P((struct cbb_pcic_handle *, int)); 71 1.2.2.2 bouyer void (*ph_write) __P((struct cbb_pcic_handle *, int, u_int8_t)); 72 1.2.2.2 bouyer int sock; 73 1.2.2.2 bouyer 74 1.2.2.2 bouyer int vendor; 75 1.2.2.2 bouyer int flags; 76 1.2.2.2 bouyer int memalloc; 77 1.2.2.2 bouyer struct { 78 1.2.2.2 bouyer bus_addr_t addr; 79 1.2.2.2 bouyer bus_size_t size; 80 1.2.2.2 bouyer long offset; 81 1.2.2.2 bouyer int kind; 82 1.2.2.2 bouyer } mem[PCIC_MEM_WINS]; 83 1.2.2.2 bouyer int ioalloc; 84 1.2.2.2 bouyer struct { 85 1.2.2.2 bouyer bus_addr_t addr; 86 1.2.2.2 bouyer bus_size_t size; 87 1.2.2.2 bouyer int width; 88 1.2.2.2 bouyer } io[PCIC_IO_WINS]; 89 1.2.2.2 bouyer int ih_irq; 90 1.2.2.2 bouyer struct device *pcmcia; 91 1.1 haya 92 1.2.2.2 bouyer int shutdown; 93 1.1 haya }; 94 1.1 haya 95 1.1 haya struct pccbb_win_chain { 96 1.2.2.2 bouyer bus_addr_t wc_start; /* Caution: region [start, end], */ 97 1.2.2.2 bouyer bus_addr_t wc_end; /* instead of [start, end). */ 98 1.2.2.2 bouyer int wc_flags; 99 1.2.2.2 bouyer bus_space_handle_t wc_handle; 100 1.2.2.2 bouyer TAILQ_ENTRY(pccbb_win_chain) wc_list; 101 1.1 haya }; 102 1.2.2.2 bouyer #define PCCBB_MEM_CACHABLE 1 103 1.1 haya 104 1.2.2.2 bouyer TAILQ_HEAD(pccbb_win_chain_head, pccbb_win_chain); 105 1.1 haya 106 1.1 haya struct pccbb_softc { 107 1.2.2.2 bouyer struct device sc_dev; 108 1.2.2.2 bouyer bus_space_tag_t sc_iot; 109 1.2.2.2 bouyer bus_space_tag_t sc_memt; 110 1.2.2.2 bouyer bus_dma_tag_t sc_dmat; 111 1.1 haya 112 1.1 haya #if rbus 113 1.2.2.2 bouyer rbus_tag_t sc_rbus_iot; /* rbus for i/o donated from parent */ 114 1.2.2.2 bouyer rbus_tag_t sc_rbus_memt; /* rbus for mem donated from parent */ 115 1.1 haya #endif 116 1.1 haya 117 1.2.2.2 bouyer bus_space_tag_t sc_base_memt; 118 1.2.2.2 bouyer bus_space_handle_t sc_base_memh; 119 1.1 haya 120 1.2.2.2 bouyer struct callout sc_insert_ch; 121 1.2.2.2 bouyer 122 1.2.2.2 bouyer void *sc_ih; /* interrupt handler */ 123 1.2.2.2 bouyer int sc_intrline; /* interrupt line */ 124 1.2.2.2 bouyer pcitag_t sc_intrtag; /* copy of pa->pa_intrtag */ 125 1.2.2.2 bouyer pci_intr_pin_t sc_intrpin; /* copy of pa->pa_intrpin */ 126 1.2.2.2 bouyer int sc_function; 127 1.2.2.2 bouyer u_int32_t sc_flags; 128 1.2.2.2 bouyer #define CBB_CARDEXIST 0x01 129 1.2.2.2 bouyer #define CBB_INSERTING 0x01000000 130 1.2.2.2 bouyer #define CBB_16BITCARD 0x04 131 1.2.2.2 bouyer #define CBB_32BITCARD 0x08 132 1.2.2.2 bouyer 133 1.2.2.2 bouyer pci_chipset_tag_t sc_pc; 134 1.2.2.2 bouyer pcitag_t sc_tag; 135 1.2.2.2 bouyer int sc_chipset; /* chipset id */ 136 1.2.2.2 bouyer 137 1.2.2.2 bouyer bus_addr_t sc_mem_start; /* CardBus/PCMCIA memory start */ 138 1.2.2.2 bouyer bus_addr_t sc_mem_end; /* CardBus/PCMCIA memory end */ 139 1.2.2.2 bouyer bus_addr_t sc_io_start; /* CardBus/PCMCIA io start */ 140 1.2.2.2 bouyer bus_addr_t sc_io_end; /* CardBus/PCMCIA io end */ 141 1.2.2.2 bouyer 142 1.2.2.2 bouyer /* CardBus stuff */ 143 1.2.2.2 bouyer struct cardslot_softc *sc_csc; 144 1.2.2.2 bouyer 145 1.2.2.2 bouyer struct pccbb_win_chain_head sc_memwindow; 146 1.2.2.2 bouyer struct pccbb_win_chain_head sc_iowindow; 147 1.2.2.2 bouyer 148 1.2.2.2 bouyer /* pcmcia stuff */ 149 1.2.2.2 bouyer struct pcic_handle sc_pcmcia_h; 150 1.2.2.2 bouyer pcmcia_chipset_tag_t sc_pct; 151 1.2.2.2 bouyer int sc_pcmcia_flags; 152 1.2.2.2 bouyer #define PCCBB_PCMCIA_IO_RELOC 0x01 /* IO addr relocatable stuff exists */ 153 1.2.2.2 bouyer #define PCCBB_PCMCIA_MEM_32 0x02 /* 32-bit memory address ready */ 154 1.2.2.2 bouyer #define PCCBB_PCMCIA_16BITONLY 0x04 /* 32-bit mode disable */ 155 1.2.2.2 bouyer 156 1.2.2.2 bouyer struct proc *sc_event_thread; 157 1.2.2.2 bouyer SIMPLEQ_HEAD(, pcic_event) sc_events; 158 1.2.2.2 bouyer 159 1.2.2.2 bouyer /* interrupt handler list on the bridge */ 160 1.2.2.2 bouyer struct pccbb_intrhand_list *sc_pil; 161 1.2.2.2 bouyer int sc_pil_intr_enable; /* can i call intr handler for child device? */ 162 1.2.2.2 bouyer }; 163 1.2.2.2 bouyer 164 1.2.2.2 bouyer /* 165 1.2.2.2 bouyer * struct pccbb_intrhand_list holds interrupt handler and argument for 166 1.2.2.2 bouyer * child devices. 167 1.2.2.2 bouyer */ 168 1.1 haya 169 1.2.2.2 bouyer struct pccbb_intrhand_list { 170 1.2.2.2 bouyer int (*pil_func) __P((void *)); 171 1.2.2.2 bouyer void *pil_arg; 172 1.2.2.2 bouyer int pil_level; 173 1.2.2.2 bouyer struct pccbb_intrhand_list *pil_next; 174 1.1 haya }; 175 1.1 haya 176 1.1 haya #endif /* _DEV_PCI_PCCBBREG_H_ */ 177
Indexes created Mon Oct 13 21:09:55 GMT 2025