pccbbvar.h revision 1.1
1 /* 2 * Copyright (c) 1999 HAYAKAWA Koichi. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. All advertising materials mentioning features or use of this software 13 * must display the following acknowledgement: 14 * This product includes software developed by HAYAKAWA Koichi. 15 * 4. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* $Id:*/ 31 32 /* require sys/device.h */ 33 /* require sys/queue.h */ 34 /* require dev/ic/i82365reg.h */ 35 /* require dev/ic/i82365var.h */ 36 37 #ifndef _DEV_PCI_PCCBBVAR_H_ 38 #define _DEV_PCI_PCCBBVAR_H_ 39 40 41 #define PCIC_FLAG_SOCKETP 0x0001 42 #define PCIC_FLAG_CARDP 0x0002 43 44 45 46 /* Chipset ID */ 47 #define CB_UNKNOWN 0 /* NOT Cardbus-PCI bridge */ 48 #define CB_TI113X 1 /* TI PCI1130/1131 */ 49 #define CB_TI12XX 2 /* TI PCI1250/1220 */ 50 #define CB_RF5C47X 3 /* RICOH RF5C475/476/477 */ 51 #define CB_RF5C46X 4 /* RICOH RF5C465/466/467 */ 52 #define CB_TOPIC95 5 /* Toshiba ToPIC95 */ 53 #define CB_TOPIC95B 6 /* Toshiba ToPIC95B */ 54 #define CB_TOPIC97 7 /* Toshiba ToPIC97 */ 55 #define CB_CIRRUS 8 /* Cirrus Logic CL-PD683X */ 56 #define CB_CHIPS_LAST 9 /* Sentinel */ 57 58 #if 0 59 static char *cb_chipset_name[CB_CHIPS_LAST] = { 60 "unknown", "TI 113X", "TI 12XX", "RF5C47X", "RF5C46X", "ToPIC95", 61 "ToPIC95B", "ToPIC97", "CL-PD 683X", 62 }; 63 #endif 64 65 struct pccbb_softc; 66 67 #if pccard 68 struct cbb_pcmcia_softc { 69 pccard_chipset_t cpc_ct; 70 struct pccard_softc *cpc_csc; 71 struct pccbb_softc *cpc_parent; 72 u_int8_t cpc_statreg; /* status register */ 73 u_int32_t cpc_regbase; /* base index of the slot */ 74 u_int16_t cpc_flags; 75 bus_space_tag_t cpc_iot; 76 bus_space_handle_t cpc_ioh; 77 }; 78 #endif /* pccard */ 79 80 struct cbb_pcic_handle { 81 struct device *ph_parent; 82 bus_space_tag_t ph_base_t; 83 bus_space_handle_t ph_base_h; 84 u_int8_t (* ph_read) __P((struct cbb_pcic_handle *, int)); 85 void (* ph_write) __P((struct cbb_pcic_handle *, int, u_int8_t)); 86 int sock; 87 88 int vendor; 89 int flags; 90 int memalloc; 91 struct { 92 bus_addr_t addr; 93 bus_size_t size; 94 long offset; 95 int kind; 96 } mem[PCIC_MEM_WINS]; 97 int ioalloc; 98 struct { 99 bus_addr_t addr; 100 bus_size_t size; 101 int width; 102 } io[PCIC_IO_WINS]; 103 int ih_irq; 104 struct device *pcmcia; 105 106 int shutdown; 107 }; 108 109 110 struct pccbb_win_chain { 111 bus_addr_t wc_start; /* Caution: region [start, end], */ 112 bus_addr_t wc_end; /* instead of [start, end). */ 113 int wc_flags; 114 #define PCCBB_MEM_CACHABLE 1 115 bus_space_handle_t wc_handle; 116 struct pccbb_win_chain *wc_next; 117 }; 118 119 120 struct pccbb_softc { 121 struct device sc_dev; 122 bus_space_tag_t sc_iot; 123 bus_space_tag_t sc_memt; 124 bus_dma_tag_t sc_dmat; 125 126 #if rbus 127 rbus_tag_t sc_rbus_iot; /* rbus for i/o donated from parent */ 128 rbus_tag_t sc_rbus_memt; /* rbus for mem donated from parent */ 129 #endif 130 131 bus_space_tag_t sc_base_memt; 132 bus_space_handle_t sc_base_memh; 133 134 void *sc_ih; /* interrupt handler */ 135 int sc_intrline; /* interrupt line */ 136 pcitag_t sc_intrtag; /* copy of pa->pa_intrtag */ 137 pci_intr_pin_t sc_intrpin; /* copy of pa->pa_intrpin */ 138 int sc_function; 139 u_int32_t sc_flags; 140 #define CBB_CARDEXIST 0x01 141 #define CBB_INSERTING 0x01000000 142 #define CBB_16BITCARD 0x04 143 #define CBB_32BITCARD 0x08 144 145 #if pccard 146 struct cbb_pcmcia_softc sc_pcmcia; 147 #endif /* pccard */ 148 pci_chipset_tag_t sc_pc; 149 pcitag_t sc_tag; 150 int sc_chipset; /* chipset id */ 151 152 bus_addr_t sc_mem_start; /* CardBus/PCMCIA memory start */ 153 bus_addr_t sc_mem_end; /* CardBus/PCMCIA memory end */ 154 bus_addr_t sc_io_start; /* CardBus/PCMCIA io start */ 155 bus_addr_t sc_io_end; /* CardBus/PCMCIA io end */ 156 157 /* CardBus stuff */ 158 struct cardslot_softc *sc_csc; 159 160 struct pccbb_win_chain *sc_memwindow; 161 struct pccbb_win_chain *sc_iowindow; 162 163 /* pcmcia stuff */ 164 struct pcic_handle sc_pcmcia_h; 165 pcmcia_chipset_tag_t sc_pct; 166 int sc_pcmcia_flags; 167 #define PCCBB_PCMCIA_IO_RELOC 0x01 /* IO address relocatable stuff exists */ 168 #define PCCBB_PCMCIA_MEM_32 0x02 /* 32-bit memory address ready */ 169 170 struct proc *sc_event_thread; 171 SIMPLEQ_HEAD(, pcic_event) sc_events; 172 }; 173 174 #endif /* _DEV_PCI_PCCBBREG_H_ */ 175
Indexes created Thu Sep 25 16:09:42 GMT 2025