pccbbvar.h revision 1.11
1 /* $NetBSD: pccbbvar.h,v 1.11 2000/03/22 09:35:08 haya Exp $ */ 2 /* 3 * Copyright (c) 1999 HAYAKAWA Koichi. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by HAYAKAWA Koichi. 16 * 4. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* require sys/device.h */ 32 /* require sys/queue.h */ 33 /* require dev/ic/i82365reg.h */ 34 /* require dev/ic/i82365var.h */ 35 36 #ifndef _DEV_PCI_PCCBBVAR_H_ 37 #define _DEV_PCI_PCCBBVAR_H_ 38 39 #define PCIC_FLAG_SOCKETP 0x0001 40 #define PCIC_FLAG_CARDP 0x0002 41 42 /* Chipset ID */ 43 #define CB_UNKNOWN 0 /* NOT Cardbus-PCI bridge */ 44 #define CB_TI113X 1 /* TI PCI1130/1131 */ 45 #define CB_TI12XX 2 /* TI PCI1250/1220 */ 46 #define CB_RX5C47X 3 /* RICOH RX5C475/476/477 */ 47 #define CB_RX5C46X 4 /* RICOH RX5C465/466/467 */ 48 #define CB_TOPIC95 5 /* Toshiba ToPIC95 */ 49 #define CB_TOPIC95B 6 /* Toshiba ToPIC95B */ 50 #define CB_TOPIC97 7 /* Toshiba ToPIC97 */ 51 #define CB_CIRRUS 8 /* Cirrus Logic CL-PD683X */ 52 #define CB_CHIPS_LAST 9 /* Sentinel */ 53 54 #if 0 55 static char *cb_chipset_name[CB_CHIPS_LAST] = { 56 "unknown", "TI 113X", "TI 12XX", "RF5C47X", "RF5C46X", "ToPIC95", 57 "ToPIC95B", "ToPIC97", "CL-PD 683X", 58 }; 59 #endif 60 61 struct pccbb_softc; 62 struct pccbb_intrhand_list; 63 64 65 struct cbb_pcic_handle { 66 struct device *ph_parent; 67 bus_space_tag_t ph_base_t; 68 bus_space_handle_t ph_base_h; 69 u_int8_t (*ph_read) __P((struct cbb_pcic_handle *, int)); 70 void (*ph_write) __P((struct cbb_pcic_handle *, int, u_int8_t)); 71 int sock; 72 73 int vendor; 74 int flags; 75 int memalloc; 76 struct { 77 bus_addr_t addr; 78 bus_size_t size; 79 long offset; 80 int kind; 81 } mem[PCIC_MEM_WINS]; 82 int ioalloc; 83 struct { 84 bus_addr_t addr; 85 bus_size_t size; 86 int width; 87 } io[PCIC_IO_WINS]; 88 int ih_irq; 89 struct device *pcmcia; 90 91 int shutdown; 92 }; 93 94 struct pccbb_win_chain { 95 bus_addr_t wc_start; /* Caution: region [start, end], */ 96 bus_addr_t wc_end; /* instead of [start, end). */ 97 int wc_flags; 98 bus_space_handle_t wc_handle; 99 TAILQ_ENTRY(pccbb_win_chain) wc_list; 100 }; 101 #define PCCBB_MEM_CACHABLE 1 102 103 TAILQ_HEAD(pccbb_win_chain_head, pccbb_win_chain); 104 105 struct pccbb_softc { 106 struct device sc_dev; 107 bus_space_tag_t sc_iot; 108 bus_space_tag_t sc_memt; 109 bus_dma_tag_t sc_dmat; 110 111 #if rbus 112 rbus_tag_t sc_rbus_iot; /* rbus for i/o donated from parent */ 113 rbus_tag_t sc_rbus_memt; /* rbus for mem donated from parent */ 114 #endif 115 116 bus_space_tag_t sc_base_memt; 117 bus_space_handle_t sc_base_memh; 118 119 void *sc_ih; /* interrupt handler */ 120 int sc_intrline; /* interrupt line */ 121 pcitag_t sc_intrtag; /* copy of pa->pa_intrtag */ 122 pci_intr_pin_t sc_intrpin; /* copy of pa->pa_intrpin */ 123 int sc_function; 124 u_int32_t sc_flags; 125 #define CBB_CARDEXIST 0x01 126 #define CBB_INSERTING 0x01000000 127 #define CBB_16BITCARD 0x04 128 #define CBB_32BITCARD 0x08 129 130 pci_chipset_tag_t sc_pc; 131 pcitag_t sc_tag; 132 int sc_chipset; /* chipset id */ 133 134 bus_addr_t sc_mem_start; /* CardBus/PCMCIA memory start */ 135 bus_addr_t sc_mem_end; /* CardBus/PCMCIA memory end */ 136 bus_addr_t sc_io_start; /* CardBus/PCMCIA io start */ 137 bus_addr_t sc_io_end; /* CardBus/PCMCIA io end */ 138 139 /* CardBus stuff */ 140 struct cardslot_softc *sc_csc; 141 142 struct pccbb_win_chain_head sc_memwindow; 143 struct pccbb_win_chain_head sc_iowindow; 144 145 /* pcmcia stuff */ 146 struct pcic_handle sc_pcmcia_h; 147 pcmcia_chipset_tag_t sc_pct; 148 int sc_pcmcia_flags; 149 #define PCCBB_PCMCIA_IO_RELOC 0x01 /* IO addr relocatable stuff exists */ 150 #define PCCBB_PCMCIA_MEM_32 0x02 /* 32-bit memory address ready */ 151 #define PCCBB_PCMCIA_16BITONLY 0x04 /* 32-bit mode disable */ 152 153 struct proc *sc_event_thread; 154 SIMPLEQ_HEAD(, pcic_event) sc_events; 155 156 /* interrupt handler list on the bridge */ 157 struct pccbb_intrhand_list *sc_pil; 158 int sc_pil_intr_enable; /* can i call intr handler for child device? */ 159 }; 160 161 /* 162 * struct pccbb_intrhand_list holds interrupt handler and argument for 163 * child devices. 164 */ 165 166 struct pccbb_intrhand_list { 167 int (*pil_func) __P((void *)); 168 void *pil_arg; 169 struct pccbb_intrhand_list *pil_next; 170 }; 171 172 #endif /* _DEV_PCI_PCCBBREG_H_ */ 173
Indexes created Fri Sep 26 20:09:58 GMT 2025