pccbbvar.h revision 1.18
1 /* $NetBSD: pccbbvar.h,v 1.18 2002/10/01 09:09:16 haya Exp $ */ 2 /* 3 * Copyright (c) 1999 HAYAKAWA Koichi. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by HAYAKAWA Koichi. 16 * 4. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* require sys/device.h */ 32 /* require sys/queue.h */ 33 /* require sys/callout.h */ 34 /* require dev/ic/i82365reg.h */ 35 /* require dev/ic/i82365var.h */ 36 37 #ifndef _DEV_PCI_PCCBBVAR_H_ 38 #define _DEV_PCI_PCCBBVAR_H_ 39 40 #define PCIC_FLAG_SOCKETP 0x0001 41 #define PCIC_FLAG_CARDP 0x0002 42 43 /* Chipset ID */ 44 #define CB_UNKNOWN 0 /* NOT Cardbus-PCI bridge */ 45 #define CB_TI113X 1 /* TI PCI1130/1131 */ 46 #define CB_TI12XX 2 /* TI PCI1250/1220 */ 47 #define CB_RX5C47X 3 /* RICOH RX5C475/476/477 */ 48 #define CB_RX5C46X 4 /* RICOH RX5C465/466/467 */ 49 #define CB_TOPIC95 5 /* Toshiba ToPIC95 */ 50 #define CB_TOPIC95B 6 /* Toshiba ToPIC95B */ 51 #define CB_TOPIC97 7 /* Toshiba ToPIC97 */ 52 #define CB_CIRRUS 8 /* Cirrus Logic CL-PD683X */ 53 #define CB_CHIPS_LAST 9 /* Sentinel */ 54 55 #if 0 56 static char *cb_chipset_name[CB_CHIPS_LAST] = { 57 "unknown", "TI 113X", "TI 12XX", "RF5C47X", "RF5C46X", "ToPIC95", 58 "ToPIC95B", "ToPIC97", "CL-PD 683X", 59 }; 60 #endif 61 62 struct pccbb_softc; 63 struct pccbb_intrhand_list; 64 65 66 struct cbb_pcic_handle { 67 struct device *ph_parent; 68 bus_space_tag_t ph_base_t; 69 bus_space_handle_t ph_base_h; 70 u_int8_t (*ph_read) __P((struct cbb_pcic_handle *, int)); 71 void (*ph_write) __P((struct cbb_pcic_handle *, int, u_int8_t)); 72 int sock; 73 74 int vendor; 75 int flags; 76 int memalloc; 77 struct { 78 bus_addr_t addr; 79 bus_size_t size; 80 long offset; 81 int kind; 82 } mem[PCIC_MEM_WINS]; 83 int ioalloc; 84 struct { 85 bus_addr_t addr; 86 bus_size_t size; 87 int width; 88 } io[PCIC_IO_WINS]; 89 int ih_irq; 90 struct device *pcmcia; 91 92 int shutdown; 93 }; 94 95 struct pccbb_win_chain { 96 bus_addr_t wc_start; /* Caution: region [start, end], */ 97 bus_addr_t wc_end; /* instead of [start, end). */ 98 int wc_flags; 99 bus_space_handle_t wc_handle; 100 TAILQ_ENTRY(pccbb_win_chain) wc_list; 101 }; 102 #define PCCBB_MEM_CACHABLE 1 103 104 TAILQ_HEAD(pccbb_win_chain_head, pccbb_win_chain); 105 106 struct pccbb_softc { 107 struct device sc_dev; 108 bus_space_tag_t sc_iot; 109 bus_space_tag_t sc_memt; 110 bus_dma_tag_t sc_dmat; 111 112 #if rbus 113 rbus_tag_t sc_rbus_iot; /* rbus for i/o donated from parent */ 114 rbus_tag_t sc_rbus_memt; /* rbus for mem donated from parent */ 115 #endif 116 117 bus_space_tag_t sc_base_memt; 118 bus_space_handle_t sc_base_memh; 119 120 struct callout sc_insert_ch; 121 122 void *sc_ih; /* interrupt handler */ 123 struct pci_attach_args sc_pa; /* copy of our attach args */ 124 int sc_function; 125 u_int32_t sc_flags; 126 #define CBB_CARDEXIST 0x01 127 #define CBB_INSERTING 0x01000000 128 #define CBB_16BITCARD 0x04 129 #define CBB_32BITCARD 0x08 130 131 pci_chipset_tag_t sc_pc; 132 pcitag_t sc_tag; 133 int sc_chipset; /* chipset id */ 134 135 bus_addr_t sc_mem_start; /* CardBus/PCMCIA memory start */ 136 bus_addr_t sc_mem_end; /* CardBus/PCMCIA memory end */ 137 bus_addr_t sc_io_start; /* CardBus/PCMCIA io start */ 138 bus_addr_t sc_io_end; /* CardBus/PCMCIA io end */ 139 140 pcireg_t sc_sockbase; /* Socket base register */ 141 pcireg_t sc_busnum; /* bus number */ 142 143 /* CardBus stuff */ 144 struct cardslot_softc *sc_csc; 145 146 struct pccbb_win_chain_head sc_memwindow; 147 struct pccbb_win_chain_head sc_iowindow; 148 149 /* pcmcia stuff */ 150 struct pcic_handle sc_pcmcia_h; 151 pcmcia_chipset_tag_t sc_pct; 152 int sc_pcmcia_flags; 153 #define PCCBB_PCMCIA_IO_RELOC 0x01 /* IO addr relocatable stuff exists */ 154 #define PCCBB_PCMCIA_MEM_32 0x02 /* 32-bit memory address ready */ 155 #define PCCBB_PCMCIA_16BITONLY 0x04 /* 32-bit mode disable */ 156 157 struct proc *sc_event_thread; 158 SIMPLEQ_HEAD(, pcic_event) sc_events; 159 160 /* interrupt handler list on the bridge */ 161 LIST_HEAD(, pccbb_intrhand_list) sc_pil; 162 int sc_pil_intr_enable; /* can i call intr handler for child device? */ 163 164 int sc_pwrmgt_offs; /* Offset for power management capability */ 165 }; 166 167 /* 168 * struct pccbb_intrhand_list holds interrupt handler and argument for 169 * child devices. 170 */ 171 172 struct pccbb_intrhand_list { 173 int (*pil_func) __P((void *)); 174 void *pil_arg; 175 int pil_level; 176 LIST_ENTRY(pccbb_intrhand_list) pil_next; 177 }; 178 179 void pccbb_intr_route __P((struct pccbb_softc *sc)); 180 181 182 #endif /* _DEV_PCI_PCCBBREG_H_ */ 183
Indexes created Thu Sep 25 16:09:42 GMT 2025