pccbbvar.h revision 1.29
1 /* $NetBSD: pccbbvar.h,v 1.29 2007/08/10 22:57:54 dyoung Exp $ */ 2 /* 3 * Copyright (c) 1999 HAYAKAWA Koichi. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by HAYAKAWA Koichi. 16 * 4. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* require sys/device.h */ 32 /* require sys/queue.h */ 33 /* require sys/callout.h */ 34 /* require dev/ic/i82365reg.h */ 35 /* require dev/ic/i82365var.h */ 36 37 #ifndef _DEV_PCI_PCCBBVAR_H_ 38 #define _DEV_PCI_PCCBBVAR_H_ 39 40 #define PCIC_FLAG_SOCKETP 0x0001 41 #define PCIC_FLAG_CARDP 0x0002 42 43 /* Chipset ID */ 44 #define CB_UNKNOWN 0 /* NOT Cardbus-PCI bridge */ 45 #define CB_TI113X 1 /* TI PCI1130/1131 */ 46 #define CB_TI12XX 2 /* TI PCI12xx/14xx/44xx/15xx/45xx */ 47 #define CB_RX5C47X 3 /* RICOH RX5C475/476/477 */ 48 #define CB_RX5C46X 4 /* RICOH RX5C465/466/467 */ 49 #define CB_TOPIC95 5 /* Toshiba ToPIC95 */ 50 #define CB_TOPIC95B 6 /* Toshiba ToPIC95B */ 51 #define CB_TOPIC97 7 /* Toshiba ToPIC97 */ 52 #define CB_CIRRUS 8 /* Cirrus Logic CL-PD683X */ 53 #define CB_TI125X 9 /* TI PCI1250/1251(B)/1450 */ 54 #define CB_TI1420 10 /* TI PCI1420 */ 55 56 struct pccbb_softc; 57 struct pccbb_intrhand_list; 58 59 60 struct cbb_pcic_handle { 61 struct device *ph_parent; 62 bus_space_tag_t ph_base_t; 63 bus_space_handle_t ph_base_h; 64 u_int8_t (*ph_read)(struct cbb_pcic_handle *, int); 65 void (*ph_write)(struct cbb_pcic_handle *, int, u_int8_t); 66 int sock; 67 68 int vendor; 69 int flags; 70 int memalloc; 71 struct { 72 bus_addr_t addr; 73 bus_size_t size; 74 long offset; 75 int kind; 76 } mem[PCIC_MEM_WINS]; 77 int ioalloc; 78 struct { 79 bus_addr_t addr; 80 bus_size_t size; 81 int width; 82 } io[PCIC_IO_WINS]; 83 int ih_irq; 84 struct device *pcmcia; 85 86 int shutdown; 87 }; 88 89 struct pccbb_win_chain { 90 bus_addr_t wc_start; /* Caution: region [start, end], */ 91 bus_addr_t wc_end; /* instead of [start, end). */ 92 int wc_flags; 93 bus_space_handle_t wc_handle; 94 TAILQ_ENTRY(pccbb_win_chain) wc_list; 95 }; 96 #define PCCBB_MEM_CACHABLE 1 97 98 TAILQ_HEAD(pccbb_win_chain_head, pccbb_win_chain); 99 100 struct pccbb_softc { 101 struct device sc_dev; 102 bus_space_tag_t sc_iot; 103 bus_space_tag_t sc_memt; 104 bus_dma_tag_t sc_dmat; 105 106 #if rbus 107 rbus_tag_t sc_rbus_iot; /* rbus for i/o donated from parent */ 108 rbus_tag_t sc_rbus_memt; /* rbus for mem donated from parent */ 109 #endif 110 111 bus_space_tag_t sc_base_memt; 112 bus_space_handle_t sc_base_memh; 113 114 struct callout sc_insert_ch; 115 116 void *sc_ih; /* interrupt handler */ 117 struct pci_attach_args sc_pa; /* copy of our attach args */ 118 int sc_function; 119 u_int32_t sc_flags; 120 #define CBB_CARDEXIST 0x01 121 #define CBB_INSERTING 0x01000000 122 #define CBB_16BITCARD 0x04 123 #define CBB_32BITCARD 0x08 124 #define CBB_MEMHMAPPED 0x02000000 125 126 pci_chipset_tag_t sc_pc; 127 pcitag_t sc_tag; 128 int sc_chipset; /* chipset id */ 129 130 bus_addr_t sc_mem_start; /* CardBus/PCMCIA memory start */ 131 bus_addr_t sc_mem_end; /* CardBus/PCMCIA memory end */ 132 bus_addr_t sc_io_start; /* CardBus/PCMCIA io start */ 133 bus_addr_t sc_io_end; /* CardBus/PCMCIA io end */ 134 135 pcireg_t sc_sockbase; /* Socket base register */ 136 pcireg_t sc_busnum; /* bus number */ 137 138 /* CardBus stuff */ 139 struct cardslot_softc *sc_csc; 140 141 struct pccbb_win_chain_head sc_memwindow; 142 struct pccbb_win_chain_head sc_iowindow; 143 144 /* pcmcia stuff */ 145 struct pcic_handle sc_pcmcia_h; 146 pcmcia_chipset_tag_t sc_pct; 147 int sc_pcmcia_flags; 148 #define PCCBB_PCMCIA_IO_RELOC 0x01 /* IO addr relocatable stuff exists */ 149 #define PCCBB_PCMCIA_MEM_32 0x02 /* 32-bit memory address ready */ 150 151 struct proc *sc_event_thread; 152 SIMPLEQ_HEAD(, pcic_event) sc_events; 153 volatile int sc_pwrcycle; 154 155 /* interrupt handler list on the bridge */ 156 LIST_HEAD(, pccbb_intrhand_list) sc_pil; 157 int sc_pil_intr_enable; /* can i call intr handler for child device? */ 158 159 int sc_pwrmgt_offs; /* Offset for power management capability */ 160 struct pci_conf_state sc_pciconf; 161 pcireg_t sc_ricoh_misc_ctrl; 162 }; 163 164 /* 165 * struct pccbb_intrhand_list holds interrupt handler and argument for 166 * child devices. 167 */ 168 169 struct pccbb_intrhand_list { 170 int (*pil_func)(void *); 171 void *pil_arg; 172 ipl_cookie_t pil_icookie; 173 LIST_ENTRY(pccbb_intrhand_list) pil_next; 174 }; 175 176 void pccbb_intr_route(struct pccbb_softc *sc); 177 178 179 #endif /* _DEV_PCI_PCCBBREG_H_ */ 180
Indexes created Wed Sep 24 05:09:52 GMT 2025