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pccbbvar.h revision 1.35 
      1 /*	$NetBSD: pccbbvar.h,v 1.35 2008/06/25 11:42:32 drochner Exp $	*/
      2 /*
      3  * Copyright (c) 1999 HAYAKAWA Koichi.  All rights reserved.
      4  *
      5  * Redistribution and use in source and binary forms, with or without
      6  * modification, are permitted provided that the following conditions
      7  * are met:
      8  * 1. Redistributions of source code must retain the above copyright
      9  *    notice, this list of conditions and the following disclaimer.
     10  * 2. Redistributions in binary form must reproduce the above copyright
     11  *    notice, this list of conditions and the following disclaimer in the
     12  *    documentation and/or other materials provided with the distribution.
     13  * 3. All advertising materials mentioning features or use of this software
     14  *    must display the following acknowledgement:
     15  *	This product includes software developed by HAYAKAWA Koichi.
     16  * 4. The name of the author may not be used to endorse or promote products
     17  *    derived from this software without specific prior written permission.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     20  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     21  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     22  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     24  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     25  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     26  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     28  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     29  */
     30 
     31 /* require sys/device.h */
     32 /* require sys/queue.h */
     33 /* require sys/callout.h */
     34 /* require dev/ic/i82365reg.h */
     35 /* require dev/ic/i82365var.h */
     36 
     37 #ifndef _DEV_PCI_PCCBBVAR_H_
     38 #define	_DEV_PCI_PCCBBVAR_H_
     39 
     40 #define	PCIC_FLAG_SOCKETP	0x0001
     41 #define	PCIC_FLAG_CARDP		0x0002
     42 
     43 /* Chipset ID */
     44 #define	CB_UNKNOWN	0	/* NOT Cardbus-PCI bridge */
     45 #define	CB_TI113X	1	/* TI PCI1130/1131 */
     46 #define	CB_TI12XX	2	/* TI PCI12xx/14xx/44xx/15xx/45xx */
     47 #define	CB_RX5C47X	3	/* RICOH RX5C475/476/477 */
     48 #define	CB_RX5C46X	4	/* RICOH RX5C465/466/467 */
     49 #define	CB_TOPIC95	5	/* Toshiba ToPIC95 */
     50 #define	CB_TOPIC95B	6	/* Toshiba ToPIC95B */
     51 #define	CB_TOPIC97	7	/* Toshiba ToPIC97 */
     52 #define	CB_CIRRUS	8	/* Cirrus Logic CL-PD683X */
     53 #define	CB_TI125X	9	/* TI PCI1250/1251(B)/1450 */
     54 #define	CB_TI1420	10	/* TI PCI1420 */
     55 #define	CB_O2MICRO	11	/* O2 Micro 67xx/68xx/69xx */
     56 
     57 struct pccbb_intrhand_list;
     58 
     59 struct pccbb_win_chain {
     60 	bus_addr_t wc_start;		/* Caution: region [start, end], */
     61 	bus_addr_t wc_end;		/* instead of [start, end). */
     62 	int wc_flags;
     63 	bus_space_handle_t wc_handle;
     64 	TAILQ_ENTRY(pccbb_win_chain) wc_list;
     65 };
     66 #define	PCCBB_MEM_CACHABLE	1
     67 
     68 TAILQ_HEAD(pccbb_win_chain_head, pccbb_win_chain);
     69 
     70 struct pccbb_softc {
     71 	device_t sc_dev;
     72 	bus_space_tag_t sc_iot;
     73 	bus_space_tag_t sc_memt;
     74 	bus_dma_tag_t sc_dmat;
     75 
     76 #if rbus
     77 	rbus_tag_t sc_rbus_iot;		/* rbus for i/o donated from parent */
     78 	rbus_tag_t sc_rbus_memt;	/* rbus for mem donated from parent */
     79 #endif
     80 
     81 	bus_space_tag_t sc_base_memt;
     82 	bus_space_handle_t sc_base_memh;
     83 	bus_size_t sc_base_size;
     84 
     85 	struct callout sc_insert_ch;
     86 
     87 	void *sc_ih;			/* interrupt handler */
     88 	struct pci_attach_args sc_pa;	/* copy of our attach args */
     89 	int sc_function;
     90 	u_int32_t sc_flags;
     91 #define	CBB_CARDEXIST	0x01
     92 #define	CBB_INSERTING	0x01000000
     93 #define	CBB_16BITCARD	0x04
     94 #define	CBB_32BITCARD	0x08
     95 #define	CBB_MEMHMAPPED	0x02000000
     96 #define	CBB_SPECMAPPED	0x04000000	/* "special" mapping */
     97 
     98 	pci_chipset_tag_t sc_pc;
     99 	pcitag_t sc_tag;
    100 	int sc_chipset;			/* chipset id */
    101 
    102 	bus_addr_t sc_mem_start;	/* CardBus/PCMCIA memory start */
    103 	bus_addr_t sc_mem_end;		/* CardBus/PCMCIA memory end */
    104 	bus_addr_t sc_io_start;		/* CardBus/PCMCIA io start */
    105 	bus_addr_t sc_io_end;		/* CardBus/PCMCIA io end */
    106 
    107 	/* CardBus stuff */
    108 	struct cardslot_softc *sc_csc;
    109 
    110 	struct pccbb_win_chain_head sc_memwindow;
    111 	struct pccbb_win_chain_head sc_iowindow;
    112 
    113 	/* pcmcia stuff */
    114 	struct pcic_handle sc_pcmcia_h;
    115 	pcmcia_chipset_tag_t sc_pct;
    116 	int sc_pcmcia_flags;
    117 #define	PCCBB_PCMCIA_IO_RELOC	0x01	/* IO addr relocatable stuff exists */
    118 #define	PCCBB_PCMCIA_MEM_32	0x02	/* 32-bit memory address ready */
    119 
    120 	struct proc *sc_event_thread;
    121 	SIMPLEQ_HEAD(, pcic_event) sc_events;
    122 	volatile int sc_pwrcycle;
    123 
    124 	/* interrupt handler list on the bridge */
    125 	LIST_HEAD(, pccbb_intrhand_list) sc_pil;
    126 	int sc_pil_intr_enable;	/* can i call intr handler for child device? */
    127 };
    128 
    129 /*
    130  * struct pccbb_intrhand_list holds interrupt handler and argument for
    131  * child devices.
    132  */
    133 
    134 struct pccbb_intrhand_list {
    135 	int (*pil_func)(void *);
    136 	void *pil_arg;
    137 	ipl_cookie_t pil_icookie;
    138 	LIST_ENTRY(pccbb_intrhand_list) pil_next;
    139 };
    140 
    141 void pccbb_intr_route(struct pccbb_softc *sc);
    142 
    143 
    144 #endif /* _DEV_PCI_PCCBBREG_H_ */
    145