pci_map.c revision 1.34 1 1.34 jakllsch /* $NetBSD: pci_map.c,v 1.34 2018/05/16 19:02:00 jakllsch Exp $ */
2 1.1 mycroft
3 1.5 mycroft /*-
4 1.7 thorpej * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
5 1.5 mycroft * All rights reserved.
6 1.5 mycroft *
7 1.5 mycroft * This code is derived from software contributed to The NetBSD Foundation
8 1.7 thorpej * by Charles M. Hannum; by William R. Studenmund; by Jason R. Thorpe.
9 1.1 mycroft *
10 1.1 mycroft * Redistribution and use in source and binary forms, with or without
11 1.1 mycroft * modification, are permitted provided that the following conditions
12 1.1 mycroft * are met:
13 1.1 mycroft * 1. Redistributions of source code must retain the above copyright
14 1.1 mycroft * notice, this list of conditions and the following disclaimer.
15 1.1 mycroft * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 mycroft * notice, this list of conditions and the following disclaimer in the
17 1.1 mycroft * documentation and/or other materials provided with the distribution.
18 1.1 mycroft *
19 1.5 mycroft * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.5 mycroft * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.5 mycroft * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.5 mycroft * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.5 mycroft * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.5 mycroft * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.5 mycroft * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.5 mycroft * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.5 mycroft * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.5 mycroft * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.5 mycroft * POSSIBILITY OF SUCH DAMAGE.
30 1.1 mycroft */
31 1.1 mycroft
32 1.1 mycroft /*
33 1.1 mycroft * PCI device mapping.
34 1.1 mycroft */
35 1.10 lukem
36 1.10 lukem #include <sys/cdefs.h>
37 1.34 jakllsch __KERNEL_RCSID(0, "$NetBSD: pci_map.c,v 1.34 2018/05/16 19:02:00 jakllsch Exp $");
38 1.1 mycroft
39 1.1 mycroft #include <sys/param.h>
40 1.1 mycroft #include <sys/systm.h>
41 1.1 mycroft #include <sys/device.h>
42 1.1 mycroft
43 1.1 mycroft #include <dev/pci/pcireg.h>
44 1.1 mycroft #include <dev/pci/pcivar.h>
45 1.1 mycroft
46 1.1 mycroft static int
47 1.18 christos pci_io_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type,
48 1.9 thorpej bus_addr_t *basep, bus_size_t *sizep, int *flagsp)
49 1.1 mycroft {
50 1.1 mycroft pcireg_t address, mask;
51 1.1 mycroft int s;
52 1.1 mycroft
53 1.8 thorpej if (reg < PCI_MAPREG_START ||
54 1.8 thorpej #if 0
55 1.8 thorpej /*
56 1.8 thorpej * Can't do this check; some devices have mapping registers
57 1.8 thorpej * way out in left field.
58 1.8 thorpej */
59 1.8 thorpej reg >= PCI_MAPREG_END ||
60 1.8 thorpej #endif
61 1.8 thorpej (reg & 3))
62 1.1 mycroft panic("pci_io_find: bad request");
63 1.1 mycroft
64 1.1 mycroft /*
65 1.1 mycroft * Section 6.2.5.1, `Address Maps', tells us that:
66 1.1 mycroft *
67 1.1 mycroft * 1) The builtin software should have already mapped the device in a
68 1.1 mycroft * reasonable way.
69 1.1 mycroft *
70 1.1 mycroft * 2) A device which wants 2^n bytes of memory will hardwire the bottom
71 1.1 mycroft * n bits of the address to 0. As recommended, we write all 1s and see
72 1.1 mycroft * what we get back.
73 1.1 mycroft */
74 1.1 mycroft s = splhigh();
75 1.1 mycroft address = pci_conf_read(pc, tag, reg);
76 1.1 mycroft pci_conf_write(pc, tag, reg, 0xffffffff);
77 1.1 mycroft mask = pci_conf_read(pc, tag, reg);
78 1.1 mycroft pci_conf_write(pc, tag, reg, address);
79 1.1 mycroft splx(s);
80 1.1 mycroft
81 1.1 mycroft if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_IO) {
82 1.22 jmcneill aprint_debug("pci_io_find: expected type i/o, found mem\n");
83 1.25 dyoung return 1;
84 1.1 mycroft }
85 1.1 mycroft
86 1.2 mycroft if (PCI_MAPREG_IO_SIZE(mask) == 0) {
87 1.19 macallan aprint_debug("pci_io_find: void region\n");
88 1.25 dyoung return 1;
89 1.2 mycroft }
90 1.2 mycroft
91 1.25 dyoung if (basep != NULL)
92 1.1 mycroft *basep = PCI_MAPREG_IO_ADDR(address);
93 1.25 dyoung if (sizep != NULL)
94 1.1 mycroft *sizep = PCI_MAPREG_IO_SIZE(mask);
95 1.25 dyoung if (flagsp != NULL)
96 1.1 mycroft *flagsp = 0;
97 1.1 mycroft
98 1.25 dyoung return 0;
99 1.1 mycroft }
100 1.1 mycroft
101 1.1 mycroft static int
102 1.9 thorpej pci_mem_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type,
103 1.9 thorpej bus_addr_t *basep, bus_size_t *sizep, int *flagsp)
104 1.1 mycroft {
105 1.7 thorpej pcireg_t address, mask, address1 = 0, mask1 = 0xffffffff;
106 1.7 thorpej u_int64_t waddress, wmask;
107 1.15 gdamore int s, is64bit, isrom;
108 1.7 thorpej
109 1.7 thorpej is64bit = (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT);
110 1.15 gdamore isrom = (reg == PCI_MAPREG_ROM);
111 1.1 mycroft
112 1.15 gdamore if ((!isrom) && (reg < PCI_MAPREG_START ||
113 1.8 thorpej #if 0
114 1.8 thorpej /*
115 1.8 thorpej * Can't do this check; some devices have mapping registers
116 1.8 thorpej * way out in left field.
117 1.8 thorpej */
118 1.8 thorpej reg >= PCI_MAPREG_END ||
119 1.8 thorpej #endif
120 1.15 gdamore (reg & 3)))
121 1.7 thorpej panic("pci_mem_find: bad request");
122 1.7 thorpej
123 1.7 thorpej if (is64bit && (reg + 4) >= PCI_MAPREG_END)
124 1.7 thorpej panic("pci_mem_find: bad 64-bit request");
125 1.1 mycroft
126 1.1 mycroft /*
127 1.1 mycroft * Section 6.2.5.1, `Address Maps', tells us that:
128 1.1 mycroft *
129 1.1 mycroft * 1) The builtin software should have already mapped the device in a
130 1.1 mycroft * reasonable way.
131 1.1 mycroft *
132 1.1 mycroft * 2) A device which wants 2^n bytes of memory will hardwire the bottom
133 1.1 mycroft * n bits of the address to 0. As recommended, we write all 1s and see
134 1.30 matt * what we get back. Only probe the upper BAR of a mem64 BAR if bit 31
135 1.30 matt * is readonly.
136 1.1 mycroft */
137 1.1 mycroft s = splhigh();
138 1.1 mycroft address = pci_conf_read(pc, tag, reg);
139 1.1 mycroft pci_conf_write(pc, tag, reg, 0xffffffff);
140 1.1 mycroft mask = pci_conf_read(pc, tag, reg);
141 1.1 mycroft pci_conf_write(pc, tag, reg, address);
142 1.7 thorpej if (is64bit) {
143 1.7 thorpej address1 = pci_conf_read(pc, tag, reg + 4);
144 1.30 matt if ((mask & 0x80000000) == 0) {
145 1.30 matt pci_conf_write(pc, tag, reg + 4, 0xffffffff);
146 1.30 matt mask1 = pci_conf_read(pc, tag, reg + 4);
147 1.30 matt pci_conf_write(pc, tag, reg + 4, address1);
148 1.30 matt }
149 1.7 thorpej }
150 1.1 mycroft splx(s);
151 1.1 mycroft
152 1.15 gdamore if (!isrom) {
153 1.15 gdamore /*
154 1.15 gdamore * roms should have an enable bit instead of a memory
155 1.15 gdamore * type decoder bit. For normal BARs, make sure that
156 1.15 gdamore * the address decoder type matches what we asked for.
157 1.15 gdamore */
158 1.15 gdamore if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_MEM) {
159 1.15 gdamore printf("pci_mem_find: expected type mem, found i/o\n");
160 1.25 dyoung return 1;
161 1.15 gdamore }
162 1.21 joerg /* XXX Allow 64bit bars for 32bit requests.*/
163 1.15 gdamore if (PCI_MAPREG_MEM_TYPE(address) !=
164 1.21 joerg PCI_MAPREG_MEM_TYPE(type) &&
165 1.21 joerg PCI_MAPREG_MEM_TYPE(address) !=
166 1.21 joerg PCI_MAPREG_MEM_TYPE_64BIT) {
167 1.15 gdamore printf("pci_mem_find: "
168 1.15 gdamore "expected mem type %08x, found %08x\n",
169 1.15 gdamore PCI_MAPREG_MEM_TYPE(type),
170 1.15 gdamore PCI_MAPREG_MEM_TYPE(address));
171 1.25 dyoung return 1;
172 1.15 gdamore }
173 1.2 mycroft }
174 1.2 mycroft
175 1.7 thorpej waddress = (u_int64_t)address1 << 32UL | address;
176 1.7 thorpej wmask = (u_int64_t)mask1 << 32UL | mask;
177 1.7 thorpej
178 1.11 bouyer if ((is64bit && PCI_MAPREG_MEM64_SIZE(wmask) == 0) ||
179 1.11 bouyer (!is64bit && PCI_MAPREG_MEM_SIZE(mask) == 0)) {
180 1.27 jmcneill aprint_debug("pci_mem_find: void region\n");
181 1.25 dyoung return 1;
182 1.1 mycroft }
183 1.1 mycroft
184 1.1 mycroft switch (PCI_MAPREG_MEM_TYPE(address)) {
185 1.1 mycroft case PCI_MAPREG_MEM_TYPE_32BIT:
186 1.1 mycroft case PCI_MAPREG_MEM_TYPE_32BIT_1M:
187 1.1 mycroft break;
188 1.1 mycroft case PCI_MAPREG_MEM_TYPE_64BIT:
189 1.7 thorpej /*
190 1.7 thorpej * Handle the case of a 64-bit memory register on a
191 1.7 thorpej * platform with 32-bit addressing. Make sure that
192 1.7 thorpej * the address assigned and the device's memory size
193 1.7 thorpej * fit in 32 bits. We implicitly assume that if
194 1.7 thorpej * bus_addr_t is 64-bit, then so is bus_size_t.
195 1.7 thorpej */
196 1.7 thorpej if (sizeof(u_int64_t) > sizeof(bus_addr_t) &&
197 1.7 thorpej (address1 != 0 || mask1 != 0xffffffff)) {
198 1.7 thorpej printf("pci_mem_find: 64-bit memory map which is "
199 1.7 thorpej "inaccessible on a 32-bit platform\n");
200 1.25 dyoung return 1;
201 1.7 thorpej }
202 1.7 thorpej break;
203 1.1 mycroft default:
204 1.1 mycroft printf("pci_mem_find: reserved mapping register type\n");
205 1.25 dyoung return 1;
206 1.1 mycroft }
207 1.1 mycroft
208 1.7 thorpej if (sizeof(u_int64_t) > sizeof(bus_addr_t)) {
209 1.25 dyoung if (basep != NULL)
210 1.7 thorpej *basep = PCI_MAPREG_MEM_ADDR(address);
211 1.25 dyoung if (sizep != NULL)
212 1.7 thorpej *sizep = PCI_MAPREG_MEM_SIZE(mask);
213 1.7 thorpej } else {
214 1.25 dyoung if (basep != NULL)
215 1.7 thorpej *basep = PCI_MAPREG_MEM64_ADDR(waddress);
216 1.25 dyoung if (sizep != NULL)
217 1.7 thorpej *sizep = PCI_MAPREG_MEM64_SIZE(wmask);
218 1.7 thorpej }
219 1.25 dyoung if (flagsp != NULL)
220 1.15 gdamore *flagsp = (isrom || PCI_MAPREG_MEM_PREFETCHABLE(address)) ?
221 1.6 drochner BUS_SPACE_MAP_PREFETCHABLE : 0;
222 1.1 mycroft
223 1.25 dyoung return 0;
224 1.7 thorpej }
225 1.7 thorpej
226 1.12 drochner #define _PCI_MAPREG_TYPEBITS(reg) \
227 1.12 drochner (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO ? \
228 1.12 drochner reg & PCI_MAPREG_TYPE_MASK : \
229 1.12 drochner reg & (PCI_MAPREG_TYPE_MASK|PCI_MAPREG_MEM_TYPE_MASK))
230 1.12 drochner
231 1.7 thorpej pcireg_t
232 1.9 thorpej pci_mapreg_type(pci_chipset_tag_t pc, pcitag_t tag, int reg)
233 1.7 thorpej {
234 1.7 thorpej
235 1.25 dyoung return _PCI_MAPREG_TYPEBITS(pci_conf_read(pc, tag, reg));
236 1.12 drochner }
237 1.12 drochner
238 1.12 drochner int
239 1.12 drochner pci_mapreg_probe(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t *typep)
240 1.12 drochner {
241 1.12 drochner pcireg_t address, mask;
242 1.12 drochner int s;
243 1.13 perry
244 1.12 drochner s = splhigh();
245 1.12 drochner address = pci_conf_read(pc, tag, reg);
246 1.12 drochner pci_conf_write(pc, tag, reg, 0xffffffff);
247 1.12 drochner mask = pci_conf_read(pc, tag, reg);
248 1.12 drochner pci_conf_write(pc, tag, reg, address);
249 1.12 drochner splx(s);
250 1.12 drochner
251 1.12 drochner if (mask == 0) /* unimplemented mapping register */
252 1.25 dyoung return 0;
253 1.12 drochner
254 1.25 dyoung if (typep != NULL)
255 1.12 drochner *typep = _PCI_MAPREG_TYPEBITS(address);
256 1.25 dyoung return 1;
257 1.1 mycroft }
258 1.1 mycroft
259 1.1 mycroft int
260 1.9 thorpej pci_mapreg_info(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type,
261 1.9 thorpej bus_addr_t *basep, bus_size_t *sizep, int *flagsp)
262 1.1 mycroft {
263 1.1 mycroft
264 1.1 mycroft if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO)
265 1.25 dyoung return pci_io_find(pc, tag, reg, type, basep, sizep,
266 1.25 dyoung flagsp);
267 1.1 mycroft else
268 1.25 dyoung return pci_mem_find(pc, tag, reg, type, basep, sizep,
269 1.25 dyoung flagsp);
270 1.1 mycroft }
271 1.1 mycroft
272 1.1 mycroft int
273 1.28 dyoung pci_mapreg_map(const struct pci_attach_args *pa, int reg, pcireg_t type,
274 1.9 thorpej int busflags, bus_space_tag_t *tagp, bus_space_handle_t *handlep,
275 1.9 thorpej bus_addr_t *basep, bus_size_t *sizep)
276 1.1 mycroft {
277 1.24 bjs return pci_mapreg_submap(pa, reg, type, busflags, 0, 0, tagp,
278 1.24 bjs handlep, basep, sizep);
279 1.24 bjs }
280 1.24 bjs
281 1.32 msaitoh int
282 1.28 dyoung pci_mapreg_submap(const struct pci_attach_args *pa, int reg, pcireg_t type,
283 1.33 msaitoh int busflags, bus_size_t reqsize, bus_size_t offset, bus_space_tag_t *tagp,
284 1.24 bjs bus_space_handle_t *handlep, bus_addr_t *basep, bus_size_t *sizep)
285 1.24 bjs {
286 1.1 mycroft bus_space_tag_t tag;
287 1.1 mycroft bus_space_handle_t handle;
288 1.1 mycroft bus_addr_t base;
289 1.33 msaitoh bus_size_t realmaxsize;
290 1.34 jakllsch pcireg_t csr;
291 1.34 jakllsch int flags, s;
292 1.1 mycroft
293 1.1 mycroft if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) {
294 1.29 dyoung if ((pa->pa_flags & PCI_FLAGS_IO_OKAY) == 0)
295 1.25 dyoung return 1;
296 1.34 jakllsch s = splhigh();
297 1.34 jakllsch csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
298 1.34 jakllsch csr |= PCI_COMMAND_IO_ENABLE;
299 1.34 jakllsch pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr);
300 1.34 jakllsch splx(s);
301 1.1 mycroft if (pci_io_find(pa->pa_pc, pa->pa_tag, reg, type, &base,
302 1.33 msaitoh &realmaxsize, &flags))
303 1.25 dyoung return 1;
304 1.1 mycroft tag = pa->pa_iot;
305 1.1 mycroft } else {
306 1.29 dyoung if ((pa->pa_flags & PCI_FLAGS_MEM_OKAY) == 0)
307 1.25 dyoung return 1;
308 1.34 jakllsch s = splhigh();
309 1.34 jakllsch csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
310 1.34 jakllsch csr |= PCI_COMMAND_MEM_ENABLE;
311 1.34 jakllsch pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr);
312 1.34 jakllsch splx(s);
313 1.1 mycroft if (pci_mem_find(pa->pa_pc, pa->pa_tag, reg, type, &base,
314 1.33 msaitoh &realmaxsize, &flags))
315 1.25 dyoung return 1;
316 1.1 mycroft tag = pa->pa_memt;
317 1.1 mycroft }
318 1.1 mycroft
319 1.15 gdamore if (reg == PCI_MAPREG_ROM) {
320 1.15 gdamore pcireg_t mask;
321 1.15 gdamore /* we have to enable the ROM address decoder... */
322 1.15 gdamore s = splhigh();
323 1.15 gdamore mask = pci_conf_read(pa->pa_pc, pa->pa_tag, reg);
324 1.15 gdamore mask |= PCI_MAPREG_ROM_ENABLE;
325 1.15 gdamore pci_conf_write(pa->pa_pc, pa->pa_tag, reg, mask);
326 1.15 gdamore splx(s);
327 1.15 gdamore }
328 1.15 gdamore
329 1.24 bjs /* If we're called with maxsize/offset of 0, behave like
330 1.24 bjs * pci_mapreg_map.
331 1.24 bjs */
332 1.24 bjs
333 1.33 msaitoh reqsize = (reqsize != 0) ? reqsize : realmaxsize;
334 1.24 bjs base += offset;
335 1.24 bjs
336 1.33 msaitoh if (realmaxsize < (offset + reqsize))
337 1.25 dyoung return 1;
338 1.24 bjs
339 1.33 msaitoh if (bus_space_map(tag, base, reqsize, busflags | flags, &handle))
340 1.25 dyoung return 1;
341 1.1 mycroft
342 1.25 dyoung if (tagp != NULL)
343 1.1 mycroft *tagp = tag;
344 1.25 dyoung if (handlep != NULL)
345 1.1 mycroft *handlep = handle;
346 1.25 dyoung if (basep != NULL)
347 1.1 mycroft *basep = base;
348 1.25 dyoung if (sizep != NULL)
349 1.33 msaitoh *sizep = reqsize;
350 1.1 mycroft
351 1.25 dyoung return 0;
352 1.1 mycroft }
353 1.16 gdamore
354 1.16 gdamore int
355 1.28 dyoung pci_find_rom(const struct pci_attach_args *pa, bus_space_tag_t bst,
356 1.31 riastrad bus_space_handle_t bsh, bus_size_t sz, int type,
357 1.31 riastrad bus_space_handle_t *romh, bus_size_t *romsz)
358 1.16 gdamore {
359 1.31 riastrad bus_size_t offset = 0, imagesz;
360 1.16 gdamore uint16_t ptr;
361 1.16 gdamore int done = 0;
362 1.16 gdamore
363 1.16 gdamore /*
364 1.16 gdamore * no upper bound check; i cannot imagine a 4GB ROM, but
365 1.16 gdamore * it appears the spec would allow it!
366 1.16 gdamore */
367 1.31 riastrad if (sz < 1024)
368 1.16 gdamore return 1;
369 1.16 gdamore
370 1.31 riastrad while (offset < sz && !done){
371 1.16 gdamore struct pci_rom_header hdr;
372 1.16 gdamore struct pci_rom rom;
373 1.16 gdamore
374 1.16 gdamore hdr.romh_magic = bus_space_read_2(bst, bsh,
375 1.16 gdamore offset + offsetof (struct pci_rom_header, romh_magic));
376 1.16 gdamore hdr.romh_data_ptr = bus_space_read_2(bst, bsh,
377 1.16 gdamore offset + offsetof (struct pci_rom_header, romh_data_ptr));
378 1.16 gdamore
379 1.16 gdamore /* no warning: quite possibly ROM is simply not populated */
380 1.16 gdamore if (hdr.romh_magic != PCI_ROM_HEADER_MAGIC)
381 1.16 gdamore return 1;
382 1.16 gdamore
383 1.16 gdamore ptr = offset + hdr.romh_data_ptr;
384 1.16 gdamore
385 1.31 riastrad if (ptr > sz) {
386 1.16 gdamore printf("pci_find_rom: rom data ptr out of range\n");
387 1.16 gdamore return 1;
388 1.16 gdamore }
389 1.16 gdamore
390 1.16 gdamore rom.rom_signature = bus_space_read_4(bst, bsh, ptr);
391 1.16 gdamore rom.rom_vendor = bus_space_read_2(bst, bsh, ptr +
392 1.16 gdamore offsetof(struct pci_rom, rom_vendor));
393 1.16 gdamore rom.rom_product = bus_space_read_2(bst, bsh, ptr +
394 1.16 gdamore offsetof(struct pci_rom, rom_product));
395 1.16 gdamore rom.rom_class = bus_space_read_1(bst, bsh,
396 1.16 gdamore ptr + offsetof (struct pci_rom, rom_class));
397 1.16 gdamore rom.rom_subclass = bus_space_read_1(bst, bsh,
398 1.16 gdamore ptr + offsetof (struct pci_rom, rom_subclass));
399 1.16 gdamore rom.rom_interface = bus_space_read_1(bst, bsh,
400 1.16 gdamore ptr + offsetof (struct pci_rom, rom_interface));
401 1.16 gdamore rom.rom_len = bus_space_read_2(bst, bsh,
402 1.16 gdamore ptr + offsetof (struct pci_rom, rom_len));
403 1.16 gdamore rom.rom_code_type = bus_space_read_1(bst, bsh,
404 1.16 gdamore ptr + offsetof (struct pci_rom, rom_code_type));
405 1.16 gdamore rom.rom_indicator = bus_space_read_1(bst, bsh,
406 1.16 gdamore ptr + offsetof (struct pci_rom, rom_indicator));
407 1.16 gdamore
408 1.16 gdamore if (rom.rom_signature != PCI_ROM_SIGNATURE) {
409 1.16 gdamore printf("pci_find_rom: bad rom data signature\n");
410 1.16 gdamore return 1;
411 1.16 gdamore }
412 1.16 gdamore
413 1.16 gdamore imagesz = rom.rom_len * 512;
414 1.16 gdamore
415 1.16 gdamore if ((rom.rom_vendor == PCI_VENDOR(pa->pa_id)) &&
416 1.16 gdamore (rom.rom_product == PCI_PRODUCT(pa->pa_id)) &&
417 1.16 gdamore (rom.rom_class == PCI_CLASS(pa->pa_class)) &&
418 1.16 gdamore (rom.rom_subclass == PCI_SUBCLASS(pa->pa_class)) &&
419 1.16 gdamore (rom.rom_interface == PCI_INTERFACE(pa->pa_class)) &&
420 1.16 gdamore (rom.rom_code_type == type)) {
421 1.31 riastrad *romsz = imagesz;
422 1.16 gdamore bus_space_subregion(bst, bsh, offset, imagesz, romh);
423 1.16 gdamore return 0;
424 1.16 gdamore }
425 1.16 gdamore
426 1.16 gdamore /* last image check */
427 1.16 gdamore if (rom.rom_indicator & PCI_ROM_INDICATOR_LAST)
428 1.16 gdamore return 1;
429 1.16 gdamore
430 1.16 gdamore /* offset by size */
431 1.16 gdamore offset += imagesz;
432 1.16 gdamore }
433 1.16 gdamore return 1;
434 1.16 gdamore }
435