pci_map.c revision 1.24.12.1
1 /* $NetBSD: pci_map.c,v 1.24.12.1 2012/01/03 18:26:25 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; by William R. Studenmund; by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * PCI device mapping. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: pci_map.c,v 1.24.12.1 2012/01/03 18:26:25 matt Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 46 static int 47 pci_io_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type, 48 bus_addr_t *basep, bus_size_t *sizep, int *flagsp) 49 { 50 pcireg_t address, mask; 51 int s; 52 53 if (reg < PCI_MAPREG_START || 54 #if 0 55 /* 56 * Can't do this check; some devices have mapping registers 57 * way out in left field. 58 */ 59 reg >= PCI_MAPREG_END || 60 #endif 61 (reg & 3)) 62 panic("pci_io_find: bad request"); 63 64 /* 65 * Section 6.2.5.1, `Address Maps', tells us that: 66 * 67 * 1) The builtin software should have already mapped the device in a 68 * reasonable way. 69 * 70 * 2) A device which wants 2^n bytes of memory will hardwire the bottom 71 * n bits of the address to 0. As recommended, we write all 1s and see 72 * what we get back. 73 */ 74 s = splhigh(); 75 address = pci_conf_read(pc, tag, reg); 76 pci_conf_write(pc, tag, reg, 0xffffffff); 77 mask = pci_conf_read(pc, tag, reg); 78 pci_conf_write(pc, tag, reg, address); 79 splx(s); 80 81 if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_IO) { 82 aprint_debug("pci_io_find: expected type i/o, found mem\n"); 83 return (1); 84 } 85 86 if (PCI_MAPREG_IO_SIZE(mask) == 0) { 87 aprint_debug("pci_io_find: void region\n"); 88 return (1); 89 } 90 91 if (basep != 0) 92 *basep = PCI_MAPREG_IO_ADDR(address); 93 if (sizep != 0) 94 *sizep = PCI_MAPREG_IO_SIZE(mask); 95 if (flagsp != 0) 96 *flagsp = 0; 97 98 return (0); 99 } 100 101 static int 102 pci_mem_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type, 103 bus_addr_t *basep, bus_size_t *sizep, int *flagsp) 104 { 105 pcireg_t address, mask, address1 = 0, mask1 = 0xffffffff; 106 u_int64_t waddress, wmask; 107 int s, is64bit, isrom; 108 109 is64bit = (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT); 110 isrom = (reg == PCI_MAPREG_ROM); 111 112 if ((!isrom) && (reg < PCI_MAPREG_START || 113 #if 0 114 /* 115 * Can't do this check; some devices have mapping registers 116 * way out in left field. 117 */ 118 reg >= PCI_MAPREG_END || 119 #endif 120 (reg & 3))) 121 panic("pci_mem_find: bad request"); 122 123 if (is64bit && (reg + 4) >= PCI_MAPREG_END) 124 panic("pci_mem_find: bad 64-bit request"); 125 126 /* 127 * Section 6.2.5.1, `Address Maps', tells us that: 128 * 129 * 1) The builtin software should have already mapped the device in a 130 * reasonable way. 131 * 132 * 2) A device which wants 2^n bytes of memory will hardwire the bottom 133 * n bits of the address to 0. As recommended, we write all 1s and see 134 * what we get back. Only probe the upper BAR of a mem64 BAR if bit 31 135 * is readonly. 136 */ 137 s = splhigh(); 138 address = pci_conf_read(pc, tag, reg); 139 pci_conf_write(pc, tag, reg, 0xffffffff); 140 mask = pci_conf_read(pc, tag, reg); 141 pci_conf_write(pc, tag, reg, address); 142 if (is64bit) { 143 address1 = pci_conf_read(pc, tag, reg + 4); 144 if ((mask & 0x80000000) == 0) { 145 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 146 mask1 = pci_conf_read(pc, tag, reg + 4); 147 pci_conf_write(pc, tag, reg + 4, address1); 148 } 149 } 150 splx(s); 151 152 if (!isrom) { 153 /* 154 * roms should have an enable bit instead of a memory 155 * type decoder bit. For normal BARs, make sure that 156 * the address decoder type matches what we asked for. 157 */ 158 if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_MEM) { 159 printf("pci_mem_find: expected type mem, found i/o\n"); 160 return (1); 161 } 162 /* XXX Allow 64bit bars for 32bit requests.*/ 163 if (PCI_MAPREG_MEM_TYPE(address) != 164 PCI_MAPREG_MEM_TYPE(type) && 165 PCI_MAPREG_MEM_TYPE(address) != 166 PCI_MAPREG_MEM_TYPE_64BIT) { 167 printf("pci_mem_find: " 168 "expected mem type %08x, found %08x\n", 169 PCI_MAPREG_MEM_TYPE(type), 170 PCI_MAPREG_MEM_TYPE(address)); 171 return (1); 172 } 173 } 174 175 waddress = (u_int64_t)address1 << 32UL | address; 176 wmask = (u_int64_t)mask1 << 32UL | mask; 177 178 if ((is64bit && PCI_MAPREG_MEM64_SIZE(wmask) == 0) || 179 (!is64bit && PCI_MAPREG_MEM_SIZE(mask) == 0)) { 180 aprint_debug("pci_mem_find: void region\n"); 181 return (1); 182 } 183 184 switch (PCI_MAPREG_MEM_TYPE(address)) { 185 case PCI_MAPREG_MEM_TYPE_32BIT: 186 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 187 break; 188 case PCI_MAPREG_MEM_TYPE_64BIT: 189 /* 190 * Handle the case of a 64-bit memory register on a 191 * platform with 32-bit addressing. Make sure that 192 * the address assigned and the device's memory size 193 * fit in 32 bits. We implicitly assume that if 194 * bus_addr_t is 64-bit, then so is bus_size_t. 195 */ 196 if (sizeof(u_int64_t) > sizeof(bus_addr_t) && 197 (address1 != 0 || mask1 != 0xffffffff)) { 198 printf("pci_mem_find: 64-bit memory map which is " 199 "inaccessible on a 32-bit platform\n"); 200 return (1); 201 } 202 break; 203 default: 204 printf("pci_mem_find: reserved mapping register type\n"); 205 return (1); 206 } 207 208 if (sizeof(u_int64_t) > sizeof(bus_addr_t)) { 209 if (basep != 0) 210 *basep = PCI_MAPREG_MEM_ADDR(address); 211 if (sizep != 0) 212 *sizep = PCI_MAPREG_MEM_SIZE(mask); 213 } else { 214 if (basep != 0) 215 *basep = PCI_MAPREG_MEM64_ADDR(waddress); 216 if (sizep != 0) 217 *sizep = PCI_MAPREG_MEM64_SIZE(wmask); 218 } 219 if (flagsp != 0) 220 *flagsp = (isrom || PCI_MAPREG_MEM_PREFETCHABLE(address)) ? 221 BUS_SPACE_MAP_PREFETCHABLE : 0; 222 223 return (0); 224 } 225 226 #define _PCI_MAPREG_TYPEBITS(reg) \ 227 (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO ? \ 228 reg & PCI_MAPREG_TYPE_MASK : \ 229 reg & (PCI_MAPREG_TYPE_MASK|PCI_MAPREG_MEM_TYPE_MASK)) 230 231 pcireg_t 232 pci_mapreg_type(pci_chipset_tag_t pc, pcitag_t tag, int reg) 233 { 234 235 return (_PCI_MAPREG_TYPEBITS(pci_conf_read(pc, tag, reg))); 236 } 237 238 int 239 pci_mapreg_probe(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t *typep) 240 { 241 pcireg_t address, mask; 242 int s; 243 244 s = splhigh(); 245 address = pci_conf_read(pc, tag, reg); 246 pci_conf_write(pc, tag, reg, 0xffffffff); 247 mask = pci_conf_read(pc, tag, reg); 248 pci_conf_write(pc, tag, reg, address); 249 splx(s); 250 251 if (mask == 0) /* unimplemented mapping register */ 252 return (0); 253 254 if (typep) 255 *typep = _PCI_MAPREG_TYPEBITS(address); 256 return (1); 257 } 258 259 int 260 pci_mapreg_info(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type, 261 bus_addr_t *basep, bus_size_t *sizep, int *flagsp) 262 { 263 264 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) 265 return (pci_io_find(pc, tag, reg, type, basep, sizep, 266 flagsp)); 267 else 268 return (pci_mem_find(pc, tag, reg, type, basep, sizep, 269 flagsp)); 270 } 271 272 int 273 pci_mapreg_map(struct pci_attach_args *pa, int reg, pcireg_t type, 274 int busflags, bus_space_tag_t *tagp, bus_space_handle_t *handlep, 275 bus_addr_t *basep, bus_size_t *sizep) 276 { 277 return pci_mapreg_submap(pa, reg, type, busflags, 0, 0, tagp, 278 handlep, basep, sizep); 279 } 280 281 int 282 pci_mapreg_submap(struct pci_attach_args *pa, int reg, pcireg_t type, 283 int busflags, bus_size_t maxsize, bus_size_t offset, bus_space_tag_t *tagp, 284 bus_space_handle_t *handlep, bus_addr_t *basep, bus_size_t *sizep) 285 { 286 bus_space_tag_t tag; 287 bus_space_handle_t handle; 288 bus_addr_t base; 289 bus_size_t size; 290 int flags; 291 292 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) { 293 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) 294 return (1); 295 if (pci_io_find(pa->pa_pc, pa->pa_tag, reg, type, &base, 296 &size, &flags)) 297 return (1); 298 tag = pa->pa_iot; 299 } else { 300 if ((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) == 0) 301 return (1); 302 if (pci_mem_find(pa->pa_pc, pa->pa_tag, reg, type, &base, 303 &size, &flags)) 304 return (1); 305 tag = pa->pa_memt; 306 } 307 308 if (reg == PCI_MAPREG_ROM) { 309 pcireg_t mask; 310 int s; 311 /* we have to enable the ROM address decoder... */ 312 s = splhigh(); 313 mask = pci_conf_read(pa->pa_pc, pa->pa_tag, reg); 314 mask |= PCI_MAPREG_ROM_ENABLE; 315 pci_conf_write(pa->pa_pc, pa->pa_tag, reg, mask); 316 splx(s); 317 } 318 319 /* If we're called with maxsize/offset of 0, behave like 320 * pci_mapreg_map. 321 */ 322 323 maxsize = (maxsize && offset) ? maxsize : size; 324 base += offset; 325 326 if ((maxsize < size && offset + maxsize <= size) || offset != 0) 327 return (1); 328 329 if (bus_space_map(tag, base, maxsize, busflags | flags, &handle)) 330 return (1); 331 332 if (tagp != 0) 333 *tagp = tag; 334 if (handlep != 0) 335 *handlep = handle; 336 if (basep != 0) 337 *basep = base; 338 if (sizep != 0) 339 *sizep = maxsize; 340 341 return (0); 342 } 343 344 int 345 pci_find_rom(struct pci_attach_args *pa, bus_space_tag_t bst, 346 bus_space_handle_t bsh, int type, bus_space_handle_t *romh, bus_size_t *sz) 347 { 348 bus_size_t romsz, offset = 0, imagesz; 349 uint16_t ptr; 350 int done = 0; 351 352 if (pci_mem_find(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 353 PCI_MAPREG_TYPE_ROM, NULL, &romsz, NULL)) 354 return 1; 355 356 /* 357 * no upper bound check; i cannot imagine a 4GB ROM, but 358 * it appears the spec would allow it! 359 */ 360 if (romsz < 1024) 361 return 1; 362 363 while (offset < romsz && !done){ 364 struct pci_rom_header hdr; 365 struct pci_rom rom; 366 367 hdr.romh_magic = bus_space_read_2(bst, bsh, 368 offset + offsetof (struct pci_rom_header, romh_magic)); 369 hdr.romh_data_ptr = bus_space_read_2(bst, bsh, 370 offset + offsetof (struct pci_rom_header, romh_data_ptr)); 371 372 /* no warning: quite possibly ROM is simply not populated */ 373 if (hdr.romh_magic != PCI_ROM_HEADER_MAGIC) 374 return 1; 375 376 ptr = offset + hdr.romh_data_ptr; 377 378 if (ptr > romsz) { 379 printf("pci_find_rom: rom data ptr out of range\n"); 380 return 1; 381 } 382 383 rom.rom_signature = bus_space_read_4(bst, bsh, ptr); 384 rom.rom_vendor = bus_space_read_2(bst, bsh, ptr + 385 offsetof(struct pci_rom, rom_vendor)); 386 rom.rom_product = bus_space_read_2(bst, bsh, ptr + 387 offsetof(struct pci_rom, rom_product)); 388 rom.rom_class = bus_space_read_1(bst, bsh, 389 ptr + offsetof (struct pci_rom, rom_class)); 390 rom.rom_subclass = bus_space_read_1(bst, bsh, 391 ptr + offsetof (struct pci_rom, rom_subclass)); 392 rom.rom_interface = bus_space_read_1(bst, bsh, 393 ptr + offsetof (struct pci_rom, rom_interface)); 394 rom.rom_len = bus_space_read_2(bst, bsh, 395 ptr + offsetof (struct pci_rom, rom_len)); 396 rom.rom_code_type = bus_space_read_1(bst, bsh, 397 ptr + offsetof (struct pci_rom, rom_code_type)); 398 rom.rom_indicator = bus_space_read_1(bst, bsh, 399 ptr + offsetof (struct pci_rom, rom_indicator)); 400 401 if (rom.rom_signature != PCI_ROM_SIGNATURE) { 402 printf("pci_find_rom: bad rom data signature\n"); 403 return 1; 404 } 405 406 imagesz = rom.rom_len * 512; 407 408 if ((rom.rom_vendor == PCI_VENDOR(pa->pa_id)) && 409 (rom.rom_product == PCI_PRODUCT(pa->pa_id)) && 410 (rom.rom_class == PCI_CLASS(pa->pa_class)) && 411 (rom.rom_subclass == PCI_SUBCLASS(pa->pa_class)) && 412 (rom.rom_interface == PCI_INTERFACE(pa->pa_class)) && 413 (rom.rom_code_type == type)) { 414 *sz = imagesz; 415 bus_space_subregion(bst, bsh, offset, imagesz, romh); 416 return 0; 417 } 418 419 /* last image check */ 420 if (rom.rom_indicator & PCI_ROM_INDICATOR_LAST) 421 return 1; 422 423 /* offset by size */ 424 offset += imagesz; 425 } 426 return 1; 427 } 428
Indexes created Thu Oct 02 10:09:58 GMT 2025