pci_map.c revision 1.31
1 /* $NetBSD: pci_map.c,v 1.31 2014/10/16 12:31:23 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; by William R. Studenmund; by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * PCI device mapping. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: pci_map.c,v 1.31 2014/10/16 12:31:23 riastradh Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 46 static int pci_mapreg_submap(const struct pci_attach_args *, int, pcireg_t, int, 47 bus_size_t, bus_size_t, bus_space_tag_t *, bus_space_handle_t *, 48 bus_addr_t *, bus_size_t *); 49 50 static int 51 pci_io_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type, 52 bus_addr_t *basep, bus_size_t *sizep, int *flagsp) 53 { 54 pcireg_t address, mask; 55 int s; 56 57 if (reg < PCI_MAPREG_START || 58 #if 0 59 /* 60 * Can't do this check; some devices have mapping registers 61 * way out in left field. 62 */ 63 reg >= PCI_MAPREG_END || 64 #endif 65 (reg & 3)) 66 panic("pci_io_find: bad request"); 67 68 /* 69 * Section 6.2.5.1, `Address Maps', tells us that: 70 * 71 * 1) The builtin software should have already mapped the device in a 72 * reasonable way. 73 * 74 * 2) A device which wants 2^n bytes of memory will hardwire the bottom 75 * n bits of the address to 0. As recommended, we write all 1s and see 76 * what we get back. 77 */ 78 s = splhigh(); 79 address = pci_conf_read(pc, tag, reg); 80 pci_conf_write(pc, tag, reg, 0xffffffff); 81 mask = pci_conf_read(pc, tag, reg); 82 pci_conf_write(pc, tag, reg, address); 83 splx(s); 84 85 if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_IO) { 86 aprint_debug("pci_io_find: expected type i/o, found mem\n"); 87 return 1; 88 } 89 90 if (PCI_MAPREG_IO_SIZE(mask) == 0) { 91 aprint_debug("pci_io_find: void region\n"); 92 return 1; 93 } 94 95 if (basep != NULL) 96 *basep = PCI_MAPREG_IO_ADDR(address); 97 if (sizep != NULL) 98 *sizep = PCI_MAPREG_IO_SIZE(mask); 99 if (flagsp != NULL) 100 *flagsp = 0; 101 102 return 0; 103 } 104 105 static int 106 pci_mem_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type, 107 bus_addr_t *basep, bus_size_t *sizep, int *flagsp) 108 { 109 pcireg_t address, mask, address1 = 0, mask1 = 0xffffffff; 110 u_int64_t waddress, wmask; 111 int s, is64bit, isrom; 112 113 is64bit = (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT); 114 isrom = (reg == PCI_MAPREG_ROM); 115 116 if ((!isrom) && (reg < PCI_MAPREG_START || 117 #if 0 118 /* 119 * Can't do this check; some devices have mapping registers 120 * way out in left field. 121 */ 122 reg >= PCI_MAPREG_END || 123 #endif 124 (reg & 3))) 125 panic("pci_mem_find: bad request"); 126 127 if (is64bit && (reg + 4) >= PCI_MAPREG_END) 128 panic("pci_mem_find: bad 64-bit request"); 129 130 /* 131 * Section 6.2.5.1, `Address Maps', tells us that: 132 * 133 * 1) The builtin software should have already mapped the device in a 134 * reasonable way. 135 * 136 * 2) A device which wants 2^n bytes of memory will hardwire the bottom 137 * n bits of the address to 0. As recommended, we write all 1s and see 138 * what we get back. Only probe the upper BAR of a mem64 BAR if bit 31 139 * is readonly. 140 */ 141 s = splhigh(); 142 address = pci_conf_read(pc, tag, reg); 143 pci_conf_write(pc, tag, reg, 0xffffffff); 144 mask = pci_conf_read(pc, tag, reg); 145 pci_conf_write(pc, tag, reg, address); 146 if (is64bit) { 147 address1 = pci_conf_read(pc, tag, reg + 4); 148 if ((mask & 0x80000000) == 0) { 149 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 150 mask1 = pci_conf_read(pc, tag, reg + 4); 151 pci_conf_write(pc, tag, reg + 4, address1); 152 } 153 } 154 splx(s); 155 156 if (!isrom) { 157 /* 158 * roms should have an enable bit instead of a memory 159 * type decoder bit. For normal BARs, make sure that 160 * the address decoder type matches what we asked for. 161 */ 162 if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_MEM) { 163 printf("pci_mem_find: expected type mem, found i/o\n"); 164 return 1; 165 } 166 /* XXX Allow 64bit bars for 32bit requests.*/ 167 if (PCI_MAPREG_MEM_TYPE(address) != 168 PCI_MAPREG_MEM_TYPE(type) && 169 PCI_MAPREG_MEM_TYPE(address) != 170 PCI_MAPREG_MEM_TYPE_64BIT) { 171 printf("pci_mem_find: " 172 "expected mem type %08x, found %08x\n", 173 PCI_MAPREG_MEM_TYPE(type), 174 PCI_MAPREG_MEM_TYPE(address)); 175 return 1; 176 } 177 } 178 179 waddress = (u_int64_t)address1 << 32UL | address; 180 wmask = (u_int64_t)mask1 << 32UL | mask; 181 182 if ((is64bit && PCI_MAPREG_MEM64_SIZE(wmask) == 0) || 183 (!is64bit && PCI_MAPREG_MEM_SIZE(mask) == 0)) { 184 aprint_debug("pci_mem_find: void region\n"); 185 return 1; 186 } 187 188 switch (PCI_MAPREG_MEM_TYPE(address)) { 189 case PCI_MAPREG_MEM_TYPE_32BIT: 190 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 191 break; 192 case PCI_MAPREG_MEM_TYPE_64BIT: 193 /* 194 * Handle the case of a 64-bit memory register on a 195 * platform with 32-bit addressing. Make sure that 196 * the address assigned and the device's memory size 197 * fit in 32 bits. We implicitly assume that if 198 * bus_addr_t is 64-bit, then so is bus_size_t. 199 */ 200 if (sizeof(u_int64_t) > sizeof(bus_addr_t) && 201 (address1 != 0 || mask1 != 0xffffffff)) { 202 printf("pci_mem_find: 64-bit memory map which is " 203 "inaccessible on a 32-bit platform\n"); 204 return 1; 205 } 206 break; 207 default: 208 printf("pci_mem_find: reserved mapping register type\n"); 209 return 1; 210 } 211 212 if (sizeof(u_int64_t) > sizeof(bus_addr_t)) { 213 if (basep != NULL) 214 *basep = PCI_MAPREG_MEM_ADDR(address); 215 if (sizep != NULL) 216 *sizep = PCI_MAPREG_MEM_SIZE(mask); 217 } else { 218 if (basep != NULL) 219 *basep = PCI_MAPREG_MEM64_ADDR(waddress); 220 if (sizep != NULL) 221 *sizep = PCI_MAPREG_MEM64_SIZE(wmask); 222 } 223 if (flagsp != NULL) 224 *flagsp = (isrom || PCI_MAPREG_MEM_PREFETCHABLE(address)) ? 225 BUS_SPACE_MAP_PREFETCHABLE : 0; 226 227 return 0; 228 } 229 230 #define _PCI_MAPREG_TYPEBITS(reg) \ 231 (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO ? \ 232 reg & PCI_MAPREG_TYPE_MASK : \ 233 reg & (PCI_MAPREG_TYPE_MASK|PCI_MAPREG_MEM_TYPE_MASK)) 234 235 pcireg_t 236 pci_mapreg_type(pci_chipset_tag_t pc, pcitag_t tag, int reg) 237 { 238 239 return _PCI_MAPREG_TYPEBITS(pci_conf_read(pc, tag, reg)); 240 } 241 242 int 243 pci_mapreg_probe(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t *typep) 244 { 245 pcireg_t address, mask; 246 int s; 247 248 s = splhigh(); 249 address = pci_conf_read(pc, tag, reg); 250 pci_conf_write(pc, tag, reg, 0xffffffff); 251 mask = pci_conf_read(pc, tag, reg); 252 pci_conf_write(pc, tag, reg, address); 253 splx(s); 254 255 if (mask == 0) /* unimplemented mapping register */ 256 return 0; 257 258 if (typep != NULL) 259 *typep = _PCI_MAPREG_TYPEBITS(address); 260 return 1; 261 } 262 263 int 264 pci_mapreg_info(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type, 265 bus_addr_t *basep, bus_size_t *sizep, int *flagsp) 266 { 267 268 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) 269 return pci_io_find(pc, tag, reg, type, basep, sizep, 270 flagsp); 271 else 272 return pci_mem_find(pc, tag, reg, type, basep, sizep, 273 flagsp); 274 } 275 276 int 277 pci_mapreg_map(const struct pci_attach_args *pa, int reg, pcireg_t type, 278 int busflags, bus_space_tag_t *tagp, bus_space_handle_t *handlep, 279 bus_addr_t *basep, bus_size_t *sizep) 280 { 281 return pci_mapreg_submap(pa, reg, type, busflags, 0, 0, tagp, 282 handlep, basep, sizep); 283 } 284 285 static int 286 pci_mapreg_submap(const struct pci_attach_args *pa, int reg, pcireg_t type, 287 int busflags, bus_size_t maxsize, bus_size_t offset, bus_space_tag_t *tagp, 288 bus_space_handle_t *handlep, bus_addr_t *basep, bus_size_t *sizep) 289 { 290 bus_space_tag_t tag; 291 bus_space_handle_t handle; 292 bus_addr_t base; 293 bus_size_t size; 294 int flags; 295 296 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) { 297 if ((pa->pa_flags & PCI_FLAGS_IO_OKAY) == 0) 298 return 1; 299 if (pci_io_find(pa->pa_pc, pa->pa_tag, reg, type, &base, 300 &size, &flags)) 301 return 1; 302 tag = pa->pa_iot; 303 } else { 304 if ((pa->pa_flags & PCI_FLAGS_MEM_OKAY) == 0) 305 return 1; 306 if (pci_mem_find(pa->pa_pc, pa->pa_tag, reg, type, &base, 307 &size, &flags)) 308 return 1; 309 tag = pa->pa_memt; 310 } 311 312 if (reg == PCI_MAPREG_ROM) { 313 pcireg_t mask; 314 int s; 315 /* we have to enable the ROM address decoder... */ 316 s = splhigh(); 317 mask = pci_conf_read(pa->pa_pc, pa->pa_tag, reg); 318 mask |= PCI_MAPREG_ROM_ENABLE; 319 pci_conf_write(pa->pa_pc, pa->pa_tag, reg, mask); 320 splx(s); 321 } 322 323 /* If we're called with maxsize/offset of 0, behave like 324 * pci_mapreg_map. 325 */ 326 327 maxsize = (maxsize && offset) ? maxsize : size; 328 base += offset; 329 330 if ((maxsize < size && offset + maxsize <= size) || offset != 0) 331 return 1; 332 333 if (bus_space_map(tag, base, maxsize, busflags | flags, &handle)) 334 return 1; 335 336 if (tagp != NULL) 337 *tagp = tag; 338 if (handlep != NULL) 339 *handlep = handle; 340 if (basep != NULL) 341 *basep = base; 342 if (sizep != NULL) 343 *sizep = maxsize; 344 345 return 0; 346 } 347 348 int 349 pci_find_rom(const struct pci_attach_args *pa, bus_space_tag_t bst, 350 bus_space_handle_t bsh, bus_size_t sz, int type, 351 bus_space_handle_t *romh, bus_size_t *romsz) 352 { 353 bus_size_t offset = 0, imagesz; 354 uint16_t ptr; 355 int done = 0; 356 357 /* 358 * no upper bound check; i cannot imagine a 4GB ROM, but 359 * it appears the spec would allow it! 360 */ 361 if (sz < 1024) 362 return 1; 363 364 while (offset < sz && !done){ 365 struct pci_rom_header hdr; 366 struct pci_rom rom; 367 368 hdr.romh_magic = bus_space_read_2(bst, bsh, 369 offset + offsetof (struct pci_rom_header, romh_magic)); 370 hdr.romh_data_ptr = bus_space_read_2(bst, bsh, 371 offset + offsetof (struct pci_rom_header, romh_data_ptr)); 372 373 /* no warning: quite possibly ROM is simply not populated */ 374 if (hdr.romh_magic != PCI_ROM_HEADER_MAGIC) 375 return 1; 376 377 ptr = offset + hdr.romh_data_ptr; 378 379 if (ptr > sz) { 380 printf("pci_find_rom: rom data ptr out of range\n"); 381 return 1; 382 } 383 384 rom.rom_signature = bus_space_read_4(bst, bsh, ptr); 385 rom.rom_vendor = bus_space_read_2(bst, bsh, ptr + 386 offsetof(struct pci_rom, rom_vendor)); 387 rom.rom_product = bus_space_read_2(bst, bsh, ptr + 388 offsetof(struct pci_rom, rom_product)); 389 rom.rom_class = bus_space_read_1(bst, bsh, 390 ptr + offsetof (struct pci_rom, rom_class)); 391 rom.rom_subclass = bus_space_read_1(bst, bsh, 392 ptr + offsetof (struct pci_rom, rom_subclass)); 393 rom.rom_interface = bus_space_read_1(bst, bsh, 394 ptr + offsetof (struct pci_rom, rom_interface)); 395 rom.rom_len = bus_space_read_2(bst, bsh, 396 ptr + offsetof (struct pci_rom, rom_len)); 397 rom.rom_code_type = bus_space_read_1(bst, bsh, 398 ptr + offsetof (struct pci_rom, rom_code_type)); 399 rom.rom_indicator = bus_space_read_1(bst, bsh, 400 ptr + offsetof (struct pci_rom, rom_indicator)); 401 402 if (rom.rom_signature != PCI_ROM_SIGNATURE) { 403 printf("pci_find_rom: bad rom data signature\n"); 404 return 1; 405 } 406 407 imagesz = rom.rom_len * 512; 408 409 if ((rom.rom_vendor == PCI_VENDOR(pa->pa_id)) && 410 (rom.rom_product == PCI_PRODUCT(pa->pa_id)) && 411 (rom.rom_class == PCI_CLASS(pa->pa_class)) && 412 (rom.rom_subclass == PCI_SUBCLASS(pa->pa_class)) && 413 (rom.rom_interface == PCI_INTERFACE(pa->pa_class)) && 414 (rom.rom_code_type == type)) { 415 *romsz = imagesz; 416 bus_space_subregion(bst, bsh, offset, imagesz, romh); 417 return 0; 418 } 419 420 /* last image check */ 421 if (rom.rom_indicator & PCI_ROM_INDICATOR_LAST) 422 return 1; 423 424 /* offset by size */ 425 offset += imagesz; 426 } 427 return 1; 428 } 429
Indexes created Thu Oct 02 10:09:58 GMT 2025