pci_map.c revision 1.36
1 /* $NetBSD: pci_map.c,v 1.36 2018/05/19 17:21:42 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; by William R. Studenmund; by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * PCI device mapping. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: pci_map.c,v 1.36 2018/05/19 17:21:42 jakllsch Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 46 bool pci_mapreg_map_enable_decode = true; 47 48 static int 49 pci_io_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type, 50 bus_addr_t *basep, bus_size_t *sizep, int *flagsp) 51 { 52 pcireg_t address, mask; 53 int s; 54 55 if (reg < PCI_MAPREG_START || 56 #if 0 57 /* 58 * Can't do this check; some devices have mapping registers 59 * way out in left field. 60 */ 61 reg >= PCI_MAPREG_END || 62 #endif 63 (reg & 3)) 64 panic("pci_io_find: bad request"); 65 66 /* 67 * Section 6.2.5.1, `Address Maps', tells us that: 68 * 69 * 1) The builtin software should have already mapped the device in a 70 * reasonable way. 71 * 72 * 2) A device which wants 2^n bytes of memory will hardwire the bottom 73 * n bits of the address to 0. As recommended, we write all 1s and see 74 * what we get back. 75 */ 76 s = splhigh(); 77 address = pci_conf_read(pc, tag, reg); 78 pci_conf_write(pc, tag, reg, 0xffffffff); 79 mask = pci_conf_read(pc, tag, reg); 80 pci_conf_write(pc, tag, reg, address); 81 splx(s); 82 83 if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_IO) { 84 aprint_debug("pci_io_find: expected type i/o, found mem\n"); 85 return 1; 86 } 87 88 if (PCI_MAPREG_IO_SIZE(mask) == 0) { 89 aprint_debug("pci_io_find: void region\n"); 90 return 1; 91 } 92 93 if (basep != NULL) 94 *basep = PCI_MAPREG_IO_ADDR(address); 95 if (sizep != NULL) 96 *sizep = PCI_MAPREG_IO_SIZE(mask); 97 if (flagsp != NULL) 98 *flagsp = 0; 99 100 return 0; 101 } 102 103 static int 104 pci_mem_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type, 105 bus_addr_t *basep, bus_size_t *sizep, int *flagsp) 106 { 107 pcireg_t address, mask, address1 = 0, mask1 = 0xffffffff; 108 u_int64_t waddress, wmask; 109 int s, is64bit, isrom; 110 111 is64bit = (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT); 112 isrom = (reg == PCI_MAPREG_ROM); 113 114 if ((!isrom) && (reg < PCI_MAPREG_START || 115 #if 0 116 /* 117 * Can't do this check; some devices have mapping registers 118 * way out in left field. 119 */ 120 reg >= PCI_MAPREG_END || 121 #endif 122 (reg & 3))) 123 panic("pci_mem_find: bad request"); 124 125 if (is64bit && (reg + 4) >= PCI_MAPREG_END) 126 panic("pci_mem_find: bad 64-bit request"); 127 128 /* 129 * Section 6.2.5.1, `Address Maps', tells us that: 130 * 131 * 1) The builtin software should have already mapped the device in a 132 * reasonable way. 133 * 134 * 2) A device which wants 2^n bytes of memory will hardwire the bottom 135 * n bits of the address to 0. As recommended, we write all 1s and see 136 * what we get back. Only probe the upper BAR of a mem64 BAR if bit 31 137 * is readonly. 138 */ 139 s = splhigh(); 140 address = pci_conf_read(pc, tag, reg); 141 pci_conf_write(pc, tag, reg, 0xffffffff); 142 mask = pci_conf_read(pc, tag, reg); 143 pci_conf_write(pc, tag, reg, address); 144 if (is64bit) { 145 address1 = pci_conf_read(pc, tag, reg + 4); 146 if ((mask & 0x80000000) == 0) { 147 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 148 mask1 = pci_conf_read(pc, tag, reg + 4); 149 pci_conf_write(pc, tag, reg + 4, address1); 150 } 151 } 152 splx(s); 153 154 if (!isrom) { 155 /* 156 * roms should have an enable bit instead of a memory 157 * type decoder bit. For normal BARs, make sure that 158 * the address decoder type matches what we asked for. 159 */ 160 if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_MEM) { 161 printf("pci_mem_find: expected type mem, found i/o\n"); 162 return 1; 163 } 164 /* XXX Allow 64bit bars for 32bit requests.*/ 165 if (PCI_MAPREG_MEM_TYPE(address) != 166 PCI_MAPREG_MEM_TYPE(type) && 167 PCI_MAPREG_MEM_TYPE(address) != 168 PCI_MAPREG_MEM_TYPE_64BIT) { 169 printf("pci_mem_find: " 170 "expected mem type %08x, found %08x\n", 171 PCI_MAPREG_MEM_TYPE(type), 172 PCI_MAPREG_MEM_TYPE(address)); 173 return 1; 174 } 175 } 176 177 waddress = (u_int64_t)address1 << 32UL | address; 178 wmask = (u_int64_t)mask1 << 32UL | mask; 179 180 if ((is64bit && PCI_MAPREG_MEM64_SIZE(wmask) == 0) || 181 (!is64bit && PCI_MAPREG_MEM_SIZE(mask) == 0)) { 182 aprint_debug("pci_mem_find: void region\n"); 183 return 1; 184 } 185 186 switch (PCI_MAPREG_MEM_TYPE(address)) { 187 case PCI_MAPREG_MEM_TYPE_32BIT: 188 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 189 break; 190 case PCI_MAPREG_MEM_TYPE_64BIT: 191 /* 192 * Handle the case of a 64-bit memory register on a 193 * platform with 32-bit addressing. Make sure that 194 * the address assigned and the device's memory size 195 * fit in 32 bits. We implicitly assume that if 196 * bus_addr_t is 64-bit, then so is bus_size_t. 197 */ 198 if (sizeof(u_int64_t) > sizeof(bus_addr_t) && 199 (address1 != 0 || mask1 != 0xffffffff)) { 200 printf("pci_mem_find: 64-bit memory map which is " 201 "inaccessible on a 32-bit platform\n"); 202 return 1; 203 } 204 break; 205 default: 206 printf("pci_mem_find: reserved mapping register type\n"); 207 return 1; 208 } 209 210 if (sizeof(u_int64_t) > sizeof(bus_addr_t)) { 211 if (basep != NULL) 212 *basep = PCI_MAPREG_MEM_ADDR(address); 213 if (sizep != NULL) 214 *sizep = PCI_MAPREG_MEM_SIZE(mask); 215 } else { 216 if (basep != NULL) 217 *basep = PCI_MAPREG_MEM64_ADDR(waddress); 218 if (sizep != NULL) 219 *sizep = PCI_MAPREG_MEM64_SIZE(wmask); 220 } 221 if (flagsp != NULL) 222 *flagsp = (isrom || PCI_MAPREG_MEM_PREFETCHABLE(address)) ? 223 BUS_SPACE_MAP_PREFETCHABLE : 0; 224 225 return 0; 226 } 227 228 #define _PCI_MAPREG_TYPEBITS(reg) \ 229 (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO ? \ 230 reg & PCI_MAPREG_TYPE_MASK : \ 231 reg & (PCI_MAPREG_TYPE_MASK|PCI_MAPREG_MEM_TYPE_MASK)) 232 233 pcireg_t 234 pci_mapreg_type(pci_chipset_tag_t pc, pcitag_t tag, int reg) 235 { 236 237 return _PCI_MAPREG_TYPEBITS(pci_conf_read(pc, tag, reg)); 238 } 239 240 int 241 pci_mapreg_probe(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t *typep) 242 { 243 pcireg_t address, mask; 244 int s; 245 246 s = splhigh(); 247 address = pci_conf_read(pc, tag, reg); 248 pci_conf_write(pc, tag, reg, 0xffffffff); 249 mask = pci_conf_read(pc, tag, reg); 250 pci_conf_write(pc, tag, reg, address); 251 splx(s); 252 253 if (mask == 0) /* unimplemented mapping register */ 254 return 0; 255 256 if (typep != NULL) 257 *typep = _PCI_MAPREG_TYPEBITS(address); 258 return 1; 259 } 260 261 int 262 pci_mapreg_info(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type, 263 bus_addr_t *basep, bus_size_t *sizep, int *flagsp) 264 { 265 266 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) 267 return pci_io_find(pc, tag, reg, type, basep, sizep, 268 flagsp); 269 else 270 return pci_mem_find(pc, tag, reg, type, basep, sizep, 271 flagsp); 272 } 273 274 int 275 pci_mapreg_map(const struct pci_attach_args *pa, int reg, pcireg_t type, 276 int busflags, bus_space_tag_t *tagp, bus_space_handle_t *handlep, 277 bus_addr_t *basep, bus_size_t *sizep) 278 { 279 return pci_mapreg_submap(pa, reg, type, busflags, 0, 0, tagp, 280 handlep, basep, sizep); 281 } 282 283 int 284 pci_mapreg_submap(const struct pci_attach_args *pa, int reg, pcireg_t type, 285 int busflags, bus_size_t reqsize, bus_size_t offset, bus_space_tag_t *tagp, 286 bus_space_handle_t *handlep, bus_addr_t *basep, bus_size_t *sizep) 287 { 288 bus_space_tag_t tag; 289 bus_space_handle_t handle; 290 bus_addr_t base; 291 bus_size_t realmaxsize; 292 pcireg_t csr; 293 int flags, s; 294 295 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) { 296 if ((pa->pa_flags & PCI_FLAGS_IO_OKAY) == 0) 297 return 1; 298 if (pci_io_find(pa->pa_pc, pa->pa_tag, reg, type, &base, 299 &realmaxsize, &flags)) 300 return 1; 301 tag = pa->pa_iot; 302 } else { 303 if ((pa->pa_flags & PCI_FLAGS_MEM_OKAY) == 0) 304 return 1; 305 if (pci_mem_find(pa->pa_pc, pa->pa_tag, reg, type, &base, 306 &realmaxsize, &flags)) 307 return 1; 308 tag = pa->pa_memt; 309 } 310 311 if (reg == PCI_MAPREG_ROM) { 312 pcireg_t mask; 313 /* we have to enable the ROM address decoder... */ 314 s = splhigh(); 315 mask = pci_conf_read(pa->pa_pc, pa->pa_tag, reg); 316 mask |= PCI_MAPREG_ROM_ENABLE; 317 pci_conf_write(pa->pa_pc, pa->pa_tag, reg, mask); 318 splx(s); 319 } 320 321 /* If we're called with maxsize/offset of 0, behave like 322 * pci_mapreg_map. 323 */ 324 325 reqsize = (reqsize != 0) ? reqsize : realmaxsize; 326 base += offset; 327 328 if (realmaxsize < (offset + reqsize)) 329 return 1; 330 331 if (bus_space_map(tag, base, reqsize, busflags | flags, &handle)) 332 return 1; 333 334 if (pci_mapreg_map_enable_decode) { 335 s = splhigh(); 336 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 337 csr |= (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) ? 338 PCI_COMMAND_IO_ENABLE : PCI_COMMAND_MEM_ENABLE; 339 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 340 splx(s); 341 } 342 343 if (tagp != NULL) 344 *tagp = tag; 345 if (handlep != NULL) 346 *handlep = handle; 347 if (basep != NULL) 348 *basep = base; 349 if (sizep != NULL) 350 *sizep = reqsize; 351 352 return 0; 353 } 354 355 int 356 pci_find_rom(const struct pci_attach_args *pa, bus_space_tag_t bst, 357 bus_space_handle_t bsh, bus_size_t sz, int type, 358 bus_space_handle_t *romh, bus_size_t *romsz) 359 { 360 bus_size_t offset = 0, imagesz; 361 uint16_t ptr; 362 int done = 0; 363 364 /* 365 * no upper bound check; i cannot imagine a 4GB ROM, but 366 * it appears the spec would allow it! 367 */ 368 if (sz < 1024) 369 return 1; 370 371 while (offset < sz && !done){ 372 struct pci_rom_header hdr; 373 struct pci_rom rom; 374 375 hdr.romh_magic = bus_space_read_2(bst, bsh, 376 offset + offsetof (struct pci_rom_header, romh_magic)); 377 hdr.romh_data_ptr = bus_space_read_2(bst, bsh, 378 offset + offsetof (struct pci_rom_header, romh_data_ptr)); 379 380 /* no warning: quite possibly ROM is simply not populated */ 381 if (hdr.romh_magic != PCI_ROM_HEADER_MAGIC) 382 return 1; 383 384 ptr = offset + hdr.romh_data_ptr; 385 386 if (ptr > sz) { 387 printf("pci_find_rom: rom data ptr out of range\n"); 388 return 1; 389 } 390 391 rom.rom_signature = bus_space_read_4(bst, bsh, ptr); 392 rom.rom_vendor = bus_space_read_2(bst, bsh, ptr + 393 offsetof(struct pci_rom, rom_vendor)); 394 rom.rom_product = bus_space_read_2(bst, bsh, ptr + 395 offsetof(struct pci_rom, rom_product)); 396 rom.rom_class = bus_space_read_1(bst, bsh, 397 ptr + offsetof (struct pci_rom, rom_class)); 398 rom.rom_subclass = bus_space_read_1(bst, bsh, 399 ptr + offsetof (struct pci_rom, rom_subclass)); 400 rom.rom_interface = bus_space_read_1(bst, bsh, 401 ptr + offsetof (struct pci_rom, rom_interface)); 402 rom.rom_len = bus_space_read_2(bst, bsh, 403 ptr + offsetof (struct pci_rom, rom_len)); 404 rom.rom_code_type = bus_space_read_1(bst, bsh, 405 ptr + offsetof (struct pci_rom, rom_code_type)); 406 rom.rom_indicator = bus_space_read_1(bst, bsh, 407 ptr + offsetof (struct pci_rom, rom_indicator)); 408 409 if (rom.rom_signature != PCI_ROM_SIGNATURE) { 410 printf("pci_find_rom: bad rom data signature\n"); 411 return 1; 412 } 413 414 imagesz = rom.rom_len * 512; 415 416 if ((rom.rom_vendor == PCI_VENDOR(pa->pa_id)) && 417 (rom.rom_product == PCI_PRODUCT(pa->pa_id)) && 418 (rom.rom_class == PCI_CLASS(pa->pa_class)) && 419 (rom.rom_subclass == PCI_SUBCLASS(pa->pa_class)) && 420 (rom.rom_interface == PCI_INTERFACE(pa->pa_class)) && 421 (rom.rom_code_type == type)) { 422 *romsz = imagesz; 423 bus_space_subregion(bst, bsh, offset, imagesz, romh); 424 return 0; 425 } 426 427 /* last image check */ 428 if (rom.rom_indicator & PCI_ROM_INDICATOR_LAST) 429 return 1; 430 431 /* offset by size */ 432 offset += imagesz; 433 } 434 return 1; 435 } 436
Indexes created Tue Sep 23 07:09:52 GMT 2025