pci_map.c revision 1.8
1 /* $NetBSD: pci_map.c,v 1.8 2000/06/28 17:32:48 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; by William R. Studenmund; by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * PCI device mapping. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 50 static int pci_io_find __P((pci_chipset_tag_t, pcitag_t, int, pcireg_t, 51 bus_addr_t *, bus_size_t *, int *)); 52 static int pci_mem_find __P((pci_chipset_tag_t, pcitag_t, int, pcireg_t, 53 bus_addr_t *, bus_size_t *, int *)); 54 55 static int 56 pci_io_find(pc, tag, reg, type, basep, sizep, flagsp) 57 pci_chipset_tag_t pc; 58 pcitag_t tag; 59 int reg; 60 pcireg_t type; 61 bus_addr_t *basep; 62 bus_size_t *sizep; 63 int *flagsp; 64 { 65 pcireg_t address, mask; 66 int s; 67 68 if (reg < PCI_MAPREG_START || 69 #if 0 70 /* 71 * Can't do this check; some devices have mapping registers 72 * way out in left field. 73 */ 74 reg >= PCI_MAPREG_END || 75 #endif 76 (reg & 3)) 77 panic("pci_io_find: bad request"); 78 79 /* 80 * Section 6.2.5.1, `Address Maps', tells us that: 81 * 82 * 1) The builtin software should have already mapped the device in a 83 * reasonable way. 84 * 85 * 2) A device which wants 2^n bytes of memory will hardwire the bottom 86 * n bits of the address to 0. As recommended, we write all 1s and see 87 * what we get back. 88 */ 89 s = splhigh(); 90 address = pci_conf_read(pc, tag, reg); 91 pci_conf_write(pc, tag, reg, 0xffffffff); 92 mask = pci_conf_read(pc, tag, reg); 93 pci_conf_write(pc, tag, reg, address); 94 splx(s); 95 96 if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_IO) { 97 printf("pci_io_find: expected type i/o, found mem\n"); 98 return (1); 99 } 100 101 if (PCI_MAPREG_IO_SIZE(mask) == 0) { 102 printf("pci_io_find: void region\n"); 103 return (1); 104 } 105 106 if (basep != 0) 107 *basep = PCI_MAPREG_IO_ADDR(address); 108 if (sizep != 0) 109 *sizep = PCI_MAPREG_IO_SIZE(mask); 110 if (flagsp != 0) 111 *flagsp = 0; 112 113 return (0); 114 } 115 116 static int 117 pci_mem_find(pc, tag, reg, type, basep, sizep, flagsp) 118 pci_chipset_tag_t pc; 119 pcitag_t tag; 120 int reg; 121 pcireg_t type; 122 bus_addr_t *basep; 123 bus_size_t *sizep; 124 int *flagsp; 125 { 126 pcireg_t address, mask, address1 = 0, mask1 = 0xffffffff; 127 u_int64_t waddress, wmask; 128 int s, is64bit; 129 130 is64bit = (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT); 131 132 if (reg < PCI_MAPREG_START || 133 #if 0 134 /* 135 * Can't do this check; some devices have mapping registers 136 * way out in left field. 137 */ 138 reg >= PCI_MAPREG_END || 139 #endif 140 (reg & 3)) 141 panic("pci_mem_find: bad request"); 142 143 if (is64bit && (reg + 4) >= PCI_MAPREG_END) 144 panic("pci_mem_find: bad 64-bit request"); 145 146 /* 147 * Section 6.2.5.1, `Address Maps', tells us that: 148 * 149 * 1) The builtin software should have already mapped the device in a 150 * reasonable way. 151 * 152 * 2) A device which wants 2^n bytes of memory will hardwire the bottom 153 * n bits of the address to 0. As recommended, we write all 1s and see 154 * what we get back. 155 */ 156 s = splhigh(); 157 address = pci_conf_read(pc, tag, reg); 158 pci_conf_write(pc, tag, reg, 0xffffffff); 159 mask = pci_conf_read(pc, tag, reg); 160 pci_conf_write(pc, tag, reg, address); 161 if (is64bit) { 162 address1 = pci_conf_read(pc, tag, reg + 4); 163 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 164 mask1 = pci_conf_read(pc, tag, reg + 4); 165 pci_conf_write(pc, tag, reg + 4, address1); 166 } 167 splx(s); 168 169 if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_MEM) { 170 printf("pci_mem_find: expected type mem, found i/o\n"); 171 return (1); 172 } 173 if (PCI_MAPREG_MEM_TYPE(address) != PCI_MAPREG_MEM_TYPE(type)) { 174 printf("pci_mem_find: expected mem type %08x, found %08x\n", 175 PCI_MAPREG_MEM_TYPE(type), 176 PCI_MAPREG_MEM_TYPE(address)); 177 return (1); 178 } 179 180 waddress = (u_int64_t)address1 << 32UL | address; 181 wmask = (u_int64_t)mask1 << 32UL | mask; 182 183 if (PCI_MAPREG_MEM64_SIZE(wmask) == 0) { 184 printf("pci_mem_find: void region\n"); 185 return (1); 186 } 187 188 switch (PCI_MAPREG_MEM_TYPE(address)) { 189 case PCI_MAPREG_MEM_TYPE_32BIT: 190 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 191 break; 192 case PCI_MAPREG_MEM_TYPE_64BIT: 193 /* 194 * Handle the case of a 64-bit memory register on a 195 * platform with 32-bit addressing. Make sure that 196 * the address assigned and the device's memory size 197 * fit in 32 bits. We implicitly assume that if 198 * bus_addr_t is 64-bit, then so is bus_size_t. 199 */ 200 if (sizeof(u_int64_t) > sizeof(bus_addr_t) && 201 (address1 != 0 || mask1 != 0xffffffff)) { 202 printf("pci_mem_find: 64-bit memory map which is " 203 "inaccessible on a 32-bit platform\n"); 204 return (1); 205 } 206 break; 207 default: 208 printf("pci_mem_find: reserved mapping register type\n"); 209 return (1); 210 } 211 212 if (sizeof(u_int64_t) > sizeof(bus_addr_t)) { 213 if (basep != 0) 214 *basep = PCI_MAPREG_MEM_ADDR(address); 215 if (sizep != 0) 216 *sizep = PCI_MAPREG_MEM_SIZE(mask); 217 } else { 218 if (basep != 0) 219 *basep = PCI_MAPREG_MEM64_ADDR(waddress); 220 if (sizep != 0) 221 *sizep = PCI_MAPREG_MEM64_SIZE(wmask); 222 } 223 if (flagsp != 0) 224 *flagsp = PCI_MAPREG_MEM_PREFETCHABLE(address) ? 225 BUS_SPACE_MAP_PREFETCHABLE : 0; 226 227 return (0); 228 } 229 230 pcireg_t 231 pci_mapreg_type(pc, tag, reg) 232 pci_chipset_tag_t pc; 233 pcitag_t tag; 234 int reg; 235 { 236 pcireg_t rv; 237 238 rv = pci_conf_read(pc, tag, reg); 239 if (PCI_MAPREG_TYPE(rv) == PCI_MAPREG_TYPE_IO) 240 rv &= PCI_MAPREG_TYPE_MASK; 241 else 242 rv &= PCI_MAPREG_TYPE_MASK|PCI_MAPREG_MEM_TYPE_MASK; 243 return (rv); 244 } 245 246 int 247 pci_mapreg_info(pc, tag, reg, type, basep, sizep, flagsp) 248 pci_chipset_tag_t pc; 249 pcitag_t tag; 250 int reg; 251 pcireg_t type; 252 bus_addr_t *basep; 253 bus_size_t *sizep; 254 int *flagsp; 255 { 256 257 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) 258 return (pci_io_find(pc, tag, reg, type, basep, sizep, 259 flagsp)); 260 else 261 return (pci_mem_find(pc, tag, reg, type, basep, sizep, 262 flagsp)); 263 } 264 265 int 266 pci_mapreg_map(pa, reg, type, busflags, tagp, handlep, basep, sizep) 267 struct pci_attach_args *pa; 268 int reg, busflags; 269 pcireg_t type; 270 bus_space_tag_t *tagp; 271 bus_space_handle_t *handlep; 272 bus_addr_t *basep; 273 bus_size_t *sizep; 274 { 275 bus_space_tag_t tag; 276 bus_space_handle_t handle; 277 bus_addr_t base; 278 bus_size_t size; 279 int flags; 280 281 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) { 282 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) 283 return (1); 284 if (pci_io_find(pa->pa_pc, pa->pa_tag, reg, type, &base, 285 &size, &flags)) 286 return (1); 287 tag = pa->pa_iot; 288 } else { 289 if ((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) == 0) 290 return (1); 291 if (pci_mem_find(pa->pa_pc, pa->pa_tag, reg, type, &base, 292 &size, &flags)) 293 return (1); 294 tag = pa->pa_memt; 295 } 296 297 if (bus_space_map(tag, base, size, busflags | flags, &handle)) 298 return (1); 299 300 if (tagp != 0) 301 *tagp = tag; 302 if (handlep != 0) 303 *handlep = handle; 304 if (basep != 0) 305 *basep = base; 306 if (sizep != 0) 307 *sizep = size; 308 309 return (0); 310 } 311
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