pci_subr.c revision 1.104
1 /* $NetBSD: pci_subr.c,v 1.104 2013/04/21 23:46:06 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.104 2013/04/21 23:46:06 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdbool.h> 58 #include <stdio.h> 59 #endif 60 61 #include <dev/pci/pcireg.h> 62 #ifdef _KERNEL 63 #include <dev/pci/pcivar.h> 64 #endif 65 66 /* 67 * Descriptions of known PCI classes and subclasses. 68 * 69 * Subclasses are described in the same way as classes, but have a 70 * NULL subclass pointer. 71 */ 72 struct pci_class { 73 const char *name; 74 u_int val; /* as wide as pci_{,sub}class_t */ 75 const struct pci_class *subclasses; 76 }; 77 78 static const struct pci_class pci_subclass_prehistoric[] = { 79 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 80 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 81 { NULL, 0, NULL, }, 82 }; 83 84 static const struct pci_class pci_subclass_mass_storage[] = { 85 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 86 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 87 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 88 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 89 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 90 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, NULL, }, 91 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, NULL, }, 92 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 93 { "NVM", PCI_SUBCLASS_MASS_STORAGE_NVM, NULL, }, 94 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 95 { NULL, 0, NULL, }, 96 }; 97 98 static const struct pci_class pci_subclass_network[] = { 99 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 100 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 101 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 102 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 103 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 104 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 105 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 106 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 107 { NULL, 0, NULL, }, 108 }; 109 110 static const struct pci_class pci_subclass_display[] = { 111 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, NULL, }, 112 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 113 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 114 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 115 { NULL, 0, NULL, }, 116 }; 117 118 static const struct pci_class pci_subclass_multimedia[] = { 119 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 120 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 121 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 122 { "HD audio", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 123 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 124 { NULL, 0, NULL, }, 125 }; 126 127 static const struct pci_class pci_subclass_memory[] = { 128 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 129 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 130 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 131 { NULL, 0, NULL, }, 132 }; 133 134 static const struct pci_class pci_subclass_bridge[] = { 135 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 136 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 137 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 138 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 139 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, NULL, }, 140 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 141 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 142 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 143 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 144 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, NULL, }, 145 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 146 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 147 { NULL, 0, NULL, }, 148 }; 149 150 static const struct pci_class pci_subclass_communications[] = { 151 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, NULL, }, 152 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, NULL, }, 153 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL, }, 154 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, NULL, }, 155 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL, }, 156 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL, }, 157 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL, }, 158 { NULL, 0, NULL, }, 159 }; 160 161 static const struct pci_class pci_subclass_system[] = { 162 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, NULL, }, 163 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, NULL, }, 164 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, NULL, }, 165 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, NULL, }, 166 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 167 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 168 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 169 { NULL, 0, NULL, }, 170 }; 171 172 static const struct pci_class pci_subclass_input[] = { 173 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 174 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 175 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 176 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 177 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, NULL, }, 178 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 179 { NULL, 0, NULL, }, 180 }; 181 182 static const struct pci_class pci_subclass_dock[] = { 183 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 184 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 185 { NULL, 0, NULL, }, 186 }; 187 188 static const struct pci_class pci_subclass_processor[] = { 189 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 190 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 191 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 192 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 193 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 194 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 195 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 196 { NULL, 0, NULL, }, 197 }; 198 199 static const struct pci_class pci_subclass_serialbus[] = { 200 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, NULL, }, 201 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 202 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 203 { "USB", PCI_SUBCLASS_SERIALBUS_USB, NULL, }, 204 /* XXX Fiber Channel/_FIBRECHANNEL */ 205 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 206 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 207 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 208 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, NULL, }, 209 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 210 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 211 { NULL, 0, NULL, }, 212 }; 213 214 static const struct pci_class pci_subclass_wireless[] = { 215 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 216 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 217 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 218 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 219 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 220 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 221 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 222 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 223 { NULL, 0, NULL, }, 224 }; 225 226 static const struct pci_class pci_subclass_i2o[] = { 227 { "standard", PCI_SUBCLASS_I2O_STANDARD, NULL, }, 228 { NULL, 0, NULL, }, 229 }; 230 231 static const struct pci_class pci_subclass_satcom[] = { 232 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 233 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 234 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 235 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 236 { NULL, 0, NULL, }, 237 }; 238 239 static const struct pci_class pci_subclass_crypto[] = { 240 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 241 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 242 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 243 { NULL, 0, NULL, }, 244 }; 245 246 static const struct pci_class pci_subclass_dasp[] = { 247 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 248 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 249 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 250 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 251 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 252 { NULL, 0, NULL, }, 253 }; 254 255 static const struct pci_class pci_class[] = { 256 { "prehistoric", PCI_CLASS_PREHISTORIC, 257 pci_subclass_prehistoric, }, 258 { "mass storage", PCI_CLASS_MASS_STORAGE, 259 pci_subclass_mass_storage, }, 260 { "network", PCI_CLASS_NETWORK, 261 pci_subclass_network, }, 262 { "display", PCI_CLASS_DISPLAY, 263 pci_subclass_display, }, 264 { "multimedia", PCI_CLASS_MULTIMEDIA, 265 pci_subclass_multimedia, }, 266 { "memory", PCI_CLASS_MEMORY, 267 pci_subclass_memory, }, 268 { "bridge", PCI_CLASS_BRIDGE, 269 pci_subclass_bridge, }, 270 { "communications", PCI_CLASS_COMMUNICATIONS, 271 pci_subclass_communications, }, 272 { "system", PCI_CLASS_SYSTEM, 273 pci_subclass_system, }, 274 { "input", PCI_CLASS_INPUT, 275 pci_subclass_input, }, 276 { "dock", PCI_CLASS_DOCK, 277 pci_subclass_dock, }, 278 { "processor", PCI_CLASS_PROCESSOR, 279 pci_subclass_processor, }, 280 { "serial bus", PCI_CLASS_SERIALBUS, 281 pci_subclass_serialbus, }, 282 { "wireless", PCI_CLASS_WIRELESS, 283 pci_subclass_wireless, }, 284 { "I2O", PCI_CLASS_I2O, 285 pci_subclass_i2o, }, 286 { "satellite comm", PCI_CLASS_SATCOM, 287 pci_subclass_satcom, }, 288 { "crypto", PCI_CLASS_CRYPTO, 289 pci_subclass_crypto, }, 290 { "DASP", PCI_CLASS_DASP, 291 pci_subclass_dasp, }, 292 { "undefined", PCI_CLASS_UNDEFINED, 293 NULL, }, 294 { NULL, 0, 295 NULL, }, 296 }; 297 298 void pci_load_verbose(void); 299 300 #if defined(_KERNEL) 301 /* 302 * In kernel, these routines are provided and linked via the 303 * pciverbose module. 304 */ 305 const char *pci_findvendor_stub(pcireg_t); 306 const char *pci_findproduct_stub(pcireg_t); 307 308 const char *(*pci_findvendor)(pcireg_t) = pci_findvendor_stub; 309 const char *(*pci_findproduct)(pcireg_t) = pci_findproduct_stub; 310 const char *pci_unmatched = ""; 311 #else 312 /* 313 * For userland we just set the vectors here. 314 */ 315 const char *(*pci_findvendor)(pcireg_t id_reg) = pci_findvendor_real; 316 const char *(*pci_findproduct)(pcireg_t id_reg) = pci_findproduct_real; 317 const char *pci_unmatched = "unmatched "; 318 #endif 319 320 int pciverbose_loaded = 0; 321 322 #if defined(_KERNEL) 323 /* 324 * Routine to load the pciverbose kernel module as needed 325 */ 326 void pci_load_verbose(void) 327 { 328 if (pciverbose_loaded == 0) 329 module_autoload("pciverbose", MODULE_CLASS_MISC); 330 } 331 332 const char *pci_findvendor_stub(pcireg_t id_reg) 333 { 334 pci_load_verbose(); 335 if (pciverbose_loaded) 336 return pci_findvendor(id_reg); 337 else 338 return NULL; 339 } 340 341 const char *pci_findproduct_stub(pcireg_t id_reg) 342 { 343 pci_load_verbose(); 344 if (pciverbose_loaded) 345 return pci_findproduct(id_reg); 346 else 347 return NULL; 348 } 349 #endif 350 351 void 352 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 353 size_t l) 354 { 355 pci_vendor_id_t vendor; 356 pci_product_id_t product; 357 pci_class_t class; 358 pci_subclass_t subclass; 359 pci_interface_t interface; 360 pci_revision_t revision; 361 const char *unmatched = pci_unmatched; 362 const char *vendor_namep, *product_namep; 363 const struct pci_class *classp, *subclassp; 364 char *ep; 365 366 ep = cp + l; 367 368 vendor = PCI_VENDOR(id_reg); 369 product = PCI_PRODUCT(id_reg); 370 371 class = PCI_CLASS(class_reg); 372 subclass = PCI_SUBCLASS(class_reg); 373 interface = PCI_INTERFACE(class_reg); 374 revision = PCI_REVISION(class_reg); 375 376 vendor_namep = pci_findvendor(id_reg); 377 product_namep = pci_findproduct(id_reg); 378 379 classp = pci_class; 380 while (classp->name != NULL) { 381 if (class == classp->val) 382 break; 383 classp++; 384 } 385 386 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 387 while (subclassp && subclassp->name != NULL) { 388 if (subclass == subclassp->val) 389 break; 390 subclassp++; 391 } 392 393 if (vendor_namep == NULL) 394 cp += snprintf(cp, ep - cp, "%svendor 0x%04x product 0x%04x", 395 unmatched, vendor, product); 396 else if (product_namep != NULL) 397 cp += snprintf(cp, ep - cp, "%s %s", vendor_namep, 398 product_namep); 399 else 400 cp += snprintf(cp, ep - cp, "%s product 0x%04x", 401 vendor_namep, product); 402 if (showclass) { 403 cp += snprintf(cp, ep - cp, " ("); 404 if (classp->name == NULL) 405 cp += snprintf(cp, ep - cp, 406 "class 0x%02x, subclass 0x%02x", class, subclass); 407 else { 408 if (subclassp == NULL || subclassp->name == NULL) 409 cp += snprintf(cp, ep - cp, 410 "%s, subclass 0x%02x", 411 classp->name, subclass); 412 else 413 cp += snprintf(cp, ep - cp, "%s %s", 414 subclassp->name, classp->name); 415 } 416 if (interface != 0) 417 cp += snprintf(cp, ep - cp, ", interface 0x%02x", 418 interface); 419 if (revision != 0) 420 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 421 revision); 422 cp += snprintf(cp, ep - cp, ")"); 423 } 424 } 425 426 #ifdef _KERNEL 427 void 428 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 429 const char *known, int addrev) 430 { 431 char devinfo[256]; 432 433 if (known) { 434 aprint_normal(": %s", known); 435 if (addrev) 436 aprint_normal(" (rev. 0x%02x)", 437 PCI_REVISION(pa->pa_class)); 438 aprint_normal("\n"); 439 } else { 440 pci_devinfo(pa->pa_id, pa->pa_class, 0, 441 devinfo, sizeof(devinfo)); 442 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 443 PCI_REVISION(pa->pa_class)); 444 } 445 if (naive) 446 aprint_naive(": %s\n", naive); 447 else 448 aprint_naive("\n"); 449 } 450 #endif 451 452 /* 453 * Print out most of the PCI configuration registers. Typically used 454 * in a device attach routine like this: 455 * 456 * #ifdef MYDEV_DEBUG 457 * printf("%s: ", device_xname(sc->sc_dev)); 458 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 459 * #endif 460 */ 461 462 #define i2o(i) ((i) * 4) 463 #define o2i(o) ((o) / 4) 464 #define onoff2(str, bit, onstr, offstr) \ 465 printf(" %s: %s\n", (str), (rval & (bit)) ? onstr : offstr); 466 #define onoff(str, bit) onoff2(str, bit, "on", "off") 467 468 static void 469 pci_conf_print_common( 470 #ifdef _KERNEL 471 pci_chipset_tag_t pc, pcitag_t tag, 472 #endif 473 const pcireg_t *regs) 474 { 475 const char *name; 476 const struct pci_class *classp, *subclassp; 477 pcireg_t rval; 478 479 rval = regs[o2i(PCI_ID_REG)]; 480 name = pci_findvendor(rval); 481 if (name) 482 printf(" Vendor Name: %s (0x%04x)\n", name, 483 PCI_VENDOR(rval)); 484 else 485 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 486 name = pci_findproduct(rval); 487 if (name) 488 printf(" Device Name: %s (0x%04x)\n", name, 489 PCI_PRODUCT(rval)); 490 else 491 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 492 493 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 494 495 printf(" Command register: 0x%04x\n", rval & 0xffff); 496 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 497 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 498 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 499 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 500 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 501 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 502 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 503 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 504 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 505 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 506 onoff("Interrupt disable", PCI_COMMAND_INTERRUPT_DISABLE); 507 508 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 509 onoff2("Interrupt status", PCI_STATUS_INT_STATUS, "active", "inactive"); 510 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 511 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 512 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 513 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 514 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 515 516 printf(" DEVSEL timing: "); 517 switch (rval & PCI_STATUS_DEVSEL_MASK) { 518 case PCI_STATUS_DEVSEL_FAST: 519 printf("fast"); 520 break; 521 case PCI_STATUS_DEVSEL_MEDIUM: 522 printf("medium"); 523 break; 524 case PCI_STATUS_DEVSEL_SLOW: 525 printf("slow"); 526 break; 527 default: 528 printf("unknown/reserved"); /* XXX */ 529 break; 530 } 531 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 532 533 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 534 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 535 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 536 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 537 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 538 539 rval = regs[o2i(PCI_CLASS_REG)]; 540 for (classp = pci_class; classp->name != NULL; classp++) { 541 if (PCI_CLASS(rval) == classp->val) 542 break; 543 } 544 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 545 while (subclassp && subclassp->name != NULL) { 546 if (PCI_SUBCLASS(rval) == subclassp->val) 547 break; 548 subclassp++; 549 } 550 if (classp->name != NULL) { 551 printf(" Class Name: %s (0x%02x)\n", classp->name, 552 PCI_CLASS(rval)); 553 if (subclassp != NULL && subclassp->name != NULL) 554 printf(" Subclass Name: %s (0x%02x)\n", 555 subclassp->name, PCI_SUBCLASS(rval)); 556 else 557 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 558 } else { 559 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 560 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 561 } 562 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 563 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 564 565 rval = regs[o2i(PCI_BHLC_REG)]; 566 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 567 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 568 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 569 PCI_HDRTYPE(rval)); 570 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 571 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 572 } 573 574 static int 575 pci_conf_print_bar( 576 #ifdef _KERNEL 577 pci_chipset_tag_t pc, pcitag_t tag, 578 #endif 579 const pcireg_t *regs, int reg, const char *name 580 #ifdef _KERNEL 581 , int sizebar 582 #endif 583 ) 584 { 585 int width; 586 pcireg_t rval, rval64h; 587 #ifdef _KERNEL 588 int s; 589 pcireg_t mask, mask64h; 590 #endif 591 592 width = 4; 593 594 /* 595 * Section 6.2.5.1, `Address Maps', tells us that: 596 * 597 * 1) The builtin software should have already mapped the 598 * device in a reasonable way. 599 * 600 * 2) A device which wants 2^n bytes of memory will hardwire 601 * the bottom n bits of the address to 0. As recommended, 602 * we write all 1s and see what we get back. 603 */ 604 605 rval = regs[o2i(reg)]; 606 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 607 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 608 rval64h = regs[o2i(reg + 4)]; 609 width = 8; 610 } else 611 rval64h = 0; 612 613 #ifdef _KERNEL 614 /* XXX don't size unknown memory type? */ 615 if (rval != 0 && sizebar) { 616 /* 617 * The following sequence seems to make some devices 618 * (e.g. host bus bridges, which don't normally 619 * have their space mapped) very unhappy, to 620 * the point of crashing the system. 621 * 622 * Therefore, if the mapping register is zero to 623 * start out with, don't bother trying. 624 */ 625 s = splhigh(); 626 pci_conf_write(pc, tag, reg, 0xffffffff); 627 mask = pci_conf_read(pc, tag, reg); 628 pci_conf_write(pc, tag, reg, rval); 629 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 630 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 631 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 632 mask64h = pci_conf_read(pc, tag, reg + 4); 633 pci_conf_write(pc, tag, reg + 4, rval64h); 634 } else 635 mask64h = 0; 636 splx(s); 637 } else 638 mask = mask64h = 0; 639 #endif /* _KERNEL */ 640 641 printf(" Base address register at 0x%02x", reg); 642 if (name) 643 printf(" (%s)", name); 644 printf("\n "); 645 if (rval == 0) { 646 printf("not implemented(?)\n"); 647 return width; 648 } 649 printf("type: "); 650 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 651 const char *type, *prefetch; 652 653 switch (PCI_MAPREG_MEM_TYPE(rval)) { 654 case PCI_MAPREG_MEM_TYPE_32BIT: 655 type = "32-bit"; 656 break; 657 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 658 type = "32-bit-1M"; 659 break; 660 case PCI_MAPREG_MEM_TYPE_64BIT: 661 type = "64-bit"; 662 break; 663 default: 664 type = "unknown (XXX)"; 665 break; 666 } 667 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 668 prefetch = ""; 669 else 670 prefetch = "non"; 671 printf("%s %sprefetchable memory\n", type, prefetch); 672 switch (PCI_MAPREG_MEM_TYPE(rval)) { 673 case PCI_MAPREG_MEM_TYPE_64BIT: 674 printf(" base: 0x%016llx, ", 675 PCI_MAPREG_MEM64_ADDR( 676 ((((long long) rval64h) << 32) | rval))); 677 #ifdef _KERNEL 678 if (sizebar) 679 printf("size: 0x%016llx", 680 PCI_MAPREG_MEM64_SIZE( 681 ((((long long) mask64h) << 32) | mask))); 682 else 683 #endif /* _KERNEL */ 684 printf("not sized"); 685 printf("\n"); 686 break; 687 case PCI_MAPREG_MEM_TYPE_32BIT: 688 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 689 default: 690 printf(" base: 0x%08x, ", 691 PCI_MAPREG_MEM_ADDR(rval)); 692 #ifdef _KERNEL 693 if (sizebar) 694 printf("size: 0x%08x", 695 PCI_MAPREG_MEM_SIZE(mask)); 696 else 697 #endif /* _KERNEL */ 698 printf("not sized"); 699 printf("\n"); 700 break; 701 } 702 } else { 703 #ifdef _KERNEL 704 if (sizebar) 705 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 706 #endif /* _KERNEL */ 707 printf("i/o\n"); 708 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 709 #ifdef _KERNEL 710 if (sizebar) 711 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 712 else 713 #endif /* _KERNEL */ 714 printf("not sized"); 715 printf("\n"); 716 } 717 718 return width; 719 } 720 721 static void 722 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 723 { 724 int off, needaddr, neednl; 725 726 needaddr = 1; 727 neednl = 0; 728 for (off = first; off < pastlast; off += 4) { 729 if ((off % 16) == 0 || needaddr) { 730 printf(" 0x%02x:", off); 731 needaddr = 0; 732 } 733 printf(" 0x%08x", regs[o2i(off)]); 734 neednl = 1; 735 if ((off % 16) == 12) { 736 printf("\n"); 737 neednl = 0; 738 } 739 } 740 if (neednl) 741 printf("\n"); 742 } 743 744 static void 745 pci_conf_print_type0( 746 #ifdef _KERNEL 747 pci_chipset_tag_t pc, pcitag_t tag, 748 #endif 749 const pcireg_t *regs 750 #ifdef _KERNEL 751 , int sizebars 752 #endif 753 ) 754 { 755 int off, width; 756 pcireg_t rval; 757 758 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 759 #ifdef _KERNEL 760 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 761 #else 762 width = pci_conf_print_bar(regs, off, NULL); 763 #endif 764 } 765 766 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 767 768 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 769 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 770 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 771 772 /* XXX */ 773 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 774 775 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 776 printf(" Capability list pointer: 0x%02x\n", 777 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 778 else 779 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 780 781 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 782 783 rval = regs[o2i(PCI_INTERRUPT_REG)]; 784 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 785 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 786 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 787 switch (PCI_INTERRUPT_PIN(rval)) { 788 case PCI_INTERRUPT_PIN_NONE: 789 printf("(none)"); 790 break; 791 case PCI_INTERRUPT_PIN_A: 792 printf("(pin A)"); 793 break; 794 case PCI_INTERRUPT_PIN_B: 795 printf("(pin B)"); 796 break; 797 case PCI_INTERRUPT_PIN_C: 798 printf("(pin C)"); 799 break; 800 case PCI_INTERRUPT_PIN_D: 801 printf("(pin D)"); 802 break; 803 default: 804 printf("(? ? ?)"); 805 break; 806 } 807 printf("\n"); 808 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 809 } 810 811 static void 812 pci_print_pcie_L0s_latency(uint32_t val) 813 { 814 815 switch (val) { 816 case 0x0: 817 printf("Less than 64ns\n"); 818 break; 819 case 0x1: 820 case 0x2: 821 case 0x3: 822 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 823 break; 824 case 0x4: 825 printf("512ns to less than 1us\n"); 826 break; 827 case 0x5: 828 printf("1us to less than 2us\n"); 829 break; 830 case 0x6: 831 printf("2us - 4us\n"); 832 break; 833 case 0x7: 834 printf("More than 4us\n"); 835 break; 836 } 837 } 838 839 static void 840 pci_print_pcie_L1_latency(uint32_t val) 841 { 842 843 switch (val) { 844 case 0x0: 845 printf("Less than 1us\n"); 846 break; 847 case 0x6: 848 printf("32us - 64us\n"); 849 break; 850 case 0x7: 851 printf("More than 64us\n"); 852 break; 853 default: 854 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 855 break; 856 } 857 } 858 859 static void 860 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 861 { 862 pcireg_t reg; /* for each register */ 863 pcireg_t val; /* for each bitfield */ 864 bool check_slot = false; 865 bool check_rootport = false; 866 static const char * const linkspeeds[] = {"2.5", "5.0", "8.0"}; 867 868 printf("\n PCI Express Capabilities Register\n"); 869 /* Capability Register */ 870 reg = regs[o2i(capoff)]; 871 printf(" Capability register: %04x\n", reg >> 16); 872 printf(" Capability version: %x\n", 873 (unsigned int)((reg & 0x000f0000) >> 16)); 874 printf(" Device type: "); 875 switch ((reg & 0x00f00000) >> 20) { 876 case 0x0: 877 printf("PCI Express Endpoint device\n"); 878 break; 879 case 0x1: 880 printf("Legacy PCI Express Endpoint device\n"); 881 break; 882 case 0x4: 883 printf("Root Port of PCI Express Root Complex\n"); 884 check_slot = true; 885 check_rootport = true; /* XXX right? */ 886 break; 887 case 0x5: 888 printf("Upstream Port of PCI Express Switch\n"); 889 break; 890 case 0x6: 891 printf("Downstream Port of PCI Express Switch\n"); 892 check_slot = true; 893 check_rootport = true; /* XXX right? */ 894 break; 895 case 0x7: 896 printf("PCI Express to PCI/PCI-X Bridge\n"); 897 break; 898 case 0x8: 899 printf("PCI/PCI-X to PCI Express Bridge\n"); 900 break; 901 case 0x9: 902 printf("Root Complex Integrated Endpoint\n"); 903 check_rootport = true; /* XXX right? */ 904 break; 905 case 0xa: 906 printf("Root Complex Event Collector\n"); 907 break; 908 default: 909 printf("unknown\n"); 910 break; 911 } 912 if (check_slot && (reg & PCIE_XCAP_SI) != 0) 913 printf(" Slot implemented\n"); 914 printf(" Interrupt Message Number: %x\n", 915 (unsigned int)((reg & PCIE_XCAP_IRQ) >> 27)); 916 917 /* Device Capability Register */ 918 reg = regs[o2i(capoff + PCIE_DCAP)]; 919 printf(" Device Capabilities Register: 0x%08x\n", reg); 920 printf(" Max Payload Size Supported: %u bytes max\n", 921 (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD) * 256); 922 printf(" Phantom Functions Supported: "); 923 switch ((reg & PCIE_DCAP_PHANTOM_FUNCS) >> 3) { 924 case 0x0: 925 printf("not available\n"); 926 break; 927 case 0x1: 928 printf("MSB\n"); 929 break; 930 case 0x2: 931 printf("two MSB\n"); 932 break; 933 case 0x3: 934 printf("All three bits\n"); 935 break; 936 } 937 printf(" Extended Tag Field Supported: %dbit\n", 938 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 939 printf(" Endpoint L0 Acceptable Latency: "); 940 pci_print_pcie_L0s_latency((reg & PCIE_DCAP_L0S_LATENCY) >> 6); 941 printf(" Endpoint L1 Acceptable Latency: "); 942 pci_print_pcie_L1_latency((reg & PCIE_DCAP_L1_LATENCY) >> 9); 943 printf(" Attention Button Present: %s\n", 944 (reg & PCIE_DCAP_ATTN_BUTTON) != 0 ? "yes" : "no"); 945 printf(" Attention Indicator Present: %s\n", 946 (reg & PCIE_DCAP_ATTN_IND) != 0 ? "yes" : "no"); 947 printf(" Power Indicator Present: %s\n", 948 (reg & PCIE_DCAP_PWR_IND) != 0 ? "yes" : "no"); 949 printf(" Role-Based Error Report: %s\n", 950 (reg & PCIE_DCAP_ROLE_ERR_RPT) != 0 ? "yes" : "no"); 951 printf(" Captured Slot Power Limit Value: %d\n", 952 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18); 953 printf(" Captured Slot Power Limit Scale: %d\n", 954 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26); 955 printf(" Function-Level Reset Capability: %s\n", 956 (reg & PCIE_DCAP_FLR) != 0 ? "yes" : "no"); 957 958 /* Device Control Register */ 959 reg = regs[o2i(capoff + PCIE_DCSR)]; 960 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 961 printf(" Correctable Error Reporting Enable: %s\n", 962 (reg & PCIE_DCSR_ENA_COR_ERR) != 0 ? "on" : "off"); 963 printf(" Non Fatal Error Reporting Enable: %s\n", 964 (reg & PCIE_DCSR_ENA_NFER) != 0 ? "on" : "off"); 965 printf(" Fatal Error Reporting Enable: %s\n", 966 (reg & PCIE_DCSR_ENA_FER) != 0 ? "on" : "off"); 967 printf(" Unsupported Request Reporting Enable: %s\n", 968 (reg & PCIE_DCSR_ENA_URR) != 0 ? "on" : "off"); 969 printf(" Enable Relaxed Ordering: %s\n", 970 (reg & PCIE_DCSR_ENA_RELAX_ORD) != 0 ? "on" : "off"); 971 printf(" Max Payload Size: %d byte\n", 972 128 << (((unsigned int)(reg & PCIE_DCSR_MAX_PAYLOAD) >> 5))); 973 printf(" Extended Tag Field Enable: %s\n", 974 (reg & PCIE_DCSR_EXT_TAG_FIELD) != 0 ? "on" : "off"); 975 printf(" Phantom Functions Enable: %s\n", 976 (reg & PCIE_DCSR_PHANTOM_FUNCS) != 0 ? "on" : "off"); 977 printf(" Aux Power PM Enable: %s\n", 978 (reg & PCIE_DCSR_AUX_POWER_PM) != 0 ? "on" : "off"); 979 printf(" Enable No Snoop: %s\n", 980 (reg & PCIE_DCSR_ENA_NO_SNOOP) != 0 ? "on" : "off"); 981 printf(" Max Read Request Size: %d byte\n", 982 128 << ((unsigned int)(reg & PCIE_DCSR_MAX_READ_REQ) >> 12)); 983 984 /* Device Status Register */ 985 reg = regs[o2i(capoff + PCIE_DCSR)]; 986 printf(" Device Status Register: 0x%04x\n", reg >> 16); 987 printf(" Correctable Error Detected: %s\n", 988 (reg & PCIE_DCSR_CED) != 0 ? "on" : "off"); 989 printf(" Non Fatal Error Detected: %s\n", 990 (reg & PCIE_DCSR_NFED) != 0 ? "on" : "off"); 991 printf(" Fatal Error Detected: %s\n", 992 (reg & PCIE_DCSR_FED) != 0 ? "on" : "off"); 993 printf(" Unsupported Request Detected: %s\n", 994 (reg & PCIE_DCSR_URD) != 0 ? "on" : "off"); 995 printf(" Aux Power Detected: %s\n", 996 (reg & PCIE_DCSR_AUX_PWR) != 0 ? "on" : "off"); 997 printf(" Transaction Pending: %s\n", 998 (reg & PCIE_DCSR_TRANSACTION_PND) != 0 ? "on" : "off"); 999 1000 /* Link Capability Register */ 1001 reg = regs[o2i(capoff + PCIE_LCAP)]; 1002 printf(" Link Capabilities Register: 0x%08x\n", reg); 1003 printf(" Maximum Link Speed: "); 1004 val = reg & PCIE_LCAP_MAX_SPEED; 1005 if (val < 1 || val > 3) { 1006 printf("unknown %u value\n", val); 1007 } else { 1008 printf("%sGb/s\n", linkspeeds[val - 1]); 1009 } 1010 printf(" Maximum Link Width: x%u lanes\n", 1011 (unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4); 1012 printf(" Active State PM Support: "); 1013 val = (reg & PCIE_LCAP_ASPM) >> 10; 1014 switch (val) { 1015 case 0x1: 1016 printf("L0s Entry supported\n"); 1017 break; 1018 case 0x3: 1019 printf("L0s and L1 supported\n"); 1020 break; 1021 default: 1022 printf("Reserved value\n"); 1023 break; 1024 } 1025 printf(" L0 Exit Latency: "); 1026 pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12); 1027 printf(" L1 Exit Latency: "); 1028 pci_print_pcie_L1_latency((reg & PCIE_LCAP_L1_EXIT) >> 15); 1029 printf(" Port Number: %u\n", reg >> 24); 1030 1031 /* Link Control Register */ 1032 reg = regs[o2i(capoff + PCIE_LCSR)]; 1033 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1034 printf(" Active State PM Control: "); 1035 val = reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S); 1036 switch (val) { 1037 case 0: 1038 printf("disabled\n"); 1039 break; 1040 case 1: 1041 printf("L0s Entry Enabled\n"); 1042 break; 1043 case 2: 1044 printf("L1 Entry Enabled\n"); 1045 break; 1046 case 3: 1047 printf("L0s and L1 Entry Enabled\n"); 1048 break; 1049 } 1050 printf(" Read Completion Boundary Control: %dbyte\n", 1051 (reg & PCIE_LCSR_RCB) != 0 ? 128 : 64); 1052 printf(" Link Disable: %s\n", 1053 (reg & PCIE_LCSR_LINK_DIS) != 0 ? "on" : "off"); 1054 printf(" Retrain Link: %s\n", 1055 (reg & PCIE_LCSR_RETRAIN) != 0 ? "on" : "off"); 1056 printf(" Common Clock Configuration: %s\n", 1057 (reg & PCIE_LCSR_COMCLKCFG) != 0 ? "on" : "off"); 1058 printf(" Extended Synch: %s\n", 1059 (reg & PCIE_LCSR_EXTNDSYNC) != 0 ? "on" : "off"); 1060 printf(" Enable Clock Power Management: %s\n", 1061 (reg & PCIE_LCSR_ENCLKPM) != 0 ? "on" : "off"); 1062 printf(" Hardware Autonomous Width Disable: %s\n", 1063 (reg & PCIE_LCSR_HAWD) != 0 ? "on" : "off"); 1064 printf(" Link Bandwidth Management Interrupt Enable: %s\n", 1065 (reg & PCIE_LCSR_LBMIE) != 0 ? "on" : "off"); 1066 printf(" Link Autonomous Bandwidth Interrupt Enable: %s\n", 1067 (reg & PCIE_LCSR_LABIE) != 0 ? "on" : "off"); 1068 1069 /* Link Status Register */ 1070 reg = regs[o2i(capoff + PCIE_LCSR)]; 1071 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1072 printf(" Negotiated Link Speed: "); 1073 if (((reg >> 16) & 0x000f) < 1 || 1074 ((reg >> 16) & 0x000f) > 3) { 1075 printf("unknown %u value\n", 1076 (unsigned int)(reg & PCIE_LCSR_LINKSPEED) >> 16); 1077 } else { 1078 printf("%sGb/s\n", 1079 linkspeeds[((reg & PCIE_LCSR_LINKSPEED) >> 16) - 1]); 1080 } 1081 printf(" Negotiated Link Width: x%u lanes\n", 1082 (reg >> 20) & 0x003f); 1083 printf(" Training Error: %s\n", 1084 (reg & PCIE_LCSR_LINKTRAIN_ERR) != 0 ? "on" : "off"); 1085 printf(" Link Training: %s\n", 1086 (reg & PCIE_LCSR_LINKTRAIN) != 0 ? "on" : "off"); 1087 printf(" Slot Clock Configuration: %s\n", 1088 (reg & PCIE_LCSR_SLOTCLKCFG) != 0 ? "on" : "off"); 1089 printf(" Data Link Layer Link Active: %s\n", 1090 (reg & PCIE_LCSR_DLACTIVE) != 0 ? "on" : "off"); 1091 printf(" Link Bandwidth Management Status: %s\n", 1092 (reg & PCIE_LCSR_LINK_BW_MGMT) != 0 ? "on" : "off"); 1093 printf(" Link Autonomous Bandwidth Status: %s\n", 1094 (reg & PCIE_LCSR_LINK_AUTO_BW) != 0 ? "on" : "off"); 1095 1096 /* XXX Is this check right? */ 1097 if (check_slot == true) { 1098 /* Slot Capability Register */ 1099 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1100 printf(" Slot Capability Register: %08x\n", reg); 1101 if ((reg & PCIE_SLCAP_ABP) != 0) 1102 printf(" Attention Button Present\n"); 1103 if ((reg & PCIE_SLCAP_PCP) != 0) 1104 printf(" Power Controller Present\n"); 1105 if ((reg & PCIE_SLCAP_MSP) != 0) 1106 printf(" MRL Sensor Present\n"); 1107 if ((reg & PCIE_SLCAP_AIP) != 0) 1108 printf(" Attention Indicator Present\n"); 1109 if ((reg & PCIE_SLCAP_PIP) != 0) 1110 printf(" Power Indicator Present\n"); 1111 if ((reg & PCIE_SLCAP_HPS) != 0) 1112 printf(" Hot-Plug Surprise\n"); 1113 if ((reg & PCIE_SLCAP_HPC) != 0) 1114 printf(" Hot-Plug Capable\n"); 1115 printf(" Slot Power Limit Value: %d\n", 1116 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1117 printf(" Slot Power Limit Scale: %d\n", 1118 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1119 if ((reg & PCIE_SLCAP_EIP) != 0) 1120 printf(" Electromechanical Interlock Present\n"); 1121 if ((reg & PCIE_SLCAP_NCCS) != 0) 1122 printf(" No Command Completed Support\n"); 1123 printf(" Physical Slot Number: %d\n", 1124 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1125 1126 /* Slot Control Register */ 1127 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1128 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1129 if ((reg & PCIE_SLCSR_ABE) != 0) 1130 printf(" Attention Button Pressed Enabled\n"); 1131 if ((reg & PCIE_SLCSR_PFE) != 0) 1132 printf(" Power Fault Detected Enabled\n"); 1133 if ((reg & PCIE_SLCSR_MSE) != 0) 1134 printf(" MRL Sensor Changed Enabled\n"); 1135 if ((reg & PCIE_SLCSR_PDE) != 0) 1136 printf(" Presense Detect Changed Enabled\n"); 1137 if ((reg & PCIE_SLCSR_CCE) != 0) 1138 printf(" Command Completed Interrupt Enabled\n"); 1139 if ((reg & PCIE_SLCSR_HPE) != 0) 1140 printf(" Hot-Plug Interrupt Enabled\n"); 1141 printf(" Attention Indicator Control: "); 1142 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1143 case 0x0: 1144 printf("reserved\n"); 1145 break; 1146 case 0x1: 1147 printf("on\n"); 1148 break; 1149 case 0x2: 1150 printf("blink\n"); 1151 break; 1152 case 0x3: 1153 printf("off\n"); 1154 break; 1155 } 1156 printf(" Power Indicator Control: "); 1157 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1158 case 0x0: 1159 printf("reserved\n"); 1160 break; 1161 case 0x1: 1162 printf("on\n"); 1163 break; 1164 case 0x2: 1165 printf("blink\n"); 1166 break; 1167 case 0x3: 1168 printf("off\n"); 1169 break; 1170 } 1171 printf(" Power Controller Control: "); 1172 if ((reg & PCIE_SLCSR_PCC) != 0) 1173 printf("off\n"); 1174 else 1175 printf("on\n"); 1176 if ((reg & PCIE_SLCSR_EIC) != 0) 1177 printf(" Electromechanical Interlock Control\n"); 1178 if ((reg & PCIE_SLCSR_LACS) != 0) 1179 printf(" Data Link Layer State Changed Enable\n"); 1180 1181 /* Slot Status Register */ 1182 printf(" Slot Status Register: %04x\n", reg >> 16); 1183 if ((reg & PCIE_SLCSR_ABP) != 0) 1184 printf(" Attention Button Pressed\n"); 1185 if ((reg & PCIE_SLCSR_PFD) != 0) 1186 printf(" Power Fault Detected\n"); 1187 if ((reg & PCIE_SLCSR_MSC) != 0) 1188 printf(" MRL Sensor Changed\n"); 1189 if ((reg & PCIE_SLCSR_PDC) != 0) 1190 printf(" Presense Detect Changed\n"); 1191 if ((reg & PCIE_SLCSR_CC) != 0) 1192 printf(" Command Completed\n"); 1193 if ((reg & PCIE_SLCSR_MS) != 0) 1194 printf(" MRL Open\n"); 1195 if ((reg & PCIE_SLCSR_PDS) != 0) 1196 printf(" Card Present in slot\n"); 1197 if ((reg & PCIE_SLCSR_EIS) != 0) 1198 printf(" Electromechanical Interlock engaged\n"); 1199 if ((reg & PCIE_SLCSR_LACS) != 0) 1200 printf(" Data Link Layer State Changed\n"); 1201 } 1202 1203 /* XXX Is this check right? */ 1204 if (check_rootport == true) { 1205 /* Root Control Register */ 1206 reg = regs[o2i(capoff + PCIE_RCR)]; 1207 printf(" Root Control Register: %04x\n", reg & 0xffff); 1208 if ((reg & PCIE_RCR_SERR_CER) != 0) 1209 printf(" SERR on Correctable Error Enable\n"); 1210 if ((reg & PCIE_RCR_SERR_NFER) != 0) 1211 printf(" SERR on Non-Fatal Error Enable\n"); 1212 if ((reg & PCIE_RCR_SERR_FER) != 0) 1213 printf(" SERR on Fatal Error Enable\n"); 1214 if ((reg & PCIE_RCR_PME_IE) != 0) 1215 printf(" PME Interrupt Enable\n"); 1216 1217 /* Root Capability Register */ 1218 printf(" Root Capability Register: %04x\n", 1219 reg >> 16); 1220 1221 /* Root Status Register */ 1222 reg = regs[o2i(capoff + PCIE_RSR)]; 1223 printf(" Root Status Register: %08x\n", reg); 1224 printf(" PME Requester ID: %04x\n", 1225 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1226 if ((reg & PCIE_RSR_PME_STAT) != 0) 1227 printf(" PME was asserted\n"); 1228 if ((reg & PCIE_RSR_PME_PEND) != 0) 1229 printf(" another PME is pending\n"); 1230 } 1231 } 1232 1233 static const char * 1234 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1235 { 1236 switch ((caps >> 6) & 7) { 1237 case 0: return "self-powered"; 1238 case 1: return "55 mA"; 1239 case 2: return "100 mA"; 1240 case 3: return "160 mA"; 1241 case 4: return "220 mA"; 1242 case 5: return "270 mA"; 1243 case 6: return "320 mA"; 1244 case 7: 1245 default: return "375 mA"; 1246 } 1247 } 1248 1249 static const char * 1250 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1251 { 1252 static const char unk[] = "unknown"; 1253 static const char *pmrev[8] = { 1254 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1255 }; 1256 if (val > 7) 1257 return unk; 1258 return pmrev[val]; 1259 } 1260 1261 static void 1262 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1263 { 1264 uint16_t caps, pmcsr; 1265 1266 caps = regs[o2i(capoff)] >> 16; 1267 pmcsr = regs[o2i(capoff + 0x04)] & 0xffff; 1268 1269 printf("\n PCI Power Management Capabilities Register\n"); 1270 1271 printf(" Capabilities register: 0x%04x\n", caps); 1272 printf(" Version: %s\n", 1273 pci_conf_print_pcipm_cap_pmrev(caps & 0x3)); 1274 printf(" PME# clock: %s\n", caps & 0x4 ? "on" : "off"); 1275 printf(" Device specific initialization: %s\n", 1276 caps & 0x20 ? "on" : "off"); 1277 printf(" 3.3V auxiliary current: %s\n", 1278 pci_conf_print_pcipm_cap_aux(caps)); 1279 printf(" D1 power management state support: %s\n", 1280 (caps >> 9) & 1 ? "on" : "off"); 1281 printf(" D2 power management state support: %s\n", 1282 (caps >> 10) & 1 ? "on" : "off"); 1283 printf(" PME# support: 0x%02x\n", caps >> 11); 1284 1285 printf(" Control/status register: 0x%04x\n", pmcsr); 1286 printf(" Power state: D%d\n", pmcsr & 3); 1287 printf(" PCI Express reserved: %s\n", 1288 (pmcsr >> 2) & 1 ? "on" : "off"); 1289 printf(" No soft reset: %s\n", (pmcsr >> 3) & 1 ? "on" : "off"); 1290 printf(" PME# assertion %sabled\n", 1291 (pmcsr >> 8) & 1 ? "en" : "dis"); 1292 printf(" PME# status: %s\n", (pmcsr >> 15) ? "on" : "off"); 1293 } 1294 1295 static void 1296 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1297 { 1298 uint32_t ctl, mmc, mme; 1299 1300 regs += o2i(capoff); 1301 ctl = *regs++; 1302 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1303 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1304 1305 printf("\n PCI Message Signaled Interrupt\n"); 1306 1307 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1308 printf(" MSI Enabled: %s\n", 1309 ctl & PCI_MSI_CTL_MSI_ENABLE ? "yes" : "no"); 1310 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1311 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1312 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1313 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1314 printf(" 64 Bit Address Capable: %s\n", 1315 ctl & PCI_MSI_CTL_64BIT_ADDR ? "yes" : "no"); 1316 printf(" Per-Vector Masking Capable: %s\n", 1317 ctl & PCI_MSI_CTL_PERVEC_MASK ? "yes" : "no"); 1318 printf(" Message Address %sregister: 0x%08x\n", 1319 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1320 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1321 printf(" Message Address %sregister: 0x%08x\n", 1322 "(upper) ", *regs++); 1323 } 1324 printf(" Message Data register: 0x%08x\n", *regs++); 1325 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1326 printf(" Vector Mask register: 0x%08x\n", *regs++); 1327 printf(" Vector Pending register: 0x%08x\n", *regs++); 1328 } 1329 } 1330 static void 1331 pci_conf_print_caplist( 1332 #ifdef _KERNEL 1333 pci_chipset_tag_t pc, pcitag_t tag, 1334 #endif 1335 const pcireg_t *regs, int capoff) 1336 { 1337 int off; 1338 pcireg_t rval; 1339 int pcie_off = -1, pcipm_off = -1, msi_off = -1; 1340 1341 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1342 off != 0; 1343 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 1344 rval = regs[o2i(off)]; 1345 printf(" Capability register at 0x%02x\n", off); 1346 1347 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 1348 switch (PCI_CAPLIST_CAP(rval)) { 1349 case PCI_CAP_RESERVED0: 1350 printf("reserved"); 1351 break; 1352 case PCI_CAP_PWRMGMT: 1353 printf("Power Management, rev. %s", 1354 pci_conf_print_pcipm_cap_pmrev((rval >> 0) & 0x07)); 1355 pcipm_off = off; 1356 break; 1357 case PCI_CAP_AGP: 1358 printf("AGP, rev. %d.%d", 1359 PCI_CAP_AGP_MAJOR(rval), 1360 PCI_CAP_AGP_MINOR(rval)); 1361 break; 1362 case PCI_CAP_VPD: 1363 printf("VPD"); 1364 break; 1365 case PCI_CAP_SLOTID: 1366 printf("SlotID"); 1367 break; 1368 case PCI_CAP_MSI: 1369 printf("MSI"); 1370 msi_off = off; 1371 break; 1372 case PCI_CAP_CPCI_HOTSWAP: 1373 printf("CompactPCI Hot-swapping"); 1374 break; 1375 case PCI_CAP_PCIX: 1376 printf("PCI-X"); 1377 break; 1378 case PCI_CAP_LDT: 1379 printf("LDT"); 1380 break; 1381 case PCI_CAP_VENDSPEC: 1382 printf("Vendor-specific"); 1383 break; 1384 case PCI_CAP_DEBUGPORT: 1385 printf("Debug Port"); 1386 break; 1387 case PCI_CAP_CPCI_RSRCCTL: 1388 printf("CompactPCI Resource Control"); 1389 break; 1390 case PCI_CAP_HOTPLUG: 1391 printf("Hot-Plug"); 1392 break; 1393 case PCI_CAP_SUBVENDOR: 1394 printf("Sub Vendor ID"); 1395 break; 1396 case PCI_CAP_AGP8: 1397 printf("AGP 8x"); 1398 break; 1399 case PCI_CAP_SECURE: 1400 printf("Secure Device"); 1401 break; 1402 case PCI_CAP_PCIEXPRESS: 1403 printf("PCI Express"); 1404 pcie_off = off; 1405 break; 1406 case PCI_CAP_MSIX: 1407 printf("MSI-X"); 1408 break; 1409 case PCI_CAP_SATA: 1410 printf("SATA"); 1411 break; 1412 case PCI_CAP_PCIAF: 1413 printf("Advanced Features"); 1414 break; 1415 default: 1416 printf("unknown"); 1417 } 1418 printf(")\n"); 1419 } 1420 if (msi_off != -1) 1421 pci_conf_print_msi_cap(regs, msi_off); 1422 if (pcipm_off != -1) 1423 pci_conf_print_pcipm_cap(regs, pcipm_off); 1424 if (pcie_off != -1) 1425 pci_conf_print_pcie_cap(regs, pcie_off); 1426 } 1427 1428 /* Print the Secondary Status Register. */ 1429 static void 1430 pci_conf_print_ssr(pcireg_t rval) 1431 { 1432 pcireg_t devsel; 1433 1434 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 1435 onoff("66 MHz capable", __BIT(5)); 1436 onoff("User Definable Features (UDF) support", __BIT(6)); 1437 onoff("Fast back-to-back capable", __BIT(7)); 1438 onoff("Data parity error detected", __BIT(8)); 1439 1440 printf(" DEVSEL timing: "); 1441 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 1442 switch (devsel) { 1443 case 0: 1444 printf("fast"); 1445 break; 1446 case 1: 1447 printf("medium"); 1448 break; 1449 case 2: 1450 printf("slow"); 1451 break; 1452 default: 1453 printf("unknown/reserved"); /* XXX */ 1454 break; 1455 } 1456 printf(" (0x%x)\n", devsel); 1457 1458 onoff("Signalled target abort", __BIT(11)); 1459 onoff("Received target abort", __BIT(12)); 1460 onoff("Received master abort", __BIT(13)); 1461 onoff("Received system error", __BIT(14)); 1462 onoff("Detected parity error", __BIT(15)); 1463 } 1464 1465 static void 1466 pci_conf_print_type1( 1467 #ifdef _KERNEL 1468 pci_chipset_tag_t pc, pcitag_t tag, 1469 #endif 1470 const pcireg_t *regs 1471 #ifdef _KERNEL 1472 , int sizebars 1473 #endif 1474 ) 1475 { 1476 int off, width; 1477 pcireg_t rval; 1478 1479 /* 1480 * XXX these need to be printed in more detail, need to be 1481 * XXX checked against specs/docs, etc. 1482 * 1483 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 1484 * Bridge chip documentation, and may not be correct with 1485 * respect to various standards. (XXX) 1486 */ 1487 1488 for (off = 0x10; off < 0x18; off += width) { 1489 #ifdef _KERNEL 1490 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 1491 #else 1492 width = pci_conf_print_bar(regs, off, NULL); 1493 #endif 1494 } 1495 1496 printf(" Primary bus number: 0x%02x\n", 1497 (regs[o2i(0x18)] >> 0) & 0xff); 1498 printf(" Secondary bus number: 0x%02x\n", 1499 (regs[o2i(0x18)] >> 8) & 0xff); 1500 printf(" Subordinate bus number: 0x%02x\n", 1501 (regs[o2i(0x18)] >> 16) & 0xff); 1502 printf(" Secondary bus latency timer: 0x%02x\n", 1503 (regs[o2i(0x18)] >> 24) & 0xff); 1504 1505 pci_conf_print_ssr(__SHIFTOUT(regs[o2i(0x1c)], __BITS(31, 16))); 1506 1507 /* XXX Print more prettily */ 1508 printf(" I/O region:\n"); 1509 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 1510 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 1511 printf(" base upper 16 bits register: 0x%04x\n", 1512 (regs[o2i(0x30)] >> 0) & 0xffff); 1513 printf(" limit upper 16 bits register: 0x%04x\n", 1514 (regs[o2i(0x30)] >> 16) & 0xffff); 1515 1516 /* XXX Print more prettily */ 1517 printf(" Memory region:\n"); 1518 printf(" base register: 0x%04x\n", 1519 (regs[o2i(0x20)] >> 0) & 0xffff); 1520 printf(" limit register: 0x%04x\n", 1521 (regs[o2i(0x20)] >> 16) & 0xffff); 1522 1523 /* XXX Print more prettily */ 1524 printf(" Prefetchable memory region:\n"); 1525 printf(" base register: 0x%04x\n", 1526 (regs[o2i(0x24)] >> 0) & 0xffff); 1527 printf(" limit register: 0x%04x\n", 1528 (regs[o2i(0x24)] >> 16) & 0xffff); 1529 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 1530 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 1531 1532 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1533 printf(" Capability list pointer: 0x%02x\n", 1534 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 1535 else 1536 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 1537 1538 /* XXX */ 1539 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 1540 1541 printf(" Interrupt line: 0x%02x\n", 1542 (regs[o2i(0x3c)] >> 0) & 0xff); 1543 printf(" Interrupt pin: 0x%02x ", 1544 (regs[o2i(0x3c)] >> 8) & 0xff); 1545 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1546 case PCI_INTERRUPT_PIN_NONE: 1547 printf("(none)"); 1548 break; 1549 case PCI_INTERRUPT_PIN_A: 1550 printf("(pin A)"); 1551 break; 1552 case PCI_INTERRUPT_PIN_B: 1553 printf("(pin B)"); 1554 break; 1555 case PCI_INTERRUPT_PIN_C: 1556 printf("(pin C)"); 1557 break; 1558 case PCI_INTERRUPT_PIN_D: 1559 printf("(pin D)"); 1560 break; 1561 default: 1562 printf("(? ? ?)"); 1563 break; 1564 } 1565 printf("\n"); 1566 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1567 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 1568 onoff("Parity error response", 0x0001); 1569 onoff("Secondary SERR forwarding", 0x0002); 1570 onoff("ISA enable", 0x0004); 1571 onoff("VGA enable", 0x0008); 1572 onoff("Master abort reporting", 0x0020); 1573 onoff("Secondary bus reset", 0x0040); 1574 onoff("Fast back-to-back capable", 0x0080); 1575 } 1576 1577 static void 1578 pci_conf_print_type2( 1579 #ifdef _KERNEL 1580 pci_chipset_tag_t pc, pcitag_t tag, 1581 #endif 1582 const pcireg_t *regs 1583 #ifdef _KERNEL 1584 , int sizebars 1585 #endif 1586 ) 1587 { 1588 pcireg_t rval; 1589 1590 /* 1591 * XXX these need to be printed in more detail, need to be 1592 * XXX checked against specs/docs, etc. 1593 * 1594 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 1595 * controller chip documentation, and may not be correct with 1596 * respect to various standards. (XXX) 1597 */ 1598 1599 #ifdef _KERNEL 1600 pci_conf_print_bar(pc, tag, regs, 0x10, 1601 "CardBus socket/ExCA registers", sizebars); 1602 #else 1603 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 1604 #endif 1605 1606 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1607 printf(" Capability list pointer: 0x%02x\n", 1608 PCI_CAPLIST_PTR(regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)])); 1609 else 1610 printf(" Reserved @ 0x14: 0x%04" PRIxMAX "\n", 1611 __SHIFTOUT(regs[o2i(0x14)], __BITS(15, 0))); 1612 pci_conf_print_ssr(__SHIFTOUT(regs[o2i(0x14)], __BITS(31, 16))); 1613 1614 printf(" PCI bus number: 0x%02x\n", 1615 (regs[o2i(0x18)] >> 0) & 0xff); 1616 printf(" CardBus bus number: 0x%02x\n", 1617 (regs[o2i(0x18)] >> 8) & 0xff); 1618 printf(" Subordinate bus number: 0x%02x\n", 1619 (regs[o2i(0x18)] >> 16) & 0xff); 1620 printf(" CardBus latency timer: 0x%02x\n", 1621 (regs[o2i(0x18)] >> 24) & 0xff); 1622 1623 /* XXX Print more prettily */ 1624 printf(" CardBus memory region 0:\n"); 1625 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 1626 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 1627 printf(" CardBus memory region 1:\n"); 1628 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 1629 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 1630 printf(" CardBus I/O region 0:\n"); 1631 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 1632 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 1633 printf(" CardBus I/O region 1:\n"); 1634 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 1635 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 1636 1637 printf(" Interrupt line: 0x%02x\n", 1638 (regs[o2i(0x3c)] >> 0) & 0xff); 1639 printf(" Interrupt pin: 0x%02x ", 1640 (regs[o2i(0x3c)] >> 8) & 0xff); 1641 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1642 case PCI_INTERRUPT_PIN_NONE: 1643 printf("(none)"); 1644 break; 1645 case PCI_INTERRUPT_PIN_A: 1646 printf("(pin A)"); 1647 break; 1648 case PCI_INTERRUPT_PIN_B: 1649 printf("(pin B)"); 1650 break; 1651 case PCI_INTERRUPT_PIN_C: 1652 printf("(pin C)"); 1653 break; 1654 case PCI_INTERRUPT_PIN_D: 1655 printf("(pin D)"); 1656 break; 1657 default: 1658 printf("(? ? ?)"); 1659 break; 1660 } 1661 printf("\n"); 1662 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1663 printf(" Bridge control register: 0x%04x\n", rval); 1664 onoff("Parity error response", __BIT(0)); 1665 onoff("SERR# enable", __BIT(1)); 1666 onoff("ISA enable", __BIT(2)); 1667 onoff("VGA enable", __BIT(3)); 1668 onoff("Master abort mode", __BIT(5)); 1669 onoff("Secondary (CardBus) bus reset", __BIT(6)); 1670 onoff("Functional interrupts routed by ExCA registers", __BIT(7)); 1671 onoff("Memory window 0 prefetchable", __BIT(8)); 1672 onoff("Memory window 1 prefetchable", __BIT(9)); 1673 onoff("Write posting enable", __BIT(10)); 1674 1675 rval = regs[o2i(0x40)]; 1676 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1677 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1678 1679 #ifdef _KERNEL 1680 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1681 sizebars); 1682 #else 1683 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 1684 #endif 1685 } 1686 1687 void 1688 pci_conf_print( 1689 #ifdef _KERNEL 1690 pci_chipset_tag_t pc, pcitag_t tag, 1691 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 1692 #else 1693 int pcifd, u_int bus, u_int dev, u_int func 1694 #endif 1695 ) 1696 { 1697 pcireg_t regs[o2i(256)]; 1698 int off, capoff, endoff, hdrtype; 1699 const char *typename; 1700 #ifdef _KERNEL 1701 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1702 int sizebars; 1703 #else 1704 void (*typeprintfn)(const pcireg_t *); 1705 #endif 1706 1707 printf("PCI configuration registers:\n"); 1708 1709 for (off = 0; off < 256; off += 4) { 1710 #ifdef _KERNEL 1711 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1712 #else 1713 if (pcibus_conf_read(pcifd, bus, dev, func, off, 1714 ®s[o2i(off)]) == -1) 1715 regs[o2i(off)] = 0; 1716 #endif 1717 } 1718 1719 #ifdef _KERNEL 1720 sizebars = 1; 1721 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1722 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1723 sizebars = 0; 1724 #endif 1725 1726 /* common header */ 1727 printf(" Common header:\n"); 1728 pci_conf_print_regs(regs, 0, 16); 1729 1730 printf("\n"); 1731 #ifdef _KERNEL 1732 pci_conf_print_common(pc, tag, regs); 1733 #else 1734 pci_conf_print_common(regs); 1735 #endif 1736 printf("\n"); 1737 1738 /* type-dependent header */ 1739 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1740 switch (hdrtype) { /* XXX make a table, eventually */ 1741 case 0: 1742 /* Standard device header */ 1743 typename = "\"normal\" device"; 1744 typeprintfn = &pci_conf_print_type0; 1745 capoff = PCI_CAPLISTPTR_REG; 1746 endoff = 64; 1747 break; 1748 case 1: 1749 /* PCI-PCI bridge header */ 1750 typename = "PCI-PCI bridge"; 1751 typeprintfn = &pci_conf_print_type1; 1752 capoff = PCI_CAPLISTPTR_REG; 1753 endoff = 64; 1754 break; 1755 case 2: 1756 /* PCI-CardBus bridge header */ 1757 typename = "PCI-CardBus bridge"; 1758 typeprintfn = &pci_conf_print_type2; 1759 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 1760 endoff = 72; 1761 break; 1762 default: 1763 typename = NULL; 1764 typeprintfn = 0; 1765 capoff = -1; 1766 endoff = 64; 1767 break; 1768 } 1769 printf(" Type %d ", hdrtype); 1770 if (typename != NULL) 1771 printf("(%s) ", typename); 1772 printf("header:\n"); 1773 pci_conf_print_regs(regs, 16, endoff); 1774 printf("\n"); 1775 if (typeprintfn) { 1776 #ifdef _KERNEL 1777 (*typeprintfn)(pc, tag, regs, sizebars); 1778 #else 1779 (*typeprintfn)(regs); 1780 #endif 1781 } else 1782 printf(" Don't know how to pretty-print type %d header.\n", 1783 hdrtype); 1784 printf("\n"); 1785 1786 /* capability list, if present */ 1787 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1788 && (capoff > 0)) { 1789 #ifdef _KERNEL 1790 pci_conf_print_caplist(pc, tag, regs, capoff); 1791 #else 1792 pci_conf_print_caplist(regs, capoff); 1793 #endif 1794 printf("\n"); 1795 } 1796 1797 /* device-dependent header */ 1798 printf(" Device-dependent header:\n"); 1799 pci_conf_print_regs(regs, endoff, 256); 1800 printf("\n"); 1801 #ifdef _KERNEL 1802 if (printfn) 1803 (*printfn)(pc, tag, regs); 1804 else 1805 printf(" Don't know how to pretty-print device-dependent header.\n"); 1806 printf("\n"); 1807 #endif /* _KERNEL */ 1808 } 1809
Indexes created Fri Sep 26 20:09:58 GMT 2025