pci_subr.c revision 1.112
1 /* $NetBSD: pci_subr.c,v 1.112 2014/05/15 06:58:19 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.112 2014/05/15 06:58:19 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdbool.h> 58 #include <stdio.h> 59 #endif 60 61 #include <dev/pci/pcireg.h> 62 #ifdef _KERNEL 63 #include <dev/pci/pcivar.h> 64 #endif 65 66 /* 67 * Descriptions of known PCI classes and subclasses. 68 * 69 * Subclasses are described in the same way as classes, but have a 70 * NULL subclass pointer. 71 */ 72 struct pci_class { 73 const char *name; 74 u_int val; /* as wide as pci_{,sub}class_t */ 75 const struct pci_class *subclasses; 76 }; 77 78 static const struct pci_class pci_subclass_prehistoric[] = { 79 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 80 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 81 { NULL, 0, NULL, }, 82 }; 83 84 static const struct pci_class pci_subclass_mass_storage[] = { 85 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 86 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 87 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 88 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 89 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 90 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, NULL, }, 91 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, NULL, }, 92 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 93 { "NVM", PCI_SUBCLASS_MASS_STORAGE_NVM, NULL, }, 94 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 95 { NULL, 0, NULL, }, 96 }; 97 98 static const struct pci_class pci_subclass_network[] = { 99 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 100 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 101 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 102 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 103 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 104 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 105 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 106 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 107 { NULL, 0, NULL, }, 108 }; 109 110 static const struct pci_class pci_subclass_display[] = { 111 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, NULL, }, 112 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 113 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 114 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 115 { NULL, 0, NULL, }, 116 }; 117 118 static const struct pci_class pci_subclass_multimedia[] = { 119 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 120 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 121 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 122 { "HD audio", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 123 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 124 { NULL, 0, NULL, }, 125 }; 126 127 static const struct pci_class pci_subclass_memory[] = { 128 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 129 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 130 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 131 { NULL, 0, NULL, }, 132 }; 133 134 static const struct pci_class pci_subclass_bridge[] = { 135 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 136 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 137 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 138 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 139 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, NULL, }, 140 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 141 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 142 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 143 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 144 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, NULL, }, 145 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 146 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 147 { NULL, 0, NULL, }, 148 }; 149 150 static const struct pci_class pci_subclass_communications[] = { 151 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, NULL, }, 152 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, NULL, }, 153 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL, }, 154 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, NULL, }, 155 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL, }, 156 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL, }, 157 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL, }, 158 { NULL, 0, NULL, }, 159 }; 160 161 static const struct pci_class pci_subclass_system[] = { 162 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, NULL, }, 163 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, NULL, }, 164 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, NULL, }, 165 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, NULL, }, 166 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 167 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 168 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 169 { NULL, 0, NULL, }, 170 }; 171 172 static const struct pci_class pci_subclass_input[] = { 173 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 174 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 175 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 176 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 177 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, NULL, }, 178 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 179 { NULL, 0, NULL, }, 180 }; 181 182 static const struct pci_class pci_subclass_dock[] = { 183 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 184 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 185 { NULL, 0, NULL, }, 186 }; 187 188 static const struct pci_class pci_subclass_processor[] = { 189 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 190 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 191 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 192 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 193 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 194 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 195 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 196 { NULL, 0, NULL, }, 197 }; 198 199 static const struct pci_class pci_subclass_serialbus[] = { 200 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, NULL, }, 201 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 202 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 203 { "USB", PCI_SUBCLASS_SERIALBUS_USB, NULL, }, 204 /* XXX Fiber Channel/_FIBRECHANNEL */ 205 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 206 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 207 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 208 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, NULL, }, 209 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 210 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 211 { NULL, 0, NULL, }, 212 }; 213 214 static const struct pci_class pci_subclass_wireless[] = { 215 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 216 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 217 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 218 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 219 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 220 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 221 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 222 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 223 { NULL, 0, NULL, }, 224 }; 225 226 static const struct pci_class pci_subclass_i2o[] = { 227 { "standard", PCI_SUBCLASS_I2O_STANDARD, NULL, }, 228 { NULL, 0, NULL, }, 229 }; 230 231 static const struct pci_class pci_subclass_satcom[] = { 232 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 233 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 234 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 235 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 236 { NULL, 0, NULL, }, 237 }; 238 239 static const struct pci_class pci_subclass_crypto[] = { 240 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 241 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 242 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 243 { NULL, 0, NULL, }, 244 }; 245 246 static const struct pci_class pci_subclass_dasp[] = { 247 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 248 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 249 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 250 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 251 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 252 { NULL, 0, NULL, }, 253 }; 254 255 static const struct pci_class pci_class[] = { 256 { "prehistoric", PCI_CLASS_PREHISTORIC, 257 pci_subclass_prehistoric, }, 258 { "mass storage", PCI_CLASS_MASS_STORAGE, 259 pci_subclass_mass_storage, }, 260 { "network", PCI_CLASS_NETWORK, 261 pci_subclass_network, }, 262 { "display", PCI_CLASS_DISPLAY, 263 pci_subclass_display, }, 264 { "multimedia", PCI_CLASS_MULTIMEDIA, 265 pci_subclass_multimedia, }, 266 { "memory", PCI_CLASS_MEMORY, 267 pci_subclass_memory, }, 268 { "bridge", PCI_CLASS_BRIDGE, 269 pci_subclass_bridge, }, 270 { "communications", PCI_CLASS_COMMUNICATIONS, 271 pci_subclass_communications, }, 272 { "system", PCI_CLASS_SYSTEM, 273 pci_subclass_system, }, 274 { "input", PCI_CLASS_INPUT, 275 pci_subclass_input, }, 276 { "dock", PCI_CLASS_DOCK, 277 pci_subclass_dock, }, 278 { "processor", PCI_CLASS_PROCESSOR, 279 pci_subclass_processor, }, 280 { "serial bus", PCI_CLASS_SERIALBUS, 281 pci_subclass_serialbus, }, 282 { "wireless", PCI_CLASS_WIRELESS, 283 pci_subclass_wireless, }, 284 { "I2O", PCI_CLASS_I2O, 285 pci_subclass_i2o, }, 286 { "satellite comm", PCI_CLASS_SATCOM, 287 pci_subclass_satcom, }, 288 { "crypto", PCI_CLASS_CRYPTO, 289 pci_subclass_crypto, }, 290 { "DASP", PCI_CLASS_DASP, 291 pci_subclass_dasp, }, 292 { "undefined", PCI_CLASS_UNDEFINED, 293 NULL, }, 294 { NULL, 0, 295 NULL, }, 296 }; 297 298 void pci_load_verbose(void); 299 300 #if defined(_KERNEL) 301 /* 302 * In kernel, these routines are provided and linked via the 303 * pciverbose module. 304 */ 305 const char *pci_findvendor_stub(pcireg_t); 306 const char *pci_findproduct_stub(pcireg_t); 307 308 const char *(*pci_findvendor)(pcireg_t) = pci_findvendor_stub; 309 const char *(*pci_findproduct)(pcireg_t) = pci_findproduct_stub; 310 const char *pci_unmatched = ""; 311 #else 312 /* 313 * For userland we just set the vectors here. 314 */ 315 const char *(*pci_findvendor)(pcireg_t id_reg) = pci_findvendor_real; 316 const char *(*pci_findproduct)(pcireg_t id_reg) = pci_findproduct_real; 317 const char *pci_unmatched = "unmatched "; 318 #endif 319 320 int pciverbose_loaded = 0; 321 322 #if defined(_KERNEL) 323 /* 324 * Routine to load the pciverbose kernel module as needed 325 */ 326 void pci_load_verbose(void) 327 { 328 if (pciverbose_loaded == 0) 329 module_autoload("pciverbose", MODULE_CLASS_MISC); 330 } 331 332 const char *pci_findvendor_stub(pcireg_t id_reg) 333 { 334 pci_load_verbose(); 335 if (pciverbose_loaded) 336 return pci_findvendor(id_reg); 337 else 338 return NULL; 339 } 340 341 const char *pci_findproduct_stub(pcireg_t id_reg) 342 { 343 pci_load_verbose(); 344 if (pciverbose_loaded) 345 return pci_findproduct(id_reg); 346 else 347 return NULL; 348 } 349 #endif 350 351 void 352 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 353 size_t l) 354 { 355 pci_vendor_id_t vendor; 356 pci_product_id_t product; 357 pci_class_t class; 358 pci_subclass_t subclass; 359 pci_interface_t interface; 360 pci_revision_t revision; 361 const char *unmatched = pci_unmatched; 362 const char *vendor_namep, *product_namep; 363 const struct pci_class *classp, *subclassp; 364 char *ep; 365 366 ep = cp + l; 367 368 vendor = PCI_VENDOR(id_reg); 369 product = PCI_PRODUCT(id_reg); 370 371 class = PCI_CLASS(class_reg); 372 subclass = PCI_SUBCLASS(class_reg); 373 interface = PCI_INTERFACE(class_reg); 374 revision = PCI_REVISION(class_reg); 375 376 vendor_namep = pci_findvendor(id_reg); 377 product_namep = pci_findproduct(id_reg); 378 379 classp = pci_class; 380 while (classp->name != NULL) { 381 if (class == classp->val) 382 break; 383 classp++; 384 } 385 386 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 387 while (subclassp && subclassp->name != NULL) { 388 if (subclass == subclassp->val) 389 break; 390 subclassp++; 391 } 392 393 if (vendor_namep == NULL) 394 cp += snprintf(cp, ep - cp, "%svendor 0x%04x product 0x%04x", 395 unmatched, vendor, product); 396 else if (product_namep != NULL) 397 cp += snprintf(cp, ep - cp, "%s %s", vendor_namep, 398 product_namep); 399 else 400 cp += snprintf(cp, ep - cp, "%s product 0x%04x", 401 vendor_namep, product); 402 if (showclass) { 403 cp += snprintf(cp, ep - cp, " ("); 404 if (classp->name == NULL) 405 cp += snprintf(cp, ep - cp, 406 "class 0x%02x, subclass 0x%02x", class, subclass); 407 else { 408 if (subclassp == NULL || subclassp->name == NULL) 409 cp += snprintf(cp, ep - cp, 410 "%s, subclass 0x%02x", 411 classp->name, subclass); 412 else 413 cp += snprintf(cp, ep - cp, "%s %s", 414 subclassp->name, classp->name); 415 } 416 if (interface != 0) 417 cp += snprintf(cp, ep - cp, ", interface 0x%02x", 418 interface); 419 if (revision != 0) 420 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 421 revision); 422 cp += snprintf(cp, ep - cp, ")"); 423 } 424 } 425 426 #ifdef _KERNEL 427 void 428 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 429 const char *known, int addrev) 430 { 431 char devinfo[256]; 432 433 if (known) { 434 aprint_normal(": %s", known); 435 if (addrev) 436 aprint_normal(" (rev. 0x%02x)", 437 PCI_REVISION(pa->pa_class)); 438 aprint_normal("\n"); 439 } else { 440 pci_devinfo(pa->pa_id, pa->pa_class, 0, 441 devinfo, sizeof(devinfo)); 442 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 443 PCI_REVISION(pa->pa_class)); 444 } 445 if (naive) 446 aprint_naive(": %s\n", naive); 447 else 448 aprint_naive("\n"); 449 } 450 #endif 451 452 /* 453 * Print out most of the PCI configuration registers. Typically used 454 * in a device attach routine like this: 455 * 456 * #ifdef MYDEV_DEBUG 457 * printf("%s: ", device_xname(sc->sc_dev)); 458 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 459 * #endif 460 */ 461 462 #define i2o(i) ((i) * 4) 463 #define o2i(o) ((o) / 4) 464 #define onoff2(str, rval, bit, onstr, offstr) \ 465 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 466 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 467 468 static void 469 pci_conf_print_common( 470 #ifdef _KERNEL 471 pci_chipset_tag_t pc, pcitag_t tag, 472 #endif 473 const pcireg_t *regs) 474 { 475 const char *name; 476 const struct pci_class *classp, *subclassp; 477 pcireg_t rval; 478 479 rval = regs[o2i(PCI_ID_REG)]; 480 name = pci_findvendor(rval); 481 if (name) 482 printf(" Vendor Name: %s (0x%04x)\n", name, 483 PCI_VENDOR(rval)); 484 else 485 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 486 name = pci_findproduct(rval); 487 if (name) 488 printf(" Device Name: %s (0x%04x)\n", name, 489 PCI_PRODUCT(rval)); 490 else 491 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 492 493 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 494 495 printf(" Command register: 0x%04x\n", rval & 0xffff); 496 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 497 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 498 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 499 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 500 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 501 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 502 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 503 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 504 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 505 onoff("Fast back-to-back transactions", rval, PCI_COMMAND_BACKTOBACK_ENABLE); 506 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 507 508 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 509 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", "inactive"); 510 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 511 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 512 onoff("User Definable Features (UDF) support", rval, PCI_STATUS_UDF_SUPPORT); 513 onoff("Fast back-to-back capable", rval, PCI_STATUS_BACKTOBACK_SUPPORT); 514 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 515 516 printf(" DEVSEL timing: "); 517 switch (rval & PCI_STATUS_DEVSEL_MASK) { 518 case PCI_STATUS_DEVSEL_FAST: 519 printf("fast"); 520 break; 521 case PCI_STATUS_DEVSEL_MEDIUM: 522 printf("medium"); 523 break; 524 case PCI_STATUS_DEVSEL_SLOW: 525 printf("slow"); 526 break; 527 default: 528 printf("unknown/reserved"); /* XXX */ 529 break; 530 } 531 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 532 533 onoff("Slave signaled Target Abort", rval, PCI_STATUS_TARGET_TARGET_ABORT); 534 onoff("Master received Target Abort", rval, PCI_STATUS_MASTER_TARGET_ABORT); 535 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 536 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 537 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 538 539 rval = regs[o2i(PCI_CLASS_REG)]; 540 for (classp = pci_class; classp->name != NULL; classp++) { 541 if (PCI_CLASS(rval) == classp->val) 542 break; 543 } 544 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 545 while (subclassp && subclassp->name != NULL) { 546 if (PCI_SUBCLASS(rval) == subclassp->val) 547 break; 548 subclassp++; 549 } 550 if (classp->name != NULL) { 551 printf(" Class Name: %s (0x%02x)\n", classp->name, 552 PCI_CLASS(rval)); 553 if (subclassp != NULL && subclassp->name != NULL) 554 printf(" Subclass Name: %s (0x%02x)\n", 555 subclassp->name, PCI_SUBCLASS(rval)); 556 else 557 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 558 } else { 559 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 560 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 561 } 562 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 563 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 564 565 rval = regs[o2i(PCI_BHLC_REG)]; 566 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 567 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 568 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 569 PCI_HDRTYPE(rval)); 570 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 571 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 572 } 573 574 static int 575 pci_conf_print_bar( 576 #ifdef _KERNEL 577 pci_chipset_tag_t pc, pcitag_t tag, 578 #endif 579 const pcireg_t *regs, int reg, const char *name 580 #ifdef _KERNEL 581 , int sizebar 582 #endif 583 ) 584 { 585 int width; 586 pcireg_t rval, rval64h; 587 #ifdef _KERNEL 588 int s; 589 pcireg_t mask, mask64h; 590 #endif 591 592 width = 4; 593 594 /* 595 * Section 6.2.5.1, `Address Maps', tells us that: 596 * 597 * 1) The builtin software should have already mapped the 598 * device in a reasonable way. 599 * 600 * 2) A device which wants 2^n bytes of memory will hardwire 601 * the bottom n bits of the address to 0. As recommended, 602 * we write all 1s and see what we get back. 603 */ 604 605 rval = regs[o2i(reg)]; 606 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 607 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 608 rval64h = regs[o2i(reg + 4)]; 609 width = 8; 610 } else 611 rval64h = 0; 612 613 #ifdef _KERNEL 614 /* XXX don't size unknown memory type? */ 615 if (rval != 0 && sizebar) { 616 /* 617 * The following sequence seems to make some devices 618 * (e.g. host bus bridges, which don't normally 619 * have their space mapped) very unhappy, to 620 * the point of crashing the system. 621 * 622 * Therefore, if the mapping register is zero to 623 * start out with, don't bother trying. 624 */ 625 s = splhigh(); 626 pci_conf_write(pc, tag, reg, 0xffffffff); 627 mask = pci_conf_read(pc, tag, reg); 628 pci_conf_write(pc, tag, reg, rval); 629 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 630 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 631 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 632 mask64h = pci_conf_read(pc, tag, reg + 4); 633 pci_conf_write(pc, tag, reg + 4, rval64h); 634 } else 635 mask64h = 0; 636 splx(s); 637 } else 638 mask = mask64h = 0; 639 #endif /* _KERNEL */ 640 641 printf(" Base address register at 0x%02x", reg); 642 if (name) 643 printf(" (%s)", name); 644 printf("\n "); 645 if (rval == 0) { 646 printf("not implemented(?)\n"); 647 return width; 648 } 649 printf("type: "); 650 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 651 const char *type, *prefetch; 652 653 switch (PCI_MAPREG_MEM_TYPE(rval)) { 654 case PCI_MAPREG_MEM_TYPE_32BIT: 655 type = "32-bit"; 656 break; 657 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 658 type = "32-bit-1M"; 659 break; 660 case PCI_MAPREG_MEM_TYPE_64BIT: 661 type = "64-bit"; 662 break; 663 default: 664 type = "unknown (XXX)"; 665 break; 666 } 667 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 668 prefetch = ""; 669 else 670 prefetch = "non"; 671 printf("%s %sprefetchable memory\n", type, prefetch); 672 switch (PCI_MAPREG_MEM_TYPE(rval)) { 673 case PCI_MAPREG_MEM_TYPE_64BIT: 674 printf(" base: 0x%016llx, ", 675 PCI_MAPREG_MEM64_ADDR( 676 ((((long long) rval64h) << 32) | rval))); 677 #ifdef _KERNEL 678 if (sizebar) 679 printf("size: 0x%016llx", 680 PCI_MAPREG_MEM64_SIZE( 681 ((((long long) mask64h) << 32) | mask))); 682 else 683 #endif /* _KERNEL */ 684 printf("not sized"); 685 printf("\n"); 686 break; 687 case PCI_MAPREG_MEM_TYPE_32BIT: 688 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 689 default: 690 printf(" base: 0x%08x, ", 691 PCI_MAPREG_MEM_ADDR(rval)); 692 #ifdef _KERNEL 693 if (sizebar) 694 printf("size: 0x%08x", 695 PCI_MAPREG_MEM_SIZE(mask)); 696 else 697 #endif /* _KERNEL */ 698 printf("not sized"); 699 printf("\n"); 700 break; 701 } 702 } else { 703 #ifdef _KERNEL 704 if (sizebar) 705 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 706 #endif /* _KERNEL */ 707 printf("i/o\n"); 708 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 709 #ifdef _KERNEL 710 if (sizebar) 711 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 712 else 713 #endif /* _KERNEL */ 714 printf("not sized"); 715 printf("\n"); 716 } 717 718 return width; 719 } 720 721 static void 722 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 723 { 724 int off, needaddr, neednl; 725 726 needaddr = 1; 727 neednl = 0; 728 for (off = first; off < pastlast; off += 4) { 729 if ((off % 16) == 0 || needaddr) { 730 printf(" 0x%02x:", off); 731 needaddr = 0; 732 } 733 printf(" 0x%08x", regs[o2i(off)]); 734 neednl = 1; 735 if ((off % 16) == 12) { 736 printf("\n"); 737 neednl = 0; 738 } 739 } 740 if (neednl) 741 printf("\n"); 742 } 743 744 static void 745 pci_conf_print_type0( 746 #ifdef _KERNEL 747 pci_chipset_tag_t pc, pcitag_t tag, 748 #endif 749 const pcireg_t *regs 750 #ifdef _KERNEL 751 , int sizebars 752 #endif 753 ) 754 { 755 int off, width; 756 pcireg_t rval; 757 758 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 759 #ifdef _KERNEL 760 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 761 #else 762 width = pci_conf_print_bar(regs, off, NULL); 763 #endif 764 } 765 766 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 767 768 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 769 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 770 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 771 772 /* XXX */ 773 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 774 775 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 776 printf(" Capability list pointer: 0x%02x\n", 777 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 778 else 779 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 780 781 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 782 783 rval = regs[o2i(PCI_INTERRUPT_REG)]; 784 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 785 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 786 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 787 switch (PCI_INTERRUPT_PIN(rval)) { 788 case PCI_INTERRUPT_PIN_NONE: 789 printf("(none)"); 790 break; 791 case PCI_INTERRUPT_PIN_A: 792 printf("(pin A)"); 793 break; 794 case PCI_INTERRUPT_PIN_B: 795 printf("(pin B)"); 796 break; 797 case PCI_INTERRUPT_PIN_C: 798 printf("(pin C)"); 799 break; 800 case PCI_INTERRUPT_PIN_D: 801 printf("(pin D)"); 802 break; 803 default: 804 printf("(? ? ?)"); 805 break; 806 } 807 printf("\n"); 808 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 809 } 810 811 static void 812 pci_print_pcie_L0s_latency(uint32_t val) 813 { 814 815 switch (val) { 816 case 0x0: 817 printf("Less than 64ns\n"); 818 break; 819 case 0x1: 820 case 0x2: 821 case 0x3: 822 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 823 break; 824 case 0x4: 825 printf("512ns to less than 1us\n"); 826 break; 827 case 0x5: 828 printf("1us to less than 2us\n"); 829 break; 830 case 0x6: 831 printf("2us - 4us\n"); 832 break; 833 case 0x7: 834 printf("More than 4us\n"); 835 break; 836 } 837 } 838 839 static void 840 pci_print_pcie_L1_latency(uint32_t val) 841 { 842 843 switch (val) { 844 case 0x0: 845 printf("Less than 1us\n"); 846 break; 847 case 0x6: 848 printf("32us - 64us\n"); 849 break; 850 case 0x7: 851 printf("More than 64us\n"); 852 break; 853 default: 854 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 855 break; 856 } 857 } 858 859 static void 860 pci_print_pcie_compl_timeout(uint32_t val) 861 { 862 863 switch (val) { 864 case 0x0: 865 printf("50us to 50ms\n"); 866 break; 867 case 0x5: 868 printf("16ms to 55ms\n"); 869 break; 870 case 0x6: 871 printf("65ms to 210ms\n"); 872 break; 873 case 0x9: 874 printf("260ms to 900ms\n"); 875 break; 876 case 0xa: 877 printf("1s to 3.5s\n"); 878 break; 879 default: 880 printf("unknown %u value\n", val); 881 break; 882 } 883 } 884 885 static void 886 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 887 { 888 pcireg_t reg; /* for each register */ 889 pcireg_t val; /* for each bitfield */ 890 bool check_link = false; 891 bool check_slot = false; 892 bool check_rootport = false; 893 unsigned int pciever; 894 static const char * const linkspeeds[] = {"2.5", "5.0", "8.0"}; 895 int i; 896 897 printf("\n PCI Express Capabilities Register\n"); 898 /* Capability Register */ 899 reg = regs[o2i(capoff)]; 900 printf(" Capability register: %04x\n", reg >> 16); 901 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 902 printf(" Capability version: %u\n", pciever); 903 printf(" Device type: "); 904 switch ((reg & 0x00f00000) >> 20) { 905 case 0x0: 906 printf("PCI Express Endpoint device\n"); 907 check_link = true; 908 break; 909 case 0x1: 910 printf("Legacy PCI Express Endpoint device\n"); 911 check_link = true; 912 break; 913 case 0x4: 914 printf("Root Port of PCI Express Root Complex\n"); 915 check_link = true; 916 check_slot = true; 917 check_rootport = true; 918 break; 919 case 0x5: 920 printf("Upstream Port of PCI Express Switch\n"); 921 break; 922 case 0x6: 923 printf("Downstream Port of PCI Express Switch\n"); 924 check_slot = true; 925 check_rootport = true; 926 break; 927 case 0x7: 928 printf("PCI Express to PCI/PCI-X Bridge\n"); 929 break; 930 case 0x8: 931 printf("PCI/PCI-X to PCI Express Bridge\n"); 932 break; 933 case 0x9: 934 printf("Root Complex Integrated Endpoint\n"); 935 break; 936 case 0xa: 937 check_rootport = true; 938 printf("Root Complex Event Collector\n"); 939 break; 940 default: 941 printf("unknown\n"); 942 break; 943 } 944 if (check_slot && (reg & PCIE_XCAP_SI) != 0) 945 printf(" Slot implemented\n"); 946 printf(" Interrupt Message Number: %x\n", 947 (unsigned int)((reg & PCIE_XCAP_IRQ) >> 27)); 948 949 /* Device Capability Register */ 950 reg = regs[o2i(capoff + PCIE_DCAP)]; 951 printf(" Device Capabilities Register: 0x%08x\n", reg); 952 printf(" Max Payload Size Supported: %u bytes max\n", 953 (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD) * 256); 954 printf(" Phantom Functions Supported: "); 955 switch ((reg & PCIE_DCAP_PHANTOM_FUNCS) >> 3) { 956 case 0x0: 957 printf("not available\n"); 958 break; 959 case 0x1: 960 printf("MSB\n"); 961 break; 962 case 0x2: 963 printf("two MSB\n"); 964 break; 965 case 0x3: 966 printf("All three bits\n"); 967 break; 968 } 969 printf(" Extended Tag Field Supported: %dbit\n", 970 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 971 printf(" Endpoint L0 Acceptable Latency: "); 972 pci_print_pcie_L0s_latency((reg & PCIE_DCAP_L0S_LATENCY) >> 6); 973 printf(" Endpoint L1 Acceptable Latency: "); 974 pci_print_pcie_L1_latency((reg & PCIE_DCAP_L1_LATENCY) >> 9); 975 onoff("Attention Button Present:", reg, PCIE_DCAP_ATTN_BUTTON); 976 onoff("Attention Indicator Present:", reg, PCIE_DCAP_ATTN_IND); 977 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 978 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 979 printf(" Captured Slot Power Limit Value: %d\n", 980 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18); 981 printf(" Captured Slot Power Limit Scale: %d\n", 982 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26); 983 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 984 985 /* Device Control Register */ 986 reg = regs[o2i(capoff + PCIE_DCSR)]; 987 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 988 onoff("Correctable Error Reporting Enable", reg, 989 PCIE_DCSR_ENA_COR_ERR); 990 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 991 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 992 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 993 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 994 printf(" Max Payload Size: %d byte\n", 995 128 << (((unsigned int)(reg & PCIE_DCSR_MAX_PAYLOAD) >> 5))); 996 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 997 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 998 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 999 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1000 printf(" Max Read Request Size: %d byte\n", 1001 128 << ((unsigned int)(reg & PCIE_DCSR_MAX_READ_REQ) >> 12)); 1002 1003 /* Device Status Register */ 1004 reg = regs[o2i(capoff + PCIE_DCSR)]; 1005 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1006 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1007 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1008 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1009 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1010 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1011 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1012 1013 if (check_link) { 1014 /* Link Capability Register */ 1015 reg = regs[o2i(capoff + PCIE_LCAP)]; 1016 printf(" Link Capabilities Register: 0x%08x\n", reg); 1017 printf(" Maximum Link Speed: "); 1018 val = reg & PCIE_LCAP_MAX_SPEED; 1019 if (val < 1 || val > 3) { 1020 printf("unknown %u value\n", val); 1021 } else { 1022 printf("%sGT/s\n", linkspeeds[val - 1]); 1023 } 1024 printf(" Maximum Link Width: x%u lanes\n", 1025 (unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4); 1026 printf(" Active State PM Support: "); 1027 val = (reg & PCIE_LCAP_ASPM) >> 10; 1028 switch (val) { 1029 case 0x1: 1030 printf("L0s Entry supported\n"); 1031 break; 1032 case 0x3: 1033 printf("L0s and L1 supported\n"); 1034 break; 1035 default: 1036 printf("Reserved value\n"); 1037 break; 1038 } 1039 printf(" L0 Exit Latency: "); 1040 pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12); 1041 printf(" L1 Exit Latency: "); 1042 pci_print_pcie_L1_latency((reg & PCIE_LCAP_L1_EXIT) >> 15); 1043 printf(" Port Number: %u\n", reg >> 24); 1044 1045 /* Link Control Register */ 1046 reg = regs[o2i(capoff + PCIE_LCSR)]; 1047 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1048 printf(" Active State PM Control: "); 1049 val = reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S); 1050 switch (val) { 1051 case 0: 1052 printf("disabled\n"); 1053 break; 1054 case 1: 1055 printf("L0s Entry Enabled\n"); 1056 break; 1057 case 2: 1058 printf("L1 Entry Enabled\n"); 1059 break; 1060 case 3: 1061 printf("L0s and L1 Entry Enabled\n"); 1062 break; 1063 } 1064 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1065 "128bytes", "64bytes"); 1066 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1067 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1068 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1069 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1070 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1071 onoff("Hardware Autonomous Width Disable", reg, 1072 PCIE_LCSR_HAWD); 1073 onoff("Link Bandwidth Management Interrupt Enable", reg, 1074 PCIE_LCSR_LBMIE); 1075 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1076 PCIE_LCSR_LABIE); 1077 1078 /* Link Status Register */ 1079 reg = regs[o2i(capoff + PCIE_LCSR)]; 1080 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1081 printf(" Negotiated Link Speed: "); 1082 if (((reg >> 16) & 0x000f) < 1 || 1083 ((reg >> 16) & 0x000f) > 3) { 1084 printf("unknown %u value\n", 1085 (unsigned int)(reg & PCIE_LCSR_LINKSPEED) >> 16); 1086 } else { 1087 printf("%sGT/s\n", 1088 linkspeeds[((reg & PCIE_LCSR_LINKSPEED) >> 16) - 1]); 1089 } 1090 printf(" Negotiated Link Width: x%u lanes\n", 1091 (reg >> 20) & 0x003f); 1092 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1093 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1094 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1095 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1096 onoff("Link Bandwidth Management Status", reg, 1097 PCIE_LCSR_LINK_BW_MGMT); 1098 onoff("Link Autonomous Bandwidth Status", reg, 1099 PCIE_LCSR_LINK_AUTO_BW); 1100 } 1101 1102 if (check_slot == true) { 1103 /* Slot Capability Register */ 1104 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1105 printf(" Slot Capability Register: %08x\n", reg); 1106 if ((reg & PCIE_SLCAP_ABP) != 0) 1107 printf(" Attention Button Present\n"); 1108 if ((reg & PCIE_SLCAP_PCP) != 0) 1109 printf(" Power Controller Present\n"); 1110 if ((reg & PCIE_SLCAP_MSP) != 0) 1111 printf(" MRL Sensor Present\n"); 1112 if ((reg & PCIE_SLCAP_AIP) != 0) 1113 printf(" Attention Indicator Present\n"); 1114 if ((reg & PCIE_SLCAP_PIP) != 0) 1115 printf(" Power Indicator Present\n"); 1116 if ((reg & PCIE_SLCAP_HPS) != 0) 1117 printf(" Hot-Plug Surprise\n"); 1118 if ((reg & PCIE_SLCAP_HPC) != 0) 1119 printf(" Hot-Plug Capable\n"); 1120 printf(" Slot Power Limit Value: %d\n", 1121 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1122 printf(" Slot Power Limit Scale: %d\n", 1123 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1124 if ((reg & PCIE_SLCAP_EIP) != 0) 1125 printf(" Electromechanical Interlock Present\n"); 1126 if ((reg & PCIE_SLCAP_NCCS) != 0) 1127 printf(" No Command Completed Support\n"); 1128 printf(" Physical Slot Number: %d\n", 1129 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1130 1131 /* Slot Control Register */ 1132 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1133 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1134 if ((reg & PCIE_SLCSR_ABE) != 0) 1135 printf(" Attention Button Pressed Enabled\n"); 1136 if ((reg & PCIE_SLCSR_PFE) != 0) 1137 printf(" Power Fault Detected Enabled\n"); 1138 if ((reg & PCIE_SLCSR_MSE) != 0) 1139 printf(" MRL Sensor Changed Enabled\n"); 1140 if ((reg & PCIE_SLCSR_PDE) != 0) 1141 printf(" Presense Detect Changed Enabled\n"); 1142 if ((reg & PCIE_SLCSR_CCE) != 0) 1143 printf(" Command Completed Interrupt Enabled\n"); 1144 if ((reg & PCIE_SLCSR_HPE) != 0) 1145 printf(" Hot-Plug Interrupt Enabled\n"); 1146 printf(" Attention Indicator Control: "); 1147 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1148 case 0x0: 1149 printf("reserved\n"); 1150 break; 1151 case 0x1: 1152 printf("on\n"); 1153 break; 1154 case 0x2: 1155 printf("blink\n"); 1156 break; 1157 case 0x3: 1158 printf("off\n"); 1159 break; 1160 } 1161 printf(" Power Indicator Control: "); 1162 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1163 case 0x0: 1164 printf("reserved\n"); 1165 break; 1166 case 0x1: 1167 printf("on\n"); 1168 break; 1169 case 0x2: 1170 printf("blink\n"); 1171 break; 1172 case 0x3: 1173 printf("off\n"); 1174 break; 1175 } 1176 printf(" Power Controller Control: "); 1177 if ((reg & PCIE_SLCSR_PCC) != 0) 1178 printf("off\n"); 1179 else 1180 printf("on\n"); 1181 if ((reg & PCIE_SLCSR_EIC) != 0) 1182 printf(" Electromechanical Interlock Control\n"); 1183 if ((reg & PCIE_SLCSR_LACS) != 0) 1184 printf(" Data Link Layer State Changed Enable\n"); 1185 1186 /* Slot Status Register */ 1187 printf(" Slot Status Register: %04x\n", reg >> 16); 1188 if ((reg & PCIE_SLCSR_ABP) != 0) 1189 printf(" Attention Button Pressed\n"); 1190 if ((reg & PCIE_SLCSR_PFD) != 0) 1191 printf(" Power Fault Detected\n"); 1192 if ((reg & PCIE_SLCSR_MSC) != 0) 1193 printf(" MRL Sensor Changed\n"); 1194 if ((reg & PCIE_SLCSR_PDC) != 0) 1195 printf(" Presense Detect Changed\n"); 1196 if ((reg & PCIE_SLCSR_CC) != 0) 1197 printf(" Command Completed\n"); 1198 if ((reg & PCIE_SLCSR_MS) != 0) 1199 printf(" MRL Open\n"); 1200 if ((reg & PCIE_SLCSR_PDS) != 0) 1201 printf(" Card Present in slot\n"); 1202 if ((reg & PCIE_SLCSR_EIS) != 0) 1203 printf(" Electromechanical Interlock engaged\n"); 1204 if ((reg & PCIE_SLCSR_LACS) != 0) 1205 printf(" Data Link Layer State Changed\n"); 1206 } 1207 1208 if (check_rootport == true) { 1209 /* Root Control Register */ 1210 reg = regs[o2i(capoff + PCIE_RCR)]; 1211 printf(" Root Control Register: %04x\n", reg & 0xffff); 1212 if ((reg & PCIE_RCR_SERR_CER) != 0) 1213 printf(" SERR on Correctable Error Enable\n"); 1214 if ((reg & PCIE_RCR_SERR_NFER) != 0) 1215 printf(" SERR on Non-Fatal Error Enable\n"); 1216 if ((reg & PCIE_RCR_SERR_FER) != 0) 1217 printf(" SERR on Fatal Error Enable\n"); 1218 if ((reg & PCIE_RCR_PME_IE) != 0) 1219 printf(" PME Interrupt Enable\n"); 1220 if ((reg & PCIE_RCR_CRS_SVE) != 0) 1221 printf(" CRS Software Visibility Enable\n"); 1222 1223 /* Root Capability Register */ 1224 printf(" Root Capability Register: %04x\n", 1225 reg >> 16); 1226 1227 /* Root Status Register */ 1228 reg = regs[o2i(capoff + PCIE_RSR)]; 1229 printf(" Root Status Register: %08x\n", reg); 1230 printf(" PME Requester ID: %04x\n", 1231 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1232 if ((reg & PCIE_RSR_PME_STAT) != 0) 1233 printf(" PME was asserted\n"); 1234 if ((reg & PCIE_RSR_PME_PEND) != 0) 1235 printf(" another PME is pending\n"); 1236 } 1237 1238 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1239 if (pciever < 2) 1240 return; 1241 1242 /* Device Capabilities 2 */ 1243 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1244 printf(" Device Capabilities 2: 0x%08x\n", reg); 1245 printf(" Completion Timeout Ranges Supported: %u \n", 1246 (unsigned int)(reg & PCIE_DCAP2_COMPT_RANGE)); 1247 onoff("Completion Timeout Disable Supported", reg, 1248 PCIE_DCAP2_COMPT_DIS); 1249 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 1250 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 1251 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 1252 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 1253 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 1254 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 1255 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 1256 printf(" TPH Completer Supported: %u\n", 1257 (unsigned int)(reg & PCIE_DCAP2_TPH_COMP) >> 12); 1258 printf(" OBFF Supported: "); 1259 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 1260 case 0x0: 1261 printf("Not supported\n"); 1262 break; 1263 case 0x1: 1264 printf("Message only\n"); 1265 break; 1266 case 0x2: 1267 printf("WAKE# only\n"); 1268 break; 1269 case 0x3: 1270 printf("Both\n"); 1271 break; 1272 } 1273 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 1274 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 1275 printf(" Max End-End TLP Prefixes: %u\n", 1276 (unsigned int)(reg & PCIE_DCAP2_MAX_EETLP) >> 22); 1277 1278 /* Device Control 2 */ 1279 reg = regs[o2i(capoff + PCIE_DCSR2)]; 1280 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 1281 printf(" Completion Timeout Value: "); 1282 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 1283 if ((reg & PCIE_DCSR2_COMPT_DIS) != 0) 1284 printf(" Completion Timeout Disabled\n"); 1285 if ((reg & PCIE_DCSR2_ARI_FWD) != 0) 1286 printf(" ARI Forwarding Enabled\n"); 1287 if ((reg & PCIE_DCSR2_ATOM_REQ) != 0) 1288 printf(" AtomicOp Rquester Enabled\n"); 1289 if ((reg & PCIE_DCSR2_ATOM_EBLK) != 0) 1290 printf(" AtomicOp Egress Blocking on\n"); 1291 if ((reg & PCIE_DCSR2_IDO_REQ) != 0) 1292 printf(" IDO Request Enabled\n"); 1293 if ((reg & PCIE_DCSR2_IDO_COMP) != 0) 1294 printf(" IDO Completion Enabled\n"); 1295 if ((reg & PCIE_DCSR2_LTR_MEC) != 0) 1296 printf(" LTR Mechanism Enabled\n"); 1297 printf(" OBFF: "); 1298 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 1299 case 0x0: 1300 printf("Disabled\n"); 1301 break; 1302 case 0x1: 1303 printf("Enabled with Message Signaling Variation A\n"); 1304 break; 1305 case 0x2: 1306 printf("Enabled with Message Signaling Variation B\n"); 1307 break; 1308 case 0x3: 1309 printf("Enabled using WAKE# signaling\n"); 1310 break; 1311 } 1312 if ((reg & PCIE_DCSR2_EETLP) != 0) 1313 printf(" End-End TLP Prefix Blocking on\n"); 1314 1315 if (check_link) { 1316 /* Link Capability 2 */ 1317 reg = regs[o2i(capoff + PCIE_LCAP2)]; 1318 printf(" Link Capabilities 2: 0x%08x\n", reg); 1319 val = (reg & PCIE_LCAP2_SUP_LNKSV) >> 1; 1320 printf(" Supported Link Speed Vector:"); 1321 for (i = 0; i <= 2; i++) { 1322 if (((val >> i) & 0x01) != 0) 1323 printf(" %sGT/s", linkspeeds[i]); 1324 } 1325 printf("\n"); 1326 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 1327 1328 /* Link Control 2 */ 1329 reg = regs[o2i(capoff + PCIE_LCSR2)]; 1330 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 1331 printf(" Target Link Speed: "); 1332 val = reg & PCIE_LCSR2_TGT_LSPEED; 1333 if (val < 1 || val > 3) { 1334 printf("unknown %u value\n", val); 1335 } else { 1336 printf("%sGT/s\n", linkspeeds[val - 1]); 1337 } 1338 if ((reg & PCIE_LCSR2_ENT_COMPL) != 0) 1339 printf(" Enter Compliance Enabled\n"); 1340 if ((reg & PCIE_LCSR2_HW_AS_DIS) != 0) 1341 printf(" HW Autonomous Speed Disabled\n"); 1342 if ((reg & PCIE_LCSR2_SEL_DEEMP) != 0) 1343 printf(" Selectable De-emphasis\n"); 1344 printf(" Transmit Margin: %u\n", 1345 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 1346 if ((reg & PCIE_LCSR2_EN_MCOMP) != 0) 1347 printf(" Enter Modified Compliance\n"); 1348 if ((reg & PCIE_LCSR2_COMP_SOS) != 0) 1349 printf(" Compliance SOS\n"); 1350 printf(" Compliance Present/De-emphasis: %u\n", 1351 (unsigned int)(reg & PCIE_LCSR2_COMP_DEEMP) >> 12); 1352 1353 /* Link Status 2 */ 1354 if ((reg & PCIE_LCSR2_DEEMP_LVL) != 0) 1355 printf(" Current De-emphasis Level\n"); 1356 if ((reg & PCIE_LCSR2_EQ_COMPL) != 0) 1357 printf(" Equalization Complete\n"); 1358 if ((reg & PCIE_LCSR2_EQP1_SUC) != 0) 1359 printf(" Equalization Phase 1 Successful\n"); 1360 if ((reg & PCIE_LCSR2_EQP2_SUC) != 0) 1361 printf(" Equalization Phase 2 Successful\n"); 1362 if ((reg & PCIE_LCSR2_EQP3_SUC) != 0) 1363 printf(" Equalization Phase 3 Successful\n"); 1364 if ((reg & PCIE_LCSR2_LNKEQ_REQ) != 0) 1365 printf(" Link Equalization Request\n"); 1366 } 1367 1368 /* Slot Capability 2 */ 1369 /* Slot Control 2 */ 1370 /* Slot Status 2 */ 1371 } 1372 1373 static const char * 1374 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1375 { 1376 switch ((caps >> 6) & 7) { 1377 case 0: return "self-powered"; 1378 case 1: return "55 mA"; 1379 case 2: return "100 mA"; 1380 case 3: return "160 mA"; 1381 case 4: return "220 mA"; 1382 case 5: return "270 mA"; 1383 case 6: return "320 mA"; 1384 case 7: 1385 default: return "375 mA"; 1386 } 1387 } 1388 1389 static const char * 1390 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1391 { 1392 static const char unk[] = "unknown"; 1393 static const char *pmrev[8] = { 1394 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1395 }; 1396 if (val > 7) 1397 return unk; 1398 return pmrev[val]; 1399 } 1400 1401 static void 1402 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1403 { 1404 uint16_t caps, pmcsr; 1405 1406 caps = regs[o2i(capoff)] >> 16; 1407 pmcsr = regs[o2i(capoff + 0x04)] & 0xffff; 1408 1409 printf("\n PCI Power Management Capabilities Register\n"); 1410 1411 printf(" Capabilities register: 0x%04x\n", caps); 1412 printf(" Version: %s\n", 1413 pci_conf_print_pcipm_cap_pmrev(caps & 0x3)); 1414 onoff("PME# clock", caps, 0x4); 1415 onoff("Device specific initialization", caps, 0x20); 1416 printf(" 3.3V auxiliary current: %s\n", 1417 pci_conf_print_pcipm_cap_aux(caps)); 1418 onoff("D1 power management state support", (caps >> 9), 1); 1419 onoff("D2 power management state support", (caps >> 10), 1); 1420 printf(" PME# support: 0x%02x\n", caps >> 11); 1421 1422 printf(" Control/status register: 0x%04x\n", pmcsr); 1423 printf(" Power state: D%d\n", pmcsr & 3); 1424 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1425 onoff("No soft reset", (pmcsr >> 3), 1); 1426 printf(" PME# assertion %sabled\n", 1427 (pmcsr >> 8) & 1 ? "en" : "dis"); 1428 printf(" PME# status: %s\n", (pmcsr >> 15) ? "on" : "off"); 1429 } 1430 1431 static void 1432 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1433 { 1434 uint32_t ctl, mmc, mme; 1435 1436 regs += o2i(capoff); 1437 ctl = *regs++; 1438 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1439 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1440 1441 printf("\n PCI Message Signaled Interrupt\n"); 1442 1443 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1444 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1445 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1446 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1447 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1448 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1449 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1450 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1451 printf(" Message Address %sregister: 0x%08x\n", 1452 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1453 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1454 printf(" Message Address %sregister: 0x%08x\n", 1455 "(upper) ", *regs++); 1456 } 1457 printf(" Message Data register: 0x%08x\n", *regs++); 1458 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1459 printf(" Vector Mask register: 0x%08x\n", *regs++); 1460 printf(" Vector Pending register: 0x%08x\n", *regs++); 1461 } 1462 } 1463 static void 1464 pci_conf_print_caplist( 1465 #ifdef _KERNEL 1466 pci_chipset_tag_t pc, pcitag_t tag, 1467 #endif 1468 const pcireg_t *regs, int capoff) 1469 { 1470 int off; 1471 pcireg_t rval; 1472 int pcie_off = -1, pcipm_off = -1, msi_off = -1; 1473 1474 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1475 off != 0; 1476 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 1477 rval = regs[o2i(off)]; 1478 printf(" Capability register at 0x%02x\n", off); 1479 1480 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 1481 switch (PCI_CAPLIST_CAP(rval)) { 1482 case PCI_CAP_RESERVED0: 1483 printf("reserved"); 1484 break; 1485 case PCI_CAP_PWRMGMT: 1486 printf("Power Management, rev. %s", 1487 pci_conf_print_pcipm_cap_pmrev((rval >> 0) & 0x07)); 1488 pcipm_off = off; 1489 break; 1490 case PCI_CAP_AGP: 1491 printf("AGP, rev. %d.%d", 1492 PCI_CAP_AGP_MAJOR(rval), 1493 PCI_CAP_AGP_MINOR(rval)); 1494 break; 1495 case PCI_CAP_VPD: 1496 printf("VPD"); 1497 break; 1498 case PCI_CAP_SLOTID: 1499 printf("SlotID"); 1500 break; 1501 case PCI_CAP_MSI: 1502 printf("MSI"); 1503 msi_off = off; 1504 break; 1505 case PCI_CAP_CPCI_HOTSWAP: 1506 printf("CompactPCI Hot-swapping"); 1507 break; 1508 case PCI_CAP_PCIX: 1509 printf("PCI-X"); 1510 break; 1511 case PCI_CAP_LDT: 1512 printf("LDT"); 1513 break; 1514 case PCI_CAP_VENDSPEC: 1515 printf("Vendor-specific"); 1516 break; 1517 case PCI_CAP_DEBUGPORT: 1518 printf("Debug Port"); 1519 break; 1520 case PCI_CAP_CPCI_RSRCCTL: 1521 printf("CompactPCI Resource Control"); 1522 break; 1523 case PCI_CAP_HOTPLUG: 1524 printf("Hot-Plug"); 1525 break; 1526 case PCI_CAP_SUBVENDOR: 1527 printf("Sub Vendor ID"); 1528 break; 1529 case PCI_CAP_AGP8: 1530 printf("AGP 8x"); 1531 break; 1532 case PCI_CAP_SECURE: 1533 printf("Secure Device"); 1534 break; 1535 case PCI_CAP_PCIEXPRESS: 1536 printf("PCI Express"); 1537 pcie_off = off; 1538 break; 1539 case PCI_CAP_MSIX: 1540 printf("MSI-X"); 1541 break; 1542 case PCI_CAP_SATA: 1543 printf("SATA"); 1544 break; 1545 case PCI_CAP_PCIAF: 1546 printf("Advanced Features"); 1547 break; 1548 default: 1549 printf("unknown"); 1550 } 1551 printf(")\n"); 1552 } 1553 if (msi_off != -1) 1554 pci_conf_print_msi_cap(regs, msi_off); 1555 if (pcipm_off != -1) 1556 pci_conf_print_pcipm_cap(regs, pcipm_off); 1557 if (pcie_off != -1) 1558 pci_conf_print_pcie_cap(regs, pcie_off); 1559 } 1560 1561 /* Print the Secondary Status Register. */ 1562 static void 1563 pci_conf_print_ssr(pcireg_t rval) 1564 { 1565 pcireg_t devsel; 1566 1567 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 1568 onoff("66 MHz capable", rval, __BIT(5)); 1569 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 1570 onoff("Fast back-to-back capable", rval, __BIT(7)); 1571 onoff("Data parity error detected", rval, __BIT(8)); 1572 1573 printf(" DEVSEL timing: "); 1574 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 1575 switch (devsel) { 1576 case 0: 1577 printf("fast"); 1578 break; 1579 case 1: 1580 printf("medium"); 1581 break; 1582 case 2: 1583 printf("slow"); 1584 break; 1585 default: 1586 printf("unknown/reserved"); /* XXX */ 1587 break; 1588 } 1589 printf(" (0x%x)\n", devsel); 1590 1591 onoff("Signalled target abort", rval, __BIT(11)); 1592 onoff("Received target abort", rval, __BIT(12)); 1593 onoff("Received master abort", rval, __BIT(13)); 1594 onoff("Received system error", rval, __BIT(14)); 1595 onoff("Detected parity error", rval, __BIT(15)); 1596 } 1597 1598 static void 1599 pci_conf_print_type1( 1600 #ifdef _KERNEL 1601 pci_chipset_tag_t pc, pcitag_t tag, 1602 #endif 1603 const pcireg_t *regs 1604 #ifdef _KERNEL 1605 , int sizebars 1606 #endif 1607 ) 1608 { 1609 int off, width; 1610 pcireg_t rval; 1611 uint32_t base, limit; 1612 uint32_t base_h, limit_h; 1613 uint64_t pbase, plimit; 1614 int use_upper; 1615 1616 /* 1617 * XXX these need to be printed in more detail, need to be 1618 * XXX checked against specs/docs, etc. 1619 * 1620 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 1621 * Bridge chip documentation, and may not be correct with 1622 * respect to various standards. (XXX) 1623 */ 1624 1625 for (off = 0x10; off < 0x18; off += width) { 1626 #ifdef _KERNEL 1627 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 1628 #else 1629 width = pci_conf_print_bar(regs, off, NULL); 1630 #endif 1631 } 1632 1633 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 1634 printf(" Primary bus number: 0x%02x\n", 1635 (rval >> 0) & 0xff); 1636 printf(" Secondary bus number: 0x%02x\n", 1637 (rval >> 8) & 0xff); 1638 printf(" Subordinate bus number: 0x%02x\n", 1639 (rval >> 16) & 0xff); 1640 printf(" Secondary bus latency timer: 0x%02x\n", 1641 (rval >> 24) & 0xff); 1642 1643 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 1644 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 1645 1646 /* I/O region */ 1647 printf(" I/O region:\n"); 1648 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 1649 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 1650 if (PCI_BRIDGE_IO_32BITS(rval)) 1651 use_upper = 1; 1652 else 1653 use_upper = 0; 1654 onoff("32bit I/O", rval, use_upper); 1655 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 1656 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 1657 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 1658 limit |= 0x00000fff; 1659 1660 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 1661 base_h = (rval >> 0) & 0xffff; 1662 limit_h = (rval >> 16) & 0xffff; 1663 printf(" base upper 16 bits register: 0x%04x\n", base_h); 1664 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 1665 1666 if (use_upper == 1) { 1667 base |= base_h << 16; 1668 limit |= limit_h << 16; 1669 } 1670 if (base < limit) { 1671 if (use_upper == 1) 1672 printf(" range: 0x%08x-0x%08x\n", base, limit); 1673 else 1674 printf(" range: 0x%04x-0x%04x\n", base, limit); 1675 } 1676 1677 /* Non-prefetchable memory region */ 1678 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 1679 printf(" Memory region:\n"); 1680 printf(" base register: 0x%04x\n", 1681 (rval >> 0) & 0xffff); 1682 printf(" limit register: 0x%04x\n", 1683 (rval >> 16) & 0xffff); 1684 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 1685 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 1686 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 1687 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 1688 if (base < limit) 1689 printf(" range: 0x%08x-0x%08x\n", base, limit); 1690 1691 /* Prefetchable memory region */ 1692 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 1693 printf(" Prefetchable memory region:\n"); 1694 printf(" base register: 0x%04x\n", 1695 (rval >> 0) & 0xffff); 1696 printf(" limit register: 0x%04x\n", 1697 (rval >> 16) & 0xffff); 1698 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 1699 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 1700 printf(" base upper 32 bits register: 0x%08x\n", 1701 base_h); 1702 printf(" limit upper 32 bits register: 0x%08x\n", 1703 limit_h); 1704 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 1705 use_upper = 1; 1706 else 1707 use_upper = 0; 1708 onoff("64bit memory address", rval, use_upper); 1709 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 1710 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 1711 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 1712 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 1713 if (use_upper == 1) { 1714 pbase |= (uint64_t)base_h << 32; 1715 plimit |= (uint64_t)limit_h << 32; 1716 } 1717 if (pbase < plimit) { 1718 if (use_upper == 1) 1719 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 "\n", 1720 pbase, plimit); 1721 else 1722 printf(" range: 0x%08x-0x%08x\n", 1723 (uint32_t)pbase, (uint32_t)plimit); 1724 } 1725 1726 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1727 printf(" Capability list pointer: 0x%02x\n", 1728 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 1729 else 1730 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 1731 1732 /* XXX */ 1733 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 1734 1735 rval = regs[o2i(PCI_INTERRUPT_REG)]; 1736 printf(" Interrupt line: 0x%02x\n", 1737 (rval >> 0) & 0xff); 1738 printf(" Interrupt pin: 0x%02x ", 1739 (rval >> 8) & 0xff); 1740 switch ((rval >> 8) & 0xff) { 1741 case PCI_INTERRUPT_PIN_NONE: 1742 printf("(none)"); 1743 break; 1744 case PCI_INTERRUPT_PIN_A: 1745 printf("(pin A)"); 1746 break; 1747 case PCI_INTERRUPT_PIN_B: 1748 printf("(pin B)"); 1749 break; 1750 case PCI_INTERRUPT_PIN_C: 1751 printf("(pin C)"); 1752 break; 1753 case PCI_INTERRUPT_PIN_D: 1754 printf("(pin D)"); 1755 break; 1756 default: 1757 printf("(? ? ?)"); 1758 break; 1759 } 1760 printf("\n"); 1761 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 1762 & PCI_BRIDGE_CONTROL_MASK; 1763 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 1764 onoff("Parity error response", rval, 0x0001); 1765 onoff("Secondary SERR forwarding", rval, 0x0002); 1766 onoff("ISA enable", rval, 0x0004); 1767 onoff("VGA enable", rval, 0x0008); 1768 onoff("Master abort reporting", rval, 0x0020); 1769 onoff("Secondary bus reset", rval, 0x0040); 1770 onoff("Fast back-to-back capable", rval, 0x0080); 1771 } 1772 1773 static void 1774 pci_conf_print_type2( 1775 #ifdef _KERNEL 1776 pci_chipset_tag_t pc, pcitag_t tag, 1777 #endif 1778 const pcireg_t *regs 1779 #ifdef _KERNEL 1780 , int sizebars 1781 #endif 1782 ) 1783 { 1784 pcireg_t rval; 1785 1786 /* 1787 * XXX these need to be printed in more detail, need to be 1788 * XXX checked against specs/docs, etc. 1789 * 1790 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 1791 * controller chip documentation, and may not be correct with 1792 * respect to various standards. (XXX) 1793 */ 1794 1795 #ifdef _KERNEL 1796 pci_conf_print_bar(pc, tag, regs, 0x10, 1797 "CardBus socket/ExCA registers", sizebars); 1798 #else 1799 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 1800 #endif 1801 1802 /* Capability list pointer and secondary status register */ 1803 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 1804 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1805 printf(" Capability list pointer: 0x%02x\n", 1806 PCI_CAPLIST_PTR(rval)); 1807 else 1808 printf(" Reserved @ 0x14: 0x%04" PRIxMAX "\n", 1809 __SHIFTOUT(rval, __BITS(15, 0))); 1810 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 1811 1812 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 1813 printf(" PCI bus number: 0x%02x\n", 1814 (rval >> 0) & 0xff); 1815 printf(" CardBus bus number: 0x%02x\n", 1816 (rval >> 8) & 0xff); 1817 printf(" Subordinate bus number: 0x%02x\n", 1818 (rval >> 16) & 0xff); 1819 printf(" CardBus latency timer: 0x%02x\n", 1820 (rval >> 24) & 0xff); 1821 1822 /* XXX Print more prettily */ 1823 printf(" CardBus memory region 0:\n"); 1824 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 1825 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 1826 printf(" CardBus memory region 1:\n"); 1827 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 1828 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 1829 printf(" CardBus I/O region 0:\n"); 1830 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 1831 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 1832 printf(" CardBus I/O region 1:\n"); 1833 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 1834 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 1835 1836 rval = regs[o2i(PCI_INTERRUPT_REG)]; 1837 printf(" Interrupt line: 0x%02x\n", 1838 (rval >> 0) & 0xff); 1839 printf(" Interrupt pin: 0x%02x ", 1840 (rval >> 8) & 0xff); 1841 switch ((rval >> 8) & 0xff) { 1842 case PCI_INTERRUPT_PIN_NONE: 1843 printf("(none)"); 1844 break; 1845 case PCI_INTERRUPT_PIN_A: 1846 printf("(pin A)"); 1847 break; 1848 case PCI_INTERRUPT_PIN_B: 1849 printf("(pin B)"); 1850 break; 1851 case PCI_INTERRUPT_PIN_C: 1852 printf("(pin C)"); 1853 break; 1854 case PCI_INTERRUPT_PIN_D: 1855 printf("(pin D)"); 1856 break; 1857 default: 1858 printf("(? ? ?)"); 1859 break; 1860 } 1861 printf("\n"); 1862 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1863 printf(" Bridge control register: 0x%04x\n", rval); 1864 onoff("Parity error response", rval, __BIT(0)); 1865 onoff("SERR# enable", rval, __BIT(1)); 1866 onoff("ISA enable", rval, __BIT(2)); 1867 onoff("VGA enable", rval, __BIT(3)); 1868 onoff("Master abort mode", rval, __BIT(5)); 1869 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 1870 onoff("Functional interrupts routed by ExCA registers", rval, __BIT(7)); 1871 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 1872 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 1873 onoff("Write posting enable", rval, __BIT(10)); 1874 1875 rval = regs[o2i(0x40)]; 1876 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1877 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1878 1879 #ifdef _KERNEL 1880 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1881 sizebars); 1882 #else 1883 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 1884 #endif 1885 } 1886 1887 void 1888 pci_conf_print( 1889 #ifdef _KERNEL 1890 pci_chipset_tag_t pc, pcitag_t tag, 1891 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 1892 #else 1893 int pcifd, u_int bus, u_int dev, u_int func 1894 #endif 1895 ) 1896 { 1897 pcireg_t regs[o2i(256)]; 1898 int off, capoff, endoff, hdrtype; 1899 const char *typename; 1900 #ifdef _KERNEL 1901 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1902 int sizebars; 1903 #else 1904 void (*typeprintfn)(const pcireg_t *); 1905 #endif 1906 1907 printf("PCI configuration registers:\n"); 1908 1909 for (off = 0; off < 256; off += 4) { 1910 #ifdef _KERNEL 1911 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1912 #else 1913 if (pcibus_conf_read(pcifd, bus, dev, func, off, 1914 ®s[o2i(off)]) == -1) 1915 regs[o2i(off)] = 0; 1916 #endif 1917 } 1918 1919 #ifdef _KERNEL 1920 sizebars = 1; 1921 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1922 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1923 sizebars = 0; 1924 #endif 1925 1926 /* common header */ 1927 printf(" Common header:\n"); 1928 pci_conf_print_regs(regs, 0, 16); 1929 1930 printf("\n"); 1931 #ifdef _KERNEL 1932 pci_conf_print_common(pc, tag, regs); 1933 #else 1934 pci_conf_print_common(regs); 1935 #endif 1936 printf("\n"); 1937 1938 /* type-dependent header */ 1939 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1940 switch (hdrtype) { /* XXX make a table, eventually */ 1941 case 0: 1942 /* Standard device header */ 1943 typename = "\"normal\" device"; 1944 typeprintfn = &pci_conf_print_type0; 1945 capoff = PCI_CAPLISTPTR_REG; 1946 endoff = 64; 1947 break; 1948 case 1: 1949 /* PCI-PCI bridge header */ 1950 typename = "PCI-PCI bridge"; 1951 typeprintfn = &pci_conf_print_type1; 1952 capoff = PCI_CAPLISTPTR_REG; 1953 endoff = 64; 1954 break; 1955 case 2: 1956 /* PCI-CardBus bridge header */ 1957 typename = "PCI-CardBus bridge"; 1958 typeprintfn = &pci_conf_print_type2; 1959 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 1960 endoff = 72; 1961 break; 1962 default: 1963 typename = NULL; 1964 typeprintfn = 0; 1965 capoff = -1; 1966 endoff = 64; 1967 break; 1968 } 1969 printf(" Type %d ", hdrtype); 1970 if (typename != NULL) 1971 printf("(%s) ", typename); 1972 printf("header:\n"); 1973 pci_conf_print_regs(regs, 16, endoff); 1974 printf("\n"); 1975 if (typeprintfn) { 1976 #ifdef _KERNEL 1977 (*typeprintfn)(pc, tag, regs, sizebars); 1978 #else 1979 (*typeprintfn)(regs); 1980 #endif 1981 } else 1982 printf(" Don't know how to pretty-print type %d header.\n", 1983 hdrtype); 1984 printf("\n"); 1985 1986 /* capability list, if present */ 1987 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1988 && (capoff > 0)) { 1989 #ifdef _KERNEL 1990 pci_conf_print_caplist(pc, tag, regs, capoff); 1991 #else 1992 pci_conf_print_caplist(regs, capoff); 1993 #endif 1994 printf("\n"); 1995 } 1996 1997 /* device-dependent header */ 1998 printf(" Device-dependent header:\n"); 1999 pci_conf_print_regs(regs, endoff, 256); 2000 printf("\n"); 2001 #ifdef _KERNEL 2002 if (printfn) 2003 (*printfn)(pc, tag, regs); 2004 else 2005 printf(" Don't know how to pretty-print device-dependent header.\n"); 2006 printf("\n"); 2007 #endif /* _KERNEL */ 2008 } 2009
Indexes created Tue Sep 23 21:09:50 GMT 2025