pci_subr.c revision 1.122
1 /* $NetBSD: pci_subr.c,v 1.122 2014/05/30 03:42:38 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.122 2014/05/30 03:42:38 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdbool.h> 58 #include <stdio.h> 59 #include <string.h> 60 #endif 61 62 #include <dev/pci/pcireg.h> 63 #ifdef _KERNEL 64 #include <dev/pci/pcivar.h> 65 #endif 66 67 /* 68 * Descriptions of known PCI classes and subclasses. 69 * 70 * Subclasses are described in the same way as classes, but have a 71 * NULL subclass pointer. 72 */ 73 struct pci_class { 74 const char *name; 75 u_int val; /* as wide as pci_{,sub}class_t */ 76 const struct pci_class *subclasses; 77 }; 78 79 /* 80 * Class 0x00. 81 * Before rev. 2.0. 82 */ 83 static const struct pci_class pci_subclass_prehistoric[] = { 84 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 85 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 86 { NULL, 0, NULL, }, 87 }; 88 89 /* 90 * Class 0x01. 91 * Mass strage controller 92 */ 93 94 /* ATA programming interface */ 95 static const struct pci_class pci_interface_ata[] = { 96 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 97 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 98 { NULL, 0, NULL, }, 99 }; 100 101 /* SATA programming interface */ 102 static const struct pci_class pci_interface_sata[] = { 103 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 104 { NULL, 0, NULL, }, 105 }; 106 107 /* Subclasses */ 108 static const struct pci_class pci_subclass_mass_storage[] = { 109 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 110 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 111 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 112 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 113 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 114 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 115 pci_interface_ata, }, 116 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 117 pci_interface_sata, }, 118 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 119 { "NVM", PCI_SUBCLASS_MASS_STORAGE_NVM, NULL, }, 120 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 121 { NULL, 0, NULL, }, 122 }; 123 124 /* 125 * Class 0x02. 126 * Network controller. 127 */ 128 static const struct pci_class pci_subclass_network[] = { 129 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 130 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 131 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 132 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 133 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 134 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 135 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 136 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 137 { NULL, 0, NULL, }, 138 }; 139 140 /* 141 * Class 0x03. 142 * Display controller. 143 */ 144 145 /* VGA programming interface */ 146 static const struct pci_class pci_interface_vga[] = { 147 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 148 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 149 { NULL, 0, NULL, }, 150 }; 151 /* Subclasses */ 152 static const struct pci_class pci_subclass_display[] = { 153 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 154 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 155 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 156 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 157 { NULL, 0, NULL, }, 158 }; 159 160 /* 161 * Class 0x04. 162 * Multimedia device. 163 */ 164 static const struct pci_class pci_subclass_multimedia[] = { 165 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 166 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 167 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 168 { "HD audio", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 169 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 170 { NULL, 0, NULL, }, 171 }; 172 173 /* 174 * Class 0x05. 175 * Memory controller. 176 */ 177 static const struct pci_class pci_subclass_memory[] = { 178 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 179 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 180 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 181 { NULL, 0, NULL, }, 182 }; 183 184 /* 185 * Class 0x06. 186 * Bridge device. 187 */ 188 189 /* PCI bridge programming interface */ 190 static const struct pci_class pci_interface_pcibridge[] = { 191 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 192 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 193 { NULL, 0, NULL, }, 194 }; 195 196 /* Semi-transparent PCI-toPCI bridge programming interface */ 197 static const struct pci_class pci_interface_stpci[] = { 198 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 199 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 200 { NULL, 0, NULL, }, 201 }; 202 203 /* Subclasses */ 204 static const struct pci_class pci_subclass_bridge[] = { 205 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 206 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 207 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 208 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 209 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 210 pci_interface_pcibridge, }, 211 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 212 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 213 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 214 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 215 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 216 pci_interface_stpci, }, 217 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 218 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 219 { NULL, 0, NULL, }, 220 }; 221 222 /* 223 * Class 0x07. 224 * Simple communications controller. 225 */ 226 227 /* Serial controller programming interface */ 228 static const struct pci_class pci_interface_serial[] = { 229 { "genric XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 230 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 231 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 232 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 233 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 234 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 235 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 236 { NULL, 0, NULL, }, 237 }; 238 239 /* Parallel controller programming interface */ 240 static const struct pci_class pci_interface_parallel[] = { 241 { "", PCI_INTERFACE_PARALLEL, NULL,}, 242 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 243 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 244 { "IEEE1284", PCI_INTERFACE_PARALLEL_IEEE1284, NULL,}, 245 { "IEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 246 { NULL, 0, NULL,}, 247 }; 248 249 /* Modem programming interface */ 250 static const struct pci_class pci_interface_modem[] = { 251 { "", PCI_INTERFACE_MODEM, NULL,}, 252 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 253 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 254 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 255 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 256 { NULL, 0, NULL,}, 257 }; 258 259 /* Subclasses */ 260 static const struct pci_class pci_subclass_communications[] = { 261 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 262 pci_interface_serial, }, 263 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 264 pci_interface_parallel, }, 265 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 266 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 267 pci_interface_modem, }, 268 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 269 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 270 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 271 { NULL, 0, NULL,}, 272 }; 273 274 /* 275 * Class 0x08. 276 * Base system peripheral. 277 */ 278 279 /* PIC programming interface */ 280 static const struct pci_class pci_interface_pic[] = { 281 { "genric 8259", PCI_INTERFACE_PIC_8259, NULL, }, 282 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 283 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 284 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 285 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 286 { NULL, 0, NULL, }, 287 }; 288 289 /* DMA programming interface */ 290 static const struct pci_class pci_interface_dma[] = { 291 { "genric 8237", PCI_INTERFACE_DMA_8237, NULL, }, 292 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 293 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 294 { NULL, 0, NULL, }, 295 }; 296 297 /* Timer programming interface */ 298 static const struct pci_class pci_interface_tmr[] = { 299 { "genric 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 300 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 301 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 302 { NULL, 0, NULL, }, 303 }; 304 305 /* RTC programming interface */ 306 static const struct pci_class pci_interface_rtc[] = { 307 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 308 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 309 { NULL, 0, NULL, }, 310 }; 311 312 /* Subclasses */ 313 static const struct pci_class pci_subclass_system[] = { 314 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 315 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 316 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 317 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 318 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 319 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 320 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 321 { NULL, 0, NULL, }, 322 }; 323 324 /* 325 * Class 0x09. 326 * Input device. 327 */ 328 329 /* Gameport programming interface */ 330 static const struct pci_class pci_interface_game[] = { 331 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 332 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 333 { NULL, 0, NULL, }, 334 }; 335 336 /* Subclasses */ 337 static const struct pci_class pci_subclass_input[] = { 338 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 339 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 340 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 341 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 342 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 343 pci_interface_game, }, 344 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 345 { NULL, 0, NULL, }, 346 }; 347 348 /* 349 * Class 0x0a. 350 * Docking station. 351 */ 352 static const struct pci_class pci_subclass_dock[] = { 353 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 354 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 355 { NULL, 0, NULL, }, 356 }; 357 358 /* 359 * Class 0x0b. 360 * Processor. 361 */ 362 static const struct pci_class pci_subclass_processor[] = { 363 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 364 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 365 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 366 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 367 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 368 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 369 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 370 { NULL, 0, NULL, }, 371 }; 372 373 /* 374 * Class 0x0c. 375 * Serial bus controller. 376 */ 377 378 /* IEEE1394 programming interface */ 379 static const struct pci_class pci_interface_ieee1394[] = { 380 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 381 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 382 { NULL, 0, NULL,}, 383 }; 384 385 /* USB programming interface */ 386 static const struct pci_class pci_interface_usb[] = { 387 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 388 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 389 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 390 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 391 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 392 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 393 { NULL, 0, NULL, }, 394 }; 395 396 /* IPMI programming interface */ 397 static const struct pci_class pci_interface_ipmi[] = { 398 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 399 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 400 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 401 { NULL, 0, NULL,}, 402 }; 403 404 /* Subclasses */ 405 static const struct pci_class pci_subclass_serialbus[] = { 406 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 407 pci_interface_ieee1394, }, 408 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 409 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 410 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 411 pci_interface_usb, }, 412 /* XXX Fiber Channel/_FIBRECHANNEL */ 413 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 414 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 415 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 416 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 417 pci_interface_ipmi, }, 418 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 419 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 420 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 421 { NULL, 0, NULL, }, 422 }; 423 424 /* 425 * Class 0x0d. 426 * Wireless Controller. 427 */ 428 static const struct pci_class pci_subclass_wireless[] = { 429 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 430 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 431 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 432 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 433 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 434 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 435 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 436 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 437 { NULL, 0, NULL, }, 438 }; 439 440 /* 441 * Class 0x0e. 442 * Intelligent IO controller. 443 */ 444 445 /* Intelligent IO programming interface */ 446 static const struct pci_class pci_interface_i2o[] = { 447 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 448 { NULL, 0, NULL,}, 449 }; 450 451 /* Subclasses */ 452 static const struct pci_class pci_subclass_i2o[] = { 453 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 454 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 455 { NULL, 0, NULL, }, 456 }; 457 458 /* 459 * Class 0x0f. 460 * Satellite communication controller. 461 */ 462 static const struct pci_class pci_subclass_satcom[] = { 463 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 464 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 465 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 466 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 467 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 468 { NULL, 0, NULL, }, 469 }; 470 471 /* 472 * Class 0x10. 473 * Encryption/Decryption controller. 474 */ 475 static const struct pci_class pci_subclass_crypto[] = { 476 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 477 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 478 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 479 { NULL, 0, NULL, }, 480 }; 481 482 /* 483 * Class 0x11. 484 * Data aquuisition and signal processing controller. 485 */ 486 static const struct pci_class pci_subclass_dasp[] = { 487 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 488 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 489 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 490 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 491 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 492 { NULL, 0, NULL, }, 493 }; 494 495 /* List of classes */ 496 static const struct pci_class pci_class[] = { 497 { "prehistoric", PCI_CLASS_PREHISTORIC, 498 pci_subclass_prehistoric, }, 499 { "mass storage", PCI_CLASS_MASS_STORAGE, 500 pci_subclass_mass_storage, }, 501 { "network", PCI_CLASS_NETWORK, 502 pci_subclass_network, }, 503 { "display", PCI_CLASS_DISPLAY, 504 pci_subclass_display, }, 505 { "multimedia", PCI_CLASS_MULTIMEDIA, 506 pci_subclass_multimedia, }, 507 { "memory", PCI_CLASS_MEMORY, 508 pci_subclass_memory, }, 509 { "bridge", PCI_CLASS_BRIDGE, 510 pci_subclass_bridge, }, 511 { "communications", PCI_CLASS_COMMUNICATIONS, 512 pci_subclass_communications, }, 513 { "system", PCI_CLASS_SYSTEM, 514 pci_subclass_system, }, 515 { "input", PCI_CLASS_INPUT, 516 pci_subclass_input, }, 517 { "dock", PCI_CLASS_DOCK, 518 pci_subclass_dock, }, 519 { "processor", PCI_CLASS_PROCESSOR, 520 pci_subclass_processor, }, 521 { "serial bus", PCI_CLASS_SERIALBUS, 522 pci_subclass_serialbus, }, 523 { "wireless", PCI_CLASS_WIRELESS, 524 pci_subclass_wireless, }, 525 { "I2O", PCI_CLASS_I2O, 526 pci_subclass_i2o, }, 527 { "satellite comm", PCI_CLASS_SATCOM, 528 pci_subclass_satcom, }, 529 { "crypto", PCI_CLASS_CRYPTO, 530 pci_subclass_crypto, }, 531 { "DASP", PCI_CLASS_DASP, 532 pci_subclass_dasp, }, 533 { "undefined", PCI_CLASS_UNDEFINED, 534 NULL, }, 535 { NULL, 0, 536 NULL, }, 537 }; 538 539 void pci_load_verbose(void); 540 541 #if defined(_KERNEL) 542 /* 543 * In kernel, these routines are provided and linked via the 544 * pciverbose module. 545 */ 546 const char *pci_findvendor_stub(pcireg_t); 547 const char *pci_findproduct_stub(pcireg_t); 548 549 const char *(*pci_findvendor)(pcireg_t) = pci_findvendor_stub; 550 const char *(*pci_findproduct)(pcireg_t) = pci_findproduct_stub; 551 const char *pci_unmatched = ""; 552 #else 553 /* 554 * For userland we just set the vectors here. 555 */ 556 const char *(*pci_findvendor)(pcireg_t id_reg) = pci_findvendor_real; 557 const char *(*pci_findproduct)(pcireg_t id_reg) = pci_findproduct_real; 558 const char *pci_unmatched = "unmatched "; 559 #endif 560 561 int pciverbose_loaded = 0; 562 563 #if defined(_KERNEL) 564 /* 565 * Routine to load the pciverbose kernel module as needed 566 */ 567 void 568 pci_load_verbose(void) 569 { 570 571 if (pciverbose_loaded == 0) 572 module_autoload("pciverbose", MODULE_CLASS_MISC); 573 } 574 575 const char * 576 pci_findvendor_stub(pcireg_t id_reg) 577 { 578 579 pci_load_verbose(); 580 if (pciverbose_loaded) 581 return pci_findvendor(id_reg); 582 else 583 return NULL; 584 } 585 586 const char * 587 pci_findproduct_stub(pcireg_t id_reg) 588 { 589 590 pci_load_verbose(); 591 if (pciverbose_loaded) 592 return pci_findproduct(id_reg); 593 else 594 return NULL; 595 } 596 #endif 597 598 void 599 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 600 size_t l) 601 { 602 pci_vendor_id_t vendor; 603 pci_product_id_t product; 604 pci_class_t class; 605 pci_subclass_t subclass; 606 pci_interface_t interface; 607 pci_revision_t revision; 608 const char *unmatched = pci_unmatched; 609 const char *vendor_namep, *product_namep; 610 const struct pci_class *classp, *subclassp, *interfacep; 611 char *ep; 612 613 ep = cp + l; 614 615 vendor = PCI_VENDOR(id_reg); 616 product = PCI_PRODUCT(id_reg); 617 618 class = PCI_CLASS(class_reg); 619 subclass = PCI_SUBCLASS(class_reg); 620 interface = PCI_INTERFACE(class_reg); 621 revision = PCI_REVISION(class_reg); 622 623 vendor_namep = pci_findvendor(id_reg); 624 product_namep = pci_findproduct(id_reg); 625 626 classp = pci_class; 627 while (classp->name != NULL) { 628 if (class == classp->val) 629 break; 630 classp++; 631 } 632 633 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 634 while (subclassp && subclassp->name != NULL) { 635 if (subclass == subclassp->val) 636 break; 637 subclassp++; 638 } 639 640 interfacep = (subclassp && subclassp->name != NULL) ? 641 subclassp->subclasses : NULL; 642 while (interfacep && interfacep->name != NULL) { 643 if (interface == interfacep->val) 644 break; 645 interfacep++; 646 } 647 648 if (vendor_namep == NULL) 649 cp += snprintf(cp, ep - cp, "%svendor 0x%04x product 0x%04x", 650 unmatched, vendor, product); 651 else if (product_namep != NULL) 652 cp += snprintf(cp, ep - cp, "%s %s", vendor_namep, 653 product_namep); 654 else 655 cp += snprintf(cp, ep - cp, "%s product 0x%04x", 656 vendor_namep, product); 657 if (showclass) { 658 cp += snprintf(cp, ep - cp, " ("); 659 if (classp->name == NULL) 660 cp += snprintf(cp, ep - cp, 661 "class 0x%02x, subclass 0x%02x", class, subclass); 662 else { 663 if (subclassp == NULL || subclassp->name == NULL) 664 cp += snprintf(cp, ep - cp, 665 "%s, subclass 0x%02x", 666 classp->name, subclass); 667 else 668 cp += snprintf(cp, ep - cp, "%s %s", 669 subclassp->name, classp->name); 670 } 671 if ((interfacep == NULL) || (interfacep->name == NULL)) { 672 if (interface != 0) 673 cp += snprintf(cp, ep - cp, 674 ", interface 0x%02x", interface); 675 } else if (strncmp(interfacep->name, "", 1) != 0) 676 cp += snprintf(cp, ep - cp, ", %s", 677 interfacep->name); 678 if (revision != 0) 679 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 680 revision); 681 cp += snprintf(cp, ep - cp, ")"); 682 } 683 } 684 685 #ifdef _KERNEL 686 void 687 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 688 const char *known, int addrev) 689 { 690 char devinfo[256]; 691 692 if (known) { 693 aprint_normal(": %s", known); 694 if (addrev) 695 aprint_normal(" (rev. 0x%02x)", 696 PCI_REVISION(pa->pa_class)); 697 aprint_normal("\n"); 698 } else { 699 pci_devinfo(pa->pa_id, pa->pa_class, 0, 700 devinfo, sizeof(devinfo)); 701 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 702 PCI_REVISION(pa->pa_class)); 703 } 704 if (naive) 705 aprint_naive(": %s\n", naive); 706 else 707 aprint_naive("\n"); 708 } 709 #endif 710 711 /* 712 * Print out most of the PCI configuration registers. Typically used 713 * in a device attach routine like this: 714 * 715 * #ifdef MYDEV_DEBUG 716 * printf("%s: ", device_xname(sc->sc_dev)); 717 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 718 * #endif 719 */ 720 721 #define i2o(i) ((i) * 4) 722 #define o2i(o) ((o) / 4) 723 #define onoff2(str, rval, bit, onstr, offstr) \ 724 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 725 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 726 727 static void 728 pci_conf_print_common( 729 #ifdef _KERNEL 730 pci_chipset_tag_t pc, pcitag_t tag, 731 #endif 732 const pcireg_t *regs) 733 { 734 const char *name; 735 const struct pci_class *classp, *subclassp; 736 pcireg_t rval; 737 unsigned int num; 738 739 rval = regs[o2i(PCI_ID_REG)]; 740 name = pci_findvendor(rval); 741 if (name) 742 printf(" Vendor Name: %s (0x%04x)\n", name, 743 PCI_VENDOR(rval)); 744 else 745 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 746 name = pci_findproduct(rval); 747 if (name) 748 printf(" Device Name: %s (0x%04x)\n", name, 749 PCI_PRODUCT(rval)); 750 else 751 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 752 753 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 754 755 printf(" Command register: 0x%04x\n", rval & 0xffff); 756 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 757 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 758 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 759 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 760 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 761 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 762 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 763 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 764 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 765 onoff("Fast back-to-back transactions", rval, 766 PCI_COMMAND_BACKTOBACK_ENABLE); 767 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 768 769 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 770 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 771 "inactive"); 772 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 773 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 774 onoff("User Definable Features (UDF) support", rval, 775 PCI_STATUS_UDF_SUPPORT); 776 onoff("Fast back-to-back capable", rval, 777 PCI_STATUS_BACKTOBACK_SUPPORT); 778 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 779 780 printf(" DEVSEL timing: "); 781 switch (rval & PCI_STATUS_DEVSEL_MASK) { 782 case PCI_STATUS_DEVSEL_FAST: 783 printf("fast"); 784 break; 785 case PCI_STATUS_DEVSEL_MEDIUM: 786 printf("medium"); 787 break; 788 case PCI_STATUS_DEVSEL_SLOW: 789 printf("slow"); 790 break; 791 default: 792 printf("unknown/reserved"); /* XXX */ 793 break; 794 } 795 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 796 797 onoff("Slave signaled Target Abort", rval, 798 PCI_STATUS_TARGET_TARGET_ABORT); 799 onoff("Master received Target Abort", rval, 800 PCI_STATUS_MASTER_TARGET_ABORT); 801 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 802 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 803 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 804 805 rval = regs[o2i(PCI_CLASS_REG)]; 806 for (classp = pci_class; classp->name != NULL; classp++) { 807 if (PCI_CLASS(rval) == classp->val) 808 break; 809 } 810 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 811 while (subclassp && subclassp->name != NULL) { 812 if (PCI_SUBCLASS(rval) == subclassp->val) 813 break; 814 subclassp++; 815 } 816 if (classp->name != NULL) { 817 printf(" Class Name: %s (0x%02x)\n", classp->name, 818 PCI_CLASS(rval)); 819 if (subclassp != NULL && subclassp->name != NULL) 820 printf(" Subclass Name: %s (0x%02x)\n", 821 subclassp->name, PCI_SUBCLASS(rval)); 822 else 823 printf(" Subclass ID: 0x%02x\n", 824 PCI_SUBCLASS(rval)); 825 } else { 826 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 827 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 828 } 829 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 830 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 831 832 rval = regs[o2i(PCI_BHLC_REG)]; 833 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 834 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 835 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 836 PCI_HDRTYPE(rval)); 837 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 838 num = PCI_CACHELINE(rval); 839 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 840 } 841 842 static int 843 pci_conf_print_bar( 844 #ifdef _KERNEL 845 pci_chipset_tag_t pc, pcitag_t tag, 846 #endif 847 const pcireg_t *regs, int reg, const char *name 848 #ifdef _KERNEL 849 , int sizebar 850 #endif 851 ) 852 { 853 int width; 854 pcireg_t rval, rval64h; 855 #ifdef _KERNEL 856 int s; 857 pcireg_t mask, mask64h; 858 #endif 859 860 width = 4; 861 862 /* 863 * Section 6.2.5.1, `Address Maps', tells us that: 864 * 865 * 1) The builtin software should have already mapped the 866 * device in a reasonable way. 867 * 868 * 2) A device which wants 2^n bytes of memory will hardwire 869 * the bottom n bits of the address to 0. As recommended, 870 * we write all 1s and see what we get back. 871 */ 872 873 rval = regs[o2i(reg)]; 874 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 875 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 876 rval64h = regs[o2i(reg + 4)]; 877 width = 8; 878 } else 879 rval64h = 0; 880 881 #ifdef _KERNEL 882 /* XXX don't size unknown memory type? */ 883 if (rval != 0 && sizebar) { 884 /* 885 * The following sequence seems to make some devices 886 * (e.g. host bus bridges, which don't normally 887 * have their space mapped) very unhappy, to 888 * the point of crashing the system. 889 * 890 * Therefore, if the mapping register is zero to 891 * start out with, don't bother trying. 892 */ 893 s = splhigh(); 894 pci_conf_write(pc, tag, reg, 0xffffffff); 895 mask = pci_conf_read(pc, tag, reg); 896 pci_conf_write(pc, tag, reg, rval); 897 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 898 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 899 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 900 mask64h = pci_conf_read(pc, tag, reg + 4); 901 pci_conf_write(pc, tag, reg + 4, rval64h); 902 } else 903 mask64h = 0; 904 splx(s); 905 } else 906 mask = mask64h = 0; 907 #endif /* _KERNEL */ 908 909 printf(" Base address register at 0x%02x", reg); 910 if (name) 911 printf(" (%s)", name); 912 printf("\n "); 913 if (rval == 0) { 914 printf("not implemented(?)\n"); 915 return width; 916 } 917 printf("type: "); 918 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 919 const char *type, *prefetch; 920 921 switch (PCI_MAPREG_MEM_TYPE(rval)) { 922 case PCI_MAPREG_MEM_TYPE_32BIT: 923 type = "32-bit"; 924 break; 925 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 926 type = "32-bit-1M"; 927 break; 928 case PCI_MAPREG_MEM_TYPE_64BIT: 929 type = "64-bit"; 930 break; 931 default: 932 type = "unknown (XXX)"; 933 break; 934 } 935 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 936 prefetch = ""; 937 else 938 prefetch = "non"; 939 printf("%s %sprefetchable memory\n", type, prefetch); 940 switch (PCI_MAPREG_MEM_TYPE(rval)) { 941 case PCI_MAPREG_MEM_TYPE_64BIT: 942 printf(" base: 0x%016llx, ", 943 PCI_MAPREG_MEM64_ADDR( 944 ((((long long) rval64h) << 32) | rval))); 945 #ifdef _KERNEL 946 if (sizebar) 947 printf("size: 0x%016llx", 948 PCI_MAPREG_MEM64_SIZE( 949 ((((long long) mask64h) << 32) | mask))); 950 else 951 #endif /* _KERNEL */ 952 printf("not sized"); 953 printf("\n"); 954 break; 955 case PCI_MAPREG_MEM_TYPE_32BIT: 956 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 957 default: 958 printf(" base: 0x%08x, ", 959 PCI_MAPREG_MEM_ADDR(rval)); 960 #ifdef _KERNEL 961 if (sizebar) 962 printf("size: 0x%08x", 963 PCI_MAPREG_MEM_SIZE(mask)); 964 else 965 #endif /* _KERNEL */ 966 printf("not sized"); 967 printf("\n"); 968 break; 969 } 970 } else { 971 #ifdef _KERNEL 972 if (sizebar) 973 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 974 #endif /* _KERNEL */ 975 printf("i/o\n"); 976 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 977 #ifdef _KERNEL 978 if (sizebar) 979 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 980 else 981 #endif /* _KERNEL */ 982 printf("not sized"); 983 printf("\n"); 984 } 985 986 return width; 987 } 988 989 static void 990 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 991 { 992 int off, needaddr, neednl; 993 994 needaddr = 1; 995 neednl = 0; 996 for (off = first; off < pastlast; off += 4) { 997 if ((off % 16) == 0 || needaddr) { 998 printf(" 0x%02x:", off); 999 needaddr = 0; 1000 } 1001 printf(" 0x%08x", regs[o2i(off)]); 1002 neednl = 1; 1003 if ((off % 16) == 12) { 1004 printf("\n"); 1005 neednl = 0; 1006 } 1007 } 1008 if (neednl) 1009 printf("\n"); 1010 } 1011 1012 static const char * 1013 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1014 { 1015 1016 switch ((caps >> 6) & 7) { 1017 case 0: return "self-powered"; 1018 case 1: return "55 mA"; 1019 case 2: return "100 mA"; 1020 case 3: return "160 mA"; 1021 case 4: return "220 mA"; 1022 case 5: return "270 mA"; 1023 case 6: return "320 mA"; 1024 case 7: 1025 default: return "375 mA"; 1026 } 1027 } 1028 1029 static const char * 1030 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1031 { 1032 static const char unk[] = "unknown"; 1033 static const char *pmrev[8] = { 1034 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1035 }; 1036 if (val > 7) 1037 return unk; 1038 return pmrev[val]; 1039 } 1040 1041 static void 1042 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1043 { 1044 uint16_t caps, pmcsr; 1045 pcireg_t reg; 1046 1047 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1048 reg = regs[o2i(capoff + PCI_PMCSR)]; 1049 pmcsr = reg & 0xffff; 1050 1051 printf("\n PCI Power Management Capabilities Register\n"); 1052 1053 printf(" Capabilities register: 0x%04x\n", caps); 1054 printf(" Version: %s\n", 1055 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1056 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1057 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1058 printf(" 3.3V auxiliary current: %s\n", 1059 pci_conf_print_pcipm_cap_aux(caps)); 1060 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1061 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1062 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1063 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1064 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1065 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1066 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1067 1068 printf(" Control/status register: 0x%04x\n", pmcsr); 1069 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1070 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1071 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1072 printf(" PME# assertion: %sabled\n", 1073 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1074 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1075 printf(" Bridge Support Extensions register: 0x%02x\n", 1076 (reg >> 16) & 0xff); 1077 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1078 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1079 printf(" Data register: 0x%02x\n", (reg >> 24) & 0xff); 1080 1081 } 1082 1083 /* XXX pci_conf_print_vpd_cap */ 1084 /* XXX pci_conf_print_slotid_cap */ 1085 1086 static void 1087 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1088 { 1089 uint32_t ctl, mmc, mme; 1090 1091 regs += o2i(capoff); 1092 ctl = *regs++; 1093 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1094 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1095 1096 printf("\n PCI Message Signaled Interrupt\n"); 1097 1098 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1099 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1100 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1101 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1102 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1103 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1104 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1105 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1106 printf(" Message Address %sregister: 0x%08x\n", 1107 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1108 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1109 printf(" Message Address %sregister: 0x%08x\n", 1110 "(upper) ", *regs++); 1111 } 1112 printf(" Message Data register: 0x%08x\n", *regs++); 1113 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1114 printf(" Vector Mask register: 0x%08x\n", *regs++); 1115 printf(" Vector Pending register: 0x%08x\n", *regs++); 1116 } 1117 } 1118 1119 /* XXX pci_conf_print_cpci_hostwap_cap */ 1120 1121 /* 1122 * For both command register and status register. 1123 * The argument "idx" is index number (0 to 7). 1124 */ 1125 static int 1126 pcix_split_trans(unsigned int idx) 1127 { 1128 static int table[8] = { 1129 1, 2, 3, 4, 8, 12, 16, 32 1130 }; 1131 1132 if (idx >= __arraycount(table)) 1133 return -1; 1134 return table[idx]; 1135 } 1136 1137 static void 1138 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1139 { 1140 pcireg_t reg; 1141 int isbridge; 1142 int i; 1143 1144 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1145 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1146 printf("\n PCI-X %s Capabilities Register\n", 1147 isbridge ? "Bridge" : "Non-bridge"); 1148 1149 reg = regs[o2i(capoff)]; 1150 if (isbridge != 0) { 1151 printf(" Secondary status register: 0x%04x\n", 1152 (reg & 0xffff0000) >> 16); 1153 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1154 onoff("133MHz capable", reg, PCIX_STATUS_133); 1155 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1156 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1157 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1158 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1159 printf(" Secondary clock frequency: 0x%x\n", 1160 (reg & PCIX_BRIDGE_2NDST_CLKF) 1161 >> PCIX_BRIDGE_2NDST_CLKF_SHIFT); 1162 printf(" Version: 0x%x\n", 1163 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1164 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1165 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1166 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1167 } else { 1168 printf(" Command register: 0x%04x\n", 1169 (reg & 0xffff0000) >> 16); 1170 onoff("Data Parity Error Recovery", reg, 1171 PCIX_CMD_PERR_RECOVER); 1172 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1173 printf(" Maximum Burst Read Count: %u\n", 1174 PCIX_CMD_BYTECNT(reg)); 1175 printf(" Maximum Split Transactions: %d\n", 1176 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1177 >> PCIX_CMD_SPLTRANS_SHIFT)); 1178 } 1179 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1180 printf(" %sStatus register: 0x%08x\n", 1181 isbridge ? "Bridge " : "", reg); 1182 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1183 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1184 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1185 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1186 onoff("133MHz capable", reg, PCIX_STATUS_133); 1187 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1188 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1189 if (isbridge != 0) { 1190 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1191 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1192 } else { 1193 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1194 "bridge device", "simple device"); 1195 printf(" Designed max memory read byte count: %d\n", 1196 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1197 >> PCIX_STATUS_MAXB_SHIFT)); 1198 printf(" Designed max outstanding split transaction: %d\n", 1199 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1200 >> PCIX_STATUS_MAXST_SHIFT)); 1201 printf(" MAX cumulative Read Size: %u\n", 1202 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1203 onoff("Received split completion error", reg, 1204 PCIX_STATUS_SCERR); 1205 } 1206 onoff("266MHz capable", reg, PCIX_STATUS_266); 1207 onoff("533MHz capable", reg, PCIX_STATUS_533); 1208 1209 if (isbridge == 0) 1210 return; 1211 1212 /* Only for bridge */ 1213 for (i = 0; i < 2; i++) { 1214 reg = regs[o2i(capoff+PCIX_BRIDGE_UP_STCR + (4 * i))]; 1215 printf(" %s split transaction control register: 0x%08x\n", 1216 (i == 0) ? "Upstream" : "Downstream", reg); 1217 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1218 printf(" Commitment Limit: %d\n", 1219 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1220 } 1221 } 1222 1223 /* XXX pci_conf_print_ldt_cap */ 1224 /* XXX pci_conf_print_vendspec_cap */ 1225 1226 static void 1227 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1228 { 1229 uint16_t caps; 1230 1231 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1232 1233 printf("\n PCI Vendor Specific Capabilities Register\n"); 1234 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1235 } 1236 1237 static void 1238 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1239 { 1240 pcireg_t val; 1241 1242 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1243 1244 printf("\n Debugport Capability Register\n"); 1245 printf(" Debug base Register: 0x%04x\n", 1246 val >> PCI_DEBUG_BASER_SHIFT); 1247 printf(" port offset: 0x%04x\n", 1248 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1249 printf(" BAR number: %u\n", 1250 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1251 } 1252 1253 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1254 /* XXX pci_conf_print_hotplug_cap */ 1255 1256 static void 1257 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1258 { 1259 pcireg_t reg; 1260 1261 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1262 1263 printf("\n Subsystem ID Capability Register\n"); 1264 printf(" Subsystem ID : 0x%08x\n", reg); 1265 } 1266 1267 /* XXX pci_conf_print_agp8_cap */ 1268 /* XXX pci_conf_print_secure_cap */ 1269 1270 static void 1271 pci_print_pcie_L0s_latency(uint32_t val) 1272 { 1273 1274 switch (val) { 1275 case 0x0: 1276 printf("Less than 64ns\n"); 1277 break; 1278 case 0x1: 1279 case 0x2: 1280 case 0x3: 1281 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1282 break; 1283 case 0x4: 1284 printf("512ns to less than 1us\n"); 1285 break; 1286 case 0x5: 1287 printf("1us to less than 2us\n"); 1288 break; 1289 case 0x6: 1290 printf("2us - 4us\n"); 1291 break; 1292 case 0x7: 1293 printf("More than 4us\n"); 1294 break; 1295 } 1296 } 1297 1298 static void 1299 pci_print_pcie_L1_latency(uint32_t val) 1300 { 1301 1302 switch (val) { 1303 case 0x0: 1304 printf("Less than 1us\n"); 1305 break; 1306 case 0x6: 1307 printf("32us - 64us\n"); 1308 break; 1309 case 0x7: 1310 printf("More than 64us\n"); 1311 break; 1312 default: 1313 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1314 break; 1315 } 1316 } 1317 1318 static void 1319 pci_print_pcie_compl_timeout(uint32_t val) 1320 { 1321 1322 switch (val) { 1323 case 0x0: 1324 printf("50us to 50ms\n"); 1325 break; 1326 case 0x5: 1327 printf("16ms to 55ms\n"); 1328 break; 1329 case 0x6: 1330 printf("65ms to 210ms\n"); 1331 break; 1332 case 0x9: 1333 printf("260ms to 900ms\n"); 1334 break; 1335 case 0xa: 1336 printf("1s to 3.5s\n"); 1337 break; 1338 default: 1339 printf("unknown %u value\n", val); 1340 break; 1341 } 1342 } 1343 1344 static void 1345 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1346 { 1347 pcireg_t reg; /* for each register */ 1348 pcireg_t val; /* for each bitfield */ 1349 bool check_link = false; 1350 bool check_slot = false; 1351 bool check_rootport = false; 1352 unsigned int pciever; 1353 static const char * const linkspeeds[] = {"2.5", "5.0", "8.0"}; 1354 int i; 1355 1356 printf("\n PCI Express Capabilities Register\n"); 1357 /* Capability Register */ 1358 reg = regs[o2i(capoff)]; 1359 printf(" Capability register: %04x\n", reg >> 16); 1360 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1361 printf(" Capability version: %u\n", pciever); 1362 printf(" Device type: "); 1363 switch ((reg & 0x00f00000) >> 20) { 1364 case 0x0: 1365 printf("PCI Express Endpoint device\n"); 1366 check_link = true; 1367 break; 1368 case 0x1: 1369 printf("Legacy PCI Express Endpoint device\n"); 1370 check_link = true; 1371 break; 1372 case 0x4: 1373 printf("Root Port of PCI Express Root Complex\n"); 1374 check_link = true; 1375 check_slot = true; 1376 check_rootport = true; 1377 break; 1378 case 0x5: 1379 printf("Upstream Port of PCI Express Switch\n"); 1380 break; 1381 case 0x6: 1382 printf("Downstream Port of PCI Express Switch\n"); 1383 check_slot = true; 1384 check_rootport = true; 1385 break; 1386 case 0x7: 1387 printf("PCI Express to PCI/PCI-X Bridge\n"); 1388 break; 1389 case 0x8: 1390 printf("PCI/PCI-X to PCI Express Bridge\n"); 1391 break; 1392 case 0x9: 1393 printf("Root Complex Integrated Endpoint\n"); 1394 break; 1395 case 0xa: 1396 check_rootport = true; 1397 printf("Root Complex Event Collector\n"); 1398 break; 1399 default: 1400 printf("unknown\n"); 1401 break; 1402 } 1403 if (check_slot && (reg & PCIE_XCAP_SI) != 0) 1404 printf(" Slot implemented\n"); 1405 printf(" Interrupt Message Number: %x\n", 1406 (unsigned int)((reg & PCIE_XCAP_IRQ) >> 27)); 1407 1408 /* Device Capability Register */ 1409 reg = regs[o2i(capoff + PCIE_DCAP)]; 1410 printf(" Device Capabilities Register: 0x%08x\n", reg); 1411 printf(" Max Payload Size Supported: %u bytes max\n", 1412 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1413 printf(" Phantom Functions Supported: "); 1414 switch ((reg & PCIE_DCAP_PHANTOM_FUNCS) >> 3) { 1415 case 0x0: 1416 printf("not available\n"); 1417 break; 1418 case 0x1: 1419 printf("MSB\n"); 1420 break; 1421 case 0x2: 1422 printf("two MSB\n"); 1423 break; 1424 case 0x3: 1425 printf("All three bits\n"); 1426 break; 1427 } 1428 printf(" Extended Tag Field Supported: %dbit\n", 1429 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1430 printf(" Endpoint L0 Acceptable Latency: "); 1431 pci_print_pcie_L0s_latency((reg & PCIE_DCAP_L0S_LATENCY) >> 6); 1432 printf(" Endpoint L1 Acceptable Latency: "); 1433 pci_print_pcie_L1_latency((reg & PCIE_DCAP_L1_LATENCY) >> 9); 1434 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1435 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1436 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1437 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1438 printf(" Captured Slot Power Limit Value: %d\n", 1439 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18); 1440 printf(" Captured Slot Power Limit Scale: %d\n", 1441 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26); 1442 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1443 1444 /* Device Control Register */ 1445 reg = regs[o2i(capoff + PCIE_DCSR)]; 1446 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1447 onoff("Correctable Error Reporting Enable", reg, 1448 PCIE_DCSR_ENA_COR_ERR); 1449 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1450 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1451 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1452 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1453 printf(" Max Payload Size: %d byte\n", 1454 128 << (((unsigned int)(reg & PCIE_DCSR_MAX_PAYLOAD) >> 5))); 1455 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1456 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1457 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1458 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1459 printf(" Max Read Request Size: %d byte\n", 1460 128 << ((unsigned int)(reg & PCIE_DCSR_MAX_READ_REQ) >> 12)); 1461 1462 /* Device Status Register */ 1463 reg = regs[o2i(capoff + PCIE_DCSR)]; 1464 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1465 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1466 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1467 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1468 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1469 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1470 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1471 1472 if (check_link) { 1473 /* Link Capability Register */ 1474 reg = regs[o2i(capoff + PCIE_LCAP)]; 1475 printf(" Link Capabilities Register: 0x%08x\n", reg); 1476 printf(" Maximum Link Speed: "); 1477 val = reg & PCIE_LCAP_MAX_SPEED; 1478 if (val < 1 || val > 3) { 1479 printf("unknown %u value\n", val); 1480 } else { 1481 printf("%sGT/s\n", linkspeeds[val - 1]); 1482 } 1483 printf(" Maximum Link Width: x%u lanes\n", 1484 (unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4); 1485 printf(" Active State PM Support: "); 1486 val = (reg & PCIE_LCAP_ASPM) >> 10; 1487 switch (val) { 1488 case 0x1: 1489 printf("L0s Entry supported\n"); 1490 break; 1491 case 0x3: 1492 printf("L0s and L1 supported\n"); 1493 break; 1494 default: 1495 printf("Reserved value\n"); 1496 break; 1497 } 1498 printf(" L0 Exit Latency: "); 1499 pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12); 1500 printf(" L1 Exit Latency: "); 1501 pci_print_pcie_L1_latency((reg & PCIE_LCAP_L1_EXIT) >> 15); 1502 printf(" Port Number: %u\n", reg >> 24); 1503 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1504 onoff("Surprise Down Error Report", reg, 1505 PCIE_LCAP_SURPRISE_DOWN); 1506 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1507 onoff("Link BW Notification Capable", reg, 1508 PCIE_LCAP_LINK_BW_NOTIFY); 1509 onoff("ASPM Optionally Compliance", reg, 1510 PCIE_LCAP_ASPM_COMPLIANCE); 1511 1512 /* Link Control Register */ 1513 reg = regs[o2i(capoff + PCIE_LCSR)]; 1514 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1515 printf(" Active State PM Control: "); 1516 val = reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S); 1517 switch (val) { 1518 case 0: 1519 printf("disabled\n"); 1520 break; 1521 case 1: 1522 printf("L0s Entry Enabled\n"); 1523 break; 1524 case 2: 1525 printf("L1 Entry Enabled\n"); 1526 break; 1527 case 3: 1528 printf("L0s and L1 Entry Enabled\n"); 1529 break; 1530 } 1531 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1532 "128bytes", "64bytes"); 1533 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1534 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1535 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1536 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1537 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1538 onoff("Hardware Autonomous Width Disable", reg, 1539 PCIE_LCSR_HAWD); 1540 onoff("Link Bandwidth Management Interrupt Enable", reg, 1541 PCIE_LCSR_LBMIE); 1542 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1543 PCIE_LCSR_LABIE); 1544 1545 /* Link Status Register */ 1546 reg = regs[o2i(capoff + PCIE_LCSR)]; 1547 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1548 printf(" Negotiated Link Speed: "); 1549 if (((reg >> 16) & 0x000f) < 1 || 1550 ((reg >> 16) & 0x000f) > 3) { 1551 printf("unknown %u value\n", 1552 (unsigned int)(reg & PCIE_LCSR_LINKSPEED) >> 16); 1553 } else { 1554 printf("%sGT/s\n", 1555 linkspeeds[((reg & PCIE_LCSR_LINKSPEED) >> 16) - 1]); 1556 } 1557 printf(" Negotiated Link Width: x%u lanes\n", 1558 (reg >> 20) & 0x003f); 1559 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1560 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1561 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1562 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1563 onoff("Link Bandwidth Management Status", reg, 1564 PCIE_LCSR_LINK_BW_MGMT); 1565 onoff("Link Autonomous Bandwidth Status", reg, 1566 PCIE_LCSR_LINK_AUTO_BW); 1567 } 1568 1569 if (check_slot == true) { 1570 /* Slot Capability Register */ 1571 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1572 printf(" Slot Capability Register: %08x\n", reg); 1573 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1574 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1575 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1576 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1577 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1578 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1579 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1580 printf(" Slot Power Limit Value: %d\n", 1581 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1582 printf(" Slot Power Limit Scale: %d\n", 1583 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1584 onoff("Electromechanical Interlock Present", reg, 1585 PCIE_SLCAP_EIP); 1586 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1587 printf(" Physical Slot Number: %d\n", 1588 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1589 1590 /* Slot Control Register */ 1591 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1592 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1593 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1594 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1595 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1596 onoff("Presense Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1597 onoff("Command Completed Interrupt Enabled", reg, 1598 PCIE_SLCSR_CCE); 1599 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1600 printf(" Attention Indicator Control: "); 1601 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1602 case 0x0: 1603 printf("reserved\n"); 1604 break; 1605 case 0x1: 1606 printf("on\n"); 1607 break; 1608 case 0x2: 1609 printf("blink\n"); 1610 break; 1611 case 0x3: 1612 printf("off\n"); 1613 break; 1614 } 1615 printf(" Power Indicator Control: "); 1616 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1617 case 0x0: 1618 printf("reserved\n"); 1619 break; 1620 case 0x1: 1621 printf("on\n"); 1622 break; 1623 case 0x2: 1624 printf("blink\n"); 1625 break; 1626 case 0x3: 1627 printf("off\n"); 1628 break; 1629 } 1630 onoff("Power Controller Control", reg, PCIE_SLCSR_PCC); 1631 onoff("Electromechanical Interlock Control", 1632 reg, PCIE_SLCSR_EIC); 1633 onoff("Data Link Layer State Changed Enable", reg, 1634 PCIE_SLCSR_DLLSCE); 1635 1636 /* Slot Status Register */ 1637 printf(" Slot Status Register: %04x\n", reg >> 16); 1638 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1639 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1640 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1641 onoff("Presense Detect Changed", reg, PCIE_SLCSR_PDC); 1642 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1643 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1644 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1645 onoff("Electromechanical Interlock engaged", reg, 1646 PCIE_SLCSR_EIS); 1647 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 1648 } 1649 1650 if (check_rootport == true) { 1651 /* Root Control Register */ 1652 reg = regs[o2i(capoff + PCIE_RCR)]; 1653 printf(" Root Control Register: %04x\n", reg & 0xffff); 1654 onoff("SERR on Correctable Error Enable", reg, 1655 PCIE_RCR_SERR_CER); 1656 onoff("SERR on Non-Fatal Error Enable", reg, 1657 PCIE_RCR_SERR_NFER); 1658 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 1659 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 1660 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 1661 1662 /* Root Capability Register */ 1663 printf(" Root Capability Register: %04x\n", 1664 reg >> 16); 1665 1666 /* Root Status Register */ 1667 reg = regs[o2i(capoff + PCIE_RSR)]; 1668 printf(" Root Status Register: %08x\n", reg); 1669 printf(" PME Requester ID: %04x\n", 1670 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1671 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 1672 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 1673 } 1674 1675 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1676 if (pciever < 2) 1677 return; 1678 1679 /* Device Capabilities 2 */ 1680 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1681 printf(" Device Capabilities 2: 0x%08x\n", reg); 1682 printf(" Completion Timeout Ranges Supported: %u \n", 1683 (unsigned int)(reg & PCIE_DCAP2_COMPT_RANGE)); 1684 onoff("Completion Timeout Disable Supported", reg, 1685 PCIE_DCAP2_COMPT_DIS); 1686 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 1687 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 1688 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 1689 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 1690 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 1691 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 1692 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 1693 printf(" TPH Completer Supported: %u\n", 1694 (unsigned int)(reg & PCIE_DCAP2_TPH_COMP) >> 12); 1695 printf(" OBFF Supported: "); 1696 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 1697 case 0x0: 1698 printf("Not supported\n"); 1699 break; 1700 case 0x1: 1701 printf("Message only\n"); 1702 break; 1703 case 0x2: 1704 printf("WAKE# only\n"); 1705 break; 1706 case 0x3: 1707 printf("Both\n"); 1708 break; 1709 } 1710 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 1711 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 1712 printf(" Max End-End TLP Prefixes: %u\n", 1713 (unsigned int)(reg & PCIE_DCAP2_MAX_EETLP) >> 22); 1714 1715 /* Device Control 2 */ 1716 reg = regs[o2i(capoff + PCIE_DCSR2)]; 1717 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 1718 printf(" Completion Timeout Value: "); 1719 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 1720 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 1721 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 1722 onoff("AtomicOp Rquester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 1723 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 1724 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 1725 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 1726 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 1727 printf(" OBFF: "); 1728 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 1729 case 0x0: 1730 printf("Disabled\n"); 1731 break; 1732 case 0x1: 1733 printf("Enabled with Message Signaling Variation A\n"); 1734 break; 1735 case 0x2: 1736 printf("Enabled with Message Signaling Variation B\n"); 1737 break; 1738 case 0x3: 1739 printf("Enabled using WAKE# signaling\n"); 1740 break; 1741 } 1742 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 1743 1744 if (check_link) { 1745 /* Link Capability 2 */ 1746 reg = regs[o2i(capoff + PCIE_LCAP2)]; 1747 printf(" Link Capabilities 2: 0x%08x\n", reg); 1748 val = (reg & PCIE_LCAP2_SUP_LNKSV) >> 1; 1749 printf(" Supported Link Speed Vector:"); 1750 for (i = 0; i <= 2; i++) { 1751 if (((val >> i) & 0x01) != 0) 1752 printf(" %sGT/s", linkspeeds[i]); 1753 } 1754 printf("\n"); 1755 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 1756 1757 /* Link Control 2 */ 1758 reg = regs[o2i(capoff + PCIE_LCSR2)]; 1759 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 1760 printf(" Target Link Speed: "); 1761 val = reg & PCIE_LCSR2_TGT_LSPEED; 1762 if (val < 1 || val > 3) 1763 printf("unknown %u value\n", val); 1764 else 1765 printf("%sGT/s\n", linkspeeds[val - 1]); 1766 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 1767 onoff("HW Autonomous Speed Disabled", reg, 1768 PCIE_LCSR2_HW_AS_DIS); 1769 onoff("Selectable De-emphasis", reg, PCIE_LCSR2_SEL_DEEMP); 1770 printf(" Transmit Margin: %u\n", 1771 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 1772 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 1773 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 1774 printf(" Compliance Present/De-emphasis: %u\n", 1775 (unsigned int)(reg & PCIE_LCSR2_COMP_DEEMP) >> 12); 1776 1777 /* Link Status 2 */ 1778 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 1779 onoff("Current De-emphasis Level", reg, PCIE_LCSR2_DEEMP_LVL); 1780 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 1781 onoff("Equalization Phase 1 Successful", reg, 1782 PCIE_LCSR2_EQP1_SUC); 1783 onoff("Equalization Phase 2 Successful", reg, 1784 PCIE_LCSR2_EQP2_SUC); 1785 onoff("Equalization Phase 3 Successful", reg, 1786 PCIE_LCSR2_EQP3_SUC); 1787 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 1788 } 1789 1790 /* Slot Capability 2 */ 1791 /* Slot Control 2 */ 1792 /* Slot Status 2 */ 1793 } 1794 1795 static void 1796 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 1797 { 1798 pcireg_t reg; 1799 1800 printf("\n MSI-X Capability Register\n"); 1801 1802 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 1803 printf(" Message Control register: 0x%04x\n", 1804 (reg >> 16) & 0xff); 1805 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 1806 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 1807 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 1808 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 1809 printf(" Table offset register: 0x%08x\n", reg); 1810 printf(" Table offset: %08x\n", reg & PCI_MSIX_TBLOFFSET_MASK); 1811 printf(" BIR: 0x%x\n", reg & PCI_MSIX_TBLBIR_MASK); 1812 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 1813 printf(" Pending bit array register: 0x%08x\n", reg); 1814 printf(" Pending bit array offset: %08x\n", 1815 reg & PCI_MSIX_PBAOFFSET_MASK); 1816 printf(" BIR: 0x%x\n", reg & PCI_MSIX_PBABIR_MASK); 1817 } 1818 1819 /* XXX pci_conf_print_sata_cap */ 1820 static void 1821 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 1822 { 1823 pcireg_t reg; 1824 1825 printf("\n Advanced Features Capability Register\n"); 1826 1827 reg = regs[o2i(capoff + PCI_AFCAPR)]; 1828 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 1829 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 1830 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 1831 reg = regs[o2i(capoff + PCI_AFCSR)]; 1832 printf(" AF Control register: 0x%02x\n", reg & 0xff); 1833 /* 1834 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 1835 * and it's always 0 on read 1836 */ 1837 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 1838 onoff("Transaction Pending", reg, PCI_AFSR_TP); 1839 } 1840 1841 static void 1842 pci_conf_print_caplist( 1843 #ifdef _KERNEL 1844 pci_chipset_tag_t pc, pcitag_t tag, 1845 #endif 1846 const pcireg_t *regs, int capoff) 1847 { 1848 int off; 1849 pcireg_t rval; 1850 int pcie_off = -1, pcipm_off = -1, msi_off = -1, pcix_off = -1; 1851 int vendspec_off = -1, msix_off = -1; 1852 int debugport_off = -1, subsystem_off = -1, pciaf_off = -1; 1853 1854 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1855 off != 0; 1856 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 1857 rval = regs[o2i(off)]; 1858 printf(" Capability register at 0x%02x\n", off); 1859 1860 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 1861 switch (PCI_CAPLIST_CAP(rval)) { 1862 case PCI_CAP_RESERVED0: 1863 printf("reserved"); 1864 break; 1865 case PCI_CAP_PWRMGMT: 1866 printf("Power Management, rev. %s", 1867 pci_conf_print_pcipm_cap_pmrev((rval >> 0) & 0x07)); 1868 pcipm_off = off; 1869 break; 1870 case PCI_CAP_AGP: 1871 printf("AGP, rev. %d.%d", 1872 PCI_CAP_AGP_MAJOR(rval), 1873 PCI_CAP_AGP_MINOR(rval)); 1874 break; 1875 case PCI_CAP_VPD: 1876 printf("VPD"); 1877 break; 1878 case PCI_CAP_SLOTID: 1879 printf("SlotID"); 1880 break; 1881 case PCI_CAP_MSI: 1882 printf("MSI"); 1883 msi_off = off; 1884 break; 1885 case PCI_CAP_CPCI_HOTSWAP: 1886 printf("CompactPCI Hot-swapping"); 1887 break; 1888 case PCI_CAP_PCIX: 1889 pcix_off = off; 1890 printf("PCI-X"); 1891 break; 1892 case PCI_CAP_LDT: 1893 printf("LDT"); 1894 break; 1895 case PCI_CAP_VENDSPEC: 1896 vendspec_off = off; 1897 printf("Vendor-specific"); 1898 break; 1899 case PCI_CAP_DEBUGPORT: 1900 printf("Debug Port"); 1901 debugport_off = off; 1902 break; 1903 case PCI_CAP_CPCI_RSRCCTL: 1904 printf("CompactPCI Resource Control"); 1905 break; 1906 case PCI_CAP_HOTPLUG: 1907 printf("Hot-Plug"); 1908 break; 1909 case PCI_CAP_SUBVENDOR: 1910 printf("Subsystem ID"); 1911 subsystem_off = off; 1912 break; 1913 case PCI_CAP_AGP8: 1914 printf("AGP 8x"); 1915 break; 1916 case PCI_CAP_SECURE: 1917 printf("Secure Device"); 1918 break; 1919 case PCI_CAP_PCIEXPRESS: 1920 printf("PCI Express"); 1921 pcie_off = off; 1922 break; 1923 case PCI_CAP_MSIX: 1924 printf("MSI-X"); 1925 msix_off = off; 1926 break; 1927 case PCI_CAP_SATA: 1928 printf("SATA"); 1929 break; 1930 case PCI_CAP_PCIAF: 1931 printf("Advanced Features"); 1932 pciaf_off = off; 1933 break; 1934 default: 1935 printf("unknown"); 1936 } 1937 printf(")\n"); 1938 } 1939 if (pcipm_off != -1) 1940 pci_conf_print_pcipm_cap(regs, pcipm_off); 1941 /* XXX AGP */ 1942 /* XXX VPD */ 1943 /* XXX SLOTID */ 1944 if (msi_off != -1) 1945 pci_conf_print_msi_cap(regs, msi_off); 1946 /* XXX CPCI_HOTSWAP */ 1947 if (pcix_off != -1) 1948 pci_conf_print_pcix_cap(regs, pcix_off); 1949 /* XXX LDT */ 1950 if (vendspec_off != -1) 1951 pci_conf_print_vendspec_cap(regs, vendspec_off); 1952 if (debugport_off != -1) 1953 pci_conf_print_debugport_cap(regs, debugport_off); 1954 /* XXX CPCI_RSRCCTL */ 1955 /* XXX HOTPLUG */ 1956 if (subsystem_off != -1) 1957 pci_conf_print_subsystem_cap(regs, subsystem_off); 1958 /* XXX AGP8 */ 1959 /* XXX SECURE */ 1960 if (pcie_off != -1) 1961 pci_conf_print_pcie_cap(regs, pcie_off); 1962 if (msix_off != -1) 1963 pci_conf_print_msix_cap(regs, msix_off); 1964 /* XXX SATA */ 1965 if (pciaf_off != -1) 1966 pci_conf_print_pciaf_cap(regs, pciaf_off); 1967 } 1968 1969 /* Print the Secondary Status Register. */ 1970 static void 1971 pci_conf_print_ssr(pcireg_t rval) 1972 { 1973 pcireg_t devsel; 1974 1975 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 1976 onoff("66 MHz capable", rval, __BIT(5)); 1977 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 1978 onoff("Fast back-to-back capable", rval, __BIT(7)); 1979 onoff("Data parity error detected", rval, __BIT(8)); 1980 1981 printf(" DEVSEL timing: "); 1982 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 1983 switch (devsel) { 1984 case 0: 1985 printf("fast"); 1986 break; 1987 case 1: 1988 printf("medium"); 1989 break; 1990 case 2: 1991 printf("slow"); 1992 break; 1993 default: 1994 printf("unknown/reserved"); /* XXX */ 1995 break; 1996 } 1997 printf(" (0x%x)\n", devsel); 1998 1999 onoff("Signalled target abort", rval, __BIT(11)); 2000 onoff("Received target abort", rval, __BIT(12)); 2001 onoff("Received master abort", rval, __BIT(13)); 2002 onoff("Received system error", rval, __BIT(14)); 2003 onoff("Detected parity error", rval, __BIT(15)); 2004 } 2005 2006 static void 2007 pci_conf_print_type0( 2008 #ifdef _KERNEL 2009 pci_chipset_tag_t pc, pcitag_t tag, 2010 #endif 2011 const pcireg_t *regs 2012 #ifdef _KERNEL 2013 , int sizebars 2014 #endif 2015 ) 2016 { 2017 int off, width; 2018 pcireg_t rval; 2019 2020 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 2021 #ifdef _KERNEL 2022 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 2023 #else 2024 width = pci_conf_print_bar(regs, off, NULL); 2025 #endif 2026 } 2027 2028 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 2029 2030 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 2031 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 2032 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 2033 2034 /* XXX */ 2035 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 2036 2037 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2038 printf(" Capability list pointer: 0x%02x\n", 2039 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 2040 else 2041 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 2042 2043 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 2044 2045 rval = regs[o2i(PCI_INTERRUPT_REG)]; 2046 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 2047 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 2048 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 2049 switch (PCI_INTERRUPT_PIN(rval)) { 2050 case PCI_INTERRUPT_PIN_NONE: 2051 printf("(none)"); 2052 break; 2053 case PCI_INTERRUPT_PIN_A: 2054 printf("(pin A)"); 2055 break; 2056 case PCI_INTERRUPT_PIN_B: 2057 printf("(pin B)"); 2058 break; 2059 case PCI_INTERRUPT_PIN_C: 2060 printf("(pin C)"); 2061 break; 2062 case PCI_INTERRUPT_PIN_D: 2063 printf("(pin D)"); 2064 break; 2065 default: 2066 printf("(? ? ?)"); 2067 break; 2068 } 2069 printf("\n"); 2070 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 2071 } 2072 2073 static void 2074 pci_conf_print_type1( 2075 #ifdef _KERNEL 2076 pci_chipset_tag_t pc, pcitag_t tag, 2077 #endif 2078 const pcireg_t *regs 2079 #ifdef _KERNEL 2080 , int sizebars 2081 #endif 2082 ) 2083 { 2084 int off, width; 2085 pcireg_t rval; 2086 uint32_t base, limit; 2087 uint32_t base_h, limit_h; 2088 uint64_t pbase, plimit; 2089 int use_upper; 2090 2091 /* 2092 * XXX these need to be printed in more detail, need to be 2093 * XXX checked against specs/docs, etc. 2094 * 2095 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 2096 * Bridge chip documentation, and may not be correct with 2097 * respect to various standards. (XXX) 2098 */ 2099 2100 for (off = 0x10; off < 0x18; off += width) { 2101 #ifdef _KERNEL 2102 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 2103 #else 2104 width = pci_conf_print_bar(regs, off, NULL); 2105 #endif 2106 } 2107 2108 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 2109 printf(" Primary bus number: 0x%02x\n", 2110 PCI_BRIDGE_BUS_PRIMARY(rval)); 2111 printf(" Secondary bus number: 0x%02x\n", 2112 PCI_BRIDGE_BUS_SECONDARY(rval)); 2113 printf(" Subordinate bus number: 0x%02x\n", 2114 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 2115 printf(" Secondary bus latency timer: 0x%02x\n", 2116 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 2117 2118 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 2119 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 2120 2121 /* I/O region */ 2122 printf(" I/O region:\n"); 2123 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 2124 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 2125 if (PCI_BRIDGE_IO_32BITS(rval)) 2126 use_upper = 1; 2127 else 2128 use_upper = 0; 2129 onoff("32bit I/O", rval, use_upper); 2130 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 2131 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 2132 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 2133 limit |= 0x00000fff; 2134 2135 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 2136 base_h = (rval >> 0) & 0xffff; 2137 limit_h = (rval >> 16) & 0xffff; 2138 printf(" base upper 16 bits register: 0x%04x\n", base_h); 2139 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 2140 2141 if (use_upper == 1) { 2142 base |= base_h << 16; 2143 limit |= limit_h << 16; 2144 } 2145 if (base < limit) { 2146 if (use_upper == 1) 2147 printf(" range: 0x%08x-0x%08x\n", base, limit); 2148 else 2149 printf(" range: 0x%04x-0x%04x\n", base, limit); 2150 } else 2151 printf(" range: not set\n"); 2152 2153 /* Non-prefetchable memory region */ 2154 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 2155 printf(" Memory region:\n"); 2156 printf(" base register: 0x%04x\n", 2157 (rval >> 0) & 0xffff); 2158 printf(" limit register: 0x%04x\n", 2159 (rval >> 16) & 0xffff); 2160 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 2161 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 2162 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 2163 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 2164 if (base < limit) 2165 printf(" range: 0x%08x-0x%08x\n", base, limit); 2166 else 2167 printf(" range: not set\n"); 2168 2169 /* Prefetchable memory region */ 2170 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 2171 printf(" Prefetchable memory region:\n"); 2172 printf(" base register: 0x%04x\n", 2173 (rval >> 0) & 0xffff); 2174 printf(" limit register: 0x%04x\n", 2175 (rval >> 16) & 0xffff); 2176 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 2177 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 2178 printf(" base upper 32 bits register: 0x%08x\n", 2179 base_h); 2180 printf(" limit upper 32 bits register: 0x%08x\n", 2181 limit_h); 2182 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 2183 use_upper = 1; 2184 else 2185 use_upper = 0; 2186 onoff("64bit memory address", rval, use_upper); 2187 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 2188 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 2189 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 2190 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 2191 if (use_upper == 1) { 2192 pbase |= (uint64_t)base_h << 32; 2193 plimit |= (uint64_t)limit_h << 32; 2194 } 2195 if (pbase < plimit) { 2196 if (use_upper == 1) 2197 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 2198 "\n", pbase, plimit); 2199 else 2200 printf(" range: 0x%08x-0x%08x\n", 2201 (uint32_t)pbase, (uint32_t)plimit); 2202 } else 2203 printf(" range: not set\n"); 2204 2205 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2206 printf(" Capability list pointer: 0x%02x\n", 2207 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 2208 else 2209 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 2210 2211 /* XXX */ 2212 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 2213 2214 rval = regs[o2i(PCI_INTERRUPT_REG)]; 2215 printf(" Interrupt line: 0x%02x\n", 2216 (rval >> 0) & 0xff); 2217 printf(" Interrupt pin: 0x%02x ", 2218 (rval >> 8) & 0xff); 2219 switch ((rval >> 8) & 0xff) { 2220 case PCI_INTERRUPT_PIN_NONE: 2221 printf("(none)"); 2222 break; 2223 case PCI_INTERRUPT_PIN_A: 2224 printf("(pin A)"); 2225 break; 2226 case PCI_INTERRUPT_PIN_B: 2227 printf("(pin B)"); 2228 break; 2229 case PCI_INTERRUPT_PIN_C: 2230 printf("(pin C)"); 2231 break; 2232 case PCI_INTERRUPT_PIN_D: 2233 printf("(pin D)"); 2234 break; 2235 default: 2236 printf("(? ? ?)"); 2237 break; 2238 } 2239 printf("\n"); 2240 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 2241 & PCI_BRIDGE_CONTROL_MASK; 2242 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 2243 onoff("Parity error response", rval, 0x0001); 2244 onoff("Secondary SERR forwarding", rval, 0x0002); 2245 onoff("ISA enable", rval, 0x0004); 2246 onoff("VGA enable", rval, 0x0008); 2247 onoff("Master abort reporting", rval, 0x0020); 2248 onoff("Secondary bus reset", rval, 0x0040); 2249 onoff("Fast back-to-back capable", rval, 0x0080); 2250 } 2251 2252 static void 2253 pci_conf_print_type2( 2254 #ifdef _KERNEL 2255 pci_chipset_tag_t pc, pcitag_t tag, 2256 #endif 2257 const pcireg_t *regs 2258 #ifdef _KERNEL 2259 , int sizebars 2260 #endif 2261 ) 2262 { 2263 pcireg_t rval; 2264 2265 /* 2266 * XXX these need to be printed in more detail, need to be 2267 * XXX checked against specs/docs, etc. 2268 * 2269 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 2270 * controller chip documentation, and may not be correct with 2271 * respect to various standards. (XXX) 2272 */ 2273 2274 #ifdef _KERNEL 2275 pci_conf_print_bar(pc, tag, regs, 0x10, 2276 "CardBus socket/ExCA registers", sizebars); 2277 #else 2278 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 2279 #endif 2280 2281 /* Capability list pointer and secondary status register */ 2282 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 2283 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2284 printf(" Capability list pointer: 0x%02x\n", 2285 PCI_CAPLIST_PTR(rval)); 2286 else 2287 printf(" Reserved @ 0x14: 0x%04" PRIxMAX "\n", 2288 __SHIFTOUT(rval, __BITS(15, 0))); 2289 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 2290 2291 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 2292 printf(" PCI bus number: 0x%02x\n", 2293 (rval >> 0) & 0xff); 2294 printf(" CardBus bus number: 0x%02x\n", 2295 (rval >> 8) & 0xff); 2296 printf(" Subordinate bus number: 0x%02x\n", 2297 (rval >> 16) & 0xff); 2298 printf(" CardBus latency timer: 0x%02x\n", 2299 (rval >> 24) & 0xff); 2300 2301 /* XXX Print more prettily */ 2302 printf(" CardBus memory region 0:\n"); 2303 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 2304 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 2305 printf(" CardBus memory region 1:\n"); 2306 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 2307 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 2308 printf(" CardBus I/O region 0:\n"); 2309 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 2310 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 2311 printf(" CardBus I/O region 1:\n"); 2312 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 2313 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 2314 2315 rval = regs[o2i(PCI_INTERRUPT_REG)]; 2316 printf(" Interrupt line: 0x%02x\n", 2317 (rval >> 0) & 0xff); 2318 printf(" Interrupt pin: 0x%02x ", 2319 (rval >> 8) & 0xff); 2320 switch ((rval >> 8) & 0xff) { 2321 case PCI_INTERRUPT_PIN_NONE: 2322 printf("(none)"); 2323 break; 2324 case PCI_INTERRUPT_PIN_A: 2325 printf("(pin A)"); 2326 break; 2327 case PCI_INTERRUPT_PIN_B: 2328 printf("(pin B)"); 2329 break; 2330 case PCI_INTERRUPT_PIN_C: 2331 printf("(pin C)"); 2332 break; 2333 case PCI_INTERRUPT_PIN_D: 2334 printf("(pin D)"); 2335 break; 2336 default: 2337 printf("(? ? ?)"); 2338 break; 2339 } 2340 printf("\n"); 2341 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 2342 printf(" Bridge control register: 0x%04x\n", rval); 2343 onoff("Parity error response", rval, __BIT(0)); 2344 onoff("SERR# enable", rval, __BIT(1)); 2345 onoff("ISA enable", rval, __BIT(2)); 2346 onoff("VGA enable", rval, __BIT(3)); 2347 onoff("Master abort mode", rval, __BIT(5)); 2348 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 2349 onoff("Functional interrupts routed by ExCA registers", rval, 2350 __BIT(7)); 2351 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 2352 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 2353 onoff("Write posting enable", rval, __BIT(10)); 2354 2355 rval = regs[o2i(0x40)]; 2356 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 2357 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 2358 2359 #ifdef _KERNEL 2360 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 2361 sizebars); 2362 #else 2363 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 2364 #endif 2365 } 2366 2367 void 2368 pci_conf_print( 2369 #ifdef _KERNEL 2370 pci_chipset_tag_t pc, pcitag_t tag, 2371 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 2372 #else 2373 int pcifd, u_int bus, u_int dev, u_int func 2374 #endif 2375 ) 2376 { 2377 pcireg_t regs[o2i(256)]; 2378 int off, capoff, endoff, hdrtype; 2379 const char *typename; 2380 #ifdef _KERNEL 2381 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 2382 int sizebars; 2383 #else 2384 void (*typeprintfn)(const pcireg_t *); 2385 #endif 2386 2387 printf("PCI configuration registers:\n"); 2388 2389 for (off = 0; off < 256; off += 4) { 2390 #ifdef _KERNEL 2391 regs[o2i(off)] = pci_conf_read(pc, tag, off); 2392 #else 2393 if (pcibus_conf_read(pcifd, bus, dev, func, off, 2394 ®s[o2i(off)]) == -1) 2395 regs[o2i(off)] = 0; 2396 #endif 2397 } 2398 2399 #ifdef _KERNEL 2400 sizebars = 1; 2401 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 2402 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 2403 sizebars = 0; 2404 #endif 2405 2406 /* common header */ 2407 printf(" Common header:\n"); 2408 pci_conf_print_regs(regs, 0, 16); 2409 2410 printf("\n"); 2411 #ifdef _KERNEL 2412 pci_conf_print_common(pc, tag, regs); 2413 #else 2414 pci_conf_print_common(regs); 2415 #endif 2416 printf("\n"); 2417 2418 /* type-dependent header */ 2419 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 2420 switch (hdrtype) { /* XXX make a table, eventually */ 2421 case 0: 2422 /* Standard device header */ 2423 typename = "\"normal\" device"; 2424 typeprintfn = &pci_conf_print_type0; 2425 capoff = PCI_CAPLISTPTR_REG; 2426 endoff = 64; 2427 break; 2428 case 1: 2429 /* PCI-PCI bridge header */ 2430 typename = "PCI-PCI bridge"; 2431 typeprintfn = &pci_conf_print_type1; 2432 capoff = PCI_CAPLISTPTR_REG; 2433 endoff = 64; 2434 break; 2435 case 2: 2436 /* PCI-CardBus bridge header */ 2437 typename = "PCI-CardBus bridge"; 2438 typeprintfn = &pci_conf_print_type2; 2439 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 2440 endoff = 72; 2441 break; 2442 default: 2443 typename = NULL; 2444 typeprintfn = 0; 2445 capoff = -1; 2446 endoff = 64; 2447 break; 2448 } 2449 printf(" Type %d ", hdrtype); 2450 if (typename != NULL) 2451 printf("(%s) ", typename); 2452 printf("header:\n"); 2453 pci_conf_print_regs(regs, 16, endoff); 2454 printf("\n"); 2455 if (typeprintfn) { 2456 #ifdef _KERNEL 2457 (*typeprintfn)(pc, tag, regs, sizebars); 2458 #else 2459 (*typeprintfn)(regs); 2460 #endif 2461 } else 2462 printf(" Don't know how to pretty-print type %d header.\n", 2463 hdrtype); 2464 printf("\n"); 2465 2466 /* capability list, if present */ 2467 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2468 && (capoff > 0)) { 2469 #ifdef _KERNEL 2470 pci_conf_print_caplist(pc, tag, regs, capoff); 2471 #else 2472 pci_conf_print_caplist(regs, capoff); 2473 #endif 2474 printf("\n"); 2475 } 2476 2477 /* device-dependent header */ 2478 printf(" Device-dependent header:\n"); 2479 pci_conf_print_regs(regs, endoff, 256); 2480 printf("\n"); 2481 #ifdef _KERNEL 2482 if (printfn) 2483 (*printfn)(pc, tag, regs); 2484 else 2485 printf(" Don't know how to pretty-print device-dependent header.\n"); 2486 printf("\n"); 2487 #endif /* _KERNEL */ 2488 } 2489
Indexes created Wed Sep 24 22:09:59 GMT 2025