pci_subr.c revision 1.124
1 /* $NetBSD: pci_subr.c,v 1.124 2014/06/09 11:08:05 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.124 2014/06/09 11:08:05 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdbool.h> 58 #include <stdio.h> 59 #include <string.h> 60 #endif 61 62 #include <dev/pci/pcireg.h> 63 #ifdef _KERNEL 64 #include <dev/pci/pcivar.h> 65 #endif 66 67 /* 68 * Descriptions of known PCI classes and subclasses. 69 * 70 * Subclasses are described in the same way as classes, but have a 71 * NULL subclass pointer. 72 */ 73 struct pci_class { 74 const char *name; 75 u_int val; /* as wide as pci_{,sub}class_t */ 76 const struct pci_class *subclasses; 77 }; 78 79 /* 80 * Class 0x00. 81 * Before rev. 2.0. 82 */ 83 static const struct pci_class pci_subclass_prehistoric[] = { 84 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 85 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 86 { NULL, 0, NULL, }, 87 }; 88 89 /* 90 * Class 0x01. 91 * Mass strage controller 92 */ 93 94 /* ATA programming interface */ 95 static const struct pci_class pci_interface_ata[] = { 96 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 97 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 98 { NULL, 0, NULL, }, 99 }; 100 101 /* SATA programming interface */ 102 static const struct pci_class pci_interface_sata[] = { 103 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 104 { NULL, 0, NULL, }, 105 }; 106 107 /* Subclasses */ 108 static const struct pci_class pci_subclass_mass_storage[] = { 109 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 110 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 111 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 112 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 113 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 114 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 115 pci_interface_ata, }, 116 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 117 pci_interface_sata, }, 118 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 119 { "NVM", PCI_SUBCLASS_MASS_STORAGE_NVM, NULL, }, 120 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 121 { NULL, 0, NULL, }, 122 }; 123 124 /* 125 * Class 0x02. 126 * Network controller. 127 */ 128 static const struct pci_class pci_subclass_network[] = { 129 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 130 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 131 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 132 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 133 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 134 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 135 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 136 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 137 { NULL, 0, NULL, }, 138 }; 139 140 /* 141 * Class 0x03. 142 * Display controller. 143 */ 144 145 /* VGA programming interface */ 146 static const struct pci_class pci_interface_vga[] = { 147 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 148 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 149 { NULL, 0, NULL, }, 150 }; 151 /* Subclasses */ 152 static const struct pci_class pci_subclass_display[] = { 153 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 154 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 155 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 156 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 157 { NULL, 0, NULL, }, 158 }; 159 160 /* 161 * Class 0x04. 162 * Multimedia device. 163 */ 164 static const struct pci_class pci_subclass_multimedia[] = { 165 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 166 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 167 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 168 { "HD audio", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 169 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 170 { NULL, 0, NULL, }, 171 }; 172 173 /* 174 * Class 0x05. 175 * Memory controller. 176 */ 177 static const struct pci_class pci_subclass_memory[] = { 178 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 179 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 180 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 181 { NULL, 0, NULL, }, 182 }; 183 184 /* 185 * Class 0x06. 186 * Bridge device. 187 */ 188 189 /* PCI bridge programming interface */ 190 static const struct pci_class pci_interface_pcibridge[] = { 191 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 192 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 193 { NULL, 0, NULL, }, 194 }; 195 196 /* Semi-transparent PCI-toPCI bridge programming interface */ 197 static const struct pci_class pci_interface_stpci[] = { 198 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 199 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 200 { NULL, 0, NULL, }, 201 }; 202 203 /* Subclasses */ 204 static const struct pci_class pci_subclass_bridge[] = { 205 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 206 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 207 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 208 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 209 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 210 pci_interface_pcibridge, }, 211 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 212 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 213 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 214 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 215 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 216 pci_interface_stpci, }, 217 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 218 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 219 { NULL, 0, NULL, }, 220 }; 221 222 /* 223 * Class 0x07. 224 * Simple communications controller. 225 */ 226 227 /* Serial controller programming interface */ 228 static const struct pci_class pci_interface_serial[] = { 229 { "genric XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 230 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 231 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 232 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 233 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 234 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 235 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 236 { NULL, 0, NULL, }, 237 }; 238 239 /* Parallel controller programming interface */ 240 static const struct pci_class pci_interface_parallel[] = { 241 { "", PCI_INTERFACE_PARALLEL, NULL,}, 242 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 243 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 244 { "IEEE1284", PCI_INTERFACE_PARALLEL_IEEE1284, NULL,}, 245 { "IEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 246 { NULL, 0, NULL,}, 247 }; 248 249 /* Modem programming interface */ 250 static const struct pci_class pci_interface_modem[] = { 251 { "", PCI_INTERFACE_MODEM, NULL,}, 252 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 253 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 254 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 255 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 256 { NULL, 0, NULL,}, 257 }; 258 259 /* Subclasses */ 260 static const struct pci_class pci_subclass_communications[] = { 261 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 262 pci_interface_serial, }, 263 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 264 pci_interface_parallel, }, 265 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 266 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 267 pci_interface_modem, }, 268 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 269 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 270 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 271 { NULL, 0, NULL,}, 272 }; 273 274 /* 275 * Class 0x08. 276 * Base system peripheral. 277 */ 278 279 /* PIC programming interface */ 280 static const struct pci_class pci_interface_pic[] = { 281 { "genric 8259", PCI_INTERFACE_PIC_8259, NULL, }, 282 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 283 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 284 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 285 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 286 { NULL, 0, NULL, }, 287 }; 288 289 /* DMA programming interface */ 290 static const struct pci_class pci_interface_dma[] = { 291 { "genric 8237", PCI_INTERFACE_DMA_8237, NULL, }, 292 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 293 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 294 { NULL, 0, NULL, }, 295 }; 296 297 /* Timer programming interface */ 298 static const struct pci_class pci_interface_tmr[] = { 299 { "genric 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 300 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 301 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 302 { NULL, 0, NULL, }, 303 }; 304 305 /* RTC programming interface */ 306 static const struct pci_class pci_interface_rtc[] = { 307 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 308 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 309 { NULL, 0, NULL, }, 310 }; 311 312 /* Subclasses */ 313 static const struct pci_class pci_subclass_system[] = { 314 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 315 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 316 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 317 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 318 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 319 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 320 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 321 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 322 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 323 { NULL, 0, NULL, }, 324 }; 325 326 /* 327 * Class 0x09. 328 * Input device. 329 */ 330 331 /* Gameport programming interface */ 332 static const struct pci_class pci_interface_game[] = { 333 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 334 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 335 { NULL, 0, NULL, }, 336 }; 337 338 /* Subclasses */ 339 static const struct pci_class pci_subclass_input[] = { 340 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 341 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 342 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 343 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 344 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 345 pci_interface_game, }, 346 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 347 { NULL, 0, NULL, }, 348 }; 349 350 /* 351 * Class 0x0a. 352 * Docking station. 353 */ 354 static const struct pci_class pci_subclass_dock[] = { 355 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 356 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 357 { NULL, 0, NULL, }, 358 }; 359 360 /* 361 * Class 0x0b. 362 * Processor. 363 */ 364 static const struct pci_class pci_subclass_processor[] = { 365 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 366 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 367 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 368 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 369 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 370 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 371 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 372 { NULL, 0, NULL, }, 373 }; 374 375 /* 376 * Class 0x0c. 377 * Serial bus controller. 378 */ 379 380 /* IEEE1394 programming interface */ 381 static const struct pci_class pci_interface_ieee1394[] = { 382 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 383 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 384 { NULL, 0, NULL,}, 385 }; 386 387 /* USB programming interface */ 388 static const struct pci_class pci_interface_usb[] = { 389 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 390 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 391 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 392 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 393 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 394 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 395 { NULL, 0, NULL, }, 396 }; 397 398 /* IPMI programming interface */ 399 static const struct pci_class pci_interface_ipmi[] = { 400 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 401 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 402 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 403 { NULL, 0, NULL,}, 404 }; 405 406 /* Subclasses */ 407 static const struct pci_class pci_subclass_serialbus[] = { 408 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 409 pci_interface_ieee1394, }, 410 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 411 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 412 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 413 pci_interface_usb, }, 414 /* XXX Fiber Channel/_FIBRECHANNEL */ 415 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 416 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 417 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 418 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 419 pci_interface_ipmi, }, 420 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 421 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 422 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 423 { NULL, 0, NULL, }, 424 }; 425 426 /* 427 * Class 0x0d. 428 * Wireless Controller. 429 */ 430 static const struct pci_class pci_subclass_wireless[] = { 431 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 432 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 433 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 434 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 435 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 436 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 437 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 438 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 439 { NULL, 0, NULL, }, 440 }; 441 442 /* 443 * Class 0x0e. 444 * Intelligent IO controller. 445 */ 446 447 /* Intelligent IO programming interface */ 448 static const struct pci_class pci_interface_i2o[] = { 449 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 450 { NULL, 0, NULL,}, 451 }; 452 453 /* Subclasses */ 454 static const struct pci_class pci_subclass_i2o[] = { 455 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 456 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 457 { NULL, 0, NULL, }, 458 }; 459 460 /* 461 * Class 0x0f. 462 * Satellite communication controller. 463 */ 464 static const struct pci_class pci_subclass_satcom[] = { 465 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 466 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 467 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 468 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 469 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 470 { NULL, 0, NULL, }, 471 }; 472 473 /* 474 * Class 0x10. 475 * Encryption/Decryption controller. 476 */ 477 static const struct pci_class pci_subclass_crypto[] = { 478 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 479 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 480 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 481 { NULL, 0, NULL, }, 482 }; 483 484 /* 485 * Class 0x11. 486 * Data aquuisition and signal processing controller. 487 */ 488 static const struct pci_class pci_subclass_dasp[] = { 489 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 490 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 491 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 492 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 493 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 494 { NULL, 0, NULL, }, 495 }; 496 497 /* List of classes */ 498 static const struct pci_class pci_class[] = { 499 { "prehistoric", PCI_CLASS_PREHISTORIC, 500 pci_subclass_prehistoric, }, 501 { "mass storage", PCI_CLASS_MASS_STORAGE, 502 pci_subclass_mass_storage, }, 503 { "network", PCI_CLASS_NETWORK, 504 pci_subclass_network, }, 505 { "display", PCI_CLASS_DISPLAY, 506 pci_subclass_display, }, 507 { "multimedia", PCI_CLASS_MULTIMEDIA, 508 pci_subclass_multimedia, }, 509 { "memory", PCI_CLASS_MEMORY, 510 pci_subclass_memory, }, 511 { "bridge", PCI_CLASS_BRIDGE, 512 pci_subclass_bridge, }, 513 { "communications", PCI_CLASS_COMMUNICATIONS, 514 pci_subclass_communications, }, 515 { "system", PCI_CLASS_SYSTEM, 516 pci_subclass_system, }, 517 { "input", PCI_CLASS_INPUT, 518 pci_subclass_input, }, 519 { "dock", PCI_CLASS_DOCK, 520 pci_subclass_dock, }, 521 { "processor", PCI_CLASS_PROCESSOR, 522 pci_subclass_processor, }, 523 { "serial bus", PCI_CLASS_SERIALBUS, 524 pci_subclass_serialbus, }, 525 { "wireless", PCI_CLASS_WIRELESS, 526 pci_subclass_wireless, }, 527 { "I2O", PCI_CLASS_I2O, 528 pci_subclass_i2o, }, 529 { "satellite comm", PCI_CLASS_SATCOM, 530 pci_subclass_satcom, }, 531 { "crypto", PCI_CLASS_CRYPTO, 532 pci_subclass_crypto, }, 533 { "DASP", PCI_CLASS_DASP, 534 pci_subclass_dasp, }, 535 { "undefined", PCI_CLASS_UNDEFINED, 536 NULL, }, 537 { NULL, 0, 538 NULL, }, 539 }; 540 541 void pci_load_verbose(void); 542 543 #if defined(_KERNEL) 544 /* 545 * In kernel, these routines are provided and linked via the 546 * pciverbose module. 547 */ 548 const char *pci_findvendor_stub(pcireg_t); 549 const char *pci_findproduct_stub(pcireg_t); 550 551 const char *(*pci_findvendor)(pcireg_t) = pci_findvendor_stub; 552 const char *(*pci_findproduct)(pcireg_t) = pci_findproduct_stub; 553 const char *pci_unmatched = ""; 554 #else 555 /* 556 * For userland we just set the vectors here. 557 */ 558 const char *(*pci_findvendor)(pcireg_t id_reg) = pci_findvendor_real; 559 const char *(*pci_findproduct)(pcireg_t id_reg) = pci_findproduct_real; 560 const char *pci_unmatched = "unmatched "; 561 #endif 562 563 int pciverbose_loaded = 0; 564 565 #if defined(_KERNEL) 566 /* 567 * Routine to load the pciverbose kernel module as needed 568 */ 569 void 570 pci_load_verbose(void) 571 { 572 573 if (pciverbose_loaded == 0) 574 module_autoload("pciverbose", MODULE_CLASS_MISC); 575 } 576 577 const char * 578 pci_findvendor_stub(pcireg_t id_reg) 579 { 580 581 pci_load_verbose(); 582 if (pciverbose_loaded) 583 return pci_findvendor(id_reg); 584 else 585 return NULL; 586 } 587 588 const char * 589 pci_findproduct_stub(pcireg_t id_reg) 590 { 591 592 pci_load_verbose(); 593 if (pciverbose_loaded) 594 return pci_findproduct(id_reg); 595 else 596 return NULL; 597 } 598 #endif 599 600 void 601 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 602 size_t l) 603 { 604 pci_vendor_id_t vendor; 605 pci_product_id_t product; 606 pci_class_t class; 607 pci_subclass_t subclass; 608 pci_interface_t interface; 609 pci_revision_t revision; 610 const char *unmatched = pci_unmatched; 611 const char *vendor_namep, *product_namep; 612 const struct pci_class *classp, *subclassp, *interfacep; 613 char *ep; 614 615 ep = cp + l; 616 617 vendor = PCI_VENDOR(id_reg); 618 product = PCI_PRODUCT(id_reg); 619 620 class = PCI_CLASS(class_reg); 621 subclass = PCI_SUBCLASS(class_reg); 622 interface = PCI_INTERFACE(class_reg); 623 revision = PCI_REVISION(class_reg); 624 625 vendor_namep = pci_findvendor(id_reg); 626 product_namep = pci_findproduct(id_reg); 627 628 classp = pci_class; 629 while (classp->name != NULL) { 630 if (class == classp->val) 631 break; 632 classp++; 633 } 634 635 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 636 while (subclassp && subclassp->name != NULL) { 637 if (subclass == subclassp->val) 638 break; 639 subclassp++; 640 } 641 642 interfacep = (subclassp && subclassp->name != NULL) ? 643 subclassp->subclasses : NULL; 644 while (interfacep && interfacep->name != NULL) { 645 if (interface == interfacep->val) 646 break; 647 interfacep++; 648 } 649 650 if (vendor_namep == NULL) 651 cp += snprintf(cp, ep - cp, "%svendor 0x%04x product 0x%04x", 652 unmatched, vendor, product); 653 else if (product_namep != NULL) 654 cp += snprintf(cp, ep - cp, "%s %s", vendor_namep, 655 product_namep); 656 else 657 cp += snprintf(cp, ep - cp, "%s product 0x%04x", 658 vendor_namep, product); 659 if (showclass) { 660 cp += snprintf(cp, ep - cp, " ("); 661 if (classp->name == NULL) 662 cp += snprintf(cp, ep - cp, 663 "class 0x%02x, subclass 0x%02x", class, subclass); 664 else { 665 if (subclassp == NULL || subclassp->name == NULL) 666 cp += snprintf(cp, ep - cp, 667 "%s, subclass 0x%02x", 668 classp->name, subclass); 669 else 670 cp += snprintf(cp, ep - cp, "%s %s", 671 subclassp->name, classp->name); 672 } 673 if ((interfacep == NULL) || (interfacep->name == NULL)) { 674 if (interface != 0) 675 cp += snprintf(cp, ep - cp, 676 ", interface 0x%02x", interface); 677 } else if (strncmp(interfacep->name, "", 1) != 0) 678 cp += snprintf(cp, ep - cp, ", %s", 679 interfacep->name); 680 if (revision != 0) 681 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 682 revision); 683 cp += snprintf(cp, ep - cp, ")"); 684 } 685 } 686 687 #ifdef _KERNEL 688 void 689 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 690 const char *known, int addrev) 691 { 692 char devinfo[256]; 693 694 if (known) { 695 aprint_normal(": %s", known); 696 if (addrev) 697 aprint_normal(" (rev. 0x%02x)", 698 PCI_REVISION(pa->pa_class)); 699 aprint_normal("\n"); 700 } else { 701 pci_devinfo(pa->pa_id, pa->pa_class, 0, 702 devinfo, sizeof(devinfo)); 703 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 704 PCI_REVISION(pa->pa_class)); 705 } 706 if (naive) 707 aprint_naive(": %s\n", naive); 708 else 709 aprint_naive("\n"); 710 } 711 #endif 712 713 /* 714 * Print out most of the PCI configuration registers. Typically used 715 * in a device attach routine like this: 716 * 717 * #ifdef MYDEV_DEBUG 718 * printf("%s: ", device_xname(sc->sc_dev)); 719 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 720 * #endif 721 */ 722 723 #define i2o(i) ((i) * 4) 724 #define o2i(o) ((o) / 4) 725 #define onoff2(str, rval, bit, onstr, offstr) \ 726 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 727 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 728 729 static void 730 pci_conf_print_common( 731 #ifdef _KERNEL 732 pci_chipset_tag_t pc, pcitag_t tag, 733 #endif 734 const pcireg_t *regs) 735 { 736 const char *name; 737 const struct pci_class *classp, *subclassp; 738 pcireg_t rval; 739 unsigned int num; 740 741 rval = regs[o2i(PCI_ID_REG)]; 742 name = pci_findvendor(rval); 743 if (name) 744 printf(" Vendor Name: %s (0x%04x)\n", name, 745 PCI_VENDOR(rval)); 746 else 747 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 748 name = pci_findproduct(rval); 749 if (name) 750 printf(" Device Name: %s (0x%04x)\n", name, 751 PCI_PRODUCT(rval)); 752 else 753 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 754 755 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 756 757 printf(" Command register: 0x%04x\n", rval & 0xffff); 758 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 759 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 760 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 761 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 762 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 763 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 764 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 765 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 766 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 767 onoff("Fast back-to-back transactions", rval, 768 PCI_COMMAND_BACKTOBACK_ENABLE); 769 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 770 771 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 772 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 773 "inactive"); 774 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 775 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 776 onoff("User Definable Features (UDF) support", rval, 777 PCI_STATUS_UDF_SUPPORT); 778 onoff("Fast back-to-back capable", rval, 779 PCI_STATUS_BACKTOBACK_SUPPORT); 780 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 781 782 printf(" DEVSEL timing: "); 783 switch (rval & PCI_STATUS_DEVSEL_MASK) { 784 case PCI_STATUS_DEVSEL_FAST: 785 printf("fast"); 786 break; 787 case PCI_STATUS_DEVSEL_MEDIUM: 788 printf("medium"); 789 break; 790 case PCI_STATUS_DEVSEL_SLOW: 791 printf("slow"); 792 break; 793 default: 794 printf("unknown/reserved"); /* XXX */ 795 break; 796 } 797 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 798 799 onoff("Slave signaled Target Abort", rval, 800 PCI_STATUS_TARGET_TARGET_ABORT); 801 onoff("Master received Target Abort", rval, 802 PCI_STATUS_MASTER_TARGET_ABORT); 803 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 804 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 805 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 806 807 rval = regs[o2i(PCI_CLASS_REG)]; 808 for (classp = pci_class; classp->name != NULL; classp++) { 809 if (PCI_CLASS(rval) == classp->val) 810 break; 811 } 812 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 813 while (subclassp && subclassp->name != NULL) { 814 if (PCI_SUBCLASS(rval) == subclassp->val) 815 break; 816 subclassp++; 817 } 818 if (classp->name != NULL) { 819 printf(" Class Name: %s (0x%02x)\n", classp->name, 820 PCI_CLASS(rval)); 821 if (subclassp != NULL && subclassp->name != NULL) 822 printf(" Subclass Name: %s (0x%02x)\n", 823 subclassp->name, PCI_SUBCLASS(rval)); 824 else 825 printf(" Subclass ID: 0x%02x\n", 826 PCI_SUBCLASS(rval)); 827 } else { 828 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 829 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 830 } 831 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 832 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 833 834 rval = regs[o2i(PCI_BHLC_REG)]; 835 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 836 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 837 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 838 PCI_HDRTYPE(rval)); 839 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 840 num = PCI_CACHELINE(rval); 841 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 842 } 843 844 static int 845 pci_conf_print_bar( 846 #ifdef _KERNEL 847 pci_chipset_tag_t pc, pcitag_t tag, 848 #endif 849 const pcireg_t *regs, int reg, const char *name 850 #ifdef _KERNEL 851 , int sizebar 852 #endif 853 ) 854 { 855 int width; 856 pcireg_t rval, rval64h; 857 #ifdef _KERNEL 858 int s; 859 pcireg_t mask, mask64h; 860 #endif 861 862 width = 4; 863 864 /* 865 * Section 6.2.5.1, `Address Maps', tells us that: 866 * 867 * 1) The builtin software should have already mapped the 868 * device in a reasonable way. 869 * 870 * 2) A device which wants 2^n bytes of memory will hardwire 871 * the bottom n bits of the address to 0. As recommended, 872 * we write all 1s and see what we get back. 873 */ 874 875 rval = regs[o2i(reg)]; 876 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 877 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 878 rval64h = regs[o2i(reg + 4)]; 879 width = 8; 880 } else 881 rval64h = 0; 882 883 #ifdef _KERNEL 884 /* XXX don't size unknown memory type? */ 885 if (rval != 0 && sizebar) { 886 /* 887 * The following sequence seems to make some devices 888 * (e.g. host bus bridges, which don't normally 889 * have their space mapped) very unhappy, to 890 * the point of crashing the system. 891 * 892 * Therefore, if the mapping register is zero to 893 * start out with, don't bother trying. 894 */ 895 s = splhigh(); 896 pci_conf_write(pc, tag, reg, 0xffffffff); 897 mask = pci_conf_read(pc, tag, reg); 898 pci_conf_write(pc, tag, reg, rval); 899 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 900 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 901 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 902 mask64h = pci_conf_read(pc, tag, reg + 4); 903 pci_conf_write(pc, tag, reg + 4, rval64h); 904 } else 905 mask64h = 0; 906 splx(s); 907 } else 908 mask = mask64h = 0; 909 #endif /* _KERNEL */ 910 911 printf(" Base address register at 0x%02x", reg); 912 if (name) 913 printf(" (%s)", name); 914 printf("\n "); 915 if (rval == 0) { 916 printf("not implemented(?)\n"); 917 return width; 918 } 919 printf("type: "); 920 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 921 const char *type, *prefetch; 922 923 switch (PCI_MAPREG_MEM_TYPE(rval)) { 924 case PCI_MAPREG_MEM_TYPE_32BIT: 925 type = "32-bit"; 926 break; 927 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 928 type = "32-bit-1M"; 929 break; 930 case PCI_MAPREG_MEM_TYPE_64BIT: 931 type = "64-bit"; 932 break; 933 default: 934 type = "unknown (XXX)"; 935 break; 936 } 937 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 938 prefetch = ""; 939 else 940 prefetch = "non"; 941 printf("%s %sprefetchable memory\n", type, prefetch); 942 switch (PCI_MAPREG_MEM_TYPE(rval)) { 943 case PCI_MAPREG_MEM_TYPE_64BIT: 944 printf(" base: 0x%016llx, ", 945 PCI_MAPREG_MEM64_ADDR( 946 ((((long long) rval64h) << 32) | rval))); 947 #ifdef _KERNEL 948 if (sizebar) 949 printf("size: 0x%016llx", 950 PCI_MAPREG_MEM64_SIZE( 951 ((((long long) mask64h) << 32) | mask))); 952 else 953 #endif /* _KERNEL */ 954 printf("not sized"); 955 printf("\n"); 956 break; 957 case PCI_MAPREG_MEM_TYPE_32BIT: 958 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 959 default: 960 printf(" base: 0x%08x, ", 961 PCI_MAPREG_MEM_ADDR(rval)); 962 #ifdef _KERNEL 963 if (sizebar) 964 printf("size: 0x%08x", 965 PCI_MAPREG_MEM_SIZE(mask)); 966 else 967 #endif /* _KERNEL */ 968 printf("not sized"); 969 printf("\n"); 970 break; 971 } 972 } else { 973 #ifdef _KERNEL 974 if (sizebar) 975 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 976 #endif /* _KERNEL */ 977 printf("i/o\n"); 978 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 979 #ifdef _KERNEL 980 if (sizebar) 981 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 982 else 983 #endif /* _KERNEL */ 984 printf("not sized"); 985 printf("\n"); 986 } 987 988 return width; 989 } 990 991 static void 992 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 993 { 994 int off, needaddr, neednl; 995 996 needaddr = 1; 997 neednl = 0; 998 for (off = first; off < pastlast; off += 4) { 999 if ((off % 16) == 0 || needaddr) { 1000 printf(" 0x%02x:", off); 1001 needaddr = 0; 1002 } 1003 printf(" 0x%08x", regs[o2i(off)]); 1004 neednl = 1; 1005 if ((off % 16) == 12) { 1006 printf("\n"); 1007 neednl = 0; 1008 } 1009 } 1010 if (neednl) 1011 printf("\n"); 1012 } 1013 1014 static const char * 1015 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1016 { 1017 1018 switch ((caps >> 6) & 7) { 1019 case 0: return "self-powered"; 1020 case 1: return "55 mA"; 1021 case 2: return "100 mA"; 1022 case 3: return "160 mA"; 1023 case 4: return "220 mA"; 1024 case 5: return "270 mA"; 1025 case 6: return "320 mA"; 1026 case 7: 1027 default: return "375 mA"; 1028 } 1029 } 1030 1031 static const char * 1032 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1033 { 1034 static const char unk[] = "unknown"; 1035 static const char *pmrev[8] = { 1036 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1037 }; 1038 if (val > 7) 1039 return unk; 1040 return pmrev[val]; 1041 } 1042 1043 static void 1044 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1045 { 1046 uint16_t caps, pmcsr; 1047 pcireg_t reg; 1048 1049 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1050 reg = regs[o2i(capoff + PCI_PMCSR)]; 1051 pmcsr = reg & 0xffff; 1052 1053 printf("\n PCI Power Management Capabilities Register\n"); 1054 1055 printf(" Capabilities register: 0x%04x\n", caps); 1056 printf(" Version: %s\n", 1057 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1058 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1059 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1060 printf(" 3.3V auxiliary current: %s\n", 1061 pci_conf_print_pcipm_cap_aux(caps)); 1062 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1063 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1064 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1065 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1066 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1067 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1068 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1069 1070 printf(" Control/status register: 0x%04x\n", pmcsr); 1071 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1072 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1073 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1074 printf(" PME# assertion: %sabled\n", 1075 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1076 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1077 printf(" Bridge Support Extensions register: 0x%02x\n", 1078 (reg >> 16) & 0xff); 1079 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1080 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1081 printf(" Data register: 0x%02x\n", (reg >> 24) & 0xff); 1082 1083 } 1084 1085 /* XXX pci_conf_print_vpd_cap */ 1086 /* XXX pci_conf_print_slotid_cap */ 1087 1088 static void 1089 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1090 { 1091 uint32_t ctl, mmc, mme; 1092 1093 regs += o2i(capoff); 1094 ctl = *regs++; 1095 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1096 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1097 1098 printf("\n PCI Message Signaled Interrupt\n"); 1099 1100 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1101 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1102 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1103 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1104 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1105 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1106 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1107 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1108 printf(" Message Address %sregister: 0x%08x\n", 1109 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1110 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1111 printf(" Message Address %sregister: 0x%08x\n", 1112 "(upper) ", *regs++); 1113 } 1114 printf(" Message Data register: 0x%08x\n", *regs++); 1115 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1116 printf(" Vector Mask register: 0x%08x\n", *regs++); 1117 printf(" Vector Pending register: 0x%08x\n", *regs++); 1118 } 1119 } 1120 1121 /* XXX pci_conf_print_cpci_hostwap_cap */ 1122 1123 /* 1124 * For both command register and status register. 1125 * The argument "idx" is index number (0 to 7). 1126 */ 1127 static int 1128 pcix_split_trans(unsigned int idx) 1129 { 1130 static int table[8] = { 1131 1, 2, 3, 4, 8, 12, 16, 32 1132 }; 1133 1134 if (idx >= __arraycount(table)) 1135 return -1; 1136 return table[idx]; 1137 } 1138 1139 static void 1140 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1141 { 1142 pcireg_t reg; 1143 int isbridge; 1144 int i; 1145 1146 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1147 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1148 printf("\n PCI-X %s Capabilities Register\n", 1149 isbridge ? "Bridge" : "Non-bridge"); 1150 1151 reg = regs[o2i(capoff)]; 1152 if (isbridge != 0) { 1153 printf(" Secondary status register: 0x%04x\n", 1154 (reg & 0xffff0000) >> 16); 1155 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1156 onoff("133MHz capable", reg, PCIX_STATUS_133); 1157 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1158 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1159 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1160 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1161 printf(" Secondary clock frequency: 0x%x\n", 1162 (reg & PCIX_BRIDGE_2NDST_CLKF) 1163 >> PCIX_BRIDGE_2NDST_CLKF_SHIFT); 1164 printf(" Version: 0x%x\n", 1165 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1166 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1167 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1168 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1169 } else { 1170 printf(" Command register: 0x%04x\n", 1171 (reg & 0xffff0000) >> 16); 1172 onoff("Data Parity Error Recovery", reg, 1173 PCIX_CMD_PERR_RECOVER); 1174 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1175 printf(" Maximum Burst Read Count: %u\n", 1176 PCIX_CMD_BYTECNT(reg)); 1177 printf(" Maximum Split Transactions: %d\n", 1178 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1179 >> PCIX_CMD_SPLTRANS_SHIFT)); 1180 } 1181 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1182 printf(" %sStatus register: 0x%08x\n", 1183 isbridge ? "Bridge " : "", reg); 1184 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1185 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1186 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1187 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1188 onoff("133MHz capable", reg, PCIX_STATUS_133); 1189 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1190 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1191 if (isbridge != 0) { 1192 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1193 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1194 } else { 1195 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1196 "bridge device", "simple device"); 1197 printf(" Designed max memory read byte count: %d\n", 1198 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1199 >> PCIX_STATUS_MAXB_SHIFT)); 1200 printf(" Designed max outstanding split transaction: %d\n", 1201 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1202 >> PCIX_STATUS_MAXST_SHIFT)); 1203 printf(" MAX cumulative Read Size: %u\n", 1204 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1205 onoff("Received split completion error", reg, 1206 PCIX_STATUS_SCERR); 1207 } 1208 onoff("266MHz capable", reg, PCIX_STATUS_266); 1209 onoff("533MHz capable", reg, PCIX_STATUS_533); 1210 1211 if (isbridge == 0) 1212 return; 1213 1214 /* Only for bridge */ 1215 for (i = 0; i < 2; i++) { 1216 reg = regs[o2i(capoff+PCIX_BRIDGE_UP_STCR + (4 * i))]; 1217 printf(" %s split transaction control register: 0x%08x\n", 1218 (i == 0) ? "Upstream" : "Downstream", reg); 1219 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1220 printf(" Commitment Limit: %d\n", 1221 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1222 } 1223 } 1224 1225 /* XXX pci_conf_print_ldt_cap */ 1226 1227 static void 1228 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1229 { 1230 uint16_t caps; 1231 1232 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1233 1234 printf("\n PCI Vendor Specific Capabilities Register\n"); 1235 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1236 } 1237 1238 static void 1239 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1240 { 1241 pcireg_t val; 1242 1243 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1244 1245 printf("\n Debugport Capability Register\n"); 1246 printf(" Debug base Register: 0x%04x\n", 1247 val >> PCI_DEBUG_BASER_SHIFT); 1248 printf(" port offset: 0x%04x\n", 1249 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1250 printf(" BAR number: %u\n", 1251 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1252 } 1253 1254 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1255 /* XXX pci_conf_print_hotplug_cap */ 1256 1257 static void 1258 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1259 { 1260 pcireg_t reg; 1261 1262 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1263 1264 printf("\n Subsystem ID Capability Register\n"); 1265 printf(" Subsystem ID : 0x%08x\n", reg); 1266 } 1267 1268 /* XXX pci_conf_print_agp8_cap */ 1269 /* XXX pci_conf_print_secure_cap */ 1270 1271 static void 1272 pci_print_pcie_L0s_latency(uint32_t val) 1273 { 1274 1275 switch (val) { 1276 case 0x0: 1277 printf("Less than 64ns\n"); 1278 break; 1279 case 0x1: 1280 case 0x2: 1281 case 0x3: 1282 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1283 break; 1284 case 0x4: 1285 printf("512ns to less than 1us\n"); 1286 break; 1287 case 0x5: 1288 printf("1us to less than 2us\n"); 1289 break; 1290 case 0x6: 1291 printf("2us - 4us\n"); 1292 break; 1293 case 0x7: 1294 printf("More than 4us\n"); 1295 break; 1296 } 1297 } 1298 1299 static void 1300 pci_print_pcie_L1_latency(uint32_t val) 1301 { 1302 1303 switch (val) { 1304 case 0x0: 1305 printf("Less than 1us\n"); 1306 break; 1307 case 0x6: 1308 printf("32us - 64us\n"); 1309 break; 1310 case 0x7: 1311 printf("More than 64us\n"); 1312 break; 1313 default: 1314 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1315 break; 1316 } 1317 } 1318 1319 static void 1320 pci_print_pcie_compl_timeout(uint32_t val) 1321 { 1322 1323 switch (val) { 1324 case 0x0: 1325 printf("50us to 50ms\n"); 1326 break; 1327 case 0x5: 1328 printf("16ms to 55ms\n"); 1329 break; 1330 case 0x6: 1331 printf("65ms to 210ms\n"); 1332 break; 1333 case 0x9: 1334 printf("260ms to 900ms\n"); 1335 break; 1336 case 0xa: 1337 printf("1s to 3.5s\n"); 1338 break; 1339 default: 1340 printf("unknown %u value\n", val); 1341 break; 1342 } 1343 } 1344 1345 static void 1346 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1347 { 1348 pcireg_t reg; /* for each register */ 1349 pcireg_t val; /* for each bitfield */ 1350 bool check_link = false; 1351 bool check_slot = false; 1352 bool check_rootport = false; 1353 unsigned int pciever; 1354 static const char * const linkspeeds[] = {"2.5", "5.0", "8.0"}; 1355 int i; 1356 1357 printf("\n PCI Express Capabilities Register\n"); 1358 /* Capability Register */ 1359 reg = regs[o2i(capoff)]; 1360 printf(" Capability register: %04x\n", reg >> 16); 1361 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1362 printf(" Capability version: %u\n", pciever); 1363 printf(" Device type: "); 1364 switch ((reg & 0x00f00000) >> 20) { 1365 case 0x0: 1366 printf("PCI Express Endpoint device\n"); 1367 check_link = true; 1368 break; 1369 case 0x1: 1370 printf("Legacy PCI Express Endpoint device\n"); 1371 check_link = true; 1372 break; 1373 case 0x4: 1374 printf("Root Port of PCI Express Root Complex\n"); 1375 check_link = true; 1376 check_slot = true; 1377 check_rootport = true; 1378 break; 1379 case 0x5: 1380 printf("Upstream Port of PCI Express Switch\n"); 1381 break; 1382 case 0x6: 1383 printf("Downstream Port of PCI Express Switch\n"); 1384 check_slot = true; 1385 check_rootport = true; 1386 break; 1387 case 0x7: 1388 printf("PCI Express to PCI/PCI-X Bridge\n"); 1389 break; 1390 case 0x8: 1391 printf("PCI/PCI-X to PCI Express Bridge\n"); 1392 break; 1393 case 0x9: 1394 printf("Root Complex Integrated Endpoint\n"); 1395 break; 1396 case 0xa: 1397 check_rootport = true; 1398 printf("Root Complex Event Collector\n"); 1399 break; 1400 default: 1401 printf("unknown\n"); 1402 break; 1403 } 1404 if (check_slot && (reg & PCIE_XCAP_SI) != 0) 1405 printf(" Slot implemented\n"); 1406 printf(" Interrupt Message Number: %x\n", 1407 (unsigned int)((reg & PCIE_XCAP_IRQ) >> 27)); 1408 1409 /* Device Capability Register */ 1410 reg = regs[o2i(capoff + PCIE_DCAP)]; 1411 printf(" Device Capabilities Register: 0x%08x\n", reg); 1412 printf(" Max Payload Size Supported: %u bytes max\n", 1413 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1414 printf(" Phantom Functions Supported: "); 1415 switch ((reg & PCIE_DCAP_PHANTOM_FUNCS) >> 3) { 1416 case 0x0: 1417 printf("not available\n"); 1418 break; 1419 case 0x1: 1420 printf("MSB\n"); 1421 break; 1422 case 0x2: 1423 printf("two MSB\n"); 1424 break; 1425 case 0x3: 1426 printf("All three bits\n"); 1427 break; 1428 } 1429 printf(" Extended Tag Field Supported: %dbit\n", 1430 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1431 printf(" Endpoint L0 Acceptable Latency: "); 1432 pci_print_pcie_L0s_latency((reg & PCIE_DCAP_L0S_LATENCY) >> 6); 1433 printf(" Endpoint L1 Acceptable Latency: "); 1434 pci_print_pcie_L1_latency((reg & PCIE_DCAP_L1_LATENCY) >> 9); 1435 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1436 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1437 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1438 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1439 printf(" Captured Slot Power Limit Value: %d\n", 1440 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18); 1441 printf(" Captured Slot Power Limit Scale: %d\n", 1442 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26); 1443 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1444 1445 /* Device Control Register */ 1446 reg = regs[o2i(capoff + PCIE_DCSR)]; 1447 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1448 onoff("Correctable Error Reporting Enable", reg, 1449 PCIE_DCSR_ENA_COR_ERR); 1450 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1451 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1452 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1453 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1454 printf(" Max Payload Size: %d byte\n", 1455 128 << (((unsigned int)(reg & PCIE_DCSR_MAX_PAYLOAD) >> 5))); 1456 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1457 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1458 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1459 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1460 printf(" Max Read Request Size: %d byte\n", 1461 128 << ((unsigned int)(reg & PCIE_DCSR_MAX_READ_REQ) >> 12)); 1462 1463 /* Device Status Register */ 1464 reg = regs[o2i(capoff + PCIE_DCSR)]; 1465 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1466 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1467 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1468 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1469 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1470 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1471 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1472 1473 if (check_link) { 1474 /* Link Capability Register */ 1475 reg = regs[o2i(capoff + PCIE_LCAP)]; 1476 printf(" Link Capabilities Register: 0x%08x\n", reg); 1477 printf(" Maximum Link Speed: "); 1478 val = reg & PCIE_LCAP_MAX_SPEED; 1479 if (val < 1 || val > 3) { 1480 printf("unknown %u value\n", val); 1481 } else { 1482 printf("%sGT/s\n", linkspeeds[val - 1]); 1483 } 1484 printf(" Maximum Link Width: x%u lanes\n", 1485 (unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4); 1486 printf(" Active State PM Support: "); 1487 val = (reg & PCIE_LCAP_ASPM) >> 10; 1488 switch (val) { 1489 case 0x1: 1490 printf("L0s Entry supported\n"); 1491 break; 1492 case 0x3: 1493 printf("L0s and L1 supported\n"); 1494 break; 1495 default: 1496 printf("Reserved value\n"); 1497 break; 1498 } 1499 printf(" L0 Exit Latency: "); 1500 pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12); 1501 printf(" L1 Exit Latency: "); 1502 pci_print_pcie_L1_latency((reg & PCIE_LCAP_L1_EXIT) >> 15); 1503 printf(" Port Number: %u\n", reg >> 24); 1504 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1505 onoff("Surprise Down Error Report", reg, 1506 PCIE_LCAP_SURPRISE_DOWN); 1507 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1508 onoff("Link BW Notification Capable", reg, 1509 PCIE_LCAP_LINK_BW_NOTIFY); 1510 onoff("ASPM Optionally Compliance", reg, 1511 PCIE_LCAP_ASPM_COMPLIANCE); 1512 1513 /* Link Control Register */ 1514 reg = regs[o2i(capoff + PCIE_LCSR)]; 1515 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1516 printf(" Active State PM Control: "); 1517 val = reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S); 1518 switch (val) { 1519 case 0: 1520 printf("disabled\n"); 1521 break; 1522 case 1: 1523 printf("L0s Entry Enabled\n"); 1524 break; 1525 case 2: 1526 printf("L1 Entry Enabled\n"); 1527 break; 1528 case 3: 1529 printf("L0s and L1 Entry Enabled\n"); 1530 break; 1531 } 1532 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1533 "128bytes", "64bytes"); 1534 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1535 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1536 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1537 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1538 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1539 onoff("Hardware Autonomous Width Disable", reg, 1540 PCIE_LCSR_HAWD); 1541 onoff("Link Bandwidth Management Interrupt Enable", reg, 1542 PCIE_LCSR_LBMIE); 1543 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1544 PCIE_LCSR_LABIE); 1545 1546 /* Link Status Register */ 1547 reg = regs[o2i(capoff + PCIE_LCSR)]; 1548 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1549 printf(" Negotiated Link Speed: "); 1550 if (((reg >> 16) & 0x000f) < 1 || 1551 ((reg >> 16) & 0x000f) > 3) { 1552 printf("unknown %u value\n", 1553 (unsigned int)(reg & PCIE_LCSR_LINKSPEED) >> 16); 1554 } else { 1555 printf("%sGT/s\n", 1556 linkspeeds[((reg & PCIE_LCSR_LINKSPEED) >> 16)-1]); 1557 } 1558 printf(" Negotiated Link Width: x%u lanes\n", 1559 (reg >> 20) & 0x003f); 1560 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1561 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1562 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1563 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1564 onoff("Link Bandwidth Management Status", reg, 1565 PCIE_LCSR_LINK_BW_MGMT); 1566 onoff("Link Autonomous Bandwidth Status", reg, 1567 PCIE_LCSR_LINK_AUTO_BW); 1568 } 1569 1570 if (check_slot == true) { 1571 /* Slot Capability Register */ 1572 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1573 printf(" Slot Capability Register: %08x\n", reg); 1574 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1575 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1576 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1577 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1578 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1579 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1580 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1581 printf(" Slot Power Limit Value: %d\n", 1582 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1583 printf(" Slot Power Limit Scale: %d\n", 1584 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1585 onoff("Electromechanical Interlock Present", reg, 1586 PCIE_SLCAP_EIP); 1587 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1588 printf(" Physical Slot Number: %d\n", 1589 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1590 1591 /* Slot Control Register */ 1592 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1593 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1594 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1595 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1596 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1597 onoff("Presense Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1598 onoff("Command Completed Interrupt Enabled", reg, 1599 PCIE_SLCSR_CCE); 1600 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1601 printf(" Attention Indicator Control: "); 1602 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1603 case 0x0: 1604 printf("reserved\n"); 1605 break; 1606 case 0x1: 1607 printf("on\n"); 1608 break; 1609 case 0x2: 1610 printf("blink\n"); 1611 break; 1612 case 0x3: 1613 printf("off\n"); 1614 break; 1615 } 1616 printf(" Power Indicator Control: "); 1617 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1618 case 0x0: 1619 printf("reserved\n"); 1620 break; 1621 case 0x1: 1622 printf("on\n"); 1623 break; 1624 case 0x2: 1625 printf("blink\n"); 1626 break; 1627 case 0x3: 1628 printf("off\n"); 1629 break; 1630 } 1631 onoff("Power Controller Control", reg, PCIE_SLCSR_PCC); 1632 onoff("Electromechanical Interlock Control", 1633 reg, PCIE_SLCSR_EIC); 1634 onoff("Data Link Layer State Changed Enable", reg, 1635 PCIE_SLCSR_DLLSCE); 1636 1637 /* Slot Status Register */ 1638 printf(" Slot Status Register: %04x\n", reg >> 16); 1639 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1640 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1641 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1642 onoff("Presense Detect Changed", reg, PCIE_SLCSR_PDC); 1643 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1644 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1645 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1646 onoff("Electromechanical Interlock engaged", reg, 1647 PCIE_SLCSR_EIS); 1648 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 1649 } 1650 1651 if (check_rootport == true) { 1652 /* Root Control Register */ 1653 reg = regs[o2i(capoff + PCIE_RCR)]; 1654 printf(" Root Control Register: %04x\n", reg & 0xffff); 1655 onoff("SERR on Correctable Error Enable", reg, 1656 PCIE_RCR_SERR_CER); 1657 onoff("SERR on Non-Fatal Error Enable", reg, 1658 PCIE_RCR_SERR_NFER); 1659 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 1660 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 1661 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 1662 1663 /* Root Capability Register */ 1664 printf(" Root Capability Register: %04x\n", 1665 reg >> 16); 1666 1667 /* Root Status Register */ 1668 reg = regs[o2i(capoff + PCIE_RSR)]; 1669 printf(" Root Status Register: %08x\n", reg); 1670 printf(" PME Requester ID: %04x\n", 1671 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1672 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 1673 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 1674 } 1675 1676 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1677 if (pciever < 2) 1678 return; 1679 1680 /* Device Capabilities 2 */ 1681 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1682 printf(" Device Capabilities 2: 0x%08x\n", reg); 1683 printf(" Completion Timeout Ranges Supported: %u \n", 1684 (unsigned int)(reg & PCIE_DCAP2_COMPT_RANGE)); 1685 onoff("Completion Timeout Disable Supported", reg, 1686 PCIE_DCAP2_COMPT_DIS); 1687 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 1688 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 1689 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 1690 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 1691 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 1692 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 1693 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 1694 printf(" TPH Completer Supported: %u\n", 1695 (unsigned int)(reg & PCIE_DCAP2_TPH_COMP) >> 12); 1696 printf(" OBFF Supported: "); 1697 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 1698 case 0x0: 1699 printf("Not supported\n"); 1700 break; 1701 case 0x1: 1702 printf("Message only\n"); 1703 break; 1704 case 0x2: 1705 printf("WAKE# only\n"); 1706 break; 1707 case 0x3: 1708 printf("Both\n"); 1709 break; 1710 } 1711 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 1712 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 1713 printf(" Max End-End TLP Prefixes: %u\n", 1714 (unsigned int)(reg & PCIE_DCAP2_MAX_EETLP) >> 22); 1715 1716 /* Device Control 2 */ 1717 reg = regs[o2i(capoff + PCIE_DCSR2)]; 1718 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 1719 printf(" Completion Timeout Value: "); 1720 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 1721 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 1722 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 1723 onoff("AtomicOp Rquester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 1724 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 1725 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 1726 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 1727 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 1728 printf(" OBFF: "); 1729 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 1730 case 0x0: 1731 printf("Disabled\n"); 1732 break; 1733 case 0x1: 1734 printf("Enabled with Message Signaling Variation A\n"); 1735 break; 1736 case 0x2: 1737 printf("Enabled with Message Signaling Variation B\n"); 1738 break; 1739 case 0x3: 1740 printf("Enabled using WAKE# signaling\n"); 1741 break; 1742 } 1743 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 1744 1745 if (check_link) { 1746 /* Link Capability 2 */ 1747 reg = regs[o2i(capoff + PCIE_LCAP2)]; 1748 printf(" Link Capabilities 2: 0x%08x\n", reg); 1749 val = (reg & PCIE_LCAP2_SUP_LNKSV) >> 1; 1750 printf(" Supported Link Speed Vector:"); 1751 for (i = 0; i <= 2; i++) { 1752 if (((val >> i) & 0x01) != 0) 1753 printf(" %sGT/s", linkspeeds[i]); 1754 } 1755 printf("\n"); 1756 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 1757 1758 /* Link Control 2 */ 1759 reg = regs[o2i(capoff + PCIE_LCSR2)]; 1760 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 1761 printf(" Target Link Speed: "); 1762 val = reg & PCIE_LCSR2_TGT_LSPEED; 1763 if (val < 1 || val > 3) 1764 printf("unknown %u value\n", val); 1765 else 1766 printf("%sGT/s\n", linkspeeds[val - 1]); 1767 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 1768 onoff("HW Autonomous Speed Disabled", reg, 1769 PCIE_LCSR2_HW_AS_DIS); 1770 onoff("Selectable De-emphasis", reg, PCIE_LCSR2_SEL_DEEMP); 1771 printf(" Transmit Margin: %u\n", 1772 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 1773 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 1774 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 1775 printf(" Compliance Present/De-emphasis: %u\n", 1776 (unsigned int)(reg & PCIE_LCSR2_COMP_DEEMP) >> 12); 1777 1778 /* Link Status 2 */ 1779 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 1780 onoff("Current De-emphasis Level", reg, PCIE_LCSR2_DEEMP_LVL); 1781 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 1782 onoff("Equalization Phase 1 Successful", reg, 1783 PCIE_LCSR2_EQP1_SUC); 1784 onoff("Equalization Phase 2 Successful", reg, 1785 PCIE_LCSR2_EQP2_SUC); 1786 onoff("Equalization Phase 3 Successful", reg, 1787 PCIE_LCSR2_EQP3_SUC); 1788 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 1789 } 1790 1791 /* Slot Capability 2 */ 1792 /* Slot Control 2 */ 1793 /* Slot Status 2 */ 1794 } 1795 1796 static void 1797 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 1798 { 1799 pcireg_t reg; 1800 1801 printf("\n MSI-X Capability Register\n"); 1802 1803 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 1804 printf(" Message Control register: 0x%04x\n", 1805 (reg >> 16) & 0xff); 1806 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 1807 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 1808 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 1809 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 1810 printf(" Table offset register: 0x%08x\n", reg); 1811 printf(" Table offset: %08x\n", reg & PCI_MSIX_TBLOFFSET_MASK); 1812 printf(" BIR: 0x%x\n", reg & PCI_MSIX_TBLBIR_MASK); 1813 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 1814 printf(" Pending bit array register: 0x%08x\n", reg); 1815 printf(" Pending bit array offset: %08x\n", 1816 reg & PCI_MSIX_PBAOFFSET_MASK); 1817 printf(" BIR: 0x%x\n", reg & PCI_MSIX_PBABIR_MASK); 1818 } 1819 1820 /* XXX pci_conf_print_sata_cap */ 1821 static void 1822 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 1823 { 1824 pcireg_t reg; 1825 1826 printf("\n Advanced Features Capability Register\n"); 1827 1828 reg = regs[o2i(capoff + PCI_AFCAPR)]; 1829 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 1830 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 1831 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 1832 reg = regs[o2i(capoff + PCI_AFCSR)]; 1833 printf(" AF Control register: 0x%02x\n", reg & 0xff); 1834 /* 1835 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 1836 * and it's always 0 on read 1837 */ 1838 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 1839 onoff("Transaction Pending", reg, PCI_AFSR_TP); 1840 } 1841 1842 static void 1843 pci_conf_print_caplist( 1844 #ifdef _KERNEL 1845 pci_chipset_tag_t pc, pcitag_t tag, 1846 #endif 1847 const pcireg_t *regs, int capoff) 1848 { 1849 int off; 1850 pcireg_t rval; 1851 int pcie_off = -1, pcipm_off = -1, msi_off = -1, pcix_off = -1; 1852 int vendspec_off = -1, msix_off = -1; 1853 int debugport_off = -1, subsystem_off = -1, pciaf_off = -1; 1854 1855 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1856 off != 0; 1857 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 1858 rval = regs[o2i(off)]; 1859 printf(" Capability register at 0x%02x\n", off); 1860 1861 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 1862 switch (PCI_CAPLIST_CAP(rval)) { 1863 case PCI_CAP_RESERVED0: 1864 printf("reserved"); 1865 break; 1866 case PCI_CAP_PWRMGMT: 1867 printf("Power Management, rev. %s", 1868 pci_conf_print_pcipm_cap_pmrev( 1869 (rval >> 0) & 0x07)); 1870 pcipm_off = off; 1871 break; 1872 case PCI_CAP_AGP: 1873 printf("AGP, rev. %d.%d", 1874 PCI_CAP_AGP_MAJOR(rval), 1875 PCI_CAP_AGP_MINOR(rval)); 1876 break; 1877 case PCI_CAP_VPD: 1878 printf("VPD"); 1879 break; 1880 case PCI_CAP_SLOTID: 1881 printf("SlotID"); 1882 break; 1883 case PCI_CAP_MSI: 1884 printf("MSI"); 1885 msi_off = off; 1886 break; 1887 case PCI_CAP_CPCI_HOTSWAP: 1888 printf("CompactPCI Hot-swapping"); 1889 break; 1890 case PCI_CAP_PCIX: 1891 pcix_off = off; 1892 printf("PCI-X"); 1893 break; 1894 case PCI_CAP_LDT: 1895 printf("LDT"); 1896 break; 1897 case PCI_CAP_VENDSPEC: 1898 vendspec_off = off; 1899 printf("Vendor-specific"); 1900 break; 1901 case PCI_CAP_DEBUGPORT: 1902 printf("Debug Port"); 1903 debugport_off = off; 1904 break; 1905 case PCI_CAP_CPCI_RSRCCTL: 1906 printf("CompactPCI Resource Control"); 1907 break; 1908 case PCI_CAP_HOTPLUG: 1909 printf("Hot-Plug"); 1910 break; 1911 case PCI_CAP_SUBVENDOR: 1912 printf("Subsystem ID"); 1913 subsystem_off = off; 1914 break; 1915 case PCI_CAP_AGP8: 1916 printf("AGP 8x"); 1917 break; 1918 case PCI_CAP_SECURE: 1919 printf("Secure Device"); 1920 break; 1921 case PCI_CAP_PCIEXPRESS: 1922 printf("PCI Express"); 1923 pcie_off = off; 1924 break; 1925 case PCI_CAP_MSIX: 1926 printf("MSI-X"); 1927 msix_off = off; 1928 break; 1929 case PCI_CAP_SATA: 1930 printf("SATA"); 1931 break; 1932 case PCI_CAP_PCIAF: 1933 printf("Advanced Features"); 1934 pciaf_off = off; 1935 break; 1936 default: 1937 printf("unknown"); 1938 } 1939 printf(")\n"); 1940 } 1941 if (pcipm_off != -1) 1942 pci_conf_print_pcipm_cap(regs, pcipm_off); 1943 /* XXX AGP */ 1944 /* XXX VPD */ 1945 /* XXX SLOTID */ 1946 if (msi_off != -1) 1947 pci_conf_print_msi_cap(regs, msi_off); 1948 /* XXX CPCI_HOTSWAP */ 1949 if (pcix_off != -1) 1950 pci_conf_print_pcix_cap(regs, pcix_off); 1951 /* XXX LDT */ 1952 if (vendspec_off != -1) 1953 pci_conf_print_vendspec_cap(regs, vendspec_off); 1954 if (debugport_off != -1) 1955 pci_conf_print_debugport_cap(regs, debugport_off); 1956 /* XXX CPCI_RSRCCTL */ 1957 /* XXX HOTPLUG */ 1958 if (subsystem_off != -1) 1959 pci_conf_print_subsystem_cap(regs, subsystem_off); 1960 /* XXX AGP8 */ 1961 /* XXX SECURE */ 1962 if (pcie_off != -1) 1963 pci_conf_print_pcie_cap(regs, pcie_off); 1964 if (msix_off != -1) 1965 pci_conf_print_msix_cap(regs, msix_off); 1966 /* XXX SATA */ 1967 if (pciaf_off != -1) 1968 pci_conf_print_pciaf_cap(regs, pciaf_off); 1969 } 1970 1971 /* Print the Secondary Status Register. */ 1972 static void 1973 pci_conf_print_ssr(pcireg_t rval) 1974 { 1975 pcireg_t devsel; 1976 1977 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 1978 onoff("66 MHz capable", rval, __BIT(5)); 1979 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 1980 onoff("Fast back-to-back capable", rval, __BIT(7)); 1981 onoff("Data parity error detected", rval, __BIT(8)); 1982 1983 printf(" DEVSEL timing: "); 1984 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 1985 switch (devsel) { 1986 case 0: 1987 printf("fast"); 1988 break; 1989 case 1: 1990 printf("medium"); 1991 break; 1992 case 2: 1993 printf("slow"); 1994 break; 1995 default: 1996 printf("unknown/reserved"); /* XXX */ 1997 break; 1998 } 1999 printf(" (0x%x)\n", devsel); 2000 2001 onoff("Signalled target abort", rval, __BIT(11)); 2002 onoff("Received target abort", rval, __BIT(12)); 2003 onoff("Received master abort", rval, __BIT(13)); 2004 onoff("Received system error", rval, __BIT(14)); 2005 onoff("Detected parity error", rval, __BIT(15)); 2006 } 2007 2008 static void 2009 pci_conf_print_type0( 2010 #ifdef _KERNEL 2011 pci_chipset_tag_t pc, pcitag_t tag, 2012 #endif 2013 const pcireg_t *regs 2014 #ifdef _KERNEL 2015 , int sizebars 2016 #endif 2017 ) 2018 { 2019 int off, width; 2020 pcireg_t rval; 2021 2022 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 2023 #ifdef _KERNEL 2024 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 2025 #else 2026 width = pci_conf_print_bar(regs, off, NULL); 2027 #endif 2028 } 2029 2030 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 2031 2032 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 2033 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 2034 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 2035 2036 /* XXX */ 2037 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 2038 2039 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2040 printf(" Capability list pointer: 0x%02x\n", 2041 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 2042 else 2043 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 2044 2045 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 2046 2047 rval = regs[o2i(PCI_INTERRUPT_REG)]; 2048 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 2049 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 2050 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 2051 switch (PCI_INTERRUPT_PIN(rval)) { 2052 case PCI_INTERRUPT_PIN_NONE: 2053 printf("(none)"); 2054 break; 2055 case PCI_INTERRUPT_PIN_A: 2056 printf("(pin A)"); 2057 break; 2058 case PCI_INTERRUPT_PIN_B: 2059 printf("(pin B)"); 2060 break; 2061 case PCI_INTERRUPT_PIN_C: 2062 printf("(pin C)"); 2063 break; 2064 case PCI_INTERRUPT_PIN_D: 2065 printf("(pin D)"); 2066 break; 2067 default: 2068 printf("(? ? ?)"); 2069 break; 2070 } 2071 printf("\n"); 2072 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 2073 } 2074 2075 static void 2076 pci_conf_print_type1( 2077 #ifdef _KERNEL 2078 pci_chipset_tag_t pc, pcitag_t tag, 2079 #endif 2080 const pcireg_t *regs 2081 #ifdef _KERNEL 2082 , int sizebars 2083 #endif 2084 ) 2085 { 2086 int off, width; 2087 pcireg_t rval; 2088 uint32_t base, limit; 2089 uint32_t base_h, limit_h; 2090 uint64_t pbase, plimit; 2091 int use_upper; 2092 2093 /* 2094 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 2095 * Bridge chip documentation, and may not be correct with 2096 * respect to various standards. (XXX) 2097 */ 2098 2099 for (off = 0x10; off < 0x18; off += width) { 2100 #ifdef _KERNEL 2101 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 2102 #else 2103 width = pci_conf_print_bar(regs, off, NULL); 2104 #endif 2105 } 2106 2107 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 2108 printf(" Primary bus number: 0x%02x\n", 2109 PCI_BRIDGE_BUS_PRIMARY(rval)); 2110 printf(" Secondary bus number: 0x%02x\n", 2111 PCI_BRIDGE_BUS_SECONDARY(rval)); 2112 printf(" Subordinate bus number: 0x%02x\n", 2113 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 2114 printf(" Secondary bus latency timer: 0x%02x\n", 2115 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 2116 2117 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 2118 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 2119 2120 /* I/O region */ 2121 printf(" I/O region:\n"); 2122 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 2123 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 2124 if (PCI_BRIDGE_IO_32BITS(rval)) 2125 use_upper = 1; 2126 else 2127 use_upper = 0; 2128 onoff("32bit I/O", rval, use_upper); 2129 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 2130 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 2131 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 2132 limit |= 0x00000fff; 2133 2134 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 2135 base_h = (rval >> 0) & 0xffff; 2136 limit_h = (rval >> 16) & 0xffff; 2137 printf(" base upper 16 bits register: 0x%04x\n", base_h); 2138 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 2139 2140 if (use_upper == 1) { 2141 base |= base_h << 16; 2142 limit |= limit_h << 16; 2143 } 2144 if (base < limit) { 2145 if (use_upper == 1) 2146 printf(" range: 0x%08x-0x%08x\n", base, limit); 2147 else 2148 printf(" range: 0x%04x-0x%04x\n", base, limit); 2149 } else 2150 printf(" range: not set\n"); 2151 2152 /* Non-prefetchable memory region */ 2153 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 2154 printf(" Memory region:\n"); 2155 printf(" base register: 0x%04x\n", 2156 (rval >> 0) & 0xffff); 2157 printf(" limit register: 0x%04x\n", 2158 (rval >> 16) & 0xffff); 2159 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 2160 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 2161 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 2162 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 2163 if (base < limit) 2164 printf(" range: 0x%08x-0x%08x\n", base, limit); 2165 else 2166 printf(" range: not set\n"); 2167 2168 /* Prefetchable memory region */ 2169 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 2170 printf(" Prefetchable memory region:\n"); 2171 printf(" base register: 0x%04x\n", 2172 (rval >> 0) & 0xffff); 2173 printf(" limit register: 0x%04x\n", 2174 (rval >> 16) & 0xffff); 2175 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 2176 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 2177 printf(" base upper 32 bits register: 0x%08x\n", 2178 base_h); 2179 printf(" limit upper 32 bits register: 0x%08x\n", 2180 limit_h); 2181 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 2182 use_upper = 1; 2183 else 2184 use_upper = 0; 2185 onoff("64bit memory address", rval, use_upper); 2186 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 2187 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 2188 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 2189 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 2190 if (use_upper == 1) { 2191 pbase |= (uint64_t)base_h << 32; 2192 plimit |= (uint64_t)limit_h << 32; 2193 } 2194 if (pbase < plimit) { 2195 if (use_upper == 1) 2196 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 2197 "\n", pbase, plimit); 2198 else 2199 printf(" range: 0x%08x-0x%08x\n", 2200 (uint32_t)pbase, (uint32_t)plimit); 2201 } else 2202 printf(" range: not set\n"); 2203 2204 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2205 printf(" Capability list pointer: 0x%02x\n", 2206 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 2207 else 2208 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 2209 2210 /* XXX */ 2211 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 2212 2213 rval = regs[o2i(PCI_INTERRUPT_REG)]; 2214 printf(" Interrupt line: 0x%02x\n", 2215 (rval >> 0) & 0xff); 2216 printf(" Interrupt pin: 0x%02x ", 2217 (rval >> 8) & 0xff); 2218 switch ((rval >> 8) & 0xff) { 2219 case PCI_INTERRUPT_PIN_NONE: 2220 printf("(none)"); 2221 break; 2222 case PCI_INTERRUPT_PIN_A: 2223 printf("(pin A)"); 2224 break; 2225 case PCI_INTERRUPT_PIN_B: 2226 printf("(pin B)"); 2227 break; 2228 case PCI_INTERRUPT_PIN_C: 2229 printf("(pin C)"); 2230 break; 2231 case PCI_INTERRUPT_PIN_D: 2232 printf("(pin D)"); 2233 break; 2234 default: 2235 printf("(? ? ?)"); 2236 break; 2237 } 2238 printf("\n"); 2239 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 2240 & PCI_BRIDGE_CONTROL_MASK; 2241 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 2242 onoff("Parity error response", rval, 0x0001); 2243 onoff("Secondary SERR forwarding", rval, 0x0002); 2244 onoff("ISA enable", rval, 0x0004); 2245 onoff("VGA enable", rval, 0x0008); 2246 onoff("Master abort reporting", rval, 0x0020); 2247 onoff("Secondary bus reset", rval, 0x0040); 2248 onoff("Fast back-to-back capable", rval, 0x0080); 2249 } 2250 2251 static void 2252 pci_conf_print_type2( 2253 #ifdef _KERNEL 2254 pci_chipset_tag_t pc, pcitag_t tag, 2255 #endif 2256 const pcireg_t *regs 2257 #ifdef _KERNEL 2258 , int sizebars 2259 #endif 2260 ) 2261 { 2262 pcireg_t rval; 2263 2264 /* 2265 * XXX these need to be printed in more detail, need to be 2266 * XXX checked against specs/docs, etc. 2267 * 2268 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 2269 * controller chip documentation, and may not be correct with 2270 * respect to various standards. (XXX) 2271 */ 2272 2273 #ifdef _KERNEL 2274 pci_conf_print_bar(pc, tag, regs, 0x10, 2275 "CardBus socket/ExCA registers", sizebars); 2276 #else 2277 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 2278 #endif 2279 2280 /* Capability list pointer and secondary status register */ 2281 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 2282 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2283 printf(" Capability list pointer: 0x%02x\n", 2284 PCI_CAPLIST_PTR(rval)); 2285 else 2286 printf(" Reserved @ 0x14: 0x%04" PRIxMAX "\n", 2287 __SHIFTOUT(rval, __BITS(15, 0))); 2288 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 2289 2290 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 2291 printf(" PCI bus number: 0x%02x\n", 2292 (rval >> 0) & 0xff); 2293 printf(" CardBus bus number: 0x%02x\n", 2294 (rval >> 8) & 0xff); 2295 printf(" Subordinate bus number: 0x%02x\n", 2296 (rval >> 16) & 0xff); 2297 printf(" CardBus latency timer: 0x%02x\n", 2298 (rval >> 24) & 0xff); 2299 2300 /* XXX Print more prettily */ 2301 printf(" CardBus memory region 0:\n"); 2302 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 2303 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 2304 printf(" CardBus memory region 1:\n"); 2305 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 2306 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 2307 printf(" CardBus I/O region 0:\n"); 2308 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 2309 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 2310 printf(" CardBus I/O region 1:\n"); 2311 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 2312 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 2313 2314 rval = regs[o2i(PCI_INTERRUPT_REG)]; 2315 printf(" Interrupt line: 0x%02x\n", 2316 (rval >> 0) & 0xff); 2317 printf(" Interrupt pin: 0x%02x ", 2318 (rval >> 8) & 0xff); 2319 switch ((rval >> 8) & 0xff) { 2320 case PCI_INTERRUPT_PIN_NONE: 2321 printf("(none)"); 2322 break; 2323 case PCI_INTERRUPT_PIN_A: 2324 printf("(pin A)"); 2325 break; 2326 case PCI_INTERRUPT_PIN_B: 2327 printf("(pin B)"); 2328 break; 2329 case PCI_INTERRUPT_PIN_C: 2330 printf("(pin C)"); 2331 break; 2332 case PCI_INTERRUPT_PIN_D: 2333 printf("(pin D)"); 2334 break; 2335 default: 2336 printf("(? ? ?)"); 2337 break; 2338 } 2339 printf("\n"); 2340 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 2341 printf(" Bridge control register: 0x%04x\n", rval); 2342 onoff("Parity error response", rval, __BIT(0)); 2343 onoff("SERR# enable", rval, __BIT(1)); 2344 onoff("ISA enable", rval, __BIT(2)); 2345 onoff("VGA enable", rval, __BIT(3)); 2346 onoff("Master abort mode", rval, __BIT(5)); 2347 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 2348 onoff("Functional interrupts routed by ExCA registers", rval, 2349 __BIT(7)); 2350 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 2351 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 2352 onoff("Write posting enable", rval, __BIT(10)); 2353 2354 rval = regs[o2i(0x40)]; 2355 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 2356 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 2357 2358 #ifdef _KERNEL 2359 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 2360 sizebars); 2361 #else 2362 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 2363 #endif 2364 } 2365 2366 void 2367 pci_conf_print( 2368 #ifdef _KERNEL 2369 pci_chipset_tag_t pc, pcitag_t tag, 2370 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 2371 #else 2372 int pcifd, u_int bus, u_int dev, u_int func 2373 #endif 2374 ) 2375 { 2376 pcireg_t regs[o2i(256)]; 2377 int off, capoff, endoff, hdrtype; 2378 const char *typename; 2379 #ifdef _KERNEL 2380 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, 2381 int); 2382 int sizebars; 2383 #else 2384 void (*typeprintfn)(const pcireg_t *); 2385 #endif 2386 2387 printf("PCI configuration registers:\n"); 2388 2389 for (off = 0; off < 256; off += 4) { 2390 #ifdef _KERNEL 2391 regs[o2i(off)] = pci_conf_read(pc, tag, off); 2392 #else 2393 if (pcibus_conf_read(pcifd, bus, dev, func, off, 2394 ®s[o2i(off)]) == -1) 2395 regs[o2i(off)] = 0; 2396 #endif 2397 } 2398 2399 #ifdef _KERNEL 2400 sizebars = 1; 2401 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 2402 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 2403 sizebars = 0; 2404 #endif 2405 2406 /* common header */ 2407 printf(" Common header:\n"); 2408 pci_conf_print_regs(regs, 0, 16); 2409 2410 printf("\n"); 2411 #ifdef _KERNEL 2412 pci_conf_print_common(pc, tag, regs); 2413 #else 2414 pci_conf_print_common(regs); 2415 #endif 2416 printf("\n"); 2417 2418 /* type-dependent header */ 2419 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 2420 switch (hdrtype) { /* XXX make a table, eventually */ 2421 case 0: 2422 /* Standard device header */ 2423 typename = "\"normal\" device"; 2424 typeprintfn = &pci_conf_print_type0; 2425 capoff = PCI_CAPLISTPTR_REG; 2426 endoff = 64; 2427 break; 2428 case 1: 2429 /* PCI-PCI bridge header */ 2430 typename = "PCI-PCI bridge"; 2431 typeprintfn = &pci_conf_print_type1; 2432 capoff = PCI_CAPLISTPTR_REG; 2433 endoff = 64; 2434 break; 2435 case 2: 2436 /* PCI-CardBus bridge header */ 2437 typename = "PCI-CardBus bridge"; 2438 typeprintfn = &pci_conf_print_type2; 2439 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 2440 endoff = 72; 2441 break; 2442 default: 2443 typename = NULL; 2444 typeprintfn = 0; 2445 capoff = -1; 2446 endoff = 64; 2447 break; 2448 } 2449 printf(" Type %d ", hdrtype); 2450 if (typename != NULL) 2451 printf("(%s) ", typename); 2452 printf("header:\n"); 2453 pci_conf_print_regs(regs, 16, endoff); 2454 printf("\n"); 2455 if (typeprintfn) { 2456 #ifdef _KERNEL 2457 (*typeprintfn)(pc, tag, regs, sizebars); 2458 #else 2459 (*typeprintfn)(regs); 2460 #endif 2461 } else 2462 printf(" Don't know how to pretty-print type %d header.\n", 2463 hdrtype); 2464 printf("\n"); 2465 2466 /* capability list, if present */ 2467 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2468 && (capoff > 0)) { 2469 #ifdef _KERNEL 2470 pci_conf_print_caplist(pc, tag, regs, capoff); 2471 #else 2472 pci_conf_print_caplist(regs, capoff); 2473 #endif 2474 printf("\n"); 2475 } 2476 2477 /* device-dependent header */ 2478 printf(" Device-dependent header:\n"); 2479 pci_conf_print_regs(regs, endoff, 256); 2480 printf("\n"); 2481 #ifdef _KERNEL 2482 if (printfn) 2483 (*printfn)(pc, tag, regs); 2484 else 2485 printf(" Don't know how to pretty-print device-dependent header.\n"); 2486 printf("\n"); 2487 #endif /* _KERNEL */ 2488 } 2489
Indexes created Thu Sep 25 16:09:42 GMT 2025