pci_subr.c revision 1.124.2.1
1 /* $NetBSD: pci_subr.c,v 1.124.2.1 2014/12/12 19:03:17 martin Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.124.2.1 2014/12/12 19:03:17 martin Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdbool.h> 58 #include <stdio.h> 59 #include <string.h> 60 #endif 61 62 #include <dev/pci/pcireg.h> 63 #ifdef _KERNEL 64 #include <dev/pci/pcivar.h> 65 #endif 66 67 /* 68 * Descriptions of known PCI classes and subclasses. 69 * 70 * Subclasses are described in the same way as classes, but have a 71 * NULL subclass pointer. 72 */ 73 struct pci_class { 74 const char *name; 75 u_int val; /* as wide as pci_{,sub}class_t */ 76 const struct pci_class *subclasses; 77 }; 78 79 /* 80 * Class 0x00. 81 * Before rev. 2.0. 82 */ 83 static const struct pci_class pci_subclass_prehistoric[] = { 84 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 85 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 86 { NULL, 0, NULL, }, 87 }; 88 89 /* 90 * Class 0x01. 91 * Mass storage controller 92 */ 93 94 /* ATA programming interface */ 95 static const struct pci_class pci_interface_ata[] = { 96 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 97 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 98 { NULL, 0, NULL, }, 99 }; 100 101 /* SATA programming interface */ 102 static const struct pci_class pci_interface_sata[] = { 103 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 104 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 105 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 106 { NULL, 0, NULL, }, 107 }; 108 109 /* Flash programming interface */ 110 static const struct pci_class pci_interface_nvm[] = { 111 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 112 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 113 { NULL, 0, NULL, }, 114 }; 115 116 /* Subclasses */ 117 static const struct pci_class pci_subclass_mass_storage[] = { 118 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 119 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 120 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 121 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 122 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 123 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 124 pci_interface_ata, }, 125 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 126 pci_interface_sata, }, 127 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 128 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 129 pci_interface_nvm, }, 130 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 131 { NULL, 0, NULL, }, 132 }; 133 134 /* 135 * Class 0x02. 136 * Network controller. 137 */ 138 static const struct pci_class pci_subclass_network[] = { 139 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 140 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 141 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 142 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 143 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 144 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 145 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 146 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 147 { NULL, 0, NULL, }, 148 }; 149 150 /* 151 * Class 0x03. 152 * Display controller. 153 */ 154 155 /* VGA programming interface */ 156 static const struct pci_class pci_interface_vga[] = { 157 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 158 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 159 { NULL, 0, NULL, }, 160 }; 161 /* Subclasses */ 162 static const struct pci_class pci_subclass_display[] = { 163 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 164 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 165 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 166 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 167 { NULL, 0, NULL, }, 168 }; 169 170 /* 171 * Class 0x04. 172 * Multimedia device. 173 */ 174 static const struct pci_class pci_subclass_multimedia[] = { 175 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 176 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 177 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 178 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 179 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 180 { NULL, 0, NULL, }, 181 }; 182 183 /* 184 * Class 0x05. 185 * Memory controller. 186 */ 187 static const struct pci_class pci_subclass_memory[] = { 188 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 189 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 190 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 191 { NULL, 0, NULL, }, 192 }; 193 194 /* 195 * Class 0x06. 196 * Bridge device. 197 */ 198 199 /* PCI bridge programming interface */ 200 static const struct pci_class pci_interface_pcibridge[] = { 201 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 202 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 203 { NULL, 0, NULL, }, 204 }; 205 206 /* Semi-transparent PCI-to-PCI bridge programming interface */ 207 static const struct pci_class pci_interface_stpci[] = { 208 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 209 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 210 { NULL, 0, NULL, }, 211 }; 212 213 /* Advanced Switching programming interface */ 214 static const struct pci_class pci_interface_advsw[] = { 215 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 216 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 217 { NULL, 0, NULL, }, 218 }; 219 220 /* Subclasses */ 221 static const struct pci_class pci_subclass_bridge[] = { 222 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 223 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 224 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 225 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 226 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 227 pci_interface_pcibridge, }, 228 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 229 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 230 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 231 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 232 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 233 pci_interface_stpci, }, 234 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 235 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 236 pci_interface_advsw, }, 237 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 238 { NULL, 0, NULL, }, 239 }; 240 241 /* 242 * Class 0x07. 243 * Simple communications controller. 244 */ 245 246 /* Serial controller programming interface */ 247 static const struct pci_class pci_interface_serial[] = { 248 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 249 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 250 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 251 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 252 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 253 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 254 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 255 { NULL, 0, NULL, }, 256 }; 257 258 /* Parallel controller programming interface */ 259 static const struct pci_class pci_interface_parallel[] = { 260 { "", PCI_INTERFACE_PARALLEL, NULL,}, 261 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 262 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 263 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 264 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 265 { NULL, 0, NULL,}, 266 }; 267 268 /* Modem programming interface */ 269 static const struct pci_class pci_interface_modem[] = { 270 { "", PCI_INTERFACE_MODEM, NULL,}, 271 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 272 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 273 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 274 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 275 { NULL, 0, NULL,}, 276 }; 277 278 /* Subclasses */ 279 static const struct pci_class pci_subclass_communications[] = { 280 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 281 pci_interface_serial, }, 282 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 283 pci_interface_parallel, }, 284 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 285 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 286 pci_interface_modem, }, 287 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 288 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 289 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 290 { NULL, 0, NULL,}, 291 }; 292 293 /* 294 * Class 0x08. 295 * Base system peripheral. 296 */ 297 298 /* PIC programming interface */ 299 static const struct pci_class pci_interface_pic[] = { 300 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 301 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 302 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 303 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 304 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 305 { NULL, 0, NULL, }, 306 }; 307 308 /* DMA programming interface */ 309 static const struct pci_class pci_interface_dma[] = { 310 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 311 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 312 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 313 { NULL, 0, NULL, }, 314 }; 315 316 /* Timer programming interface */ 317 static const struct pci_class pci_interface_tmr[] = { 318 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 319 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 320 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 321 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 322 { NULL, 0, NULL, }, 323 }; 324 325 /* RTC programming interface */ 326 static const struct pci_class pci_interface_rtc[] = { 327 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 328 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 329 { NULL, 0, NULL, }, 330 }; 331 332 /* Subclasses */ 333 static const struct pci_class pci_subclass_system[] = { 334 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 335 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 336 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 337 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 338 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 339 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 340 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 341 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 342 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 343 { NULL, 0, NULL, }, 344 }; 345 346 /* 347 * Class 0x09. 348 * Input device. 349 */ 350 351 /* Gameport programming interface */ 352 static const struct pci_class pci_interface_game[] = { 353 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 354 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 355 { NULL, 0, NULL, }, 356 }; 357 358 /* Subclasses */ 359 static const struct pci_class pci_subclass_input[] = { 360 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 361 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 362 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 363 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 364 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 365 pci_interface_game, }, 366 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 367 { NULL, 0, NULL, }, 368 }; 369 370 /* 371 * Class 0x0a. 372 * Docking station. 373 */ 374 static const struct pci_class pci_subclass_dock[] = { 375 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 376 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 377 { NULL, 0, NULL, }, 378 }; 379 380 /* 381 * Class 0x0b. 382 * Processor. 383 */ 384 static const struct pci_class pci_subclass_processor[] = { 385 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 386 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 387 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 388 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 389 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 390 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 391 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 392 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 393 { NULL, 0, NULL, }, 394 }; 395 396 /* 397 * Class 0x0c. 398 * Serial bus controller. 399 */ 400 401 /* IEEE1394 programming interface */ 402 static const struct pci_class pci_interface_ieee1394[] = { 403 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 404 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 405 { NULL, 0, NULL,}, 406 }; 407 408 /* USB programming interface */ 409 static const struct pci_class pci_interface_usb[] = { 410 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 411 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 412 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 413 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 414 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 415 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 416 { NULL, 0, NULL, }, 417 }; 418 419 /* IPMI programming interface */ 420 static const struct pci_class pci_interface_ipmi[] = { 421 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 422 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 423 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 424 { NULL, 0, NULL,}, 425 }; 426 427 /* Subclasses */ 428 static const struct pci_class pci_subclass_serialbus[] = { 429 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 430 pci_interface_ieee1394, }, 431 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 432 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 433 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 434 pci_interface_usb, }, 435 /* XXX Fiber Channel/_FIBRECHANNEL */ 436 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 437 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 438 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 439 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 440 pci_interface_ipmi, }, 441 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 442 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 443 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 444 { NULL, 0, NULL, }, 445 }; 446 447 /* 448 * Class 0x0d. 449 * Wireless Controller. 450 */ 451 static const struct pci_class pci_subclass_wireless[] = { 452 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 453 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 454 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 455 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 456 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 457 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 458 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 459 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 460 { NULL, 0, NULL, }, 461 }; 462 463 /* 464 * Class 0x0e. 465 * Intelligent IO controller. 466 */ 467 468 /* Intelligent IO programming interface */ 469 static const struct pci_class pci_interface_i2o[] = { 470 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 471 { NULL, 0, NULL,}, 472 }; 473 474 /* Subclasses */ 475 static const struct pci_class pci_subclass_i2o[] = { 476 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 477 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 478 { NULL, 0, NULL, }, 479 }; 480 481 /* 482 * Class 0x0f. 483 * Satellite communication controller. 484 */ 485 static const struct pci_class pci_subclass_satcom[] = { 486 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 487 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 488 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 489 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 490 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 491 { NULL, 0, NULL, }, 492 }; 493 494 /* 495 * Class 0x10. 496 * Encryption/Decryption controller. 497 */ 498 static const struct pci_class pci_subclass_crypto[] = { 499 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 500 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 501 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 502 { NULL, 0, NULL, }, 503 }; 504 505 /* 506 * Class 0x11. 507 * Data aquuisition and signal processing controller. 508 */ 509 static const struct pci_class pci_subclass_dasp[] = { 510 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 511 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 512 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 513 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 514 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 515 { NULL, 0, NULL, }, 516 }; 517 518 /* List of classes */ 519 static const struct pci_class pci_class[] = { 520 { "prehistoric", PCI_CLASS_PREHISTORIC, 521 pci_subclass_prehistoric, }, 522 { "mass storage", PCI_CLASS_MASS_STORAGE, 523 pci_subclass_mass_storage, }, 524 { "network", PCI_CLASS_NETWORK, 525 pci_subclass_network, }, 526 { "display", PCI_CLASS_DISPLAY, 527 pci_subclass_display, }, 528 { "multimedia", PCI_CLASS_MULTIMEDIA, 529 pci_subclass_multimedia, }, 530 { "memory", PCI_CLASS_MEMORY, 531 pci_subclass_memory, }, 532 { "bridge", PCI_CLASS_BRIDGE, 533 pci_subclass_bridge, }, 534 { "communications", PCI_CLASS_COMMUNICATIONS, 535 pci_subclass_communications, }, 536 { "system", PCI_CLASS_SYSTEM, 537 pci_subclass_system, }, 538 { "input", PCI_CLASS_INPUT, 539 pci_subclass_input, }, 540 { "dock", PCI_CLASS_DOCK, 541 pci_subclass_dock, }, 542 { "processor", PCI_CLASS_PROCESSOR, 543 pci_subclass_processor, }, 544 { "serial bus", PCI_CLASS_SERIALBUS, 545 pci_subclass_serialbus, }, 546 { "wireless", PCI_CLASS_WIRELESS, 547 pci_subclass_wireless, }, 548 { "I2O", PCI_CLASS_I2O, 549 pci_subclass_i2o, }, 550 { "satellite comm", PCI_CLASS_SATCOM, 551 pci_subclass_satcom, }, 552 { "crypto", PCI_CLASS_CRYPTO, 553 pci_subclass_crypto, }, 554 { "DASP", PCI_CLASS_DASP, 555 pci_subclass_dasp, }, 556 { "undefined", PCI_CLASS_UNDEFINED, 557 NULL, }, 558 { NULL, 0, 559 NULL, }, 560 }; 561 562 void pci_load_verbose(void); 563 564 #if defined(_KERNEL) 565 /* 566 * In kernel, these routines are provided and linked via the 567 * pciverbose module. 568 */ 569 const char *pci_findvendor_stub(pcireg_t); 570 const char *pci_findproduct_stub(pcireg_t); 571 572 const char *(*pci_findvendor)(pcireg_t) = pci_findvendor_stub; 573 const char *(*pci_findproduct)(pcireg_t) = pci_findproduct_stub; 574 const char *pci_unmatched = ""; 575 #else 576 /* 577 * For userland we just set the vectors here. 578 */ 579 const char *(*pci_findvendor)(pcireg_t id_reg) = pci_findvendor_real; 580 const char *(*pci_findproduct)(pcireg_t id_reg) = pci_findproduct_real; 581 const char *pci_unmatched = "unmatched "; 582 #endif 583 584 int pciverbose_loaded = 0; 585 586 #if defined(_KERNEL) 587 /* 588 * Routine to load the pciverbose kernel module as needed 589 */ 590 void 591 pci_load_verbose(void) 592 { 593 594 if (pciverbose_loaded == 0) 595 module_autoload("pciverbose", MODULE_CLASS_MISC); 596 } 597 598 const char * 599 pci_findvendor_stub(pcireg_t id_reg) 600 { 601 602 pci_load_verbose(); 603 if (pciverbose_loaded) 604 return pci_findvendor(id_reg); 605 else 606 return NULL; 607 } 608 609 const char * 610 pci_findproduct_stub(pcireg_t id_reg) 611 { 612 613 pci_load_verbose(); 614 if (pciverbose_loaded) 615 return pci_findproduct(id_reg); 616 else 617 return NULL; 618 } 619 #endif 620 621 void 622 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 623 size_t l) 624 { 625 pci_vendor_id_t vendor; 626 pci_product_id_t product; 627 pci_class_t class; 628 pci_subclass_t subclass; 629 pci_interface_t interface; 630 pci_revision_t revision; 631 const char *unmatched = pci_unmatched; 632 const char *vendor_namep, *product_namep; 633 const struct pci_class *classp, *subclassp, *interfacep; 634 char *ep; 635 636 ep = cp + l; 637 638 vendor = PCI_VENDOR(id_reg); 639 product = PCI_PRODUCT(id_reg); 640 641 class = PCI_CLASS(class_reg); 642 subclass = PCI_SUBCLASS(class_reg); 643 interface = PCI_INTERFACE(class_reg); 644 revision = PCI_REVISION(class_reg); 645 646 vendor_namep = pci_findvendor(id_reg); 647 product_namep = pci_findproduct(id_reg); 648 649 classp = pci_class; 650 while (classp->name != NULL) { 651 if (class == classp->val) 652 break; 653 classp++; 654 } 655 656 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 657 while (subclassp && subclassp->name != NULL) { 658 if (subclass == subclassp->val) 659 break; 660 subclassp++; 661 } 662 663 interfacep = (subclassp && subclassp->name != NULL) ? 664 subclassp->subclasses : NULL; 665 while (interfacep && interfacep->name != NULL) { 666 if (interface == interfacep->val) 667 break; 668 interfacep++; 669 } 670 671 if (vendor_namep == NULL) 672 cp += snprintf(cp, ep - cp, "%svendor 0x%04x product 0x%04x", 673 unmatched, vendor, product); 674 else if (product_namep != NULL) 675 cp += snprintf(cp, ep - cp, "%s %s", vendor_namep, 676 product_namep); 677 else 678 cp += snprintf(cp, ep - cp, "%s product 0x%04x", 679 vendor_namep, product); 680 if (showclass) { 681 cp += snprintf(cp, ep - cp, " ("); 682 if (classp->name == NULL) 683 cp += snprintf(cp, ep - cp, 684 "class 0x%02x, subclass 0x%02x", class, subclass); 685 else { 686 if (subclassp == NULL || subclassp->name == NULL) 687 cp += snprintf(cp, ep - cp, 688 "%s, subclass 0x%02x", 689 classp->name, subclass); 690 else 691 cp += snprintf(cp, ep - cp, "%s %s", 692 subclassp->name, classp->name); 693 } 694 if ((interfacep == NULL) || (interfacep->name == NULL)) { 695 if (interface != 0) 696 cp += snprintf(cp, ep - cp, 697 ", interface 0x%02x", interface); 698 } else if (strncmp(interfacep->name, "", 1) != 0) 699 cp += snprintf(cp, ep - cp, ", %s", 700 interfacep->name); 701 if (revision != 0) 702 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 703 revision); 704 cp += snprintf(cp, ep - cp, ")"); 705 } 706 } 707 708 #ifdef _KERNEL 709 void 710 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 711 const char *known, int addrev) 712 { 713 char devinfo[256]; 714 715 if (known) { 716 aprint_normal(": %s", known); 717 if (addrev) 718 aprint_normal(" (rev. 0x%02x)", 719 PCI_REVISION(pa->pa_class)); 720 aprint_normal("\n"); 721 } else { 722 pci_devinfo(pa->pa_id, pa->pa_class, 0, 723 devinfo, sizeof(devinfo)); 724 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 725 PCI_REVISION(pa->pa_class)); 726 } 727 if (naive) 728 aprint_naive(": %s\n", naive); 729 else 730 aprint_naive("\n"); 731 } 732 #endif 733 734 /* 735 * Print out most of the PCI configuration registers. Typically used 736 * in a device attach routine like this: 737 * 738 * #ifdef MYDEV_DEBUG 739 * printf("%s: ", device_xname(sc->sc_dev)); 740 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 741 * #endif 742 */ 743 744 #define i2o(i) ((i) * 4) 745 #define o2i(o) ((o) / 4) 746 #define onoff2(str, rval, bit, onstr, offstr) \ 747 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 748 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 749 750 static void 751 pci_conf_print_common( 752 #ifdef _KERNEL 753 pci_chipset_tag_t pc, pcitag_t tag, 754 #endif 755 const pcireg_t *regs) 756 { 757 const char *name; 758 const struct pci_class *classp, *subclassp; 759 pcireg_t rval; 760 unsigned int num; 761 762 rval = regs[o2i(PCI_ID_REG)]; 763 name = pci_findvendor(rval); 764 if (name) 765 printf(" Vendor Name: %s (0x%04x)\n", name, 766 PCI_VENDOR(rval)); 767 else 768 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 769 name = pci_findproduct(rval); 770 if (name) 771 printf(" Device Name: %s (0x%04x)\n", name, 772 PCI_PRODUCT(rval)); 773 else 774 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 775 776 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 777 778 printf(" Command register: 0x%04x\n", rval & 0xffff); 779 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 780 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 781 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 782 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 783 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 784 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 785 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 786 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 787 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 788 onoff("Fast back-to-back transactions", rval, 789 PCI_COMMAND_BACKTOBACK_ENABLE); 790 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 791 792 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 793 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 794 "inactive"); 795 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 796 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 797 onoff("User Definable Features (UDF) support", rval, 798 PCI_STATUS_UDF_SUPPORT); 799 onoff("Fast back-to-back capable", rval, 800 PCI_STATUS_BACKTOBACK_SUPPORT); 801 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 802 803 printf(" DEVSEL timing: "); 804 switch (rval & PCI_STATUS_DEVSEL_MASK) { 805 case PCI_STATUS_DEVSEL_FAST: 806 printf("fast"); 807 break; 808 case PCI_STATUS_DEVSEL_MEDIUM: 809 printf("medium"); 810 break; 811 case PCI_STATUS_DEVSEL_SLOW: 812 printf("slow"); 813 break; 814 default: 815 printf("unknown/reserved"); /* XXX */ 816 break; 817 } 818 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 819 820 onoff("Slave signaled Target Abort", rval, 821 PCI_STATUS_TARGET_TARGET_ABORT); 822 onoff("Master received Target Abort", rval, 823 PCI_STATUS_MASTER_TARGET_ABORT); 824 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 825 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 826 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 827 828 rval = regs[o2i(PCI_CLASS_REG)]; 829 for (classp = pci_class; classp->name != NULL; classp++) { 830 if (PCI_CLASS(rval) == classp->val) 831 break; 832 } 833 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 834 while (subclassp && subclassp->name != NULL) { 835 if (PCI_SUBCLASS(rval) == subclassp->val) 836 break; 837 subclassp++; 838 } 839 if (classp->name != NULL) { 840 printf(" Class Name: %s (0x%02x)\n", classp->name, 841 PCI_CLASS(rval)); 842 if (subclassp != NULL && subclassp->name != NULL) 843 printf(" Subclass Name: %s (0x%02x)\n", 844 subclassp->name, PCI_SUBCLASS(rval)); 845 else 846 printf(" Subclass ID: 0x%02x\n", 847 PCI_SUBCLASS(rval)); 848 } else { 849 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 850 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 851 } 852 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 853 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 854 855 rval = regs[o2i(PCI_BHLC_REG)]; 856 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 857 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 858 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 859 PCI_HDRTYPE(rval)); 860 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 861 num = PCI_CACHELINE(rval); 862 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 863 } 864 865 static int 866 pci_conf_print_bar( 867 #ifdef _KERNEL 868 pci_chipset_tag_t pc, pcitag_t tag, 869 #endif 870 const pcireg_t *regs, int reg, const char *name 871 #ifdef _KERNEL 872 , int sizebar 873 #endif 874 ) 875 { 876 int width; 877 pcireg_t rval, rval64h; 878 #ifdef _KERNEL 879 int s; 880 pcireg_t mask, mask64h; 881 #endif 882 883 width = 4; 884 885 /* 886 * Section 6.2.5.1, `Address Maps', tells us that: 887 * 888 * 1) The builtin software should have already mapped the 889 * device in a reasonable way. 890 * 891 * 2) A device which wants 2^n bytes of memory will hardwire 892 * the bottom n bits of the address to 0. As recommended, 893 * we write all 1s and see what we get back. 894 */ 895 896 rval = regs[o2i(reg)]; 897 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 898 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 899 rval64h = regs[o2i(reg + 4)]; 900 width = 8; 901 } else 902 rval64h = 0; 903 904 #ifdef _KERNEL 905 /* XXX don't size unknown memory type? */ 906 if (rval != 0 && sizebar) { 907 /* 908 * The following sequence seems to make some devices 909 * (e.g. host bus bridges, which don't normally 910 * have their space mapped) very unhappy, to 911 * the point of crashing the system. 912 * 913 * Therefore, if the mapping register is zero to 914 * start out with, don't bother trying. 915 */ 916 s = splhigh(); 917 pci_conf_write(pc, tag, reg, 0xffffffff); 918 mask = pci_conf_read(pc, tag, reg); 919 pci_conf_write(pc, tag, reg, rval); 920 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 921 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 922 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 923 mask64h = pci_conf_read(pc, tag, reg + 4); 924 pci_conf_write(pc, tag, reg + 4, rval64h); 925 } else 926 mask64h = 0; 927 splx(s); 928 } else 929 mask = mask64h = 0; 930 #endif /* _KERNEL */ 931 932 printf(" Base address register at 0x%02x", reg); 933 if (name) 934 printf(" (%s)", name); 935 printf("\n "); 936 if (rval == 0) { 937 printf("not implemented(?)\n"); 938 return width; 939 } 940 printf("type: "); 941 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 942 const char *type, *prefetch; 943 944 switch (PCI_MAPREG_MEM_TYPE(rval)) { 945 case PCI_MAPREG_MEM_TYPE_32BIT: 946 type = "32-bit"; 947 break; 948 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 949 type = "32-bit-1M"; 950 break; 951 case PCI_MAPREG_MEM_TYPE_64BIT: 952 type = "64-bit"; 953 break; 954 default: 955 type = "unknown (XXX)"; 956 break; 957 } 958 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 959 prefetch = ""; 960 else 961 prefetch = "non"; 962 printf("%s %sprefetchable memory\n", type, prefetch); 963 switch (PCI_MAPREG_MEM_TYPE(rval)) { 964 case PCI_MAPREG_MEM_TYPE_64BIT: 965 printf(" base: 0x%016llx, ", 966 PCI_MAPREG_MEM64_ADDR( 967 ((((long long) rval64h) << 32) | rval))); 968 #ifdef _KERNEL 969 if (sizebar) 970 printf("size: 0x%016llx", 971 PCI_MAPREG_MEM64_SIZE( 972 ((((long long) mask64h) << 32) | mask))); 973 else 974 #endif /* _KERNEL */ 975 printf("not sized"); 976 printf("\n"); 977 break; 978 case PCI_MAPREG_MEM_TYPE_32BIT: 979 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 980 default: 981 printf(" base: 0x%08x, ", 982 PCI_MAPREG_MEM_ADDR(rval)); 983 #ifdef _KERNEL 984 if (sizebar) 985 printf("size: 0x%08x", 986 PCI_MAPREG_MEM_SIZE(mask)); 987 else 988 #endif /* _KERNEL */ 989 printf("not sized"); 990 printf("\n"); 991 break; 992 } 993 } else { 994 #ifdef _KERNEL 995 if (sizebar) 996 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 997 #endif /* _KERNEL */ 998 printf("i/o\n"); 999 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 1000 #ifdef _KERNEL 1001 if (sizebar) 1002 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 1003 else 1004 #endif /* _KERNEL */ 1005 printf("not sized"); 1006 printf("\n"); 1007 } 1008 1009 return width; 1010 } 1011 1012 static void 1013 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 1014 { 1015 int off, needaddr, neednl; 1016 1017 needaddr = 1; 1018 neednl = 0; 1019 for (off = first; off < pastlast; off += 4) { 1020 if ((off % 16) == 0 || needaddr) { 1021 printf(" 0x%02x:", off); 1022 needaddr = 0; 1023 } 1024 printf(" 0x%08x", regs[o2i(off)]); 1025 neednl = 1; 1026 if ((off % 16) == 12) { 1027 printf("\n"); 1028 neednl = 0; 1029 } 1030 } 1031 if (neednl) 1032 printf("\n"); 1033 } 1034 1035 static void 1036 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1037 { 1038 pcireg_t rval; 1039 1040 printf("\n AGP Capabilities Register\n"); 1041 1042 rval = regs[o2i(capoff)]; 1043 printf(" Revision: %d.%d\n", 1044 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1045 1046 /* XXX need more */ 1047 } 1048 1049 static const char * 1050 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1051 { 1052 1053 switch ((caps >> 6) & 7) { 1054 case 0: return "self-powered"; 1055 case 1: return "55 mA"; 1056 case 2: return "100 mA"; 1057 case 3: return "160 mA"; 1058 case 4: return "220 mA"; 1059 case 5: return "270 mA"; 1060 case 6: return "320 mA"; 1061 case 7: 1062 default: return "375 mA"; 1063 } 1064 } 1065 1066 static const char * 1067 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1068 { 1069 static const char unk[] = "unknown"; 1070 static const char *pmrev[8] = { 1071 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1072 }; 1073 if (val > 7) 1074 return unk; 1075 return pmrev[val]; 1076 } 1077 1078 static void 1079 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1080 { 1081 uint16_t caps, pmcsr; 1082 pcireg_t reg; 1083 1084 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1085 reg = regs[o2i(capoff + PCI_PMCSR)]; 1086 pmcsr = reg & 0xffff; 1087 1088 printf("\n PCI Power Management Capabilities Register\n"); 1089 1090 printf(" Capabilities register: 0x%04x\n", caps); 1091 printf(" Version: %s\n", 1092 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1093 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1094 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1095 printf(" 3.3V auxiliary current: %s\n", 1096 pci_conf_print_pcipm_cap_aux(caps)); 1097 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1098 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1099 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1100 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1101 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1102 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1103 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1104 1105 printf(" Control/status register: 0x%04x\n", pmcsr); 1106 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1107 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1108 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1109 printf(" PME# assertion: %sabled\n", 1110 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1111 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1112 printf(" Bridge Support Extensions register: 0x%02x\n", 1113 (reg >> 16) & 0xff); 1114 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1115 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1116 printf(" Data register: 0x%02x\n", (reg >> 24) & 0xff); 1117 1118 } 1119 1120 /* XXX pci_conf_print_vpd_cap */ 1121 /* XXX pci_conf_print_slotid_cap */ 1122 1123 static void 1124 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1125 { 1126 uint32_t ctl, mmc, mme; 1127 1128 regs += o2i(capoff); 1129 ctl = *regs++; 1130 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1131 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1132 1133 printf("\n PCI Message Signaled Interrupt\n"); 1134 1135 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1136 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1137 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1138 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1139 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1140 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1141 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1142 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1143 printf(" Message Address %sregister: 0x%08x\n", 1144 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1145 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1146 printf(" Message Address %sregister: 0x%08x\n", 1147 "(upper) ", *regs++); 1148 } 1149 printf(" Message Data register: 0x%08x\n", *regs++); 1150 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1151 printf(" Vector Mask register: 0x%08x\n", *regs++); 1152 printf(" Vector Pending register: 0x%08x\n", *regs++); 1153 } 1154 } 1155 1156 /* XXX pci_conf_print_cpci_hostwap_cap */ 1157 1158 /* 1159 * For both command register and status register. 1160 * The argument "idx" is index number (0 to 7). 1161 */ 1162 static int 1163 pcix_split_trans(unsigned int idx) 1164 { 1165 static int table[8] = { 1166 1, 2, 3, 4, 8, 12, 16, 32 1167 }; 1168 1169 if (idx >= __arraycount(table)) 1170 return -1; 1171 return table[idx]; 1172 } 1173 1174 static void 1175 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1176 { 1177 pcireg_t reg; 1178 int isbridge; 1179 int i; 1180 1181 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1182 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1183 printf("\n PCI-X %s Capabilities Register\n", 1184 isbridge ? "Bridge" : "Non-bridge"); 1185 1186 reg = regs[o2i(capoff)]; 1187 if (isbridge != 0) { 1188 printf(" Secondary status register: 0x%04x\n", 1189 (reg & 0xffff0000) >> 16); 1190 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1191 onoff("133MHz capable", reg, PCIX_STATUS_133); 1192 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1193 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1194 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1195 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1196 printf(" Secondary clock frequency: 0x%x\n", 1197 (reg & PCIX_BRIDGE_2NDST_CLKF) 1198 >> PCIX_BRIDGE_2NDST_CLKF_SHIFT); 1199 printf(" Version: 0x%x\n", 1200 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1201 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1202 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1203 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1204 } else { 1205 printf(" Command register: 0x%04x\n", 1206 (reg & 0xffff0000) >> 16); 1207 onoff("Data Parity Error Recovery", reg, 1208 PCIX_CMD_PERR_RECOVER); 1209 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1210 printf(" Maximum Burst Read Count: %u\n", 1211 PCIX_CMD_BYTECNT(reg)); 1212 printf(" Maximum Split Transactions: %d\n", 1213 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1214 >> PCIX_CMD_SPLTRANS_SHIFT)); 1215 } 1216 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1217 printf(" %sStatus register: 0x%08x\n", 1218 isbridge ? "Bridge " : "", reg); 1219 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1220 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1221 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1222 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1223 onoff("133MHz capable", reg, PCIX_STATUS_133); 1224 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1225 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1226 if (isbridge != 0) { 1227 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1228 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1229 } else { 1230 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1231 "bridge device", "simple device"); 1232 printf(" Designed max memory read byte count: %d\n", 1233 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1234 >> PCIX_STATUS_MAXB_SHIFT)); 1235 printf(" Designed max outstanding split transaction: %d\n", 1236 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1237 >> PCIX_STATUS_MAXST_SHIFT)); 1238 printf(" MAX cumulative Read Size: %u\n", 1239 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1240 onoff("Received split completion error", reg, 1241 PCIX_STATUS_SCERR); 1242 } 1243 onoff("266MHz capable", reg, PCIX_STATUS_266); 1244 onoff("533MHz capable", reg, PCIX_STATUS_533); 1245 1246 if (isbridge == 0) 1247 return; 1248 1249 /* Only for bridge */ 1250 for (i = 0; i < 2; i++) { 1251 reg = regs[o2i(capoff+PCIX_BRIDGE_UP_STCR + (4 * i))]; 1252 printf(" %s split transaction control register: 0x%08x\n", 1253 (i == 0) ? "Upstream" : "Downstream", reg); 1254 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1255 printf(" Commitment Limit: %d\n", 1256 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1257 } 1258 } 1259 1260 /* XXX pci_conf_print_ldt_cap */ 1261 1262 static void 1263 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1264 { 1265 uint16_t caps; 1266 1267 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1268 1269 printf("\n PCI Vendor Specific Capabilities Register\n"); 1270 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1271 } 1272 1273 static void 1274 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1275 { 1276 pcireg_t val; 1277 1278 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1279 1280 printf("\n Debugport Capability Register\n"); 1281 printf(" Debug base Register: 0x%04x\n", 1282 val >> PCI_DEBUG_BASER_SHIFT); 1283 printf(" port offset: 0x%04x\n", 1284 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1285 printf(" BAR number: %u\n", 1286 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1287 } 1288 1289 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1290 /* XXX pci_conf_print_hotplug_cap */ 1291 1292 static void 1293 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1294 { 1295 pcireg_t reg; 1296 1297 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1298 1299 printf("\n Subsystem ID Capability Register\n"); 1300 printf(" Subsystem ID : 0x%08x\n", reg); 1301 } 1302 1303 /* XXX pci_conf_print_agp8_cap */ 1304 /* XXX pci_conf_print_secure_cap */ 1305 1306 static void 1307 pci_print_pcie_L0s_latency(uint32_t val) 1308 { 1309 1310 switch (val) { 1311 case 0x0: 1312 printf("Less than 64ns\n"); 1313 break; 1314 case 0x1: 1315 case 0x2: 1316 case 0x3: 1317 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1318 break; 1319 case 0x4: 1320 printf("512ns to less than 1us\n"); 1321 break; 1322 case 0x5: 1323 printf("1us to less than 2us\n"); 1324 break; 1325 case 0x6: 1326 printf("2us - 4us\n"); 1327 break; 1328 case 0x7: 1329 printf("More than 4us\n"); 1330 break; 1331 } 1332 } 1333 1334 static void 1335 pci_print_pcie_L1_latency(uint32_t val) 1336 { 1337 1338 switch (val) { 1339 case 0x0: 1340 printf("Less than 1us\n"); 1341 break; 1342 case 0x6: 1343 printf("32us - 64us\n"); 1344 break; 1345 case 0x7: 1346 printf("More than 64us\n"); 1347 break; 1348 default: 1349 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1350 break; 1351 } 1352 } 1353 1354 static void 1355 pci_print_pcie_compl_timeout(uint32_t val) 1356 { 1357 1358 switch (val) { 1359 case 0x0: 1360 printf("50us to 50ms\n"); 1361 break; 1362 case 0x5: 1363 printf("16ms to 55ms\n"); 1364 break; 1365 case 0x6: 1366 printf("65ms to 210ms\n"); 1367 break; 1368 case 0x9: 1369 printf("260ms to 900ms\n"); 1370 break; 1371 case 0xa: 1372 printf("1s to 3.5s\n"); 1373 break; 1374 default: 1375 printf("unknown %u value\n", val); 1376 break; 1377 } 1378 } 1379 1380 static void 1381 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1382 { 1383 pcireg_t reg; /* for each register */ 1384 pcireg_t val; /* for each bitfield */ 1385 bool check_link = false; 1386 bool check_slot = false; 1387 bool check_rootport = false; 1388 unsigned int pciever; 1389 static const char * const linkspeeds[] = {"2.5", "5.0", "8.0"}; 1390 int i; 1391 1392 printf("\n PCI Express Capabilities Register\n"); 1393 /* Capability Register */ 1394 reg = regs[o2i(capoff)]; 1395 printf(" Capability register: %04x\n", reg >> 16); 1396 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1397 printf(" Capability version: %u\n", pciever); 1398 printf(" Device type: "); 1399 switch ((reg & 0x00f00000) >> 20) { 1400 case 0x0: 1401 printf("PCI Express Endpoint device\n"); 1402 check_link = true; 1403 break; 1404 case 0x1: 1405 printf("Legacy PCI Express Endpoint device\n"); 1406 check_link = true; 1407 break; 1408 case 0x4: 1409 printf("Root Port of PCI Express Root Complex\n"); 1410 check_link = true; 1411 check_slot = true; 1412 check_rootport = true; 1413 break; 1414 case 0x5: 1415 printf("Upstream Port of PCI Express Switch\n"); 1416 break; 1417 case 0x6: 1418 printf("Downstream Port of PCI Express Switch\n"); 1419 check_slot = true; 1420 check_rootport = true; 1421 break; 1422 case 0x7: 1423 printf("PCI Express to PCI/PCI-X Bridge\n"); 1424 break; 1425 case 0x8: 1426 printf("PCI/PCI-X to PCI Express Bridge\n"); 1427 break; 1428 case 0x9: 1429 printf("Root Complex Integrated Endpoint\n"); 1430 break; 1431 case 0xa: 1432 check_rootport = true; 1433 printf("Root Complex Event Collector\n"); 1434 break; 1435 default: 1436 printf("unknown\n"); 1437 break; 1438 } 1439 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1440 printf(" Interrupt Message Number: %x\n", 1441 (unsigned int)((reg & PCIE_XCAP_IRQ) >> 27)); 1442 1443 /* Device Capability Register */ 1444 reg = regs[o2i(capoff + PCIE_DCAP)]; 1445 printf(" Device Capabilities Register: 0x%08x\n", reg); 1446 printf(" Max Payload Size Supported: %u bytes max\n", 1447 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1448 printf(" Phantom Functions Supported: "); 1449 switch ((reg & PCIE_DCAP_PHANTOM_FUNCS) >> 3) { 1450 case 0x0: 1451 printf("not available\n"); 1452 break; 1453 case 0x1: 1454 printf("MSB\n"); 1455 break; 1456 case 0x2: 1457 printf("two MSB\n"); 1458 break; 1459 case 0x3: 1460 printf("All three bits\n"); 1461 break; 1462 } 1463 printf(" Extended Tag Field Supported: %dbit\n", 1464 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1465 printf(" Endpoint L0 Acceptable Latency: "); 1466 pci_print_pcie_L0s_latency((reg & PCIE_DCAP_L0S_LATENCY) >> 6); 1467 printf(" Endpoint L1 Acceptable Latency: "); 1468 pci_print_pcie_L1_latency((reg & PCIE_DCAP_L1_LATENCY) >> 9); 1469 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1470 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1471 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1472 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1473 printf(" Captured Slot Power Limit Value: %d\n", 1474 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18); 1475 printf(" Captured Slot Power Limit Scale: %d\n", 1476 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26); 1477 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1478 1479 /* Device Control Register */ 1480 reg = regs[o2i(capoff + PCIE_DCSR)]; 1481 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1482 onoff("Correctable Error Reporting Enable", reg, 1483 PCIE_DCSR_ENA_COR_ERR); 1484 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1485 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1486 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1487 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1488 printf(" Max Payload Size: %d byte\n", 1489 128 << (((unsigned int)(reg & PCIE_DCSR_MAX_PAYLOAD) >> 5))); 1490 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1491 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1492 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1493 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1494 printf(" Max Read Request Size: %d byte\n", 1495 128 << ((unsigned int)(reg & PCIE_DCSR_MAX_READ_REQ) >> 12)); 1496 1497 /* Device Status Register */ 1498 reg = regs[o2i(capoff + PCIE_DCSR)]; 1499 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1500 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1501 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1502 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1503 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1504 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1505 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1506 1507 if (check_link) { 1508 /* Link Capability Register */ 1509 reg = regs[o2i(capoff + PCIE_LCAP)]; 1510 printf(" Link Capabilities Register: 0x%08x\n", reg); 1511 printf(" Maximum Link Speed: "); 1512 val = reg & PCIE_LCAP_MAX_SPEED; 1513 if (val < 1 || val > 3) { 1514 printf("unknown %u value\n", val); 1515 } else { 1516 printf("%sGT/s\n", linkspeeds[val - 1]); 1517 } 1518 printf(" Maximum Link Width: x%u lanes\n", 1519 (unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4); 1520 printf(" Active State PM Support: "); 1521 val = (reg & PCIE_LCAP_ASPM) >> 10; 1522 switch (val) { 1523 case 0x1: 1524 printf("L0s Entry supported\n"); 1525 break; 1526 case 0x3: 1527 printf("L0s and L1 supported\n"); 1528 break; 1529 default: 1530 printf("Reserved value\n"); 1531 break; 1532 } 1533 printf(" L0 Exit Latency: "); 1534 pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12); 1535 printf(" L1 Exit Latency: "); 1536 pci_print_pcie_L1_latency((reg & PCIE_LCAP_L1_EXIT) >> 15); 1537 printf(" Port Number: %u\n", reg >> 24); 1538 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1539 onoff("Surprise Down Error Report", reg, 1540 PCIE_LCAP_SURPRISE_DOWN); 1541 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1542 onoff("Link BW Notification Capable", reg, 1543 PCIE_LCAP_LINK_BW_NOTIFY); 1544 onoff("ASPM Optionally Compliance", reg, 1545 PCIE_LCAP_ASPM_COMPLIANCE); 1546 1547 /* Link Control Register */ 1548 reg = regs[o2i(capoff + PCIE_LCSR)]; 1549 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1550 printf(" Active State PM Control: "); 1551 val = reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S); 1552 switch (val) { 1553 case 0: 1554 printf("disabled\n"); 1555 break; 1556 case 1: 1557 printf("L0s Entry Enabled\n"); 1558 break; 1559 case 2: 1560 printf("L1 Entry Enabled\n"); 1561 break; 1562 case 3: 1563 printf("L0s and L1 Entry Enabled\n"); 1564 break; 1565 } 1566 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1567 "128bytes", "64bytes"); 1568 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1569 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1570 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1571 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1572 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1573 onoff("Hardware Autonomous Width Disable", reg, 1574 PCIE_LCSR_HAWD); 1575 onoff("Link Bandwidth Management Interrupt Enable", reg, 1576 PCIE_LCSR_LBMIE); 1577 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1578 PCIE_LCSR_LABIE); 1579 1580 /* Link Status Register */ 1581 reg = regs[o2i(capoff + PCIE_LCSR)]; 1582 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1583 printf(" Negotiated Link Speed: "); 1584 if (((reg >> 16) & 0x000f) < 1 || 1585 ((reg >> 16) & 0x000f) > 3) { 1586 printf("unknown %u value\n", 1587 (unsigned int)(reg & PCIE_LCSR_LINKSPEED) >> 16); 1588 } else { 1589 printf("%sGT/s\n", 1590 linkspeeds[((reg & PCIE_LCSR_LINKSPEED) >> 16)-1]); 1591 } 1592 printf(" Negotiated Link Width: x%u lanes\n", 1593 (reg >> 20) & 0x003f); 1594 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1595 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1596 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1597 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1598 onoff("Link Bandwidth Management Status", reg, 1599 PCIE_LCSR_LINK_BW_MGMT); 1600 onoff("Link Autonomous Bandwidth Status", reg, 1601 PCIE_LCSR_LINK_AUTO_BW); 1602 } 1603 1604 if (check_slot == true) { 1605 /* Slot Capability Register */ 1606 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1607 printf(" Slot Capability Register: %08x\n", reg); 1608 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1609 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1610 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1611 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1612 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1613 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1614 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1615 printf(" Slot Power Limit Value: %d\n", 1616 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1617 printf(" Slot Power Limit Scale: %d\n", 1618 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1619 onoff("Electromechanical Interlock Present", reg, 1620 PCIE_SLCAP_EIP); 1621 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1622 printf(" Physical Slot Number: %d\n", 1623 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1624 1625 /* Slot Control Register */ 1626 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1627 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1628 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1629 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1630 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1631 onoff("Presense Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1632 onoff("Command Completed Interrupt Enabled", reg, 1633 PCIE_SLCSR_CCE); 1634 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1635 printf(" Attention Indicator Control: "); 1636 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1637 case 0x0: 1638 printf("reserved\n"); 1639 break; 1640 case 0x1: 1641 printf("on\n"); 1642 break; 1643 case 0x2: 1644 printf("blink\n"); 1645 break; 1646 case 0x3: 1647 printf("off\n"); 1648 break; 1649 } 1650 printf(" Power Indicator Control: "); 1651 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1652 case 0x0: 1653 printf("reserved\n"); 1654 break; 1655 case 0x1: 1656 printf("on\n"); 1657 break; 1658 case 0x2: 1659 printf("blink\n"); 1660 break; 1661 case 0x3: 1662 printf("off\n"); 1663 break; 1664 } 1665 onoff("Power Controller Control", reg, PCIE_SLCSR_PCC); 1666 onoff("Electromechanical Interlock Control", 1667 reg, PCIE_SLCSR_EIC); 1668 onoff("Data Link Layer State Changed Enable", reg, 1669 PCIE_SLCSR_DLLSCE); 1670 1671 /* Slot Status Register */ 1672 printf(" Slot Status Register: %04x\n", reg >> 16); 1673 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1674 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1675 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1676 onoff("Presense Detect Changed", reg, PCIE_SLCSR_PDC); 1677 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1678 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1679 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1680 onoff("Electromechanical Interlock engaged", reg, 1681 PCIE_SLCSR_EIS); 1682 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 1683 } 1684 1685 if (check_rootport == true) { 1686 /* Root Control Register */ 1687 reg = regs[o2i(capoff + PCIE_RCR)]; 1688 printf(" Root Control Register: %04x\n", reg & 0xffff); 1689 onoff("SERR on Correctable Error Enable", reg, 1690 PCIE_RCR_SERR_CER); 1691 onoff("SERR on Non-Fatal Error Enable", reg, 1692 PCIE_RCR_SERR_NFER); 1693 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 1694 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 1695 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 1696 1697 /* Root Capability Register */ 1698 printf(" Root Capability Register: %04x\n", 1699 reg >> 16); 1700 1701 /* Root Status Register */ 1702 reg = regs[o2i(capoff + PCIE_RSR)]; 1703 printf(" Root Status Register: %08x\n", reg); 1704 printf(" PME Requester ID: %04x\n", 1705 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1706 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 1707 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 1708 } 1709 1710 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1711 if (pciever < 2) 1712 return; 1713 1714 /* Device Capabilities 2 */ 1715 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1716 printf(" Device Capabilities 2: 0x%08x\n", reg); 1717 printf(" Completion Timeout Ranges Supported: %u \n", 1718 (unsigned int)(reg & PCIE_DCAP2_COMPT_RANGE)); 1719 onoff("Completion Timeout Disable Supported", reg, 1720 PCIE_DCAP2_COMPT_DIS); 1721 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 1722 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 1723 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 1724 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 1725 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 1726 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 1727 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 1728 printf(" TPH Completer Supported: %u\n", 1729 (unsigned int)(reg & PCIE_DCAP2_TPH_COMP) >> 12); 1730 printf(" OBFF Supported: "); 1731 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 1732 case 0x0: 1733 printf("Not supported\n"); 1734 break; 1735 case 0x1: 1736 printf("Message only\n"); 1737 break; 1738 case 0x2: 1739 printf("WAKE# only\n"); 1740 break; 1741 case 0x3: 1742 printf("Both\n"); 1743 break; 1744 } 1745 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 1746 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 1747 printf(" Max End-End TLP Prefixes: %u\n", 1748 (unsigned int)(reg & PCIE_DCAP2_MAX_EETLP) >> 22); 1749 1750 /* Device Control 2 */ 1751 reg = regs[o2i(capoff + PCIE_DCSR2)]; 1752 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 1753 printf(" Completion Timeout Value: "); 1754 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 1755 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 1756 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 1757 onoff("AtomicOp Rquester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 1758 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 1759 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 1760 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 1761 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 1762 printf(" OBFF: "); 1763 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 1764 case 0x0: 1765 printf("Disabled\n"); 1766 break; 1767 case 0x1: 1768 printf("Enabled with Message Signaling Variation A\n"); 1769 break; 1770 case 0x2: 1771 printf("Enabled with Message Signaling Variation B\n"); 1772 break; 1773 case 0x3: 1774 printf("Enabled using WAKE# signaling\n"); 1775 break; 1776 } 1777 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 1778 1779 if (check_link) { 1780 /* Link Capability 2 */ 1781 reg = regs[o2i(capoff + PCIE_LCAP2)]; 1782 printf(" Link Capabilities 2: 0x%08x\n", reg); 1783 val = (reg & PCIE_LCAP2_SUP_LNKSV) >> 1; 1784 printf(" Supported Link Speed Vector:"); 1785 for (i = 0; i <= 2; i++) { 1786 if (((val >> i) & 0x01) != 0) 1787 printf(" %sGT/s", linkspeeds[i]); 1788 } 1789 printf("\n"); 1790 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 1791 1792 /* Link Control 2 */ 1793 reg = regs[o2i(capoff + PCIE_LCSR2)]; 1794 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 1795 printf(" Target Link Speed: "); 1796 val = reg & PCIE_LCSR2_TGT_LSPEED; 1797 if (val < 1 || val > 3) 1798 printf("unknown %u value\n", val); 1799 else 1800 printf("%sGT/s\n", linkspeeds[val - 1]); 1801 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 1802 onoff("HW Autonomous Speed Disabled", reg, 1803 PCIE_LCSR2_HW_AS_DIS); 1804 onoff("Selectable De-emphasis", reg, PCIE_LCSR2_SEL_DEEMP); 1805 printf(" Transmit Margin: %u\n", 1806 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 1807 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 1808 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 1809 printf(" Compliance Present/De-emphasis: %u\n", 1810 (unsigned int)(reg & PCIE_LCSR2_COMP_DEEMP) >> 12); 1811 1812 /* Link Status 2 */ 1813 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 1814 onoff("Current De-emphasis Level", reg, PCIE_LCSR2_DEEMP_LVL); 1815 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 1816 onoff("Equalization Phase 1 Successful", reg, 1817 PCIE_LCSR2_EQP1_SUC); 1818 onoff("Equalization Phase 2 Successful", reg, 1819 PCIE_LCSR2_EQP2_SUC); 1820 onoff("Equalization Phase 3 Successful", reg, 1821 PCIE_LCSR2_EQP3_SUC); 1822 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 1823 } 1824 1825 /* Slot Capability 2 */ 1826 /* Slot Control 2 */ 1827 /* Slot Status 2 */ 1828 } 1829 1830 static void 1831 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 1832 { 1833 pcireg_t reg; 1834 1835 printf("\n MSI-X Capability Register\n"); 1836 1837 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 1838 printf(" Message Control register: 0x%04x\n", 1839 (reg >> 16) & 0xff); 1840 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 1841 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 1842 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 1843 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 1844 printf(" Table offset register: 0x%08x\n", reg); 1845 printf(" Table offset: %08x\n", reg & PCI_MSIX_TBLOFFSET_MASK); 1846 printf(" BIR: 0x%x\n", reg & PCI_MSIX_TBLBIR_MASK); 1847 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 1848 printf(" Pending bit array register: 0x%08x\n", reg); 1849 printf(" Pending bit array offset: %08x\n", 1850 reg & PCI_MSIX_PBAOFFSET_MASK); 1851 printf(" BIR: 0x%x\n", reg & PCI_MSIX_PBABIR_MASK); 1852 } 1853 1854 /* XXX pci_conf_print_sata_cap */ 1855 static void 1856 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 1857 { 1858 pcireg_t reg; 1859 1860 printf("\n Advanced Features Capability Register\n"); 1861 1862 reg = regs[o2i(capoff + PCI_AFCAPR)]; 1863 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 1864 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 1865 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 1866 reg = regs[o2i(capoff + PCI_AFCSR)]; 1867 printf(" AF Control register: 0x%02x\n", reg & 0xff); 1868 /* 1869 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 1870 * and it's always 0 on read 1871 */ 1872 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 1873 onoff("Transaction Pending", reg, PCI_AFSR_TP); 1874 } 1875 1876 static struct { 1877 pcireg_t cap; 1878 const char *name; 1879 void (*printfunc)(const pcireg_t *, int); 1880 } pci_captab[] = { 1881 { PCI_CAP_RESERVED0, "reserved", NULL }, 1882 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 1883 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 1884 { PCI_CAP_VPD, "VPD", NULL }, 1885 { PCI_CAP_SLOTID, "SlotID", NULL }, 1886 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 1887 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 1888 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 1889 { PCI_CAP_LDT, "HyperTransport", NULL }, 1890 { PCI_CAP_VENDSPEC, "Vendor-specific", 1891 pci_conf_print_vendspec_cap }, 1892 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 1893 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 1894 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 1895 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 1896 pci_conf_print_subsystem_cap }, 1897 { PCI_CAP_AGP8, "AGP 8x", NULL }, 1898 { PCI_CAP_SECURE, "Secure Device", NULL }, 1899 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 1900 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 1901 { PCI_CAP_SATA, "SATA", NULL }, 1902 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap } 1903 }; 1904 1905 static void 1906 pci_conf_print_caplist( 1907 #ifdef _KERNEL 1908 pci_chipset_tag_t pc, pcitag_t tag, 1909 #endif 1910 const pcireg_t *regs, int capoff) 1911 { 1912 int off; 1913 pcireg_t foundcap; 1914 pcireg_t rval; 1915 bool foundtable[__arraycount(pci_captab)]; 1916 unsigned int i; 1917 1918 /* Clear table */ 1919 for (i = 0; i < __arraycount(pci_captab); i++) 1920 foundtable[i] = false; 1921 1922 /* Print capability register's offset and the type first */ 1923 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1924 off != 0; 1925 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 1926 rval = regs[o2i(off)]; 1927 printf(" Capability register at 0x%02x\n", off); 1928 1929 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 1930 foundcap = PCI_CAPLIST_CAP(rval); 1931 if (foundcap < __arraycount(pci_captab)) { 1932 printf("%s)\n", pci_captab[foundcap].name); 1933 /* Mark as found */ 1934 foundtable[foundcap] = true; 1935 } else 1936 printf("unknown)\n"); 1937 } 1938 1939 /* 1940 * And then, print the detail of each capability registers 1941 * in capability value's order. 1942 */ 1943 for (i = 0; i < __arraycount(pci_captab); i++) { 1944 if (foundtable[i] == false) 1945 continue; 1946 1947 /* 1948 * The type was found. Search capability list again and 1949 * print all capabilities that the capabiliy type is 1950 * the same. This is required because some capabilities 1951 * appear multiple times (e.g. HyperTransport capability). 1952 */ 1953 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1954 off != 0; 1955 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 1956 rval = regs[o2i(off)]; 1957 foundcap = PCI_CAPLIST_CAP(rval); 1958 if ((i == foundcap) 1959 && (pci_captab[foundcap].printfunc != NULL)) 1960 pci_captab[foundcap].printfunc(regs, off); 1961 } 1962 } 1963 } 1964 1965 /* Print the Secondary Status Register. */ 1966 static void 1967 pci_conf_print_ssr(pcireg_t rval) 1968 { 1969 pcireg_t devsel; 1970 1971 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 1972 onoff("66 MHz capable", rval, __BIT(5)); 1973 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 1974 onoff("Fast back-to-back capable", rval, __BIT(7)); 1975 onoff("Data parity error detected", rval, __BIT(8)); 1976 1977 printf(" DEVSEL timing: "); 1978 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 1979 switch (devsel) { 1980 case 0: 1981 printf("fast"); 1982 break; 1983 case 1: 1984 printf("medium"); 1985 break; 1986 case 2: 1987 printf("slow"); 1988 break; 1989 default: 1990 printf("unknown/reserved"); /* XXX */ 1991 break; 1992 } 1993 printf(" (0x%x)\n", devsel); 1994 1995 onoff("Signalled target abort", rval, __BIT(11)); 1996 onoff("Received target abort", rval, __BIT(12)); 1997 onoff("Received master abort", rval, __BIT(13)); 1998 onoff("Received system error", rval, __BIT(14)); 1999 onoff("Detected parity error", rval, __BIT(15)); 2000 } 2001 2002 static void 2003 pci_conf_print_type0( 2004 #ifdef _KERNEL 2005 pci_chipset_tag_t pc, pcitag_t tag, 2006 #endif 2007 const pcireg_t *regs 2008 #ifdef _KERNEL 2009 , int sizebars 2010 #endif 2011 ) 2012 { 2013 int off, width; 2014 pcireg_t rval; 2015 2016 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 2017 #ifdef _KERNEL 2018 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 2019 #else 2020 width = pci_conf_print_bar(regs, off, NULL); 2021 #endif 2022 } 2023 2024 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 2025 2026 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 2027 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 2028 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 2029 2030 /* XXX */ 2031 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 2032 2033 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2034 printf(" Capability list pointer: 0x%02x\n", 2035 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 2036 else 2037 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 2038 2039 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 2040 2041 rval = regs[o2i(PCI_INTERRUPT_REG)]; 2042 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 2043 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 2044 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 2045 switch (PCI_INTERRUPT_PIN(rval)) { 2046 case PCI_INTERRUPT_PIN_NONE: 2047 printf("(none)"); 2048 break; 2049 case PCI_INTERRUPT_PIN_A: 2050 printf("(pin A)"); 2051 break; 2052 case PCI_INTERRUPT_PIN_B: 2053 printf("(pin B)"); 2054 break; 2055 case PCI_INTERRUPT_PIN_C: 2056 printf("(pin C)"); 2057 break; 2058 case PCI_INTERRUPT_PIN_D: 2059 printf("(pin D)"); 2060 break; 2061 default: 2062 printf("(? ? ?)"); 2063 break; 2064 } 2065 printf("\n"); 2066 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 2067 } 2068 2069 static void 2070 pci_conf_print_type1( 2071 #ifdef _KERNEL 2072 pci_chipset_tag_t pc, pcitag_t tag, 2073 #endif 2074 const pcireg_t *regs 2075 #ifdef _KERNEL 2076 , int sizebars 2077 #endif 2078 ) 2079 { 2080 int off, width; 2081 pcireg_t rval; 2082 uint32_t base, limit; 2083 uint32_t base_h, limit_h; 2084 uint64_t pbase, plimit; 2085 int use_upper; 2086 2087 /* 2088 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 2089 * Bridge chip documentation, and may not be correct with 2090 * respect to various standards. (XXX) 2091 */ 2092 2093 for (off = 0x10; off < 0x18; off += width) { 2094 #ifdef _KERNEL 2095 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 2096 #else 2097 width = pci_conf_print_bar(regs, off, NULL); 2098 #endif 2099 } 2100 2101 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 2102 printf(" Primary bus number: 0x%02x\n", 2103 PCI_BRIDGE_BUS_PRIMARY(rval)); 2104 printf(" Secondary bus number: 0x%02x\n", 2105 PCI_BRIDGE_BUS_SECONDARY(rval)); 2106 printf(" Subordinate bus number: 0x%02x\n", 2107 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 2108 printf(" Secondary bus latency timer: 0x%02x\n", 2109 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 2110 2111 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 2112 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 2113 2114 /* I/O region */ 2115 printf(" I/O region:\n"); 2116 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 2117 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 2118 if (PCI_BRIDGE_IO_32BITS(rval)) 2119 use_upper = 1; 2120 else 2121 use_upper = 0; 2122 onoff("32bit I/O", rval, use_upper); 2123 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 2124 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 2125 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 2126 limit |= 0x00000fff; 2127 2128 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 2129 base_h = (rval >> 0) & 0xffff; 2130 limit_h = (rval >> 16) & 0xffff; 2131 printf(" base upper 16 bits register: 0x%04x\n", base_h); 2132 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 2133 2134 if (use_upper == 1) { 2135 base |= base_h << 16; 2136 limit |= limit_h << 16; 2137 } 2138 if (base < limit) { 2139 if (use_upper == 1) 2140 printf(" range: 0x%08x-0x%08x\n", base, limit); 2141 else 2142 printf(" range: 0x%04x-0x%04x\n", base, limit); 2143 } else 2144 printf(" range: not set\n"); 2145 2146 /* Non-prefetchable memory region */ 2147 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 2148 printf(" Memory region:\n"); 2149 printf(" base register: 0x%04x\n", 2150 (rval >> 0) & 0xffff); 2151 printf(" limit register: 0x%04x\n", 2152 (rval >> 16) & 0xffff); 2153 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 2154 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 2155 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 2156 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 2157 if (base < limit) 2158 printf(" range: 0x%08x-0x%08x\n", base, limit); 2159 else 2160 printf(" range: not set\n"); 2161 2162 /* Prefetchable memory region */ 2163 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 2164 printf(" Prefetchable memory region:\n"); 2165 printf(" base register: 0x%04x\n", 2166 (rval >> 0) & 0xffff); 2167 printf(" limit register: 0x%04x\n", 2168 (rval >> 16) & 0xffff); 2169 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 2170 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 2171 printf(" base upper 32 bits register: 0x%08x\n", 2172 base_h); 2173 printf(" limit upper 32 bits register: 0x%08x\n", 2174 limit_h); 2175 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 2176 use_upper = 1; 2177 else 2178 use_upper = 0; 2179 onoff("64bit memory address", rval, use_upper); 2180 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 2181 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 2182 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 2183 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 2184 if (use_upper == 1) { 2185 pbase |= (uint64_t)base_h << 32; 2186 plimit |= (uint64_t)limit_h << 32; 2187 } 2188 if (pbase < plimit) { 2189 if (use_upper == 1) 2190 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 2191 "\n", pbase, plimit); 2192 else 2193 printf(" range: 0x%08x-0x%08x\n", 2194 (uint32_t)pbase, (uint32_t)plimit); 2195 } else 2196 printf(" range: not set\n"); 2197 2198 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2199 printf(" Capability list pointer: 0x%02x\n", 2200 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 2201 else 2202 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 2203 2204 /* XXX */ 2205 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 2206 2207 rval = regs[o2i(PCI_INTERRUPT_REG)]; 2208 printf(" Interrupt line: 0x%02x\n", 2209 (rval >> 0) & 0xff); 2210 printf(" Interrupt pin: 0x%02x ", 2211 (rval >> 8) & 0xff); 2212 switch ((rval >> 8) & 0xff) { 2213 case PCI_INTERRUPT_PIN_NONE: 2214 printf("(none)"); 2215 break; 2216 case PCI_INTERRUPT_PIN_A: 2217 printf("(pin A)"); 2218 break; 2219 case PCI_INTERRUPT_PIN_B: 2220 printf("(pin B)"); 2221 break; 2222 case PCI_INTERRUPT_PIN_C: 2223 printf("(pin C)"); 2224 break; 2225 case PCI_INTERRUPT_PIN_D: 2226 printf("(pin D)"); 2227 break; 2228 default: 2229 printf("(? ? ?)"); 2230 break; 2231 } 2232 printf("\n"); 2233 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 2234 & PCI_BRIDGE_CONTROL_MASK; 2235 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 2236 onoff("Parity error response", rval, 0x0001); 2237 onoff("Secondary SERR forwarding", rval, 0x0002); 2238 onoff("ISA enable", rval, 0x0004); 2239 onoff("VGA enable", rval, 0x0008); 2240 onoff("Master abort reporting", rval, 0x0020); 2241 onoff("Secondary bus reset", rval, 0x0040); 2242 onoff("Fast back-to-back capable", rval, 0x0080); 2243 } 2244 2245 static void 2246 pci_conf_print_type2( 2247 #ifdef _KERNEL 2248 pci_chipset_tag_t pc, pcitag_t tag, 2249 #endif 2250 const pcireg_t *regs 2251 #ifdef _KERNEL 2252 , int sizebars 2253 #endif 2254 ) 2255 { 2256 pcireg_t rval; 2257 2258 /* 2259 * XXX these need to be printed in more detail, need to be 2260 * XXX checked against specs/docs, etc. 2261 * 2262 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 2263 * controller chip documentation, and may not be correct with 2264 * respect to various standards. (XXX) 2265 */ 2266 2267 #ifdef _KERNEL 2268 pci_conf_print_bar(pc, tag, regs, 0x10, 2269 "CardBus socket/ExCA registers", sizebars); 2270 #else 2271 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 2272 #endif 2273 2274 /* Capability list pointer and secondary status register */ 2275 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 2276 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2277 printf(" Capability list pointer: 0x%02x\n", 2278 PCI_CAPLIST_PTR(rval)); 2279 else 2280 printf(" Reserved @ 0x14: 0x%04" PRIxMAX "\n", 2281 __SHIFTOUT(rval, __BITS(15, 0))); 2282 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 2283 2284 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 2285 printf(" PCI bus number: 0x%02x\n", 2286 (rval >> 0) & 0xff); 2287 printf(" CardBus bus number: 0x%02x\n", 2288 (rval >> 8) & 0xff); 2289 printf(" Subordinate bus number: 0x%02x\n", 2290 (rval >> 16) & 0xff); 2291 printf(" CardBus latency timer: 0x%02x\n", 2292 (rval >> 24) & 0xff); 2293 2294 /* XXX Print more prettily */ 2295 printf(" CardBus memory region 0:\n"); 2296 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 2297 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 2298 printf(" CardBus memory region 1:\n"); 2299 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 2300 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 2301 printf(" CardBus I/O region 0:\n"); 2302 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 2303 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 2304 printf(" CardBus I/O region 1:\n"); 2305 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 2306 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 2307 2308 rval = regs[o2i(PCI_INTERRUPT_REG)]; 2309 printf(" Interrupt line: 0x%02x\n", 2310 (rval >> 0) & 0xff); 2311 printf(" Interrupt pin: 0x%02x ", 2312 (rval >> 8) & 0xff); 2313 switch ((rval >> 8) & 0xff) { 2314 case PCI_INTERRUPT_PIN_NONE: 2315 printf("(none)"); 2316 break; 2317 case PCI_INTERRUPT_PIN_A: 2318 printf("(pin A)"); 2319 break; 2320 case PCI_INTERRUPT_PIN_B: 2321 printf("(pin B)"); 2322 break; 2323 case PCI_INTERRUPT_PIN_C: 2324 printf("(pin C)"); 2325 break; 2326 case PCI_INTERRUPT_PIN_D: 2327 printf("(pin D)"); 2328 break; 2329 default: 2330 printf("(? ? ?)"); 2331 break; 2332 } 2333 printf("\n"); 2334 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 2335 printf(" Bridge control register: 0x%04x\n", rval); 2336 onoff("Parity error response", rval, __BIT(0)); 2337 onoff("SERR# enable", rval, __BIT(1)); 2338 onoff("ISA enable", rval, __BIT(2)); 2339 onoff("VGA enable", rval, __BIT(3)); 2340 onoff("Master abort mode", rval, __BIT(5)); 2341 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 2342 onoff("Functional interrupts routed by ExCA registers", rval, 2343 __BIT(7)); 2344 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 2345 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 2346 onoff("Write posting enable", rval, __BIT(10)); 2347 2348 rval = regs[o2i(0x40)]; 2349 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 2350 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 2351 2352 #ifdef _KERNEL 2353 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 2354 sizebars); 2355 #else 2356 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 2357 #endif 2358 } 2359 2360 void 2361 pci_conf_print( 2362 #ifdef _KERNEL 2363 pci_chipset_tag_t pc, pcitag_t tag, 2364 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 2365 #else 2366 int pcifd, u_int bus, u_int dev, u_int func 2367 #endif 2368 ) 2369 { 2370 pcireg_t regs[o2i(256)]; 2371 int off, capoff, endoff, hdrtype; 2372 const char *typename; 2373 #ifdef _KERNEL 2374 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, 2375 int); 2376 int sizebars; 2377 #else 2378 void (*typeprintfn)(const pcireg_t *); 2379 #endif 2380 2381 printf("PCI configuration registers:\n"); 2382 2383 for (off = 0; off < 256; off += 4) { 2384 #ifdef _KERNEL 2385 regs[o2i(off)] = pci_conf_read(pc, tag, off); 2386 #else 2387 if (pcibus_conf_read(pcifd, bus, dev, func, off, 2388 ®s[o2i(off)]) == -1) 2389 regs[o2i(off)] = 0; 2390 #endif 2391 } 2392 2393 #ifdef _KERNEL 2394 sizebars = 1; 2395 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 2396 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 2397 sizebars = 0; 2398 #endif 2399 2400 /* common header */ 2401 printf(" Common header:\n"); 2402 pci_conf_print_regs(regs, 0, 16); 2403 2404 printf("\n"); 2405 #ifdef _KERNEL 2406 pci_conf_print_common(pc, tag, regs); 2407 #else 2408 pci_conf_print_common(regs); 2409 #endif 2410 printf("\n"); 2411 2412 /* type-dependent header */ 2413 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 2414 switch (hdrtype) { /* XXX make a table, eventually */ 2415 case 0: 2416 /* Standard device header */ 2417 typename = "\"normal\" device"; 2418 typeprintfn = &pci_conf_print_type0; 2419 capoff = PCI_CAPLISTPTR_REG; 2420 endoff = 64; 2421 break; 2422 case 1: 2423 /* PCI-PCI bridge header */ 2424 typename = "PCI-PCI bridge"; 2425 typeprintfn = &pci_conf_print_type1; 2426 capoff = PCI_CAPLISTPTR_REG; 2427 endoff = 64; 2428 break; 2429 case 2: 2430 /* PCI-CardBus bridge header */ 2431 typename = "PCI-CardBus bridge"; 2432 typeprintfn = &pci_conf_print_type2; 2433 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 2434 endoff = 72; 2435 break; 2436 default: 2437 typename = NULL; 2438 typeprintfn = 0; 2439 capoff = -1; 2440 endoff = 64; 2441 break; 2442 } 2443 printf(" Type %d ", hdrtype); 2444 if (typename != NULL) 2445 printf("(%s) ", typename); 2446 printf("header:\n"); 2447 pci_conf_print_regs(regs, 16, endoff); 2448 printf("\n"); 2449 if (typeprintfn) { 2450 #ifdef _KERNEL 2451 (*typeprintfn)(pc, tag, regs, sizebars); 2452 #else 2453 (*typeprintfn)(regs); 2454 #endif 2455 } else 2456 printf(" Don't know how to pretty-print type %d header.\n", 2457 hdrtype); 2458 printf("\n"); 2459 2460 /* capability list, if present */ 2461 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2462 && (capoff > 0)) { 2463 #ifdef _KERNEL 2464 pci_conf_print_caplist(pc, tag, regs, capoff); 2465 #else 2466 pci_conf_print_caplist(regs, capoff); 2467 #endif 2468 printf("\n"); 2469 } 2470 2471 /* device-dependent header */ 2472 printf(" Device-dependent header:\n"); 2473 pci_conf_print_regs(regs, endoff, 256); 2474 printf("\n"); 2475 #ifdef _KERNEL 2476 if (printfn) 2477 (*printfn)(pc, tag, regs); 2478 else 2479 printf(" Don't know how to pretty-print device-dependent header.\n"); 2480 printf("\n"); 2481 #endif /* _KERNEL */ 2482 } 2483
Indexes created Tue Sep 30 11:09:46 GMT 2025