pci_subr.c revision 1.124.2.3
1 /* $NetBSD: pci_subr.c,v 1.124.2.3 2016/12/09 04:56:25 snj Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.124.2.3 2016/12/09 04:56:25 snj Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdarg.h> 58 #include <stdbool.h> 59 #include <stdio.h> 60 #include <string.h> 61 #endif 62 63 #include <dev/pci/pcireg.h> 64 #ifdef _KERNEL 65 #include <dev/pci/pcivar.h> 66 #endif 67 68 /* 69 * Descriptions of known PCI classes and subclasses. 70 * 71 * Subclasses are described in the same way as classes, but have a 72 * NULL subclass pointer. 73 */ 74 struct pci_class { 75 const char *name; 76 u_int val; /* as wide as pci_{,sub}class_t */ 77 const struct pci_class *subclasses; 78 }; 79 80 /* 81 * Class 0x00. 82 * Before rev. 2.0. 83 */ 84 static const struct pci_class pci_subclass_prehistoric[] = { 85 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 86 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 87 { NULL, 0, NULL, }, 88 }; 89 90 /* 91 * Class 0x01. 92 * Mass storage controller 93 */ 94 95 /* ATA programming interface */ 96 static const struct pci_class pci_interface_ata[] = { 97 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 98 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 99 { NULL, 0, NULL, }, 100 }; 101 102 /* SATA programming interface */ 103 static const struct pci_class pci_interface_sata[] = { 104 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 105 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 106 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 107 { NULL, 0, NULL, }, 108 }; 109 110 /* Flash programming interface */ 111 static const struct pci_class pci_interface_nvm[] = { 112 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 113 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 114 { NULL, 0, NULL, }, 115 }; 116 117 /* Subclasses */ 118 static const struct pci_class pci_subclass_mass_storage[] = { 119 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 120 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 121 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 122 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 123 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 124 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 125 pci_interface_ata, }, 126 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 127 pci_interface_sata, }, 128 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 129 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 130 pci_interface_nvm, }, 131 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 132 { NULL, 0, NULL, }, 133 }; 134 135 /* 136 * Class 0x02. 137 * Network controller. 138 */ 139 static const struct pci_class pci_subclass_network[] = { 140 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 141 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 142 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 143 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 144 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 145 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 146 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 147 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 148 { NULL, 0, NULL, }, 149 }; 150 151 /* 152 * Class 0x03. 153 * Display controller. 154 */ 155 156 /* VGA programming interface */ 157 static const struct pci_class pci_interface_vga[] = { 158 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 159 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 160 { NULL, 0, NULL, }, 161 }; 162 /* Subclasses */ 163 static const struct pci_class pci_subclass_display[] = { 164 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 165 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 166 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 167 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 168 { NULL, 0, NULL, }, 169 }; 170 171 /* 172 * Class 0x04. 173 * Multimedia device. 174 */ 175 static const struct pci_class pci_subclass_multimedia[] = { 176 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 177 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 178 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 179 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 180 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 181 { NULL, 0, NULL, }, 182 }; 183 184 /* 185 * Class 0x05. 186 * Memory controller. 187 */ 188 static const struct pci_class pci_subclass_memory[] = { 189 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 190 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 191 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 192 { NULL, 0, NULL, }, 193 }; 194 195 /* 196 * Class 0x06. 197 * Bridge device. 198 */ 199 200 /* PCI bridge programming interface */ 201 static const struct pci_class pci_interface_pcibridge[] = { 202 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 203 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 204 { NULL, 0, NULL, }, 205 }; 206 207 /* Semi-transparent PCI-to-PCI bridge programming interface */ 208 static const struct pci_class pci_interface_stpci[] = { 209 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 210 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 211 { NULL, 0, NULL, }, 212 }; 213 214 /* Advanced Switching programming interface */ 215 static const struct pci_class pci_interface_advsw[] = { 216 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 217 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 218 { NULL, 0, NULL, }, 219 }; 220 221 /* Subclasses */ 222 static const struct pci_class pci_subclass_bridge[] = { 223 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 224 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 225 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 226 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 227 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 228 pci_interface_pcibridge, }, 229 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 230 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 231 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 232 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 233 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 234 pci_interface_stpci, }, 235 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 236 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 237 pci_interface_advsw, }, 238 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 239 { NULL, 0, NULL, }, 240 }; 241 242 /* 243 * Class 0x07. 244 * Simple communications controller. 245 */ 246 247 /* Serial controller programming interface */ 248 static const struct pci_class pci_interface_serial[] = { 249 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 250 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 251 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 252 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 253 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 254 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 255 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 256 { NULL, 0, NULL, }, 257 }; 258 259 /* Parallel controller programming interface */ 260 static const struct pci_class pci_interface_parallel[] = { 261 { "", PCI_INTERFACE_PARALLEL, NULL,}, 262 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 263 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 264 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 265 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 266 { NULL, 0, NULL,}, 267 }; 268 269 /* Modem programming interface */ 270 static const struct pci_class pci_interface_modem[] = { 271 { "", PCI_INTERFACE_MODEM, NULL,}, 272 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 273 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 274 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 275 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 276 { NULL, 0, NULL,}, 277 }; 278 279 /* Subclasses */ 280 static const struct pci_class pci_subclass_communications[] = { 281 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 282 pci_interface_serial, }, 283 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 284 pci_interface_parallel, }, 285 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 286 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 287 pci_interface_modem, }, 288 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 289 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 290 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 291 { NULL, 0, NULL,}, 292 }; 293 294 /* 295 * Class 0x08. 296 * Base system peripheral. 297 */ 298 299 /* PIC programming interface */ 300 static const struct pci_class pci_interface_pic[] = { 301 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 302 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 303 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 304 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 305 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 306 { NULL, 0, NULL, }, 307 }; 308 309 /* DMA programming interface */ 310 static const struct pci_class pci_interface_dma[] = { 311 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 312 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 313 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 314 { NULL, 0, NULL, }, 315 }; 316 317 /* Timer programming interface */ 318 static const struct pci_class pci_interface_tmr[] = { 319 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 320 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 321 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 322 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 323 { NULL, 0, NULL, }, 324 }; 325 326 /* RTC programming interface */ 327 static const struct pci_class pci_interface_rtc[] = { 328 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 329 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 330 { NULL, 0, NULL, }, 331 }; 332 333 /* Subclasses */ 334 static const struct pci_class pci_subclass_system[] = { 335 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 336 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 337 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 338 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 339 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 340 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 341 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 342 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 343 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 344 { NULL, 0, NULL, }, 345 }; 346 347 /* 348 * Class 0x09. 349 * Input device. 350 */ 351 352 /* Gameport programming interface */ 353 static const struct pci_class pci_interface_game[] = { 354 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 355 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 356 { NULL, 0, NULL, }, 357 }; 358 359 /* Subclasses */ 360 static const struct pci_class pci_subclass_input[] = { 361 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 362 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 363 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 364 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 365 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 366 pci_interface_game, }, 367 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 368 { NULL, 0, NULL, }, 369 }; 370 371 /* 372 * Class 0x0a. 373 * Docking station. 374 */ 375 static const struct pci_class pci_subclass_dock[] = { 376 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 377 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 378 { NULL, 0, NULL, }, 379 }; 380 381 /* 382 * Class 0x0b. 383 * Processor. 384 */ 385 static const struct pci_class pci_subclass_processor[] = { 386 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 387 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 388 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 389 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 390 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 391 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 392 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 393 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 394 { NULL, 0, NULL, }, 395 }; 396 397 /* 398 * Class 0x0c. 399 * Serial bus controller. 400 */ 401 402 /* IEEE1394 programming interface */ 403 static const struct pci_class pci_interface_ieee1394[] = { 404 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 405 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 406 { NULL, 0, NULL,}, 407 }; 408 409 /* USB programming interface */ 410 static const struct pci_class pci_interface_usb[] = { 411 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 412 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 413 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 414 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 415 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 416 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 417 { NULL, 0, NULL, }, 418 }; 419 420 /* IPMI programming interface */ 421 static const struct pci_class pci_interface_ipmi[] = { 422 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 423 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 424 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 425 { NULL, 0, NULL,}, 426 }; 427 428 /* Subclasses */ 429 static const struct pci_class pci_subclass_serialbus[] = { 430 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 431 pci_interface_ieee1394, }, 432 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 433 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 434 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 435 pci_interface_usb, }, 436 /* XXX Fiber Channel/_FIBRECHANNEL */ 437 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 438 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 439 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 440 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 441 pci_interface_ipmi, }, 442 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 443 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 444 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 445 { NULL, 0, NULL, }, 446 }; 447 448 /* 449 * Class 0x0d. 450 * Wireless Controller. 451 */ 452 static const struct pci_class pci_subclass_wireless[] = { 453 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 454 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 455 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 456 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 457 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 458 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 459 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 460 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 461 { NULL, 0, NULL, }, 462 }; 463 464 /* 465 * Class 0x0e. 466 * Intelligent IO controller. 467 */ 468 469 /* Intelligent IO programming interface */ 470 static const struct pci_class pci_interface_i2o[] = { 471 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 472 { NULL, 0, NULL,}, 473 }; 474 475 /* Subclasses */ 476 static const struct pci_class pci_subclass_i2o[] = { 477 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 478 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 479 { NULL, 0, NULL, }, 480 }; 481 482 /* 483 * Class 0x0f. 484 * Satellite communication controller. 485 */ 486 static const struct pci_class pci_subclass_satcom[] = { 487 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 488 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 489 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 490 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 491 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 492 { NULL, 0, NULL, }, 493 }; 494 495 /* 496 * Class 0x10. 497 * Encryption/Decryption controller. 498 */ 499 static const struct pci_class pci_subclass_crypto[] = { 500 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 501 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 502 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 503 { NULL, 0, NULL, }, 504 }; 505 506 /* 507 * Class 0x11. 508 * Data aquuisition and signal processing controller. 509 */ 510 static const struct pci_class pci_subclass_dasp[] = { 511 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 512 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 513 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 514 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 515 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 516 { NULL, 0, NULL, }, 517 }; 518 519 /* List of classes */ 520 static const struct pci_class pci_class[] = { 521 { "prehistoric", PCI_CLASS_PREHISTORIC, 522 pci_subclass_prehistoric, }, 523 { "mass storage", PCI_CLASS_MASS_STORAGE, 524 pci_subclass_mass_storage, }, 525 { "network", PCI_CLASS_NETWORK, 526 pci_subclass_network, }, 527 { "display", PCI_CLASS_DISPLAY, 528 pci_subclass_display, }, 529 { "multimedia", PCI_CLASS_MULTIMEDIA, 530 pci_subclass_multimedia, }, 531 { "memory", PCI_CLASS_MEMORY, 532 pci_subclass_memory, }, 533 { "bridge", PCI_CLASS_BRIDGE, 534 pci_subclass_bridge, }, 535 { "communications", PCI_CLASS_COMMUNICATIONS, 536 pci_subclass_communications, }, 537 { "system", PCI_CLASS_SYSTEM, 538 pci_subclass_system, }, 539 { "input", PCI_CLASS_INPUT, 540 pci_subclass_input, }, 541 { "dock", PCI_CLASS_DOCK, 542 pci_subclass_dock, }, 543 { "processor", PCI_CLASS_PROCESSOR, 544 pci_subclass_processor, }, 545 { "serial bus", PCI_CLASS_SERIALBUS, 546 pci_subclass_serialbus, }, 547 { "wireless", PCI_CLASS_WIRELESS, 548 pci_subclass_wireless, }, 549 { "I2O", PCI_CLASS_I2O, 550 pci_subclass_i2o, }, 551 { "satellite comm", PCI_CLASS_SATCOM, 552 pci_subclass_satcom, }, 553 { "crypto", PCI_CLASS_CRYPTO, 554 pci_subclass_crypto, }, 555 { "DASP", PCI_CLASS_DASP, 556 pci_subclass_dasp, }, 557 { "undefined", PCI_CLASS_UNDEFINED, 558 NULL, }, 559 { NULL, 0, 560 NULL, }, 561 }; 562 563 void pci_load_verbose(void); 564 565 #if defined(_KERNEL) 566 /* 567 * In kernel, these routines are provided and linked via the 568 * pciverbose module. 569 */ 570 const char *pci_findvendor_stub(pcireg_t); 571 const char *pci_findproduct_stub(pcireg_t); 572 573 const char *(*pci_findvendor)(pcireg_t) = pci_findvendor_stub; 574 const char *(*pci_findproduct)(pcireg_t) = pci_findproduct_stub; 575 const char *pci_unmatched = ""; 576 #else 577 /* 578 * For userland we just set the vectors here. 579 */ 580 const char *(*pci_findvendor)(pcireg_t id_reg) = pci_findvendor_real; 581 const char *(*pci_findproduct)(pcireg_t id_reg) = pci_findproduct_real; 582 const char *pci_unmatched = "unmatched "; 583 #endif 584 585 int pciverbose_loaded = 0; 586 587 #if defined(_KERNEL) 588 /* 589 * Routine to load the pciverbose kernel module as needed 590 */ 591 void 592 pci_load_verbose(void) 593 { 594 595 if (pciverbose_loaded == 0) 596 module_autoload("pciverbose", MODULE_CLASS_MISC); 597 } 598 599 const char * 600 pci_findvendor_stub(pcireg_t id_reg) 601 { 602 603 pci_load_verbose(); 604 if (pciverbose_loaded) 605 return pci_findvendor(id_reg); 606 else 607 return NULL; 608 } 609 610 const char * 611 pci_findproduct_stub(pcireg_t id_reg) 612 { 613 614 pci_load_verbose(); 615 if (pciverbose_loaded) 616 return pci_findproduct(id_reg); 617 else 618 return NULL; 619 } 620 #endif 621 622 /* 623 * Append a formatted string to dest without writing more than len 624 * characters (including the trailing NUL character). dest and len 625 * are updated for use in subsequent calls to snappendf(). 626 * 627 * Returns 0 on success, a negative value if vnsprintf() fails, or 628 * a positive value if the dest buffer would have overflowed. 629 */ 630 631 static int __printflike(3,4) 632 snappendf(char **dest, size_t *len, const char * restrict fmt, ...) 633 { 634 va_list ap; 635 int count; 636 637 va_start(ap, fmt); 638 count = vsnprintf(*dest, *len, fmt, ap); 639 va_end(ap); 640 641 /* Let vsnprintf() errors bubble up to caller */ 642 if (count < 0 || *len == 0) 643 return count; 644 645 /* Handle overflow */ 646 if ((size_t)count >= *len) { 647 *dest += *len - 1; 648 *len = 1; 649 return 1; 650 } 651 652 /* Update dest & len to point at trailing NUL */ 653 *dest += count; 654 *len -= count; 655 656 return 0; 657 } 658 659 void 660 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 661 size_t l) 662 { 663 pci_vendor_id_t vendor; 664 pci_product_id_t product; 665 pci_class_t class; 666 pci_subclass_t subclass; 667 pci_interface_t interface; 668 pci_revision_t revision; 669 const char *unmatched = pci_unmatched; 670 const char *vendor_namep, *product_namep; 671 const struct pci_class *classp, *subclassp, *interfacep; 672 673 vendor = PCI_VENDOR(id_reg); 674 product = PCI_PRODUCT(id_reg); 675 676 class = PCI_CLASS(class_reg); 677 subclass = PCI_SUBCLASS(class_reg); 678 interface = PCI_INTERFACE(class_reg); 679 revision = PCI_REVISION(class_reg); 680 681 vendor_namep = pci_findvendor(id_reg); 682 product_namep = pci_findproduct(id_reg); 683 684 classp = pci_class; 685 while (classp->name != NULL) { 686 if (class == classp->val) 687 break; 688 classp++; 689 } 690 691 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 692 while (subclassp && subclassp->name != NULL) { 693 if (subclass == subclassp->val) 694 break; 695 subclassp++; 696 } 697 698 interfacep = (subclassp && subclassp->name != NULL) ? 699 subclassp->subclasses : NULL; 700 while (interfacep && interfacep->name != NULL) { 701 if (interface == interfacep->val) 702 break; 703 interfacep++; 704 } 705 706 if (vendor_namep == NULL) 707 (void)snappendf(&cp, &l, "%svendor 0x%04x product 0x%04x", 708 unmatched, vendor, product); 709 else if (product_namep != NULL) 710 (void)snappendf(&cp, &l, "%s %s", vendor_namep, product_namep); 711 else 712 (void)snappendf(&cp, &l, "%s product 0x%04x", 713 vendor_namep, product); 714 if (showclass) { 715 (void)snappendf(&cp, &l, " ("); 716 if (classp->name == NULL) 717 (void)snappendf(&cp, &l, 718 "class 0x%02x, subclass 0x%02x", class, subclass); 719 else { 720 if (subclassp == NULL || subclassp->name == NULL) 721 (void)snappendf(&cp, &l, "%s, subclass 0x%02x", 722 classp->name, subclass); 723 else 724 (void)snappendf(&cp, &l, "%s %s", 725 subclassp->name, classp->name); 726 } 727 if ((interfacep == NULL) || (interfacep->name == NULL)) { 728 if (interface != 0) 729 (void)snappendf(&cp, &l, ", interface 0x%02x", 730 interface); 731 } else if (strncmp(interfacep->name, "", 1) != 0) 732 (void)snappendf(&cp, &l, ", %s", interfacep->name); 733 if (revision != 0) 734 (void)snappendf(&cp, &l, ", revision 0x%02x", revision); 735 (void)snappendf(&cp, &l, ")"); 736 } 737 } 738 739 #ifdef _KERNEL 740 void 741 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 742 const char *known, int addrev) 743 { 744 char devinfo[256]; 745 746 if (known) { 747 aprint_normal(": %s", known); 748 if (addrev) 749 aprint_normal(" (rev. 0x%02x)", 750 PCI_REVISION(pa->pa_class)); 751 aprint_normal("\n"); 752 } else { 753 pci_devinfo(pa->pa_id, pa->pa_class, 0, 754 devinfo, sizeof(devinfo)); 755 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 756 PCI_REVISION(pa->pa_class)); 757 } 758 if (naive) 759 aprint_naive(": %s\n", naive); 760 else 761 aprint_naive("\n"); 762 } 763 #endif 764 765 /* 766 * Print out most of the PCI configuration registers. Typically used 767 * in a device attach routine like this: 768 * 769 * #ifdef MYDEV_DEBUG 770 * printf("%s: ", device_xname(sc->sc_dev)); 771 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 772 * #endif 773 */ 774 775 #define i2o(i) ((i) * 4) 776 #define o2i(o) ((o) / 4) 777 #define onoff2(str, rval, bit, onstr, offstr) \ 778 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 779 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 780 781 static void 782 pci_conf_print_common( 783 #ifdef _KERNEL 784 pci_chipset_tag_t pc, pcitag_t tag, 785 #endif 786 const pcireg_t *regs) 787 { 788 const char *name; 789 const struct pci_class *classp, *subclassp; 790 pcireg_t rval; 791 unsigned int num; 792 793 rval = regs[o2i(PCI_ID_REG)]; 794 name = pci_findvendor(rval); 795 if (name) 796 printf(" Vendor Name: %s (0x%04x)\n", name, 797 PCI_VENDOR(rval)); 798 else 799 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 800 name = pci_findproduct(rval); 801 if (name) 802 printf(" Device Name: %s (0x%04x)\n", name, 803 PCI_PRODUCT(rval)); 804 else 805 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 806 807 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 808 809 printf(" Command register: 0x%04x\n", rval & 0xffff); 810 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 811 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 812 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 813 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 814 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 815 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 816 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 817 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 818 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 819 onoff("Fast back-to-back transactions", rval, 820 PCI_COMMAND_BACKTOBACK_ENABLE); 821 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 822 823 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 824 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 825 "inactive"); 826 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 827 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 828 onoff("User Definable Features (UDF) support", rval, 829 PCI_STATUS_UDF_SUPPORT); 830 onoff("Fast back-to-back capable", rval, 831 PCI_STATUS_BACKTOBACK_SUPPORT); 832 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 833 834 printf(" DEVSEL timing: "); 835 switch (rval & PCI_STATUS_DEVSEL_MASK) { 836 case PCI_STATUS_DEVSEL_FAST: 837 printf("fast"); 838 break; 839 case PCI_STATUS_DEVSEL_MEDIUM: 840 printf("medium"); 841 break; 842 case PCI_STATUS_DEVSEL_SLOW: 843 printf("slow"); 844 break; 845 default: 846 printf("unknown/reserved"); /* XXX */ 847 break; 848 } 849 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 850 851 onoff("Slave signaled Target Abort", rval, 852 PCI_STATUS_TARGET_TARGET_ABORT); 853 onoff("Master received Target Abort", rval, 854 PCI_STATUS_MASTER_TARGET_ABORT); 855 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 856 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 857 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 858 859 rval = regs[o2i(PCI_CLASS_REG)]; 860 for (classp = pci_class; classp->name != NULL; classp++) { 861 if (PCI_CLASS(rval) == classp->val) 862 break; 863 } 864 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 865 while (subclassp && subclassp->name != NULL) { 866 if (PCI_SUBCLASS(rval) == subclassp->val) 867 break; 868 subclassp++; 869 } 870 if (classp->name != NULL) { 871 printf(" Class Name: %s (0x%02x)\n", classp->name, 872 PCI_CLASS(rval)); 873 if (subclassp != NULL && subclassp->name != NULL) 874 printf(" Subclass Name: %s (0x%02x)\n", 875 subclassp->name, PCI_SUBCLASS(rval)); 876 else 877 printf(" Subclass ID: 0x%02x\n", 878 PCI_SUBCLASS(rval)); 879 } else { 880 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 881 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 882 } 883 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 884 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 885 886 rval = regs[o2i(PCI_BHLC_REG)]; 887 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 888 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 889 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 890 PCI_HDRTYPE(rval)); 891 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 892 num = PCI_CACHELINE(rval); 893 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 894 } 895 896 static int 897 pci_conf_print_bar( 898 #ifdef _KERNEL 899 pci_chipset_tag_t pc, pcitag_t tag, 900 #endif 901 const pcireg_t *regs, int reg, const char *name 902 #ifdef _KERNEL 903 , int sizebar 904 #endif 905 ) 906 { 907 int width; 908 pcireg_t rval, rval64h; 909 #ifdef _KERNEL 910 int s; 911 pcireg_t mask, mask64h; 912 #endif 913 914 width = 4; 915 916 /* 917 * Section 6.2.5.1, `Address Maps', tells us that: 918 * 919 * 1) The builtin software should have already mapped the 920 * device in a reasonable way. 921 * 922 * 2) A device which wants 2^n bytes of memory will hardwire 923 * the bottom n bits of the address to 0. As recommended, 924 * we write all 1s and see what we get back. 925 */ 926 927 rval = regs[o2i(reg)]; 928 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 929 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 930 rval64h = regs[o2i(reg + 4)]; 931 width = 8; 932 } else 933 rval64h = 0; 934 935 #ifdef _KERNEL 936 /* XXX don't size unknown memory type? */ 937 if (rval != 0 && sizebar) { 938 /* 939 * The following sequence seems to make some devices 940 * (e.g. host bus bridges, which don't normally 941 * have their space mapped) very unhappy, to 942 * the point of crashing the system. 943 * 944 * Therefore, if the mapping register is zero to 945 * start out with, don't bother trying. 946 */ 947 s = splhigh(); 948 pci_conf_write(pc, tag, reg, 0xffffffff); 949 mask = pci_conf_read(pc, tag, reg); 950 pci_conf_write(pc, tag, reg, rval); 951 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 952 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 953 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 954 mask64h = pci_conf_read(pc, tag, reg + 4); 955 pci_conf_write(pc, tag, reg + 4, rval64h); 956 } else 957 mask64h = 0; 958 splx(s); 959 } else 960 mask = mask64h = 0; 961 #endif /* _KERNEL */ 962 963 printf(" Base address register at 0x%02x", reg); 964 if (name) 965 printf(" (%s)", name); 966 printf("\n "); 967 if (rval == 0) { 968 printf("not implemented(?)\n"); 969 return width; 970 } 971 printf("type: "); 972 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 973 const char *type, *prefetch; 974 975 switch (PCI_MAPREG_MEM_TYPE(rval)) { 976 case PCI_MAPREG_MEM_TYPE_32BIT: 977 type = "32-bit"; 978 break; 979 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 980 type = "32-bit-1M"; 981 break; 982 case PCI_MAPREG_MEM_TYPE_64BIT: 983 type = "64-bit"; 984 break; 985 default: 986 type = "unknown (XXX)"; 987 break; 988 } 989 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 990 prefetch = ""; 991 else 992 prefetch = "non"; 993 printf("%s %sprefetchable memory\n", type, prefetch); 994 switch (PCI_MAPREG_MEM_TYPE(rval)) { 995 case PCI_MAPREG_MEM_TYPE_64BIT: 996 printf(" base: 0x%016llx, ", 997 PCI_MAPREG_MEM64_ADDR( 998 ((((long long) rval64h) << 32) | rval))); 999 #ifdef _KERNEL 1000 if (sizebar) 1001 printf("size: 0x%016llx", 1002 PCI_MAPREG_MEM64_SIZE( 1003 ((((long long) mask64h) << 32) | mask))); 1004 else 1005 #endif /* _KERNEL */ 1006 printf("not sized"); 1007 printf("\n"); 1008 break; 1009 case PCI_MAPREG_MEM_TYPE_32BIT: 1010 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 1011 default: 1012 printf(" base: 0x%08x, ", 1013 PCI_MAPREG_MEM_ADDR(rval)); 1014 #ifdef _KERNEL 1015 if (sizebar) 1016 printf("size: 0x%08x", 1017 PCI_MAPREG_MEM_SIZE(mask)); 1018 else 1019 #endif /* _KERNEL */ 1020 printf("not sized"); 1021 printf("\n"); 1022 break; 1023 } 1024 } else { 1025 #ifdef _KERNEL 1026 if (sizebar) 1027 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 1028 #endif /* _KERNEL */ 1029 printf("i/o\n"); 1030 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 1031 #ifdef _KERNEL 1032 if (sizebar) 1033 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 1034 else 1035 #endif /* _KERNEL */ 1036 printf("not sized"); 1037 printf("\n"); 1038 } 1039 1040 return width; 1041 } 1042 1043 static void 1044 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 1045 { 1046 int off, needaddr, neednl; 1047 1048 needaddr = 1; 1049 neednl = 0; 1050 for (off = first; off < pastlast; off += 4) { 1051 if ((off % 16) == 0 || needaddr) { 1052 printf(" 0x%02x:", off); 1053 needaddr = 0; 1054 } 1055 printf(" 0x%08x", regs[o2i(off)]); 1056 neednl = 1; 1057 if ((off % 16) == 12) { 1058 printf("\n"); 1059 neednl = 0; 1060 } 1061 } 1062 if (neednl) 1063 printf("\n"); 1064 } 1065 1066 static void 1067 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1068 { 1069 pcireg_t rval; 1070 1071 printf("\n AGP Capabilities Register\n"); 1072 1073 rval = regs[o2i(capoff)]; 1074 printf(" Revision: %d.%d\n", 1075 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1076 1077 /* XXX need more */ 1078 } 1079 1080 static const char * 1081 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1082 { 1083 1084 switch ((caps >> 6) & 7) { 1085 case 0: return "self-powered"; 1086 case 1: return "55 mA"; 1087 case 2: return "100 mA"; 1088 case 3: return "160 mA"; 1089 case 4: return "220 mA"; 1090 case 5: return "270 mA"; 1091 case 6: return "320 mA"; 1092 case 7: 1093 default: return "375 mA"; 1094 } 1095 } 1096 1097 static const char * 1098 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1099 { 1100 static const char unk[] = "unknown"; 1101 static const char *pmrev[8] = { 1102 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1103 }; 1104 if (val > 7) 1105 return unk; 1106 return pmrev[val]; 1107 } 1108 1109 static void 1110 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1111 { 1112 uint16_t caps, pmcsr; 1113 pcireg_t reg; 1114 1115 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1116 reg = regs[o2i(capoff + PCI_PMCSR)]; 1117 pmcsr = reg & 0xffff; 1118 1119 printf("\n PCI Power Management Capabilities Register\n"); 1120 1121 printf(" Capabilities register: 0x%04x\n", caps); 1122 printf(" Version: %s\n", 1123 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1124 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1125 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1126 printf(" 3.3V auxiliary current: %s\n", 1127 pci_conf_print_pcipm_cap_aux(caps)); 1128 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1129 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1130 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1131 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1132 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1133 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1134 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1135 1136 printf(" Control/status register: 0x%04x\n", pmcsr); 1137 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1138 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1139 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1140 printf(" PME# assertion: %sabled\n", 1141 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1142 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1143 printf(" Bridge Support Extensions register: 0x%02x\n", 1144 (reg >> 16) & 0xff); 1145 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1146 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1147 printf(" Data register: 0x%02x\n", (reg >> 24) & 0xff); 1148 1149 } 1150 1151 /* XXX pci_conf_print_vpd_cap */ 1152 /* XXX pci_conf_print_slotid_cap */ 1153 1154 static void 1155 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1156 { 1157 uint32_t ctl, mmc, mme; 1158 1159 regs += o2i(capoff); 1160 ctl = *regs++; 1161 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1162 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1163 1164 printf("\n PCI Message Signaled Interrupt\n"); 1165 1166 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1167 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1168 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1169 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1170 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1171 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1172 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1173 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1174 printf(" Message Address %sregister: 0x%08x\n", 1175 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1176 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1177 printf(" Message Address %sregister: 0x%08x\n", 1178 "(upper) ", *regs++); 1179 } 1180 printf(" Message Data register: 0x%08x\n", *regs++); 1181 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1182 printf(" Vector Mask register: 0x%08x\n", *regs++); 1183 printf(" Vector Pending register: 0x%08x\n", *regs++); 1184 } 1185 } 1186 1187 /* XXX pci_conf_print_cpci_hostwap_cap */ 1188 1189 /* 1190 * For both command register and status register. 1191 * The argument "idx" is index number (0 to 7). 1192 */ 1193 static int 1194 pcix_split_trans(unsigned int idx) 1195 { 1196 static int table[8] = { 1197 1, 2, 3, 4, 8, 12, 16, 32 1198 }; 1199 1200 if (idx >= __arraycount(table)) 1201 return -1; 1202 return table[idx]; 1203 } 1204 1205 static void 1206 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1207 { 1208 pcireg_t reg; 1209 int isbridge; 1210 int i; 1211 1212 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1213 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1214 printf("\n PCI-X %s Capabilities Register\n", 1215 isbridge ? "Bridge" : "Non-bridge"); 1216 1217 reg = regs[o2i(capoff)]; 1218 if (isbridge != 0) { 1219 printf(" Secondary status register: 0x%04x\n", 1220 (reg & 0xffff0000) >> 16); 1221 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1222 onoff("133MHz capable", reg, PCIX_STATUS_133); 1223 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1224 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1225 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1226 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1227 printf(" Secondary clock frequency: 0x%x\n", 1228 (reg & PCIX_BRIDGE_2NDST_CLKF) 1229 >> PCIX_BRIDGE_2NDST_CLKF_SHIFT); 1230 printf(" Version: 0x%x\n", 1231 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1232 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1233 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1234 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1235 } else { 1236 printf(" Command register: 0x%04x\n", 1237 (reg & 0xffff0000) >> 16); 1238 onoff("Data Parity Error Recovery", reg, 1239 PCIX_CMD_PERR_RECOVER); 1240 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1241 printf(" Maximum Burst Read Count: %u\n", 1242 PCIX_CMD_BYTECNT(reg)); 1243 printf(" Maximum Split Transactions: %d\n", 1244 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1245 >> PCIX_CMD_SPLTRANS_SHIFT)); 1246 } 1247 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1248 printf(" %sStatus register: 0x%08x\n", 1249 isbridge ? "Bridge " : "", reg); 1250 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1251 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1252 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1253 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1254 onoff("133MHz capable", reg, PCIX_STATUS_133); 1255 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1256 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1257 if (isbridge != 0) { 1258 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1259 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1260 } else { 1261 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1262 "bridge device", "simple device"); 1263 printf(" Designed max memory read byte count: %d\n", 1264 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1265 >> PCIX_STATUS_MAXB_SHIFT)); 1266 printf(" Designed max outstanding split transaction: %d\n", 1267 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1268 >> PCIX_STATUS_MAXST_SHIFT)); 1269 printf(" MAX cumulative Read Size: %u\n", 1270 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1271 onoff("Received split completion error", reg, 1272 PCIX_STATUS_SCERR); 1273 } 1274 onoff("266MHz capable", reg, PCIX_STATUS_266); 1275 onoff("533MHz capable", reg, PCIX_STATUS_533); 1276 1277 if (isbridge == 0) 1278 return; 1279 1280 /* Only for bridge */ 1281 for (i = 0; i < 2; i++) { 1282 reg = regs[o2i(capoff+PCIX_BRIDGE_UP_STCR + (4 * i))]; 1283 printf(" %s split transaction control register: 0x%08x\n", 1284 (i == 0) ? "Upstream" : "Downstream", reg); 1285 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1286 printf(" Commitment Limit: %d\n", 1287 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1288 } 1289 } 1290 1291 /* XXX pci_conf_print_ldt_cap */ 1292 1293 static void 1294 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1295 { 1296 uint16_t caps; 1297 1298 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1299 1300 printf("\n PCI Vendor Specific Capabilities Register\n"); 1301 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1302 } 1303 1304 static void 1305 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1306 { 1307 pcireg_t val; 1308 1309 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1310 1311 printf("\n Debugport Capability Register\n"); 1312 printf(" Debug base Register: 0x%04x\n", 1313 val >> PCI_DEBUG_BASER_SHIFT); 1314 printf(" port offset: 0x%04x\n", 1315 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1316 printf(" BAR number: %u\n", 1317 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1318 } 1319 1320 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1321 /* XXX pci_conf_print_hotplug_cap */ 1322 1323 static void 1324 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1325 { 1326 pcireg_t reg; 1327 1328 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1329 1330 printf("\n Subsystem ID Capability Register\n"); 1331 printf(" Subsystem ID : 0x%08x\n", reg); 1332 } 1333 1334 /* XXX pci_conf_print_agp8_cap */ 1335 /* XXX pci_conf_print_secure_cap */ 1336 1337 static void 1338 pci_print_pcie_L0s_latency(uint32_t val) 1339 { 1340 1341 switch (val) { 1342 case 0x0: 1343 printf("Less than 64ns\n"); 1344 break; 1345 case 0x1: 1346 case 0x2: 1347 case 0x3: 1348 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1349 break; 1350 case 0x4: 1351 printf("512ns to less than 1us\n"); 1352 break; 1353 case 0x5: 1354 printf("1us to less than 2us\n"); 1355 break; 1356 case 0x6: 1357 printf("2us - 4us\n"); 1358 break; 1359 case 0x7: 1360 printf("More than 4us\n"); 1361 break; 1362 } 1363 } 1364 1365 static void 1366 pci_print_pcie_L1_latency(uint32_t val) 1367 { 1368 1369 switch (val) { 1370 case 0x0: 1371 printf("Less than 1us\n"); 1372 break; 1373 case 0x6: 1374 printf("32us - 64us\n"); 1375 break; 1376 case 0x7: 1377 printf("More than 64us\n"); 1378 break; 1379 default: 1380 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1381 break; 1382 } 1383 } 1384 1385 static void 1386 pci_print_pcie_compl_timeout(uint32_t val) 1387 { 1388 1389 switch (val) { 1390 case 0x0: 1391 printf("50us to 50ms\n"); 1392 break; 1393 case 0x5: 1394 printf("16ms to 55ms\n"); 1395 break; 1396 case 0x6: 1397 printf("65ms to 210ms\n"); 1398 break; 1399 case 0x9: 1400 printf("260ms to 900ms\n"); 1401 break; 1402 case 0xa: 1403 printf("1s to 3.5s\n"); 1404 break; 1405 default: 1406 printf("unknown %u value\n", val); 1407 break; 1408 } 1409 } 1410 1411 static void 1412 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1413 { 1414 pcireg_t reg; /* for each register */ 1415 pcireg_t val; /* for each bitfield */ 1416 bool check_link = false; 1417 bool check_slot = false; 1418 bool check_rootport = false; 1419 unsigned int pciever; 1420 static const char * const linkspeeds[] = {"2.5", "5.0", "8.0"}; 1421 int i; 1422 1423 printf("\n PCI Express Capabilities Register\n"); 1424 /* Capability Register */ 1425 reg = regs[o2i(capoff)]; 1426 printf(" Capability register: %04x\n", reg >> 16); 1427 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1428 printf(" Capability version: %u\n", pciever); 1429 printf(" Device type: "); 1430 switch ((reg & 0x00f00000) >> 20) { 1431 case 0x0: 1432 printf("PCI Express Endpoint device\n"); 1433 check_link = true; 1434 break; 1435 case 0x1: 1436 printf("Legacy PCI Express Endpoint device\n"); 1437 check_link = true; 1438 break; 1439 case 0x4: 1440 printf("Root Port of PCI Express Root Complex\n"); 1441 check_link = true; 1442 check_slot = true; 1443 check_rootport = true; 1444 break; 1445 case 0x5: 1446 printf("Upstream Port of PCI Express Switch\n"); 1447 break; 1448 case 0x6: 1449 printf("Downstream Port of PCI Express Switch\n"); 1450 check_slot = true; 1451 check_rootport = true; 1452 break; 1453 case 0x7: 1454 printf("PCI Express to PCI/PCI-X Bridge\n"); 1455 break; 1456 case 0x8: 1457 printf("PCI/PCI-X to PCI Express Bridge\n"); 1458 break; 1459 case 0x9: 1460 printf("Root Complex Integrated Endpoint\n"); 1461 break; 1462 case 0xa: 1463 check_rootport = true; 1464 printf("Root Complex Event Collector\n"); 1465 break; 1466 default: 1467 printf("unknown\n"); 1468 break; 1469 } 1470 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1471 printf(" Interrupt Message Number: %x\n", 1472 (unsigned int)((reg & PCIE_XCAP_IRQ) >> 27)); 1473 1474 /* Device Capability Register */ 1475 reg = regs[o2i(capoff + PCIE_DCAP)]; 1476 printf(" Device Capabilities Register: 0x%08x\n", reg); 1477 printf(" Max Payload Size Supported: %u bytes max\n", 1478 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1479 printf(" Phantom Functions Supported: "); 1480 switch ((reg & PCIE_DCAP_PHANTOM_FUNCS) >> 3) { 1481 case 0x0: 1482 printf("not available\n"); 1483 break; 1484 case 0x1: 1485 printf("MSB\n"); 1486 break; 1487 case 0x2: 1488 printf("two MSB\n"); 1489 break; 1490 case 0x3: 1491 printf("All three bits\n"); 1492 break; 1493 } 1494 printf(" Extended Tag Field Supported: %dbit\n", 1495 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1496 printf(" Endpoint L0 Acceptable Latency: "); 1497 pci_print_pcie_L0s_latency((reg & PCIE_DCAP_L0S_LATENCY) >> 6); 1498 printf(" Endpoint L1 Acceptable Latency: "); 1499 pci_print_pcie_L1_latency((reg & PCIE_DCAP_L1_LATENCY) >> 9); 1500 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1501 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1502 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1503 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1504 printf(" Captured Slot Power Limit Value: %d\n", 1505 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18); 1506 printf(" Captured Slot Power Limit Scale: %d\n", 1507 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26); 1508 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1509 1510 /* Device Control Register */ 1511 reg = regs[o2i(capoff + PCIE_DCSR)]; 1512 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1513 onoff("Correctable Error Reporting Enable", reg, 1514 PCIE_DCSR_ENA_COR_ERR); 1515 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1516 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1517 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1518 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1519 printf(" Max Payload Size: %d byte\n", 1520 128 << (((unsigned int)(reg & PCIE_DCSR_MAX_PAYLOAD) >> 5))); 1521 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1522 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1523 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1524 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1525 printf(" Max Read Request Size: %d byte\n", 1526 128 << ((unsigned int)(reg & PCIE_DCSR_MAX_READ_REQ) >> 12)); 1527 1528 /* Device Status Register */ 1529 reg = regs[o2i(capoff + PCIE_DCSR)]; 1530 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1531 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1532 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1533 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1534 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1535 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1536 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1537 1538 if (check_link) { 1539 /* Link Capability Register */ 1540 reg = regs[o2i(capoff + PCIE_LCAP)]; 1541 printf(" Link Capabilities Register: 0x%08x\n", reg); 1542 printf(" Maximum Link Speed: "); 1543 val = reg & PCIE_LCAP_MAX_SPEED; 1544 if (val < 1 || val > 3) { 1545 printf("unknown %u value\n", val); 1546 } else { 1547 printf("%sGT/s\n", linkspeeds[val - 1]); 1548 } 1549 printf(" Maximum Link Width: x%u lanes\n", 1550 (unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4); 1551 printf(" Active State PM Support: "); 1552 val = (reg & PCIE_LCAP_ASPM) >> 10; 1553 switch (val) { 1554 case 0x1: 1555 printf("L0s Entry supported\n"); 1556 break; 1557 case 0x3: 1558 printf("L0s and L1 supported\n"); 1559 break; 1560 default: 1561 printf("Reserved value\n"); 1562 break; 1563 } 1564 printf(" L0 Exit Latency: "); 1565 pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12); 1566 printf(" L1 Exit Latency: "); 1567 pci_print_pcie_L1_latency((reg & PCIE_LCAP_L1_EXIT) >> 15); 1568 printf(" Port Number: %u\n", reg >> 24); 1569 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1570 onoff("Surprise Down Error Report", reg, 1571 PCIE_LCAP_SURPRISE_DOWN); 1572 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1573 onoff("Link BW Notification Capable", reg, 1574 PCIE_LCAP_LINK_BW_NOTIFY); 1575 onoff("ASPM Optionally Compliance", reg, 1576 PCIE_LCAP_ASPM_COMPLIANCE); 1577 1578 /* Link Control Register */ 1579 reg = regs[o2i(capoff + PCIE_LCSR)]; 1580 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1581 printf(" Active State PM Control: "); 1582 val = reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S); 1583 switch (val) { 1584 case 0: 1585 printf("disabled\n"); 1586 break; 1587 case 1: 1588 printf("L0s Entry Enabled\n"); 1589 break; 1590 case 2: 1591 printf("L1 Entry Enabled\n"); 1592 break; 1593 case 3: 1594 printf("L0s and L1 Entry Enabled\n"); 1595 break; 1596 } 1597 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1598 "128bytes", "64bytes"); 1599 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1600 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1601 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1602 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1603 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1604 onoff("Hardware Autonomous Width Disable", reg, 1605 PCIE_LCSR_HAWD); 1606 onoff("Link Bandwidth Management Interrupt Enable", reg, 1607 PCIE_LCSR_LBMIE); 1608 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1609 PCIE_LCSR_LABIE); 1610 1611 /* Link Status Register */ 1612 reg = regs[o2i(capoff + PCIE_LCSR)]; 1613 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1614 printf(" Negotiated Link Speed: "); 1615 if (((reg >> 16) & 0x000f) < 1 || 1616 ((reg >> 16) & 0x000f) > 3) { 1617 printf("unknown %u value\n", 1618 (unsigned int)(reg & PCIE_LCSR_LINKSPEED) >> 16); 1619 } else { 1620 printf("%sGT/s\n", 1621 linkspeeds[((reg & PCIE_LCSR_LINKSPEED) >> 16)-1]); 1622 } 1623 printf(" Negotiated Link Width: x%u lanes\n", 1624 (reg >> 20) & 0x003f); 1625 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1626 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1627 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1628 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1629 onoff("Link Bandwidth Management Status", reg, 1630 PCIE_LCSR_LINK_BW_MGMT); 1631 onoff("Link Autonomous Bandwidth Status", reg, 1632 PCIE_LCSR_LINK_AUTO_BW); 1633 } 1634 1635 if (check_slot == true) { 1636 /* Slot Capability Register */ 1637 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1638 printf(" Slot Capability Register: %08x\n", reg); 1639 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1640 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1641 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1642 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1643 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1644 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1645 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1646 printf(" Slot Power Limit Value: %d\n", 1647 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1648 printf(" Slot Power Limit Scale: %d\n", 1649 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1650 onoff("Electromechanical Interlock Present", reg, 1651 PCIE_SLCAP_EIP); 1652 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1653 printf(" Physical Slot Number: %d\n", 1654 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1655 1656 /* Slot Control Register */ 1657 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1658 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1659 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1660 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1661 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1662 onoff("Presense Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1663 onoff("Command Completed Interrupt Enabled", reg, 1664 PCIE_SLCSR_CCE); 1665 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1666 printf(" Attention Indicator Control: "); 1667 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1668 case 0x0: 1669 printf("reserved\n"); 1670 break; 1671 case 0x1: 1672 printf("on\n"); 1673 break; 1674 case 0x2: 1675 printf("blink\n"); 1676 break; 1677 case 0x3: 1678 printf("off\n"); 1679 break; 1680 } 1681 printf(" Power Indicator Control: "); 1682 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1683 case 0x0: 1684 printf("reserved\n"); 1685 break; 1686 case 0x1: 1687 printf("on\n"); 1688 break; 1689 case 0x2: 1690 printf("blink\n"); 1691 break; 1692 case 0x3: 1693 printf("off\n"); 1694 break; 1695 } 1696 onoff("Power Controller Control", reg, PCIE_SLCSR_PCC); 1697 onoff("Electromechanical Interlock Control", 1698 reg, PCIE_SLCSR_EIC); 1699 onoff("Data Link Layer State Changed Enable", reg, 1700 PCIE_SLCSR_DLLSCE); 1701 1702 /* Slot Status Register */ 1703 printf(" Slot Status Register: %04x\n", reg >> 16); 1704 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1705 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1706 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1707 onoff("Presense Detect Changed", reg, PCIE_SLCSR_PDC); 1708 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1709 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1710 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1711 onoff("Electromechanical Interlock engaged", reg, 1712 PCIE_SLCSR_EIS); 1713 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 1714 } 1715 1716 if (check_rootport == true) { 1717 /* Root Control Register */ 1718 reg = regs[o2i(capoff + PCIE_RCR)]; 1719 printf(" Root Control Register: %04x\n", reg & 0xffff); 1720 onoff("SERR on Correctable Error Enable", reg, 1721 PCIE_RCR_SERR_CER); 1722 onoff("SERR on Non-Fatal Error Enable", reg, 1723 PCIE_RCR_SERR_NFER); 1724 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 1725 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 1726 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 1727 1728 /* Root Capability Register */ 1729 printf(" Root Capability Register: %04x\n", 1730 reg >> 16); 1731 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 1732 1733 /* Root Status Register */ 1734 reg = regs[o2i(capoff + PCIE_RSR)]; 1735 printf(" Root Status Register: %08x\n", reg); 1736 printf(" PME Requester ID: %04x\n", 1737 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1738 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 1739 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 1740 } 1741 1742 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1743 if (pciever < 2) 1744 return; 1745 1746 /* Device Capabilities 2 */ 1747 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1748 printf(" Device Capabilities 2: 0x%08x\n", reg); 1749 printf(" Completion Timeout Ranges Supported: %u \n", 1750 (unsigned int)(reg & PCIE_DCAP2_COMPT_RANGE)); 1751 onoff("Completion Timeout Disable Supported", reg, 1752 PCIE_DCAP2_COMPT_DIS); 1753 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 1754 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 1755 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 1756 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 1757 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 1758 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 1759 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 1760 printf(" TPH Completer Supported: %u\n", 1761 (unsigned int)(reg & PCIE_DCAP2_TPH_COMP) >> 12); 1762 printf(" OBFF Supported: "); 1763 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 1764 case 0x0: 1765 printf("Not supported\n"); 1766 break; 1767 case 0x1: 1768 printf("Message only\n"); 1769 break; 1770 case 0x2: 1771 printf("WAKE# only\n"); 1772 break; 1773 case 0x3: 1774 printf("Both\n"); 1775 break; 1776 } 1777 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 1778 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 1779 printf(" Max End-End TLP Prefixes: %u\n", 1780 (unsigned int)(reg & PCIE_DCAP2_MAX_EETLP) >> 22); 1781 1782 /* Device Control 2 */ 1783 reg = regs[o2i(capoff + PCIE_DCSR2)]; 1784 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 1785 printf(" Completion Timeout Value: "); 1786 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 1787 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 1788 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 1789 onoff("AtomicOp Rquester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 1790 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 1791 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 1792 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 1793 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 1794 printf(" OBFF: "); 1795 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 1796 case 0x0: 1797 printf("Disabled\n"); 1798 break; 1799 case 0x1: 1800 printf("Enabled with Message Signaling Variation A\n"); 1801 break; 1802 case 0x2: 1803 printf("Enabled with Message Signaling Variation B\n"); 1804 break; 1805 case 0x3: 1806 printf("Enabled using WAKE# signaling\n"); 1807 break; 1808 } 1809 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 1810 1811 if (check_link) { 1812 /* Link Capability 2 */ 1813 reg = regs[o2i(capoff + PCIE_LCAP2)]; 1814 printf(" Link Capabilities 2: 0x%08x\n", reg); 1815 val = (reg & PCIE_LCAP2_SUP_LNKSV) >> 1; 1816 printf(" Supported Link Speed Vector:"); 1817 for (i = 0; i <= 2; i++) { 1818 if (((val >> i) & 0x01) != 0) 1819 printf(" %sGT/s", linkspeeds[i]); 1820 } 1821 printf("\n"); 1822 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 1823 1824 /* Link Control 2 */ 1825 reg = regs[o2i(capoff + PCIE_LCSR2)]; 1826 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 1827 printf(" Target Link Speed: "); 1828 val = reg & PCIE_LCSR2_TGT_LSPEED; 1829 if (val < 1 || val > 3) 1830 printf("unknown %u value\n", val); 1831 else 1832 printf("%sGT/s\n", linkspeeds[val - 1]); 1833 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 1834 onoff("HW Autonomous Speed Disabled", reg, 1835 PCIE_LCSR2_HW_AS_DIS); 1836 onoff("Selectable De-emphasis", reg, PCIE_LCSR2_SEL_DEEMP); 1837 printf(" Transmit Margin: %u\n", 1838 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 1839 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 1840 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 1841 printf(" Compliance Present/De-emphasis: %u\n", 1842 (unsigned int)(reg & PCIE_LCSR2_COMP_DEEMP) >> 12); 1843 1844 /* Link Status 2 */ 1845 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 1846 onoff("Current De-emphasis Level", reg, PCIE_LCSR2_DEEMP_LVL); 1847 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 1848 onoff("Equalization Phase 1 Successful", reg, 1849 PCIE_LCSR2_EQP1_SUC); 1850 onoff("Equalization Phase 2 Successful", reg, 1851 PCIE_LCSR2_EQP2_SUC); 1852 onoff("Equalization Phase 3 Successful", reg, 1853 PCIE_LCSR2_EQP3_SUC); 1854 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 1855 } 1856 1857 /* Slot Capability 2 */ 1858 /* Slot Control 2 */ 1859 /* Slot Status 2 */ 1860 } 1861 1862 static void 1863 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 1864 { 1865 pcireg_t reg; 1866 1867 printf("\n MSI-X Capability Register\n"); 1868 1869 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 1870 printf(" Message Control register: 0x%04x\n", 1871 (reg >> 16) & 0xff); 1872 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 1873 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 1874 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 1875 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 1876 printf(" Table offset register: 0x%08x\n", reg); 1877 printf(" Table offset: %08x\n", reg & PCI_MSIX_TBLOFFSET_MASK); 1878 printf(" BIR: 0x%x\n", reg & PCI_MSIX_TBLBIR_MASK); 1879 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 1880 printf(" Pending bit array register: 0x%08x\n", reg); 1881 printf(" Pending bit array offset: %08x\n", 1882 reg & PCI_MSIX_PBAOFFSET_MASK); 1883 printf(" BIR: 0x%x\n", reg & PCI_MSIX_PBABIR_MASK); 1884 } 1885 1886 /* XXX pci_conf_print_sata_cap */ 1887 static void 1888 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 1889 { 1890 pcireg_t reg; 1891 1892 printf("\n Advanced Features Capability Register\n"); 1893 1894 reg = regs[o2i(capoff + PCI_AFCAPR)]; 1895 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 1896 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 1897 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 1898 reg = regs[o2i(capoff + PCI_AFCSR)]; 1899 printf(" AF Control register: 0x%02x\n", reg & 0xff); 1900 /* 1901 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 1902 * and it's always 0 on read 1903 */ 1904 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 1905 onoff("Transaction Pending", reg, PCI_AFSR_TP); 1906 } 1907 1908 static struct { 1909 pcireg_t cap; 1910 const char *name; 1911 void (*printfunc)(const pcireg_t *, int); 1912 } pci_captab[] = { 1913 { PCI_CAP_RESERVED0, "reserved", NULL }, 1914 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 1915 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 1916 { PCI_CAP_VPD, "VPD", NULL }, 1917 { PCI_CAP_SLOTID, "SlotID", NULL }, 1918 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 1919 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 1920 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 1921 { PCI_CAP_LDT, "HyperTransport", NULL }, 1922 { PCI_CAP_VENDSPEC, "Vendor-specific", 1923 pci_conf_print_vendspec_cap }, 1924 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 1925 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 1926 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 1927 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 1928 pci_conf_print_subsystem_cap }, 1929 { PCI_CAP_AGP8, "AGP 8x", NULL }, 1930 { PCI_CAP_SECURE, "Secure Device", NULL }, 1931 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 1932 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 1933 { PCI_CAP_SATA, "SATA", NULL }, 1934 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap } 1935 }; 1936 1937 static void 1938 pci_conf_print_caplist( 1939 #ifdef _KERNEL 1940 pci_chipset_tag_t pc, pcitag_t tag, 1941 #endif 1942 const pcireg_t *regs, int capoff) 1943 { 1944 int off; 1945 pcireg_t foundcap; 1946 pcireg_t rval; 1947 bool foundtable[__arraycount(pci_captab)]; 1948 unsigned int i; 1949 1950 /* Clear table */ 1951 for (i = 0; i < __arraycount(pci_captab); i++) 1952 foundtable[i] = false; 1953 1954 /* Print capability register's offset and the type first */ 1955 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1956 off != 0; 1957 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 1958 rval = regs[o2i(off)]; 1959 printf(" Capability register at 0x%02x\n", off); 1960 1961 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 1962 foundcap = PCI_CAPLIST_CAP(rval); 1963 if (foundcap < __arraycount(pci_captab)) { 1964 printf("%s)\n", pci_captab[foundcap].name); 1965 /* Mark as found */ 1966 foundtable[foundcap] = true; 1967 } else 1968 printf("unknown)\n"); 1969 } 1970 1971 /* 1972 * And then, print the detail of each capability registers 1973 * in capability value's order. 1974 */ 1975 for (i = 0; i < __arraycount(pci_captab); i++) { 1976 if (foundtable[i] == false) 1977 continue; 1978 1979 /* 1980 * The type was found. Search capability list again and 1981 * print all capabilities that the capabiliy type is 1982 * the same. This is required because some capabilities 1983 * appear multiple times (e.g. HyperTransport capability). 1984 */ 1985 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1986 off != 0; 1987 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 1988 rval = regs[o2i(off)]; 1989 foundcap = PCI_CAPLIST_CAP(rval); 1990 if ((i == foundcap) 1991 && (pci_captab[foundcap].printfunc != NULL)) 1992 pci_captab[foundcap].printfunc(regs, off); 1993 } 1994 } 1995 } 1996 1997 /* Print the Secondary Status Register. */ 1998 static void 1999 pci_conf_print_ssr(pcireg_t rval) 2000 { 2001 pcireg_t devsel; 2002 2003 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 2004 onoff("66 MHz capable", rval, __BIT(5)); 2005 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 2006 onoff("Fast back-to-back capable", rval, __BIT(7)); 2007 onoff("Data parity error detected", rval, __BIT(8)); 2008 2009 printf(" DEVSEL timing: "); 2010 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 2011 switch (devsel) { 2012 case 0: 2013 printf("fast"); 2014 break; 2015 case 1: 2016 printf("medium"); 2017 break; 2018 case 2: 2019 printf("slow"); 2020 break; 2021 default: 2022 printf("unknown/reserved"); /* XXX */ 2023 break; 2024 } 2025 printf(" (0x%x)\n", devsel); 2026 2027 onoff("Signalled target abort", rval, __BIT(11)); 2028 onoff("Received target abort", rval, __BIT(12)); 2029 onoff("Received master abort", rval, __BIT(13)); 2030 onoff("Received system error", rval, __BIT(14)); 2031 onoff("Detected parity error", rval, __BIT(15)); 2032 } 2033 2034 static void 2035 pci_conf_print_type0( 2036 #ifdef _KERNEL 2037 pci_chipset_tag_t pc, pcitag_t tag, 2038 #endif 2039 const pcireg_t *regs 2040 #ifdef _KERNEL 2041 , int sizebars 2042 #endif 2043 ) 2044 { 2045 int off, width; 2046 pcireg_t rval; 2047 2048 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 2049 #ifdef _KERNEL 2050 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 2051 #else 2052 width = pci_conf_print_bar(regs, off, NULL); 2053 #endif 2054 } 2055 2056 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 2057 2058 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 2059 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 2060 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 2061 2062 /* XXX */ 2063 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 2064 2065 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2066 printf(" Capability list pointer: 0x%02x\n", 2067 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 2068 else 2069 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 2070 2071 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 2072 2073 rval = regs[o2i(PCI_INTERRUPT_REG)]; 2074 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 2075 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 2076 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 2077 switch (PCI_INTERRUPT_PIN(rval)) { 2078 case PCI_INTERRUPT_PIN_NONE: 2079 printf("(none)"); 2080 break; 2081 case PCI_INTERRUPT_PIN_A: 2082 printf("(pin A)"); 2083 break; 2084 case PCI_INTERRUPT_PIN_B: 2085 printf("(pin B)"); 2086 break; 2087 case PCI_INTERRUPT_PIN_C: 2088 printf("(pin C)"); 2089 break; 2090 case PCI_INTERRUPT_PIN_D: 2091 printf("(pin D)"); 2092 break; 2093 default: 2094 printf("(? ? ?)"); 2095 break; 2096 } 2097 printf("\n"); 2098 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 2099 } 2100 2101 static void 2102 pci_conf_print_type1( 2103 #ifdef _KERNEL 2104 pci_chipset_tag_t pc, pcitag_t tag, 2105 #endif 2106 const pcireg_t *regs 2107 #ifdef _KERNEL 2108 , int sizebars 2109 #endif 2110 ) 2111 { 2112 int off, width; 2113 pcireg_t rval; 2114 uint32_t base, limit; 2115 uint32_t base_h, limit_h; 2116 uint64_t pbase, plimit; 2117 int use_upper; 2118 2119 /* 2120 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 2121 * Bridge chip documentation, and may not be correct with 2122 * respect to various standards. (XXX) 2123 */ 2124 2125 for (off = 0x10; off < 0x18; off += width) { 2126 #ifdef _KERNEL 2127 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 2128 #else 2129 width = pci_conf_print_bar(regs, off, NULL); 2130 #endif 2131 } 2132 2133 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 2134 printf(" Primary bus number: 0x%02x\n", 2135 PCI_BRIDGE_BUS_PRIMARY(rval)); 2136 printf(" Secondary bus number: 0x%02x\n", 2137 PCI_BRIDGE_BUS_SECONDARY(rval)); 2138 printf(" Subordinate bus number: 0x%02x\n", 2139 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 2140 printf(" Secondary bus latency timer: 0x%02x\n", 2141 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 2142 2143 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 2144 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 2145 2146 /* I/O region */ 2147 printf(" I/O region:\n"); 2148 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 2149 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 2150 if (PCI_BRIDGE_IO_32BITS(rval)) 2151 use_upper = 1; 2152 else 2153 use_upper = 0; 2154 onoff("32bit I/O", rval, use_upper); 2155 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 2156 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 2157 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 2158 limit |= 0x00000fff; 2159 2160 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 2161 base_h = (rval >> 0) & 0xffff; 2162 limit_h = (rval >> 16) & 0xffff; 2163 printf(" base upper 16 bits register: 0x%04x\n", base_h); 2164 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 2165 2166 if (use_upper == 1) { 2167 base |= base_h << 16; 2168 limit |= limit_h << 16; 2169 } 2170 if (base < limit) { 2171 if (use_upper == 1) 2172 printf(" range: 0x%08x-0x%08x\n", base, limit); 2173 else 2174 printf(" range: 0x%04x-0x%04x\n", base, limit); 2175 } else 2176 printf(" range: not set\n"); 2177 2178 /* Non-prefetchable memory region */ 2179 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 2180 printf(" Memory region:\n"); 2181 printf(" base register: 0x%04x\n", 2182 (rval >> 0) & 0xffff); 2183 printf(" limit register: 0x%04x\n", 2184 (rval >> 16) & 0xffff); 2185 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 2186 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 2187 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 2188 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 2189 if (base < limit) 2190 printf(" range: 0x%08x-0x%08x\n", base, limit); 2191 else 2192 printf(" range: not set\n"); 2193 2194 /* Prefetchable memory region */ 2195 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 2196 printf(" Prefetchable memory region:\n"); 2197 printf(" base register: 0x%04x\n", 2198 (rval >> 0) & 0xffff); 2199 printf(" limit register: 0x%04x\n", 2200 (rval >> 16) & 0xffff); 2201 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 2202 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 2203 printf(" base upper 32 bits register: 0x%08x\n", 2204 base_h); 2205 printf(" limit upper 32 bits register: 0x%08x\n", 2206 limit_h); 2207 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 2208 use_upper = 1; 2209 else 2210 use_upper = 0; 2211 onoff("64bit memory address", rval, use_upper); 2212 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 2213 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 2214 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 2215 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 2216 if (use_upper == 1) { 2217 pbase |= (uint64_t)base_h << 32; 2218 plimit |= (uint64_t)limit_h << 32; 2219 } 2220 if (pbase < plimit) { 2221 if (use_upper == 1) 2222 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 2223 "\n", pbase, plimit); 2224 else 2225 printf(" range: 0x%08x-0x%08x\n", 2226 (uint32_t)pbase, (uint32_t)plimit); 2227 } else 2228 printf(" range: not set\n"); 2229 2230 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2231 printf(" Capability list pointer: 0x%02x\n", 2232 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 2233 else 2234 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 2235 2236 /* XXX */ 2237 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 2238 2239 rval = regs[o2i(PCI_INTERRUPT_REG)]; 2240 printf(" Interrupt line: 0x%02x\n", 2241 (rval >> 0) & 0xff); 2242 printf(" Interrupt pin: 0x%02x ", 2243 (rval >> 8) & 0xff); 2244 switch ((rval >> 8) & 0xff) { 2245 case PCI_INTERRUPT_PIN_NONE: 2246 printf("(none)"); 2247 break; 2248 case PCI_INTERRUPT_PIN_A: 2249 printf("(pin A)"); 2250 break; 2251 case PCI_INTERRUPT_PIN_B: 2252 printf("(pin B)"); 2253 break; 2254 case PCI_INTERRUPT_PIN_C: 2255 printf("(pin C)"); 2256 break; 2257 case PCI_INTERRUPT_PIN_D: 2258 printf("(pin D)"); 2259 break; 2260 default: 2261 printf("(? ? ?)"); 2262 break; 2263 } 2264 printf("\n"); 2265 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 2266 & PCI_BRIDGE_CONTROL_MASK; 2267 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 2268 onoff("Parity error response", rval, 0x0001); 2269 onoff("Secondary SERR forwarding", rval, 0x0002); 2270 onoff("ISA enable", rval, 0x0004); 2271 onoff("VGA enable", rval, 0x0008); 2272 onoff("Master abort reporting", rval, 0x0020); 2273 onoff("Secondary bus reset", rval, 0x0040); 2274 onoff("Fast back-to-back capable", rval, 0x0080); 2275 } 2276 2277 static void 2278 pci_conf_print_type2( 2279 #ifdef _KERNEL 2280 pci_chipset_tag_t pc, pcitag_t tag, 2281 #endif 2282 const pcireg_t *regs 2283 #ifdef _KERNEL 2284 , int sizebars 2285 #endif 2286 ) 2287 { 2288 pcireg_t rval; 2289 2290 /* 2291 * XXX these need to be printed in more detail, need to be 2292 * XXX checked against specs/docs, etc. 2293 * 2294 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 2295 * controller chip documentation, and may not be correct with 2296 * respect to various standards. (XXX) 2297 */ 2298 2299 #ifdef _KERNEL 2300 pci_conf_print_bar(pc, tag, regs, 0x10, 2301 "CardBus socket/ExCA registers", sizebars); 2302 #else 2303 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 2304 #endif 2305 2306 /* Capability list pointer and secondary status register */ 2307 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 2308 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2309 printf(" Capability list pointer: 0x%02x\n", 2310 PCI_CAPLIST_PTR(rval)); 2311 else 2312 printf(" Reserved @ 0x14: 0x%04" PRIxMAX "\n", 2313 __SHIFTOUT(rval, __BITS(15, 0))); 2314 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 2315 2316 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 2317 printf(" PCI bus number: 0x%02x\n", 2318 (rval >> 0) & 0xff); 2319 printf(" CardBus bus number: 0x%02x\n", 2320 (rval >> 8) & 0xff); 2321 printf(" Subordinate bus number: 0x%02x\n", 2322 (rval >> 16) & 0xff); 2323 printf(" CardBus latency timer: 0x%02x\n", 2324 (rval >> 24) & 0xff); 2325 2326 /* XXX Print more prettily */ 2327 printf(" CardBus memory region 0:\n"); 2328 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 2329 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 2330 printf(" CardBus memory region 1:\n"); 2331 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 2332 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 2333 printf(" CardBus I/O region 0:\n"); 2334 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 2335 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 2336 printf(" CardBus I/O region 1:\n"); 2337 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 2338 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 2339 2340 rval = regs[o2i(PCI_INTERRUPT_REG)]; 2341 printf(" Interrupt line: 0x%02x\n", 2342 (rval >> 0) & 0xff); 2343 printf(" Interrupt pin: 0x%02x ", 2344 (rval >> 8) & 0xff); 2345 switch ((rval >> 8) & 0xff) { 2346 case PCI_INTERRUPT_PIN_NONE: 2347 printf("(none)"); 2348 break; 2349 case PCI_INTERRUPT_PIN_A: 2350 printf("(pin A)"); 2351 break; 2352 case PCI_INTERRUPT_PIN_B: 2353 printf("(pin B)"); 2354 break; 2355 case PCI_INTERRUPT_PIN_C: 2356 printf("(pin C)"); 2357 break; 2358 case PCI_INTERRUPT_PIN_D: 2359 printf("(pin D)"); 2360 break; 2361 default: 2362 printf("(? ? ?)"); 2363 break; 2364 } 2365 printf("\n"); 2366 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 2367 printf(" Bridge control register: 0x%04x\n", rval); 2368 onoff("Parity error response", rval, __BIT(0)); 2369 onoff("SERR# enable", rval, __BIT(1)); 2370 onoff("ISA enable", rval, __BIT(2)); 2371 onoff("VGA enable", rval, __BIT(3)); 2372 onoff("Master abort mode", rval, __BIT(5)); 2373 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 2374 onoff("Functional interrupts routed by ExCA registers", rval, 2375 __BIT(7)); 2376 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 2377 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 2378 onoff("Write posting enable", rval, __BIT(10)); 2379 2380 rval = regs[o2i(0x40)]; 2381 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 2382 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 2383 2384 #ifdef _KERNEL 2385 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 2386 sizebars); 2387 #else 2388 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 2389 #endif 2390 } 2391 2392 void 2393 pci_conf_print( 2394 #ifdef _KERNEL 2395 pci_chipset_tag_t pc, pcitag_t tag, 2396 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 2397 #else 2398 int pcifd, u_int bus, u_int dev, u_int func 2399 #endif 2400 ) 2401 { 2402 pcireg_t regs[o2i(256)]; 2403 int off, capoff, endoff, hdrtype; 2404 const char *typename; 2405 #ifdef _KERNEL 2406 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, 2407 int); 2408 int sizebars; 2409 #else 2410 void (*typeprintfn)(const pcireg_t *); 2411 #endif 2412 2413 printf("PCI configuration registers:\n"); 2414 2415 for (off = 0; off < 256; off += 4) { 2416 #ifdef _KERNEL 2417 regs[o2i(off)] = pci_conf_read(pc, tag, off); 2418 #else 2419 if (pcibus_conf_read(pcifd, bus, dev, func, off, 2420 ®s[o2i(off)]) == -1) 2421 regs[o2i(off)] = 0; 2422 #endif 2423 } 2424 2425 #ifdef _KERNEL 2426 sizebars = 1; 2427 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 2428 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 2429 sizebars = 0; 2430 #endif 2431 2432 /* common header */ 2433 printf(" Common header:\n"); 2434 pci_conf_print_regs(regs, 0, 16); 2435 2436 printf("\n"); 2437 #ifdef _KERNEL 2438 pci_conf_print_common(pc, tag, regs); 2439 #else 2440 pci_conf_print_common(regs); 2441 #endif 2442 printf("\n"); 2443 2444 /* type-dependent header */ 2445 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 2446 switch (hdrtype) { /* XXX make a table, eventually */ 2447 case 0: 2448 /* Standard device header */ 2449 typename = "\"normal\" device"; 2450 typeprintfn = &pci_conf_print_type0; 2451 capoff = PCI_CAPLISTPTR_REG; 2452 endoff = 64; 2453 break; 2454 case 1: 2455 /* PCI-PCI bridge header */ 2456 typename = "PCI-PCI bridge"; 2457 typeprintfn = &pci_conf_print_type1; 2458 capoff = PCI_CAPLISTPTR_REG; 2459 endoff = 64; 2460 break; 2461 case 2: 2462 /* PCI-CardBus bridge header */ 2463 typename = "PCI-CardBus bridge"; 2464 typeprintfn = &pci_conf_print_type2; 2465 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 2466 endoff = 72; 2467 break; 2468 default: 2469 typename = NULL; 2470 typeprintfn = 0; 2471 capoff = -1; 2472 endoff = 64; 2473 break; 2474 } 2475 printf(" Type %d ", hdrtype); 2476 if (typename != NULL) 2477 printf("(%s) ", typename); 2478 printf("header:\n"); 2479 pci_conf_print_regs(regs, 16, endoff); 2480 printf("\n"); 2481 if (typeprintfn) { 2482 #ifdef _KERNEL 2483 (*typeprintfn)(pc, tag, regs, sizebars); 2484 #else 2485 (*typeprintfn)(regs); 2486 #endif 2487 } else 2488 printf(" Don't know how to pretty-print type %d header.\n", 2489 hdrtype); 2490 printf("\n"); 2491 2492 /* capability list, if present */ 2493 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2494 && (capoff > 0)) { 2495 #ifdef _KERNEL 2496 pci_conf_print_caplist(pc, tag, regs, capoff); 2497 #else 2498 pci_conf_print_caplist(regs, capoff); 2499 #endif 2500 printf("\n"); 2501 } 2502 2503 /* device-dependent header */ 2504 printf(" Device-dependent header:\n"); 2505 pci_conf_print_regs(regs, endoff, 256); 2506 printf("\n"); 2507 #ifdef _KERNEL 2508 if (printfn) 2509 (*printfn)(pc, tag, regs); 2510 else 2511 printf(" Don't know how to pretty-print device-dependent header.\n"); 2512 printf("\n"); 2513 #endif /* _KERNEL */ 2514 } 2515
Indexes created Tue Sep 30 11:09:46 GMT 2025