pci_subr.c revision 1.126
1 /* $NetBSD: pci_subr.c,v 1.126 2014/09/21 14:30:22 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.126 2014/09/21 14:30:22 christos Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdbool.h> 58 #include <stdio.h> 59 #include <string.h> 60 #endif 61 62 #include <dev/pci/pcireg.h> 63 #ifdef _KERNEL 64 #include <dev/pci/pcivar.h> 65 #else 66 #include <dev/pci/pci_verbose.h> 67 #include <dev/pci/pcidevs.h> 68 #include <dev/pci/pcidevs_data.h> 69 #endif 70 71 /* 72 * Descriptions of known PCI classes and subclasses. 73 * 74 * Subclasses are described in the same way as classes, but have a 75 * NULL subclass pointer. 76 */ 77 struct pci_class { 78 const char *name; 79 u_int val; /* as wide as pci_{,sub}class_t */ 80 const struct pci_class *subclasses; 81 }; 82 83 /* 84 * Class 0x00. 85 * Before rev. 2.0. 86 */ 87 static const struct pci_class pci_subclass_prehistoric[] = { 88 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 89 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 90 { NULL, 0, NULL, }, 91 }; 92 93 /* 94 * Class 0x01. 95 * Mass strage controller 96 */ 97 98 /* ATA programming interface */ 99 static const struct pci_class pci_interface_ata[] = { 100 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 101 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 102 { NULL, 0, NULL, }, 103 }; 104 105 /* SATA programming interface */ 106 static const struct pci_class pci_interface_sata[] = { 107 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 108 { NULL, 0, NULL, }, 109 }; 110 111 /* Subclasses */ 112 static const struct pci_class pci_subclass_mass_storage[] = { 113 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 114 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 115 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 116 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 117 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 118 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 119 pci_interface_ata, }, 120 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 121 pci_interface_sata, }, 122 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 123 { "NVM", PCI_SUBCLASS_MASS_STORAGE_NVM, NULL, }, 124 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 125 { NULL, 0, NULL, }, 126 }; 127 128 /* 129 * Class 0x02. 130 * Network controller. 131 */ 132 static const struct pci_class pci_subclass_network[] = { 133 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 134 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 135 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 136 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 137 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 138 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 139 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 140 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 141 { NULL, 0, NULL, }, 142 }; 143 144 /* 145 * Class 0x03. 146 * Display controller. 147 */ 148 149 /* VGA programming interface */ 150 static const struct pci_class pci_interface_vga[] = { 151 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 152 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 153 { NULL, 0, NULL, }, 154 }; 155 /* Subclasses */ 156 static const struct pci_class pci_subclass_display[] = { 157 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 158 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 159 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 160 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 161 { NULL, 0, NULL, }, 162 }; 163 164 /* 165 * Class 0x04. 166 * Multimedia device. 167 */ 168 static const struct pci_class pci_subclass_multimedia[] = { 169 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 170 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 171 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 172 { "HD audio", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 173 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 174 { NULL, 0, NULL, }, 175 }; 176 177 /* 178 * Class 0x05. 179 * Memory controller. 180 */ 181 static const struct pci_class pci_subclass_memory[] = { 182 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 183 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 184 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 185 { NULL, 0, NULL, }, 186 }; 187 188 /* 189 * Class 0x06. 190 * Bridge device. 191 */ 192 193 /* PCI bridge programming interface */ 194 static const struct pci_class pci_interface_pcibridge[] = { 195 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 196 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 197 { NULL, 0, NULL, }, 198 }; 199 200 /* Semi-transparent PCI-toPCI bridge programming interface */ 201 static const struct pci_class pci_interface_stpci[] = { 202 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 203 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 204 { NULL, 0, NULL, }, 205 }; 206 207 /* Subclasses */ 208 static const struct pci_class pci_subclass_bridge[] = { 209 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 210 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 211 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 212 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 213 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 214 pci_interface_pcibridge, }, 215 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 216 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 217 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 218 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 219 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 220 pci_interface_stpci, }, 221 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 222 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 223 { NULL, 0, NULL, }, 224 }; 225 226 /* 227 * Class 0x07. 228 * Simple communications controller. 229 */ 230 231 /* Serial controller programming interface */ 232 static const struct pci_class pci_interface_serial[] = { 233 { "genric XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 234 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 235 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 236 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 237 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 238 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 239 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 240 { NULL, 0, NULL, }, 241 }; 242 243 /* Parallel controller programming interface */ 244 static const struct pci_class pci_interface_parallel[] = { 245 { "", PCI_INTERFACE_PARALLEL, NULL,}, 246 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 247 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 248 { "IEEE1284", PCI_INTERFACE_PARALLEL_IEEE1284, NULL,}, 249 { "IEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 250 { NULL, 0, NULL,}, 251 }; 252 253 /* Modem programming interface */ 254 static const struct pci_class pci_interface_modem[] = { 255 { "", PCI_INTERFACE_MODEM, NULL,}, 256 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 257 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 258 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 259 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 260 { NULL, 0, NULL,}, 261 }; 262 263 /* Subclasses */ 264 static const struct pci_class pci_subclass_communications[] = { 265 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 266 pci_interface_serial, }, 267 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 268 pci_interface_parallel, }, 269 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 270 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 271 pci_interface_modem, }, 272 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 273 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 274 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 275 { NULL, 0, NULL,}, 276 }; 277 278 /* 279 * Class 0x08. 280 * Base system peripheral. 281 */ 282 283 /* PIC programming interface */ 284 static const struct pci_class pci_interface_pic[] = { 285 { "genric 8259", PCI_INTERFACE_PIC_8259, NULL, }, 286 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 287 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 288 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 289 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 290 { NULL, 0, NULL, }, 291 }; 292 293 /* DMA programming interface */ 294 static const struct pci_class pci_interface_dma[] = { 295 { "genric 8237", PCI_INTERFACE_DMA_8237, NULL, }, 296 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 297 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 298 { NULL, 0, NULL, }, 299 }; 300 301 /* Timer programming interface */ 302 static const struct pci_class pci_interface_tmr[] = { 303 { "genric 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 304 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 305 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 306 { NULL, 0, NULL, }, 307 }; 308 309 /* RTC programming interface */ 310 static const struct pci_class pci_interface_rtc[] = { 311 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 312 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 313 { NULL, 0, NULL, }, 314 }; 315 316 /* Subclasses */ 317 static const struct pci_class pci_subclass_system[] = { 318 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 319 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 320 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 321 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 322 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 323 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 324 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 325 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 326 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 327 { NULL, 0, NULL, }, 328 }; 329 330 /* 331 * Class 0x09. 332 * Input device. 333 */ 334 335 /* Gameport programming interface */ 336 static const struct pci_class pci_interface_game[] = { 337 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 338 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 339 { NULL, 0, NULL, }, 340 }; 341 342 /* Subclasses */ 343 static const struct pci_class pci_subclass_input[] = { 344 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 345 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 346 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 347 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 348 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 349 pci_interface_game, }, 350 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 351 { NULL, 0, NULL, }, 352 }; 353 354 /* 355 * Class 0x0a. 356 * Docking station. 357 */ 358 static const struct pci_class pci_subclass_dock[] = { 359 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 360 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 361 { NULL, 0, NULL, }, 362 }; 363 364 /* 365 * Class 0x0b. 366 * Processor. 367 */ 368 static const struct pci_class pci_subclass_processor[] = { 369 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 370 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 371 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 372 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 373 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 374 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 375 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 376 { NULL, 0, NULL, }, 377 }; 378 379 /* 380 * Class 0x0c. 381 * Serial bus controller. 382 */ 383 384 /* IEEE1394 programming interface */ 385 static const struct pci_class pci_interface_ieee1394[] = { 386 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 387 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 388 { NULL, 0, NULL,}, 389 }; 390 391 /* USB programming interface */ 392 static const struct pci_class pci_interface_usb[] = { 393 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 394 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 395 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 396 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 397 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 398 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 399 { NULL, 0, NULL, }, 400 }; 401 402 /* IPMI programming interface */ 403 static const struct pci_class pci_interface_ipmi[] = { 404 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 405 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 406 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 407 { NULL, 0, NULL,}, 408 }; 409 410 /* Subclasses */ 411 static const struct pci_class pci_subclass_serialbus[] = { 412 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 413 pci_interface_ieee1394, }, 414 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 415 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 416 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 417 pci_interface_usb, }, 418 /* XXX Fiber Channel/_FIBRECHANNEL */ 419 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 420 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 421 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 422 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 423 pci_interface_ipmi, }, 424 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 425 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 426 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 427 { NULL, 0, NULL, }, 428 }; 429 430 /* 431 * Class 0x0d. 432 * Wireless Controller. 433 */ 434 static const struct pci_class pci_subclass_wireless[] = { 435 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 436 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 437 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 438 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 439 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 440 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 441 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 442 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 443 { NULL, 0, NULL, }, 444 }; 445 446 /* 447 * Class 0x0e. 448 * Intelligent IO controller. 449 */ 450 451 /* Intelligent IO programming interface */ 452 static const struct pci_class pci_interface_i2o[] = { 453 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 454 { NULL, 0, NULL,}, 455 }; 456 457 /* Subclasses */ 458 static const struct pci_class pci_subclass_i2o[] = { 459 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 460 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 461 { NULL, 0, NULL, }, 462 }; 463 464 /* 465 * Class 0x0f. 466 * Satellite communication controller. 467 */ 468 static const struct pci_class pci_subclass_satcom[] = { 469 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 470 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 471 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 472 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 473 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 474 { NULL, 0, NULL, }, 475 }; 476 477 /* 478 * Class 0x10. 479 * Encryption/Decryption controller. 480 */ 481 static const struct pci_class pci_subclass_crypto[] = { 482 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 483 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 484 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 485 { NULL, 0, NULL, }, 486 }; 487 488 /* 489 * Class 0x11. 490 * Data aquuisition and signal processing controller. 491 */ 492 static const struct pci_class pci_subclass_dasp[] = { 493 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 494 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 495 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 496 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 497 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 498 { NULL, 0, NULL, }, 499 }; 500 501 /* List of classes */ 502 static const struct pci_class pci_class[] = { 503 { "prehistoric", PCI_CLASS_PREHISTORIC, 504 pci_subclass_prehistoric, }, 505 { "mass storage", PCI_CLASS_MASS_STORAGE, 506 pci_subclass_mass_storage, }, 507 { "network", PCI_CLASS_NETWORK, 508 pci_subclass_network, }, 509 { "display", PCI_CLASS_DISPLAY, 510 pci_subclass_display, }, 511 { "multimedia", PCI_CLASS_MULTIMEDIA, 512 pci_subclass_multimedia, }, 513 { "memory", PCI_CLASS_MEMORY, 514 pci_subclass_memory, }, 515 { "bridge", PCI_CLASS_BRIDGE, 516 pci_subclass_bridge, }, 517 { "communications", PCI_CLASS_COMMUNICATIONS, 518 pci_subclass_communications, }, 519 { "system", PCI_CLASS_SYSTEM, 520 pci_subclass_system, }, 521 { "input", PCI_CLASS_INPUT, 522 pci_subclass_input, }, 523 { "dock", PCI_CLASS_DOCK, 524 pci_subclass_dock, }, 525 { "processor", PCI_CLASS_PROCESSOR, 526 pci_subclass_processor, }, 527 { "serial bus", PCI_CLASS_SERIALBUS, 528 pci_subclass_serialbus, }, 529 { "wireless", PCI_CLASS_WIRELESS, 530 pci_subclass_wireless, }, 531 { "I2O", PCI_CLASS_I2O, 532 pci_subclass_i2o, }, 533 { "satellite comm", PCI_CLASS_SATCOM, 534 pci_subclass_satcom, }, 535 { "crypto", PCI_CLASS_CRYPTO, 536 pci_subclass_crypto, }, 537 { "DASP", PCI_CLASS_DASP, 538 pci_subclass_dasp, }, 539 { "undefined", PCI_CLASS_UNDEFINED, 540 NULL, }, 541 { NULL, 0, 542 NULL, }, 543 }; 544 545 DEV_VERBOSE_DEFINE(pci); 546 547 void 548 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 549 size_t l) 550 { 551 pci_class_t pciclass; 552 pci_subclass_t subclass; 553 pci_interface_t interface; 554 pci_revision_t revision; 555 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 556 const struct pci_class *classp, *subclassp, *interfacep; 557 char *ep; 558 559 ep = cp + l; 560 561 pciclass = PCI_CLASS(class_reg); 562 subclass = PCI_SUBCLASS(class_reg); 563 interface = PCI_INTERFACE(class_reg); 564 revision = PCI_REVISION(class_reg); 565 566 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 567 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 568 PCI_PRODUCT(id_reg)); 569 570 classp = pci_class; 571 while (classp->name != NULL) { 572 if (pciclass == classp->val) 573 break; 574 classp++; 575 } 576 577 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 578 while (subclassp && subclassp->name != NULL) { 579 if (subclass == subclassp->val) 580 break; 581 subclassp++; 582 } 583 584 interfacep = (subclassp && subclassp->name != NULL) ? 585 subclassp->subclasses : NULL; 586 while (interfacep && interfacep->name != NULL) { 587 if (interface == interfacep->val) 588 break; 589 interfacep++; 590 } 591 592 cp += snprintf(cp, ep - cp, "%s %s", vendor, product); 593 if (showclass) { 594 cp += snprintf(cp, ep - cp, " ("); 595 if (classp->name == NULL) 596 cp += snprintf(cp, ep - cp, 597 "class 0x%02x, subclass 0x%02x", pciclass, subclass); 598 else { 599 if (subclassp == NULL || subclassp->name == NULL) 600 cp += snprintf(cp, ep - cp, 601 "%s, subclass 0x%02x", 602 classp->name, subclass); 603 else 604 cp += snprintf(cp, ep - cp, "%s %s", 605 subclassp->name, classp->name); 606 } 607 if ((interfacep == NULL) || (interfacep->name == NULL)) { 608 if (interface != 0) 609 cp += snprintf(cp, ep - cp, 610 ", interface 0x%02x", interface); 611 } else if (strncmp(interfacep->name, "", 1) != 0) 612 cp += snprintf(cp, ep - cp, ", %s", 613 interfacep->name); 614 if (revision != 0) 615 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 616 revision); 617 cp += snprintf(cp, ep - cp, ")"); 618 } 619 } 620 621 #ifdef _KERNEL 622 void 623 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 624 const char *known, int addrev) 625 { 626 char devinfo[256]; 627 628 if (known) { 629 aprint_normal(": %s", known); 630 if (addrev) 631 aprint_normal(" (rev. 0x%02x)", 632 PCI_REVISION(pa->pa_class)); 633 aprint_normal("\n"); 634 } else { 635 pci_devinfo(pa->pa_id, pa->pa_class, 0, 636 devinfo, sizeof(devinfo)); 637 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 638 PCI_REVISION(pa->pa_class)); 639 } 640 if (naive) 641 aprint_naive(": %s\n", naive); 642 else 643 aprint_naive("\n"); 644 } 645 #endif 646 647 /* 648 * Print out most of the PCI configuration registers. Typically used 649 * in a device attach routine like this: 650 * 651 * #ifdef MYDEV_DEBUG 652 * printf("%s: ", device_xname(sc->sc_dev)); 653 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 654 * #endif 655 */ 656 657 #define i2o(i) ((i) * 4) 658 #define o2i(o) ((o) / 4) 659 #define onoff2(str, rval, bit, onstr, offstr) \ 660 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 661 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 662 663 static void 664 pci_conf_print_common( 665 #ifdef _KERNEL 666 pci_chipset_tag_t pc, pcitag_t tag, 667 #endif 668 const pcireg_t *regs) 669 { 670 const char *name; 671 const struct pci_class *classp, *subclassp; 672 char vendor[PCI_VENDORSTR_LEN]; 673 char product[PCI_PRODUCTSTR_LEN]; 674 pcireg_t rval; 675 unsigned int num; 676 677 rval = regs[o2i(PCI_ID_REG)]; 678 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 679 if (name) 680 printf(" Vendor Name: %s (0x%04x)\n", name, 681 PCI_VENDOR(rval)); 682 else 683 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 684 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 685 PCI_PRODUCT(rval)); 686 if (name) 687 printf(" Device Name: %s (0x%04x)\n", name, 688 PCI_PRODUCT(rval)); 689 else 690 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 691 692 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 693 694 printf(" Command register: 0x%04x\n", rval & 0xffff); 695 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 696 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 697 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 698 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 699 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 700 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 701 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 702 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 703 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 704 onoff("Fast back-to-back transactions", rval, 705 PCI_COMMAND_BACKTOBACK_ENABLE); 706 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 707 708 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 709 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 710 "inactive"); 711 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 712 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 713 onoff("User Definable Features (UDF) support", rval, 714 PCI_STATUS_UDF_SUPPORT); 715 onoff("Fast back-to-back capable", rval, 716 PCI_STATUS_BACKTOBACK_SUPPORT); 717 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 718 719 printf(" DEVSEL timing: "); 720 switch (rval & PCI_STATUS_DEVSEL_MASK) { 721 case PCI_STATUS_DEVSEL_FAST: 722 printf("fast"); 723 break; 724 case PCI_STATUS_DEVSEL_MEDIUM: 725 printf("medium"); 726 break; 727 case PCI_STATUS_DEVSEL_SLOW: 728 printf("slow"); 729 break; 730 default: 731 printf("unknown/reserved"); /* XXX */ 732 break; 733 } 734 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 735 736 onoff("Slave signaled Target Abort", rval, 737 PCI_STATUS_TARGET_TARGET_ABORT); 738 onoff("Master received Target Abort", rval, 739 PCI_STATUS_MASTER_TARGET_ABORT); 740 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 741 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 742 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 743 744 rval = regs[o2i(PCI_CLASS_REG)]; 745 for (classp = pci_class; classp->name != NULL; classp++) { 746 if (PCI_CLASS(rval) == classp->val) 747 break; 748 } 749 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 750 while (subclassp && subclassp->name != NULL) { 751 if (PCI_SUBCLASS(rval) == subclassp->val) 752 break; 753 subclassp++; 754 } 755 if (classp->name != NULL) { 756 printf(" Class Name: %s (0x%02x)\n", classp->name, 757 PCI_CLASS(rval)); 758 if (subclassp != NULL && subclassp->name != NULL) 759 printf(" Subclass Name: %s (0x%02x)\n", 760 subclassp->name, PCI_SUBCLASS(rval)); 761 else 762 printf(" Subclass ID: 0x%02x\n", 763 PCI_SUBCLASS(rval)); 764 } else { 765 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 766 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 767 } 768 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 769 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 770 771 rval = regs[o2i(PCI_BHLC_REG)]; 772 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 773 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 774 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 775 PCI_HDRTYPE(rval)); 776 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 777 num = PCI_CACHELINE(rval); 778 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 779 } 780 781 static int 782 pci_conf_print_bar( 783 #ifdef _KERNEL 784 pci_chipset_tag_t pc, pcitag_t tag, 785 #endif 786 const pcireg_t *regs, int reg, const char *name 787 #ifdef _KERNEL 788 , int sizebar 789 #endif 790 ) 791 { 792 int width; 793 pcireg_t rval, rval64h; 794 #ifdef _KERNEL 795 int s; 796 pcireg_t mask, mask64h; 797 #endif 798 799 width = 4; 800 801 /* 802 * Section 6.2.5.1, `Address Maps', tells us that: 803 * 804 * 1) The builtin software should have already mapped the 805 * device in a reasonable way. 806 * 807 * 2) A device which wants 2^n bytes of memory will hardwire 808 * the bottom n bits of the address to 0. As recommended, 809 * we write all 1s and see what we get back. 810 */ 811 812 rval = regs[o2i(reg)]; 813 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 814 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 815 rval64h = regs[o2i(reg + 4)]; 816 width = 8; 817 } else 818 rval64h = 0; 819 820 #ifdef _KERNEL 821 /* XXX don't size unknown memory type? */ 822 if (rval != 0 && sizebar) { 823 /* 824 * The following sequence seems to make some devices 825 * (e.g. host bus bridges, which don't normally 826 * have their space mapped) very unhappy, to 827 * the point of crashing the system. 828 * 829 * Therefore, if the mapping register is zero to 830 * start out with, don't bother trying. 831 */ 832 s = splhigh(); 833 pci_conf_write(pc, tag, reg, 0xffffffff); 834 mask = pci_conf_read(pc, tag, reg); 835 pci_conf_write(pc, tag, reg, rval); 836 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 837 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 838 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 839 mask64h = pci_conf_read(pc, tag, reg + 4); 840 pci_conf_write(pc, tag, reg + 4, rval64h); 841 } else 842 mask64h = 0; 843 splx(s); 844 } else 845 mask = mask64h = 0; 846 #endif /* _KERNEL */ 847 848 printf(" Base address register at 0x%02x", reg); 849 if (name) 850 printf(" (%s)", name); 851 printf("\n "); 852 if (rval == 0) { 853 printf("not implemented(?)\n"); 854 return width; 855 } 856 printf("type: "); 857 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 858 const char *type, *prefetch; 859 860 switch (PCI_MAPREG_MEM_TYPE(rval)) { 861 case PCI_MAPREG_MEM_TYPE_32BIT: 862 type = "32-bit"; 863 break; 864 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 865 type = "32-bit-1M"; 866 break; 867 case PCI_MAPREG_MEM_TYPE_64BIT: 868 type = "64-bit"; 869 break; 870 default: 871 type = "unknown (XXX)"; 872 break; 873 } 874 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 875 prefetch = ""; 876 else 877 prefetch = "non"; 878 printf("%s %sprefetchable memory\n", type, prefetch); 879 switch (PCI_MAPREG_MEM_TYPE(rval)) { 880 case PCI_MAPREG_MEM_TYPE_64BIT: 881 printf(" base: 0x%016llx, ", 882 PCI_MAPREG_MEM64_ADDR( 883 ((((long long) rval64h) << 32) | rval))); 884 #ifdef _KERNEL 885 if (sizebar) 886 printf("size: 0x%016llx", 887 PCI_MAPREG_MEM64_SIZE( 888 ((((long long) mask64h) << 32) | mask))); 889 else 890 #endif /* _KERNEL */ 891 printf("not sized"); 892 printf("\n"); 893 break; 894 case PCI_MAPREG_MEM_TYPE_32BIT: 895 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 896 default: 897 printf(" base: 0x%08x, ", 898 PCI_MAPREG_MEM_ADDR(rval)); 899 #ifdef _KERNEL 900 if (sizebar) 901 printf("size: 0x%08x", 902 PCI_MAPREG_MEM_SIZE(mask)); 903 else 904 #endif /* _KERNEL */ 905 printf("not sized"); 906 printf("\n"); 907 break; 908 } 909 } else { 910 #ifdef _KERNEL 911 if (sizebar) 912 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 913 #endif /* _KERNEL */ 914 printf("i/o\n"); 915 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 916 #ifdef _KERNEL 917 if (sizebar) 918 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 919 else 920 #endif /* _KERNEL */ 921 printf("not sized"); 922 printf("\n"); 923 } 924 925 return width; 926 } 927 928 static void 929 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 930 { 931 int off, needaddr, neednl; 932 933 needaddr = 1; 934 neednl = 0; 935 for (off = first; off < pastlast; off += 4) { 936 if ((off % 16) == 0 || needaddr) { 937 printf(" 0x%02x:", off); 938 needaddr = 0; 939 } 940 printf(" 0x%08x", regs[o2i(off)]); 941 neednl = 1; 942 if ((off % 16) == 12) { 943 printf("\n"); 944 neednl = 0; 945 } 946 } 947 if (neednl) 948 printf("\n"); 949 } 950 951 static const char * 952 pci_conf_print_pcipm_cap_aux(uint16_t caps) 953 { 954 955 switch ((caps >> 6) & 7) { 956 case 0: return "self-powered"; 957 case 1: return "55 mA"; 958 case 2: return "100 mA"; 959 case 3: return "160 mA"; 960 case 4: return "220 mA"; 961 case 5: return "270 mA"; 962 case 6: return "320 mA"; 963 case 7: 964 default: return "375 mA"; 965 } 966 } 967 968 static const char * 969 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 970 { 971 static const char unk[] = "unknown"; 972 static const char *pmrev[8] = { 973 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 974 }; 975 if (val > 7) 976 return unk; 977 return pmrev[val]; 978 } 979 980 static void 981 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 982 { 983 uint16_t caps, pmcsr; 984 pcireg_t reg; 985 986 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 987 reg = regs[o2i(capoff + PCI_PMCSR)]; 988 pmcsr = reg & 0xffff; 989 990 printf("\n PCI Power Management Capabilities Register\n"); 991 992 printf(" Capabilities register: 0x%04x\n", caps); 993 printf(" Version: %s\n", 994 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 995 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 996 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 997 printf(" 3.3V auxiliary current: %s\n", 998 pci_conf_print_pcipm_cap_aux(caps)); 999 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1000 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1001 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1002 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1003 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1004 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1005 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1006 1007 printf(" Control/status register: 0x%04x\n", pmcsr); 1008 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1009 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1010 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1011 printf(" PME# assertion: %sabled\n", 1012 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1013 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1014 printf(" Bridge Support Extensions register: 0x%02x\n", 1015 (reg >> 16) & 0xff); 1016 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1017 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1018 printf(" Data register: 0x%02x\n", (reg >> 24) & 0xff); 1019 1020 } 1021 1022 /* XXX pci_conf_print_vpd_cap */ 1023 /* XXX pci_conf_print_slotid_cap */ 1024 1025 static void 1026 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1027 { 1028 uint32_t ctl, mmc, mme; 1029 1030 regs += o2i(capoff); 1031 ctl = *regs++; 1032 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1033 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1034 1035 printf("\n PCI Message Signaled Interrupt\n"); 1036 1037 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1038 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1039 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1040 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1041 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1042 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1043 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1044 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1045 printf(" Message Address %sregister: 0x%08x\n", 1046 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1047 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1048 printf(" Message Address %sregister: 0x%08x\n", 1049 "(upper) ", *regs++); 1050 } 1051 printf(" Message Data register: 0x%08x\n", *regs++); 1052 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1053 printf(" Vector Mask register: 0x%08x\n", *regs++); 1054 printf(" Vector Pending register: 0x%08x\n", *regs++); 1055 } 1056 } 1057 1058 /* XXX pci_conf_print_cpci_hostwap_cap */ 1059 1060 /* 1061 * For both command register and status register. 1062 * The argument "idx" is index number (0 to 7). 1063 */ 1064 static int 1065 pcix_split_trans(unsigned int idx) 1066 { 1067 static int table[8] = { 1068 1, 2, 3, 4, 8, 12, 16, 32 1069 }; 1070 1071 if (idx >= __arraycount(table)) 1072 return -1; 1073 return table[idx]; 1074 } 1075 1076 static void 1077 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1078 { 1079 pcireg_t reg; 1080 int isbridge; 1081 int i; 1082 1083 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1084 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1085 printf("\n PCI-X %s Capabilities Register\n", 1086 isbridge ? "Bridge" : "Non-bridge"); 1087 1088 reg = regs[o2i(capoff)]; 1089 if (isbridge != 0) { 1090 printf(" Secondary status register: 0x%04x\n", 1091 (reg & 0xffff0000) >> 16); 1092 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1093 onoff("133MHz capable", reg, PCIX_STATUS_133); 1094 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1095 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1096 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1097 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1098 printf(" Secondary clock frequency: 0x%x\n", 1099 (reg & PCIX_BRIDGE_2NDST_CLKF) 1100 >> PCIX_BRIDGE_2NDST_CLKF_SHIFT); 1101 printf(" Version: 0x%x\n", 1102 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1103 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1104 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1105 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1106 } else { 1107 printf(" Command register: 0x%04x\n", 1108 (reg & 0xffff0000) >> 16); 1109 onoff("Data Parity Error Recovery", reg, 1110 PCIX_CMD_PERR_RECOVER); 1111 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1112 printf(" Maximum Burst Read Count: %u\n", 1113 PCIX_CMD_BYTECNT(reg)); 1114 printf(" Maximum Split Transactions: %d\n", 1115 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1116 >> PCIX_CMD_SPLTRANS_SHIFT)); 1117 } 1118 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1119 printf(" %sStatus register: 0x%08x\n", 1120 isbridge ? "Bridge " : "", reg); 1121 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1122 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1123 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1124 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1125 onoff("133MHz capable", reg, PCIX_STATUS_133); 1126 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1127 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1128 if (isbridge != 0) { 1129 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1130 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1131 } else { 1132 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1133 "bridge device", "simple device"); 1134 printf(" Designed max memory read byte count: %d\n", 1135 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1136 >> PCIX_STATUS_MAXB_SHIFT)); 1137 printf(" Designed max outstanding split transaction: %d\n", 1138 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1139 >> PCIX_STATUS_MAXST_SHIFT)); 1140 printf(" MAX cumulative Read Size: %u\n", 1141 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1142 onoff("Received split completion error", reg, 1143 PCIX_STATUS_SCERR); 1144 } 1145 onoff("266MHz capable", reg, PCIX_STATUS_266); 1146 onoff("533MHz capable", reg, PCIX_STATUS_533); 1147 1148 if (isbridge == 0) 1149 return; 1150 1151 /* Only for bridge */ 1152 for (i = 0; i < 2; i++) { 1153 reg = regs[o2i(capoff+PCIX_BRIDGE_UP_STCR + (4 * i))]; 1154 printf(" %s split transaction control register: 0x%08x\n", 1155 (i == 0) ? "Upstream" : "Downstream", reg); 1156 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1157 printf(" Commitment Limit: %d\n", 1158 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1159 } 1160 } 1161 1162 /* XXX pci_conf_print_ldt_cap */ 1163 1164 static void 1165 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1166 { 1167 uint16_t caps; 1168 1169 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1170 1171 printf("\n PCI Vendor Specific Capabilities Register\n"); 1172 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1173 } 1174 1175 static void 1176 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1177 { 1178 pcireg_t val; 1179 1180 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1181 1182 printf("\n Debugport Capability Register\n"); 1183 printf(" Debug base Register: 0x%04x\n", 1184 val >> PCI_DEBUG_BASER_SHIFT); 1185 printf(" port offset: 0x%04x\n", 1186 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1187 printf(" BAR number: %u\n", 1188 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1189 } 1190 1191 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1192 /* XXX pci_conf_print_hotplug_cap */ 1193 1194 static void 1195 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1196 { 1197 pcireg_t reg; 1198 1199 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1200 1201 printf("\n Subsystem ID Capability Register\n"); 1202 printf(" Subsystem ID : 0x%08x\n", reg); 1203 } 1204 1205 /* XXX pci_conf_print_agp8_cap */ 1206 /* XXX pci_conf_print_secure_cap */ 1207 1208 static void 1209 pci_print_pcie_L0s_latency(uint32_t val) 1210 { 1211 1212 switch (val) { 1213 case 0x0: 1214 printf("Less than 64ns\n"); 1215 break; 1216 case 0x1: 1217 case 0x2: 1218 case 0x3: 1219 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1220 break; 1221 case 0x4: 1222 printf("512ns to less than 1us\n"); 1223 break; 1224 case 0x5: 1225 printf("1us to less than 2us\n"); 1226 break; 1227 case 0x6: 1228 printf("2us - 4us\n"); 1229 break; 1230 case 0x7: 1231 printf("More than 4us\n"); 1232 break; 1233 } 1234 } 1235 1236 static void 1237 pci_print_pcie_L1_latency(uint32_t val) 1238 { 1239 1240 switch (val) { 1241 case 0x0: 1242 printf("Less than 1us\n"); 1243 break; 1244 case 0x6: 1245 printf("32us - 64us\n"); 1246 break; 1247 case 0x7: 1248 printf("More than 64us\n"); 1249 break; 1250 default: 1251 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1252 break; 1253 } 1254 } 1255 1256 static void 1257 pci_print_pcie_compl_timeout(uint32_t val) 1258 { 1259 1260 switch (val) { 1261 case 0x0: 1262 printf("50us to 50ms\n"); 1263 break; 1264 case 0x5: 1265 printf("16ms to 55ms\n"); 1266 break; 1267 case 0x6: 1268 printf("65ms to 210ms\n"); 1269 break; 1270 case 0x9: 1271 printf("260ms to 900ms\n"); 1272 break; 1273 case 0xa: 1274 printf("1s to 3.5s\n"); 1275 break; 1276 default: 1277 printf("unknown %u value\n", val); 1278 break; 1279 } 1280 } 1281 1282 static void 1283 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1284 { 1285 pcireg_t reg; /* for each register */ 1286 pcireg_t val; /* for each bitfield */ 1287 bool check_link = false; 1288 bool check_slot = false; 1289 bool check_rootport = false; 1290 unsigned int pciever; 1291 static const char * const linkspeeds[] = {"2.5", "5.0", "8.0"}; 1292 int i; 1293 1294 printf("\n PCI Express Capabilities Register\n"); 1295 /* Capability Register */ 1296 reg = regs[o2i(capoff)]; 1297 printf(" Capability register: %04x\n", reg >> 16); 1298 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1299 printf(" Capability version: %u\n", pciever); 1300 printf(" Device type: "); 1301 switch ((reg & 0x00f00000) >> 20) { 1302 case 0x0: 1303 printf("PCI Express Endpoint device\n"); 1304 check_link = true; 1305 break; 1306 case 0x1: 1307 printf("Legacy PCI Express Endpoint device\n"); 1308 check_link = true; 1309 break; 1310 case 0x4: 1311 printf("Root Port of PCI Express Root Complex\n"); 1312 check_link = true; 1313 check_slot = true; 1314 check_rootport = true; 1315 break; 1316 case 0x5: 1317 printf("Upstream Port of PCI Express Switch\n"); 1318 break; 1319 case 0x6: 1320 printf("Downstream Port of PCI Express Switch\n"); 1321 check_slot = true; 1322 check_rootport = true; 1323 break; 1324 case 0x7: 1325 printf("PCI Express to PCI/PCI-X Bridge\n"); 1326 break; 1327 case 0x8: 1328 printf("PCI/PCI-X to PCI Express Bridge\n"); 1329 break; 1330 case 0x9: 1331 printf("Root Complex Integrated Endpoint\n"); 1332 break; 1333 case 0xa: 1334 check_rootport = true; 1335 printf("Root Complex Event Collector\n"); 1336 break; 1337 default: 1338 printf("unknown\n"); 1339 break; 1340 } 1341 if (check_slot && (reg & PCIE_XCAP_SI) != 0) 1342 printf(" Slot implemented\n"); 1343 printf(" Interrupt Message Number: %x\n", 1344 (unsigned int)((reg & PCIE_XCAP_IRQ) >> 27)); 1345 1346 /* Device Capability Register */ 1347 reg = regs[o2i(capoff + PCIE_DCAP)]; 1348 printf(" Device Capabilities Register: 0x%08x\n", reg); 1349 printf(" Max Payload Size Supported: %u bytes max\n", 1350 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1351 printf(" Phantom Functions Supported: "); 1352 switch ((reg & PCIE_DCAP_PHANTOM_FUNCS) >> 3) { 1353 case 0x0: 1354 printf("not available\n"); 1355 break; 1356 case 0x1: 1357 printf("MSB\n"); 1358 break; 1359 case 0x2: 1360 printf("two MSB\n"); 1361 break; 1362 case 0x3: 1363 printf("All three bits\n"); 1364 break; 1365 } 1366 printf(" Extended Tag Field Supported: %dbit\n", 1367 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1368 printf(" Endpoint L0 Acceptable Latency: "); 1369 pci_print_pcie_L0s_latency((reg & PCIE_DCAP_L0S_LATENCY) >> 6); 1370 printf(" Endpoint L1 Acceptable Latency: "); 1371 pci_print_pcie_L1_latency((reg & PCIE_DCAP_L1_LATENCY) >> 9); 1372 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1373 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1374 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1375 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1376 printf(" Captured Slot Power Limit Value: %d\n", 1377 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18); 1378 printf(" Captured Slot Power Limit Scale: %d\n", 1379 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26); 1380 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1381 1382 /* Device Control Register */ 1383 reg = regs[o2i(capoff + PCIE_DCSR)]; 1384 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1385 onoff("Correctable Error Reporting Enable", reg, 1386 PCIE_DCSR_ENA_COR_ERR); 1387 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1388 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1389 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1390 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1391 printf(" Max Payload Size: %d byte\n", 1392 128 << (((unsigned int)(reg & PCIE_DCSR_MAX_PAYLOAD) >> 5))); 1393 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1394 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1395 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1396 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1397 printf(" Max Read Request Size: %d byte\n", 1398 128 << ((unsigned int)(reg & PCIE_DCSR_MAX_READ_REQ) >> 12)); 1399 1400 /* Device Status Register */ 1401 reg = regs[o2i(capoff + PCIE_DCSR)]; 1402 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1403 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1404 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1405 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1406 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1407 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1408 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1409 1410 if (check_link) { 1411 /* Link Capability Register */ 1412 reg = regs[o2i(capoff + PCIE_LCAP)]; 1413 printf(" Link Capabilities Register: 0x%08x\n", reg); 1414 printf(" Maximum Link Speed: "); 1415 val = reg & PCIE_LCAP_MAX_SPEED; 1416 if (val < 1 || val > 3) { 1417 printf("unknown %u value\n", val); 1418 } else { 1419 printf("%sGT/s\n", linkspeeds[val - 1]); 1420 } 1421 printf(" Maximum Link Width: x%u lanes\n", 1422 (unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4); 1423 printf(" Active State PM Support: "); 1424 val = (reg & PCIE_LCAP_ASPM) >> 10; 1425 switch (val) { 1426 case 0x1: 1427 printf("L0s Entry supported\n"); 1428 break; 1429 case 0x3: 1430 printf("L0s and L1 supported\n"); 1431 break; 1432 default: 1433 printf("Reserved value\n"); 1434 break; 1435 } 1436 printf(" L0 Exit Latency: "); 1437 pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12); 1438 printf(" L1 Exit Latency: "); 1439 pci_print_pcie_L1_latency((reg & PCIE_LCAP_L1_EXIT) >> 15); 1440 printf(" Port Number: %u\n", reg >> 24); 1441 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1442 onoff("Surprise Down Error Report", reg, 1443 PCIE_LCAP_SURPRISE_DOWN); 1444 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1445 onoff("Link BW Notification Capable", reg, 1446 PCIE_LCAP_LINK_BW_NOTIFY); 1447 onoff("ASPM Optionally Compliance", reg, 1448 PCIE_LCAP_ASPM_COMPLIANCE); 1449 1450 /* Link Control Register */ 1451 reg = regs[o2i(capoff + PCIE_LCSR)]; 1452 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1453 printf(" Active State PM Control: "); 1454 val = reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S); 1455 switch (val) { 1456 case 0: 1457 printf("disabled\n"); 1458 break; 1459 case 1: 1460 printf("L0s Entry Enabled\n"); 1461 break; 1462 case 2: 1463 printf("L1 Entry Enabled\n"); 1464 break; 1465 case 3: 1466 printf("L0s and L1 Entry Enabled\n"); 1467 break; 1468 } 1469 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1470 "128bytes", "64bytes"); 1471 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1472 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1473 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1474 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1475 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1476 onoff("Hardware Autonomous Width Disable", reg, 1477 PCIE_LCSR_HAWD); 1478 onoff("Link Bandwidth Management Interrupt Enable", reg, 1479 PCIE_LCSR_LBMIE); 1480 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1481 PCIE_LCSR_LABIE); 1482 1483 /* Link Status Register */ 1484 reg = regs[o2i(capoff + PCIE_LCSR)]; 1485 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1486 printf(" Negotiated Link Speed: "); 1487 if (((reg >> 16) & 0x000f) < 1 || 1488 ((reg >> 16) & 0x000f) > 3) { 1489 printf("unknown %u value\n", 1490 (unsigned int)(reg & PCIE_LCSR_LINKSPEED) >> 16); 1491 } else { 1492 printf("%sGT/s\n", 1493 linkspeeds[((reg & PCIE_LCSR_LINKSPEED) >> 16)-1]); 1494 } 1495 printf(" Negotiated Link Width: x%u lanes\n", 1496 (reg >> 20) & 0x003f); 1497 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1498 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1499 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1500 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1501 onoff("Link Bandwidth Management Status", reg, 1502 PCIE_LCSR_LINK_BW_MGMT); 1503 onoff("Link Autonomous Bandwidth Status", reg, 1504 PCIE_LCSR_LINK_AUTO_BW); 1505 } 1506 1507 if (check_slot == true) { 1508 /* Slot Capability Register */ 1509 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1510 printf(" Slot Capability Register: %08x\n", reg); 1511 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1512 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1513 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1514 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1515 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1516 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1517 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1518 printf(" Slot Power Limit Value: %d\n", 1519 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1520 printf(" Slot Power Limit Scale: %d\n", 1521 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1522 onoff("Electromechanical Interlock Present", reg, 1523 PCIE_SLCAP_EIP); 1524 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1525 printf(" Physical Slot Number: %d\n", 1526 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1527 1528 /* Slot Control Register */ 1529 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1530 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1531 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1532 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1533 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1534 onoff("Presense Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1535 onoff("Command Completed Interrupt Enabled", reg, 1536 PCIE_SLCSR_CCE); 1537 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1538 printf(" Attention Indicator Control: "); 1539 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1540 case 0x0: 1541 printf("reserved\n"); 1542 break; 1543 case 0x1: 1544 printf("on\n"); 1545 break; 1546 case 0x2: 1547 printf("blink\n"); 1548 break; 1549 case 0x3: 1550 printf("off\n"); 1551 break; 1552 } 1553 printf(" Power Indicator Control: "); 1554 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1555 case 0x0: 1556 printf("reserved\n"); 1557 break; 1558 case 0x1: 1559 printf("on\n"); 1560 break; 1561 case 0x2: 1562 printf("blink\n"); 1563 break; 1564 case 0x3: 1565 printf("off\n"); 1566 break; 1567 } 1568 onoff("Power Controller Control", reg, PCIE_SLCSR_PCC); 1569 onoff("Electromechanical Interlock Control", 1570 reg, PCIE_SLCSR_EIC); 1571 onoff("Data Link Layer State Changed Enable", reg, 1572 PCIE_SLCSR_DLLSCE); 1573 1574 /* Slot Status Register */ 1575 printf(" Slot Status Register: %04x\n", reg >> 16); 1576 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1577 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1578 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1579 onoff("Presense Detect Changed", reg, PCIE_SLCSR_PDC); 1580 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1581 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1582 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1583 onoff("Electromechanical Interlock engaged", reg, 1584 PCIE_SLCSR_EIS); 1585 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 1586 } 1587 1588 if (check_rootport == true) { 1589 /* Root Control Register */ 1590 reg = regs[o2i(capoff + PCIE_RCR)]; 1591 printf(" Root Control Register: %04x\n", reg & 0xffff); 1592 onoff("SERR on Correctable Error Enable", reg, 1593 PCIE_RCR_SERR_CER); 1594 onoff("SERR on Non-Fatal Error Enable", reg, 1595 PCIE_RCR_SERR_NFER); 1596 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 1597 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 1598 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 1599 1600 /* Root Capability Register */ 1601 printf(" Root Capability Register: %04x\n", 1602 reg >> 16); 1603 1604 /* Root Status Register */ 1605 reg = regs[o2i(capoff + PCIE_RSR)]; 1606 printf(" Root Status Register: %08x\n", reg); 1607 printf(" PME Requester ID: %04x\n", 1608 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1609 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 1610 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 1611 } 1612 1613 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1614 if (pciever < 2) 1615 return; 1616 1617 /* Device Capabilities 2 */ 1618 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1619 printf(" Device Capabilities 2: 0x%08x\n", reg); 1620 printf(" Completion Timeout Ranges Supported: %u \n", 1621 (unsigned int)(reg & PCIE_DCAP2_COMPT_RANGE)); 1622 onoff("Completion Timeout Disable Supported", reg, 1623 PCIE_DCAP2_COMPT_DIS); 1624 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 1625 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 1626 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 1627 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 1628 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 1629 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 1630 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 1631 printf(" TPH Completer Supported: %u\n", 1632 (unsigned int)(reg & PCIE_DCAP2_TPH_COMP) >> 12); 1633 printf(" OBFF Supported: "); 1634 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 1635 case 0x0: 1636 printf("Not supported\n"); 1637 break; 1638 case 0x1: 1639 printf("Message only\n"); 1640 break; 1641 case 0x2: 1642 printf("WAKE# only\n"); 1643 break; 1644 case 0x3: 1645 printf("Both\n"); 1646 break; 1647 } 1648 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 1649 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 1650 printf(" Max End-End TLP Prefixes: %u\n", 1651 (unsigned int)(reg & PCIE_DCAP2_MAX_EETLP) >> 22); 1652 1653 /* Device Control 2 */ 1654 reg = regs[o2i(capoff + PCIE_DCSR2)]; 1655 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 1656 printf(" Completion Timeout Value: "); 1657 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 1658 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 1659 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 1660 onoff("AtomicOp Rquester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 1661 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 1662 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 1663 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 1664 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 1665 printf(" OBFF: "); 1666 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 1667 case 0x0: 1668 printf("Disabled\n"); 1669 break; 1670 case 0x1: 1671 printf("Enabled with Message Signaling Variation A\n"); 1672 break; 1673 case 0x2: 1674 printf("Enabled with Message Signaling Variation B\n"); 1675 break; 1676 case 0x3: 1677 printf("Enabled using WAKE# signaling\n"); 1678 break; 1679 } 1680 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 1681 1682 if (check_link) { 1683 /* Link Capability 2 */ 1684 reg = regs[o2i(capoff + PCIE_LCAP2)]; 1685 printf(" Link Capabilities 2: 0x%08x\n", reg); 1686 val = (reg & PCIE_LCAP2_SUP_LNKSV) >> 1; 1687 printf(" Supported Link Speed Vector:"); 1688 for (i = 0; i <= 2; i++) { 1689 if (((val >> i) & 0x01) != 0) 1690 printf(" %sGT/s", linkspeeds[i]); 1691 } 1692 printf("\n"); 1693 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 1694 1695 /* Link Control 2 */ 1696 reg = regs[o2i(capoff + PCIE_LCSR2)]; 1697 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 1698 printf(" Target Link Speed: "); 1699 val = reg & PCIE_LCSR2_TGT_LSPEED; 1700 if (val < 1 || val > 3) 1701 printf("unknown %u value\n", val); 1702 else 1703 printf("%sGT/s\n", linkspeeds[val - 1]); 1704 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 1705 onoff("HW Autonomous Speed Disabled", reg, 1706 PCIE_LCSR2_HW_AS_DIS); 1707 onoff("Selectable De-emphasis", reg, PCIE_LCSR2_SEL_DEEMP); 1708 printf(" Transmit Margin: %u\n", 1709 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 1710 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 1711 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 1712 printf(" Compliance Present/De-emphasis: %u\n", 1713 (unsigned int)(reg & PCIE_LCSR2_COMP_DEEMP) >> 12); 1714 1715 /* Link Status 2 */ 1716 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 1717 onoff("Current De-emphasis Level", reg, PCIE_LCSR2_DEEMP_LVL); 1718 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 1719 onoff("Equalization Phase 1 Successful", reg, 1720 PCIE_LCSR2_EQP1_SUC); 1721 onoff("Equalization Phase 2 Successful", reg, 1722 PCIE_LCSR2_EQP2_SUC); 1723 onoff("Equalization Phase 3 Successful", reg, 1724 PCIE_LCSR2_EQP3_SUC); 1725 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 1726 } 1727 1728 /* Slot Capability 2 */ 1729 /* Slot Control 2 */ 1730 /* Slot Status 2 */ 1731 } 1732 1733 static void 1734 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 1735 { 1736 pcireg_t reg; 1737 1738 printf("\n MSI-X Capability Register\n"); 1739 1740 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 1741 printf(" Message Control register: 0x%04x\n", 1742 (reg >> 16) & 0xff); 1743 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 1744 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 1745 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 1746 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 1747 printf(" Table offset register: 0x%08x\n", reg); 1748 printf(" Table offset: %08x\n", reg & PCI_MSIX_TBLOFFSET_MASK); 1749 printf(" BIR: 0x%x\n", reg & PCI_MSIX_TBLBIR_MASK); 1750 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 1751 printf(" Pending bit array register: 0x%08x\n", reg); 1752 printf(" Pending bit array offset: %08x\n", 1753 reg & PCI_MSIX_PBAOFFSET_MASK); 1754 printf(" BIR: 0x%x\n", reg & PCI_MSIX_PBABIR_MASK); 1755 } 1756 1757 /* XXX pci_conf_print_sata_cap */ 1758 static void 1759 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 1760 { 1761 pcireg_t reg; 1762 1763 printf("\n Advanced Features Capability Register\n"); 1764 1765 reg = regs[o2i(capoff + PCI_AFCAPR)]; 1766 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 1767 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 1768 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 1769 reg = regs[o2i(capoff + PCI_AFCSR)]; 1770 printf(" AF Control register: 0x%02x\n", reg & 0xff); 1771 /* 1772 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 1773 * and it's always 0 on read 1774 */ 1775 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 1776 onoff("Transaction Pending", reg, PCI_AFSR_TP); 1777 } 1778 1779 static void 1780 pci_conf_print_caplist( 1781 #ifdef _KERNEL 1782 pci_chipset_tag_t pc, pcitag_t tag, 1783 #endif 1784 const pcireg_t *regs, int capoff) 1785 { 1786 int off; 1787 pcireg_t rval; 1788 int pcie_off = -1, pcipm_off = -1, msi_off = -1, pcix_off = -1; 1789 int vendspec_off = -1, msix_off = -1; 1790 int debugport_off = -1, subsystem_off = -1, pciaf_off = -1; 1791 1792 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1793 off != 0; 1794 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 1795 rval = regs[o2i(off)]; 1796 printf(" Capability register at 0x%02x\n", off); 1797 1798 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 1799 switch (PCI_CAPLIST_CAP(rval)) { 1800 case PCI_CAP_RESERVED0: 1801 printf("reserved"); 1802 break; 1803 case PCI_CAP_PWRMGMT: 1804 printf("Power Management, rev. %s", 1805 pci_conf_print_pcipm_cap_pmrev( 1806 (rval >> 0) & 0x07)); 1807 pcipm_off = off; 1808 break; 1809 case PCI_CAP_AGP: 1810 printf("AGP, rev. %d.%d", 1811 PCI_CAP_AGP_MAJOR(rval), 1812 PCI_CAP_AGP_MINOR(rval)); 1813 break; 1814 case PCI_CAP_VPD: 1815 printf("VPD"); 1816 break; 1817 case PCI_CAP_SLOTID: 1818 printf("SlotID"); 1819 break; 1820 case PCI_CAP_MSI: 1821 printf("MSI"); 1822 msi_off = off; 1823 break; 1824 case PCI_CAP_CPCI_HOTSWAP: 1825 printf("CompactPCI Hot-swapping"); 1826 break; 1827 case PCI_CAP_PCIX: 1828 pcix_off = off; 1829 printf("PCI-X"); 1830 break; 1831 case PCI_CAP_LDT: 1832 printf("LDT"); 1833 break; 1834 case PCI_CAP_VENDSPEC: 1835 vendspec_off = off; 1836 printf("Vendor-specific"); 1837 break; 1838 case PCI_CAP_DEBUGPORT: 1839 printf("Debug Port"); 1840 debugport_off = off; 1841 break; 1842 case PCI_CAP_CPCI_RSRCCTL: 1843 printf("CompactPCI Resource Control"); 1844 break; 1845 case PCI_CAP_HOTPLUG: 1846 printf("Hot-Plug"); 1847 break; 1848 case PCI_CAP_SUBVENDOR: 1849 printf("Subsystem ID"); 1850 subsystem_off = off; 1851 break; 1852 case PCI_CAP_AGP8: 1853 printf("AGP 8x"); 1854 break; 1855 case PCI_CAP_SECURE: 1856 printf("Secure Device"); 1857 break; 1858 case PCI_CAP_PCIEXPRESS: 1859 printf("PCI Express"); 1860 pcie_off = off; 1861 break; 1862 case PCI_CAP_MSIX: 1863 printf("MSI-X"); 1864 msix_off = off; 1865 break; 1866 case PCI_CAP_SATA: 1867 printf("SATA"); 1868 break; 1869 case PCI_CAP_PCIAF: 1870 printf("Advanced Features"); 1871 pciaf_off = off; 1872 break; 1873 default: 1874 printf("unknown"); 1875 } 1876 printf(")\n"); 1877 } 1878 if (pcipm_off != -1) 1879 pci_conf_print_pcipm_cap(regs, pcipm_off); 1880 /* XXX AGP */ 1881 /* XXX VPD */ 1882 /* XXX SLOTID */ 1883 if (msi_off != -1) 1884 pci_conf_print_msi_cap(regs, msi_off); 1885 /* XXX CPCI_HOTSWAP */ 1886 if (pcix_off != -1) 1887 pci_conf_print_pcix_cap(regs, pcix_off); 1888 /* XXX LDT */ 1889 if (vendspec_off != -1) 1890 pci_conf_print_vendspec_cap(regs, vendspec_off); 1891 if (debugport_off != -1) 1892 pci_conf_print_debugport_cap(regs, debugport_off); 1893 /* XXX CPCI_RSRCCTL */ 1894 /* XXX HOTPLUG */ 1895 if (subsystem_off != -1) 1896 pci_conf_print_subsystem_cap(regs, subsystem_off); 1897 /* XXX AGP8 */ 1898 /* XXX SECURE */ 1899 if (pcie_off != -1) 1900 pci_conf_print_pcie_cap(regs, pcie_off); 1901 if (msix_off != -1) 1902 pci_conf_print_msix_cap(regs, msix_off); 1903 /* XXX SATA */ 1904 if (pciaf_off != -1) 1905 pci_conf_print_pciaf_cap(regs, pciaf_off); 1906 } 1907 1908 /* Print the Secondary Status Register. */ 1909 static void 1910 pci_conf_print_ssr(pcireg_t rval) 1911 { 1912 pcireg_t devsel; 1913 1914 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 1915 onoff("66 MHz capable", rval, __BIT(5)); 1916 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 1917 onoff("Fast back-to-back capable", rval, __BIT(7)); 1918 onoff("Data parity error detected", rval, __BIT(8)); 1919 1920 printf(" DEVSEL timing: "); 1921 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 1922 switch (devsel) { 1923 case 0: 1924 printf("fast"); 1925 break; 1926 case 1: 1927 printf("medium"); 1928 break; 1929 case 2: 1930 printf("slow"); 1931 break; 1932 default: 1933 printf("unknown/reserved"); /* XXX */ 1934 break; 1935 } 1936 printf(" (0x%x)\n", devsel); 1937 1938 onoff("Signalled target abort", rval, __BIT(11)); 1939 onoff("Received target abort", rval, __BIT(12)); 1940 onoff("Received master abort", rval, __BIT(13)); 1941 onoff("Received system error", rval, __BIT(14)); 1942 onoff("Detected parity error", rval, __BIT(15)); 1943 } 1944 1945 static void 1946 pci_conf_print_type0( 1947 #ifdef _KERNEL 1948 pci_chipset_tag_t pc, pcitag_t tag, 1949 #endif 1950 const pcireg_t *regs 1951 #ifdef _KERNEL 1952 , int sizebars 1953 #endif 1954 ) 1955 { 1956 int off, width; 1957 pcireg_t rval; 1958 1959 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 1960 #ifdef _KERNEL 1961 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 1962 #else 1963 width = pci_conf_print_bar(regs, off, NULL); 1964 #endif 1965 } 1966 1967 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 1968 1969 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 1970 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1971 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1972 1973 /* XXX */ 1974 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 1975 1976 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1977 printf(" Capability list pointer: 0x%02x\n", 1978 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 1979 else 1980 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 1981 1982 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 1983 1984 rval = regs[o2i(PCI_INTERRUPT_REG)]; 1985 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 1986 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 1987 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 1988 switch (PCI_INTERRUPT_PIN(rval)) { 1989 case PCI_INTERRUPT_PIN_NONE: 1990 printf("(none)"); 1991 break; 1992 case PCI_INTERRUPT_PIN_A: 1993 printf("(pin A)"); 1994 break; 1995 case PCI_INTERRUPT_PIN_B: 1996 printf("(pin B)"); 1997 break; 1998 case PCI_INTERRUPT_PIN_C: 1999 printf("(pin C)"); 2000 break; 2001 case PCI_INTERRUPT_PIN_D: 2002 printf("(pin D)"); 2003 break; 2004 default: 2005 printf("(? ? ?)"); 2006 break; 2007 } 2008 printf("\n"); 2009 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 2010 } 2011 2012 static void 2013 pci_conf_print_type1( 2014 #ifdef _KERNEL 2015 pci_chipset_tag_t pc, pcitag_t tag, 2016 #endif 2017 const pcireg_t *regs 2018 #ifdef _KERNEL 2019 , int sizebars 2020 #endif 2021 ) 2022 { 2023 int off, width; 2024 pcireg_t rval; 2025 uint32_t base, limit; 2026 uint32_t base_h, limit_h; 2027 uint64_t pbase, plimit; 2028 int use_upper; 2029 2030 /* 2031 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 2032 * Bridge chip documentation, and may not be correct with 2033 * respect to various standards. (XXX) 2034 */ 2035 2036 for (off = 0x10; off < 0x18; off += width) { 2037 #ifdef _KERNEL 2038 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 2039 #else 2040 width = pci_conf_print_bar(regs, off, NULL); 2041 #endif 2042 } 2043 2044 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 2045 printf(" Primary bus number: 0x%02x\n", 2046 PCI_BRIDGE_BUS_PRIMARY(rval)); 2047 printf(" Secondary bus number: 0x%02x\n", 2048 PCI_BRIDGE_BUS_SECONDARY(rval)); 2049 printf(" Subordinate bus number: 0x%02x\n", 2050 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 2051 printf(" Secondary bus latency timer: 0x%02x\n", 2052 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 2053 2054 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 2055 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 2056 2057 /* I/O region */ 2058 printf(" I/O region:\n"); 2059 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 2060 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 2061 if (PCI_BRIDGE_IO_32BITS(rval)) 2062 use_upper = 1; 2063 else 2064 use_upper = 0; 2065 onoff("32bit I/O", rval, use_upper); 2066 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 2067 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 2068 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 2069 limit |= 0x00000fff; 2070 2071 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 2072 base_h = (rval >> 0) & 0xffff; 2073 limit_h = (rval >> 16) & 0xffff; 2074 printf(" base upper 16 bits register: 0x%04x\n", base_h); 2075 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 2076 2077 if (use_upper == 1) { 2078 base |= base_h << 16; 2079 limit |= limit_h << 16; 2080 } 2081 if (base < limit) { 2082 if (use_upper == 1) 2083 printf(" range: 0x%08x-0x%08x\n", base, limit); 2084 else 2085 printf(" range: 0x%04x-0x%04x\n", base, limit); 2086 } else 2087 printf(" range: not set\n"); 2088 2089 /* Non-prefetchable memory region */ 2090 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 2091 printf(" Memory region:\n"); 2092 printf(" base register: 0x%04x\n", 2093 (rval >> 0) & 0xffff); 2094 printf(" limit register: 0x%04x\n", 2095 (rval >> 16) & 0xffff); 2096 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 2097 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 2098 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 2099 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 2100 if (base < limit) 2101 printf(" range: 0x%08x-0x%08x\n", base, limit); 2102 else 2103 printf(" range: not set\n"); 2104 2105 /* Prefetchable memory region */ 2106 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 2107 printf(" Prefetchable memory region:\n"); 2108 printf(" base register: 0x%04x\n", 2109 (rval >> 0) & 0xffff); 2110 printf(" limit register: 0x%04x\n", 2111 (rval >> 16) & 0xffff); 2112 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 2113 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 2114 printf(" base upper 32 bits register: 0x%08x\n", 2115 base_h); 2116 printf(" limit upper 32 bits register: 0x%08x\n", 2117 limit_h); 2118 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 2119 use_upper = 1; 2120 else 2121 use_upper = 0; 2122 onoff("64bit memory address", rval, use_upper); 2123 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 2124 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 2125 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 2126 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 2127 if (use_upper == 1) { 2128 pbase |= (uint64_t)base_h << 32; 2129 plimit |= (uint64_t)limit_h << 32; 2130 } 2131 if (pbase < plimit) { 2132 if (use_upper == 1) 2133 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 2134 "\n", pbase, plimit); 2135 else 2136 printf(" range: 0x%08x-0x%08x\n", 2137 (uint32_t)pbase, (uint32_t)plimit); 2138 } else 2139 printf(" range: not set\n"); 2140 2141 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2142 printf(" Capability list pointer: 0x%02x\n", 2143 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 2144 else 2145 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 2146 2147 /* XXX */ 2148 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 2149 2150 rval = regs[o2i(PCI_INTERRUPT_REG)]; 2151 printf(" Interrupt line: 0x%02x\n", 2152 (rval >> 0) & 0xff); 2153 printf(" Interrupt pin: 0x%02x ", 2154 (rval >> 8) & 0xff); 2155 switch ((rval >> 8) & 0xff) { 2156 case PCI_INTERRUPT_PIN_NONE: 2157 printf("(none)"); 2158 break; 2159 case PCI_INTERRUPT_PIN_A: 2160 printf("(pin A)"); 2161 break; 2162 case PCI_INTERRUPT_PIN_B: 2163 printf("(pin B)"); 2164 break; 2165 case PCI_INTERRUPT_PIN_C: 2166 printf("(pin C)"); 2167 break; 2168 case PCI_INTERRUPT_PIN_D: 2169 printf("(pin D)"); 2170 break; 2171 default: 2172 printf("(? ? ?)"); 2173 break; 2174 } 2175 printf("\n"); 2176 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 2177 & PCI_BRIDGE_CONTROL_MASK; 2178 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 2179 onoff("Parity error response", rval, 0x0001); 2180 onoff("Secondary SERR forwarding", rval, 0x0002); 2181 onoff("ISA enable", rval, 0x0004); 2182 onoff("VGA enable", rval, 0x0008); 2183 onoff("Master abort reporting", rval, 0x0020); 2184 onoff("Secondary bus reset", rval, 0x0040); 2185 onoff("Fast back-to-back capable", rval, 0x0080); 2186 } 2187 2188 static void 2189 pci_conf_print_type2( 2190 #ifdef _KERNEL 2191 pci_chipset_tag_t pc, pcitag_t tag, 2192 #endif 2193 const pcireg_t *regs 2194 #ifdef _KERNEL 2195 , int sizebars 2196 #endif 2197 ) 2198 { 2199 pcireg_t rval; 2200 2201 /* 2202 * XXX these need to be printed in more detail, need to be 2203 * XXX checked against specs/docs, etc. 2204 * 2205 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 2206 * controller chip documentation, and may not be correct with 2207 * respect to various standards. (XXX) 2208 */ 2209 2210 #ifdef _KERNEL 2211 pci_conf_print_bar(pc, tag, regs, 0x10, 2212 "CardBus socket/ExCA registers", sizebars); 2213 #else 2214 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 2215 #endif 2216 2217 /* Capability list pointer and secondary status register */ 2218 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 2219 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2220 printf(" Capability list pointer: 0x%02x\n", 2221 PCI_CAPLIST_PTR(rval)); 2222 else 2223 printf(" Reserved @ 0x14: 0x%04" PRIxMAX "\n", 2224 __SHIFTOUT(rval, __BITS(15, 0))); 2225 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 2226 2227 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 2228 printf(" PCI bus number: 0x%02x\n", 2229 (rval >> 0) & 0xff); 2230 printf(" CardBus bus number: 0x%02x\n", 2231 (rval >> 8) & 0xff); 2232 printf(" Subordinate bus number: 0x%02x\n", 2233 (rval >> 16) & 0xff); 2234 printf(" CardBus latency timer: 0x%02x\n", 2235 (rval >> 24) & 0xff); 2236 2237 /* XXX Print more prettily */ 2238 printf(" CardBus memory region 0:\n"); 2239 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 2240 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 2241 printf(" CardBus memory region 1:\n"); 2242 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 2243 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 2244 printf(" CardBus I/O region 0:\n"); 2245 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 2246 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 2247 printf(" CardBus I/O region 1:\n"); 2248 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 2249 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 2250 2251 rval = regs[o2i(PCI_INTERRUPT_REG)]; 2252 printf(" Interrupt line: 0x%02x\n", 2253 (rval >> 0) & 0xff); 2254 printf(" Interrupt pin: 0x%02x ", 2255 (rval >> 8) & 0xff); 2256 switch ((rval >> 8) & 0xff) { 2257 case PCI_INTERRUPT_PIN_NONE: 2258 printf("(none)"); 2259 break; 2260 case PCI_INTERRUPT_PIN_A: 2261 printf("(pin A)"); 2262 break; 2263 case PCI_INTERRUPT_PIN_B: 2264 printf("(pin B)"); 2265 break; 2266 case PCI_INTERRUPT_PIN_C: 2267 printf("(pin C)"); 2268 break; 2269 case PCI_INTERRUPT_PIN_D: 2270 printf("(pin D)"); 2271 break; 2272 default: 2273 printf("(? ? ?)"); 2274 break; 2275 } 2276 printf("\n"); 2277 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 2278 printf(" Bridge control register: 0x%04x\n", rval); 2279 onoff("Parity error response", rval, __BIT(0)); 2280 onoff("SERR# enable", rval, __BIT(1)); 2281 onoff("ISA enable", rval, __BIT(2)); 2282 onoff("VGA enable", rval, __BIT(3)); 2283 onoff("Master abort mode", rval, __BIT(5)); 2284 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 2285 onoff("Functional interrupts routed by ExCA registers", rval, 2286 __BIT(7)); 2287 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 2288 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 2289 onoff("Write posting enable", rval, __BIT(10)); 2290 2291 rval = regs[o2i(0x40)]; 2292 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 2293 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 2294 2295 #ifdef _KERNEL 2296 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 2297 sizebars); 2298 #else 2299 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 2300 #endif 2301 } 2302 2303 void 2304 pci_conf_print( 2305 #ifdef _KERNEL 2306 pci_chipset_tag_t pc, pcitag_t tag, 2307 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 2308 #else 2309 int pcifd, u_int bus, u_int dev, u_int func 2310 #endif 2311 ) 2312 { 2313 pcireg_t regs[o2i(256)]; 2314 int off, capoff, endoff, hdrtype; 2315 const char *type_name; 2316 #ifdef _KERNEL 2317 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, 2318 int); 2319 int sizebars; 2320 #else 2321 void (*type_printfn)(const pcireg_t *); 2322 #endif 2323 2324 printf("PCI configuration registers:\n"); 2325 2326 for (off = 0; off < 256; off += 4) { 2327 #ifdef _KERNEL 2328 regs[o2i(off)] = pci_conf_read(pc, tag, off); 2329 #else 2330 if (pcibus_conf_read(pcifd, bus, dev, func, off, 2331 ®s[o2i(off)]) == -1) 2332 regs[o2i(off)] = 0; 2333 #endif 2334 } 2335 2336 #ifdef _KERNEL 2337 sizebars = 1; 2338 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 2339 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 2340 sizebars = 0; 2341 #endif 2342 2343 /* common header */ 2344 printf(" Common header:\n"); 2345 pci_conf_print_regs(regs, 0, 16); 2346 2347 printf("\n"); 2348 #ifdef _KERNEL 2349 pci_conf_print_common(pc, tag, regs); 2350 #else 2351 pci_conf_print_common(regs); 2352 #endif 2353 printf("\n"); 2354 2355 /* type-dependent header */ 2356 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 2357 switch (hdrtype) { /* XXX make a table, eventually */ 2358 case 0: 2359 /* Standard device header */ 2360 type_name = "\"normal\" device"; 2361 type_printfn = &pci_conf_print_type0; 2362 capoff = PCI_CAPLISTPTR_REG; 2363 endoff = 64; 2364 break; 2365 case 1: 2366 /* PCI-PCI bridge header */ 2367 type_name = "PCI-PCI bridge"; 2368 type_printfn = &pci_conf_print_type1; 2369 capoff = PCI_CAPLISTPTR_REG; 2370 endoff = 64; 2371 break; 2372 case 2: 2373 /* PCI-CardBus bridge header */ 2374 type_name = "PCI-CardBus bridge"; 2375 type_printfn = &pci_conf_print_type2; 2376 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 2377 endoff = 72; 2378 break; 2379 default: 2380 type_name = NULL; 2381 type_printfn = 0; 2382 capoff = -1; 2383 endoff = 64; 2384 break; 2385 } 2386 printf(" Type %d ", hdrtype); 2387 if (type_name != NULL) 2388 printf("(%s) ", type_name); 2389 printf("header:\n"); 2390 pci_conf_print_regs(regs, 16, endoff); 2391 printf("\n"); 2392 if (type_printfn) { 2393 #ifdef _KERNEL 2394 (*type_printfn)(pc, tag, regs, sizebars); 2395 #else 2396 (*type_printfn)(regs); 2397 #endif 2398 } else 2399 printf(" Don't know how to pretty-print type %d header.\n", 2400 hdrtype); 2401 printf("\n"); 2402 2403 /* capability list, if present */ 2404 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2405 && (capoff > 0)) { 2406 #ifdef _KERNEL 2407 pci_conf_print_caplist(pc, tag, regs, capoff); 2408 #else 2409 pci_conf_print_caplist(regs, capoff); 2410 #endif 2411 printf("\n"); 2412 } 2413 2414 /* device-dependent header */ 2415 printf(" Device-dependent header:\n"); 2416 pci_conf_print_regs(regs, endoff, 256); 2417 printf("\n"); 2418 #ifdef _KERNEL 2419 if (printfn) 2420 (*printfn)(pc, tag, regs); 2421 else 2422 printf(" Don't know how to pretty-print device-dependent header.\n"); 2423 printf("\n"); 2424 #endif /* _KERNEL */ 2425 } 2426
Indexes created Wed Sep 24 22:09:59 GMT 2025