pci_subr.c revision 1.129
1 /* $NetBSD: pci_subr.c,v 1.129 2014/10/06 08:00:57 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.129 2014/10/06 08:00:57 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdbool.h> 58 #include <stdio.h> 59 #include <string.h> 60 #endif 61 62 #include <dev/pci/pcireg.h> 63 #ifdef _KERNEL 64 #include <dev/pci/pcivar.h> 65 #else 66 #include <dev/pci/pci_verbose.h> 67 #include <dev/pci/pcidevs.h> 68 #include <dev/pci/pcidevs_data.h> 69 #endif 70 71 /* 72 * Descriptions of known PCI classes and subclasses. 73 * 74 * Subclasses are described in the same way as classes, but have a 75 * NULL subclass pointer. 76 */ 77 struct pci_class { 78 const char *name; 79 u_int val; /* as wide as pci_{,sub}class_t */ 80 const struct pci_class *subclasses; 81 }; 82 83 /* 84 * Class 0x00. 85 * Before rev. 2.0. 86 */ 87 static const struct pci_class pci_subclass_prehistoric[] = { 88 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 89 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 90 { NULL, 0, NULL, }, 91 }; 92 93 /* 94 * Class 0x01. 95 * Mass strage controller 96 */ 97 98 /* ATA programming interface */ 99 static const struct pci_class pci_interface_ata[] = { 100 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 101 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 102 { NULL, 0, NULL, }, 103 }; 104 105 /* SATA programming interface */ 106 static const struct pci_class pci_interface_sata[] = { 107 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 108 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 109 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 110 { NULL, 0, NULL, }, 111 }; 112 113 /* Flash programming interface */ 114 static const struct pci_class pci_interface_nvm[] = { 115 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 116 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 117 { NULL, 0, NULL, }, 118 }; 119 120 /* Subclasses */ 121 static const struct pci_class pci_subclass_mass_storage[] = { 122 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 123 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 124 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 125 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 126 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 127 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 128 pci_interface_ata, }, 129 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 130 pci_interface_sata, }, 131 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 132 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 133 pci_interface_nvm, }, 134 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 135 { NULL, 0, NULL, }, 136 }; 137 138 /* 139 * Class 0x02. 140 * Network controller. 141 */ 142 static const struct pci_class pci_subclass_network[] = { 143 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 144 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 145 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 146 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 147 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 148 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 149 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 150 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 151 { NULL, 0, NULL, }, 152 }; 153 154 /* 155 * Class 0x03. 156 * Display controller. 157 */ 158 159 /* VGA programming interface */ 160 static const struct pci_class pci_interface_vga[] = { 161 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 162 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 163 { NULL, 0, NULL, }, 164 }; 165 /* Subclasses */ 166 static const struct pci_class pci_subclass_display[] = { 167 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 168 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 169 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 170 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 171 { NULL, 0, NULL, }, 172 }; 173 174 /* 175 * Class 0x04. 176 * Multimedia device. 177 */ 178 static const struct pci_class pci_subclass_multimedia[] = { 179 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 180 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 181 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 182 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 183 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 184 { NULL, 0, NULL, }, 185 }; 186 187 /* 188 * Class 0x05. 189 * Memory controller. 190 */ 191 static const struct pci_class pci_subclass_memory[] = { 192 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 193 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 194 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 195 { NULL, 0, NULL, }, 196 }; 197 198 /* 199 * Class 0x06. 200 * Bridge device. 201 */ 202 203 /* PCI bridge programming interface */ 204 static const struct pci_class pci_interface_pcibridge[] = { 205 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 206 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 207 { NULL, 0, NULL, }, 208 }; 209 210 /* Semi-transparent PCI-to-PCI bridge programming interface */ 211 static const struct pci_class pci_interface_stpci[] = { 212 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 213 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 214 { NULL, 0, NULL, }, 215 }; 216 217 /* Advanced Switching programming interface */ 218 static const struct pci_class pci_interface_advsw[] = { 219 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 220 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 221 { NULL, 0, NULL, }, 222 }; 223 224 /* Subclasses */ 225 static const struct pci_class pci_subclass_bridge[] = { 226 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 227 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 228 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 229 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 230 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 231 pci_interface_pcibridge, }, 232 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 233 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 234 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 235 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 236 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 237 pci_interface_stpci, }, 238 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 239 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 240 pci_interface_advsw, }, 241 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 242 { NULL, 0, NULL, }, 243 }; 244 245 /* 246 * Class 0x07. 247 * Simple communications controller. 248 */ 249 250 /* Serial controller programming interface */ 251 static const struct pci_class pci_interface_serial[] = { 252 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 253 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 254 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 255 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 256 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 257 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 258 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 259 { NULL, 0, NULL, }, 260 }; 261 262 /* Parallel controller programming interface */ 263 static const struct pci_class pci_interface_parallel[] = { 264 { "", PCI_INTERFACE_PARALLEL, NULL,}, 265 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 266 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 267 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 268 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 269 { NULL, 0, NULL,}, 270 }; 271 272 /* Modem programming interface */ 273 static const struct pci_class pci_interface_modem[] = { 274 { "", PCI_INTERFACE_MODEM, NULL,}, 275 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 276 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 277 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 278 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 279 { NULL, 0, NULL,}, 280 }; 281 282 /* Subclasses */ 283 static const struct pci_class pci_subclass_communications[] = { 284 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 285 pci_interface_serial, }, 286 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 287 pci_interface_parallel, }, 288 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 289 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 290 pci_interface_modem, }, 291 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 292 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 293 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 294 { NULL, 0, NULL,}, 295 }; 296 297 /* 298 * Class 0x08. 299 * Base system peripheral. 300 */ 301 302 /* PIC programming interface */ 303 static const struct pci_class pci_interface_pic[] = { 304 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 305 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 306 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 307 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 308 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 309 { NULL, 0, NULL, }, 310 }; 311 312 /* DMA programming interface */ 313 static const struct pci_class pci_interface_dma[] = { 314 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 315 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 316 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 317 { NULL, 0, NULL, }, 318 }; 319 320 /* Timer programming interface */ 321 static const struct pci_class pci_interface_tmr[] = { 322 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 323 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 324 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 325 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 326 { NULL, 0, NULL, }, 327 }; 328 329 /* RTC programming interface */ 330 static const struct pci_class pci_interface_rtc[] = { 331 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 332 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 333 { NULL, 0, NULL, }, 334 }; 335 336 /* Subclasses */ 337 static const struct pci_class pci_subclass_system[] = { 338 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 339 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 340 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 341 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 342 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 343 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 344 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 345 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 346 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 347 { NULL, 0, NULL, }, 348 }; 349 350 /* 351 * Class 0x09. 352 * Input device. 353 */ 354 355 /* Gameport programming interface */ 356 static const struct pci_class pci_interface_game[] = { 357 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 358 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 359 { NULL, 0, NULL, }, 360 }; 361 362 /* Subclasses */ 363 static const struct pci_class pci_subclass_input[] = { 364 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 365 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 366 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 367 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 368 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 369 pci_interface_game, }, 370 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 371 { NULL, 0, NULL, }, 372 }; 373 374 /* 375 * Class 0x0a. 376 * Docking station. 377 */ 378 static const struct pci_class pci_subclass_dock[] = { 379 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 380 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 381 { NULL, 0, NULL, }, 382 }; 383 384 /* 385 * Class 0x0b. 386 * Processor. 387 */ 388 static const struct pci_class pci_subclass_processor[] = { 389 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 390 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 391 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 392 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 393 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 394 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 395 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 396 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 397 { NULL, 0, NULL, }, 398 }; 399 400 /* 401 * Class 0x0c. 402 * Serial bus controller. 403 */ 404 405 /* IEEE1394 programming interface */ 406 static const struct pci_class pci_interface_ieee1394[] = { 407 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 408 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 409 { NULL, 0, NULL,}, 410 }; 411 412 /* USB programming interface */ 413 static const struct pci_class pci_interface_usb[] = { 414 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 415 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 416 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 417 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 418 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 419 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 420 { NULL, 0, NULL, }, 421 }; 422 423 /* IPMI programming interface */ 424 static const struct pci_class pci_interface_ipmi[] = { 425 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 426 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 427 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 428 { NULL, 0, NULL,}, 429 }; 430 431 /* Subclasses */ 432 static const struct pci_class pci_subclass_serialbus[] = { 433 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 434 pci_interface_ieee1394, }, 435 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 436 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 437 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 438 pci_interface_usb, }, 439 /* XXX Fiber Channel/_FIBRECHANNEL */ 440 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 441 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 442 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 443 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 444 pci_interface_ipmi, }, 445 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 446 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 447 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 448 { NULL, 0, NULL, }, 449 }; 450 451 /* 452 * Class 0x0d. 453 * Wireless Controller. 454 */ 455 static const struct pci_class pci_subclass_wireless[] = { 456 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 457 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 458 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 459 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 460 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 461 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 462 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 463 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 464 { NULL, 0, NULL, }, 465 }; 466 467 /* 468 * Class 0x0e. 469 * Intelligent IO controller. 470 */ 471 472 /* Intelligent IO programming interface */ 473 static const struct pci_class pci_interface_i2o[] = { 474 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 475 { NULL, 0, NULL,}, 476 }; 477 478 /* Subclasses */ 479 static const struct pci_class pci_subclass_i2o[] = { 480 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 481 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 482 { NULL, 0, NULL, }, 483 }; 484 485 /* 486 * Class 0x0f. 487 * Satellite communication controller. 488 */ 489 static const struct pci_class pci_subclass_satcom[] = { 490 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 491 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 492 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 493 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 494 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 495 { NULL, 0, NULL, }, 496 }; 497 498 /* 499 * Class 0x10. 500 * Encryption/Decryption controller. 501 */ 502 static const struct pci_class pci_subclass_crypto[] = { 503 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 504 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 505 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 506 { NULL, 0, NULL, }, 507 }; 508 509 /* 510 * Class 0x11. 511 * Data aquuisition and signal processing controller. 512 */ 513 static const struct pci_class pci_subclass_dasp[] = { 514 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 515 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 516 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 517 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 518 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 519 { NULL, 0, NULL, }, 520 }; 521 522 /* List of classes */ 523 static const struct pci_class pci_class[] = { 524 { "prehistoric", PCI_CLASS_PREHISTORIC, 525 pci_subclass_prehistoric, }, 526 { "mass storage", PCI_CLASS_MASS_STORAGE, 527 pci_subclass_mass_storage, }, 528 { "network", PCI_CLASS_NETWORK, 529 pci_subclass_network, }, 530 { "display", PCI_CLASS_DISPLAY, 531 pci_subclass_display, }, 532 { "multimedia", PCI_CLASS_MULTIMEDIA, 533 pci_subclass_multimedia, }, 534 { "memory", PCI_CLASS_MEMORY, 535 pci_subclass_memory, }, 536 { "bridge", PCI_CLASS_BRIDGE, 537 pci_subclass_bridge, }, 538 { "communications", PCI_CLASS_COMMUNICATIONS, 539 pci_subclass_communications, }, 540 { "system", PCI_CLASS_SYSTEM, 541 pci_subclass_system, }, 542 { "input", PCI_CLASS_INPUT, 543 pci_subclass_input, }, 544 { "dock", PCI_CLASS_DOCK, 545 pci_subclass_dock, }, 546 { "processor", PCI_CLASS_PROCESSOR, 547 pci_subclass_processor, }, 548 { "serial bus", PCI_CLASS_SERIALBUS, 549 pci_subclass_serialbus, }, 550 { "wireless", PCI_CLASS_WIRELESS, 551 pci_subclass_wireless, }, 552 { "I2O", PCI_CLASS_I2O, 553 pci_subclass_i2o, }, 554 { "satellite comm", PCI_CLASS_SATCOM, 555 pci_subclass_satcom, }, 556 { "crypto", PCI_CLASS_CRYPTO, 557 pci_subclass_crypto, }, 558 { "DASP", PCI_CLASS_DASP, 559 pci_subclass_dasp, }, 560 { "undefined", PCI_CLASS_UNDEFINED, 561 NULL, }, 562 { NULL, 0, 563 NULL, }, 564 }; 565 566 DEV_VERBOSE_DEFINE(pci); 567 568 void 569 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 570 size_t l) 571 { 572 pci_class_t pciclass; 573 pci_subclass_t subclass; 574 pci_interface_t interface; 575 pci_revision_t revision; 576 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 577 const struct pci_class *classp, *subclassp, *interfacep; 578 char *ep; 579 580 ep = cp + l; 581 582 pciclass = PCI_CLASS(class_reg); 583 subclass = PCI_SUBCLASS(class_reg); 584 interface = PCI_INTERFACE(class_reg); 585 revision = PCI_REVISION(class_reg); 586 587 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 588 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 589 PCI_PRODUCT(id_reg)); 590 591 classp = pci_class; 592 while (classp->name != NULL) { 593 if (pciclass == classp->val) 594 break; 595 classp++; 596 } 597 598 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 599 while (subclassp && subclassp->name != NULL) { 600 if (subclass == subclassp->val) 601 break; 602 subclassp++; 603 } 604 605 interfacep = (subclassp && subclassp->name != NULL) ? 606 subclassp->subclasses : NULL; 607 while (interfacep && interfacep->name != NULL) { 608 if (interface == interfacep->val) 609 break; 610 interfacep++; 611 } 612 613 cp += snprintf(cp, ep - cp, "%s %s", vendor, product); 614 if (showclass) { 615 cp += snprintf(cp, ep - cp, " ("); 616 if (classp->name == NULL) 617 cp += snprintf(cp, ep - cp, 618 "class 0x%02x, subclass 0x%02x", pciclass, subclass); 619 else { 620 if (subclassp == NULL || subclassp->name == NULL) 621 cp += snprintf(cp, ep - cp, 622 "%s, subclass 0x%02x", 623 classp->name, subclass); 624 else 625 cp += snprintf(cp, ep - cp, "%s %s", 626 subclassp->name, classp->name); 627 } 628 if ((interfacep == NULL) || (interfacep->name == NULL)) { 629 if (interface != 0) 630 cp += snprintf(cp, ep - cp, 631 ", interface 0x%02x", interface); 632 } else if (strncmp(interfacep->name, "", 1) != 0) 633 cp += snprintf(cp, ep - cp, ", %s", 634 interfacep->name); 635 if (revision != 0) 636 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 637 revision); 638 cp += snprintf(cp, ep - cp, ")"); 639 } 640 } 641 642 #ifdef _KERNEL 643 void 644 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 645 const char *known, int addrev) 646 { 647 char devinfo[256]; 648 649 if (known) { 650 aprint_normal(": %s", known); 651 if (addrev) 652 aprint_normal(" (rev. 0x%02x)", 653 PCI_REVISION(pa->pa_class)); 654 aprint_normal("\n"); 655 } else { 656 pci_devinfo(pa->pa_id, pa->pa_class, 0, 657 devinfo, sizeof(devinfo)); 658 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 659 PCI_REVISION(pa->pa_class)); 660 } 661 if (naive) 662 aprint_naive(": %s\n", naive); 663 else 664 aprint_naive("\n"); 665 } 666 #endif 667 668 /* 669 * Print out most of the PCI configuration registers. Typically used 670 * in a device attach routine like this: 671 * 672 * #ifdef MYDEV_DEBUG 673 * printf("%s: ", device_xname(sc->sc_dev)); 674 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 675 * #endif 676 */ 677 678 #define i2o(i) ((i) * 4) 679 #define o2i(o) ((o) / 4) 680 #define onoff2(str, rval, bit, onstr, offstr) \ 681 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 682 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 683 684 static void 685 pci_conf_print_common( 686 #ifdef _KERNEL 687 pci_chipset_tag_t pc, pcitag_t tag, 688 #endif 689 const pcireg_t *regs) 690 { 691 const char *name; 692 const struct pci_class *classp, *subclassp; 693 char vendor[PCI_VENDORSTR_LEN]; 694 char product[PCI_PRODUCTSTR_LEN]; 695 pcireg_t rval; 696 unsigned int num; 697 698 rval = regs[o2i(PCI_ID_REG)]; 699 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 700 if (name) 701 printf(" Vendor Name: %s (0x%04x)\n", name, 702 PCI_VENDOR(rval)); 703 else 704 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 705 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 706 PCI_PRODUCT(rval)); 707 if (name) 708 printf(" Device Name: %s (0x%04x)\n", name, 709 PCI_PRODUCT(rval)); 710 else 711 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 712 713 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 714 715 printf(" Command register: 0x%04x\n", rval & 0xffff); 716 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 717 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 718 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 719 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 720 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 721 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 722 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 723 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 724 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 725 onoff("Fast back-to-back transactions", rval, 726 PCI_COMMAND_BACKTOBACK_ENABLE); 727 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 728 729 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 730 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 731 "inactive"); 732 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 733 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 734 onoff("User Definable Features (UDF) support", rval, 735 PCI_STATUS_UDF_SUPPORT); 736 onoff("Fast back-to-back capable", rval, 737 PCI_STATUS_BACKTOBACK_SUPPORT); 738 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 739 740 printf(" DEVSEL timing: "); 741 switch (rval & PCI_STATUS_DEVSEL_MASK) { 742 case PCI_STATUS_DEVSEL_FAST: 743 printf("fast"); 744 break; 745 case PCI_STATUS_DEVSEL_MEDIUM: 746 printf("medium"); 747 break; 748 case PCI_STATUS_DEVSEL_SLOW: 749 printf("slow"); 750 break; 751 default: 752 printf("unknown/reserved"); /* XXX */ 753 break; 754 } 755 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 756 757 onoff("Slave signaled Target Abort", rval, 758 PCI_STATUS_TARGET_TARGET_ABORT); 759 onoff("Master received Target Abort", rval, 760 PCI_STATUS_MASTER_TARGET_ABORT); 761 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 762 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 763 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 764 765 rval = regs[o2i(PCI_CLASS_REG)]; 766 for (classp = pci_class; classp->name != NULL; classp++) { 767 if (PCI_CLASS(rval) == classp->val) 768 break; 769 } 770 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 771 while (subclassp && subclassp->name != NULL) { 772 if (PCI_SUBCLASS(rval) == subclassp->val) 773 break; 774 subclassp++; 775 } 776 if (classp->name != NULL) { 777 printf(" Class Name: %s (0x%02x)\n", classp->name, 778 PCI_CLASS(rval)); 779 if (subclassp != NULL && subclassp->name != NULL) 780 printf(" Subclass Name: %s (0x%02x)\n", 781 subclassp->name, PCI_SUBCLASS(rval)); 782 else 783 printf(" Subclass ID: 0x%02x\n", 784 PCI_SUBCLASS(rval)); 785 } else { 786 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 787 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 788 } 789 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 790 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 791 792 rval = regs[o2i(PCI_BHLC_REG)]; 793 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 794 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 795 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 796 PCI_HDRTYPE(rval)); 797 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 798 num = PCI_CACHELINE(rval); 799 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 800 } 801 802 static int 803 pci_conf_print_bar( 804 #ifdef _KERNEL 805 pci_chipset_tag_t pc, pcitag_t tag, 806 #endif 807 const pcireg_t *regs, int reg, const char *name 808 #ifdef _KERNEL 809 , int sizebar 810 #endif 811 ) 812 { 813 int width; 814 pcireg_t rval, rval64h; 815 #ifdef _KERNEL 816 int s; 817 pcireg_t mask, mask64h; 818 #endif 819 820 width = 4; 821 822 /* 823 * Section 6.2.5.1, `Address Maps', tells us that: 824 * 825 * 1) The builtin software should have already mapped the 826 * device in a reasonable way. 827 * 828 * 2) A device which wants 2^n bytes of memory will hardwire 829 * the bottom n bits of the address to 0. As recommended, 830 * we write all 1s and see what we get back. 831 */ 832 833 rval = regs[o2i(reg)]; 834 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 835 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 836 rval64h = regs[o2i(reg + 4)]; 837 width = 8; 838 } else 839 rval64h = 0; 840 841 #ifdef _KERNEL 842 /* XXX don't size unknown memory type? */ 843 if (rval != 0 && sizebar) { 844 /* 845 * The following sequence seems to make some devices 846 * (e.g. host bus bridges, which don't normally 847 * have their space mapped) very unhappy, to 848 * the point of crashing the system. 849 * 850 * Therefore, if the mapping register is zero to 851 * start out with, don't bother trying. 852 */ 853 s = splhigh(); 854 pci_conf_write(pc, tag, reg, 0xffffffff); 855 mask = pci_conf_read(pc, tag, reg); 856 pci_conf_write(pc, tag, reg, rval); 857 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 858 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 859 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 860 mask64h = pci_conf_read(pc, tag, reg + 4); 861 pci_conf_write(pc, tag, reg + 4, rval64h); 862 } else 863 mask64h = 0; 864 splx(s); 865 } else 866 mask = mask64h = 0; 867 #endif /* _KERNEL */ 868 869 printf(" Base address register at 0x%02x", reg); 870 if (name) 871 printf(" (%s)", name); 872 printf("\n "); 873 if (rval == 0) { 874 printf("not implemented(?)\n"); 875 return width; 876 } 877 printf("type: "); 878 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 879 const char *type, *prefetch; 880 881 switch (PCI_MAPREG_MEM_TYPE(rval)) { 882 case PCI_MAPREG_MEM_TYPE_32BIT: 883 type = "32-bit"; 884 break; 885 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 886 type = "32-bit-1M"; 887 break; 888 case PCI_MAPREG_MEM_TYPE_64BIT: 889 type = "64-bit"; 890 break; 891 default: 892 type = "unknown (XXX)"; 893 break; 894 } 895 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 896 prefetch = ""; 897 else 898 prefetch = "non"; 899 printf("%s %sprefetchable memory\n", type, prefetch); 900 switch (PCI_MAPREG_MEM_TYPE(rval)) { 901 case PCI_MAPREG_MEM_TYPE_64BIT: 902 printf(" base: 0x%016llx, ", 903 PCI_MAPREG_MEM64_ADDR( 904 ((((long long) rval64h) << 32) | rval))); 905 #ifdef _KERNEL 906 if (sizebar) 907 printf("size: 0x%016llx", 908 PCI_MAPREG_MEM64_SIZE( 909 ((((long long) mask64h) << 32) | mask))); 910 else 911 #endif /* _KERNEL */ 912 printf("not sized"); 913 printf("\n"); 914 break; 915 case PCI_MAPREG_MEM_TYPE_32BIT: 916 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 917 default: 918 printf(" base: 0x%08x, ", 919 PCI_MAPREG_MEM_ADDR(rval)); 920 #ifdef _KERNEL 921 if (sizebar) 922 printf("size: 0x%08x", 923 PCI_MAPREG_MEM_SIZE(mask)); 924 else 925 #endif /* _KERNEL */ 926 printf("not sized"); 927 printf("\n"); 928 break; 929 } 930 } else { 931 #ifdef _KERNEL 932 if (sizebar) 933 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 934 #endif /* _KERNEL */ 935 printf("i/o\n"); 936 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 937 #ifdef _KERNEL 938 if (sizebar) 939 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 940 else 941 #endif /* _KERNEL */ 942 printf("not sized"); 943 printf("\n"); 944 } 945 946 return width; 947 } 948 949 static void 950 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 951 { 952 int off, needaddr, neednl; 953 954 needaddr = 1; 955 neednl = 0; 956 for (off = first; off < pastlast; off += 4) { 957 if ((off % 16) == 0 || needaddr) { 958 printf(" 0x%02x:", off); 959 needaddr = 0; 960 } 961 printf(" 0x%08x", regs[o2i(off)]); 962 neednl = 1; 963 if ((off % 16) == 12) { 964 printf("\n"); 965 neednl = 0; 966 } 967 } 968 if (neednl) 969 printf("\n"); 970 } 971 972 static const char * 973 pci_conf_print_pcipm_cap_aux(uint16_t caps) 974 { 975 976 switch ((caps >> 6) & 7) { 977 case 0: return "self-powered"; 978 case 1: return "55 mA"; 979 case 2: return "100 mA"; 980 case 3: return "160 mA"; 981 case 4: return "220 mA"; 982 case 5: return "270 mA"; 983 case 6: return "320 mA"; 984 case 7: 985 default: return "375 mA"; 986 } 987 } 988 989 static const char * 990 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 991 { 992 static const char unk[] = "unknown"; 993 static const char *pmrev[8] = { 994 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 995 }; 996 if (val > 7) 997 return unk; 998 return pmrev[val]; 999 } 1000 1001 static void 1002 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1003 { 1004 uint16_t caps, pmcsr; 1005 pcireg_t reg; 1006 1007 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1008 reg = regs[o2i(capoff + PCI_PMCSR)]; 1009 pmcsr = reg & 0xffff; 1010 1011 printf("\n PCI Power Management Capabilities Register\n"); 1012 1013 printf(" Capabilities register: 0x%04x\n", caps); 1014 printf(" Version: %s\n", 1015 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1016 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1017 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1018 printf(" 3.3V auxiliary current: %s\n", 1019 pci_conf_print_pcipm_cap_aux(caps)); 1020 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1021 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1022 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1023 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1024 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1025 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1026 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1027 1028 printf(" Control/status register: 0x%04x\n", pmcsr); 1029 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1030 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1031 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1032 printf(" PME# assertion: %sabled\n", 1033 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1034 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1035 printf(" Bridge Support Extensions register: 0x%02x\n", 1036 (reg >> 16) & 0xff); 1037 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1038 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1039 printf(" Data register: 0x%02x\n", (reg >> 24) & 0xff); 1040 1041 } 1042 1043 /* XXX pci_conf_print_vpd_cap */ 1044 /* XXX pci_conf_print_slotid_cap */ 1045 1046 static void 1047 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1048 { 1049 uint32_t ctl, mmc, mme; 1050 1051 regs += o2i(capoff); 1052 ctl = *regs++; 1053 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1054 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1055 1056 printf("\n PCI Message Signaled Interrupt\n"); 1057 1058 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1059 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1060 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1061 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1062 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1063 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1064 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1065 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1066 printf(" Message Address %sregister: 0x%08x\n", 1067 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1068 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1069 printf(" Message Address %sregister: 0x%08x\n", 1070 "(upper) ", *regs++); 1071 } 1072 printf(" Message Data register: 0x%08x\n", *regs++); 1073 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1074 printf(" Vector Mask register: 0x%08x\n", *regs++); 1075 printf(" Vector Pending register: 0x%08x\n", *regs++); 1076 } 1077 } 1078 1079 /* XXX pci_conf_print_cpci_hostwap_cap */ 1080 1081 /* 1082 * For both command register and status register. 1083 * The argument "idx" is index number (0 to 7). 1084 */ 1085 static int 1086 pcix_split_trans(unsigned int idx) 1087 { 1088 static int table[8] = { 1089 1, 2, 3, 4, 8, 12, 16, 32 1090 }; 1091 1092 if (idx >= __arraycount(table)) 1093 return -1; 1094 return table[idx]; 1095 } 1096 1097 static void 1098 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1099 { 1100 pcireg_t reg; 1101 int isbridge; 1102 int i; 1103 1104 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1105 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1106 printf("\n PCI-X %s Capabilities Register\n", 1107 isbridge ? "Bridge" : "Non-bridge"); 1108 1109 reg = regs[o2i(capoff)]; 1110 if (isbridge != 0) { 1111 printf(" Secondary status register: 0x%04x\n", 1112 (reg & 0xffff0000) >> 16); 1113 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1114 onoff("133MHz capable", reg, PCIX_STATUS_133); 1115 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1116 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1117 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1118 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1119 printf(" Secondary clock frequency: 0x%x\n", 1120 (reg & PCIX_BRIDGE_2NDST_CLKF) 1121 >> PCIX_BRIDGE_2NDST_CLKF_SHIFT); 1122 printf(" Version: 0x%x\n", 1123 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1124 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1125 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1126 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1127 } else { 1128 printf(" Command register: 0x%04x\n", 1129 (reg & 0xffff0000) >> 16); 1130 onoff("Data Parity Error Recovery", reg, 1131 PCIX_CMD_PERR_RECOVER); 1132 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1133 printf(" Maximum Burst Read Count: %u\n", 1134 PCIX_CMD_BYTECNT(reg)); 1135 printf(" Maximum Split Transactions: %d\n", 1136 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1137 >> PCIX_CMD_SPLTRANS_SHIFT)); 1138 } 1139 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1140 printf(" %sStatus register: 0x%08x\n", 1141 isbridge ? "Bridge " : "", reg); 1142 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1143 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1144 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1145 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1146 onoff("133MHz capable", reg, PCIX_STATUS_133); 1147 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1148 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1149 if (isbridge != 0) { 1150 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1151 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1152 } else { 1153 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1154 "bridge device", "simple device"); 1155 printf(" Designed max memory read byte count: %d\n", 1156 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1157 >> PCIX_STATUS_MAXB_SHIFT)); 1158 printf(" Designed max outstanding split transaction: %d\n", 1159 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1160 >> PCIX_STATUS_MAXST_SHIFT)); 1161 printf(" MAX cumulative Read Size: %u\n", 1162 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1163 onoff("Received split completion error", reg, 1164 PCIX_STATUS_SCERR); 1165 } 1166 onoff("266MHz capable", reg, PCIX_STATUS_266); 1167 onoff("533MHz capable", reg, PCIX_STATUS_533); 1168 1169 if (isbridge == 0) 1170 return; 1171 1172 /* Only for bridge */ 1173 for (i = 0; i < 2; i++) { 1174 reg = regs[o2i(capoff+PCIX_BRIDGE_UP_STCR + (4 * i))]; 1175 printf(" %s split transaction control register: 0x%08x\n", 1176 (i == 0) ? "Upstream" : "Downstream", reg); 1177 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1178 printf(" Commitment Limit: %d\n", 1179 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1180 } 1181 } 1182 1183 /* XXX pci_conf_print_ldt_cap */ 1184 1185 static void 1186 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1187 { 1188 uint16_t caps; 1189 1190 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1191 1192 printf("\n PCI Vendor Specific Capabilities Register\n"); 1193 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1194 } 1195 1196 static void 1197 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1198 { 1199 pcireg_t val; 1200 1201 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1202 1203 printf("\n Debugport Capability Register\n"); 1204 printf(" Debug base Register: 0x%04x\n", 1205 val >> PCI_DEBUG_BASER_SHIFT); 1206 printf(" port offset: 0x%04x\n", 1207 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1208 printf(" BAR number: %u\n", 1209 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1210 } 1211 1212 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1213 /* XXX pci_conf_print_hotplug_cap */ 1214 1215 static void 1216 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1217 { 1218 pcireg_t reg; 1219 1220 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1221 1222 printf("\n Subsystem ID Capability Register\n"); 1223 printf(" Subsystem ID : 0x%08x\n", reg); 1224 } 1225 1226 /* XXX pci_conf_print_agp8_cap */ 1227 /* XXX pci_conf_print_secure_cap */ 1228 1229 static void 1230 pci_print_pcie_L0s_latency(uint32_t val) 1231 { 1232 1233 switch (val) { 1234 case 0x0: 1235 printf("Less than 64ns\n"); 1236 break; 1237 case 0x1: 1238 case 0x2: 1239 case 0x3: 1240 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1241 break; 1242 case 0x4: 1243 printf("512ns to less than 1us\n"); 1244 break; 1245 case 0x5: 1246 printf("1us to less than 2us\n"); 1247 break; 1248 case 0x6: 1249 printf("2us - 4us\n"); 1250 break; 1251 case 0x7: 1252 printf("More than 4us\n"); 1253 break; 1254 } 1255 } 1256 1257 static void 1258 pci_print_pcie_L1_latency(uint32_t val) 1259 { 1260 1261 switch (val) { 1262 case 0x0: 1263 printf("Less than 1us\n"); 1264 break; 1265 case 0x6: 1266 printf("32us - 64us\n"); 1267 break; 1268 case 0x7: 1269 printf("More than 64us\n"); 1270 break; 1271 default: 1272 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1273 break; 1274 } 1275 } 1276 1277 static void 1278 pci_print_pcie_compl_timeout(uint32_t val) 1279 { 1280 1281 switch (val) { 1282 case 0x0: 1283 printf("50us to 50ms\n"); 1284 break; 1285 case 0x5: 1286 printf("16ms to 55ms\n"); 1287 break; 1288 case 0x6: 1289 printf("65ms to 210ms\n"); 1290 break; 1291 case 0x9: 1292 printf("260ms to 900ms\n"); 1293 break; 1294 case 0xa: 1295 printf("1s to 3.5s\n"); 1296 break; 1297 default: 1298 printf("unknown %u value\n", val); 1299 break; 1300 } 1301 } 1302 1303 static void 1304 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1305 { 1306 pcireg_t reg; /* for each register */ 1307 pcireg_t val; /* for each bitfield */ 1308 bool check_link = false; 1309 bool check_slot = false; 1310 bool check_rootport = false; 1311 unsigned int pciever; 1312 static const char * const linkspeeds[] = {"2.5", "5.0", "8.0"}; 1313 int i; 1314 1315 printf("\n PCI Express Capabilities Register\n"); 1316 /* Capability Register */ 1317 reg = regs[o2i(capoff)]; 1318 printf(" Capability register: %04x\n", reg >> 16); 1319 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1320 printf(" Capability version: %u\n", pciever); 1321 printf(" Device type: "); 1322 switch ((reg & 0x00f00000) >> 20) { 1323 case 0x0: 1324 printf("PCI Express Endpoint device\n"); 1325 check_link = true; 1326 break; 1327 case 0x1: 1328 printf("Legacy PCI Express Endpoint device\n"); 1329 check_link = true; 1330 break; 1331 case 0x4: 1332 printf("Root Port of PCI Express Root Complex\n"); 1333 check_link = true; 1334 check_slot = true; 1335 check_rootport = true; 1336 break; 1337 case 0x5: 1338 printf("Upstream Port of PCI Express Switch\n"); 1339 break; 1340 case 0x6: 1341 printf("Downstream Port of PCI Express Switch\n"); 1342 check_slot = true; 1343 check_rootport = true; 1344 break; 1345 case 0x7: 1346 printf("PCI Express to PCI/PCI-X Bridge\n"); 1347 break; 1348 case 0x8: 1349 printf("PCI/PCI-X to PCI Express Bridge\n"); 1350 break; 1351 case 0x9: 1352 printf("Root Complex Integrated Endpoint\n"); 1353 break; 1354 case 0xa: 1355 check_rootport = true; 1356 printf("Root Complex Event Collector\n"); 1357 break; 1358 default: 1359 printf("unknown\n"); 1360 break; 1361 } 1362 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1363 printf(" Interrupt Message Number: %x\n", 1364 (unsigned int)((reg & PCIE_XCAP_IRQ) >> 27)); 1365 1366 /* Device Capability Register */ 1367 reg = regs[o2i(capoff + PCIE_DCAP)]; 1368 printf(" Device Capabilities Register: 0x%08x\n", reg); 1369 printf(" Max Payload Size Supported: %u bytes max\n", 1370 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1371 printf(" Phantom Functions Supported: "); 1372 switch ((reg & PCIE_DCAP_PHANTOM_FUNCS) >> 3) { 1373 case 0x0: 1374 printf("not available\n"); 1375 break; 1376 case 0x1: 1377 printf("MSB\n"); 1378 break; 1379 case 0x2: 1380 printf("two MSB\n"); 1381 break; 1382 case 0x3: 1383 printf("All three bits\n"); 1384 break; 1385 } 1386 printf(" Extended Tag Field Supported: %dbit\n", 1387 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1388 printf(" Endpoint L0 Acceptable Latency: "); 1389 pci_print_pcie_L0s_latency((reg & PCIE_DCAP_L0S_LATENCY) >> 6); 1390 printf(" Endpoint L1 Acceptable Latency: "); 1391 pci_print_pcie_L1_latency((reg & PCIE_DCAP_L1_LATENCY) >> 9); 1392 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1393 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1394 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1395 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1396 printf(" Captured Slot Power Limit Value: %d\n", 1397 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18); 1398 printf(" Captured Slot Power Limit Scale: %d\n", 1399 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26); 1400 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1401 1402 /* Device Control Register */ 1403 reg = regs[o2i(capoff + PCIE_DCSR)]; 1404 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1405 onoff("Correctable Error Reporting Enable", reg, 1406 PCIE_DCSR_ENA_COR_ERR); 1407 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1408 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1409 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1410 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1411 printf(" Max Payload Size: %d byte\n", 1412 128 << (((unsigned int)(reg & PCIE_DCSR_MAX_PAYLOAD) >> 5))); 1413 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1414 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1415 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1416 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1417 printf(" Max Read Request Size: %d byte\n", 1418 128 << ((unsigned int)(reg & PCIE_DCSR_MAX_READ_REQ) >> 12)); 1419 1420 /* Device Status Register */ 1421 reg = regs[o2i(capoff + PCIE_DCSR)]; 1422 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1423 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1424 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1425 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1426 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1427 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1428 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1429 1430 if (check_link) { 1431 /* Link Capability Register */ 1432 reg = regs[o2i(capoff + PCIE_LCAP)]; 1433 printf(" Link Capabilities Register: 0x%08x\n", reg); 1434 printf(" Maximum Link Speed: "); 1435 val = reg & PCIE_LCAP_MAX_SPEED; 1436 if (val < 1 || val > 3) { 1437 printf("unknown %u value\n", val); 1438 } else { 1439 printf("%sGT/s\n", linkspeeds[val - 1]); 1440 } 1441 printf(" Maximum Link Width: x%u lanes\n", 1442 (unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4); 1443 printf(" Active State PM Support: "); 1444 val = (reg & PCIE_LCAP_ASPM) >> 10; 1445 switch (val) { 1446 case 0x1: 1447 printf("L0s Entry supported\n"); 1448 break; 1449 case 0x3: 1450 printf("L0s and L1 supported\n"); 1451 break; 1452 default: 1453 printf("Reserved value\n"); 1454 break; 1455 } 1456 printf(" L0 Exit Latency: "); 1457 pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12); 1458 printf(" L1 Exit Latency: "); 1459 pci_print_pcie_L1_latency((reg & PCIE_LCAP_L1_EXIT) >> 15); 1460 printf(" Port Number: %u\n", reg >> 24); 1461 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1462 onoff("Surprise Down Error Report", reg, 1463 PCIE_LCAP_SURPRISE_DOWN); 1464 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1465 onoff("Link BW Notification Capable", reg, 1466 PCIE_LCAP_LINK_BW_NOTIFY); 1467 onoff("ASPM Optionally Compliance", reg, 1468 PCIE_LCAP_ASPM_COMPLIANCE); 1469 1470 /* Link Control Register */ 1471 reg = regs[o2i(capoff + PCIE_LCSR)]; 1472 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1473 printf(" Active State PM Control: "); 1474 val = reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S); 1475 switch (val) { 1476 case 0: 1477 printf("disabled\n"); 1478 break; 1479 case 1: 1480 printf("L0s Entry Enabled\n"); 1481 break; 1482 case 2: 1483 printf("L1 Entry Enabled\n"); 1484 break; 1485 case 3: 1486 printf("L0s and L1 Entry Enabled\n"); 1487 break; 1488 } 1489 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1490 "128bytes", "64bytes"); 1491 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1492 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1493 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1494 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1495 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1496 onoff("Hardware Autonomous Width Disable", reg, 1497 PCIE_LCSR_HAWD); 1498 onoff("Link Bandwidth Management Interrupt Enable", reg, 1499 PCIE_LCSR_LBMIE); 1500 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1501 PCIE_LCSR_LABIE); 1502 1503 /* Link Status Register */ 1504 reg = regs[o2i(capoff + PCIE_LCSR)]; 1505 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1506 printf(" Negotiated Link Speed: "); 1507 if (((reg >> 16) & 0x000f) < 1 || 1508 ((reg >> 16) & 0x000f) > 3) { 1509 printf("unknown %u value\n", 1510 (unsigned int)(reg & PCIE_LCSR_LINKSPEED) >> 16); 1511 } else { 1512 printf("%sGT/s\n", 1513 linkspeeds[((reg & PCIE_LCSR_LINKSPEED) >> 16)-1]); 1514 } 1515 printf(" Negotiated Link Width: x%u lanes\n", 1516 (reg >> 20) & 0x003f); 1517 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1518 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1519 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1520 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1521 onoff("Link Bandwidth Management Status", reg, 1522 PCIE_LCSR_LINK_BW_MGMT); 1523 onoff("Link Autonomous Bandwidth Status", reg, 1524 PCIE_LCSR_LINK_AUTO_BW); 1525 } 1526 1527 if (check_slot == true) { 1528 /* Slot Capability Register */ 1529 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1530 printf(" Slot Capability Register: %08x\n", reg); 1531 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1532 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1533 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1534 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1535 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1536 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1537 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1538 printf(" Slot Power Limit Value: %d\n", 1539 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1540 printf(" Slot Power Limit Scale: %d\n", 1541 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1542 onoff("Electromechanical Interlock Present", reg, 1543 PCIE_SLCAP_EIP); 1544 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1545 printf(" Physical Slot Number: %d\n", 1546 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1547 1548 /* Slot Control Register */ 1549 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1550 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1551 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1552 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1553 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1554 onoff("Presense Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1555 onoff("Command Completed Interrupt Enabled", reg, 1556 PCIE_SLCSR_CCE); 1557 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1558 printf(" Attention Indicator Control: "); 1559 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1560 case 0x0: 1561 printf("reserved\n"); 1562 break; 1563 case 0x1: 1564 printf("on\n"); 1565 break; 1566 case 0x2: 1567 printf("blink\n"); 1568 break; 1569 case 0x3: 1570 printf("off\n"); 1571 break; 1572 } 1573 printf(" Power Indicator Control: "); 1574 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1575 case 0x0: 1576 printf("reserved\n"); 1577 break; 1578 case 0x1: 1579 printf("on\n"); 1580 break; 1581 case 0x2: 1582 printf("blink\n"); 1583 break; 1584 case 0x3: 1585 printf("off\n"); 1586 break; 1587 } 1588 onoff("Power Controller Control", reg, PCIE_SLCSR_PCC); 1589 onoff("Electromechanical Interlock Control", 1590 reg, PCIE_SLCSR_EIC); 1591 onoff("Data Link Layer State Changed Enable", reg, 1592 PCIE_SLCSR_DLLSCE); 1593 1594 /* Slot Status Register */ 1595 printf(" Slot Status Register: %04x\n", reg >> 16); 1596 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1597 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1598 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1599 onoff("Presense Detect Changed", reg, PCIE_SLCSR_PDC); 1600 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1601 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1602 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1603 onoff("Electromechanical Interlock engaged", reg, 1604 PCIE_SLCSR_EIS); 1605 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 1606 } 1607 1608 if (check_rootport == true) { 1609 /* Root Control Register */ 1610 reg = regs[o2i(capoff + PCIE_RCR)]; 1611 printf(" Root Control Register: %04x\n", reg & 0xffff); 1612 onoff("SERR on Correctable Error Enable", reg, 1613 PCIE_RCR_SERR_CER); 1614 onoff("SERR on Non-Fatal Error Enable", reg, 1615 PCIE_RCR_SERR_NFER); 1616 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 1617 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 1618 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 1619 1620 /* Root Capability Register */ 1621 printf(" Root Capability Register: %04x\n", 1622 reg >> 16); 1623 1624 /* Root Status Register */ 1625 reg = regs[o2i(capoff + PCIE_RSR)]; 1626 printf(" Root Status Register: %08x\n", reg); 1627 printf(" PME Requester ID: %04x\n", 1628 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1629 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 1630 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 1631 } 1632 1633 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1634 if (pciever < 2) 1635 return; 1636 1637 /* Device Capabilities 2 */ 1638 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1639 printf(" Device Capabilities 2: 0x%08x\n", reg); 1640 printf(" Completion Timeout Ranges Supported: %u \n", 1641 (unsigned int)(reg & PCIE_DCAP2_COMPT_RANGE)); 1642 onoff("Completion Timeout Disable Supported", reg, 1643 PCIE_DCAP2_COMPT_DIS); 1644 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 1645 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 1646 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 1647 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 1648 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 1649 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 1650 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 1651 printf(" TPH Completer Supported: %u\n", 1652 (unsigned int)(reg & PCIE_DCAP2_TPH_COMP) >> 12); 1653 printf(" OBFF Supported: "); 1654 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 1655 case 0x0: 1656 printf("Not supported\n"); 1657 break; 1658 case 0x1: 1659 printf("Message only\n"); 1660 break; 1661 case 0x2: 1662 printf("WAKE# only\n"); 1663 break; 1664 case 0x3: 1665 printf("Both\n"); 1666 break; 1667 } 1668 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 1669 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 1670 printf(" Max End-End TLP Prefixes: %u\n", 1671 (unsigned int)(reg & PCIE_DCAP2_MAX_EETLP) >> 22); 1672 1673 /* Device Control 2 */ 1674 reg = regs[o2i(capoff + PCIE_DCSR2)]; 1675 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 1676 printf(" Completion Timeout Value: "); 1677 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 1678 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 1679 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 1680 onoff("AtomicOp Rquester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 1681 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 1682 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 1683 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 1684 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 1685 printf(" OBFF: "); 1686 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 1687 case 0x0: 1688 printf("Disabled\n"); 1689 break; 1690 case 0x1: 1691 printf("Enabled with Message Signaling Variation A\n"); 1692 break; 1693 case 0x2: 1694 printf("Enabled with Message Signaling Variation B\n"); 1695 break; 1696 case 0x3: 1697 printf("Enabled using WAKE# signaling\n"); 1698 break; 1699 } 1700 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 1701 1702 if (check_link) { 1703 /* Link Capability 2 */ 1704 reg = regs[o2i(capoff + PCIE_LCAP2)]; 1705 printf(" Link Capabilities 2: 0x%08x\n", reg); 1706 val = (reg & PCIE_LCAP2_SUP_LNKSV) >> 1; 1707 printf(" Supported Link Speed Vector:"); 1708 for (i = 0; i <= 2; i++) { 1709 if (((val >> i) & 0x01) != 0) 1710 printf(" %sGT/s", linkspeeds[i]); 1711 } 1712 printf("\n"); 1713 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 1714 1715 /* Link Control 2 */ 1716 reg = regs[o2i(capoff + PCIE_LCSR2)]; 1717 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 1718 printf(" Target Link Speed: "); 1719 val = reg & PCIE_LCSR2_TGT_LSPEED; 1720 if (val < 1 || val > 3) 1721 printf("unknown %u value\n", val); 1722 else 1723 printf("%sGT/s\n", linkspeeds[val - 1]); 1724 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 1725 onoff("HW Autonomous Speed Disabled", reg, 1726 PCIE_LCSR2_HW_AS_DIS); 1727 onoff("Selectable De-emphasis", reg, PCIE_LCSR2_SEL_DEEMP); 1728 printf(" Transmit Margin: %u\n", 1729 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 1730 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 1731 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 1732 printf(" Compliance Present/De-emphasis: %u\n", 1733 (unsigned int)(reg & PCIE_LCSR2_COMP_DEEMP) >> 12); 1734 1735 /* Link Status 2 */ 1736 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 1737 onoff("Current De-emphasis Level", reg, PCIE_LCSR2_DEEMP_LVL); 1738 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 1739 onoff("Equalization Phase 1 Successful", reg, 1740 PCIE_LCSR2_EQP1_SUC); 1741 onoff("Equalization Phase 2 Successful", reg, 1742 PCIE_LCSR2_EQP2_SUC); 1743 onoff("Equalization Phase 3 Successful", reg, 1744 PCIE_LCSR2_EQP3_SUC); 1745 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 1746 } 1747 1748 /* Slot Capability 2 */ 1749 /* Slot Control 2 */ 1750 /* Slot Status 2 */ 1751 } 1752 1753 static void 1754 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 1755 { 1756 pcireg_t reg; 1757 1758 printf("\n MSI-X Capability Register\n"); 1759 1760 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 1761 printf(" Message Control register: 0x%04x\n", 1762 (reg >> 16) & 0xff); 1763 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 1764 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 1765 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 1766 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 1767 printf(" Table offset register: 0x%08x\n", reg); 1768 printf(" Table offset: %08x\n", reg & PCI_MSIX_TBLOFFSET_MASK); 1769 printf(" BIR: 0x%x\n", reg & PCI_MSIX_TBLBIR_MASK); 1770 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 1771 printf(" Pending bit array register: 0x%08x\n", reg); 1772 printf(" Pending bit array offset: %08x\n", 1773 reg & PCI_MSIX_PBAOFFSET_MASK); 1774 printf(" BIR: 0x%x\n", reg & PCI_MSIX_PBABIR_MASK); 1775 } 1776 1777 /* XXX pci_conf_print_sata_cap */ 1778 static void 1779 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 1780 { 1781 pcireg_t reg; 1782 1783 printf("\n Advanced Features Capability Register\n"); 1784 1785 reg = regs[o2i(capoff + PCI_AFCAPR)]; 1786 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 1787 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 1788 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 1789 reg = regs[o2i(capoff + PCI_AFCSR)]; 1790 printf(" AF Control register: 0x%02x\n", reg & 0xff); 1791 /* 1792 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 1793 * and it's always 0 on read 1794 */ 1795 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 1796 onoff("Transaction Pending", reg, PCI_AFSR_TP); 1797 } 1798 1799 static void 1800 pci_conf_print_caplist( 1801 #ifdef _KERNEL 1802 pci_chipset_tag_t pc, pcitag_t tag, 1803 #endif 1804 const pcireg_t *regs, int capoff) 1805 { 1806 int off; 1807 pcireg_t rval; 1808 int pcie_off = -1, pcipm_off = -1, msi_off = -1, pcix_off = -1; 1809 int vendspec_off = -1, msix_off = -1; 1810 int debugport_off = -1, subsystem_off = -1, pciaf_off = -1; 1811 1812 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1813 off != 0; 1814 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 1815 rval = regs[o2i(off)]; 1816 printf(" Capability register at 0x%02x\n", off); 1817 1818 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 1819 switch (PCI_CAPLIST_CAP(rval)) { 1820 case PCI_CAP_RESERVED0: 1821 printf("reserved"); 1822 break; 1823 case PCI_CAP_PWRMGMT: 1824 printf("Power Management, rev. %s", 1825 pci_conf_print_pcipm_cap_pmrev( 1826 (rval >> 0) & 0x07)); 1827 pcipm_off = off; 1828 break; 1829 case PCI_CAP_AGP: 1830 printf("AGP, rev. %d.%d", 1831 PCI_CAP_AGP_MAJOR(rval), 1832 PCI_CAP_AGP_MINOR(rval)); 1833 break; 1834 case PCI_CAP_VPD: 1835 printf("VPD"); 1836 break; 1837 case PCI_CAP_SLOTID: 1838 printf("SlotID"); 1839 break; 1840 case PCI_CAP_MSI: 1841 printf("MSI"); 1842 msi_off = off; 1843 break; 1844 case PCI_CAP_CPCI_HOTSWAP: 1845 printf("CompactPCI Hot-swapping"); 1846 break; 1847 case PCI_CAP_PCIX: 1848 pcix_off = off; 1849 printf("PCI-X"); 1850 break; 1851 case PCI_CAP_LDT: 1852 printf("HyperTransport"); 1853 break; 1854 case PCI_CAP_VENDSPEC: 1855 vendspec_off = off; 1856 printf("Vendor-specific"); 1857 break; 1858 case PCI_CAP_DEBUGPORT: 1859 printf("Debug Port"); 1860 debugport_off = off; 1861 break; 1862 case PCI_CAP_CPCI_RSRCCTL: 1863 printf("CompactPCI Resource Control"); 1864 break; 1865 case PCI_CAP_HOTPLUG: 1866 printf("Hot-Plug"); 1867 break; 1868 case PCI_CAP_SUBVENDOR: 1869 printf("Subsystem vendor ID"); 1870 subsystem_off = off; 1871 break; 1872 case PCI_CAP_AGP8: 1873 printf("AGP 8x"); 1874 break; 1875 case PCI_CAP_SECURE: 1876 printf("Secure Device"); 1877 break; 1878 case PCI_CAP_PCIEXPRESS: 1879 printf("PCI Express"); 1880 pcie_off = off; 1881 break; 1882 case PCI_CAP_MSIX: 1883 printf("MSI-X"); 1884 msix_off = off; 1885 break; 1886 case PCI_CAP_SATA: 1887 printf("SATA"); 1888 break; 1889 case PCI_CAP_PCIAF: 1890 printf("Advanced Features"); 1891 pciaf_off = off; 1892 break; 1893 default: 1894 printf("unknown"); 1895 } 1896 printf(")\n"); 1897 } 1898 if (pcipm_off != -1) 1899 pci_conf_print_pcipm_cap(regs, pcipm_off); 1900 /* XXX AGP */ 1901 /* XXX VPD */ 1902 /* XXX SLOTID */ 1903 if (msi_off != -1) 1904 pci_conf_print_msi_cap(regs, msi_off); 1905 /* XXX CPCI_HOTSWAP */ 1906 if (pcix_off != -1) 1907 pci_conf_print_pcix_cap(regs, pcix_off); 1908 /* XXX LDT */ 1909 if (vendspec_off != -1) 1910 pci_conf_print_vendspec_cap(regs, vendspec_off); 1911 if (debugport_off != -1) 1912 pci_conf_print_debugport_cap(regs, debugport_off); 1913 /* XXX CPCI_RSRCCTL */ 1914 /* XXX HOTPLUG */ 1915 if (subsystem_off != -1) 1916 pci_conf_print_subsystem_cap(regs, subsystem_off); 1917 /* XXX AGP8 */ 1918 /* XXX SECURE */ 1919 if (pcie_off != -1) 1920 pci_conf_print_pcie_cap(regs, pcie_off); 1921 if (msix_off != -1) 1922 pci_conf_print_msix_cap(regs, msix_off); 1923 /* XXX SATA */ 1924 if (pciaf_off != -1) 1925 pci_conf_print_pciaf_cap(regs, pciaf_off); 1926 } 1927 1928 /* Print the Secondary Status Register. */ 1929 static void 1930 pci_conf_print_ssr(pcireg_t rval) 1931 { 1932 pcireg_t devsel; 1933 1934 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 1935 onoff("66 MHz capable", rval, __BIT(5)); 1936 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 1937 onoff("Fast back-to-back capable", rval, __BIT(7)); 1938 onoff("Data parity error detected", rval, __BIT(8)); 1939 1940 printf(" DEVSEL timing: "); 1941 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 1942 switch (devsel) { 1943 case 0: 1944 printf("fast"); 1945 break; 1946 case 1: 1947 printf("medium"); 1948 break; 1949 case 2: 1950 printf("slow"); 1951 break; 1952 default: 1953 printf("unknown/reserved"); /* XXX */ 1954 break; 1955 } 1956 printf(" (0x%x)\n", devsel); 1957 1958 onoff("Signalled target abort", rval, __BIT(11)); 1959 onoff("Received target abort", rval, __BIT(12)); 1960 onoff("Received master abort", rval, __BIT(13)); 1961 onoff("Received system error", rval, __BIT(14)); 1962 onoff("Detected parity error", rval, __BIT(15)); 1963 } 1964 1965 static void 1966 pci_conf_print_type0( 1967 #ifdef _KERNEL 1968 pci_chipset_tag_t pc, pcitag_t tag, 1969 #endif 1970 const pcireg_t *regs 1971 #ifdef _KERNEL 1972 , int sizebars 1973 #endif 1974 ) 1975 { 1976 int off, width; 1977 pcireg_t rval; 1978 1979 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 1980 #ifdef _KERNEL 1981 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 1982 #else 1983 width = pci_conf_print_bar(regs, off, NULL); 1984 #endif 1985 } 1986 1987 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 1988 1989 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 1990 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1991 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1992 1993 /* XXX */ 1994 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 1995 1996 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1997 printf(" Capability list pointer: 0x%02x\n", 1998 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 1999 else 2000 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 2001 2002 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 2003 2004 rval = regs[o2i(PCI_INTERRUPT_REG)]; 2005 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 2006 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 2007 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 2008 switch (PCI_INTERRUPT_PIN(rval)) { 2009 case PCI_INTERRUPT_PIN_NONE: 2010 printf("(none)"); 2011 break; 2012 case PCI_INTERRUPT_PIN_A: 2013 printf("(pin A)"); 2014 break; 2015 case PCI_INTERRUPT_PIN_B: 2016 printf("(pin B)"); 2017 break; 2018 case PCI_INTERRUPT_PIN_C: 2019 printf("(pin C)"); 2020 break; 2021 case PCI_INTERRUPT_PIN_D: 2022 printf("(pin D)"); 2023 break; 2024 default: 2025 printf("(? ? ?)"); 2026 break; 2027 } 2028 printf("\n"); 2029 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 2030 } 2031 2032 static void 2033 pci_conf_print_type1( 2034 #ifdef _KERNEL 2035 pci_chipset_tag_t pc, pcitag_t tag, 2036 #endif 2037 const pcireg_t *regs 2038 #ifdef _KERNEL 2039 , int sizebars 2040 #endif 2041 ) 2042 { 2043 int off, width; 2044 pcireg_t rval; 2045 uint32_t base, limit; 2046 uint32_t base_h, limit_h; 2047 uint64_t pbase, plimit; 2048 int use_upper; 2049 2050 /* 2051 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 2052 * Bridge chip documentation, and may not be correct with 2053 * respect to various standards. (XXX) 2054 */ 2055 2056 for (off = 0x10; off < 0x18; off += width) { 2057 #ifdef _KERNEL 2058 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 2059 #else 2060 width = pci_conf_print_bar(regs, off, NULL); 2061 #endif 2062 } 2063 2064 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 2065 printf(" Primary bus number: 0x%02x\n", 2066 PCI_BRIDGE_BUS_PRIMARY(rval)); 2067 printf(" Secondary bus number: 0x%02x\n", 2068 PCI_BRIDGE_BUS_SECONDARY(rval)); 2069 printf(" Subordinate bus number: 0x%02x\n", 2070 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 2071 printf(" Secondary bus latency timer: 0x%02x\n", 2072 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 2073 2074 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 2075 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 2076 2077 /* I/O region */ 2078 printf(" I/O region:\n"); 2079 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 2080 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 2081 if (PCI_BRIDGE_IO_32BITS(rval)) 2082 use_upper = 1; 2083 else 2084 use_upper = 0; 2085 onoff("32bit I/O", rval, use_upper); 2086 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 2087 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 2088 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 2089 limit |= 0x00000fff; 2090 2091 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 2092 base_h = (rval >> 0) & 0xffff; 2093 limit_h = (rval >> 16) & 0xffff; 2094 printf(" base upper 16 bits register: 0x%04x\n", base_h); 2095 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 2096 2097 if (use_upper == 1) { 2098 base |= base_h << 16; 2099 limit |= limit_h << 16; 2100 } 2101 if (base < limit) { 2102 if (use_upper == 1) 2103 printf(" range: 0x%08x-0x%08x\n", base, limit); 2104 else 2105 printf(" range: 0x%04x-0x%04x\n", base, limit); 2106 } else 2107 printf(" range: not set\n"); 2108 2109 /* Non-prefetchable memory region */ 2110 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 2111 printf(" Memory region:\n"); 2112 printf(" base register: 0x%04x\n", 2113 (rval >> 0) & 0xffff); 2114 printf(" limit register: 0x%04x\n", 2115 (rval >> 16) & 0xffff); 2116 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 2117 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 2118 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 2119 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 2120 if (base < limit) 2121 printf(" range: 0x%08x-0x%08x\n", base, limit); 2122 else 2123 printf(" range: not set\n"); 2124 2125 /* Prefetchable memory region */ 2126 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 2127 printf(" Prefetchable memory region:\n"); 2128 printf(" base register: 0x%04x\n", 2129 (rval >> 0) & 0xffff); 2130 printf(" limit register: 0x%04x\n", 2131 (rval >> 16) & 0xffff); 2132 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 2133 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 2134 printf(" base upper 32 bits register: 0x%08x\n", 2135 base_h); 2136 printf(" limit upper 32 bits register: 0x%08x\n", 2137 limit_h); 2138 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 2139 use_upper = 1; 2140 else 2141 use_upper = 0; 2142 onoff("64bit memory address", rval, use_upper); 2143 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 2144 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 2145 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 2146 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 2147 if (use_upper == 1) { 2148 pbase |= (uint64_t)base_h << 32; 2149 plimit |= (uint64_t)limit_h << 32; 2150 } 2151 if (pbase < plimit) { 2152 if (use_upper == 1) 2153 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 2154 "\n", pbase, plimit); 2155 else 2156 printf(" range: 0x%08x-0x%08x\n", 2157 (uint32_t)pbase, (uint32_t)plimit); 2158 } else 2159 printf(" range: not set\n"); 2160 2161 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2162 printf(" Capability list pointer: 0x%02x\n", 2163 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 2164 else 2165 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 2166 2167 /* XXX */ 2168 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 2169 2170 rval = regs[o2i(PCI_INTERRUPT_REG)]; 2171 printf(" Interrupt line: 0x%02x\n", 2172 (rval >> 0) & 0xff); 2173 printf(" Interrupt pin: 0x%02x ", 2174 (rval >> 8) & 0xff); 2175 switch ((rval >> 8) & 0xff) { 2176 case PCI_INTERRUPT_PIN_NONE: 2177 printf("(none)"); 2178 break; 2179 case PCI_INTERRUPT_PIN_A: 2180 printf("(pin A)"); 2181 break; 2182 case PCI_INTERRUPT_PIN_B: 2183 printf("(pin B)"); 2184 break; 2185 case PCI_INTERRUPT_PIN_C: 2186 printf("(pin C)"); 2187 break; 2188 case PCI_INTERRUPT_PIN_D: 2189 printf("(pin D)"); 2190 break; 2191 default: 2192 printf("(? ? ?)"); 2193 break; 2194 } 2195 printf("\n"); 2196 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 2197 & PCI_BRIDGE_CONTROL_MASK; 2198 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 2199 onoff("Parity error response", rval, 0x0001); 2200 onoff("Secondary SERR forwarding", rval, 0x0002); 2201 onoff("ISA enable", rval, 0x0004); 2202 onoff("VGA enable", rval, 0x0008); 2203 onoff("Master abort reporting", rval, 0x0020); 2204 onoff("Secondary bus reset", rval, 0x0040); 2205 onoff("Fast back-to-back capable", rval, 0x0080); 2206 } 2207 2208 static void 2209 pci_conf_print_type2( 2210 #ifdef _KERNEL 2211 pci_chipset_tag_t pc, pcitag_t tag, 2212 #endif 2213 const pcireg_t *regs 2214 #ifdef _KERNEL 2215 , int sizebars 2216 #endif 2217 ) 2218 { 2219 pcireg_t rval; 2220 2221 /* 2222 * XXX these need to be printed in more detail, need to be 2223 * XXX checked against specs/docs, etc. 2224 * 2225 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 2226 * controller chip documentation, and may not be correct with 2227 * respect to various standards. (XXX) 2228 */ 2229 2230 #ifdef _KERNEL 2231 pci_conf_print_bar(pc, tag, regs, 0x10, 2232 "CardBus socket/ExCA registers", sizebars); 2233 #else 2234 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 2235 #endif 2236 2237 /* Capability list pointer and secondary status register */ 2238 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 2239 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2240 printf(" Capability list pointer: 0x%02x\n", 2241 PCI_CAPLIST_PTR(rval)); 2242 else 2243 printf(" Reserved @ 0x14: 0x%04" PRIxMAX "\n", 2244 __SHIFTOUT(rval, __BITS(15, 0))); 2245 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 2246 2247 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 2248 printf(" PCI bus number: 0x%02x\n", 2249 (rval >> 0) & 0xff); 2250 printf(" CardBus bus number: 0x%02x\n", 2251 (rval >> 8) & 0xff); 2252 printf(" Subordinate bus number: 0x%02x\n", 2253 (rval >> 16) & 0xff); 2254 printf(" CardBus latency timer: 0x%02x\n", 2255 (rval >> 24) & 0xff); 2256 2257 /* XXX Print more prettily */ 2258 printf(" CardBus memory region 0:\n"); 2259 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 2260 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 2261 printf(" CardBus memory region 1:\n"); 2262 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 2263 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 2264 printf(" CardBus I/O region 0:\n"); 2265 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 2266 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 2267 printf(" CardBus I/O region 1:\n"); 2268 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 2269 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 2270 2271 rval = regs[o2i(PCI_INTERRUPT_REG)]; 2272 printf(" Interrupt line: 0x%02x\n", 2273 (rval >> 0) & 0xff); 2274 printf(" Interrupt pin: 0x%02x ", 2275 (rval >> 8) & 0xff); 2276 switch ((rval >> 8) & 0xff) { 2277 case PCI_INTERRUPT_PIN_NONE: 2278 printf("(none)"); 2279 break; 2280 case PCI_INTERRUPT_PIN_A: 2281 printf("(pin A)"); 2282 break; 2283 case PCI_INTERRUPT_PIN_B: 2284 printf("(pin B)"); 2285 break; 2286 case PCI_INTERRUPT_PIN_C: 2287 printf("(pin C)"); 2288 break; 2289 case PCI_INTERRUPT_PIN_D: 2290 printf("(pin D)"); 2291 break; 2292 default: 2293 printf("(? ? ?)"); 2294 break; 2295 } 2296 printf("\n"); 2297 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 2298 printf(" Bridge control register: 0x%04x\n", rval); 2299 onoff("Parity error response", rval, __BIT(0)); 2300 onoff("SERR# enable", rval, __BIT(1)); 2301 onoff("ISA enable", rval, __BIT(2)); 2302 onoff("VGA enable", rval, __BIT(3)); 2303 onoff("Master abort mode", rval, __BIT(5)); 2304 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 2305 onoff("Functional interrupts routed by ExCA registers", rval, 2306 __BIT(7)); 2307 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 2308 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 2309 onoff("Write posting enable", rval, __BIT(10)); 2310 2311 rval = regs[o2i(0x40)]; 2312 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 2313 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 2314 2315 #ifdef _KERNEL 2316 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 2317 sizebars); 2318 #else 2319 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 2320 #endif 2321 } 2322 2323 void 2324 pci_conf_print( 2325 #ifdef _KERNEL 2326 pci_chipset_tag_t pc, pcitag_t tag, 2327 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 2328 #else 2329 int pcifd, u_int bus, u_int dev, u_int func 2330 #endif 2331 ) 2332 { 2333 pcireg_t regs[o2i(256)]; 2334 int off, capoff, endoff, hdrtype; 2335 const char *type_name; 2336 #ifdef _KERNEL 2337 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, 2338 int); 2339 int sizebars; 2340 #else 2341 void (*type_printfn)(const pcireg_t *); 2342 #endif 2343 2344 printf("PCI configuration registers:\n"); 2345 2346 for (off = 0; off < 256; off += 4) { 2347 #ifdef _KERNEL 2348 regs[o2i(off)] = pci_conf_read(pc, tag, off); 2349 #else 2350 if (pcibus_conf_read(pcifd, bus, dev, func, off, 2351 ®s[o2i(off)]) == -1) 2352 regs[o2i(off)] = 0; 2353 #endif 2354 } 2355 2356 #ifdef _KERNEL 2357 sizebars = 1; 2358 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 2359 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 2360 sizebars = 0; 2361 #endif 2362 2363 /* common header */ 2364 printf(" Common header:\n"); 2365 pci_conf_print_regs(regs, 0, 16); 2366 2367 printf("\n"); 2368 #ifdef _KERNEL 2369 pci_conf_print_common(pc, tag, regs); 2370 #else 2371 pci_conf_print_common(regs); 2372 #endif 2373 printf("\n"); 2374 2375 /* type-dependent header */ 2376 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 2377 switch (hdrtype) { /* XXX make a table, eventually */ 2378 case 0: 2379 /* Standard device header */ 2380 type_name = "\"normal\" device"; 2381 type_printfn = &pci_conf_print_type0; 2382 capoff = PCI_CAPLISTPTR_REG; 2383 endoff = 64; 2384 break; 2385 case 1: 2386 /* PCI-PCI bridge header */ 2387 type_name = "PCI-PCI bridge"; 2388 type_printfn = &pci_conf_print_type1; 2389 capoff = PCI_CAPLISTPTR_REG; 2390 endoff = 64; 2391 break; 2392 case 2: 2393 /* PCI-CardBus bridge header */ 2394 type_name = "PCI-CardBus bridge"; 2395 type_printfn = &pci_conf_print_type2; 2396 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 2397 endoff = 72; 2398 break; 2399 default: 2400 type_name = NULL; 2401 type_printfn = 0; 2402 capoff = -1; 2403 endoff = 64; 2404 break; 2405 } 2406 printf(" Type %d ", hdrtype); 2407 if (type_name != NULL) 2408 printf("(%s) ", type_name); 2409 printf("header:\n"); 2410 pci_conf_print_regs(regs, 16, endoff); 2411 printf("\n"); 2412 if (type_printfn) { 2413 #ifdef _KERNEL 2414 (*type_printfn)(pc, tag, regs, sizebars); 2415 #else 2416 (*type_printfn)(regs); 2417 #endif 2418 } else 2419 printf(" Don't know how to pretty-print type %d header.\n", 2420 hdrtype); 2421 printf("\n"); 2422 2423 /* capability list, if present */ 2424 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2425 && (capoff > 0)) { 2426 #ifdef _KERNEL 2427 pci_conf_print_caplist(pc, tag, regs, capoff); 2428 #else 2429 pci_conf_print_caplist(regs, capoff); 2430 #endif 2431 printf("\n"); 2432 } 2433 2434 /* device-dependent header */ 2435 printf(" Device-dependent header:\n"); 2436 pci_conf_print_regs(regs, endoff, 256); 2437 printf("\n"); 2438 #ifdef _KERNEL 2439 if (printfn) 2440 (*printfn)(pc, tag, regs); 2441 else 2442 printf(" Don't know how to pretty-print device-dependent header.\n"); 2443 printf("\n"); 2444 #endif /* _KERNEL */ 2445 } 2446
Indexes created Tue Sep 30 11:09:46 GMT 2025