pci_subr.c revision 1.134
1 /* $NetBSD: pci_subr.c,v 1.134 2015/07/27 15:46:03 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.134 2015/07/27 15:46:03 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdbool.h> 58 #include <stdio.h> 59 #include <string.h> 60 #endif 61 62 #include <dev/pci/pcireg.h> 63 #ifdef _KERNEL 64 #include <dev/pci/pcivar.h> 65 #else 66 #include <dev/pci/pci_verbose.h> 67 #include <dev/pci/pcidevs.h> 68 #include <dev/pci/pcidevs_data.h> 69 #endif 70 71 /* 72 * Descriptions of known PCI classes and subclasses. 73 * 74 * Subclasses are described in the same way as classes, but have a 75 * NULL subclass pointer. 76 */ 77 struct pci_class { 78 const char *name; 79 u_int val; /* as wide as pci_{,sub}class_t */ 80 const struct pci_class *subclasses; 81 }; 82 83 /* 84 * Class 0x00. 85 * Before rev. 2.0. 86 */ 87 static const struct pci_class pci_subclass_prehistoric[] = { 88 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 89 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 90 { NULL, 0, NULL, }, 91 }; 92 93 /* 94 * Class 0x01. 95 * Mass storage controller 96 */ 97 98 /* ATA programming interface */ 99 static const struct pci_class pci_interface_ata[] = { 100 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 101 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 102 { NULL, 0, NULL, }, 103 }; 104 105 /* SATA programming interface */ 106 static const struct pci_class pci_interface_sata[] = { 107 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 108 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 109 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 110 { NULL, 0, NULL, }, 111 }; 112 113 /* Flash programming interface */ 114 static const struct pci_class pci_interface_nvm[] = { 115 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 116 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 117 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 118 { NULL, 0, NULL, }, 119 }; 120 121 /* Subclasses */ 122 static const struct pci_class pci_subclass_mass_storage[] = { 123 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 124 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 125 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 126 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 127 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 128 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 129 pci_interface_ata, }, 130 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 131 pci_interface_sata, }, 132 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 133 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 134 pci_interface_nvm, }, 135 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 136 { NULL, 0, NULL, }, 137 }; 138 139 /* 140 * Class 0x02. 141 * Network controller. 142 */ 143 static const struct pci_class pci_subclass_network[] = { 144 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 145 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 146 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 147 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 148 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 149 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 150 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 151 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 152 { NULL, 0, NULL, }, 153 }; 154 155 /* 156 * Class 0x03. 157 * Display controller. 158 */ 159 160 /* VGA programming interface */ 161 static const struct pci_class pci_interface_vga[] = { 162 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 163 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 164 { NULL, 0, NULL, }, 165 }; 166 /* Subclasses */ 167 static const struct pci_class pci_subclass_display[] = { 168 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 169 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 170 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 171 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 172 { NULL, 0, NULL, }, 173 }; 174 175 /* 176 * Class 0x04. 177 * Multimedia device. 178 */ 179 static const struct pci_class pci_subclass_multimedia[] = { 180 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 181 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 182 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 183 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 184 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 185 { NULL, 0, NULL, }, 186 }; 187 188 /* 189 * Class 0x05. 190 * Memory controller. 191 */ 192 static const struct pci_class pci_subclass_memory[] = { 193 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 194 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 195 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 196 { NULL, 0, NULL, }, 197 }; 198 199 /* 200 * Class 0x06. 201 * Bridge device. 202 */ 203 204 /* PCI bridge programming interface */ 205 static const struct pci_class pci_interface_pcibridge[] = { 206 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 207 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 208 { NULL, 0, NULL, }, 209 }; 210 211 /* Semi-transparent PCI-to-PCI bridge programming interface */ 212 static const struct pci_class pci_interface_stpci[] = { 213 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 214 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 215 { NULL, 0, NULL, }, 216 }; 217 218 /* Advanced Switching programming interface */ 219 static const struct pci_class pci_interface_advsw[] = { 220 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 221 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 222 { NULL, 0, NULL, }, 223 }; 224 225 /* Subclasses */ 226 static const struct pci_class pci_subclass_bridge[] = { 227 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 228 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 229 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 230 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 231 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 232 pci_interface_pcibridge, }, 233 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 234 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 235 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 236 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 237 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 238 pci_interface_stpci, }, 239 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 240 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 241 pci_interface_advsw, }, 242 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 243 { NULL, 0, NULL, }, 244 }; 245 246 /* 247 * Class 0x07. 248 * Simple communications controller. 249 */ 250 251 /* Serial controller programming interface */ 252 static const struct pci_class pci_interface_serial[] = { 253 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 254 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 255 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 256 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 257 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 258 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 259 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 260 { NULL, 0, NULL, }, 261 }; 262 263 /* Parallel controller programming interface */ 264 static const struct pci_class pci_interface_parallel[] = { 265 { "", PCI_INTERFACE_PARALLEL, NULL,}, 266 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 267 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 268 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 269 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 270 { NULL, 0, NULL,}, 271 }; 272 273 /* Modem programming interface */ 274 static const struct pci_class pci_interface_modem[] = { 275 { "", PCI_INTERFACE_MODEM, NULL,}, 276 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 277 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 278 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 279 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 280 { NULL, 0, NULL,}, 281 }; 282 283 /* Subclasses */ 284 static const struct pci_class pci_subclass_communications[] = { 285 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 286 pci_interface_serial, }, 287 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 288 pci_interface_parallel, }, 289 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 290 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 291 pci_interface_modem, }, 292 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 293 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 294 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 295 { NULL, 0, NULL,}, 296 }; 297 298 /* 299 * Class 0x08. 300 * Base system peripheral. 301 */ 302 303 /* PIC programming interface */ 304 static const struct pci_class pci_interface_pic[] = { 305 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 306 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 307 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 308 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 309 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 310 { NULL, 0, NULL, }, 311 }; 312 313 /* DMA programming interface */ 314 static const struct pci_class pci_interface_dma[] = { 315 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 316 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 317 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 318 { NULL, 0, NULL, }, 319 }; 320 321 /* Timer programming interface */ 322 static const struct pci_class pci_interface_tmr[] = { 323 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 324 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 325 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 326 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 327 { NULL, 0, NULL, }, 328 }; 329 330 /* RTC programming interface */ 331 static const struct pci_class pci_interface_rtc[] = { 332 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 333 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 334 { NULL, 0, NULL, }, 335 }; 336 337 /* Subclasses */ 338 static const struct pci_class pci_subclass_system[] = { 339 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 340 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 341 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 342 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 343 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 344 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 345 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 346 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 347 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 348 { NULL, 0, NULL, }, 349 }; 350 351 /* 352 * Class 0x09. 353 * Input device. 354 */ 355 356 /* Gameport programming interface */ 357 static const struct pci_class pci_interface_game[] = { 358 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 359 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 360 { NULL, 0, NULL, }, 361 }; 362 363 /* Subclasses */ 364 static const struct pci_class pci_subclass_input[] = { 365 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 366 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 367 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 368 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 369 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 370 pci_interface_game, }, 371 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 372 { NULL, 0, NULL, }, 373 }; 374 375 /* 376 * Class 0x0a. 377 * Docking station. 378 */ 379 static const struct pci_class pci_subclass_dock[] = { 380 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 381 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 382 { NULL, 0, NULL, }, 383 }; 384 385 /* 386 * Class 0x0b. 387 * Processor. 388 */ 389 static const struct pci_class pci_subclass_processor[] = { 390 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 391 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 392 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 393 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 394 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 395 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 396 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 397 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 398 { NULL, 0, NULL, }, 399 }; 400 401 /* 402 * Class 0x0c. 403 * Serial bus controller. 404 */ 405 406 /* IEEE1394 programming interface */ 407 static const struct pci_class pci_interface_ieee1394[] = { 408 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 409 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 410 { NULL, 0, NULL,}, 411 }; 412 413 /* USB programming interface */ 414 static const struct pci_class pci_interface_usb[] = { 415 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 416 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 417 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 418 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 419 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 420 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 421 { NULL, 0, NULL, }, 422 }; 423 424 /* IPMI programming interface */ 425 static const struct pci_class pci_interface_ipmi[] = { 426 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 427 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 428 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 429 { NULL, 0, NULL,}, 430 }; 431 432 /* Subclasses */ 433 static const struct pci_class pci_subclass_serialbus[] = { 434 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 435 pci_interface_ieee1394, }, 436 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 437 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 438 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 439 pci_interface_usb, }, 440 /* XXX Fiber Channel/_FIBRECHANNEL */ 441 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 442 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 443 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 444 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 445 pci_interface_ipmi, }, 446 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 447 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 448 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 449 { NULL, 0, NULL, }, 450 }; 451 452 /* 453 * Class 0x0d. 454 * Wireless Controller. 455 */ 456 static const struct pci_class pci_subclass_wireless[] = { 457 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 458 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 459 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 460 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 461 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 462 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 463 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 464 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 465 { NULL, 0, NULL, }, 466 }; 467 468 /* 469 * Class 0x0e. 470 * Intelligent IO controller. 471 */ 472 473 /* Intelligent IO programming interface */ 474 static const struct pci_class pci_interface_i2o[] = { 475 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 476 { NULL, 0, NULL,}, 477 }; 478 479 /* Subclasses */ 480 static const struct pci_class pci_subclass_i2o[] = { 481 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 482 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 483 { NULL, 0, NULL, }, 484 }; 485 486 /* 487 * Class 0x0f. 488 * Satellite communication controller. 489 */ 490 static const struct pci_class pci_subclass_satcom[] = { 491 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 492 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 493 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 494 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 495 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 496 { NULL, 0, NULL, }, 497 }; 498 499 /* 500 * Class 0x10. 501 * Encryption/Decryption controller. 502 */ 503 static const struct pci_class pci_subclass_crypto[] = { 504 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 505 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 506 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 507 { NULL, 0, NULL, }, 508 }; 509 510 /* 511 * Class 0x11. 512 * Data aquuisition and signal processing controller. 513 */ 514 static const struct pci_class pci_subclass_dasp[] = { 515 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 516 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 517 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 518 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 519 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 520 { NULL, 0, NULL, }, 521 }; 522 523 /* List of classes */ 524 static const struct pci_class pci_class[] = { 525 { "prehistoric", PCI_CLASS_PREHISTORIC, 526 pci_subclass_prehistoric, }, 527 { "mass storage", PCI_CLASS_MASS_STORAGE, 528 pci_subclass_mass_storage, }, 529 { "network", PCI_CLASS_NETWORK, 530 pci_subclass_network, }, 531 { "display", PCI_CLASS_DISPLAY, 532 pci_subclass_display, }, 533 { "multimedia", PCI_CLASS_MULTIMEDIA, 534 pci_subclass_multimedia, }, 535 { "memory", PCI_CLASS_MEMORY, 536 pci_subclass_memory, }, 537 { "bridge", PCI_CLASS_BRIDGE, 538 pci_subclass_bridge, }, 539 { "communications", PCI_CLASS_COMMUNICATIONS, 540 pci_subclass_communications, }, 541 { "system", PCI_CLASS_SYSTEM, 542 pci_subclass_system, }, 543 { "input", PCI_CLASS_INPUT, 544 pci_subclass_input, }, 545 { "dock", PCI_CLASS_DOCK, 546 pci_subclass_dock, }, 547 { "processor", PCI_CLASS_PROCESSOR, 548 pci_subclass_processor, }, 549 { "serial bus", PCI_CLASS_SERIALBUS, 550 pci_subclass_serialbus, }, 551 { "wireless", PCI_CLASS_WIRELESS, 552 pci_subclass_wireless, }, 553 { "I2O", PCI_CLASS_I2O, 554 pci_subclass_i2o, }, 555 { "satellite comm", PCI_CLASS_SATCOM, 556 pci_subclass_satcom, }, 557 { "crypto", PCI_CLASS_CRYPTO, 558 pci_subclass_crypto, }, 559 { "DASP", PCI_CLASS_DASP, 560 pci_subclass_dasp, }, 561 { "undefined", PCI_CLASS_UNDEFINED, 562 NULL, }, 563 { NULL, 0, 564 NULL, }, 565 }; 566 567 DEV_VERBOSE_DEFINE(pci); 568 569 void 570 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 571 size_t l) 572 { 573 pci_class_t pciclass; 574 pci_subclass_t subclass; 575 pci_interface_t interface; 576 pci_revision_t revision; 577 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 578 const struct pci_class *classp, *subclassp, *interfacep; 579 char *ep; 580 581 ep = cp + l; 582 583 pciclass = PCI_CLASS(class_reg); 584 subclass = PCI_SUBCLASS(class_reg); 585 interface = PCI_INTERFACE(class_reg); 586 revision = PCI_REVISION(class_reg); 587 588 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 589 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 590 PCI_PRODUCT(id_reg)); 591 592 classp = pci_class; 593 while (classp->name != NULL) { 594 if (pciclass == classp->val) 595 break; 596 classp++; 597 } 598 599 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 600 while (subclassp && subclassp->name != NULL) { 601 if (subclass == subclassp->val) 602 break; 603 subclassp++; 604 } 605 606 interfacep = (subclassp && subclassp->name != NULL) ? 607 subclassp->subclasses : NULL; 608 while (interfacep && interfacep->name != NULL) { 609 if (interface == interfacep->val) 610 break; 611 interfacep++; 612 } 613 614 cp += snprintf(cp, ep - cp, "%s %s", vendor, product); 615 if (showclass) { 616 cp += snprintf(cp, ep - cp, " ("); 617 if (classp->name == NULL) 618 cp += snprintf(cp, ep - cp, 619 "class 0x%02x, subclass 0x%02x", pciclass, subclass); 620 else { 621 if (subclassp == NULL || subclassp->name == NULL) 622 cp += snprintf(cp, ep - cp, 623 "%s, subclass 0x%02x", 624 classp->name, subclass); 625 else 626 cp += snprintf(cp, ep - cp, "%s %s", 627 subclassp->name, classp->name); 628 } 629 if ((interfacep == NULL) || (interfacep->name == NULL)) { 630 if (interface != 0) 631 cp += snprintf(cp, ep - cp, 632 ", interface 0x%02x", interface); 633 } else if (strncmp(interfacep->name, "", 1) != 0) 634 cp += snprintf(cp, ep - cp, ", %s", 635 interfacep->name); 636 if (revision != 0) 637 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 638 revision); 639 cp += snprintf(cp, ep - cp, ")"); 640 } 641 } 642 643 #ifdef _KERNEL 644 void 645 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 646 const char *known, int addrev) 647 { 648 char devinfo[256]; 649 650 if (known) { 651 aprint_normal(": %s", known); 652 if (addrev) 653 aprint_normal(" (rev. 0x%02x)", 654 PCI_REVISION(pa->pa_class)); 655 aprint_normal("\n"); 656 } else { 657 pci_devinfo(pa->pa_id, pa->pa_class, 0, 658 devinfo, sizeof(devinfo)); 659 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 660 PCI_REVISION(pa->pa_class)); 661 } 662 if (naive) 663 aprint_naive(": %s\n", naive); 664 else 665 aprint_naive("\n"); 666 } 667 #endif 668 669 /* 670 * Print out most of the PCI configuration registers. Typically used 671 * in a device attach routine like this: 672 * 673 * #ifdef MYDEV_DEBUG 674 * printf("%s: ", device_xname(sc->sc_dev)); 675 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 676 * #endif 677 */ 678 679 #define i2o(i) ((i) * 4) 680 #define o2i(o) ((o) / 4) 681 #define onoff2(str, rval, bit, onstr, offstr) \ 682 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 683 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 684 685 static void 686 pci_conf_print_common( 687 #ifdef _KERNEL 688 pci_chipset_tag_t pc, pcitag_t tag, 689 #endif 690 const pcireg_t *regs) 691 { 692 const char *name; 693 const struct pci_class *classp, *subclassp; 694 char vendor[PCI_VENDORSTR_LEN]; 695 char product[PCI_PRODUCTSTR_LEN]; 696 pcireg_t rval; 697 unsigned int num; 698 699 rval = regs[o2i(PCI_ID_REG)]; 700 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 701 if (name) 702 printf(" Vendor Name: %s (0x%04x)\n", name, 703 PCI_VENDOR(rval)); 704 else 705 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 706 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 707 PCI_PRODUCT(rval)); 708 if (name) 709 printf(" Device Name: %s (0x%04x)\n", name, 710 PCI_PRODUCT(rval)); 711 else 712 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 713 714 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 715 716 printf(" Command register: 0x%04x\n", rval & 0xffff); 717 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 718 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 719 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 720 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 721 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 722 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 723 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 724 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 725 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 726 onoff("Fast back-to-back transactions", rval, 727 PCI_COMMAND_BACKTOBACK_ENABLE); 728 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 729 730 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 731 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 732 "inactive"); 733 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 734 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 735 onoff("User Definable Features (UDF) support", rval, 736 PCI_STATUS_UDF_SUPPORT); 737 onoff("Fast back-to-back capable", rval, 738 PCI_STATUS_BACKTOBACK_SUPPORT); 739 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 740 741 printf(" DEVSEL timing: "); 742 switch (rval & PCI_STATUS_DEVSEL_MASK) { 743 case PCI_STATUS_DEVSEL_FAST: 744 printf("fast"); 745 break; 746 case PCI_STATUS_DEVSEL_MEDIUM: 747 printf("medium"); 748 break; 749 case PCI_STATUS_DEVSEL_SLOW: 750 printf("slow"); 751 break; 752 default: 753 printf("unknown/reserved"); /* XXX */ 754 break; 755 } 756 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 757 758 onoff("Slave signaled Target Abort", rval, 759 PCI_STATUS_TARGET_TARGET_ABORT); 760 onoff("Master received Target Abort", rval, 761 PCI_STATUS_MASTER_TARGET_ABORT); 762 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 763 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 764 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 765 766 rval = regs[o2i(PCI_CLASS_REG)]; 767 for (classp = pci_class; classp->name != NULL; classp++) { 768 if (PCI_CLASS(rval) == classp->val) 769 break; 770 } 771 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 772 while (subclassp && subclassp->name != NULL) { 773 if (PCI_SUBCLASS(rval) == subclassp->val) 774 break; 775 subclassp++; 776 } 777 if (classp->name != NULL) { 778 printf(" Class Name: %s (0x%02x)\n", classp->name, 779 PCI_CLASS(rval)); 780 if (subclassp != NULL && subclassp->name != NULL) 781 printf(" Subclass Name: %s (0x%02x)\n", 782 subclassp->name, PCI_SUBCLASS(rval)); 783 else 784 printf(" Subclass ID: 0x%02x\n", 785 PCI_SUBCLASS(rval)); 786 } else { 787 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 788 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 789 } 790 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 791 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 792 793 rval = regs[o2i(PCI_BHLC_REG)]; 794 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 795 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 796 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 797 PCI_HDRTYPE(rval)); 798 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 799 num = PCI_CACHELINE(rval); 800 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 801 } 802 803 static int 804 pci_conf_print_bar( 805 #ifdef _KERNEL 806 pci_chipset_tag_t pc, pcitag_t tag, 807 #endif 808 const pcireg_t *regs, int reg, const char *name 809 #ifdef _KERNEL 810 , int sizebar 811 #endif 812 ) 813 { 814 int width; 815 pcireg_t rval, rval64h; 816 #ifdef _KERNEL 817 int s; 818 pcireg_t mask, mask64h; 819 #endif 820 821 width = 4; 822 823 /* 824 * Section 6.2.5.1, `Address Maps', tells us that: 825 * 826 * 1) The builtin software should have already mapped the 827 * device in a reasonable way. 828 * 829 * 2) A device which wants 2^n bytes of memory will hardwire 830 * the bottom n bits of the address to 0. As recommended, 831 * we write all 1s and see what we get back. 832 */ 833 834 rval = regs[o2i(reg)]; 835 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 836 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 837 rval64h = regs[o2i(reg + 4)]; 838 width = 8; 839 } else 840 rval64h = 0; 841 842 #ifdef _KERNEL 843 /* XXX don't size unknown memory type? */ 844 if (rval != 0 && sizebar) { 845 /* 846 * The following sequence seems to make some devices 847 * (e.g. host bus bridges, which don't normally 848 * have their space mapped) very unhappy, to 849 * the point of crashing the system. 850 * 851 * Therefore, if the mapping register is zero to 852 * start out with, don't bother trying. 853 */ 854 s = splhigh(); 855 pci_conf_write(pc, tag, reg, 0xffffffff); 856 mask = pci_conf_read(pc, tag, reg); 857 pci_conf_write(pc, tag, reg, rval); 858 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 859 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 860 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 861 mask64h = pci_conf_read(pc, tag, reg + 4); 862 pci_conf_write(pc, tag, reg + 4, rval64h); 863 } else 864 mask64h = 0; 865 splx(s); 866 } else 867 mask = mask64h = 0; 868 #endif /* _KERNEL */ 869 870 printf(" Base address register at 0x%02x", reg); 871 if (name) 872 printf(" (%s)", name); 873 printf("\n "); 874 if (rval == 0) { 875 printf("not implemented(?)\n"); 876 return width; 877 } 878 printf("type: "); 879 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 880 const char *type, *prefetch; 881 882 switch (PCI_MAPREG_MEM_TYPE(rval)) { 883 case PCI_MAPREG_MEM_TYPE_32BIT: 884 type = "32-bit"; 885 break; 886 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 887 type = "32-bit-1M"; 888 break; 889 case PCI_MAPREG_MEM_TYPE_64BIT: 890 type = "64-bit"; 891 break; 892 default: 893 type = "unknown (XXX)"; 894 break; 895 } 896 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 897 prefetch = ""; 898 else 899 prefetch = "non"; 900 printf("%s %sprefetchable memory\n", type, prefetch); 901 switch (PCI_MAPREG_MEM_TYPE(rval)) { 902 case PCI_MAPREG_MEM_TYPE_64BIT: 903 printf(" base: 0x%016llx, ", 904 PCI_MAPREG_MEM64_ADDR( 905 ((((long long) rval64h) << 32) | rval))); 906 #ifdef _KERNEL 907 if (sizebar) 908 printf("size: 0x%016llx", 909 PCI_MAPREG_MEM64_SIZE( 910 ((((long long) mask64h) << 32) | mask))); 911 else 912 #endif /* _KERNEL */ 913 printf("not sized"); 914 printf("\n"); 915 break; 916 case PCI_MAPREG_MEM_TYPE_32BIT: 917 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 918 default: 919 printf(" base: 0x%08x, ", 920 PCI_MAPREG_MEM_ADDR(rval)); 921 #ifdef _KERNEL 922 if (sizebar) 923 printf("size: 0x%08x", 924 PCI_MAPREG_MEM_SIZE(mask)); 925 else 926 #endif /* _KERNEL */ 927 printf("not sized"); 928 printf("\n"); 929 break; 930 } 931 } else { 932 #ifdef _KERNEL 933 if (sizebar) 934 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 935 #endif /* _KERNEL */ 936 printf("i/o\n"); 937 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 938 #ifdef _KERNEL 939 if (sizebar) 940 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 941 else 942 #endif /* _KERNEL */ 943 printf("not sized"); 944 printf("\n"); 945 } 946 947 return width; 948 } 949 950 static void 951 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 952 { 953 int off, needaddr, neednl; 954 955 needaddr = 1; 956 neednl = 0; 957 for (off = first; off < pastlast; off += 4) { 958 if ((off % 16) == 0 || needaddr) { 959 printf(" 0x%02x:", off); 960 needaddr = 0; 961 } 962 printf(" 0x%08x", regs[o2i(off)]); 963 neednl = 1; 964 if ((off % 16) == 12) { 965 printf("\n"); 966 neednl = 0; 967 } 968 } 969 if (neednl) 970 printf("\n"); 971 } 972 973 static void 974 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 975 { 976 pcireg_t rval; 977 978 printf("\n AGP Capabilities Register\n"); 979 980 rval = regs[o2i(capoff)]; 981 printf(" Revision: %d.%d\n", 982 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 983 984 /* XXX need more */ 985 } 986 987 static const char * 988 pci_conf_print_pcipm_cap_aux(uint16_t caps) 989 { 990 991 switch ((caps >> 6) & 7) { 992 case 0: return "self-powered"; 993 case 1: return "55 mA"; 994 case 2: return "100 mA"; 995 case 3: return "160 mA"; 996 case 4: return "220 mA"; 997 case 5: return "270 mA"; 998 case 6: return "320 mA"; 999 case 7: 1000 default: return "375 mA"; 1001 } 1002 } 1003 1004 static const char * 1005 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1006 { 1007 static const char unk[] = "unknown"; 1008 static const char *pmrev[8] = { 1009 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1010 }; 1011 if (val > 7) 1012 return unk; 1013 return pmrev[val]; 1014 } 1015 1016 static void 1017 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1018 { 1019 uint16_t caps, pmcsr; 1020 pcireg_t reg; 1021 1022 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1023 reg = regs[o2i(capoff + PCI_PMCSR)]; 1024 pmcsr = reg & 0xffff; 1025 1026 printf("\n PCI Power Management Capabilities Register\n"); 1027 1028 printf(" Capabilities register: 0x%04x\n", caps); 1029 printf(" Version: %s\n", 1030 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1031 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1032 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1033 printf(" 3.3V auxiliary current: %s\n", 1034 pci_conf_print_pcipm_cap_aux(caps)); 1035 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1036 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1037 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1038 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1039 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1040 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1041 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1042 1043 printf(" Control/status register: 0x%04x\n", pmcsr); 1044 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1045 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1046 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1047 printf(" PME# assertion: %sabled\n", 1048 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1049 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1050 printf(" Bridge Support Extensions register: 0x%02x\n", 1051 (reg >> 16) & 0xff); 1052 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1053 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1054 printf(" Data register: 0x%02x\n", (reg >> 24) & 0xff); 1055 1056 } 1057 1058 /* XXX pci_conf_print_vpd_cap */ 1059 /* XXX pci_conf_print_slotid_cap */ 1060 1061 static void 1062 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1063 { 1064 uint32_t ctl, mmc, mme; 1065 1066 regs += o2i(capoff); 1067 ctl = *regs++; 1068 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1069 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1070 1071 printf("\n PCI Message Signaled Interrupt\n"); 1072 1073 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1074 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1075 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1076 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1077 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1078 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1079 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1080 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1081 printf(" Message Address %sregister: 0x%08x\n", 1082 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1083 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1084 printf(" Message Address %sregister: 0x%08x\n", 1085 "(upper) ", *regs++); 1086 } 1087 printf(" Message Data register: 0x%08x\n", *regs++); 1088 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1089 printf(" Vector Mask register: 0x%08x\n", *regs++); 1090 printf(" Vector Pending register: 0x%08x\n", *regs++); 1091 } 1092 } 1093 1094 /* XXX pci_conf_print_cpci_hostwap_cap */ 1095 1096 /* 1097 * For both command register and status register. 1098 * The argument "idx" is index number (0 to 7). 1099 */ 1100 static int 1101 pcix_split_trans(unsigned int idx) 1102 { 1103 static int table[8] = { 1104 1, 2, 3, 4, 8, 12, 16, 32 1105 }; 1106 1107 if (idx >= __arraycount(table)) 1108 return -1; 1109 return table[idx]; 1110 } 1111 1112 static void 1113 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1114 { 1115 pcireg_t reg; 1116 int isbridge; 1117 int i; 1118 1119 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1120 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1121 printf("\n PCI-X %s Capabilities Register\n", 1122 isbridge ? "Bridge" : "Non-bridge"); 1123 1124 reg = regs[o2i(capoff)]; 1125 if (isbridge != 0) { 1126 printf(" Secondary status register: 0x%04x\n", 1127 (reg & 0xffff0000) >> 16); 1128 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1129 onoff("133MHz capable", reg, PCIX_STATUS_133); 1130 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1131 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1132 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1133 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1134 printf(" Secondary clock frequency: 0x%x\n", 1135 (reg & PCIX_BRIDGE_2NDST_CLKF) 1136 >> PCIX_BRIDGE_2NDST_CLKF_SHIFT); 1137 printf(" Version: 0x%x\n", 1138 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1139 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1140 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1141 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1142 } else { 1143 printf(" Command register: 0x%04x\n", 1144 (reg & 0xffff0000) >> 16); 1145 onoff("Data Parity Error Recovery", reg, 1146 PCIX_CMD_PERR_RECOVER); 1147 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1148 printf(" Maximum Burst Read Count: %u\n", 1149 PCIX_CMD_BYTECNT(reg)); 1150 printf(" Maximum Split Transactions: %d\n", 1151 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1152 >> PCIX_CMD_SPLTRANS_SHIFT)); 1153 } 1154 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1155 printf(" %sStatus register: 0x%08x\n", 1156 isbridge ? "Bridge " : "", reg); 1157 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1158 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1159 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1160 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1161 onoff("133MHz capable", reg, PCIX_STATUS_133); 1162 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1163 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1164 if (isbridge != 0) { 1165 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1166 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1167 } else { 1168 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1169 "bridge device", "simple device"); 1170 printf(" Designed max memory read byte count: %d\n", 1171 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1172 >> PCIX_STATUS_MAXB_SHIFT)); 1173 printf(" Designed max outstanding split transaction: %d\n", 1174 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1175 >> PCIX_STATUS_MAXST_SHIFT)); 1176 printf(" MAX cumulative Read Size: %u\n", 1177 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1178 onoff("Received split completion error", reg, 1179 PCIX_STATUS_SCERR); 1180 } 1181 onoff("266MHz capable", reg, PCIX_STATUS_266); 1182 onoff("533MHz capable", reg, PCIX_STATUS_533); 1183 1184 if (isbridge == 0) 1185 return; 1186 1187 /* Only for bridge */ 1188 for (i = 0; i < 2; i++) { 1189 reg = regs[o2i(capoff+PCIX_BRIDGE_UP_STCR + (4 * i))]; 1190 printf(" %s split transaction control register: 0x%08x\n", 1191 (i == 0) ? "Upstream" : "Downstream", reg); 1192 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1193 printf(" Commitment Limit: %d\n", 1194 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1195 } 1196 } 1197 1198 /* XXX pci_conf_print_ldt_cap */ 1199 1200 static void 1201 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1202 { 1203 uint16_t caps; 1204 1205 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1206 1207 printf("\n PCI Vendor Specific Capabilities Register\n"); 1208 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1209 } 1210 1211 static void 1212 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1213 { 1214 pcireg_t val; 1215 1216 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1217 1218 printf("\n Debugport Capability Register\n"); 1219 printf(" Debug base Register: 0x%04x\n", 1220 val >> PCI_DEBUG_BASER_SHIFT); 1221 printf(" port offset: 0x%04x\n", 1222 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1223 printf(" BAR number: %u\n", 1224 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1225 } 1226 1227 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1228 /* XXX pci_conf_print_hotplug_cap */ 1229 1230 static void 1231 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1232 { 1233 pcireg_t reg; 1234 1235 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1236 1237 printf("\n Subsystem ID Capability Register\n"); 1238 printf(" Subsystem ID : 0x%08x\n", reg); 1239 } 1240 1241 /* XXX pci_conf_print_agp8_cap */ 1242 /* XXX pci_conf_print_secure_cap */ 1243 1244 static void 1245 pci_print_pcie_L0s_latency(uint32_t val) 1246 { 1247 1248 switch (val) { 1249 case 0x0: 1250 printf("Less than 64ns\n"); 1251 break; 1252 case 0x1: 1253 case 0x2: 1254 case 0x3: 1255 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1256 break; 1257 case 0x4: 1258 printf("512ns to less than 1us\n"); 1259 break; 1260 case 0x5: 1261 printf("1us to less than 2us\n"); 1262 break; 1263 case 0x6: 1264 printf("2us - 4us\n"); 1265 break; 1266 case 0x7: 1267 printf("More than 4us\n"); 1268 break; 1269 } 1270 } 1271 1272 static void 1273 pci_print_pcie_L1_latency(uint32_t val) 1274 { 1275 1276 switch (val) { 1277 case 0x0: 1278 printf("Less than 1us\n"); 1279 break; 1280 case 0x6: 1281 printf("32us - 64us\n"); 1282 break; 1283 case 0x7: 1284 printf("More than 64us\n"); 1285 break; 1286 default: 1287 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1288 break; 1289 } 1290 } 1291 1292 static void 1293 pci_print_pcie_compl_timeout(uint32_t val) 1294 { 1295 1296 switch (val) { 1297 case 0x0: 1298 printf("50us to 50ms\n"); 1299 break; 1300 case 0x5: 1301 printf("16ms to 55ms\n"); 1302 break; 1303 case 0x6: 1304 printf("65ms to 210ms\n"); 1305 break; 1306 case 0x9: 1307 printf("260ms to 900ms\n"); 1308 break; 1309 case 0xa: 1310 printf("1s to 3.5s\n"); 1311 break; 1312 default: 1313 printf("unknown %u value\n", val); 1314 break; 1315 } 1316 } 1317 1318 static void 1319 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1320 { 1321 pcireg_t reg; /* for each register */ 1322 pcireg_t val; /* for each bitfield */ 1323 bool check_link = false; 1324 bool check_slot = false; 1325 bool check_rootport = false; 1326 unsigned int pciever; 1327 static const char * const linkspeeds[] = {"2.5", "5.0", "8.0"}; 1328 int i; 1329 1330 printf("\n PCI Express Capabilities Register\n"); 1331 /* Capability Register */ 1332 reg = regs[o2i(capoff)]; 1333 printf(" Capability register: %04x\n", reg >> 16); 1334 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1335 printf(" Capability version: %u\n", pciever); 1336 printf(" Device type: "); 1337 switch ((reg & 0x00f00000) >> 20) { 1338 case 0x0: 1339 printf("PCI Express Endpoint device\n"); 1340 check_link = true; 1341 break; 1342 case 0x1: 1343 printf("Legacy PCI Express Endpoint device\n"); 1344 check_link = true; 1345 break; 1346 case 0x4: 1347 printf("Root Port of PCI Express Root Complex\n"); 1348 check_link = true; 1349 check_slot = true; 1350 check_rootport = true; 1351 break; 1352 case 0x5: 1353 printf("Upstream Port of PCI Express Switch\n"); 1354 break; 1355 case 0x6: 1356 printf("Downstream Port of PCI Express Switch\n"); 1357 check_slot = true; 1358 check_rootport = true; 1359 break; 1360 case 0x7: 1361 printf("PCI Express to PCI/PCI-X Bridge\n"); 1362 break; 1363 case 0x8: 1364 printf("PCI/PCI-X to PCI Express Bridge\n"); 1365 break; 1366 case 0x9: 1367 printf("Root Complex Integrated Endpoint\n"); 1368 break; 1369 case 0xa: 1370 check_rootport = true; 1371 printf("Root Complex Event Collector\n"); 1372 break; 1373 default: 1374 printf("unknown\n"); 1375 break; 1376 } 1377 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1378 printf(" Interrupt Message Number: %x\n", 1379 (unsigned int)((reg & PCIE_XCAP_IRQ) >> 27)); 1380 1381 /* Device Capability Register */ 1382 reg = regs[o2i(capoff + PCIE_DCAP)]; 1383 printf(" Device Capabilities Register: 0x%08x\n", reg); 1384 printf(" Max Payload Size Supported: %u bytes max\n", 1385 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1386 printf(" Phantom Functions Supported: "); 1387 switch ((reg & PCIE_DCAP_PHANTOM_FUNCS) >> 3) { 1388 case 0x0: 1389 printf("not available\n"); 1390 break; 1391 case 0x1: 1392 printf("MSB\n"); 1393 break; 1394 case 0x2: 1395 printf("two MSB\n"); 1396 break; 1397 case 0x3: 1398 printf("All three bits\n"); 1399 break; 1400 } 1401 printf(" Extended Tag Field Supported: %dbit\n", 1402 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1403 printf(" Endpoint L0 Acceptable Latency: "); 1404 pci_print_pcie_L0s_latency((reg & PCIE_DCAP_L0S_LATENCY) >> 6); 1405 printf(" Endpoint L1 Acceptable Latency: "); 1406 pci_print_pcie_L1_latency((reg & PCIE_DCAP_L1_LATENCY) >> 9); 1407 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1408 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1409 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1410 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1411 printf(" Captured Slot Power Limit Value: %d\n", 1412 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18); 1413 printf(" Captured Slot Power Limit Scale: %d\n", 1414 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26); 1415 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1416 1417 /* Device Control Register */ 1418 reg = regs[o2i(capoff + PCIE_DCSR)]; 1419 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1420 onoff("Correctable Error Reporting Enable", reg, 1421 PCIE_DCSR_ENA_COR_ERR); 1422 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1423 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1424 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1425 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1426 printf(" Max Payload Size: %d byte\n", 1427 128 << (((unsigned int)(reg & PCIE_DCSR_MAX_PAYLOAD) >> 5))); 1428 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1429 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1430 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1431 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1432 printf(" Max Read Request Size: %d byte\n", 1433 128 << ((unsigned int)(reg & PCIE_DCSR_MAX_READ_REQ) >> 12)); 1434 1435 /* Device Status Register */ 1436 reg = regs[o2i(capoff + PCIE_DCSR)]; 1437 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1438 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1439 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1440 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1441 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1442 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1443 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1444 1445 if (check_link) { 1446 /* Link Capability Register */ 1447 reg = regs[o2i(capoff + PCIE_LCAP)]; 1448 printf(" Link Capabilities Register: 0x%08x\n", reg); 1449 printf(" Maximum Link Speed: "); 1450 val = reg & PCIE_LCAP_MAX_SPEED; 1451 if (val < 1 || val > 3) { 1452 printf("unknown %u value\n", val); 1453 } else { 1454 printf("%sGT/s\n", linkspeeds[val - 1]); 1455 } 1456 printf(" Maximum Link Width: x%u lanes\n", 1457 (unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4); 1458 printf(" Active State PM Support: "); 1459 val = (reg & PCIE_LCAP_ASPM) >> 10; 1460 switch (val) { 1461 case 0x1: 1462 printf("L0s Entry supported\n"); 1463 break; 1464 case 0x3: 1465 printf("L0s and L1 supported\n"); 1466 break; 1467 default: 1468 printf("Reserved value\n"); 1469 break; 1470 } 1471 printf(" L0 Exit Latency: "); 1472 pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12); 1473 printf(" L1 Exit Latency: "); 1474 pci_print_pcie_L1_latency((reg & PCIE_LCAP_L1_EXIT) >> 15); 1475 printf(" Port Number: %u\n", reg >> 24); 1476 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1477 onoff("Surprise Down Error Report", reg, 1478 PCIE_LCAP_SURPRISE_DOWN); 1479 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1480 onoff("Link BW Notification Capable", reg, 1481 PCIE_LCAP_LINK_BW_NOTIFY); 1482 onoff("ASPM Optionally Compliance", reg, 1483 PCIE_LCAP_ASPM_COMPLIANCE); 1484 1485 /* Link Control Register */ 1486 reg = regs[o2i(capoff + PCIE_LCSR)]; 1487 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1488 printf(" Active State PM Control: "); 1489 val = reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S); 1490 switch (val) { 1491 case 0: 1492 printf("disabled\n"); 1493 break; 1494 case 1: 1495 printf("L0s Entry Enabled\n"); 1496 break; 1497 case 2: 1498 printf("L1 Entry Enabled\n"); 1499 break; 1500 case 3: 1501 printf("L0s and L1 Entry Enabled\n"); 1502 break; 1503 } 1504 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1505 "128bytes", "64bytes"); 1506 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1507 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1508 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1509 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1510 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1511 onoff("Hardware Autonomous Width Disable", reg, 1512 PCIE_LCSR_HAWD); 1513 onoff("Link Bandwidth Management Interrupt Enable", reg, 1514 PCIE_LCSR_LBMIE); 1515 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1516 PCIE_LCSR_LABIE); 1517 1518 /* Link Status Register */ 1519 reg = regs[o2i(capoff + PCIE_LCSR)]; 1520 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1521 printf(" Negotiated Link Speed: "); 1522 if (((reg >> 16) & 0x000f) < 1 || 1523 ((reg >> 16) & 0x000f) > 3) { 1524 printf("unknown %u value\n", 1525 (unsigned int)(reg & PCIE_LCSR_LINKSPEED) >> 16); 1526 } else { 1527 printf("%sGT/s\n", 1528 linkspeeds[((reg & PCIE_LCSR_LINKSPEED) >> 16)-1]); 1529 } 1530 printf(" Negotiated Link Width: x%u lanes\n", 1531 (reg >> 20) & 0x003f); 1532 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1533 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1534 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1535 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1536 onoff("Link Bandwidth Management Status", reg, 1537 PCIE_LCSR_LINK_BW_MGMT); 1538 onoff("Link Autonomous Bandwidth Status", reg, 1539 PCIE_LCSR_LINK_AUTO_BW); 1540 } 1541 1542 if (check_slot == true) { 1543 /* Slot Capability Register */ 1544 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1545 printf(" Slot Capability Register: %08x\n", reg); 1546 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1547 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1548 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1549 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1550 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1551 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1552 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1553 printf(" Slot Power Limit Value: %d\n", 1554 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1555 printf(" Slot Power Limit Scale: %d\n", 1556 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1557 onoff("Electromechanical Interlock Present", reg, 1558 PCIE_SLCAP_EIP); 1559 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1560 printf(" Physical Slot Number: %d\n", 1561 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1562 1563 /* Slot Control Register */ 1564 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1565 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1566 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1567 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1568 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1569 onoff("Presense Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1570 onoff("Command Completed Interrupt Enabled", reg, 1571 PCIE_SLCSR_CCE); 1572 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1573 printf(" Attention Indicator Control: "); 1574 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1575 case 0x0: 1576 printf("reserved\n"); 1577 break; 1578 case 0x1: 1579 printf("on\n"); 1580 break; 1581 case 0x2: 1582 printf("blink\n"); 1583 break; 1584 case 0x3: 1585 printf("off\n"); 1586 break; 1587 } 1588 printf(" Power Indicator Control: "); 1589 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1590 case 0x0: 1591 printf("reserved\n"); 1592 break; 1593 case 0x1: 1594 printf("on\n"); 1595 break; 1596 case 0x2: 1597 printf("blink\n"); 1598 break; 1599 case 0x3: 1600 printf("off\n"); 1601 break; 1602 } 1603 onoff("Power Controller Control", reg, PCIE_SLCSR_PCC); 1604 onoff("Electromechanical Interlock Control", 1605 reg, PCIE_SLCSR_EIC); 1606 onoff("Data Link Layer State Changed Enable", reg, 1607 PCIE_SLCSR_DLLSCE); 1608 1609 /* Slot Status Register */ 1610 printf(" Slot Status Register: %04x\n", reg >> 16); 1611 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1612 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1613 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1614 onoff("Presense Detect Changed", reg, PCIE_SLCSR_PDC); 1615 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1616 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1617 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1618 onoff("Electromechanical Interlock engaged", reg, 1619 PCIE_SLCSR_EIS); 1620 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 1621 } 1622 1623 if (check_rootport == true) { 1624 /* Root Control Register */ 1625 reg = regs[o2i(capoff + PCIE_RCR)]; 1626 printf(" Root Control Register: %04x\n", reg & 0xffff); 1627 onoff("SERR on Correctable Error Enable", reg, 1628 PCIE_RCR_SERR_CER); 1629 onoff("SERR on Non-Fatal Error Enable", reg, 1630 PCIE_RCR_SERR_NFER); 1631 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 1632 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 1633 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 1634 1635 /* Root Capability Register */ 1636 printf(" Root Capability Register: %04x\n", 1637 reg >> 16); 1638 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 1639 1640 /* Root Status Register */ 1641 reg = regs[o2i(capoff + PCIE_RSR)]; 1642 printf(" Root Status Register: %08x\n", reg); 1643 printf(" PME Requester ID: %04x\n", 1644 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1645 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 1646 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 1647 } 1648 1649 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1650 if (pciever < 2) 1651 return; 1652 1653 /* Device Capabilities 2 */ 1654 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1655 printf(" Device Capabilities 2: 0x%08x\n", reg); 1656 printf(" Completion Timeout Ranges Supported: %u \n", 1657 (unsigned int)(reg & PCIE_DCAP2_COMPT_RANGE)); 1658 onoff("Completion Timeout Disable Supported", reg, 1659 PCIE_DCAP2_COMPT_DIS); 1660 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 1661 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 1662 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 1663 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 1664 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 1665 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 1666 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 1667 printf(" TPH Completer Supported: %u\n", 1668 (unsigned int)(reg & PCIE_DCAP2_TPH_COMP) >> 12); 1669 printf(" OBFF Supported: "); 1670 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 1671 case 0x0: 1672 printf("Not supported\n"); 1673 break; 1674 case 0x1: 1675 printf("Message only\n"); 1676 break; 1677 case 0x2: 1678 printf("WAKE# only\n"); 1679 break; 1680 case 0x3: 1681 printf("Both\n"); 1682 break; 1683 } 1684 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 1685 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 1686 printf(" Max End-End TLP Prefixes: %u\n", 1687 (unsigned int)(reg & PCIE_DCAP2_MAX_EETLP) >> 22); 1688 1689 /* Device Control 2 */ 1690 reg = regs[o2i(capoff + PCIE_DCSR2)]; 1691 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 1692 printf(" Completion Timeout Value: "); 1693 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 1694 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 1695 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 1696 onoff("AtomicOp Rquester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 1697 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 1698 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 1699 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 1700 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 1701 printf(" OBFF: "); 1702 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 1703 case 0x0: 1704 printf("Disabled\n"); 1705 break; 1706 case 0x1: 1707 printf("Enabled with Message Signaling Variation A\n"); 1708 break; 1709 case 0x2: 1710 printf("Enabled with Message Signaling Variation B\n"); 1711 break; 1712 case 0x3: 1713 printf("Enabled using WAKE# signaling\n"); 1714 break; 1715 } 1716 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 1717 1718 if (check_link) { 1719 /* Link Capability 2 */ 1720 reg = regs[o2i(capoff + PCIE_LCAP2)]; 1721 printf(" Link Capabilities 2: 0x%08x\n", reg); 1722 val = (reg & PCIE_LCAP2_SUP_LNKSV) >> 1; 1723 printf(" Supported Link Speed Vector:"); 1724 for (i = 0; i <= 2; i++) { 1725 if (((val >> i) & 0x01) != 0) 1726 printf(" %sGT/s", linkspeeds[i]); 1727 } 1728 printf("\n"); 1729 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 1730 1731 /* Link Control 2 */ 1732 reg = regs[o2i(capoff + PCIE_LCSR2)]; 1733 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 1734 printf(" Target Link Speed: "); 1735 val = reg & PCIE_LCSR2_TGT_LSPEED; 1736 if (val < 1 || val > 3) 1737 printf("unknown %u value\n", val); 1738 else 1739 printf("%sGT/s\n", linkspeeds[val - 1]); 1740 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 1741 onoff("HW Autonomous Speed Disabled", reg, 1742 PCIE_LCSR2_HW_AS_DIS); 1743 onoff("Selectable De-emphasis", reg, PCIE_LCSR2_SEL_DEEMP); 1744 printf(" Transmit Margin: %u\n", 1745 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 1746 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 1747 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 1748 printf(" Compliance Present/De-emphasis: %u\n", 1749 (unsigned int)(reg & PCIE_LCSR2_COMP_DEEMP) >> 12); 1750 1751 /* Link Status 2 */ 1752 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 1753 onoff("Current De-emphasis Level", reg, PCIE_LCSR2_DEEMP_LVL); 1754 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 1755 onoff("Equalization Phase 1 Successful", reg, 1756 PCIE_LCSR2_EQP1_SUC); 1757 onoff("Equalization Phase 2 Successful", reg, 1758 PCIE_LCSR2_EQP2_SUC); 1759 onoff("Equalization Phase 3 Successful", reg, 1760 PCIE_LCSR2_EQP3_SUC); 1761 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 1762 } 1763 1764 /* Slot Capability 2 */ 1765 /* Slot Control 2 */ 1766 /* Slot Status 2 */ 1767 } 1768 1769 static void 1770 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 1771 { 1772 pcireg_t reg; 1773 1774 printf("\n MSI-X Capability Register\n"); 1775 1776 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 1777 printf(" Message Control register: 0x%04x\n", 1778 (reg >> 16) & 0xff); 1779 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 1780 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 1781 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 1782 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 1783 printf(" Table offset register: 0x%08x\n", reg); 1784 printf(" Table offset: %08x\n", reg & PCI_MSIX_TBLOFFSET_MASK); 1785 printf(" BIR: 0x%x\n", reg & PCI_MSIX_TBLBIR_MASK); 1786 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 1787 printf(" Pending bit array register: 0x%08x\n", reg); 1788 printf(" Pending bit array offset: %08x\n", 1789 reg & PCI_MSIX_PBAOFFSET_MASK); 1790 printf(" BIR: 0x%x\n", reg & PCI_MSIX_PBABIR_MASK); 1791 } 1792 1793 /* XXX pci_conf_print_sata_cap */ 1794 static void 1795 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 1796 { 1797 pcireg_t reg; 1798 1799 printf("\n Advanced Features Capability Register\n"); 1800 1801 reg = regs[o2i(capoff + PCI_AFCAPR)]; 1802 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 1803 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 1804 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 1805 reg = regs[o2i(capoff + PCI_AFCSR)]; 1806 printf(" AF Control register: 0x%02x\n", reg & 0xff); 1807 /* 1808 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 1809 * and it's always 0 on read 1810 */ 1811 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 1812 onoff("Transaction Pending", reg, PCI_AFSR_TP); 1813 } 1814 1815 static struct { 1816 pcireg_t cap; 1817 const char *name; 1818 void (*printfunc)(const pcireg_t *, int); 1819 } pci_captab[] = { 1820 { PCI_CAP_RESERVED0, "reserved", NULL }, 1821 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 1822 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 1823 { PCI_CAP_VPD, "VPD", NULL }, 1824 { PCI_CAP_SLOTID, "SlotID", NULL }, 1825 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 1826 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 1827 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 1828 { PCI_CAP_LDT, "HyperTransport", NULL }, 1829 { PCI_CAP_VENDSPEC, "Vendor-specific", 1830 pci_conf_print_vendspec_cap }, 1831 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 1832 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 1833 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 1834 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 1835 pci_conf_print_subsystem_cap }, 1836 { PCI_CAP_AGP8, "AGP 8x", NULL }, 1837 { PCI_CAP_SECURE, "Secure Device", NULL }, 1838 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 1839 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 1840 { PCI_CAP_SATA, "SATA", NULL }, 1841 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap } 1842 }; 1843 1844 static void 1845 pci_conf_print_caplist( 1846 #ifdef _KERNEL 1847 pci_chipset_tag_t pc, pcitag_t tag, 1848 #endif 1849 const pcireg_t *regs, int capoff) 1850 { 1851 int off; 1852 pcireg_t foundcap; 1853 pcireg_t rval; 1854 bool foundtable[__arraycount(pci_captab)]; 1855 unsigned int i; 1856 1857 /* Clear table */ 1858 for (i = 0; i < __arraycount(pci_captab); i++) 1859 foundtable[i] = false; 1860 1861 /* Print capability register's offset and the type first */ 1862 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1863 off != 0; 1864 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 1865 rval = regs[o2i(off)]; 1866 printf(" Capability register at 0x%02x\n", off); 1867 1868 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 1869 foundcap = PCI_CAPLIST_CAP(rval); 1870 if (foundcap < __arraycount(pci_captab)) { 1871 printf("%s)\n", pci_captab[foundcap].name); 1872 /* Mark as found */ 1873 foundtable[foundcap] = true; 1874 } else 1875 printf("unknown)\n"); 1876 } 1877 1878 /* 1879 * And then, print the detail of each capability registers 1880 * in capability value's order. 1881 */ 1882 for (i = 0; i < __arraycount(pci_captab); i++) { 1883 if (foundtable[i] == false) 1884 continue; 1885 1886 /* 1887 * The type was found. Search capability list again and 1888 * print all capabilities that the capabiliy type is 1889 * the same. This is required because some capabilities 1890 * appear multiple times (e.g. HyperTransport capability). 1891 */ 1892 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1893 off != 0; 1894 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 1895 rval = regs[o2i(off)]; 1896 foundcap = PCI_CAPLIST_CAP(rval); 1897 if ((i == foundcap) 1898 && (pci_captab[foundcap].printfunc != NULL)) 1899 pci_captab[foundcap].printfunc(regs, off); 1900 } 1901 } 1902 } 1903 1904 /* Print the Secondary Status Register. */ 1905 static void 1906 pci_conf_print_ssr(pcireg_t rval) 1907 { 1908 pcireg_t devsel; 1909 1910 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 1911 onoff("66 MHz capable", rval, __BIT(5)); 1912 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 1913 onoff("Fast back-to-back capable", rval, __BIT(7)); 1914 onoff("Data parity error detected", rval, __BIT(8)); 1915 1916 printf(" DEVSEL timing: "); 1917 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 1918 switch (devsel) { 1919 case 0: 1920 printf("fast"); 1921 break; 1922 case 1: 1923 printf("medium"); 1924 break; 1925 case 2: 1926 printf("slow"); 1927 break; 1928 default: 1929 printf("unknown/reserved"); /* XXX */ 1930 break; 1931 } 1932 printf(" (0x%x)\n", devsel); 1933 1934 onoff("Signalled target abort", rval, __BIT(11)); 1935 onoff("Received target abort", rval, __BIT(12)); 1936 onoff("Received master abort", rval, __BIT(13)); 1937 onoff("Received system error", rval, __BIT(14)); 1938 onoff("Detected parity error", rval, __BIT(15)); 1939 } 1940 1941 static void 1942 pci_conf_print_type0( 1943 #ifdef _KERNEL 1944 pci_chipset_tag_t pc, pcitag_t tag, 1945 #endif 1946 const pcireg_t *regs 1947 #ifdef _KERNEL 1948 , int sizebars 1949 #endif 1950 ) 1951 { 1952 int off, width; 1953 pcireg_t rval; 1954 1955 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 1956 #ifdef _KERNEL 1957 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 1958 #else 1959 width = pci_conf_print_bar(regs, off, NULL); 1960 #endif 1961 } 1962 1963 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 1964 1965 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 1966 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1967 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1968 1969 /* XXX */ 1970 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 1971 1972 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1973 printf(" Capability list pointer: 0x%02x\n", 1974 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 1975 else 1976 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 1977 1978 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 1979 1980 rval = regs[o2i(PCI_INTERRUPT_REG)]; 1981 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 1982 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 1983 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 1984 switch (PCI_INTERRUPT_PIN(rval)) { 1985 case PCI_INTERRUPT_PIN_NONE: 1986 printf("(none)"); 1987 break; 1988 case PCI_INTERRUPT_PIN_A: 1989 printf("(pin A)"); 1990 break; 1991 case PCI_INTERRUPT_PIN_B: 1992 printf("(pin B)"); 1993 break; 1994 case PCI_INTERRUPT_PIN_C: 1995 printf("(pin C)"); 1996 break; 1997 case PCI_INTERRUPT_PIN_D: 1998 printf("(pin D)"); 1999 break; 2000 default: 2001 printf("(? ? ?)"); 2002 break; 2003 } 2004 printf("\n"); 2005 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 2006 } 2007 2008 static void 2009 pci_conf_print_type1( 2010 #ifdef _KERNEL 2011 pci_chipset_tag_t pc, pcitag_t tag, 2012 #endif 2013 const pcireg_t *regs 2014 #ifdef _KERNEL 2015 , int sizebars 2016 #endif 2017 ) 2018 { 2019 int off, width; 2020 pcireg_t rval; 2021 uint32_t base, limit; 2022 uint32_t base_h, limit_h; 2023 uint64_t pbase, plimit; 2024 int use_upper; 2025 2026 /* 2027 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 2028 * Bridge chip documentation, and may not be correct with 2029 * respect to various standards. (XXX) 2030 */ 2031 2032 for (off = 0x10; off < 0x18; off += width) { 2033 #ifdef _KERNEL 2034 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 2035 #else 2036 width = pci_conf_print_bar(regs, off, NULL); 2037 #endif 2038 } 2039 2040 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 2041 printf(" Primary bus number: 0x%02x\n", 2042 PCI_BRIDGE_BUS_PRIMARY(rval)); 2043 printf(" Secondary bus number: 0x%02x\n", 2044 PCI_BRIDGE_BUS_SECONDARY(rval)); 2045 printf(" Subordinate bus number: 0x%02x\n", 2046 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 2047 printf(" Secondary bus latency timer: 0x%02x\n", 2048 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 2049 2050 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 2051 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 2052 2053 /* I/O region */ 2054 printf(" I/O region:\n"); 2055 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 2056 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 2057 if (PCI_BRIDGE_IO_32BITS(rval)) 2058 use_upper = 1; 2059 else 2060 use_upper = 0; 2061 onoff("32bit I/O", rval, use_upper); 2062 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 2063 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 2064 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 2065 limit |= 0x00000fff; 2066 2067 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 2068 base_h = (rval >> 0) & 0xffff; 2069 limit_h = (rval >> 16) & 0xffff; 2070 printf(" base upper 16 bits register: 0x%04x\n", base_h); 2071 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 2072 2073 if (use_upper == 1) { 2074 base |= base_h << 16; 2075 limit |= limit_h << 16; 2076 } 2077 if (base < limit) { 2078 if (use_upper == 1) 2079 printf(" range: 0x%08x-0x%08x\n", base, limit); 2080 else 2081 printf(" range: 0x%04x-0x%04x\n", base, limit); 2082 } else 2083 printf(" range: not set\n"); 2084 2085 /* Non-prefetchable memory region */ 2086 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 2087 printf(" Memory region:\n"); 2088 printf(" base register: 0x%04x\n", 2089 (rval >> 0) & 0xffff); 2090 printf(" limit register: 0x%04x\n", 2091 (rval >> 16) & 0xffff); 2092 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 2093 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 2094 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 2095 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 2096 if (base < limit) 2097 printf(" range: 0x%08x-0x%08x\n", base, limit); 2098 else 2099 printf(" range: not set\n"); 2100 2101 /* Prefetchable memory region */ 2102 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 2103 printf(" Prefetchable memory region:\n"); 2104 printf(" base register: 0x%04x\n", 2105 (rval >> 0) & 0xffff); 2106 printf(" limit register: 0x%04x\n", 2107 (rval >> 16) & 0xffff); 2108 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 2109 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 2110 printf(" base upper 32 bits register: 0x%08x\n", 2111 base_h); 2112 printf(" limit upper 32 bits register: 0x%08x\n", 2113 limit_h); 2114 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 2115 use_upper = 1; 2116 else 2117 use_upper = 0; 2118 onoff("64bit memory address", rval, use_upper); 2119 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 2120 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 2121 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 2122 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 2123 if (use_upper == 1) { 2124 pbase |= (uint64_t)base_h << 32; 2125 plimit |= (uint64_t)limit_h << 32; 2126 } 2127 if (pbase < plimit) { 2128 if (use_upper == 1) 2129 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 2130 "\n", pbase, plimit); 2131 else 2132 printf(" range: 0x%08x-0x%08x\n", 2133 (uint32_t)pbase, (uint32_t)plimit); 2134 } else 2135 printf(" range: not set\n"); 2136 2137 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2138 printf(" Capability list pointer: 0x%02x\n", 2139 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 2140 else 2141 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 2142 2143 /* XXX */ 2144 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 2145 2146 rval = regs[o2i(PCI_INTERRUPT_REG)]; 2147 printf(" Interrupt line: 0x%02x\n", 2148 (rval >> 0) & 0xff); 2149 printf(" Interrupt pin: 0x%02x ", 2150 (rval >> 8) & 0xff); 2151 switch ((rval >> 8) & 0xff) { 2152 case PCI_INTERRUPT_PIN_NONE: 2153 printf("(none)"); 2154 break; 2155 case PCI_INTERRUPT_PIN_A: 2156 printf("(pin A)"); 2157 break; 2158 case PCI_INTERRUPT_PIN_B: 2159 printf("(pin B)"); 2160 break; 2161 case PCI_INTERRUPT_PIN_C: 2162 printf("(pin C)"); 2163 break; 2164 case PCI_INTERRUPT_PIN_D: 2165 printf("(pin D)"); 2166 break; 2167 default: 2168 printf("(? ? ?)"); 2169 break; 2170 } 2171 printf("\n"); 2172 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 2173 & PCI_BRIDGE_CONTROL_MASK; 2174 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 2175 onoff("Parity error response", rval, 0x0001); 2176 onoff("Secondary SERR forwarding", rval, 0x0002); 2177 onoff("ISA enable", rval, 0x0004); 2178 onoff("VGA enable", rval, 0x0008); 2179 onoff("Master abort reporting", rval, 0x0020); 2180 onoff("Secondary bus reset", rval, 0x0040); 2181 onoff("Fast back-to-back capable", rval, 0x0080); 2182 } 2183 2184 static void 2185 pci_conf_print_type2( 2186 #ifdef _KERNEL 2187 pci_chipset_tag_t pc, pcitag_t tag, 2188 #endif 2189 const pcireg_t *regs 2190 #ifdef _KERNEL 2191 , int sizebars 2192 #endif 2193 ) 2194 { 2195 pcireg_t rval; 2196 2197 /* 2198 * XXX these need to be printed in more detail, need to be 2199 * XXX checked against specs/docs, etc. 2200 * 2201 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 2202 * controller chip documentation, and may not be correct with 2203 * respect to various standards. (XXX) 2204 */ 2205 2206 #ifdef _KERNEL 2207 pci_conf_print_bar(pc, tag, regs, 0x10, 2208 "CardBus socket/ExCA registers", sizebars); 2209 #else 2210 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 2211 #endif 2212 2213 /* Capability list pointer and secondary status register */ 2214 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 2215 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2216 printf(" Capability list pointer: 0x%02x\n", 2217 PCI_CAPLIST_PTR(rval)); 2218 else 2219 printf(" Reserved @ 0x14: 0x%04" PRIxMAX "\n", 2220 __SHIFTOUT(rval, __BITS(15, 0))); 2221 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 2222 2223 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 2224 printf(" PCI bus number: 0x%02x\n", 2225 (rval >> 0) & 0xff); 2226 printf(" CardBus bus number: 0x%02x\n", 2227 (rval >> 8) & 0xff); 2228 printf(" Subordinate bus number: 0x%02x\n", 2229 (rval >> 16) & 0xff); 2230 printf(" CardBus latency timer: 0x%02x\n", 2231 (rval >> 24) & 0xff); 2232 2233 /* XXX Print more prettily */ 2234 printf(" CardBus memory region 0:\n"); 2235 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 2236 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 2237 printf(" CardBus memory region 1:\n"); 2238 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 2239 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 2240 printf(" CardBus I/O region 0:\n"); 2241 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 2242 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 2243 printf(" CardBus I/O region 1:\n"); 2244 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 2245 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 2246 2247 rval = regs[o2i(PCI_INTERRUPT_REG)]; 2248 printf(" Interrupt line: 0x%02x\n", 2249 (rval >> 0) & 0xff); 2250 printf(" Interrupt pin: 0x%02x ", 2251 (rval >> 8) & 0xff); 2252 switch ((rval >> 8) & 0xff) { 2253 case PCI_INTERRUPT_PIN_NONE: 2254 printf("(none)"); 2255 break; 2256 case PCI_INTERRUPT_PIN_A: 2257 printf("(pin A)"); 2258 break; 2259 case PCI_INTERRUPT_PIN_B: 2260 printf("(pin B)"); 2261 break; 2262 case PCI_INTERRUPT_PIN_C: 2263 printf("(pin C)"); 2264 break; 2265 case PCI_INTERRUPT_PIN_D: 2266 printf("(pin D)"); 2267 break; 2268 default: 2269 printf("(? ? ?)"); 2270 break; 2271 } 2272 printf("\n"); 2273 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 2274 printf(" Bridge control register: 0x%04x\n", rval); 2275 onoff("Parity error response", rval, __BIT(0)); 2276 onoff("SERR# enable", rval, __BIT(1)); 2277 onoff("ISA enable", rval, __BIT(2)); 2278 onoff("VGA enable", rval, __BIT(3)); 2279 onoff("Master abort mode", rval, __BIT(5)); 2280 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 2281 onoff("Functional interrupts routed by ExCA registers", rval, 2282 __BIT(7)); 2283 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 2284 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 2285 onoff("Write posting enable", rval, __BIT(10)); 2286 2287 rval = regs[o2i(0x40)]; 2288 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 2289 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 2290 2291 #ifdef _KERNEL 2292 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 2293 sizebars); 2294 #else 2295 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 2296 #endif 2297 } 2298 2299 void 2300 pci_conf_print( 2301 #ifdef _KERNEL 2302 pci_chipset_tag_t pc, pcitag_t tag, 2303 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 2304 #else 2305 int pcifd, u_int bus, u_int dev, u_int func 2306 #endif 2307 ) 2308 { 2309 pcireg_t regs[o2i(256)]; 2310 int off, capoff, endoff, hdrtype; 2311 const char *type_name; 2312 #ifdef _KERNEL 2313 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, 2314 int); 2315 int sizebars; 2316 #else 2317 void (*type_printfn)(const pcireg_t *); 2318 #endif 2319 2320 printf("PCI configuration registers:\n"); 2321 2322 for (off = 0; off < 256; off += 4) { 2323 #ifdef _KERNEL 2324 regs[o2i(off)] = pci_conf_read(pc, tag, off); 2325 #else 2326 if (pcibus_conf_read(pcifd, bus, dev, func, off, 2327 ®s[o2i(off)]) == -1) 2328 regs[o2i(off)] = 0; 2329 #endif 2330 } 2331 2332 #ifdef _KERNEL 2333 sizebars = 1; 2334 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 2335 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 2336 sizebars = 0; 2337 #endif 2338 2339 /* common header */ 2340 printf(" Common header:\n"); 2341 pci_conf_print_regs(regs, 0, 16); 2342 2343 printf("\n"); 2344 #ifdef _KERNEL 2345 pci_conf_print_common(pc, tag, regs); 2346 #else 2347 pci_conf_print_common(regs); 2348 #endif 2349 printf("\n"); 2350 2351 /* type-dependent header */ 2352 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 2353 switch (hdrtype) { /* XXX make a table, eventually */ 2354 case 0: 2355 /* Standard device header */ 2356 type_name = "\"normal\" device"; 2357 type_printfn = &pci_conf_print_type0; 2358 capoff = PCI_CAPLISTPTR_REG; 2359 endoff = 64; 2360 break; 2361 case 1: 2362 /* PCI-PCI bridge header */ 2363 type_name = "PCI-PCI bridge"; 2364 type_printfn = &pci_conf_print_type1; 2365 capoff = PCI_CAPLISTPTR_REG; 2366 endoff = 64; 2367 break; 2368 case 2: 2369 /* PCI-CardBus bridge header */ 2370 type_name = "PCI-CardBus bridge"; 2371 type_printfn = &pci_conf_print_type2; 2372 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 2373 endoff = 72; 2374 break; 2375 default: 2376 type_name = NULL; 2377 type_printfn = 0; 2378 capoff = -1; 2379 endoff = 64; 2380 break; 2381 } 2382 printf(" Type %d ", hdrtype); 2383 if (type_name != NULL) 2384 printf("(%s) ", type_name); 2385 printf("header:\n"); 2386 pci_conf_print_regs(regs, 16, endoff); 2387 printf("\n"); 2388 if (type_printfn) { 2389 #ifdef _KERNEL 2390 (*type_printfn)(pc, tag, regs, sizebars); 2391 #else 2392 (*type_printfn)(regs); 2393 #endif 2394 } else 2395 printf(" Don't know how to pretty-print type %d header.\n", 2396 hdrtype); 2397 printf("\n"); 2398 2399 /* capability list, if present */ 2400 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 2401 && (capoff > 0)) { 2402 #ifdef _KERNEL 2403 pci_conf_print_caplist(pc, tag, regs, capoff); 2404 #else 2405 pci_conf_print_caplist(regs, capoff); 2406 #endif 2407 printf("\n"); 2408 } 2409 2410 /* device-dependent header */ 2411 printf(" Device-dependent header:\n"); 2412 pci_conf_print_regs(regs, endoff, 256); 2413 printf("\n"); 2414 #ifdef _KERNEL 2415 if (printfn) 2416 (*printfn)(pc, tag, regs); 2417 else 2418 printf(" Don't know how to pretty-print device-dependent header.\n"); 2419 printf("\n"); 2420 #endif /* _KERNEL */ 2421 } 2422
Indexes created Wed Sep 24 15:09:51 GMT 2025