pci_subr.c revision 1.135
1 /* $NetBSD: pci_subr.c,v 1.135 2015/10/02 05:22:53 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.135 2015/10/02 05:22:53 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdbool.h> 58 #include <stdio.h> 59 #include <stdlib.h> 60 #include <string.h> 61 #endif 62 63 #include <dev/pci/pcireg.h> 64 #ifdef _KERNEL 65 #include <dev/pci/pcivar.h> 66 #else 67 #include <dev/pci/pci_verbose.h> 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcidevs_data.h> 70 #endif 71 72 /* 73 * Descriptions of known PCI classes and subclasses. 74 * 75 * Subclasses are described in the same way as classes, but have a 76 * NULL subclass pointer. 77 */ 78 struct pci_class { 79 const char *name; 80 u_int val; /* as wide as pci_{,sub}class_t */ 81 const struct pci_class *subclasses; 82 }; 83 84 /* 85 * Class 0x00. 86 * Before rev. 2.0. 87 */ 88 static const struct pci_class pci_subclass_prehistoric[] = { 89 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 90 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 91 { NULL, 0, NULL, }, 92 }; 93 94 /* 95 * Class 0x01. 96 * Mass storage controller 97 */ 98 99 /* ATA programming interface */ 100 static const struct pci_class pci_interface_ata[] = { 101 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 102 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 103 { NULL, 0, NULL, }, 104 }; 105 106 /* SATA programming interface */ 107 static const struct pci_class pci_interface_sata[] = { 108 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 109 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 110 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 111 { NULL, 0, NULL, }, 112 }; 113 114 /* Flash programming interface */ 115 static const struct pci_class pci_interface_nvm[] = { 116 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 117 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 118 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 119 { NULL, 0, NULL, }, 120 }; 121 122 /* Subclasses */ 123 static const struct pci_class pci_subclass_mass_storage[] = { 124 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 125 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 126 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 127 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 128 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 129 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 130 pci_interface_ata, }, 131 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 132 pci_interface_sata, }, 133 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 134 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 135 pci_interface_nvm, }, 136 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 137 { NULL, 0, NULL, }, 138 }; 139 140 /* 141 * Class 0x02. 142 * Network controller. 143 */ 144 static const struct pci_class pci_subclass_network[] = { 145 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 146 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 147 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 148 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 149 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 150 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 151 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 152 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 153 { NULL, 0, NULL, }, 154 }; 155 156 /* 157 * Class 0x03. 158 * Display controller. 159 */ 160 161 /* VGA programming interface */ 162 static const struct pci_class pci_interface_vga[] = { 163 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 164 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 165 { NULL, 0, NULL, }, 166 }; 167 /* Subclasses */ 168 static const struct pci_class pci_subclass_display[] = { 169 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 170 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 171 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 172 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 173 { NULL, 0, NULL, }, 174 }; 175 176 /* 177 * Class 0x04. 178 * Multimedia device. 179 */ 180 static const struct pci_class pci_subclass_multimedia[] = { 181 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 182 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 183 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 184 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 185 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 186 { NULL, 0, NULL, }, 187 }; 188 189 /* 190 * Class 0x05. 191 * Memory controller. 192 */ 193 static const struct pci_class pci_subclass_memory[] = { 194 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 195 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 196 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 197 { NULL, 0, NULL, }, 198 }; 199 200 /* 201 * Class 0x06. 202 * Bridge device. 203 */ 204 205 /* PCI bridge programming interface */ 206 static const struct pci_class pci_interface_pcibridge[] = { 207 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 208 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 209 { NULL, 0, NULL, }, 210 }; 211 212 /* Semi-transparent PCI-to-PCI bridge programming interface */ 213 static const struct pci_class pci_interface_stpci[] = { 214 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 215 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 216 { NULL, 0, NULL, }, 217 }; 218 219 /* Advanced Switching programming interface */ 220 static const struct pci_class pci_interface_advsw[] = { 221 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 222 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 223 { NULL, 0, NULL, }, 224 }; 225 226 /* Subclasses */ 227 static const struct pci_class pci_subclass_bridge[] = { 228 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 229 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 230 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 231 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 232 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 233 pci_interface_pcibridge, }, 234 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 235 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 236 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 237 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 238 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 239 pci_interface_stpci, }, 240 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 241 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 242 pci_interface_advsw, }, 243 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 244 { NULL, 0, NULL, }, 245 }; 246 247 /* 248 * Class 0x07. 249 * Simple communications controller. 250 */ 251 252 /* Serial controller programming interface */ 253 static const struct pci_class pci_interface_serial[] = { 254 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 255 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 256 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 257 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 258 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 259 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 260 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 261 { NULL, 0, NULL, }, 262 }; 263 264 /* Parallel controller programming interface */ 265 static const struct pci_class pci_interface_parallel[] = { 266 { "", PCI_INTERFACE_PARALLEL, NULL,}, 267 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 268 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 269 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 270 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 271 { NULL, 0, NULL,}, 272 }; 273 274 /* Modem programming interface */ 275 static const struct pci_class pci_interface_modem[] = { 276 { "", PCI_INTERFACE_MODEM, NULL,}, 277 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 278 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 279 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 280 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 281 { NULL, 0, NULL,}, 282 }; 283 284 /* Subclasses */ 285 static const struct pci_class pci_subclass_communications[] = { 286 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 287 pci_interface_serial, }, 288 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 289 pci_interface_parallel, }, 290 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 291 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 292 pci_interface_modem, }, 293 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 294 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 295 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 296 { NULL, 0, NULL,}, 297 }; 298 299 /* 300 * Class 0x08. 301 * Base system peripheral. 302 */ 303 304 /* PIC programming interface */ 305 static const struct pci_class pci_interface_pic[] = { 306 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 307 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 308 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 309 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 310 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 311 { NULL, 0, NULL, }, 312 }; 313 314 /* DMA programming interface */ 315 static const struct pci_class pci_interface_dma[] = { 316 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 317 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 318 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 319 { NULL, 0, NULL, }, 320 }; 321 322 /* Timer programming interface */ 323 static const struct pci_class pci_interface_tmr[] = { 324 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 325 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 326 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 327 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 328 { NULL, 0, NULL, }, 329 }; 330 331 /* RTC programming interface */ 332 static const struct pci_class pci_interface_rtc[] = { 333 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 334 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 335 { NULL, 0, NULL, }, 336 }; 337 338 /* Subclasses */ 339 static const struct pci_class pci_subclass_system[] = { 340 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 341 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 342 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 343 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 344 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 345 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 346 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 347 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 348 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 349 { NULL, 0, NULL, }, 350 }; 351 352 /* 353 * Class 0x09. 354 * Input device. 355 */ 356 357 /* Gameport programming interface */ 358 static const struct pci_class pci_interface_game[] = { 359 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 360 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 361 { NULL, 0, NULL, }, 362 }; 363 364 /* Subclasses */ 365 static const struct pci_class pci_subclass_input[] = { 366 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 367 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 368 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 369 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 370 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 371 pci_interface_game, }, 372 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 373 { NULL, 0, NULL, }, 374 }; 375 376 /* 377 * Class 0x0a. 378 * Docking station. 379 */ 380 static const struct pci_class pci_subclass_dock[] = { 381 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 382 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 383 { NULL, 0, NULL, }, 384 }; 385 386 /* 387 * Class 0x0b. 388 * Processor. 389 */ 390 static const struct pci_class pci_subclass_processor[] = { 391 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 392 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 393 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 394 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 395 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 396 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 397 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 398 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 399 { NULL, 0, NULL, }, 400 }; 401 402 /* 403 * Class 0x0c. 404 * Serial bus controller. 405 */ 406 407 /* IEEE1394 programming interface */ 408 static const struct pci_class pci_interface_ieee1394[] = { 409 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 410 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 411 { NULL, 0, NULL,}, 412 }; 413 414 /* USB programming interface */ 415 static const struct pci_class pci_interface_usb[] = { 416 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 417 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 418 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 419 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 420 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 421 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 422 { NULL, 0, NULL, }, 423 }; 424 425 /* IPMI programming interface */ 426 static const struct pci_class pci_interface_ipmi[] = { 427 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 428 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 429 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 430 { NULL, 0, NULL,}, 431 }; 432 433 /* Subclasses */ 434 static const struct pci_class pci_subclass_serialbus[] = { 435 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 436 pci_interface_ieee1394, }, 437 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 438 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 439 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 440 pci_interface_usb, }, 441 /* XXX Fiber Channel/_FIBRECHANNEL */ 442 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 443 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 444 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 445 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 446 pci_interface_ipmi, }, 447 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 448 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 449 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 450 { NULL, 0, NULL, }, 451 }; 452 453 /* 454 * Class 0x0d. 455 * Wireless Controller. 456 */ 457 static const struct pci_class pci_subclass_wireless[] = { 458 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 459 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 460 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 461 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 462 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 463 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 464 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 465 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 466 { NULL, 0, NULL, }, 467 }; 468 469 /* 470 * Class 0x0e. 471 * Intelligent IO controller. 472 */ 473 474 /* Intelligent IO programming interface */ 475 static const struct pci_class pci_interface_i2o[] = { 476 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 477 { NULL, 0, NULL,}, 478 }; 479 480 /* Subclasses */ 481 static const struct pci_class pci_subclass_i2o[] = { 482 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 483 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 484 { NULL, 0, NULL, }, 485 }; 486 487 /* 488 * Class 0x0f. 489 * Satellite communication controller. 490 */ 491 static const struct pci_class pci_subclass_satcom[] = { 492 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 493 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 494 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 495 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 496 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 497 { NULL, 0, NULL, }, 498 }; 499 500 /* 501 * Class 0x10. 502 * Encryption/Decryption controller. 503 */ 504 static const struct pci_class pci_subclass_crypto[] = { 505 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 506 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 507 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 508 { NULL, 0, NULL, }, 509 }; 510 511 /* 512 * Class 0x11. 513 * Data aquuisition and signal processing controller. 514 */ 515 static const struct pci_class pci_subclass_dasp[] = { 516 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 517 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 518 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 519 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 520 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 521 { NULL, 0, NULL, }, 522 }; 523 524 /* List of classes */ 525 static const struct pci_class pci_class[] = { 526 { "prehistoric", PCI_CLASS_PREHISTORIC, 527 pci_subclass_prehistoric, }, 528 { "mass storage", PCI_CLASS_MASS_STORAGE, 529 pci_subclass_mass_storage, }, 530 { "network", PCI_CLASS_NETWORK, 531 pci_subclass_network, }, 532 { "display", PCI_CLASS_DISPLAY, 533 pci_subclass_display, }, 534 { "multimedia", PCI_CLASS_MULTIMEDIA, 535 pci_subclass_multimedia, }, 536 { "memory", PCI_CLASS_MEMORY, 537 pci_subclass_memory, }, 538 { "bridge", PCI_CLASS_BRIDGE, 539 pci_subclass_bridge, }, 540 { "communications", PCI_CLASS_COMMUNICATIONS, 541 pci_subclass_communications, }, 542 { "system", PCI_CLASS_SYSTEM, 543 pci_subclass_system, }, 544 { "input", PCI_CLASS_INPUT, 545 pci_subclass_input, }, 546 { "dock", PCI_CLASS_DOCK, 547 pci_subclass_dock, }, 548 { "processor", PCI_CLASS_PROCESSOR, 549 pci_subclass_processor, }, 550 { "serial bus", PCI_CLASS_SERIALBUS, 551 pci_subclass_serialbus, }, 552 { "wireless", PCI_CLASS_WIRELESS, 553 pci_subclass_wireless, }, 554 { "I2O", PCI_CLASS_I2O, 555 pci_subclass_i2o, }, 556 { "satellite comm", PCI_CLASS_SATCOM, 557 pci_subclass_satcom, }, 558 { "crypto", PCI_CLASS_CRYPTO, 559 pci_subclass_crypto, }, 560 { "DASP", PCI_CLASS_DASP, 561 pci_subclass_dasp, }, 562 { "undefined", PCI_CLASS_UNDEFINED, 563 NULL, }, 564 { NULL, 0, 565 NULL, }, 566 }; 567 568 DEV_VERBOSE_DEFINE(pci); 569 570 void 571 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 572 size_t l) 573 { 574 pci_class_t pciclass; 575 pci_subclass_t subclass; 576 pci_interface_t interface; 577 pci_revision_t revision; 578 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 579 const struct pci_class *classp, *subclassp, *interfacep; 580 char *ep; 581 582 ep = cp + l; 583 584 pciclass = PCI_CLASS(class_reg); 585 subclass = PCI_SUBCLASS(class_reg); 586 interface = PCI_INTERFACE(class_reg); 587 revision = PCI_REVISION(class_reg); 588 589 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 590 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 591 PCI_PRODUCT(id_reg)); 592 593 classp = pci_class; 594 while (classp->name != NULL) { 595 if (pciclass == classp->val) 596 break; 597 classp++; 598 } 599 600 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 601 while (subclassp && subclassp->name != NULL) { 602 if (subclass == subclassp->val) 603 break; 604 subclassp++; 605 } 606 607 interfacep = (subclassp && subclassp->name != NULL) ? 608 subclassp->subclasses : NULL; 609 while (interfacep && interfacep->name != NULL) { 610 if (interface == interfacep->val) 611 break; 612 interfacep++; 613 } 614 615 cp += snprintf(cp, ep - cp, "%s %s", vendor, product); 616 if (showclass) { 617 cp += snprintf(cp, ep - cp, " ("); 618 if (classp->name == NULL) 619 cp += snprintf(cp, ep - cp, 620 "class 0x%02x, subclass 0x%02x", pciclass, subclass); 621 else { 622 if (subclassp == NULL || subclassp->name == NULL) 623 cp += snprintf(cp, ep - cp, 624 "%s, subclass 0x%02x", 625 classp->name, subclass); 626 else 627 cp += snprintf(cp, ep - cp, "%s %s", 628 subclassp->name, classp->name); 629 } 630 if ((interfacep == NULL) || (interfacep->name == NULL)) { 631 if (interface != 0) 632 cp += snprintf(cp, ep - cp, 633 ", interface 0x%02x", interface); 634 } else if (strncmp(interfacep->name, "", 1) != 0) 635 cp += snprintf(cp, ep - cp, ", %s", 636 interfacep->name); 637 if (revision != 0) 638 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 639 revision); 640 cp += snprintf(cp, ep - cp, ")"); 641 } 642 } 643 644 #ifdef _KERNEL 645 void 646 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 647 const char *known, int addrev) 648 { 649 char devinfo[256]; 650 651 if (known) { 652 aprint_normal(": %s", known); 653 if (addrev) 654 aprint_normal(" (rev. 0x%02x)", 655 PCI_REVISION(pa->pa_class)); 656 aprint_normal("\n"); 657 } else { 658 pci_devinfo(pa->pa_id, pa->pa_class, 0, 659 devinfo, sizeof(devinfo)); 660 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 661 PCI_REVISION(pa->pa_class)); 662 } 663 if (naive) 664 aprint_naive(": %s\n", naive); 665 else 666 aprint_naive("\n"); 667 } 668 #endif 669 670 /* 671 * Print out most of the PCI configuration registers. Typically used 672 * in a device attach routine like this: 673 * 674 * #ifdef MYDEV_DEBUG 675 * printf("%s: ", device_xname(sc->sc_dev)); 676 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 677 * #endif 678 */ 679 680 #define i2o(i) ((i) * 4) 681 #define o2i(o) ((o) / 4) 682 #define onoff2(str, rval, bit, onstr, offstr) \ 683 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 684 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 685 686 static void 687 pci_conf_print_common( 688 #ifdef _KERNEL 689 pci_chipset_tag_t pc, pcitag_t tag, 690 #endif 691 const pcireg_t *regs) 692 { 693 const char *name; 694 const struct pci_class *classp, *subclassp; 695 char vendor[PCI_VENDORSTR_LEN]; 696 char product[PCI_PRODUCTSTR_LEN]; 697 pcireg_t rval; 698 unsigned int num; 699 700 rval = regs[o2i(PCI_ID_REG)]; 701 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 702 if (name) 703 printf(" Vendor Name: %s (0x%04x)\n", name, 704 PCI_VENDOR(rval)); 705 else 706 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 707 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 708 PCI_PRODUCT(rval)); 709 if (name) 710 printf(" Device Name: %s (0x%04x)\n", name, 711 PCI_PRODUCT(rval)); 712 else 713 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 714 715 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 716 717 printf(" Command register: 0x%04x\n", rval & 0xffff); 718 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 719 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 720 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 721 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 722 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 723 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 724 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 725 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 726 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 727 onoff("Fast back-to-back transactions", rval, 728 PCI_COMMAND_BACKTOBACK_ENABLE); 729 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 730 731 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 732 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 733 "inactive"); 734 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 735 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 736 onoff("User Definable Features (UDF) support", rval, 737 PCI_STATUS_UDF_SUPPORT); 738 onoff("Fast back-to-back capable", rval, 739 PCI_STATUS_BACKTOBACK_SUPPORT); 740 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 741 742 printf(" DEVSEL timing: "); 743 switch (rval & PCI_STATUS_DEVSEL_MASK) { 744 case PCI_STATUS_DEVSEL_FAST: 745 printf("fast"); 746 break; 747 case PCI_STATUS_DEVSEL_MEDIUM: 748 printf("medium"); 749 break; 750 case PCI_STATUS_DEVSEL_SLOW: 751 printf("slow"); 752 break; 753 default: 754 printf("unknown/reserved"); /* XXX */ 755 break; 756 } 757 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 758 759 onoff("Slave signaled Target Abort", rval, 760 PCI_STATUS_TARGET_TARGET_ABORT); 761 onoff("Master received Target Abort", rval, 762 PCI_STATUS_MASTER_TARGET_ABORT); 763 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 764 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 765 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 766 767 rval = regs[o2i(PCI_CLASS_REG)]; 768 for (classp = pci_class; classp->name != NULL; classp++) { 769 if (PCI_CLASS(rval) == classp->val) 770 break; 771 } 772 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 773 while (subclassp && subclassp->name != NULL) { 774 if (PCI_SUBCLASS(rval) == subclassp->val) 775 break; 776 subclassp++; 777 } 778 if (classp->name != NULL) { 779 printf(" Class Name: %s (0x%02x)\n", classp->name, 780 PCI_CLASS(rval)); 781 if (subclassp != NULL && subclassp->name != NULL) 782 printf(" Subclass Name: %s (0x%02x)\n", 783 subclassp->name, PCI_SUBCLASS(rval)); 784 else 785 printf(" Subclass ID: 0x%02x\n", 786 PCI_SUBCLASS(rval)); 787 } else { 788 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 789 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 790 } 791 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 792 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 793 794 rval = regs[o2i(PCI_BHLC_REG)]; 795 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 796 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 797 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 798 PCI_HDRTYPE(rval)); 799 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 800 num = PCI_CACHELINE(rval); 801 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 802 } 803 804 static int 805 pci_conf_print_bar( 806 #ifdef _KERNEL 807 pci_chipset_tag_t pc, pcitag_t tag, 808 #endif 809 const pcireg_t *regs, int reg, const char *name 810 #ifdef _KERNEL 811 , int sizebar 812 #endif 813 ) 814 { 815 int width; 816 pcireg_t rval, rval64h; 817 #ifdef _KERNEL 818 int s; 819 pcireg_t mask, mask64h; 820 #endif 821 822 width = 4; 823 824 /* 825 * Section 6.2.5.1, `Address Maps', tells us that: 826 * 827 * 1) The builtin software should have already mapped the 828 * device in a reasonable way. 829 * 830 * 2) A device which wants 2^n bytes of memory will hardwire 831 * the bottom n bits of the address to 0. As recommended, 832 * we write all 1s and see what we get back. 833 */ 834 835 rval = regs[o2i(reg)]; 836 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 837 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 838 rval64h = regs[o2i(reg + 4)]; 839 width = 8; 840 } else 841 rval64h = 0; 842 843 #ifdef _KERNEL 844 /* XXX don't size unknown memory type? */ 845 if (rval != 0 && sizebar) { 846 /* 847 * The following sequence seems to make some devices 848 * (e.g. host bus bridges, which don't normally 849 * have their space mapped) very unhappy, to 850 * the point of crashing the system. 851 * 852 * Therefore, if the mapping register is zero to 853 * start out with, don't bother trying. 854 */ 855 s = splhigh(); 856 pci_conf_write(pc, tag, reg, 0xffffffff); 857 mask = pci_conf_read(pc, tag, reg); 858 pci_conf_write(pc, tag, reg, rval); 859 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 860 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 861 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 862 mask64h = pci_conf_read(pc, tag, reg + 4); 863 pci_conf_write(pc, tag, reg + 4, rval64h); 864 } else 865 mask64h = 0; 866 splx(s); 867 } else 868 mask = mask64h = 0; 869 #endif /* _KERNEL */ 870 871 printf(" Base address register at 0x%02x", reg); 872 if (name) 873 printf(" (%s)", name); 874 printf("\n "); 875 if (rval == 0) { 876 printf("not implemented(?)\n"); 877 return width; 878 } 879 printf("type: "); 880 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 881 const char *type, *prefetch; 882 883 switch (PCI_MAPREG_MEM_TYPE(rval)) { 884 case PCI_MAPREG_MEM_TYPE_32BIT: 885 type = "32-bit"; 886 break; 887 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 888 type = "32-bit-1M"; 889 break; 890 case PCI_MAPREG_MEM_TYPE_64BIT: 891 type = "64-bit"; 892 break; 893 default: 894 type = "unknown (XXX)"; 895 break; 896 } 897 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 898 prefetch = ""; 899 else 900 prefetch = "non"; 901 printf("%s %sprefetchable memory\n", type, prefetch); 902 switch (PCI_MAPREG_MEM_TYPE(rval)) { 903 case PCI_MAPREG_MEM_TYPE_64BIT: 904 printf(" base: 0x%016llx, ", 905 PCI_MAPREG_MEM64_ADDR( 906 ((((long long) rval64h) << 32) | rval))); 907 #ifdef _KERNEL 908 if (sizebar) 909 printf("size: 0x%016llx", 910 PCI_MAPREG_MEM64_SIZE( 911 ((((long long) mask64h) << 32) | mask))); 912 else 913 #endif /* _KERNEL */ 914 printf("not sized"); 915 printf("\n"); 916 break; 917 case PCI_MAPREG_MEM_TYPE_32BIT: 918 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 919 default: 920 printf(" base: 0x%08x, ", 921 PCI_MAPREG_MEM_ADDR(rval)); 922 #ifdef _KERNEL 923 if (sizebar) 924 printf("size: 0x%08x", 925 PCI_MAPREG_MEM_SIZE(mask)); 926 else 927 #endif /* _KERNEL */ 928 printf("not sized"); 929 printf("\n"); 930 break; 931 } 932 } else { 933 #ifdef _KERNEL 934 if (sizebar) 935 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 936 #endif /* _KERNEL */ 937 printf("i/o\n"); 938 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 939 #ifdef _KERNEL 940 if (sizebar) 941 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 942 else 943 #endif /* _KERNEL */ 944 printf("not sized"); 945 printf("\n"); 946 } 947 948 return width; 949 } 950 951 static void 952 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 953 { 954 int off, needaddr, neednl; 955 956 needaddr = 1; 957 neednl = 0; 958 for (off = first; off < pastlast; off += 4) { 959 if ((off % 16) == 0 || needaddr) { 960 printf(" 0x%02x:", off); 961 needaddr = 0; 962 } 963 printf(" 0x%08x", regs[o2i(off)]); 964 neednl = 1; 965 if ((off % 16) == 12) { 966 printf("\n"); 967 neednl = 0; 968 } 969 } 970 if (neednl) 971 printf("\n"); 972 } 973 974 static void 975 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 976 { 977 pcireg_t rval; 978 979 printf("\n AGP Capabilities Register\n"); 980 981 rval = regs[o2i(capoff)]; 982 printf(" Revision: %d.%d\n", 983 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 984 985 /* XXX need more */ 986 } 987 988 static const char * 989 pci_conf_print_pcipm_cap_aux(uint16_t caps) 990 { 991 992 switch ((caps >> 6) & 7) { 993 case 0: return "self-powered"; 994 case 1: return "55 mA"; 995 case 2: return "100 mA"; 996 case 3: return "160 mA"; 997 case 4: return "220 mA"; 998 case 5: return "270 mA"; 999 case 6: return "320 mA"; 1000 case 7: 1001 default: return "375 mA"; 1002 } 1003 } 1004 1005 static const char * 1006 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1007 { 1008 static const char unk[] = "unknown"; 1009 static const char *pmrev[8] = { 1010 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1011 }; 1012 if (val > 7) 1013 return unk; 1014 return pmrev[val]; 1015 } 1016 1017 static void 1018 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1019 { 1020 uint16_t caps, pmcsr; 1021 pcireg_t reg; 1022 1023 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1024 reg = regs[o2i(capoff + PCI_PMCSR)]; 1025 pmcsr = reg & 0xffff; 1026 1027 printf("\n PCI Power Management Capabilities Register\n"); 1028 1029 printf(" Capabilities register: 0x%04x\n", caps); 1030 printf(" Version: %s\n", 1031 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1032 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1033 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1034 printf(" 3.3V auxiliary current: %s\n", 1035 pci_conf_print_pcipm_cap_aux(caps)); 1036 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1037 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1038 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1039 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1040 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1041 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1042 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1043 1044 printf(" Control/status register: 0x%04x\n", pmcsr); 1045 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1046 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1047 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1048 printf(" PME# assertion: %sabled\n", 1049 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1050 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1051 printf(" Bridge Support Extensions register: 0x%02x\n", 1052 (reg >> 16) & 0xff); 1053 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1054 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1055 printf(" Data register: 0x%02x\n", (reg >> 24) & 0xff); 1056 1057 } 1058 1059 /* XXX pci_conf_print_vpd_cap */ 1060 /* XXX pci_conf_print_slotid_cap */ 1061 1062 static void 1063 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1064 { 1065 uint32_t ctl, mmc, mme; 1066 1067 regs += o2i(capoff); 1068 ctl = *regs++; 1069 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1070 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1071 1072 printf("\n PCI Message Signaled Interrupt\n"); 1073 1074 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1075 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1076 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1077 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1078 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1079 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1080 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1081 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1082 printf(" Message Address %sregister: 0x%08x\n", 1083 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1084 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1085 printf(" Message Address %sregister: 0x%08x\n", 1086 "(upper) ", *regs++); 1087 } 1088 printf(" Message Data register: 0x%08x\n", *regs++); 1089 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1090 printf(" Vector Mask register: 0x%08x\n", *regs++); 1091 printf(" Vector Pending register: 0x%08x\n", *regs++); 1092 } 1093 } 1094 1095 /* XXX pci_conf_print_cpci_hostwap_cap */ 1096 1097 /* 1098 * For both command register and status register. 1099 * The argument "idx" is index number (0 to 7). 1100 */ 1101 static int 1102 pcix_split_trans(unsigned int idx) 1103 { 1104 static int table[8] = { 1105 1, 2, 3, 4, 8, 12, 16, 32 1106 }; 1107 1108 if (idx >= __arraycount(table)) 1109 return -1; 1110 return table[idx]; 1111 } 1112 1113 static void 1114 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1115 { 1116 pcireg_t reg; 1117 int isbridge; 1118 int i; 1119 1120 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1121 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1122 printf("\n PCI-X %s Capabilities Register\n", 1123 isbridge ? "Bridge" : "Non-bridge"); 1124 1125 reg = regs[o2i(capoff)]; 1126 if (isbridge != 0) { 1127 printf(" Secondary status register: 0x%04x\n", 1128 (reg & 0xffff0000) >> 16); 1129 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1130 onoff("133MHz capable", reg, PCIX_STATUS_133); 1131 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1132 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1133 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1134 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1135 printf(" Secondary clock frequency: 0x%x\n", 1136 (reg & PCIX_BRIDGE_2NDST_CLKF) 1137 >> PCIX_BRIDGE_2NDST_CLKF_SHIFT); 1138 printf(" Version: 0x%x\n", 1139 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1140 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1141 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1142 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1143 } else { 1144 printf(" Command register: 0x%04x\n", 1145 (reg & 0xffff0000) >> 16); 1146 onoff("Data Parity Error Recovery", reg, 1147 PCIX_CMD_PERR_RECOVER); 1148 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1149 printf(" Maximum Burst Read Count: %u\n", 1150 PCIX_CMD_BYTECNT(reg)); 1151 printf(" Maximum Split Transactions: %d\n", 1152 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1153 >> PCIX_CMD_SPLTRANS_SHIFT)); 1154 } 1155 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1156 printf(" %sStatus register: 0x%08x\n", 1157 isbridge ? "Bridge " : "", reg); 1158 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1159 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1160 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1161 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1162 onoff("133MHz capable", reg, PCIX_STATUS_133); 1163 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1164 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1165 if (isbridge != 0) { 1166 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1167 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1168 } else { 1169 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1170 "bridge device", "simple device"); 1171 printf(" Designed max memory read byte count: %d\n", 1172 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1173 >> PCIX_STATUS_MAXB_SHIFT)); 1174 printf(" Designed max outstanding split transaction: %d\n", 1175 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1176 >> PCIX_STATUS_MAXST_SHIFT)); 1177 printf(" MAX cumulative Read Size: %u\n", 1178 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1179 onoff("Received split completion error", reg, 1180 PCIX_STATUS_SCERR); 1181 } 1182 onoff("266MHz capable", reg, PCIX_STATUS_266); 1183 onoff("533MHz capable", reg, PCIX_STATUS_533); 1184 1185 if (isbridge == 0) 1186 return; 1187 1188 /* Only for bridge */ 1189 for (i = 0; i < 2; i++) { 1190 reg = regs[o2i(capoff+PCIX_BRIDGE_UP_STCR + (4 * i))]; 1191 printf(" %s split transaction control register: 0x%08x\n", 1192 (i == 0) ? "Upstream" : "Downstream", reg); 1193 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1194 printf(" Commitment Limit: %d\n", 1195 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1196 } 1197 } 1198 1199 /* XXX pci_conf_print_ldt_cap */ 1200 1201 static void 1202 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1203 { 1204 uint16_t caps; 1205 1206 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1207 1208 printf("\n PCI Vendor Specific Capabilities Register\n"); 1209 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1210 } 1211 1212 static void 1213 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1214 { 1215 pcireg_t val; 1216 1217 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1218 1219 printf("\n Debugport Capability Register\n"); 1220 printf(" Debug base Register: 0x%04x\n", 1221 val >> PCI_DEBUG_BASER_SHIFT); 1222 printf(" port offset: 0x%04x\n", 1223 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1224 printf(" BAR number: %u\n", 1225 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1226 } 1227 1228 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1229 /* XXX pci_conf_print_hotplug_cap */ 1230 1231 static void 1232 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1233 { 1234 pcireg_t reg; 1235 1236 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1237 1238 printf("\n Subsystem ID Capability Register\n"); 1239 printf(" Subsystem ID : 0x%08x\n", reg); 1240 } 1241 1242 /* XXX pci_conf_print_agp8_cap */ 1243 /* XXX pci_conf_print_secure_cap */ 1244 1245 static void 1246 pci_print_pcie_L0s_latency(uint32_t val) 1247 { 1248 1249 switch (val) { 1250 case 0x0: 1251 printf("Less than 64ns\n"); 1252 break; 1253 case 0x1: 1254 case 0x2: 1255 case 0x3: 1256 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1257 break; 1258 case 0x4: 1259 printf("512ns to less than 1us\n"); 1260 break; 1261 case 0x5: 1262 printf("1us to less than 2us\n"); 1263 break; 1264 case 0x6: 1265 printf("2us - 4us\n"); 1266 break; 1267 case 0x7: 1268 printf("More than 4us\n"); 1269 break; 1270 } 1271 } 1272 1273 static void 1274 pci_print_pcie_L1_latency(uint32_t val) 1275 { 1276 1277 switch (val) { 1278 case 0x0: 1279 printf("Less than 1us\n"); 1280 break; 1281 case 0x6: 1282 printf("32us - 64us\n"); 1283 break; 1284 case 0x7: 1285 printf("More than 64us\n"); 1286 break; 1287 default: 1288 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1289 break; 1290 } 1291 } 1292 1293 static void 1294 pci_print_pcie_compl_timeout(uint32_t val) 1295 { 1296 1297 switch (val) { 1298 case 0x0: 1299 printf("50us to 50ms\n"); 1300 break; 1301 case 0x5: 1302 printf("16ms to 55ms\n"); 1303 break; 1304 case 0x6: 1305 printf("65ms to 210ms\n"); 1306 break; 1307 case 0x9: 1308 printf("260ms to 900ms\n"); 1309 break; 1310 case 0xa: 1311 printf("1s to 3.5s\n"); 1312 break; 1313 default: 1314 printf("unknown %u value\n", val); 1315 break; 1316 } 1317 } 1318 1319 static void 1320 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1321 { 1322 pcireg_t reg; /* for each register */ 1323 pcireg_t val; /* for each bitfield */ 1324 bool check_link = false; 1325 bool check_slot = false; 1326 bool check_rootport = false; 1327 unsigned int pciever; 1328 static const char * const linkspeeds[] = {"2.5", "5.0", "8.0"}; 1329 int i; 1330 1331 printf("\n PCI Express Capabilities Register\n"); 1332 /* Capability Register */ 1333 reg = regs[o2i(capoff)]; 1334 printf(" Capability register: %04x\n", reg >> 16); 1335 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1336 printf(" Capability version: %u\n", pciever); 1337 printf(" Device type: "); 1338 switch ((reg & 0x00f00000) >> 20) { 1339 case 0x0: 1340 printf("PCI Express Endpoint device\n"); 1341 check_link = true; 1342 break; 1343 case 0x1: 1344 printf("Legacy PCI Express Endpoint device\n"); 1345 check_link = true; 1346 break; 1347 case 0x4: 1348 printf("Root Port of PCI Express Root Complex\n"); 1349 check_link = true; 1350 check_slot = true; 1351 check_rootport = true; 1352 break; 1353 case 0x5: 1354 printf("Upstream Port of PCI Express Switch\n"); 1355 break; 1356 case 0x6: 1357 printf("Downstream Port of PCI Express Switch\n"); 1358 check_slot = true; 1359 check_rootport = true; 1360 break; 1361 case 0x7: 1362 printf("PCI Express to PCI/PCI-X Bridge\n"); 1363 break; 1364 case 0x8: 1365 printf("PCI/PCI-X to PCI Express Bridge\n"); 1366 break; 1367 case 0x9: 1368 printf("Root Complex Integrated Endpoint\n"); 1369 break; 1370 case 0xa: 1371 check_rootport = true; 1372 printf("Root Complex Event Collector\n"); 1373 break; 1374 default: 1375 printf("unknown\n"); 1376 break; 1377 } 1378 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1379 printf(" Interrupt Message Number: %x\n", 1380 (unsigned int)((reg & PCIE_XCAP_IRQ) >> 27)); 1381 1382 /* Device Capability Register */ 1383 reg = regs[o2i(capoff + PCIE_DCAP)]; 1384 printf(" Device Capabilities Register: 0x%08x\n", reg); 1385 printf(" Max Payload Size Supported: %u bytes max\n", 1386 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1387 printf(" Phantom Functions Supported: "); 1388 switch ((reg & PCIE_DCAP_PHANTOM_FUNCS) >> 3) { 1389 case 0x0: 1390 printf("not available\n"); 1391 break; 1392 case 0x1: 1393 printf("MSB\n"); 1394 break; 1395 case 0x2: 1396 printf("two MSB\n"); 1397 break; 1398 case 0x3: 1399 printf("All three bits\n"); 1400 break; 1401 } 1402 printf(" Extended Tag Field Supported: %dbit\n", 1403 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1404 printf(" Endpoint L0 Acceptable Latency: "); 1405 pci_print_pcie_L0s_latency((reg & PCIE_DCAP_L0S_LATENCY) >> 6); 1406 printf(" Endpoint L1 Acceptable Latency: "); 1407 pci_print_pcie_L1_latency((reg & PCIE_DCAP_L1_LATENCY) >> 9); 1408 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1409 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1410 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1411 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1412 printf(" Captured Slot Power Limit Value: %d\n", 1413 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18); 1414 printf(" Captured Slot Power Limit Scale: %d\n", 1415 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26); 1416 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1417 1418 /* Device Control Register */ 1419 reg = regs[o2i(capoff + PCIE_DCSR)]; 1420 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1421 onoff("Correctable Error Reporting Enable", reg, 1422 PCIE_DCSR_ENA_COR_ERR); 1423 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1424 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1425 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1426 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1427 printf(" Max Payload Size: %d byte\n", 1428 128 << (((unsigned int)(reg & PCIE_DCSR_MAX_PAYLOAD) >> 5))); 1429 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1430 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1431 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1432 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1433 printf(" Max Read Request Size: %d byte\n", 1434 128 << ((unsigned int)(reg & PCIE_DCSR_MAX_READ_REQ) >> 12)); 1435 1436 /* Device Status Register */ 1437 reg = regs[o2i(capoff + PCIE_DCSR)]; 1438 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1439 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1440 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1441 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1442 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1443 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1444 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1445 1446 if (check_link) { 1447 /* Link Capability Register */ 1448 reg = regs[o2i(capoff + PCIE_LCAP)]; 1449 printf(" Link Capabilities Register: 0x%08x\n", reg); 1450 printf(" Maximum Link Speed: "); 1451 val = reg & PCIE_LCAP_MAX_SPEED; 1452 if (val < 1 || val > 3) { 1453 printf("unknown %u value\n", val); 1454 } else { 1455 printf("%sGT/s\n", linkspeeds[val - 1]); 1456 } 1457 printf(" Maximum Link Width: x%u lanes\n", 1458 (unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4); 1459 printf(" Active State PM Support: "); 1460 val = (reg & PCIE_LCAP_ASPM) >> 10; 1461 switch (val) { 1462 case 0x1: 1463 printf("L0s Entry supported\n"); 1464 break; 1465 case 0x3: 1466 printf("L0s and L1 supported\n"); 1467 break; 1468 default: 1469 printf("Reserved value\n"); 1470 break; 1471 } 1472 printf(" L0 Exit Latency: "); 1473 pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12); 1474 printf(" L1 Exit Latency: "); 1475 pci_print_pcie_L1_latency((reg & PCIE_LCAP_L1_EXIT) >> 15); 1476 printf(" Port Number: %u\n", reg >> 24); 1477 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1478 onoff("Surprise Down Error Report", reg, 1479 PCIE_LCAP_SURPRISE_DOWN); 1480 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1481 onoff("Link BW Notification Capable", reg, 1482 PCIE_LCAP_LINK_BW_NOTIFY); 1483 onoff("ASPM Optionally Compliance", reg, 1484 PCIE_LCAP_ASPM_COMPLIANCE); 1485 1486 /* Link Control Register */ 1487 reg = regs[o2i(capoff + PCIE_LCSR)]; 1488 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1489 printf(" Active State PM Control: "); 1490 val = reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S); 1491 switch (val) { 1492 case 0: 1493 printf("disabled\n"); 1494 break; 1495 case 1: 1496 printf("L0s Entry Enabled\n"); 1497 break; 1498 case 2: 1499 printf("L1 Entry Enabled\n"); 1500 break; 1501 case 3: 1502 printf("L0s and L1 Entry Enabled\n"); 1503 break; 1504 } 1505 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1506 "128bytes", "64bytes"); 1507 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1508 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1509 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1510 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1511 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1512 onoff("Hardware Autonomous Width Disable", reg, 1513 PCIE_LCSR_HAWD); 1514 onoff("Link Bandwidth Management Interrupt Enable", reg, 1515 PCIE_LCSR_LBMIE); 1516 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1517 PCIE_LCSR_LABIE); 1518 1519 /* Link Status Register */ 1520 reg = regs[o2i(capoff + PCIE_LCSR)]; 1521 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1522 printf(" Negotiated Link Speed: "); 1523 if (((reg >> 16) & 0x000f) < 1 || 1524 ((reg >> 16) & 0x000f) > 3) { 1525 printf("unknown %u value\n", 1526 (unsigned int)(reg & PCIE_LCSR_LINKSPEED) >> 16); 1527 } else { 1528 printf("%sGT/s\n", 1529 linkspeeds[((reg & PCIE_LCSR_LINKSPEED) >> 16)-1]); 1530 } 1531 printf(" Negotiated Link Width: x%u lanes\n", 1532 (reg >> 20) & 0x003f); 1533 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1534 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1535 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1536 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1537 onoff("Link Bandwidth Management Status", reg, 1538 PCIE_LCSR_LINK_BW_MGMT); 1539 onoff("Link Autonomous Bandwidth Status", reg, 1540 PCIE_LCSR_LINK_AUTO_BW); 1541 } 1542 1543 if (check_slot == true) { 1544 /* Slot Capability Register */ 1545 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1546 printf(" Slot Capability Register: %08x\n", reg); 1547 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1548 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1549 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1550 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1551 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1552 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1553 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1554 printf(" Slot Power Limit Value: %d\n", 1555 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1556 printf(" Slot Power Limit Scale: %d\n", 1557 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1558 onoff("Electromechanical Interlock Present", reg, 1559 PCIE_SLCAP_EIP); 1560 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1561 printf(" Physical Slot Number: %d\n", 1562 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1563 1564 /* Slot Control Register */ 1565 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1566 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1567 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1568 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1569 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1570 onoff("Presense Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1571 onoff("Command Completed Interrupt Enabled", reg, 1572 PCIE_SLCSR_CCE); 1573 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1574 printf(" Attention Indicator Control: "); 1575 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1576 case 0x0: 1577 printf("reserved\n"); 1578 break; 1579 case 0x1: 1580 printf("on\n"); 1581 break; 1582 case 0x2: 1583 printf("blink\n"); 1584 break; 1585 case 0x3: 1586 printf("off\n"); 1587 break; 1588 } 1589 printf(" Power Indicator Control: "); 1590 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1591 case 0x0: 1592 printf("reserved\n"); 1593 break; 1594 case 0x1: 1595 printf("on\n"); 1596 break; 1597 case 0x2: 1598 printf("blink\n"); 1599 break; 1600 case 0x3: 1601 printf("off\n"); 1602 break; 1603 } 1604 onoff("Power Controller Control", reg, PCIE_SLCSR_PCC); 1605 onoff("Electromechanical Interlock Control", 1606 reg, PCIE_SLCSR_EIC); 1607 onoff("Data Link Layer State Changed Enable", reg, 1608 PCIE_SLCSR_DLLSCE); 1609 1610 /* Slot Status Register */ 1611 printf(" Slot Status Register: %04x\n", reg >> 16); 1612 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1613 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1614 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1615 onoff("Presense Detect Changed", reg, PCIE_SLCSR_PDC); 1616 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1617 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1618 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1619 onoff("Electromechanical Interlock engaged", reg, 1620 PCIE_SLCSR_EIS); 1621 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 1622 } 1623 1624 if (check_rootport == true) { 1625 /* Root Control Register */ 1626 reg = regs[o2i(capoff + PCIE_RCR)]; 1627 printf(" Root Control Register: %04x\n", reg & 0xffff); 1628 onoff("SERR on Correctable Error Enable", reg, 1629 PCIE_RCR_SERR_CER); 1630 onoff("SERR on Non-Fatal Error Enable", reg, 1631 PCIE_RCR_SERR_NFER); 1632 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 1633 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 1634 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 1635 1636 /* Root Capability Register */ 1637 printf(" Root Capability Register: %04x\n", 1638 reg >> 16); 1639 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 1640 1641 /* Root Status Register */ 1642 reg = regs[o2i(capoff + PCIE_RSR)]; 1643 printf(" Root Status Register: %08x\n", reg); 1644 printf(" PME Requester ID: %04x\n", 1645 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1646 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 1647 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 1648 } 1649 1650 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1651 if (pciever < 2) 1652 return; 1653 1654 /* Device Capabilities 2 */ 1655 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1656 printf(" Device Capabilities 2: 0x%08x\n", reg); 1657 printf(" Completion Timeout Ranges Supported: %u \n", 1658 (unsigned int)(reg & PCIE_DCAP2_COMPT_RANGE)); 1659 onoff("Completion Timeout Disable Supported", reg, 1660 PCIE_DCAP2_COMPT_DIS); 1661 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 1662 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 1663 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 1664 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 1665 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 1666 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 1667 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 1668 printf(" TPH Completer Supported: %u\n", 1669 (unsigned int)(reg & PCIE_DCAP2_TPH_COMP) >> 12); 1670 printf(" OBFF Supported: "); 1671 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 1672 case 0x0: 1673 printf("Not supported\n"); 1674 break; 1675 case 0x1: 1676 printf("Message only\n"); 1677 break; 1678 case 0x2: 1679 printf("WAKE# only\n"); 1680 break; 1681 case 0x3: 1682 printf("Both\n"); 1683 break; 1684 } 1685 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 1686 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 1687 printf(" Max End-End TLP Prefixes: %u\n", 1688 (unsigned int)(reg & PCIE_DCAP2_MAX_EETLP) >> 22); 1689 1690 /* Device Control 2 */ 1691 reg = regs[o2i(capoff + PCIE_DCSR2)]; 1692 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 1693 printf(" Completion Timeout Value: "); 1694 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 1695 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 1696 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 1697 onoff("AtomicOp Rquester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 1698 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 1699 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 1700 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 1701 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 1702 printf(" OBFF: "); 1703 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 1704 case 0x0: 1705 printf("Disabled\n"); 1706 break; 1707 case 0x1: 1708 printf("Enabled with Message Signaling Variation A\n"); 1709 break; 1710 case 0x2: 1711 printf("Enabled with Message Signaling Variation B\n"); 1712 break; 1713 case 0x3: 1714 printf("Enabled using WAKE# signaling\n"); 1715 break; 1716 } 1717 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 1718 1719 if (check_link) { 1720 /* Link Capability 2 */ 1721 reg = regs[o2i(capoff + PCIE_LCAP2)]; 1722 printf(" Link Capabilities 2: 0x%08x\n", reg); 1723 val = (reg & PCIE_LCAP2_SUP_LNKSV) >> 1; 1724 printf(" Supported Link Speed Vector:"); 1725 for (i = 0; i <= 2; i++) { 1726 if (((val >> i) & 0x01) != 0) 1727 printf(" %sGT/s", linkspeeds[i]); 1728 } 1729 printf("\n"); 1730 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 1731 1732 /* Link Control 2 */ 1733 reg = regs[o2i(capoff + PCIE_LCSR2)]; 1734 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 1735 printf(" Target Link Speed: "); 1736 val = reg & PCIE_LCSR2_TGT_LSPEED; 1737 if (val < 1 || val > 3) 1738 printf("unknown %u value\n", val); 1739 else 1740 printf("%sGT/s\n", linkspeeds[val - 1]); 1741 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 1742 onoff("HW Autonomous Speed Disabled", reg, 1743 PCIE_LCSR2_HW_AS_DIS); 1744 onoff("Selectable De-emphasis", reg, PCIE_LCSR2_SEL_DEEMP); 1745 printf(" Transmit Margin: %u\n", 1746 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 1747 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 1748 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 1749 printf(" Compliance Present/De-emphasis: %u\n", 1750 (unsigned int)(reg & PCIE_LCSR2_COMP_DEEMP) >> 12); 1751 1752 /* Link Status 2 */ 1753 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 1754 onoff("Current De-emphasis Level", reg, PCIE_LCSR2_DEEMP_LVL); 1755 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 1756 onoff("Equalization Phase 1 Successful", reg, 1757 PCIE_LCSR2_EQP1_SUC); 1758 onoff("Equalization Phase 2 Successful", reg, 1759 PCIE_LCSR2_EQP2_SUC); 1760 onoff("Equalization Phase 3 Successful", reg, 1761 PCIE_LCSR2_EQP3_SUC); 1762 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 1763 } 1764 1765 /* Slot Capability 2 */ 1766 /* Slot Control 2 */ 1767 /* Slot Status 2 */ 1768 } 1769 1770 static void 1771 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 1772 { 1773 pcireg_t reg; 1774 1775 printf("\n MSI-X Capability Register\n"); 1776 1777 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 1778 printf(" Message Control register: 0x%04x\n", 1779 (reg >> 16) & 0xff); 1780 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 1781 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 1782 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 1783 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 1784 printf(" Table offset register: 0x%08x\n", reg); 1785 printf(" Table offset: %08x\n", reg & PCI_MSIX_TBLOFFSET_MASK); 1786 printf(" BIR: 0x%x\n", reg & PCI_MSIX_TBLBIR_MASK); 1787 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 1788 printf(" Pending bit array register: 0x%08x\n", reg); 1789 printf(" Pending bit array offset: %08x\n", 1790 reg & PCI_MSIX_PBAOFFSET_MASK); 1791 printf(" BIR: 0x%x\n", reg & PCI_MSIX_PBABIR_MASK); 1792 } 1793 1794 /* XXX pci_conf_print_sata_cap */ 1795 static void 1796 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 1797 { 1798 pcireg_t reg; 1799 1800 printf("\n Advanced Features Capability Register\n"); 1801 1802 reg = regs[o2i(capoff + PCI_AFCAPR)]; 1803 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 1804 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 1805 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 1806 reg = regs[o2i(capoff + PCI_AFCSR)]; 1807 printf(" AF Control register: 0x%02x\n", reg & 0xff); 1808 /* 1809 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 1810 * and it's always 0 on read 1811 */ 1812 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 1813 onoff("Transaction Pending", reg, PCI_AFSR_TP); 1814 } 1815 1816 static struct { 1817 pcireg_t cap; 1818 const char *name; 1819 void (*printfunc)(const pcireg_t *, int); 1820 } pci_captab[] = { 1821 { PCI_CAP_RESERVED0, "reserved", NULL }, 1822 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 1823 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 1824 { PCI_CAP_VPD, "VPD", NULL }, 1825 { PCI_CAP_SLOTID, "SlotID", NULL }, 1826 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 1827 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 1828 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 1829 { PCI_CAP_LDT, "HyperTransport", NULL }, 1830 { PCI_CAP_VENDSPEC, "Vendor-specific", 1831 pci_conf_print_vendspec_cap }, 1832 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 1833 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 1834 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 1835 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 1836 pci_conf_print_subsystem_cap }, 1837 { PCI_CAP_AGP8, "AGP 8x", NULL }, 1838 { PCI_CAP_SECURE, "Secure Device", NULL }, 1839 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 1840 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 1841 { PCI_CAP_SATA, "SATA", NULL }, 1842 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap } 1843 }; 1844 1845 static int 1846 pci_conf_find_cap(const pcireg_t *regs, int capoff, unsigned int capid, 1847 int *offsetp) 1848 { 1849 pcireg_t rval; 1850 int off; 1851 1852 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1853 off != 0; 1854 off = PCI_CAPLIST_NEXT(rval)) { 1855 rval = regs[o2i(off)]; 1856 if (capid == PCI_CAPLIST_CAP(rval)) { 1857 if (offsetp != NULL) 1858 *offsetp = off; 1859 return 1; 1860 } 1861 } 1862 return 0; 1863 } 1864 1865 static void 1866 pci_conf_print_caplist( 1867 #ifdef _KERNEL 1868 pci_chipset_tag_t pc, pcitag_t tag, 1869 #endif 1870 const pcireg_t *regs, int capoff) 1871 { 1872 int off; 1873 pcireg_t foundcap; 1874 pcireg_t rval; 1875 bool foundtable[__arraycount(pci_captab)]; 1876 unsigned int i; 1877 1878 /* Clear table */ 1879 for (i = 0; i < __arraycount(pci_captab); i++) 1880 foundtable[i] = false; 1881 1882 /* Print capability register's offset and the type first */ 1883 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1884 off != 0; 1885 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 1886 rval = regs[o2i(off)]; 1887 printf(" Capability register at 0x%02x\n", off); 1888 1889 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 1890 foundcap = PCI_CAPLIST_CAP(rval); 1891 if (foundcap < __arraycount(pci_captab)) { 1892 printf("%s)\n", pci_captab[foundcap].name); 1893 /* Mark as found */ 1894 foundtable[foundcap] = true; 1895 } else 1896 printf("unknown)\n"); 1897 } 1898 1899 /* 1900 * And then, print the detail of each capability registers 1901 * in capability value's order. 1902 */ 1903 for (i = 0; i < __arraycount(pci_captab); i++) { 1904 if (foundtable[i] == false) 1905 continue; 1906 1907 /* 1908 * The type was found. Search capability list again and 1909 * print all capabilities that the capabiliy type is 1910 * the same. This is required because some capabilities 1911 * appear multiple times (e.g. HyperTransport capability). 1912 */ 1913 if (pci_conf_find_cap(regs, capoff, i, &off)) { 1914 rval = regs[o2i(off)]; 1915 if (pci_captab[i].printfunc != NULL) 1916 pci_captab[i].printfunc(regs, off); 1917 } 1918 } 1919 } 1920 1921 /* Extended Capability */ 1922 1923 static void 1924 pci_conf_print_aer_cap_uc(pcireg_t reg) 1925 { 1926 1927 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 1928 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 1929 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 1930 onoff("Poisoned TLP", reg, PCI_AER_UC_POISONED_TLP); 1931 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 1932 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 1933 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 1934 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 1935 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 1936 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 1937 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 1938 onoff("Unsupported Request Error", reg, 1939 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 1940 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 1941 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 1942 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 1943 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 1944 onoff("TLP Prefix Blocked Error", reg, 1945 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 1946 } 1947 1948 static void 1949 pci_conf_print_aer_cap_cor(pcireg_t reg) 1950 { 1951 1952 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 1953 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 1954 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 1955 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 1956 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 1957 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 1958 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 1959 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 1960 } 1961 1962 static void 1963 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 1964 { 1965 1966 printf(" First Error Pointer: 0x%04x\n", 1967 (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 1968 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 1969 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 1970 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 1971 onoff("ECRC Check Enab", reg, PCI_AER_ECRC_CHECK_ENABLE); 1972 onoff("Multiple Header Recording Capable", reg, 1973 PCI_AER_MULT_HDR_CAPABLE); 1974 onoff("Multiple Header Recording Enable", reg, PCI_AER_MULT_HDR_ENABLE); 1975 1976 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 1977 if (!tlp_prefix_log) 1978 return; 1979 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 1980 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 1981 } 1982 1983 static void 1984 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 1985 { 1986 1987 onoff("Correctable Error Reporting Enable", reg, 1988 PCI_AER_ROOTERR_COR_ENABLE); 1989 onoff("Non-Fatal Error Reporting Enable", reg, 1990 PCI_AER_ROOTERR_NF_ENABLE); 1991 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 1992 } 1993 1994 static void 1995 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 1996 { 1997 1998 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 1999 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2000 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2001 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2002 PCI_AER_ROOTERR_MULTI_UC_ERR); 2003 onoff("First Uncorrectable Fatal", reg, PCI_AER_ROOTERR_FIRST_UC_FATAL); 2004 onoff("Non-Fatal Error Messages Received", reg, PCI_AER_ROOTERR_NF_ERR); 2005 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2006 printf(" Advanced Error Interrupt Message Number: 0x%u\n", 2007 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2008 } 2009 2010 static void 2011 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2012 { 2013 2014 printf(" Correctable Source ID: 0x%04x\n", 2015 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2016 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2017 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2018 } 2019 2020 static void 2021 pci_conf_print_aer_cap(const pcireg_t *regs, int capoff, int extcapoff) 2022 { 2023 pcireg_t reg; 2024 int pcie_capoff; 2025 int pcie_devtype = -1; 2026 bool tlp_prefix_log = false; 2027 2028 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2029 reg = regs[o2i(pcie_capoff)]; 2030 pcie_devtype = reg & PCIE_XCAP_TYPE_MASK; 2031 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2032 if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2033 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2034 /* End-End TLP Prefix Supported */ 2035 if (reg & PCIE_DCAP2_EETLP_PREF) { 2036 tlp_prefix_log = true; 2037 } 2038 } 2039 } 2040 2041 printf("\n Advanced Error Reporting Register\n"); 2042 2043 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2044 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2045 pci_conf_print_aer_cap_uc(reg); 2046 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2047 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2048 pci_conf_print_aer_cap_uc(reg); 2049 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2050 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2051 pci_conf_print_aer_cap_uc(reg); 2052 2053 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2054 printf(" Correctable Error Status register: 0x%08x\n", reg); 2055 pci_conf_print_aer_cap_cor(reg); 2056 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2057 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2058 pci_conf_print_aer_cap_cor(reg); 2059 2060 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2061 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2062 reg); 2063 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2064 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2065 printf(" Header Log register:\n"); 2066 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2067 extcapoff + PCI_AER_ROOTERR_CMD); 2068 2069 switch (pcie_devtype) { 2070 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ 2071 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ 2072 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2073 printf(" Root Error Command register: 0x%08x\n", reg); 2074 pci_conf_print_aer_cap_rooterr_cmd(reg); 2075 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2076 printf(" Root Error Status register: 0x%08x\n", reg); 2077 pci_conf_print_aer_cap_rooterr_status(reg); 2078 2079 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2080 printf(" Error Source Identification: 0x%04x\n", reg); 2081 pci_conf_print_aer_cap_errsrc_id(reg); 2082 break; 2083 } 2084 2085 if (tlp_prefix_log) { 2086 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2087 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2088 } 2089 } 2090 2091 static void 2092 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2093 pcireg_t parbsel, int parbsize) 2094 { 2095 pcireg_t reg; 2096 int num = 16 << parbsel; 2097 int num_per_reg = sizeof(pcireg_t) / parbsize; 2098 int i, j; 2099 2100 /* First, dump the table */ 2101 for (i = 0; i < num; i += num_per_reg) { 2102 reg = regs[o2i(off + i / num_per_reg)]; 2103 printf(" %s Arbitration Table: 0x%08x\n", name, reg); 2104 } 2105 /* And then, decode each entry */ 2106 for (i = 0; i < num; i += num_per_reg) { 2107 reg = regs[o2i(off + i / num_per_reg)]; 2108 for (j = 0; j < num_per_reg; j++) 2109 printf(" Phase[%d]: %d\n", j, reg); 2110 } 2111 } 2112 2113 static void 2114 pci_conf_print_vc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2115 { 2116 pcireg_t reg, n; 2117 int parbtab, parbsize; 2118 pcireg_t parbsel; 2119 int varbtab, varbsize; 2120 pcireg_t varbsel; 2121 int i, count; 2122 2123 printf("\n Virtual Channel Register\n"); 2124 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2125 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2126 count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2127 printf(" Extended VC Count: %d\n", count); 2128 n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2129 printf(" Low Priority Extended VC Count: %u\n", n); 2130 n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2131 printf(" Reference Clock: %s\n", 2132 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100" : "unknown"); 2133 parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2134 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2135 2136 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 2137 printf(" Port VC Capability register 2: 0x%08x\n", reg); 2138 onoff("Hardware fixed arbitration scheme", 2139 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 2140 onoff("WRR arbitration with 32 phases", 2141 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 2142 onoff("WRR arbitration with 64 phases", 2143 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 2144 onoff("WRR arbitration with 128 phases", 2145 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 2146 varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 2147 printf(" VC Arbitration Table Offset: 0x%x\n", varbtab); 2148 2149 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 2150 printf(" Port VC Control register: 0x%04x\n", reg); 2151 varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 2152 printf(" VC Arbitration Select: 0x%x\n", varbsel); 2153 2154 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 2155 printf(" Port VC Status register: 0x%04x\n", reg); 2156 onoff("VC Arbitration Table Status", 2157 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 2158 2159 for (i = 0; i < count + 1; i++) { 2160 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 2161 printf(" VC number %d\n", i); 2162 printf(" VC Resource Capability Register: 0x%08x\n", reg); 2163 onoff(" Non-configurable Hardware fixed arbitration scheme", 2164 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 2165 onoff(" WRR arbitration with 32 phases", 2166 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 2167 onoff(" WRR arbitration with 64 phases", 2168 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 2169 onoff(" WRR arbitration with 128 phases", 2170 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 2171 onoff(" Time-based WRR arbitration with 128 phases", 2172 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 2173 onoff(" WRR arbitration with 256 phases", 2174 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 2175 onoff(" Advanced Packet Switching", 2176 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 2177 onoff(" Reject Snoop Transaction", 2178 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 2179 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 2180 printf(" Maximum Time Slots: %d\n", n); 2181 parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S; 2182 printf(" Port Arbitration Table offset: 0x%02x\n", 2183 parbtab); 2184 2185 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 2186 printf(" VC Resource Control Register: 0x%08x\n", reg); 2187 printf(" TC/VC Map: %02x\n", 2188 (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 2189 /* 2190 * The load Port Arbitration Table bit is used to update 2191 * the Port Arbitration logic and it's always 0 on read, so 2192 * we don't print it. 2193 */ 2194 parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 2195 printf(" Port Arbitration Select: %x\n", parbsel); 2196 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 2197 printf(" VC ID %d\n", n); 2198 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 2199 2200 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 2201 printf(" VC Resource Status Register: 0x%08x\n", reg); 2202 onoff(" Port Arbitration Table Status", 2203 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 2204 onoff(" VC Negotiation Pending", 2205 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 2206 2207 if ((parbtab != 0) && (parbsel != 0)) 2208 pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab, 2209 "Port", parbsel, parbsize); 2210 } 2211 2212 varbsize = 8; 2213 if ((varbtab != 0) && (varbsel != 0)) 2214 pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab, 2215 " VC", varbsel, varbsize); 2216 } 2217 2218 static const char * 2219 pci_conf_print_pwrbdgt_base_power(uint8_t reg) 2220 { 2221 2222 switch (reg) { 2223 case 0xf0: 2224 return "250W"; 2225 case 0xf1: 2226 return "275W"; 2227 case 0xf2: 2228 return "300W"; 2229 default: 2230 return "Unknown"; 2231 } 2232 } 2233 2234 static const char * 2235 pci_conf_print_pwrbdgt_data_scale(uint8_t reg) 2236 { 2237 2238 switch (reg) { 2239 case 0x00: 2240 return "1.0x"; 2241 case 0x01: 2242 return "0.1x"; 2243 case 0x02: 2244 return "0.01x"; 2245 case 0x03: 2246 return "0.001x"; 2247 default: 2248 return "wrong value!"; 2249 } 2250 } 2251 2252 static const char * 2253 pci_conf_print_pwrbdgt_type(uint8_t reg) 2254 { 2255 2256 switch (reg) { 2257 case 0x00: 2258 return "PME Aux"; 2259 case 0x01: 2260 return "Auxilary"; 2261 case 0x02: 2262 return "Idle"; 2263 case 0x03: 2264 return "Sustained"; 2265 case 0x07: 2266 return "Maximun"; 2267 default: 2268 return "Unknown"; 2269 } 2270 } 2271 2272 static const char * 2273 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 2274 { 2275 2276 switch (reg) { 2277 case 0x00: 2278 return "Power(12V)"; 2279 case 0x01: 2280 return "Power(3.3V)"; 2281 case 0x02: 2282 return "Power(1.5V or 1.8V)"; 2283 case 0x07: 2284 return "Thermal"; 2285 default: 2286 return "Unknown"; 2287 } 2288 } 2289 2290 static void 2291 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff) 2292 { 2293 pcireg_t reg; 2294 2295 printf("\n Power Budget Register\n"); 2296 2297 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 2298 printf(" Data Select register: 0x%08x\n", reg); 2299 2300 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 2301 printf(" Data register: 0x%08x\n", reg); 2302 printf(" Base Power: %s\n", 2303 pci_conf_print_pwrbdgt_base_power((uint8_t)reg)); 2304 printf(" Data Scale: %s\n", 2305 pci_conf_print_pwrbdgt_data_scale( 2306 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE)))); 2307 printf(" PM Sub State: 0x%hhx\n", 2308 (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 2309 printf(" PM State: D%u\n", 2310 (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 2311 printf(" Type: %s\n", 2312 pci_conf_print_pwrbdgt_type( 2313 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 2314 printf(" Power Rail: %s\n", 2315 pci_conf_print_pwrbdgt_pwrrail( 2316 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 2317 2318 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 2319 printf(" Power Budget Capability register: 0x%08x\n", reg); 2320 onoff("System Allocated", 2321 reg, PCI_PWRBDGT_CAP_SYSALLOC); 2322 } 2323 2324 static const char * 2325 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 2326 { 2327 2328 switch (type) { 2329 case 0x00: 2330 return "Configuration Space Element"; 2331 case 0x01: 2332 return "System Egress Port or internal sink (memory)"; 2333 case 0x02: 2334 return "Internal Root Complex Link"; 2335 default: 2336 return "Unknown"; 2337 } 2338 } 2339 2340 static void 2341 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int capoff, int extcapoff) 2342 { 2343 pcireg_t reg; 2344 unsigned char nent, linktype; 2345 int i; 2346 2347 printf("\n Root Complex Link Declaration\n"); 2348 2349 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 2350 printf(" Element Self Description Register: 0x%08x\n", reg); 2351 printf(" Element Type: %s\n", 2352 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 2353 nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 2354 printf(" Number of Link Entries: %hhu\n", nent); 2355 printf(" Component ID: %hhu\n", 2356 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 2357 printf(" Port Number: %hhu\n", 2358 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 2359 for (i = 0; i < nent; i++) { 2360 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 2361 printf(" Link Description Register: 0x%08x\n", reg); 2362 onoff("Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID); 2363 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 2364 onoff2("Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 2365 "Configuration Space", "Memory-Mapped Space"); 2366 onoff("Associated RCRB Header", reg, 2367 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 2368 printf(" Target Component ID: %hhu\n", 2369 (unsigned char)__SHIFTOUT(reg, 2370 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 2371 printf(" Target Port Number: %hhu\n", 2372 (unsigned char)__SHIFTOUT(reg, 2373 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 2374 2375 if (linktype == 0) { 2376 /* Memory-Mapped Space */ 2377 reg = regs[o2i(extcapoff 2378 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 2379 printf(" Link Address Low Register: 0x%08x\n", reg); 2380 reg = regs[o2i(extcapoff 2381 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 2382 printf(" Link Address High Register: 0x%08x\n",reg); 2383 } else { 2384 unsigned int nb; 2385 pcireg_t lo, hi; 2386 2387 /* Configuration Space */ 2388 lo = regs[o2i(extcapoff 2389 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 2390 printf(" Configuration Space Low Register: 0x%08x" 2391 "\n", lo); 2392 hi = regs[o2i(extcapoff 2393 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 2394 printf(" Configuration Space High Register: 0x%08x" 2395 "\n", hi); 2396 nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 2397 printf(" N: %u\n", nb); 2398 printf(" Func: %hhu\n", 2399 (unsigned char)__SHIFTOUT(lo, 2400 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 2401 printf(" Dev: %hhu\n", 2402 (unsigned char)__SHIFTOUT(lo, 2403 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 2404 printf(" Bus: %hhu\n", 2405 (unsigned char)__SHIFTOUT(lo, 2406 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 2407 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 2408 printf(" Configuration Space Base Address: 0x%016" 2409 PRIx64 "\n", ((uint64_t)hi << 32) + lo); 2410 } 2411 } 2412 } 2413 2414 /* XXX pci_conf_print_rclink_ctl_cap */ 2415 2416 static void 2417 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2418 { 2419 pcireg_t reg; 2420 2421 printf("\n Root Complex Event Collector Association\n"); 2422 2423 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 2424 printf(" Association Bitmap for Root Complex Integrated Devices:" 2425 " 0x%08x\n", reg); 2426 } 2427 2428 /* XXX pci_conf_print_mfvc_cap */ 2429 /* XXX pci_conf_print_vc2_cap */ 2430 /* XXX pci_conf_print_rcrb_cap */ 2431 /* XXX pci_conf_print_vendor_cap */ 2432 /* XXX pci_conf_print_cac_cap */ 2433 2434 static void 2435 pci_conf_print_acs_cap(const pcireg_t *regs, int capoff, int extcapoff) 2436 { 2437 pcireg_t reg, cap, ctl; 2438 unsigned int size, i; 2439 2440 printf("\n Access Control Services\n"); 2441 2442 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 2443 cap = reg & 0xffff; 2444 ctl = reg >> 16; 2445 printf(" ACS Capability register: 0x%08x\n", cap); 2446 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 2447 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 2448 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 2449 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 2450 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 2451 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 2452 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 2453 size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 2454 if (size == 0) 2455 size = 256; 2456 printf(" Egress Control Vector Size: %u\n", size); 2457 printf(" ACS Control register: 0x%08x\n", ctl); 2458 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 2459 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 2460 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 2461 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 2462 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 2463 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 2464 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 2465 2466 /* 2467 * If the P2P Egress Control Capability bit is 0, ignore the Egress 2468 * Control vector. 2469 */ 2470 if ((cap & PCI_ACS_CAP_E) == 0) 2471 return; 2472 for (i = 0; i < size; i += 32) 2473 printf(" Egress Control Vector [%u..%u]: %x\n", i + 31, 2474 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 2475 } 2476 2477 static void 2478 pci_conf_print_ari_cap(const pcireg_t *regs, int capoff, int extcapoff) 2479 { 2480 pcireg_t reg, cap, ctl; 2481 2482 printf("\n Alternative Routing-ID Interpretation Register\n"); 2483 2484 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2485 cap = reg & 0xffff; 2486 ctl = reg >> 16; 2487 printf(" Capability register: 0x%08x\n", cap); 2488 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 2489 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 2490 printf(" Next Function Number: %u\n", 2491 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 2492 printf(" Control register: 0x%08x\n", ctl); 2493 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 2494 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 2495 printf(" Function Group: %u\n", 2496 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 2497 } 2498 2499 static void 2500 pci_conf_print_ats_cap(const pcireg_t *regs, int capoff, int extcapoff) 2501 { 2502 pcireg_t reg, cap, ctl; 2503 unsigned int num; 2504 2505 printf("\n Address Translation Services\n"); 2506 2507 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2508 cap = reg & 0xffff; 2509 ctl = reg >> 16; 2510 printf(" Capability register: 0x%04x\n", cap); 2511 num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 2512 if (num == 0) 2513 num = 32; 2514 printf(" Invalidate Queue Depth: %u\n", num); 2515 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 2516 2517 printf(" Control register: 0x%04x\n", ctl); 2518 printf(" Smallest Translation Unit: %u\n", 2519 (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU)); 2520 onoff("Enable", reg, PCI_ATS_CTL_EN); 2521 } 2522 2523 static void 2524 pci_conf_print_sernum_cap(const pcireg_t *regs, int capoff, int extcapoff) 2525 { 2526 pcireg_t lo, hi; 2527 2528 printf("\n Device Serial Number Register\n"); 2529 2530 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 2531 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 2532 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 2533 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 2534 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 2535 } 2536 2537 static void 2538 pci_conf_print_sriov_cap(const pcireg_t *regs, int capoff, int extcapoff) 2539 { 2540 char buf[sizeof("99999 MB")]; 2541 pcireg_t reg; 2542 pcireg_t total_vfs; 2543 int i; 2544 bool first; 2545 2546 printf("\n Single Root IO Virtualization Register\n"); 2547 2548 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 2549 printf(" Capabilities register: 0x%08x\n", reg); 2550 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 2551 onoff("ARI Capable Hierarchy Preserved", reg, 2552 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 2553 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 2554 printf(" VF Migration Interrupt Message Number: 0x%u\n", 2555 (pcireg_t)__SHIFTOUT(reg, 2556 PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 2557 } 2558 2559 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 2560 printf(" Control register: 0x%04x\n", reg); 2561 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 2562 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 2563 onoff("VF Migration Interrupt Enable", reg, 2564 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 2565 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 2566 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 2567 2568 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 2569 printf(" Status register: 0x%04x\n", reg); 2570 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 2571 2572 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 2573 printf(" InitialVFs register: 0x%04x\n", reg); 2574 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 2575 printf(" TotalVFs register: 0x%04x\n", reg); 2576 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 2577 printf(" NumVFs register: 0x%04x\n", reg); 2578 2579 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 2580 printf(" Function Dependency Link register: 0x%04x\n", reg); 2581 2582 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 2583 printf(" First VF Offset register: 0x%04x\n", reg); 2584 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 2585 printf(" VF Stride register: 0x%04x\n", reg); 2586 2587 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 2588 printf(" Supported Page Sizes register: 0x%08x\n", reg); 2589 printf(" Supported Page Size:"); 2590 for (i = 0, first = true; i < 32; i++) { 2591 if (reg & __BIT(i)) { 2592 #ifdef _KERNEL 2593 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 2594 #else 2595 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 2596 HN_AUTOSCALE, 0); 2597 #endif 2598 printf("%s %s", first ? "" : ",", buf); 2599 first = false; 2600 } 2601 } 2602 printf("\n"); 2603 2604 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 2605 printf(" System Page Sizes register: 0x%08x\n", reg); 2606 printf(" Page Size: "); 2607 if (reg != 0) { 2608 #ifdef _KERNEL 2609 format_bytes(buf, sizeof(buf), 1LL << (ffs(reg) + 12)); 2610 #else 2611 humanize_number(buf, sizeof(buf), 1LL << (ffs(reg) + 12), "B", 2612 HN_AUTOSCALE, 0); 2613 #endif 2614 printf("%s", buf); 2615 } else { 2616 printf("unknown"); 2617 } 2618 printf("\n"); 2619 2620 for (i = 0; i < 6; i++) { 2621 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 2622 printf(" VF BAR%d register: 0x%08x\n", i, reg); 2623 } 2624 2625 if (total_vfs > 0) { 2626 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 2627 printf(" VF Migration State Array Offset register: 0x%08x\n", 2628 reg); 2629 printf(" VF Migration State Offset: 0x%08x\n", 2630 (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 2631 i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 2632 printf(" VF Migration State BIR: "); 2633 if (i >= 0 && i <= 5) { 2634 printf("BAR%d", i); 2635 } else { 2636 printf("unknown BAR (%d)", i); 2637 } 2638 printf("\n"); 2639 } 2640 } 2641 2642 /* XXX pci_conf_print_mriov_cap */ 2643 /* XXX pci_conf_print_multicast_cap */ 2644 2645 static void 2646 pci_conf_print_page_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 2647 { 2648 pcireg_t reg, ctl, sta; 2649 2650 printf("\n Page Request\n"); 2651 2652 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 2653 ctl = reg & 0xffff; 2654 sta = reg >> 16; 2655 printf(" Control Register: 0x%04x\n", ctl); 2656 onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E); 2657 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 2658 2659 printf(" Status Register: 0x%04x\n", sta); 2660 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 2661 onoff("Unexpected Page Request Group Index", reg, 2662 PCI_PAGE_REQ_STA_UPRGI); 2663 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 2664 2665 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 2666 printf(" Outstanding Page Request Capacity: %u\n", reg); 2667 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 2668 printf(" Outstanding Page Request Allocation: %u\n", reg); 2669 } 2670 2671 /* XXX pci_conf_print_amd_cap */ 2672 /* XXX pci_conf_print_resize_bar_cap */ 2673 /* XXX pci_conf_print_dpa_cap */ 2674 2675 static const char * 2676 pci_conf_print_tph_req_cap_sttabloc(unsigned char val) 2677 { 2678 2679 switch (val) { 2680 case 0x0: 2681 return "Not Present"; 2682 case 0x1: 2683 return "in the TPH Requester Capability Structure"; 2684 case 0x2: 2685 return "in the MSI-X Table"; 2686 default: 2687 return "Unknown"; 2688 } 2689 } 2690 2691 static void 2692 pci_conf_print_tph_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 2693 { 2694 pcireg_t reg; 2695 int size, i, j; 2696 2697 printf("\n TPH Requester Extended Capability\n"); 2698 2699 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 2700 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 2701 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 2702 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 2703 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 2704 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 2705 printf(" ST Table Location: %s\n", 2706 pci_conf_print_tph_req_cap_sttabloc( 2707 (unsigned char)__SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC))); 2708 size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 2709 printf(" ST Table Size: %d\n", size); 2710 for (i = 0; i < size ; i += 2) { 2711 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 2712 for (j = 0; j < 2 ; j++) { 2713 uint16_t entry = reg; 2714 2715 if (j != 0) 2716 entry >>= 16; 2717 entry &= 0xffff; 2718 printf(" TPH ST Table Entry (%d): 0x%04hx\n", 2719 i + j, entry); 2720 } 2721 } 2722 } 2723 2724 static void 2725 pci_conf_print_ltr_cap(const pcireg_t *regs, int capoff, int extcapoff) 2726 { 2727 pcireg_t reg; 2728 2729 printf("\n Latency Tolerance Reporting\n"); 2730 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)] & 0xffff; 2731 printf(" Max Snoop Latency Register: 0x%04x\n", reg); 2732 printf(" Max Snoop LatencyValue: %u\n", 2733 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL)); 2734 printf(" Max Snoop LatencyScale: %uns\n", 2735 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE))); 2736 reg = regs[o2i(extcapoff + PCI_LTR_MAXNOSNOOPLAT)] >> 16; 2737 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg); 2738 printf(" Max No-Snoop LatencyValue: %u\n", 2739 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL)); 2740 printf(" Max No-Snoop LatencyScale: %uns\n", 2741 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE))); 2742 } 2743 2744 static void 2745 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int capoff, int extcapoff) 2746 { 2747 int pcie_capoff; 2748 pcireg_t reg; 2749 int i, maxlinkwidth; 2750 2751 printf("\n Secondary PCI Express Register\n"); 2752 2753 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 2754 printf(" Link Control 3 register: 0x%08x\n", reg); 2755 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 2756 onoff("Link Equalization Request Interrupt Enable", 2757 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 2758 2759 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 2760 printf(" Lane Error Status register: 0x%08x\n", reg); 2761 2762 /* Get Max Link Width */ 2763 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)){ 2764 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 2765 maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 2766 } else { 2767 printf("error: falied to get PCIe capablity\n"); 2768 return; 2769 } 2770 for (i = 0; i < maxlinkwidth; i++) { 2771 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 2772 if (i % 2 != 0) 2773 reg >>= 16; 2774 else 2775 reg &= 0xffff; 2776 printf(" Equalization Control Register (Link %d): %04x\n", 2777 i, reg); 2778 printf(" Downstream Port Transmit Preset: 0x%x\n", 2779 (pcireg_t)__SHIFTOUT(reg, 2780 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 2781 printf(" Downstream Port Receive Hint: 0x%x\n", 2782 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 2783 printf(" Upstream Port Transmit Preset: 0x%x\n", 2784 (pcireg_t)__SHIFTOUT(reg, 2785 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 2786 printf(" Upstream Port Receive Hint: 0x%x\n", 2787 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 2788 } 2789 } 2790 2791 /* XXX pci_conf_print_pmux_cap */ 2792 2793 static void 2794 pci_conf_print_pasid_cap(const pcireg_t *regs, int capoff, int extcapoff) 2795 { 2796 pcireg_t reg, cap, ctl; 2797 unsigned int num; 2798 2799 printf("\n Process Address Space ID\n"); 2800 2801 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 2802 cap = reg & 0xffff; 2803 ctl = reg >> 16; 2804 printf(" PASID Capability Register: 0x%04x\n", cap); 2805 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 2806 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 2807 num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 2808 printf(" Max PASID Width: %u\n", num); 2809 2810 printf(" PASID Control Register: 0x%04x\n", ctl); 2811 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 2812 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 2813 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 2814 } 2815 2816 static void 2817 pci_conf_print_lnr_cap(const pcireg_t *regs, int capoff, int extcapoff) 2818 { 2819 pcireg_t reg, cap, ctl; 2820 unsigned int num; 2821 2822 printf("\n LN Requester\n"); 2823 2824 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 2825 cap = reg & 0xffff; 2826 ctl = reg >> 16; 2827 printf(" LNR Capability register: 0x%04x\n", cap); 2828 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 2829 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 2830 num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 2831 printf(" LNR Registration MAX: %u\n", num); 2832 2833 printf(" LNR Control register: 0x%04x\n", ctl); 2834 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 2835 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 2836 num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 2837 printf(" LNR Registration Limit: %u\n", num); 2838 } 2839 2840 /* XXX pci_conf_print_dpc_cap */ 2841 2842 static int 2843 pci_conf_l1pm_cap_tposcale(unsigned char scale) 2844 { 2845 2846 /* Return scale in us */ 2847 switch (scale) { 2848 case 0x0: 2849 return 2; 2850 case 0x1: 2851 return 10; 2852 case 0x2: 2853 return 100; 2854 default: 2855 return -1; 2856 } 2857 } 2858 2859 static void 2860 pci_conf_print_l1pm_cap(const pcireg_t *regs, int capoff, int extcapoff) 2861 { 2862 pcireg_t reg; 2863 int scale, val; 2864 2865 printf("\n L1 PM Substates\n"); 2866 2867 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 2868 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 2869 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 2870 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 2871 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 2872 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 2873 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 2874 printf(" Port Common Mode Restore Time: %uus\n", 2875 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 2876 scale = pci_conf_l1pm_cap_tposcale( 2877 __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 2878 val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 2879 printf(" Port T_POWER_ON: "); 2880 if (scale == -1) 2881 printf("unknown\n"); 2882 else 2883 printf("%dus\n", val * scale); 2884 2885 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 2886 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 2887 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 2888 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 2889 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 2890 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 2891 printf(" Common Mode Restore Time: %uus\n", 2892 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 2893 scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 2894 val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 2895 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 2896 2897 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 2898 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 2899 scale = pci_conf_l1pm_cap_tposcale( 2900 __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 2901 val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 2902 printf(" T_POWER_ON: "); 2903 if (scale == -1) 2904 printf("unknown\n"); 2905 else 2906 printf("%dus\n", val * scale); 2907 } 2908 2909 /* XXX pci_conf_print_ptm_cap */ 2910 /* XXX pci_conf_print_mpcie_cap */ 2911 /* XXX pci_conf_print_frsq_cap */ 2912 /* XXX pci_conf_print_rtr_cap */ 2913 /* XXX pci_conf_print_desigvndsp_cap */ 2914 2915 #undef MS 2916 #undef SM 2917 #undef RW 2918 2919 static struct { 2920 pcireg_t cap; 2921 const char *name; 2922 void (*printfunc)(const pcireg_t *, int, int); 2923 } pci_extcaptab[] = { 2924 { 0, "reserved", 2925 NULL }, 2926 { PCI_EXTCAP_AER, "Advanced Error Reporting", 2927 pci_conf_print_aer_cap }, 2928 { PCI_EXTCAP_VC, "Virtual Channel", 2929 pci_conf_print_vc_cap }, 2930 { PCI_EXTCAP_SERNUM, "Device Serial Number", 2931 pci_conf_print_sernum_cap }, 2932 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 2933 pci_conf_print_pwrbdgt_cap }, 2934 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 2935 pci_conf_print_rclink_dcl_cap }, 2936 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 2937 NULL }, 2938 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 2939 pci_conf_print_rcec_assoc_cap }, 2940 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 2941 NULL }, 2942 { PCI_EXTCAP_VC2, "Virtual Channel", 2943 NULL }, 2944 { PCI_EXTCAP_RCRB, "RCRB Header", 2945 NULL }, 2946 { PCI_EXTCAP_VENDOR, "Vendor Unique", 2947 NULL }, 2948 { PCI_EXTCAP_CAC, "Configuration Access Correction", 2949 NULL }, 2950 { PCI_EXTCAP_ACS, "Access Control Services", 2951 pci_conf_print_acs_cap }, 2952 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 2953 pci_conf_print_ari_cap }, 2954 { PCI_EXTCAP_ATS, "Address Translation Services", 2955 pci_conf_print_ats_cap }, 2956 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 2957 pci_conf_print_sriov_cap }, 2958 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 2959 NULL }, 2960 { PCI_EXTCAP_MULTICAST, "Multicast", 2961 NULL }, 2962 { PCI_EXTCAP_PAGE_REQ, "Page Request", 2963 pci_conf_print_page_req_cap }, 2964 { PCI_EXTCAP_AMD, "Reserved for AMD", 2965 NULL }, 2966 { PCI_EXTCAP_RESIZE_BAR,"Resizable BAR", 2967 NULL }, 2968 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 2969 NULL }, 2970 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 2971 pci_conf_print_tph_req_cap }, 2972 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 2973 pci_conf_print_ltr_cap }, 2974 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 2975 pci_conf_print_sec_pcie_cap }, 2976 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 2977 NULL }, 2978 { PCI_EXTCAP_PASID, "Process Address Space ID", 2979 pci_conf_print_pasid_cap }, 2980 { PCI_EXTCAP_LN_REQ, "LN Requester", 2981 pci_conf_print_lnr_cap }, 2982 { PCI_EXTCAP_DPC, "Downstream Port Containment", 2983 NULL }, 2984 { PCI_EXTCAP_L1PM, "L1 PM Substates", 2985 pci_conf_print_l1pm_cap }, 2986 { PCI_EXTCAP_PTM, "Precision Time Management", 2987 NULL }, 2988 { PCI_EXTCAP_MPCIE, "M-PCIe", 2989 NULL }, 2990 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 2991 NULL }, 2992 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 2993 NULL }, 2994 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 2995 NULL }, 2996 }; 2997 2998 static int 2999 pci_conf_find_extcap(const pcireg_t *regs, int capoff, unsigned int capid, 3000 int *offsetp) 3001 { 3002 int off; 3003 pcireg_t rval; 3004 3005 for (off = PCI_EXTCAPLIST_BASE; 3006 off != 0; 3007 off = PCI_EXTCAPLIST_NEXT(rval)) { 3008 rval = regs[o2i(off)]; 3009 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 3010 if (offsetp != NULL) 3011 *offsetp = off; 3012 return 1; 3013 } 3014 } 3015 return 0; 3016 } 3017 3018 static void 3019 pci_conf_print_extcaplist( 3020 #ifdef _KERNEL 3021 pci_chipset_tag_t pc, pcitag_t tag, 3022 #endif 3023 const pcireg_t *regs, int capoff) 3024 { 3025 int off; 3026 pcireg_t foundcap; 3027 pcireg_t rval; 3028 bool foundtable[__arraycount(pci_extcaptab)]; 3029 unsigned int i; 3030 3031 /* Check Extended capability structure */ 3032 off = PCI_EXTCAPLIST_BASE; 3033 rval = regs[o2i(off)]; 3034 if (rval == 0xffffffff || rval == 0) 3035 return; 3036 3037 /* Clear table */ 3038 for (i = 0; i < __arraycount(pci_extcaptab); i++) 3039 foundtable[i] = false; 3040 3041 /* Print extended capability register's offset and the type first */ 3042 for (;;) { 3043 printf(" Extended Capability Register at 0x%02x\n", off); 3044 3045 foundcap = PCI_EXTCAPLIST_CAP(rval); 3046 printf(" type: 0x%04x (", foundcap); 3047 if (foundcap < __arraycount(pci_extcaptab)) { 3048 printf("%s)\n", pci_extcaptab[foundcap].name); 3049 /* Mark as found */ 3050 foundtable[foundcap] = true; 3051 } else 3052 printf("unknown)\n"); 3053 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 3054 3055 off = PCI_EXTCAPLIST_NEXT(rval); 3056 if (off == 0) 3057 break; 3058 rval = regs[o2i(off)]; 3059 } 3060 3061 /* 3062 * And then, print the detail of each capability registers 3063 * in capability value's order. 3064 */ 3065 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 3066 if (foundtable[i] == false) 3067 continue; 3068 3069 /* 3070 * The type was found. Search capability list again and 3071 * print all capabilities that the capabiliy type is 3072 * the same. 3073 */ 3074 if (pci_conf_find_extcap(regs, capoff, i, &off) == 0) 3075 continue; 3076 rval = regs[o2i(off)]; 3077 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 3078 || (pci_extcaptab[i].printfunc == NULL)) 3079 continue; 3080 3081 pci_extcaptab[i].printfunc(regs, capoff, off); 3082 3083 } 3084 } 3085 3086 /* Print the Secondary Status Register. */ 3087 static void 3088 pci_conf_print_ssr(pcireg_t rval) 3089 { 3090 pcireg_t devsel; 3091 3092 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 3093 onoff("66 MHz capable", rval, __BIT(5)); 3094 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 3095 onoff("Fast back-to-back capable", rval, __BIT(7)); 3096 onoff("Data parity error detected", rval, __BIT(8)); 3097 3098 printf(" DEVSEL timing: "); 3099 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 3100 switch (devsel) { 3101 case 0: 3102 printf("fast"); 3103 break; 3104 case 1: 3105 printf("medium"); 3106 break; 3107 case 2: 3108 printf("slow"); 3109 break; 3110 default: 3111 printf("unknown/reserved"); /* XXX */ 3112 break; 3113 } 3114 printf(" (0x%x)\n", devsel); 3115 3116 onoff("Signalled target abort", rval, __BIT(11)); 3117 onoff("Received target abort", rval, __BIT(12)); 3118 onoff("Received master abort", rval, __BIT(13)); 3119 onoff("Received system error", rval, __BIT(14)); 3120 onoff("Detected parity error", rval, __BIT(15)); 3121 } 3122 3123 static void 3124 pci_conf_print_type0( 3125 #ifdef _KERNEL 3126 pci_chipset_tag_t pc, pcitag_t tag, 3127 #endif 3128 const pcireg_t *regs 3129 #ifdef _KERNEL 3130 , int sizebars 3131 #endif 3132 ) 3133 { 3134 int off, width; 3135 pcireg_t rval; 3136 3137 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 3138 #ifdef _KERNEL 3139 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3140 #else 3141 width = pci_conf_print_bar(regs, off, NULL); 3142 #endif 3143 } 3144 3145 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 3146 3147 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 3148 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 3149 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 3150 3151 /* XXX */ 3152 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 3153 3154 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3155 printf(" Capability list pointer: 0x%02x\n", 3156 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 3157 else 3158 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 3159 3160 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 3161 3162 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3163 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 3164 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 3165 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 3166 switch (PCI_INTERRUPT_PIN(rval)) { 3167 case PCI_INTERRUPT_PIN_NONE: 3168 printf("(none)"); 3169 break; 3170 case PCI_INTERRUPT_PIN_A: 3171 printf("(pin A)"); 3172 break; 3173 case PCI_INTERRUPT_PIN_B: 3174 printf("(pin B)"); 3175 break; 3176 case PCI_INTERRUPT_PIN_C: 3177 printf("(pin C)"); 3178 break; 3179 case PCI_INTERRUPT_PIN_D: 3180 printf("(pin D)"); 3181 break; 3182 default: 3183 printf("(? ? ?)"); 3184 break; 3185 } 3186 printf("\n"); 3187 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 3188 } 3189 3190 static void 3191 pci_conf_print_type1( 3192 #ifdef _KERNEL 3193 pci_chipset_tag_t pc, pcitag_t tag, 3194 #endif 3195 const pcireg_t *regs 3196 #ifdef _KERNEL 3197 , int sizebars 3198 #endif 3199 ) 3200 { 3201 int off, width; 3202 pcireg_t rval; 3203 uint32_t base, limit; 3204 uint32_t base_h, limit_h; 3205 uint64_t pbase, plimit; 3206 int use_upper; 3207 3208 /* 3209 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 3210 * Bridge chip documentation, and may not be correct with 3211 * respect to various standards. (XXX) 3212 */ 3213 3214 for (off = 0x10; off < 0x18; off += width) { 3215 #ifdef _KERNEL 3216 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3217 #else 3218 width = pci_conf_print_bar(regs, off, NULL); 3219 #endif 3220 } 3221 3222 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 3223 printf(" Primary bus number: 0x%02x\n", 3224 PCI_BRIDGE_BUS_PRIMARY(rval)); 3225 printf(" Secondary bus number: 0x%02x\n", 3226 PCI_BRIDGE_BUS_SECONDARY(rval)); 3227 printf(" Subordinate bus number: 0x%02x\n", 3228 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 3229 printf(" Secondary bus latency timer: 0x%02x\n", 3230 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 3231 3232 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 3233 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 3234 3235 /* I/O region */ 3236 printf(" I/O region:\n"); 3237 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 3238 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 3239 if (PCI_BRIDGE_IO_32BITS(rval)) 3240 use_upper = 1; 3241 else 3242 use_upper = 0; 3243 onoff("32bit I/O", rval, use_upper); 3244 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 3245 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 3246 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 3247 limit |= 0x00000fff; 3248 3249 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 3250 base_h = (rval >> 0) & 0xffff; 3251 limit_h = (rval >> 16) & 0xffff; 3252 printf(" base upper 16 bits register: 0x%04x\n", base_h); 3253 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 3254 3255 if (use_upper == 1) { 3256 base |= base_h << 16; 3257 limit |= limit_h << 16; 3258 } 3259 if (base < limit) { 3260 if (use_upper == 1) 3261 printf(" range: 0x%08x-0x%08x\n", base, limit); 3262 else 3263 printf(" range: 0x%04x-0x%04x\n", base, limit); 3264 } else 3265 printf(" range: not set\n"); 3266 3267 /* Non-prefetchable memory region */ 3268 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 3269 printf(" Memory region:\n"); 3270 printf(" base register: 0x%04x\n", 3271 (rval >> 0) & 0xffff); 3272 printf(" limit register: 0x%04x\n", 3273 (rval >> 16) & 0xffff); 3274 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 3275 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 3276 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 3277 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 3278 if (base < limit) 3279 printf(" range: 0x%08x-0x%08x\n", base, limit); 3280 else 3281 printf(" range: not set\n"); 3282 3283 /* Prefetchable memory region */ 3284 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 3285 printf(" Prefetchable memory region:\n"); 3286 printf(" base register: 0x%04x\n", 3287 (rval >> 0) & 0xffff); 3288 printf(" limit register: 0x%04x\n", 3289 (rval >> 16) & 0xffff); 3290 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 3291 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 3292 printf(" base upper 32 bits register: 0x%08x\n", 3293 base_h); 3294 printf(" limit upper 32 bits register: 0x%08x\n", 3295 limit_h); 3296 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 3297 use_upper = 1; 3298 else 3299 use_upper = 0; 3300 onoff("64bit memory address", rval, use_upper); 3301 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 3302 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 3303 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 3304 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 3305 if (use_upper == 1) { 3306 pbase |= (uint64_t)base_h << 32; 3307 plimit |= (uint64_t)limit_h << 32; 3308 } 3309 if (pbase < plimit) { 3310 if (use_upper == 1) 3311 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 3312 "\n", pbase, plimit); 3313 else 3314 printf(" range: 0x%08x-0x%08x\n", 3315 (uint32_t)pbase, (uint32_t)plimit); 3316 } else 3317 printf(" range: not set\n"); 3318 3319 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3320 printf(" Capability list pointer: 0x%02x\n", 3321 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 3322 else 3323 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 3324 3325 /* XXX */ 3326 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 3327 3328 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3329 printf(" Interrupt line: 0x%02x\n", 3330 (rval >> 0) & 0xff); 3331 printf(" Interrupt pin: 0x%02x ", 3332 (rval >> 8) & 0xff); 3333 switch ((rval >> 8) & 0xff) { 3334 case PCI_INTERRUPT_PIN_NONE: 3335 printf("(none)"); 3336 break; 3337 case PCI_INTERRUPT_PIN_A: 3338 printf("(pin A)"); 3339 break; 3340 case PCI_INTERRUPT_PIN_B: 3341 printf("(pin B)"); 3342 break; 3343 case PCI_INTERRUPT_PIN_C: 3344 printf("(pin C)"); 3345 break; 3346 case PCI_INTERRUPT_PIN_D: 3347 printf("(pin D)"); 3348 break; 3349 default: 3350 printf("(? ? ?)"); 3351 break; 3352 } 3353 printf("\n"); 3354 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 3355 & PCI_BRIDGE_CONTROL_MASK; 3356 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 3357 onoff("Parity error response", rval, 0x0001); 3358 onoff("Secondary SERR forwarding", rval, 0x0002); 3359 onoff("ISA enable", rval, 0x0004); 3360 onoff("VGA enable", rval, 0x0008); 3361 onoff("Master abort reporting", rval, 0x0020); 3362 onoff("Secondary bus reset", rval, 0x0040); 3363 onoff("Fast back-to-back capable", rval, 0x0080); 3364 } 3365 3366 static void 3367 pci_conf_print_type2( 3368 #ifdef _KERNEL 3369 pci_chipset_tag_t pc, pcitag_t tag, 3370 #endif 3371 const pcireg_t *regs 3372 #ifdef _KERNEL 3373 , int sizebars 3374 #endif 3375 ) 3376 { 3377 pcireg_t rval; 3378 3379 /* 3380 * XXX these need to be printed in more detail, need to be 3381 * XXX checked against specs/docs, etc. 3382 * 3383 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 3384 * controller chip documentation, and may not be correct with 3385 * respect to various standards. (XXX) 3386 */ 3387 3388 #ifdef _KERNEL 3389 pci_conf_print_bar(pc, tag, regs, 0x10, 3390 "CardBus socket/ExCA registers", sizebars); 3391 #else 3392 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 3393 #endif 3394 3395 /* Capability list pointer and secondary status register */ 3396 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 3397 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3398 printf(" Capability list pointer: 0x%02x\n", 3399 PCI_CAPLIST_PTR(rval)); 3400 else 3401 printf(" Reserved @ 0x14: 0x%04x\n", 3402 (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0))); 3403 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 3404 3405 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 3406 printf(" PCI bus number: 0x%02x\n", 3407 (rval >> 0) & 0xff); 3408 printf(" CardBus bus number: 0x%02x\n", 3409 (rval >> 8) & 0xff); 3410 printf(" Subordinate bus number: 0x%02x\n", 3411 (rval >> 16) & 0xff); 3412 printf(" CardBus latency timer: 0x%02x\n", 3413 (rval >> 24) & 0xff); 3414 3415 /* XXX Print more prettily */ 3416 printf(" CardBus memory region 0:\n"); 3417 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 3418 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 3419 printf(" CardBus memory region 1:\n"); 3420 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 3421 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 3422 printf(" CardBus I/O region 0:\n"); 3423 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 3424 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 3425 printf(" CardBus I/O region 1:\n"); 3426 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 3427 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 3428 3429 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3430 printf(" Interrupt line: 0x%02x\n", 3431 (rval >> 0) & 0xff); 3432 printf(" Interrupt pin: 0x%02x ", 3433 (rval >> 8) & 0xff); 3434 switch ((rval >> 8) & 0xff) { 3435 case PCI_INTERRUPT_PIN_NONE: 3436 printf("(none)"); 3437 break; 3438 case PCI_INTERRUPT_PIN_A: 3439 printf("(pin A)"); 3440 break; 3441 case PCI_INTERRUPT_PIN_B: 3442 printf("(pin B)"); 3443 break; 3444 case PCI_INTERRUPT_PIN_C: 3445 printf("(pin C)"); 3446 break; 3447 case PCI_INTERRUPT_PIN_D: 3448 printf("(pin D)"); 3449 break; 3450 default: 3451 printf("(? ? ?)"); 3452 break; 3453 } 3454 printf("\n"); 3455 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 3456 printf(" Bridge control register: 0x%04x\n", rval); 3457 onoff("Parity error response", rval, __BIT(0)); 3458 onoff("SERR# enable", rval, __BIT(1)); 3459 onoff("ISA enable", rval, __BIT(2)); 3460 onoff("VGA enable", rval, __BIT(3)); 3461 onoff("Master abort mode", rval, __BIT(5)); 3462 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 3463 onoff("Functional interrupts routed by ExCA registers", rval, 3464 __BIT(7)); 3465 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 3466 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 3467 onoff("Write posting enable", rval, __BIT(10)); 3468 3469 rval = regs[o2i(0x40)]; 3470 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 3471 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 3472 3473 #ifdef _KERNEL 3474 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 3475 sizebars); 3476 #else 3477 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 3478 #endif 3479 } 3480 3481 void 3482 pci_conf_print( 3483 #ifdef _KERNEL 3484 pci_chipset_tag_t pc, pcitag_t tag, 3485 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 3486 #else 3487 int pcifd, u_int bus, u_int dev, u_int func 3488 #endif 3489 ) 3490 { 3491 pcireg_t regs[o2i(PCI_EXTCONF_SIZE)]; 3492 int off, capoff, endoff, hdrtype; 3493 const char *type_name; 3494 #ifdef _KERNEL 3495 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, 3496 int); 3497 int sizebars; 3498 #else 3499 void (*type_printfn)(const pcireg_t *); 3500 #endif 3501 3502 printf("PCI configuration registers:\n"); 3503 3504 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 3505 #ifdef _KERNEL 3506 regs[o2i(off)] = pci_conf_read(pc, tag, off); 3507 #else 3508 if (pcibus_conf_read(pcifd, bus, dev, func, off, 3509 ®s[o2i(off)]) == -1) 3510 regs[o2i(off)] = 0; 3511 #endif 3512 } 3513 3514 #ifdef _KERNEL 3515 sizebars = 1; 3516 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 3517 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 3518 sizebars = 0; 3519 #endif 3520 3521 /* common header */ 3522 printf(" Common header:\n"); 3523 pci_conf_print_regs(regs, 0, 16); 3524 3525 printf("\n"); 3526 #ifdef _KERNEL 3527 pci_conf_print_common(pc, tag, regs); 3528 #else 3529 pci_conf_print_common(regs); 3530 #endif 3531 printf("\n"); 3532 3533 /* type-dependent header */ 3534 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 3535 switch (hdrtype) { /* XXX make a table, eventually */ 3536 case 0: 3537 /* Standard device header */ 3538 type_name = "\"normal\" device"; 3539 type_printfn = &pci_conf_print_type0; 3540 capoff = PCI_CAPLISTPTR_REG; 3541 endoff = 64; 3542 break; 3543 case 1: 3544 /* PCI-PCI bridge header */ 3545 type_name = "PCI-PCI bridge"; 3546 type_printfn = &pci_conf_print_type1; 3547 capoff = PCI_CAPLISTPTR_REG; 3548 endoff = 64; 3549 break; 3550 case 2: 3551 /* PCI-CardBus bridge header */ 3552 type_name = "PCI-CardBus bridge"; 3553 type_printfn = &pci_conf_print_type2; 3554 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 3555 endoff = 72; 3556 break; 3557 default: 3558 type_name = NULL; 3559 type_printfn = 0; 3560 capoff = -1; 3561 endoff = 64; 3562 break; 3563 } 3564 printf(" Type %d ", hdrtype); 3565 if (type_name != NULL) 3566 printf("(%s) ", type_name); 3567 printf("header:\n"); 3568 pci_conf_print_regs(regs, 16, endoff); 3569 printf("\n"); 3570 if (type_printfn) { 3571 #ifdef _KERNEL 3572 (*type_printfn)(pc, tag, regs, sizebars); 3573 #else 3574 (*type_printfn)(regs); 3575 #endif 3576 } else 3577 printf(" Don't know how to pretty-print type %d header.\n", 3578 hdrtype); 3579 printf("\n"); 3580 3581 /* capability list, if present */ 3582 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3583 && (capoff > 0)) { 3584 #ifdef _KERNEL 3585 pci_conf_print_caplist(pc, tag, regs, capoff); 3586 #else 3587 pci_conf_print_caplist(regs, capoff); 3588 #endif 3589 printf("\n"); 3590 } 3591 3592 /* device-dependent header */ 3593 printf(" Device-dependent header:\n"); 3594 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 3595 printf("\n"); 3596 #ifdef _KERNEL 3597 if (printfn) 3598 (*printfn)(pc, tag, regs); 3599 else 3600 printf(" Don't know how to pretty-print device-dependent header.\n"); 3601 printf("\n"); 3602 #endif /* _KERNEL */ 3603 3604 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 3605 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 3606 return; 3607 3608 #ifdef _KERNEL 3609 pci_conf_print_extcaplist(pc, tag, regs, capoff); 3610 #else 3611 pci_conf_print_extcaplist(regs, capoff); 3612 #endif 3613 printf("\n"); 3614 3615 /* Extended Configuration Space, if present */ 3616 printf(" Extended Configuration Space:\n"); 3617 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 3618 } 3619
Indexes created Fri Sep 26 20:09:58 GMT 2025