pci_subr.c revision 1.140
1 /* $NetBSD: pci_subr.c,v 1.140 2015/10/30 20:03:45 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.140 2015/10/30 20:03:45 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdbool.h> 58 #include <stdio.h> 59 #include <stdlib.h> 60 #include <string.h> 61 #endif 62 63 #include <dev/pci/pcireg.h> 64 #ifdef _KERNEL 65 #include <dev/pci/pcivar.h> 66 #else 67 #include <dev/pci/pci_verbose.h> 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcidevs_data.h> 70 #endif 71 72 /* 73 * Descriptions of known PCI classes and subclasses. 74 * 75 * Subclasses are described in the same way as classes, but have a 76 * NULL subclass pointer. 77 */ 78 struct pci_class { 79 const char *name; 80 u_int val; /* as wide as pci_{,sub}class_t */ 81 const struct pci_class *subclasses; 82 }; 83 84 /* 85 * Class 0x00. 86 * Before rev. 2.0. 87 */ 88 static const struct pci_class pci_subclass_prehistoric[] = { 89 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 90 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 91 { NULL, 0, NULL, }, 92 }; 93 94 /* 95 * Class 0x01. 96 * Mass storage controller 97 */ 98 99 /* ATA programming interface */ 100 static const struct pci_class pci_interface_ata[] = { 101 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 102 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 103 { NULL, 0, NULL, }, 104 }; 105 106 /* SATA programming interface */ 107 static const struct pci_class pci_interface_sata[] = { 108 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 109 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 110 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 111 { NULL, 0, NULL, }, 112 }; 113 114 /* Flash programming interface */ 115 static const struct pci_class pci_interface_nvm[] = { 116 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 117 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 118 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 119 { NULL, 0, NULL, }, 120 }; 121 122 /* Subclasses */ 123 static const struct pci_class pci_subclass_mass_storage[] = { 124 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 125 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 126 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 127 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 128 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 129 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 130 pci_interface_ata, }, 131 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 132 pci_interface_sata, }, 133 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 134 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 135 pci_interface_nvm, }, 136 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 137 { NULL, 0, NULL, }, 138 }; 139 140 /* 141 * Class 0x02. 142 * Network controller. 143 */ 144 static const struct pci_class pci_subclass_network[] = { 145 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 146 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 147 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 148 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 149 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 150 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 151 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 152 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 153 { NULL, 0, NULL, }, 154 }; 155 156 /* 157 * Class 0x03. 158 * Display controller. 159 */ 160 161 /* VGA programming interface */ 162 static const struct pci_class pci_interface_vga[] = { 163 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 164 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 165 { NULL, 0, NULL, }, 166 }; 167 /* Subclasses */ 168 static const struct pci_class pci_subclass_display[] = { 169 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 170 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 171 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 172 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 173 { NULL, 0, NULL, }, 174 }; 175 176 /* 177 * Class 0x04. 178 * Multimedia device. 179 */ 180 static const struct pci_class pci_subclass_multimedia[] = { 181 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 182 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 183 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 184 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 185 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 186 { NULL, 0, NULL, }, 187 }; 188 189 /* 190 * Class 0x05. 191 * Memory controller. 192 */ 193 static const struct pci_class pci_subclass_memory[] = { 194 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 195 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 196 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 197 { NULL, 0, NULL, }, 198 }; 199 200 /* 201 * Class 0x06. 202 * Bridge device. 203 */ 204 205 /* PCI bridge programming interface */ 206 static const struct pci_class pci_interface_pcibridge[] = { 207 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 208 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 209 { NULL, 0, NULL, }, 210 }; 211 212 /* Semi-transparent PCI-to-PCI bridge programming interface */ 213 static const struct pci_class pci_interface_stpci[] = { 214 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 215 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 216 { NULL, 0, NULL, }, 217 }; 218 219 /* Advanced Switching programming interface */ 220 static const struct pci_class pci_interface_advsw[] = { 221 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 222 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 223 { NULL, 0, NULL, }, 224 }; 225 226 /* Subclasses */ 227 static const struct pci_class pci_subclass_bridge[] = { 228 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 229 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 230 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 231 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 232 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 233 pci_interface_pcibridge, }, 234 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 235 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 236 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 237 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 238 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 239 pci_interface_stpci, }, 240 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 241 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 242 pci_interface_advsw, }, 243 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 244 { NULL, 0, NULL, }, 245 }; 246 247 /* 248 * Class 0x07. 249 * Simple communications controller. 250 */ 251 252 /* Serial controller programming interface */ 253 static const struct pci_class pci_interface_serial[] = { 254 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 255 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 256 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 257 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 258 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 259 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 260 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 261 { NULL, 0, NULL, }, 262 }; 263 264 /* Parallel controller programming interface */ 265 static const struct pci_class pci_interface_parallel[] = { 266 { "", PCI_INTERFACE_PARALLEL, NULL,}, 267 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 268 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 269 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 270 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 271 { NULL, 0, NULL,}, 272 }; 273 274 /* Modem programming interface */ 275 static const struct pci_class pci_interface_modem[] = { 276 { "", PCI_INTERFACE_MODEM, NULL,}, 277 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 278 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 279 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 280 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 281 { NULL, 0, NULL,}, 282 }; 283 284 /* Subclasses */ 285 static const struct pci_class pci_subclass_communications[] = { 286 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 287 pci_interface_serial, }, 288 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 289 pci_interface_parallel, }, 290 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 291 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 292 pci_interface_modem, }, 293 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 294 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 295 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 296 { NULL, 0, NULL,}, 297 }; 298 299 /* 300 * Class 0x08. 301 * Base system peripheral. 302 */ 303 304 /* PIC programming interface */ 305 static const struct pci_class pci_interface_pic[] = { 306 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 307 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 308 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 309 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 310 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 311 { NULL, 0, NULL, }, 312 }; 313 314 /* DMA programming interface */ 315 static const struct pci_class pci_interface_dma[] = { 316 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 317 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 318 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 319 { NULL, 0, NULL, }, 320 }; 321 322 /* Timer programming interface */ 323 static const struct pci_class pci_interface_tmr[] = { 324 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 325 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 326 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 327 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 328 { NULL, 0, NULL, }, 329 }; 330 331 /* RTC programming interface */ 332 static const struct pci_class pci_interface_rtc[] = { 333 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 334 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 335 { NULL, 0, NULL, }, 336 }; 337 338 /* Subclasses */ 339 static const struct pci_class pci_subclass_system[] = { 340 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 341 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 342 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 343 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 344 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 345 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 346 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 347 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 348 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 349 { NULL, 0, NULL, }, 350 }; 351 352 /* 353 * Class 0x09. 354 * Input device. 355 */ 356 357 /* Gameport programming interface */ 358 static const struct pci_class pci_interface_game[] = { 359 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 360 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 361 { NULL, 0, NULL, }, 362 }; 363 364 /* Subclasses */ 365 static const struct pci_class pci_subclass_input[] = { 366 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 367 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 368 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 369 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 370 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 371 pci_interface_game, }, 372 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 373 { NULL, 0, NULL, }, 374 }; 375 376 /* 377 * Class 0x0a. 378 * Docking station. 379 */ 380 static const struct pci_class pci_subclass_dock[] = { 381 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 382 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 383 { NULL, 0, NULL, }, 384 }; 385 386 /* 387 * Class 0x0b. 388 * Processor. 389 */ 390 static const struct pci_class pci_subclass_processor[] = { 391 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 392 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 393 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 394 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 395 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 396 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 397 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 398 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 399 { NULL, 0, NULL, }, 400 }; 401 402 /* 403 * Class 0x0c. 404 * Serial bus controller. 405 */ 406 407 /* IEEE1394 programming interface */ 408 static const struct pci_class pci_interface_ieee1394[] = { 409 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 410 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 411 { NULL, 0, NULL,}, 412 }; 413 414 /* USB programming interface */ 415 static const struct pci_class pci_interface_usb[] = { 416 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 417 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 418 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 419 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 420 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 421 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 422 { NULL, 0, NULL, }, 423 }; 424 425 /* IPMI programming interface */ 426 static const struct pci_class pci_interface_ipmi[] = { 427 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 428 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 429 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 430 { NULL, 0, NULL,}, 431 }; 432 433 /* Subclasses */ 434 static const struct pci_class pci_subclass_serialbus[] = { 435 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 436 pci_interface_ieee1394, }, 437 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 438 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 439 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 440 pci_interface_usb, }, 441 /* XXX Fiber Channel/_FIBRECHANNEL */ 442 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 443 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 444 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 445 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 446 pci_interface_ipmi, }, 447 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 448 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 449 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 450 { NULL, 0, NULL, }, 451 }; 452 453 /* 454 * Class 0x0d. 455 * Wireless Controller. 456 */ 457 static const struct pci_class pci_subclass_wireless[] = { 458 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 459 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 460 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 461 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 462 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 463 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 464 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 465 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 466 { NULL, 0, NULL, }, 467 }; 468 469 /* 470 * Class 0x0e. 471 * Intelligent IO controller. 472 */ 473 474 /* Intelligent IO programming interface */ 475 static const struct pci_class pci_interface_i2o[] = { 476 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 477 { NULL, 0, NULL,}, 478 }; 479 480 /* Subclasses */ 481 static const struct pci_class pci_subclass_i2o[] = { 482 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 483 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 484 { NULL, 0, NULL, }, 485 }; 486 487 /* 488 * Class 0x0f. 489 * Satellite communication controller. 490 */ 491 static const struct pci_class pci_subclass_satcom[] = { 492 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 493 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 494 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 495 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 496 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 497 { NULL, 0, NULL, }, 498 }; 499 500 /* 501 * Class 0x10. 502 * Encryption/Decryption controller. 503 */ 504 static const struct pci_class pci_subclass_crypto[] = { 505 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 506 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 507 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 508 { NULL, 0, NULL, }, 509 }; 510 511 /* 512 * Class 0x11. 513 * Data aquuisition and signal processing controller. 514 */ 515 static const struct pci_class pci_subclass_dasp[] = { 516 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 517 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 518 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 519 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 520 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 521 { NULL, 0, NULL, }, 522 }; 523 524 /* List of classes */ 525 static const struct pci_class pci_class[] = { 526 { "prehistoric", PCI_CLASS_PREHISTORIC, 527 pci_subclass_prehistoric, }, 528 { "mass storage", PCI_CLASS_MASS_STORAGE, 529 pci_subclass_mass_storage, }, 530 { "network", PCI_CLASS_NETWORK, 531 pci_subclass_network, }, 532 { "display", PCI_CLASS_DISPLAY, 533 pci_subclass_display, }, 534 { "multimedia", PCI_CLASS_MULTIMEDIA, 535 pci_subclass_multimedia, }, 536 { "memory", PCI_CLASS_MEMORY, 537 pci_subclass_memory, }, 538 { "bridge", PCI_CLASS_BRIDGE, 539 pci_subclass_bridge, }, 540 { "communications", PCI_CLASS_COMMUNICATIONS, 541 pci_subclass_communications, }, 542 { "system", PCI_CLASS_SYSTEM, 543 pci_subclass_system, }, 544 { "input", PCI_CLASS_INPUT, 545 pci_subclass_input, }, 546 { "dock", PCI_CLASS_DOCK, 547 pci_subclass_dock, }, 548 { "processor", PCI_CLASS_PROCESSOR, 549 pci_subclass_processor, }, 550 { "serial bus", PCI_CLASS_SERIALBUS, 551 pci_subclass_serialbus, }, 552 { "wireless", PCI_CLASS_WIRELESS, 553 pci_subclass_wireless, }, 554 { "I2O", PCI_CLASS_I2O, 555 pci_subclass_i2o, }, 556 { "satellite comm", PCI_CLASS_SATCOM, 557 pci_subclass_satcom, }, 558 { "crypto", PCI_CLASS_CRYPTO, 559 pci_subclass_crypto, }, 560 { "DASP", PCI_CLASS_DASP, 561 pci_subclass_dasp, }, 562 { "undefined", PCI_CLASS_UNDEFINED, 563 NULL, }, 564 { NULL, 0, 565 NULL, }, 566 }; 567 568 DEV_VERBOSE_DEFINE(pci); 569 570 void 571 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 572 size_t l) 573 { 574 pci_class_t pciclass; 575 pci_subclass_t subclass; 576 pci_interface_t interface; 577 pci_revision_t revision; 578 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 579 const struct pci_class *classp, *subclassp, *interfacep; 580 char *ep; 581 582 ep = cp + l; 583 584 pciclass = PCI_CLASS(class_reg); 585 subclass = PCI_SUBCLASS(class_reg); 586 interface = PCI_INTERFACE(class_reg); 587 revision = PCI_REVISION(class_reg); 588 589 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 590 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 591 PCI_PRODUCT(id_reg)); 592 593 classp = pci_class; 594 while (classp->name != NULL) { 595 if (pciclass == classp->val) 596 break; 597 classp++; 598 } 599 600 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 601 while (subclassp && subclassp->name != NULL) { 602 if (subclass == subclassp->val) 603 break; 604 subclassp++; 605 } 606 607 interfacep = (subclassp && subclassp->name != NULL) ? 608 subclassp->subclasses : NULL; 609 while (interfacep && interfacep->name != NULL) { 610 if (interface == interfacep->val) 611 break; 612 interfacep++; 613 } 614 615 cp += snprintf(cp, ep - cp, "%s %s", vendor, product); 616 if (showclass) { 617 cp += snprintf(cp, ep - cp, " ("); 618 if (classp->name == NULL) 619 cp += snprintf(cp, ep - cp, 620 "class 0x%02x, subclass 0x%02x", pciclass, subclass); 621 else { 622 if (subclassp == NULL || subclassp->name == NULL) 623 cp += snprintf(cp, ep - cp, 624 "%s, subclass 0x%02x", 625 classp->name, subclass); 626 else 627 cp += snprintf(cp, ep - cp, "%s %s", 628 subclassp->name, classp->name); 629 } 630 if ((interfacep == NULL) || (interfacep->name == NULL)) { 631 if (interface != 0) 632 cp += snprintf(cp, ep - cp, 633 ", interface 0x%02x", interface); 634 } else if (strncmp(interfacep->name, "", 1) != 0) 635 cp += snprintf(cp, ep - cp, ", %s", 636 interfacep->name); 637 if (revision != 0) 638 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 639 revision); 640 cp += snprintf(cp, ep - cp, ")"); 641 } 642 } 643 644 #ifdef _KERNEL 645 void 646 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 647 const char *known, int addrev) 648 { 649 char devinfo[256]; 650 651 if (known) { 652 aprint_normal(": %s", known); 653 if (addrev) 654 aprint_normal(" (rev. 0x%02x)", 655 PCI_REVISION(pa->pa_class)); 656 aprint_normal("\n"); 657 } else { 658 pci_devinfo(pa->pa_id, pa->pa_class, 0, 659 devinfo, sizeof(devinfo)); 660 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 661 PCI_REVISION(pa->pa_class)); 662 } 663 if (naive) 664 aprint_naive(": %s\n", naive); 665 else 666 aprint_naive("\n"); 667 } 668 #endif 669 670 /* 671 * Print out most of the PCI configuration registers. Typically used 672 * in a device attach routine like this: 673 * 674 * #ifdef MYDEV_DEBUG 675 * printf("%s: ", device_xname(sc->sc_dev)); 676 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 677 * #endif 678 */ 679 680 #define i2o(i) ((i) * 4) 681 #define o2i(o) ((o) / 4) 682 #define onoff2(str, rval, bit, onstr, offstr) \ 683 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 684 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 685 686 static void 687 pci_conf_print_common( 688 #ifdef _KERNEL 689 pci_chipset_tag_t pc, pcitag_t tag, 690 #endif 691 const pcireg_t *regs) 692 { 693 const char *name; 694 const struct pci_class *classp, *subclassp; 695 char vendor[PCI_VENDORSTR_LEN]; 696 char product[PCI_PRODUCTSTR_LEN]; 697 pcireg_t rval; 698 unsigned int num; 699 700 rval = regs[o2i(PCI_ID_REG)]; 701 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 702 if (name) 703 printf(" Vendor Name: %s (0x%04x)\n", name, 704 PCI_VENDOR(rval)); 705 else 706 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 707 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 708 PCI_PRODUCT(rval)); 709 if (name) 710 printf(" Device Name: %s (0x%04x)\n", name, 711 PCI_PRODUCT(rval)); 712 else 713 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 714 715 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 716 717 printf(" Command register: 0x%04x\n", rval & 0xffff); 718 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 719 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 720 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 721 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 722 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 723 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 724 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 725 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 726 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 727 onoff("Fast back-to-back transactions", rval, 728 PCI_COMMAND_BACKTOBACK_ENABLE); 729 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 730 731 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 732 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 733 "inactive"); 734 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 735 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 736 onoff("User Definable Features (UDF) support", rval, 737 PCI_STATUS_UDF_SUPPORT); 738 onoff("Fast back-to-back capable", rval, 739 PCI_STATUS_BACKTOBACK_SUPPORT); 740 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 741 742 printf(" DEVSEL timing: "); 743 switch (rval & PCI_STATUS_DEVSEL_MASK) { 744 case PCI_STATUS_DEVSEL_FAST: 745 printf("fast"); 746 break; 747 case PCI_STATUS_DEVSEL_MEDIUM: 748 printf("medium"); 749 break; 750 case PCI_STATUS_DEVSEL_SLOW: 751 printf("slow"); 752 break; 753 default: 754 printf("unknown/reserved"); /* XXX */ 755 break; 756 } 757 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 758 759 onoff("Slave signaled Target Abort", rval, 760 PCI_STATUS_TARGET_TARGET_ABORT); 761 onoff("Master received Target Abort", rval, 762 PCI_STATUS_MASTER_TARGET_ABORT); 763 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 764 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 765 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 766 767 rval = regs[o2i(PCI_CLASS_REG)]; 768 for (classp = pci_class; classp->name != NULL; classp++) { 769 if (PCI_CLASS(rval) == classp->val) 770 break; 771 } 772 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 773 while (subclassp && subclassp->name != NULL) { 774 if (PCI_SUBCLASS(rval) == subclassp->val) 775 break; 776 subclassp++; 777 } 778 if (classp->name != NULL) { 779 printf(" Class Name: %s (0x%02x)\n", classp->name, 780 PCI_CLASS(rval)); 781 if (subclassp != NULL && subclassp->name != NULL) 782 printf(" Subclass Name: %s (0x%02x)\n", 783 subclassp->name, PCI_SUBCLASS(rval)); 784 else 785 printf(" Subclass ID: 0x%02x\n", 786 PCI_SUBCLASS(rval)); 787 } else { 788 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 789 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 790 } 791 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 792 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 793 794 rval = regs[o2i(PCI_BHLC_REG)]; 795 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 796 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 797 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 798 PCI_HDRTYPE(rval)); 799 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 800 num = PCI_CACHELINE(rval); 801 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 802 } 803 804 static int 805 pci_conf_print_bar( 806 #ifdef _KERNEL 807 pci_chipset_tag_t pc, pcitag_t tag, 808 #endif 809 const pcireg_t *regs, int reg, const char *name 810 #ifdef _KERNEL 811 , int sizebar 812 #endif 813 ) 814 { 815 int width; 816 pcireg_t rval, rval64h; 817 #ifdef _KERNEL 818 int s; 819 pcireg_t mask, mask64h; 820 #endif 821 822 width = 4; 823 824 /* 825 * Section 6.2.5.1, `Address Maps', tells us that: 826 * 827 * 1) The builtin software should have already mapped the 828 * device in a reasonable way. 829 * 830 * 2) A device which wants 2^n bytes of memory will hardwire 831 * the bottom n bits of the address to 0. As recommended, 832 * we write all 1s and see what we get back. 833 */ 834 835 rval = regs[o2i(reg)]; 836 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 837 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 838 rval64h = regs[o2i(reg + 4)]; 839 width = 8; 840 } else 841 rval64h = 0; 842 843 #ifdef _KERNEL 844 /* XXX don't size unknown memory type? */ 845 if (rval != 0 && sizebar) { 846 /* 847 * The following sequence seems to make some devices 848 * (e.g. host bus bridges, which don't normally 849 * have their space mapped) very unhappy, to 850 * the point of crashing the system. 851 * 852 * Therefore, if the mapping register is zero to 853 * start out with, don't bother trying. 854 */ 855 s = splhigh(); 856 pci_conf_write(pc, tag, reg, 0xffffffff); 857 mask = pci_conf_read(pc, tag, reg); 858 pci_conf_write(pc, tag, reg, rval); 859 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 860 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 861 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 862 mask64h = pci_conf_read(pc, tag, reg + 4); 863 pci_conf_write(pc, tag, reg + 4, rval64h); 864 } else 865 mask64h = 0; 866 splx(s); 867 } else 868 mask = mask64h = 0; 869 #endif /* _KERNEL */ 870 871 printf(" Base address register at 0x%02x", reg); 872 if (name) 873 printf(" (%s)", name); 874 printf("\n "); 875 if (rval == 0) { 876 printf("not implemented(?)\n"); 877 return width; 878 } 879 printf("type: "); 880 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 881 const char *type, *prefetch; 882 883 switch (PCI_MAPREG_MEM_TYPE(rval)) { 884 case PCI_MAPREG_MEM_TYPE_32BIT: 885 type = "32-bit"; 886 break; 887 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 888 type = "32-bit-1M"; 889 break; 890 case PCI_MAPREG_MEM_TYPE_64BIT: 891 type = "64-bit"; 892 break; 893 default: 894 type = "unknown (XXX)"; 895 break; 896 } 897 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 898 prefetch = ""; 899 else 900 prefetch = "non"; 901 printf("%s %sprefetchable memory\n", type, prefetch); 902 switch (PCI_MAPREG_MEM_TYPE(rval)) { 903 case PCI_MAPREG_MEM_TYPE_64BIT: 904 printf(" base: 0x%016llx, ", 905 PCI_MAPREG_MEM64_ADDR( 906 ((((long long) rval64h) << 32) | rval))); 907 #ifdef _KERNEL 908 if (sizebar) 909 printf("size: 0x%016llx", 910 PCI_MAPREG_MEM64_SIZE( 911 ((((long long) mask64h) << 32) | mask))); 912 else 913 #endif /* _KERNEL */ 914 printf("not sized"); 915 printf("\n"); 916 break; 917 case PCI_MAPREG_MEM_TYPE_32BIT: 918 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 919 default: 920 printf(" base: 0x%08x, ", 921 PCI_MAPREG_MEM_ADDR(rval)); 922 #ifdef _KERNEL 923 if (sizebar) 924 printf("size: 0x%08x", 925 PCI_MAPREG_MEM_SIZE(mask)); 926 else 927 #endif /* _KERNEL */ 928 printf("not sized"); 929 printf("\n"); 930 break; 931 } 932 } else { 933 #ifdef _KERNEL 934 if (sizebar) 935 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 936 #endif /* _KERNEL */ 937 printf("i/o\n"); 938 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 939 #ifdef _KERNEL 940 if (sizebar) 941 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 942 else 943 #endif /* _KERNEL */ 944 printf("not sized"); 945 printf("\n"); 946 } 947 948 return width; 949 } 950 951 static void 952 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 953 { 954 int off, needaddr, neednl; 955 956 needaddr = 1; 957 neednl = 0; 958 for (off = first; off < pastlast; off += 4) { 959 if ((off % 16) == 0 || needaddr) { 960 printf(" 0x%02x:", off); 961 needaddr = 0; 962 } 963 printf(" 0x%08x", regs[o2i(off)]); 964 neednl = 1; 965 if ((off % 16) == 12) { 966 printf("\n"); 967 neednl = 0; 968 } 969 } 970 if (neednl) 971 printf("\n"); 972 } 973 974 static void 975 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 976 { 977 pcireg_t rval; 978 979 printf("\n AGP Capabilities Register\n"); 980 981 rval = regs[o2i(capoff)]; 982 printf(" Revision: %d.%d\n", 983 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 984 985 /* XXX need more */ 986 } 987 988 static const char * 989 pci_conf_print_pcipm_cap_aux(uint16_t caps) 990 { 991 992 switch ((caps >> 6) & 7) { 993 case 0: return "self-powered"; 994 case 1: return "55 mA"; 995 case 2: return "100 mA"; 996 case 3: return "160 mA"; 997 case 4: return "220 mA"; 998 case 5: return "270 mA"; 999 case 6: return "320 mA"; 1000 case 7: 1001 default: return "375 mA"; 1002 } 1003 } 1004 1005 static const char * 1006 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1007 { 1008 static const char unk[] = "unknown"; 1009 static const char *pmrev[8] = { 1010 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1011 }; 1012 if (val > 7) 1013 return unk; 1014 return pmrev[val]; 1015 } 1016 1017 static void 1018 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1019 { 1020 uint16_t caps, pmcsr; 1021 pcireg_t reg; 1022 1023 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1024 reg = regs[o2i(capoff + PCI_PMCSR)]; 1025 pmcsr = reg & 0xffff; 1026 1027 printf("\n PCI Power Management Capabilities Register\n"); 1028 1029 printf(" Capabilities register: 0x%04x\n", caps); 1030 printf(" Version: %s\n", 1031 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1032 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1033 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1034 printf(" 3.3V auxiliary current: %s\n", 1035 pci_conf_print_pcipm_cap_aux(caps)); 1036 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1037 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1038 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1039 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1040 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1041 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1042 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1043 1044 printf(" Control/status register: 0x%04x\n", pmcsr); 1045 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1046 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1047 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1048 printf(" PME# assertion: %sabled\n", 1049 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1050 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1051 printf(" Bridge Support Extensions register: 0x%02x\n", 1052 (reg >> 16) & 0xff); 1053 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1054 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1055 printf(" Data register: 0x%02x\n", (reg >> 24) & 0xff); 1056 1057 } 1058 1059 /* XXX pci_conf_print_vpd_cap */ 1060 /* XXX pci_conf_print_slotid_cap */ 1061 1062 static void 1063 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1064 { 1065 uint32_t ctl, mmc, mme; 1066 1067 regs += o2i(capoff); 1068 ctl = *regs++; 1069 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1070 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1071 1072 printf("\n PCI Message Signaled Interrupt\n"); 1073 1074 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1075 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1076 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1077 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1078 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1079 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1080 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1081 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1082 printf(" Message Address %sregister: 0x%08x\n", 1083 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1084 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1085 printf(" Message Address %sregister: 0x%08x\n", 1086 "(upper) ", *regs++); 1087 } 1088 printf(" Message Data register: 0x%08x\n", *regs++); 1089 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1090 printf(" Vector Mask register: 0x%08x\n", *regs++); 1091 printf(" Vector Pending register: 0x%08x\n", *regs++); 1092 } 1093 } 1094 1095 /* XXX pci_conf_print_cpci_hostwap_cap */ 1096 1097 /* 1098 * For both command register and status register. 1099 * The argument "idx" is index number (0 to 7). 1100 */ 1101 static int 1102 pcix_split_trans(unsigned int idx) 1103 { 1104 static int table[8] = { 1105 1, 2, 3, 4, 8, 12, 16, 32 1106 }; 1107 1108 if (idx >= __arraycount(table)) 1109 return -1; 1110 return table[idx]; 1111 } 1112 1113 static void 1114 pci_conf_print_pcix_cap_2ndbusmode(int num) 1115 { 1116 const char *maxfreq, *maxperiod; 1117 1118 printf(" Mode: "); 1119 if (num <= 0x07) 1120 printf("PCI-X Mode 1\n"); 1121 else if (num <= 0x0b) 1122 printf("PCI-X 266 (Mode 2)\n"); 1123 else 1124 printf("PCI-X 533 (Mode 2)\n"); 1125 1126 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1127 switch (num & 0x03) { 1128 default: 1129 case 0: 1130 maxfreq = "N/A"; 1131 maxperiod = "N/A"; 1132 break; 1133 case 1: 1134 maxfreq = "66MHz"; 1135 maxperiod = "15ns"; 1136 break; 1137 case 2: 1138 maxfreq = "100MHz"; 1139 maxperiod = "10ns"; 1140 break; 1141 case 3: 1142 maxfreq = "133MHz"; 1143 maxperiod = "7.5ns"; 1144 break; 1145 } 1146 printf(" Max Clock Freq: %s\n", maxfreq); 1147 printf(" Min Clock Period: %s\n", maxperiod); 1148 } 1149 1150 static void 1151 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1152 { 1153 pcireg_t reg; 1154 int isbridge; 1155 int i; 1156 1157 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1158 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1159 printf("\n PCI-X %s Capabilities Register\n", 1160 isbridge ? "Bridge" : "Non-bridge"); 1161 1162 reg = regs[o2i(capoff)]; 1163 if (isbridge != 0) { 1164 printf(" Secondary status register: 0x%04x\n", 1165 (reg & 0xffff0000) >> 16); 1166 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1167 onoff("133MHz capable", reg, PCIX_STATUS_133); 1168 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1169 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1170 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1171 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1172 pci_conf_print_pcix_cap_2ndbusmode( 1173 __SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1174 printf(" Version: 0x%x\n", 1175 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1176 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1177 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1178 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1179 } else { 1180 printf(" Command register: 0x%04x\n", 1181 (reg & 0xffff0000) >> 16); 1182 onoff("Data Parity Error Recovery", reg, 1183 PCIX_CMD_PERR_RECOVER); 1184 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1185 printf(" Maximum Burst Read Count: %u\n", 1186 PCIX_CMD_BYTECNT(reg)); 1187 printf(" Maximum Split Transactions: %d\n", 1188 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1189 >> PCIX_CMD_SPLTRANS_SHIFT)); 1190 } 1191 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1192 printf(" %sStatus register: 0x%08x\n", 1193 isbridge ? "Bridge " : "", reg); 1194 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1195 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1196 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1197 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1198 onoff("133MHz capable", reg, PCIX_STATUS_133); 1199 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1200 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1201 if (isbridge != 0) { 1202 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1203 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1204 } else { 1205 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1206 "bridge device", "simple device"); 1207 printf(" Designed max memory read byte count: %d\n", 1208 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1209 >> PCIX_STATUS_MAXB_SHIFT)); 1210 printf(" Designed max outstanding split transaction: %d\n", 1211 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1212 >> PCIX_STATUS_MAXST_SHIFT)); 1213 printf(" MAX cumulative Read Size: %u\n", 1214 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1215 onoff("Received split completion error", reg, 1216 PCIX_STATUS_SCERR); 1217 } 1218 onoff("266MHz capable", reg, PCIX_STATUS_266); 1219 onoff("533MHz capable", reg, PCIX_STATUS_533); 1220 1221 if (isbridge == 0) 1222 return; 1223 1224 /* Only for bridge */ 1225 for (i = 0; i < 2; i++) { 1226 reg = regs[o2i(capoff+PCIX_BRIDGE_UP_STCR + (4 * i))]; 1227 printf(" %s split transaction control register: 0x%08x\n", 1228 (i == 0) ? "Upstream" : "Downstream", reg); 1229 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1230 printf(" Commitment Limit: %d\n", 1231 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1232 } 1233 } 1234 1235 /* XXX pci_conf_print_ldt_cap */ 1236 1237 static void 1238 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1239 { 1240 uint16_t caps; 1241 1242 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1243 1244 printf("\n PCI Vendor Specific Capabilities Register\n"); 1245 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1246 } 1247 1248 static void 1249 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1250 { 1251 pcireg_t val; 1252 1253 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1254 1255 printf("\n Debugport Capability Register\n"); 1256 printf(" Debug base Register: 0x%04x\n", 1257 val >> PCI_DEBUG_BASER_SHIFT); 1258 printf(" port offset: 0x%04x\n", 1259 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1260 printf(" BAR number: %u\n", 1261 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1262 } 1263 1264 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1265 /* XXX pci_conf_print_hotplug_cap */ 1266 1267 static void 1268 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1269 { 1270 pcireg_t reg; 1271 1272 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1273 1274 printf("\n Subsystem ID Capability Register\n"); 1275 printf(" Subsystem ID : 0x%08x\n", reg); 1276 } 1277 1278 /* XXX pci_conf_print_agp8_cap */ 1279 /* XXX pci_conf_print_secure_cap */ 1280 1281 static void 1282 pci_print_pcie_L0s_latency(uint32_t val) 1283 { 1284 1285 switch (val) { 1286 case 0x0: 1287 printf("Less than 64ns\n"); 1288 break; 1289 case 0x1: 1290 case 0x2: 1291 case 0x3: 1292 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1293 break; 1294 case 0x4: 1295 printf("512ns to less than 1us\n"); 1296 break; 1297 case 0x5: 1298 printf("1us to less than 2us\n"); 1299 break; 1300 case 0x6: 1301 printf("2us - 4us\n"); 1302 break; 1303 case 0x7: 1304 printf("More than 4us\n"); 1305 break; 1306 } 1307 } 1308 1309 static void 1310 pci_print_pcie_L1_latency(uint32_t val) 1311 { 1312 1313 switch (val) { 1314 case 0x0: 1315 printf("Less than 1us\n"); 1316 break; 1317 case 0x6: 1318 printf("32us - 64us\n"); 1319 break; 1320 case 0x7: 1321 printf("More than 64us\n"); 1322 break; 1323 default: 1324 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1325 break; 1326 } 1327 } 1328 1329 static void 1330 pci_print_pcie_compl_timeout(uint32_t val) 1331 { 1332 1333 switch (val) { 1334 case 0x0: 1335 printf("50us to 50ms\n"); 1336 break; 1337 case 0x5: 1338 printf("16ms to 55ms\n"); 1339 break; 1340 case 0x6: 1341 printf("65ms to 210ms\n"); 1342 break; 1343 case 0x9: 1344 printf("260ms to 900ms\n"); 1345 break; 1346 case 0xa: 1347 printf("1s to 3.5s\n"); 1348 break; 1349 default: 1350 printf("unknown %u value\n", val); 1351 break; 1352 } 1353 } 1354 1355 static void 1356 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1357 { 1358 pcireg_t reg; /* for each register */ 1359 pcireg_t val; /* for each bitfield */ 1360 bool check_link = false; 1361 bool check_slot = false; 1362 bool check_rootport = false; 1363 unsigned int pciever; 1364 static const char * const linkspeeds[] = {"2.5", "5.0", "8.0"}; 1365 int i; 1366 1367 printf("\n PCI Express Capabilities Register\n"); 1368 /* Capability Register */ 1369 reg = regs[o2i(capoff)]; 1370 printf(" Capability register: %04x\n", reg >> 16); 1371 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1372 printf(" Capability version: %u\n", pciever); 1373 printf(" Device type: "); 1374 switch ((reg & 0x00f00000) >> 20) { 1375 case 0x0: 1376 printf("PCI Express Endpoint device\n"); 1377 check_link = true; 1378 break; 1379 case 0x1: 1380 printf("Legacy PCI Express Endpoint device\n"); 1381 check_link = true; 1382 break; 1383 case 0x4: 1384 printf("Root Port of PCI Express Root Complex\n"); 1385 check_link = true; 1386 check_slot = true; 1387 check_rootport = true; 1388 break; 1389 case 0x5: 1390 printf("Upstream Port of PCI Express Switch\n"); 1391 break; 1392 case 0x6: 1393 printf("Downstream Port of PCI Express Switch\n"); 1394 check_slot = true; 1395 check_rootport = true; 1396 break; 1397 case 0x7: 1398 printf("PCI Express to PCI/PCI-X Bridge\n"); 1399 break; 1400 case 0x8: 1401 printf("PCI/PCI-X to PCI Express Bridge\n"); 1402 break; 1403 case 0x9: 1404 printf("Root Complex Integrated Endpoint\n"); 1405 break; 1406 case 0xa: 1407 check_rootport = true; 1408 printf("Root Complex Event Collector\n"); 1409 break; 1410 default: 1411 printf("unknown\n"); 1412 break; 1413 } 1414 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1415 printf(" Interrupt Message Number: %x\n", 1416 (unsigned int)((reg & PCIE_XCAP_IRQ) >> 27)); 1417 1418 /* Device Capability Register */ 1419 reg = regs[o2i(capoff + PCIE_DCAP)]; 1420 printf(" Device Capabilities Register: 0x%08x\n", reg); 1421 printf(" Max Payload Size Supported: %u bytes max\n", 1422 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1423 printf(" Phantom Functions Supported: "); 1424 switch ((reg & PCIE_DCAP_PHANTOM_FUNCS) >> 3) { 1425 case 0x0: 1426 printf("not available\n"); 1427 break; 1428 case 0x1: 1429 printf("MSB\n"); 1430 break; 1431 case 0x2: 1432 printf("two MSB\n"); 1433 break; 1434 case 0x3: 1435 printf("All three bits\n"); 1436 break; 1437 } 1438 printf(" Extended Tag Field Supported: %dbit\n", 1439 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1440 printf(" Endpoint L0 Acceptable Latency: "); 1441 pci_print_pcie_L0s_latency((reg & PCIE_DCAP_L0S_LATENCY) >> 6); 1442 printf(" Endpoint L1 Acceptable Latency: "); 1443 pci_print_pcie_L1_latency((reg & PCIE_DCAP_L1_LATENCY) >> 9); 1444 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1445 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1446 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1447 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1448 printf(" Captured Slot Power Limit Value: %d\n", 1449 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18); 1450 printf(" Captured Slot Power Limit Scale: %d\n", 1451 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26); 1452 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1453 1454 /* Device Control Register */ 1455 reg = regs[o2i(capoff + PCIE_DCSR)]; 1456 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1457 onoff("Correctable Error Reporting Enable", reg, 1458 PCIE_DCSR_ENA_COR_ERR); 1459 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1460 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1461 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1462 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1463 printf(" Max Payload Size: %d byte\n", 1464 128 << (((unsigned int)(reg & PCIE_DCSR_MAX_PAYLOAD) >> 5))); 1465 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1466 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1467 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1468 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1469 printf(" Max Read Request Size: %d byte\n", 1470 128 << ((unsigned int)(reg & PCIE_DCSR_MAX_READ_REQ) >> 12)); 1471 1472 /* Device Status Register */ 1473 reg = regs[o2i(capoff + PCIE_DCSR)]; 1474 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1475 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1476 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1477 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1478 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1479 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1480 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1481 1482 if (check_link) { 1483 /* Link Capability Register */ 1484 reg = regs[o2i(capoff + PCIE_LCAP)]; 1485 printf(" Link Capabilities Register: 0x%08x\n", reg); 1486 printf(" Maximum Link Speed: "); 1487 val = reg & PCIE_LCAP_MAX_SPEED; 1488 if (val < 1 || val > 3) { 1489 printf("unknown %u value\n", val); 1490 } else { 1491 printf("%sGT/s\n", linkspeeds[val - 1]); 1492 } 1493 printf(" Maximum Link Width: x%u lanes\n", 1494 (unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4); 1495 printf(" Active State PM Support: "); 1496 val = (reg & PCIE_LCAP_ASPM) >> 10; 1497 switch (val) { 1498 case 0x1: 1499 printf("L0s Entry supported\n"); 1500 break; 1501 case 0x3: 1502 printf("L0s and L1 supported\n"); 1503 break; 1504 default: 1505 printf("Reserved value\n"); 1506 break; 1507 } 1508 printf(" L0 Exit Latency: "); 1509 pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12); 1510 printf(" L1 Exit Latency: "); 1511 pci_print_pcie_L1_latency((reg & PCIE_LCAP_L1_EXIT) >> 15); 1512 printf(" Port Number: %u\n", reg >> 24); 1513 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1514 onoff("Surprise Down Error Report", reg, 1515 PCIE_LCAP_SURPRISE_DOWN); 1516 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1517 onoff("Link BW Notification Capable", reg, 1518 PCIE_LCAP_LINK_BW_NOTIFY); 1519 onoff("ASPM Optionally Compliance", reg, 1520 PCIE_LCAP_ASPM_COMPLIANCE); 1521 1522 /* Link Control Register */ 1523 reg = regs[o2i(capoff + PCIE_LCSR)]; 1524 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1525 printf(" Active State PM Control: "); 1526 val = reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S); 1527 switch (val) { 1528 case 0: 1529 printf("disabled\n"); 1530 break; 1531 case 1: 1532 printf("L0s Entry Enabled\n"); 1533 break; 1534 case 2: 1535 printf("L1 Entry Enabled\n"); 1536 break; 1537 case 3: 1538 printf("L0s and L1 Entry Enabled\n"); 1539 break; 1540 } 1541 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1542 "128bytes", "64bytes"); 1543 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1544 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1545 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1546 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1547 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1548 onoff("Hardware Autonomous Width Disable", reg, 1549 PCIE_LCSR_HAWD); 1550 onoff("Link Bandwidth Management Interrupt Enable", reg, 1551 PCIE_LCSR_LBMIE); 1552 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1553 PCIE_LCSR_LABIE); 1554 1555 /* Link Status Register */ 1556 reg = regs[o2i(capoff + PCIE_LCSR)]; 1557 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1558 printf(" Negotiated Link Speed: "); 1559 if (((reg >> 16) & 0x000f) < 1 || 1560 ((reg >> 16) & 0x000f) > 3) { 1561 printf("unknown %u value\n", 1562 (unsigned int)(reg & PCIE_LCSR_LINKSPEED) >> 16); 1563 } else { 1564 printf("%sGT/s\n", 1565 linkspeeds[((reg & PCIE_LCSR_LINKSPEED) >> 16)-1]); 1566 } 1567 printf(" Negotiated Link Width: x%u lanes\n", 1568 (reg >> 20) & 0x003f); 1569 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1570 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1571 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1572 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1573 onoff("Link Bandwidth Management Status", reg, 1574 PCIE_LCSR_LINK_BW_MGMT); 1575 onoff("Link Autonomous Bandwidth Status", reg, 1576 PCIE_LCSR_LINK_AUTO_BW); 1577 } 1578 1579 if (check_slot == true) { 1580 /* Slot Capability Register */ 1581 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1582 printf(" Slot Capability Register: %08x\n", reg); 1583 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1584 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1585 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1586 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1587 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1588 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1589 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1590 printf(" Slot Power Limit Value: %d\n", 1591 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1592 printf(" Slot Power Limit Scale: %d\n", 1593 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1594 onoff("Electromechanical Interlock Present", reg, 1595 PCIE_SLCAP_EIP); 1596 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1597 printf(" Physical Slot Number: %d\n", 1598 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1599 1600 /* Slot Control Register */ 1601 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1602 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1603 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1604 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1605 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1606 onoff("Presense Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1607 onoff("Command Completed Interrupt Enabled", reg, 1608 PCIE_SLCSR_CCE); 1609 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1610 printf(" Attention Indicator Control: "); 1611 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1612 case 0x0: 1613 printf("reserved\n"); 1614 break; 1615 case 0x1: 1616 printf("on\n"); 1617 break; 1618 case 0x2: 1619 printf("blink\n"); 1620 break; 1621 case 0x3: 1622 printf("off\n"); 1623 break; 1624 } 1625 printf(" Power Indicator Control: "); 1626 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1627 case 0x0: 1628 printf("reserved\n"); 1629 break; 1630 case 0x1: 1631 printf("on\n"); 1632 break; 1633 case 0x2: 1634 printf("blink\n"); 1635 break; 1636 case 0x3: 1637 printf("off\n"); 1638 break; 1639 } 1640 onoff("Power Controller Control", reg, PCIE_SLCSR_PCC); 1641 onoff("Electromechanical Interlock Control", 1642 reg, PCIE_SLCSR_EIC); 1643 onoff("Data Link Layer State Changed Enable", reg, 1644 PCIE_SLCSR_DLLSCE); 1645 1646 /* Slot Status Register */ 1647 printf(" Slot Status Register: %04x\n", reg >> 16); 1648 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1649 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1650 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1651 onoff("Presense Detect Changed", reg, PCIE_SLCSR_PDC); 1652 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1653 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1654 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1655 onoff("Electromechanical Interlock engaged", reg, 1656 PCIE_SLCSR_EIS); 1657 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 1658 } 1659 1660 if (check_rootport == true) { 1661 /* Root Control Register */ 1662 reg = regs[o2i(capoff + PCIE_RCR)]; 1663 printf(" Root Control Register: %04x\n", reg & 0xffff); 1664 onoff("SERR on Correctable Error Enable", reg, 1665 PCIE_RCR_SERR_CER); 1666 onoff("SERR on Non-Fatal Error Enable", reg, 1667 PCIE_RCR_SERR_NFER); 1668 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 1669 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 1670 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 1671 1672 /* Root Capability Register */ 1673 printf(" Root Capability Register: %04x\n", 1674 reg >> 16); 1675 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 1676 1677 /* Root Status Register */ 1678 reg = regs[o2i(capoff + PCIE_RSR)]; 1679 printf(" Root Status Register: %08x\n", reg); 1680 printf(" PME Requester ID: %04x\n", 1681 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1682 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 1683 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 1684 } 1685 1686 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1687 if (pciever < 2) 1688 return; 1689 1690 /* Device Capabilities 2 */ 1691 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1692 printf(" Device Capabilities 2: 0x%08x\n", reg); 1693 printf(" Completion Timeout Ranges Supported: %u \n", 1694 (unsigned int)(reg & PCIE_DCAP2_COMPT_RANGE)); 1695 onoff("Completion Timeout Disable Supported", reg, 1696 PCIE_DCAP2_COMPT_DIS); 1697 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 1698 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 1699 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 1700 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 1701 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 1702 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 1703 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 1704 printf(" TPH Completer Supported: %u\n", 1705 (unsigned int)(reg & PCIE_DCAP2_TPH_COMP) >> 12); 1706 printf(" OBFF Supported: "); 1707 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 1708 case 0x0: 1709 printf("Not supported\n"); 1710 break; 1711 case 0x1: 1712 printf("Message only\n"); 1713 break; 1714 case 0x2: 1715 printf("WAKE# only\n"); 1716 break; 1717 case 0x3: 1718 printf("Both\n"); 1719 break; 1720 } 1721 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 1722 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 1723 printf(" Max End-End TLP Prefixes: %u\n", 1724 (unsigned int)(reg & PCIE_DCAP2_MAX_EETLP) >> 22); 1725 1726 /* Device Control 2 */ 1727 reg = regs[o2i(capoff + PCIE_DCSR2)]; 1728 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 1729 printf(" Completion Timeout Value: "); 1730 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 1731 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 1732 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 1733 onoff("AtomicOp Rquester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 1734 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 1735 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 1736 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 1737 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 1738 printf(" OBFF: "); 1739 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 1740 case 0x0: 1741 printf("Disabled\n"); 1742 break; 1743 case 0x1: 1744 printf("Enabled with Message Signaling Variation A\n"); 1745 break; 1746 case 0x2: 1747 printf("Enabled with Message Signaling Variation B\n"); 1748 break; 1749 case 0x3: 1750 printf("Enabled using WAKE# signaling\n"); 1751 break; 1752 } 1753 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 1754 1755 if (check_link) { 1756 /* Link Capability 2 */ 1757 reg = regs[o2i(capoff + PCIE_LCAP2)]; 1758 printf(" Link Capabilities 2: 0x%08x\n", reg); 1759 val = (reg & PCIE_LCAP2_SUP_LNKSV) >> 1; 1760 printf(" Supported Link Speed Vector:"); 1761 for (i = 0; i <= 2; i++) { 1762 if (((val >> i) & 0x01) != 0) 1763 printf(" %sGT/s", linkspeeds[i]); 1764 } 1765 printf("\n"); 1766 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 1767 1768 /* Link Control 2 */ 1769 reg = regs[o2i(capoff + PCIE_LCSR2)]; 1770 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 1771 printf(" Target Link Speed: "); 1772 val = reg & PCIE_LCSR2_TGT_LSPEED; 1773 if (val < 1 || val > 3) 1774 printf("unknown %u value\n", val); 1775 else 1776 printf("%sGT/s\n", linkspeeds[val - 1]); 1777 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 1778 onoff("HW Autonomous Speed Disabled", reg, 1779 PCIE_LCSR2_HW_AS_DIS); 1780 onoff("Selectable De-emphasis", reg, PCIE_LCSR2_SEL_DEEMP); 1781 printf(" Transmit Margin: %u\n", 1782 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 1783 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 1784 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 1785 printf(" Compliance Present/De-emphasis: %u\n", 1786 (unsigned int)(reg & PCIE_LCSR2_COMP_DEEMP) >> 12); 1787 1788 /* Link Status 2 */ 1789 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 1790 onoff("Current De-emphasis Level", reg, PCIE_LCSR2_DEEMP_LVL); 1791 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 1792 onoff("Equalization Phase 1 Successful", reg, 1793 PCIE_LCSR2_EQP1_SUC); 1794 onoff("Equalization Phase 2 Successful", reg, 1795 PCIE_LCSR2_EQP2_SUC); 1796 onoff("Equalization Phase 3 Successful", reg, 1797 PCIE_LCSR2_EQP3_SUC); 1798 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 1799 } 1800 1801 /* Slot Capability 2 */ 1802 /* Slot Control 2 */ 1803 /* Slot Status 2 */ 1804 } 1805 1806 static void 1807 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 1808 { 1809 pcireg_t reg; 1810 1811 printf("\n MSI-X Capability Register\n"); 1812 1813 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 1814 printf(" Message Control register: 0x%04x\n", 1815 (reg >> 16) & 0xff); 1816 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 1817 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 1818 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 1819 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 1820 printf(" Table offset register: 0x%08x\n", reg); 1821 printf(" Table offset: %08x\n", reg & PCI_MSIX_TBLOFFSET_MASK); 1822 printf(" BIR: 0x%x\n", reg & PCI_MSIX_TBLBIR_MASK); 1823 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 1824 printf(" Pending bit array register: 0x%08x\n", reg); 1825 printf(" Pending bit array offset: %08x\n", 1826 reg & PCI_MSIX_PBAOFFSET_MASK); 1827 printf(" BIR: 0x%x\n", reg & PCI_MSIX_PBABIR_MASK); 1828 } 1829 1830 static void 1831 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 1832 { 1833 pcireg_t reg; 1834 1835 printf("\n Serial ATA Capability Register\n"); 1836 1837 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 1838 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 1839 printf(" Revision: %u.%u\n", 1840 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 1841 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 1842 1843 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 1844 1845 printf(" BAR Register: 0x%08x\n", reg); 1846 printf(" Register location: "); 1847 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 1848 printf("in config space\n"); 1849 else { 1850 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 1851 printf(" BAR offset: 0x%08x\n", 1852 (pcireg_t)__SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 1853 } 1854 } 1855 1856 static void 1857 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 1858 { 1859 pcireg_t reg; 1860 1861 printf("\n Advanced Features Capability Register\n"); 1862 1863 reg = regs[o2i(capoff + PCI_AFCAPR)]; 1864 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 1865 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 1866 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 1867 reg = regs[o2i(capoff + PCI_AFCSR)]; 1868 printf(" AF Control register: 0x%02x\n", reg & 0xff); 1869 /* 1870 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 1871 * and it's always 0 on read 1872 */ 1873 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 1874 onoff("Transaction Pending", reg, PCI_AFSR_TP); 1875 } 1876 1877 static struct { 1878 pcireg_t cap; 1879 const char *name; 1880 void (*printfunc)(const pcireg_t *, int); 1881 } pci_captab[] = { 1882 { PCI_CAP_RESERVED0, "reserved", NULL }, 1883 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 1884 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 1885 { PCI_CAP_VPD, "VPD", NULL }, 1886 { PCI_CAP_SLOTID, "SlotID", NULL }, 1887 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 1888 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 1889 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 1890 { PCI_CAP_LDT, "HyperTransport", NULL }, 1891 { PCI_CAP_VENDSPEC, "Vendor-specific", 1892 pci_conf_print_vendspec_cap }, 1893 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 1894 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 1895 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 1896 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 1897 pci_conf_print_subsystem_cap }, 1898 { PCI_CAP_AGP8, "AGP 8x", NULL }, 1899 { PCI_CAP_SECURE, "Secure Device", NULL }, 1900 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 1901 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 1902 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 1903 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap } 1904 }; 1905 1906 static int 1907 pci_conf_find_cap(const pcireg_t *regs, int capoff, unsigned int capid, 1908 int *offsetp) 1909 { 1910 pcireg_t rval; 1911 int off; 1912 1913 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1914 off != 0; 1915 off = PCI_CAPLIST_NEXT(rval)) { 1916 rval = regs[o2i(off)]; 1917 if (capid == PCI_CAPLIST_CAP(rval)) { 1918 if (offsetp != NULL) 1919 *offsetp = off; 1920 return 1; 1921 } 1922 } 1923 return 0; 1924 } 1925 1926 static void 1927 pci_conf_print_caplist( 1928 #ifdef _KERNEL 1929 pci_chipset_tag_t pc, pcitag_t tag, 1930 #endif 1931 const pcireg_t *regs, int capoff) 1932 { 1933 int off; 1934 pcireg_t foundcap; 1935 pcireg_t rval; 1936 bool foundtable[__arraycount(pci_captab)]; 1937 unsigned int i; 1938 1939 /* Clear table */ 1940 for (i = 0; i < __arraycount(pci_captab); i++) 1941 foundtable[i] = false; 1942 1943 /* Print capability register's offset and the type first */ 1944 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1945 off != 0; 1946 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 1947 rval = regs[o2i(off)]; 1948 printf(" Capability register at 0x%02x\n", off); 1949 1950 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 1951 foundcap = PCI_CAPLIST_CAP(rval); 1952 if (foundcap < __arraycount(pci_captab)) { 1953 printf("%s)\n", pci_captab[foundcap].name); 1954 /* Mark as found */ 1955 foundtable[foundcap] = true; 1956 } else 1957 printf("unknown)\n"); 1958 } 1959 1960 /* 1961 * And then, print the detail of each capability registers 1962 * in capability value's order. 1963 */ 1964 for (i = 0; i < __arraycount(pci_captab); i++) { 1965 if (foundtable[i] == false) 1966 continue; 1967 1968 /* 1969 * The type was found. Search capability list again and 1970 * print all capabilities that the capabiliy type is 1971 * the same. This is required because some capabilities 1972 * appear multiple times (e.g. HyperTransport capability). 1973 */ 1974 if (pci_conf_find_cap(regs, capoff, i, &off)) { 1975 rval = regs[o2i(off)]; 1976 if (pci_captab[i].printfunc != NULL) 1977 pci_captab[i].printfunc(regs, off); 1978 } 1979 } 1980 } 1981 1982 /* Extended Capability */ 1983 1984 static void 1985 pci_conf_print_aer_cap_uc(pcireg_t reg) 1986 { 1987 1988 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 1989 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 1990 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 1991 onoff("Poisoned TLP", reg, PCI_AER_UC_POISONED_TLP); 1992 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 1993 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 1994 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 1995 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 1996 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 1997 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 1998 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 1999 onoff("Unsupported Request Error", reg, 2000 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2001 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2002 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2003 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2004 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2005 onoff("TLP Prefix Blocked Error", reg, 2006 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2007 } 2008 2009 static void 2010 pci_conf_print_aer_cap_cor(pcireg_t reg) 2011 { 2012 2013 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2014 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2015 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2016 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2017 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2018 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2019 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2020 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2021 } 2022 2023 static void 2024 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2025 { 2026 2027 printf(" First Error Pointer: 0x%04x\n", 2028 (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2029 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2030 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2031 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2032 onoff("ECRC Check Enab", reg, PCI_AER_ECRC_CHECK_ENABLE); 2033 onoff("Multiple Header Recording Capable", reg, 2034 PCI_AER_MULT_HDR_CAPABLE); 2035 onoff("Multiple Header Recording Enable", reg, PCI_AER_MULT_HDR_ENABLE); 2036 2037 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2038 if (!tlp_prefix_log) 2039 return; 2040 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2041 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2042 } 2043 2044 static void 2045 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2046 { 2047 2048 onoff("Correctable Error Reporting Enable", reg, 2049 PCI_AER_ROOTERR_COR_ENABLE); 2050 onoff("Non-Fatal Error Reporting Enable", reg, 2051 PCI_AER_ROOTERR_NF_ENABLE); 2052 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2053 } 2054 2055 static void 2056 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2057 { 2058 2059 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2060 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2061 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2062 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2063 PCI_AER_ROOTERR_MULTI_UC_ERR); 2064 onoff("First Uncorrectable Fatal", reg, PCI_AER_ROOTERR_FIRST_UC_FATAL); 2065 onoff("Non-Fatal Error Messages Received", reg, PCI_AER_ROOTERR_NF_ERR); 2066 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2067 printf(" Advanced Error Interrupt Message Number: 0x%u\n", 2068 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2069 } 2070 2071 static void 2072 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2073 { 2074 2075 printf(" Correctable Source ID: 0x%04x\n", 2076 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2077 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2078 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2079 } 2080 2081 static void 2082 pci_conf_print_aer_cap(const pcireg_t *regs, int capoff, int extcapoff) 2083 { 2084 pcireg_t reg; 2085 int pcie_capoff; 2086 int pcie_devtype = -1; 2087 bool tlp_prefix_log = false; 2088 2089 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2090 reg = regs[o2i(pcie_capoff)]; 2091 pcie_devtype = reg & PCIE_XCAP_TYPE_MASK; 2092 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2093 if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2094 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2095 /* End-End TLP Prefix Supported */ 2096 if (reg & PCIE_DCAP2_EETLP_PREF) { 2097 tlp_prefix_log = true; 2098 } 2099 } 2100 } 2101 2102 printf("\n Advanced Error Reporting Register\n"); 2103 2104 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2105 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2106 pci_conf_print_aer_cap_uc(reg); 2107 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2108 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2109 pci_conf_print_aer_cap_uc(reg); 2110 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2111 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2112 pci_conf_print_aer_cap_uc(reg); 2113 2114 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2115 printf(" Correctable Error Status register: 0x%08x\n", reg); 2116 pci_conf_print_aer_cap_cor(reg); 2117 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2118 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2119 pci_conf_print_aer_cap_cor(reg); 2120 2121 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2122 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2123 reg); 2124 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2125 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2126 printf(" Header Log register:\n"); 2127 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2128 extcapoff + PCI_AER_ROOTERR_CMD); 2129 2130 switch (pcie_devtype) { 2131 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ 2132 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ 2133 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2134 printf(" Root Error Command register: 0x%08x\n", reg); 2135 pci_conf_print_aer_cap_rooterr_cmd(reg); 2136 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2137 printf(" Root Error Status register: 0x%08x\n", reg); 2138 pci_conf_print_aer_cap_rooterr_status(reg); 2139 2140 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2141 printf(" Error Source Identification: 0x%04x\n", reg); 2142 pci_conf_print_aer_cap_errsrc_id(reg); 2143 break; 2144 } 2145 2146 if (tlp_prefix_log) { 2147 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2148 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2149 } 2150 } 2151 2152 static void 2153 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2154 pcireg_t parbsel, int parbsize) 2155 { 2156 pcireg_t reg; 2157 int num = 16 << parbsel; 2158 int num_per_reg = sizeof(pcireg_t) / parbsize; 2159 int i, j; 2160 2161 /* First, dump the table */ 2162 for (i = 0; i < num; i += num_per_reg) { 2163 reg = regs[o2i(off + i / num_per_reg)]; 2164 printf(" %s Arbitration Table: 0x%08x\n", name, reg); 2165 } 2166 /* And then, decode each entry */ 2167 for (i = 0; i < num; i += num_per_reg) { 2168 reg = regs[o2i(off + i / num_per_reg)]; 2169 for (j = 0; j < num_per_reg; j++) 2170 printf(" Phase[%d]: %d\n", j, reg); 2171 } 2172 } 2173 2174 static void 2175 pci_conf_print_vc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2176 { 2177 pcireg_t reg, n; 2178 int parbtab, parbsize; 2179 pcireg_t parbsel; 2180 int varbtab, varbsize; 2181 pcireg_t varbsel; 2182 int i, count; 2183 2184 printf("\n Virtual Channel Register\n"); 2185 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2186 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2187 count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2188 printf(" Extended VC Count: %d\n", count); 2189 n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2190 printf(" Low Priority Extended VC Count: %u\n", n); 2191 n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2192 printf(" Reference Clock: %s\n", 2193 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 2194 parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2195 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2196 2197 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 2198 printf(" Port VC Capability register 2: 0x%08x\n", reg); 2199 onoff("Hardware fixed arbitration scheme", 2200 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 2201 onoff("WRR arbitration with 32 phases", 2202 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 2203 onoff("WRR arbitration with 64 phases", 2204 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 2205 onoff("WRR arbitration with 128 phases", 2206 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 2207 varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 2208 printf(" VC Arbitration Table Offset: 0x%x\n", varbtab); 2209 2210 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 2211 printf(" Port VC Control register: 0x%04x\n", reg); 2212 varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 2213 printf(" VC Arbitration Select: 0x%x\n", varbsel); 2214 2215 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 2216 printf(" Port VC Status register: 0x%04x\n", reg); 2217 onoff("VC Arbitration Table Status", 2218 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 2219 2220 for (i = 0; i < count + 1; i++) { 2221 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 2222 printf(" VC number %d\n", i); 2223 printf(" VC Resource Capability Register: 0x%08x\n", reg); 2224 onoff(" Non-configurable Hardware fixed arbitration scheme", 2225 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 2226 onoff(" WRR arbitration with 32 phases", 2227 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 2228 onoff(" WRR arbitration with 64 phases", 2229 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 2230 onoff(" WRR arbitration with 128 phases", 2231 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 2232 onoff(" Time-based WRR arbitration with 128 phases", 2233 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 2234 onoff(" WRR arbitration with 256 phases", 2235 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 2236 onoff(" Advanced Packet Switching", 2237 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 2238 onoff(" Reject Snoop Transaction", 2239 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 2240 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 2241 printf(" Maximum Time Slots: %d\n", n); 2242 parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S; 2243 printf(" Port Arbitration Table offset: 0x%02x\n", 2244 parbtab); 2245 2246 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 2247 printf(" VC Resource Control Register: 0x%08x\n", reg); 2248 printf(" TC/VC Map: %02x\n", 2249 (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 2250 /* 2251 * The load Port Arbitration Table bit is used to update 2252 * the Port Arbitration logic and it's always 0 on read, so 2253 * we don't print it. 2254 */ 2255 parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 2256 printf(" Port Arbitration Select: %x\n", parbsel); 2257 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 2258 printf(" VC ID %d\n", n); 2259 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 2260 2261 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 2262 printf(" VC Resource Status Register: 0x%08x\n", reg); 2263 onoff(" Port Arbitration Table Status", 2264 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 2265 onoff(" VC Negotiation Pending", 2266 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 2267 2268 if ((parbtab != 0) && (parbsel != 0)) 2269 pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab, 2270 "Port", parbsel, parbsize); 2271 } 2272 2273 varbsize = 8; 2274 if ((varbtab != 0) && (varbsel != 0)) 2275 pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab, 2276 " VC", varbsel, varbsize); 2277 } 2278 2279 static const char * 2280 pci_conf_print_pwrbdgt_base_power(uint8_t reg) 2281 { 2282 2283 switch (reg) { 2284 case 0xf0: 2285 return "250W"; 2286 case 0xf1: 2287 return "275W"; 2288 case 0xf2: 2289 return "300W"; 2290 default: 2291 return "Unknown"; 2292 } 2293 } 2294 2295 static const char * 2296 pci_conf_print_pwrbdgt_data_scale(uint8_t reg) 2297 { 2298 2299 switch (reg) { 2300 case 0x00: 2301 return "1.0x"; 2302 case 0x01: 2303 return "0.1x"; 2304 case 0x02: 2305 return "0.01x"; 2306 case 0x03: 2307 return "0.001x"; 2308 default: 2309 return "wrong value!"; 2310 } 2311 } 2312 2313 static const char * 2314 pci_conf_print_pwrbdgt_type(uint8_t reg) 2315 { 2316 2317 switch (reg) { 2318 case 0x00: 2319 return "PME Aux"; 2320 case 0x01: 2321 return "Auxilary"; 2322 case 0x02: 2323 return "Idle"; 2324 case 0x03: 2325 return "Sustained"; 2326 case 0x07: 2327 return "Maximun"; 2328 default: 2329 return "Unknown"; 2330 } 2331 } 2332 2333 static const char * 2334 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 2335 { 2336 2337 switch (reg) { 2338 case 0x00: 2339 return "Power(12V)"; 2340 case 0x01: 2341 return "Power(3.3V)"; 2342 case 0x02: 2343 return "Power(1.5V or 1.8V)"; 2344 case 0x07: 2345 return "Thermal"; 2346 default: 2347 return "Unknown"; 2348 } 2349 } 2350 2351 static void 2352 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff) 2353 { 2354 pcireg_t reg; 2355 2356 printf("\n Power Budget Register\n"); 2357 2358 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 2359 printf(" Data Select register: 0x%08x\n", reg); 2360 2361 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 2362 printf(" Data register: 0x%08x\n", reg); 2363 printf(" Base Power: %s\n", 2364 pci_conf_print_pwrbdgt_base_power((uint8_t)reg)); 2365 printf(" Data Scale: %s\n", 2366 pci_conf_print_pwrbdgt_data_scale( 2367 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE)))); 2368 printf(" PM Sub State: 0x%hhx\n", 2369 (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 2370 printf(" PM State: D%u\n", 2371 (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 2372 printf(" Type: %s\n", 2373 pci_conf_print_pwrbdgt_type( 2374 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 2375 printf(" Power Rail: %s\n", 2376 pci_conf_print_pwrbdgt_pwrrail( 2377 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 2378 2379 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 2380 printf(" Power Budget Capability register: 0x%08x\n", reg); 2381 onoff("System Allocated", 2382 reg, PCI_PWRBDGT_CAP_SYSALLOC); 2383 } 2384 2385 static const char * 2386 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 2387 { 2388 2389 switch (type) { 2390 case 0x00: 2391 return "Configuration Space Element"; 2392 case 0x01: 2393 return "System Egress Port or internal sink (memory)"; 2394 case 0x02: 2395 return "Internal Root Complex Link"; 2396 default: 2397 return "Unknown"; 2398 } 2399 } 2400 2401 static void 2402 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int capoff, int extcapoff) 2403 { 2404 pcireg_t reg; 2405 unsigned char nent, linktype; 2406 int i; 2407 2408 printf("\n Root Complex Link Declaration\n"); 2409 2410 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 2411 printf(" Element Self Description Register: 0x%08x\n", reg); 2412 printf(" Element Type: %s\n", 2413 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 2414 nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 2415 printf(" Number of Link Entries: %hhu\n", nent); 2416 printf(" Component ID: %hhu\n", 2417 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 2418 printf(" Port Number: %hhu\n", 2419 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 2420 for (i = 0; i < nent; i++) { 2421 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 2422 printf(" Link Entry %d:\n", i + 1); 2423 printf(" Link Description Register: 0x%08x\n", reg); 2424 onoff(" Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID); 2425 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 2426 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 2427 "Configuration Space", "Memory-Mapped Space"); 2428 onoff(" Associated RCRB Header", reg, 2429 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 2430 printf(" Target Component ID: %hhu\n", 2431 (unsigned char)__SHIFTOUT(reg, 2432 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 2433 printf(" Target Port Number: %hhu\n", 2434 (unsigned char)__SHIFTOUT(reg, 2435 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 2436 2437 if (linktype == 0) { 2438 /* Memory-Mapped Space */ 2439 reg = regs[o2i(extcapoff 2440 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 2441 printf(" Link Address Low Register: 0x%08x\n", 2442 reg); 2443 reg = regs[o2i(extcapoff 2444 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 2445 printf(" Link Address High Register: 0x%08x\n", 2446 reg); 2447 } else { 2448 unsigned int nb; 2449 pcireg_t lo, hi; 2450 2451 /* Configuration Space */ 2452 lo = regs[o2i(extcapoff 2453 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 2454 printf(" Configuration Space Low Register: " 2455 "0x%08x\n", lo); 2456 hi = regs[o2i(extcapoff 2457 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 2458 printf(" Configuration Space High Register: " 2459 "0x%08x\n", hi); 2460 nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 2461 printf(" N: %u\n", nb); 2462 printf(" Func: %hhu\n", 2463 (unsigned char)__SHIFTOUT(lo, 2464 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 2465 printf(" Dev: %hhu\n", 2466 (unsigned char)__SHIFTOUT(lo, 2467 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 2468 printf(" Bus: %hhu\n", 2469 (unsigned char)__SHIFTOUT(lo, 2470 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 2471 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 2472 printf(" Configuration Space Base Address: " 2473 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 2474 } 2475 } 2476 } 2477 2478 /* XXX pci_conf_print_rclink_ctl_cap */ 2479 2480 static void 2481 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2482 { 2483 pcireg_t reg; 2484 2485 printf("\n Root Complex Event Collector Association\n"); 2486 2487 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 2488 printf(" Association Bitmap for Root Complex Integrated Devices:" 2489 " 0x%08x\n", reg); 2490 } 2491 2492 /* XXX pci_conf_print_mfvc_cap */ 2493 /* XXX pci_conf_print_vc2_cap */ 2494 /* XXX pci_conf_print_rcrb_cap */ 2495 /* XXX pci_conf_print_vendor_cap */ 2496 /* XXX pci_conf_print_cac_cap */ 2497 2498 static void 2499 pci_conf_print_acs_cap(const pcireg_t *regs, int capoff, int extcapoff) 2500 { 2501 pcireg_t reg, cap, ctl; 2502 unsigned int size, i; 2503 2504 printf("\n Access Control Services\n"); 2505 2506 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 2507 cap = reg & 0xffff; 2508 ctl = reg >> 16; 2509 printf(" ACS Capability register: 0x%08x\n", cap); 2510 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 2511 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 2512 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 2513 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 2514 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 2515 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 2516 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 2517 size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 2518 if (size == 0) 2519 size = 256; 2520 printf(" Egress Control Vector Size: %u\n", size); 2521 printf(" ACS Control register: 0x%08x\n", ctl); 2522 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 2523 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 2524 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 2525 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 2526 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 2527 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 2528 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 2529 2530 /* 2531 * If the P2P Egress Control Capability bit is 0, ignore the Egress 2532 * Control vector. 2533 */ 2534 if ((cap & PCI_ACS_CAP_E) == 0) 2535 return; 2536 for (i = 0; i < size; i += 32) 2537 printf(" Egress Control Vector [%u..%u]: %x\n", i + 31, 2538 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 2539 } 2540 2541 static void 2542 pci_conf_print_ari_cap(const pcireg_t *regs, int capoff, int extcapoff) 2543 { 2544 pcireg_t reg, cap, ctl; 2545 2546 printf("\n Alternative Routing-ID Interpretation Register\n"); 2547 2548 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2549 cap = reg & 0xffff; 2550 ctl = reg >> 16; 2551 printf(" Capability register: 0x%08x\n", cap); 2552 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 2553 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 2554 printf(" Next Function Number: %u\n", 2555 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 2556 printf(" Control register: 0x%08x\n", ctl); 2557 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 2558 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 2559 printf(" Function Group: %u\n", 2560 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 2561 } 2562 2563 static void 2564 pci_conf_print_ats_cap(const pcireg_t *regs, int capoff, int extcapoff) 2565 { 2566 pcireg_t reg, cap, ctl; 2567 unsigned int num; 2568 2569 printf("\n Address Translation Services\n"); 2570 2571 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2572 cap = reg & 0xffff; 2573 ctl = reg >> 16; 2574 printf(" Capability register: 0x%04x\n", cap); 2575 num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 2576 if (num == 0) 2577 num = 32; 2578 printf(" Invalidate Queue Depth: %u\n", num); 2579 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 2580 2581 printf(" Control register: 0x%04x\n", ctl); 2582 printf(" Smallest Translation Unit: %u\n", 2583 (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU)); 2584 onoff("Enable", reg, PCI_ATS_CTL_EN); 2585 } 2586 2587 static void 2588 pci_conf_print_sernum_cap(const pcireg_t *regs, int capoff, int extcapoff) 2589 { 2590 pcireg_t lo, hi; 2591 2592 printf("\n Device Serial Number Register\n"); 2593 2594 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 2595 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 2596 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 2597 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 2598 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 2599 } 2600 2601 static void 2602 pci_conf_print_sriov_cap(const pcireg_t *regs, int capoff, int extcapoff) 2603 { 2604 char buf[sizeof("99999 MB")]; 2605 pcireg_t reg; 2606 pcireg_t total_vfs; 2607 int i; 2608 bool first; 2609 2610 printf("\n Single Root IO Virtualization Register\n"); 2611 2612 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 2613 printf(" Capabilities register: 0x%08x\n", reg); 2614 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 2615 onoff("ARI Capable Hierarchy Preserved", reg, 2616 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 2617 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 2618 printf(" VF Migration Interrupt Message Number: 0x%u\n", 2619 (pcireg_t)__SHIFTOUT(reg, 2620 PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 2621 } 2622 2623 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 2624 printf(" Control register: 0x%04x\n", reg); 2625 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 2626 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 2627 onoff("VF Migration Interrupt Enable", reg, 2628 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 2629 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 2630 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 2631 2632 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 2633 printf(" Status register: 0x%04x\n", reg); 2634 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 2635 2636 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 2637 printf(" InitialVFs register: 0x%04x\n", reg); 2638 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 2639 printf(" TotalVFs register: 0x%04x\n", reg); 2640 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 2641 printf(" NumVFs register: 0x%04x\n", reg); 2642 2643 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 2644 printf(" Function Dependency Link register: 0x%04x\n", reg); 2645 2646 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 2647 printf(" First VF Offset register: 0x%04x\n", reg); 2648 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 2649 printf(" VF Stride register: 0x%04x\n", reg); 2650 2651 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 2652 printf(" Supported Page Sizes register: 0x%08x\n", reg); 2653 printf(" Supported Page Size:"); 2654 for (i = 0, first = true; i < 32; i++) { 2655 if (reg & __BIT(i)) { 2656 #ifdef _KERNEL 2657 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 2658 #else 2659 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 2660 HN_AUTOSCALE, 0); 2661 #endif 2662 printf("%s %s", first ? "" : ",", buf); 2663 first = false; 2664 } 2665 } 2666 printf("\n"); 2667 2668 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 2669 printf(" System Page Sizes register: 0x%08x\n", reg); 2670 printf(" Page Size: "); 2671 if (reg != 0) { 2672 #ifdef _KERNEL 2673 format_bytes(buf, sizeof(buf), 1LL << (ffs(reg) + 12)); 2674 #else 2675 humanize_number(buf, sizeof(buf), 1LL << (ffs(reg) + 12), "B", 2676 HN_AUTOSCALE, 0); 2677 #endif 2678 printf("%s", buf); 2679 } else { 2680 printf("unknown"); 2681 } 2682 printf("\n"); 2683 2684 for (i = 0; i < 6; i++) { 2685 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 2686 printf(" VF BAR%d register: 0x%08x\n", i, reg); 2687 } 2688 2689 if (total_vfs > 0) { 2690 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 2691 printf(" VF Migration State Array Offset register: 0x%08x\n", 2692 reg); 2693 printf(" VF Migration State Offset: 0x%08x\n", 2694 (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 2695 i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 2696 printf(" VF Migration State BIR: "); 2697 if (i >= 0 && i <= 5) { 2698 printf("BAR%d", i); 2699 } else { 2700 printf("unknown BAR (%d)", i); 2701 } 2702 printf("\n"); 2703 } 2704 } 2705 2706 /* XXX pci_conf_print_mriov_cap */ 2707 2708 static void 2709 pci_conf_print_multicast_cap(const pcireg_t *regs, int capoff, int extcapoff) 2710 { 2711 pcireg_t reg, cap, ctl; 2712 pcireg_t regl, regh; 2713 uint64_t addr; 2714 int n; 2715 2716 printf("\n Multicast\n"); 2717 2718 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 2719 cap = reg & 0xffff; 2720 ctl = reg >> 16; 2721 printf(" Capability Register: 0x%04x\n", cap); 2722 printf(" Max Group: %u\n", 2723 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 2724 2725 /* Endpoint Only */ 2726 n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 2727 if (n > 0) 2728 printf(" Windw Size Requested: %d\n", 1 << (n - 1)); 2729 2730 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 2731 2732 printf(" Control Register: 0x%04x\n", ctl); 2733 printf(" Num Group: %u\n", 2734 (unsigned int)__SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 2735 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 2736 2737 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 2738 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 2739 printf(" Base Address Register 0: 0x%08x\n", regl); 2740 printf(" Base Address Register 1: 0x%08x\n", regh); 2741 printf(" Index Position: %u\n", 2742 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 2743 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 2744 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 2745 2746 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 2747 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 2748 printf(" Receive Register 0: 0x%08x\n", regl); 2749 printf(" Receive Register 1: 0x%08x\n", regh); 2750 2751 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 2752 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 2753 printf(" Block All Register 0: 0x%08x\n", regl); 2754 printf(" Block All Register 1: 0x%08x\n", regh); 2755 2756 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 2757 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 2758 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 2759 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 2760 2761 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 2762 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 2763 printf(" Overlay BAR 0: 0x%08x\n", regl); 2764 printf(" Overlay BAR 1: 0x%08x\n", regh); 2765 2766 n = regl & PCI_MCAST_OVERLAYL_SIZE; 2767 printf(" Overlay Size: "); 2768 if (n >= 6) 2769 printf("%d\n", n); 2770 else 2771 printf("off\n"); 2772 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 2773 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 2774 } 2775 2776 static void 2777 pci_conf_print_page_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 2778 { 2779 pcireg_t reg, ctl, sta; 2780 2781 printf("\n Page Request\n"); 2782 2783 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 2784 ctl = reg & 0xffff; 2785 sta = reg >> 16; 2786 printf(" Control Register: 0x%04x\n", ctl); 2787 onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E); 2788 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 2789 2790 printf(" Status Register: 0x%04x\n", sta); 2791 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 2792 onoff("Unexpected Page Request Group Index", reg, 2793 PCI_PAGE_REQ_STA_UPRGI); 2794 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 2795 2796 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 2797 printf(" Outstanding Page Request Capacity: %u\n", reg); 2798 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 2799 printf(" Outstanding Page Request Allocation: %u\n", reg); 2800 } 2801 2802 /* XXX pci_conf_print_amd_cap */ 2803 /* XXX pci_conf_print_resize_bar_cap */ 2804 /* XXX pci_conf_print_dpa_cap */ 2805 2806 static const char * 2807 pci_conf_print_tph_req_cap_sttabloc(unsigned char val) 2808 { 2809 2810 switch (val) { 2811 case 0x0: 2812 return "Not Present"; 2813 case 0x1: 2814 return "in the TPH Requester Capability Structure"; 2815 case 0x2: 2816 return "in the MSI-X Table"; 2817 default: 2818 return "Unknown"; 2819 } 2820 } 2821 2822 static void 2823 pci_conf_print_tph_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 2824 { 2825 pcireg_t reg; 2826 int size, i, j; 2827 2828 printf("\n TPH Requester Extended Capability\n"); 2829 2830 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 2831 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 2832 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 2833 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 2834 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 2835 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 2836 printf(" ST Table Location: %s\n", 2837 pci_conf_print_tph_req_cap_sttabloc( 2838 (unsigned char)__SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC))); 2839 size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 2840 printf(" ST Table Size: %d\n", size); 2841 for (i = 0; i < size ; i += 2) { 2842 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 2843 for (j = 0; j < 2 ; j++) { 2844 uint32_t entry = reg; 2845 2846 if (j != 0) 2847 entry >>= 16; 2848 entry &= 0xffff; 2849 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 2850 i + j, entry); 2851 } 2852 } 2853 } 2854 2855 static void 2856 pci_conf_print_ltr_cap(const pcireg_t *regs, int capoff, int extcapoff) 2857 { 2858 pcireg_t reg; 2859 2860 printf("\n Latency Tolerance Reporting\n"); 2861 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)] & 0xffff; 2862 printf(" Max Snoop Latency Register: 0x%04x\n", reg); 2863 printf(" Max Snoop LatencyValue: %u\n", 2864 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL)); 2865 printf(" Max Snoop LatencyScale: %uns\n", 2866 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE))); 2867 reg = regs[o2i(extcapoff + PCI_LTR_MAXNOSNOOPLAT)] >> 16; 2868 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg); 2869 printf(" Max No-Snoop LatencyValue: %u\n", 2870 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL)); 2871 printf(" Max No-Snoop LatencyScale: %uns\n", 2872 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE))); 2873 } 2874 2875 static void 2876 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int capoff, int extcapoff) 2877 { 2878 int pcie_capoff; 2879 pcireg_t reg; 2880 int i, maxlinkwidth; 2881 2882 printf("\n Secondary PCI Express Register\n"); 2883 2884 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 2885 printf(" Link Control 3 register: 0x%08x\n", reg); 2886 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 2887 onoff("Link Equalization Request Interrupt Enable", 2888 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 2889 2890 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 2891 printf(" Lane Error Status register: 0x%08x\n", reg); 2892 2893 /* Get Max Link Width */ 2894 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)){ 2895 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 2896 maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 2897 } else { 2898 printf("error: falied to get PCIe capablity\n"); 2899 return; 2900 } 2901 for (i = 0; i < maxlinkwidth; i++) { 2902 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 2903 if (i % 2 != 0) 2904 reg >>= 16; 2905 else 2906 reg &= 0xffff; 2907 printf(" Equalization Control Register (Link %d): %04x\n", 2908 i, reg); 2909 printf(" Downstream Port Transmit Preset: 0x%x\n", 2910 (pcireg_t)__SHIFTOUT(reg, 2911 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 2912 printf(" Downstream Port Receive Hint: 0x%x\n", 2913 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 2914 printf(" Upstream Port Transmit Preset: 0x%x\n", 2915 (pcireg_t)__SHIFTOUT(reg, 2916 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 2917 printf(" Upstream Port Receive Hint: 0x%x\n", 2918 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 2919 } 2920 } 2921 2922 /* XXX pci_conf_print_pmux_cap */ 2923 2924 static void 2925 pci_conf_print_pasid_cap(const pcireg_t *regs, int capoff, int extcapoff) 2926 { 2927 pcireg_t reg, cap, ctl; 2928 unsigned int num; 2929 2930 printf("\n Process Address Space ID\n"); 2931 2932 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 2933 cap = reg & 0xffff; 2934 ctl = reg >> 16; 2935 printf(" PASID Capability Register: 0x%04x\n", cap); 2936 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 2937 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 2938 num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 2939 printf(" Max PASID Width: %u\n", num); 2940 2941 printf(" PASID Control Register: 0x%04x\n", ctl); 2942 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 2943 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 2944 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 2945 } 2946 2947 static void 2948 pci_conf_print_lnr_cap(const pcireg_t *regs, int capoff, int extcapoff) 2949 { 2950 pcireg_t reg, cap, ctl; 2951 unsigned int num; 2952 2953 printf("\n LN Requester\n"); 2954 2955 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 2956 cap = reg & 0xffff; 2957 ctl = reg >> 16; 2958 printf(" LNR Capability register: 0x%04x\n", cap); 2959 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 2960 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 2961 num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 2962 printf(" LNR Registration MAX: %u\n", num); 2963 2964 printf(" LNR Control register: 0x%04x\n", ctl); 2965 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 2966 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 2967 num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 2968 printf(" LNR Registration Limit: %u\n", num); 2969 } 2970 2971 /* XXX pci_conf_print_dpc_cap */ 2972 2973 static int 2974 pci_conf_l1pm_cap_tposcale(unsigned char scale) 2975 { 2976 2977 /* Return scale in us */ 2978 switch (scale) { 2979 case 0x0: 2980 return 2; 2981 case 0x1: 2982 return 10; 2983 case 0x2: 2984 return 100; 2985 default: 2986 return -1; 2987 } 2988 } 2989 2990 static void 2991 pci_conf_print_l1pm_cap(const pcireg_t *regs, int capoff, int extcapoff) 2992 { 2993 pcireg_t reg; 2994 int scale, val; 2995 2996 printf("\n L1 PM Substates\n"); 2997 2998 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 2999 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 3000 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 3001 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 3002 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 3003 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 3004 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 3005 printf(" Port Common Mode Restore Time: %uus\n", 3006 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 3007 scale = pci_conf_l1pm_cap_tposcale( 3008 __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 3009 val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 3010 printf(" Port T_POWER_ON: "); 3011 if (scale == -1) 3012 printf("unknown\n"); 3013 else 3014 printf("%dus\n", val * scale); 3015 3016 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 3017 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 3018 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 3019 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 3020 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 3021 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 3022 printf(" Common Mode Restore Time: %uus\n", 3023 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 3024 scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 3025 val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 3026 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 3027 3028 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 3029 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 3030 scale = pci_conf_l1pm_cap_tposcale( 3031 __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 3032 val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 3033 printf(" T_POWER_ON: "); 3034 if (scale == -1) 3035 printf("unknown\n"); 3036 else 3037 printf("%dus\n", val * scale); 3038 } 3039 3040 /* XXX pci_conf_print_ptm_cap */ 3041 /* XXX pci_conf_print_mpcie_cap */ 3042 /* XXX pci_conf_print_frsq_cap */ 3043 /* XXX pci_conf_print_rtr_cap */ 3044 /* XXX pci_conf_print_desigvndsp_cap */ 3045 3046 #undef MS 3047 #undef SM 3048 #undef RW 3049 3050 static struct { 3051 pcireg_t cap; 3052 const char *name; 3053 void (*printfunc)(const pcireg_t *, int, int); 3054 } pci_extcaptab[] = { 3055 { 0, "reserved", 3056 NULL }, 3057 { PCI_EXTCAP_AER, "Advanced Error Reporting", 3058 pci_conf_print_aer_cap }, 3059 { PCI_EXTCAP_VC, "Virtual Channel", 3060 pci_conf_print_vc_cap }, 3061 { PCI_EXTCAP_SERNUM, "Device Serial Number", 3062 pci_conf_print_sernum_cap }, 3063 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 3064 pci_conf_print_pwrbdgt_cap }, 3065 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 3066 pci_conf_print_rclink_dcl_cap }, 3067 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 3068 NULL }, 3069 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 3070 pci_conf_print_rcec_assoc_cap }, 3071 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 3072 NULL }, 3073 { PCI_EXTCAP_VC2, "Virtual Channel", 3074 NULL }, 3075 { PCI_EXTCAP_RCRB, "RCRB Header", 3076 NULL }, 3077 { PCI_EXTCAP_VENDOR, "Vendor Unique", 3078 NULL }, 3079 { PCI_EXTCAP_CAC, "Configuration Access Correction", 3080 NULL }, 3081 { PCI_EXTCAP_ACS, "Access Control Services", 3082 pci_conf_print_acs_cap }, 3083 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 3084 pci_conf_print_ari_cap }, 3085 { PCI_EXTCAP_ATS, "Address Translation Services", 3086 pci_conf_print_ats_cap }, 3087 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 3088 pci_conf_print_sriov_cap }, 3089 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 3090 NULL }, 3091 { PCI_EXTCAP_MCAST, "Multicast", 3092 pci_conf_print_multicast_cap }, 3093 { PCI_EXTCAP_PAGE_REQ, "Page Request", 3094 pci_conf_print_page_req_cap }, 3095 { PCI_EXTCAP_AMD, "Reserved for AMD", 3096 NULL }, 3097 { PCI_EXTCAP_RESIZE_BAR,"Resizable BAR", 3098 NULL }, 3099 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 3100 NULL }, 3101 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 3102 pci_conf_print_tph_req_cap }, 3103 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 3104 pci_conf_print_ltr_cap }, 3105 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 3106 pci_conf_print_sec_pcie_cap }, 3107 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 3108 NULL }, 3109 { PCI_EXTCAP_PASID, "Process Address Space ID", 3110 pci_conf_print_pasid_cap }, 3111 { PCI_EXTCAP_LN_REQ, "LN Requester", 3112 pci_conf_print_lnr_cap }, 3113 { PCI_EXTCAP_DPC, "Downstream Port Containment", 3114 NULL }, 3115 { PCI_EXTCAP_L1PM, "L1 PM Substates", 3116 pci_conf_print_l1pm_cap }, 3117 { PCI_EXTCAP_PTM, "Precision Time Management", 3118 NULL }, 3119 { PCI_EXTCAP_MPCIE, "M-PCIe", 3120 NULL }, 3121 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 3122 NULL }, 3123 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 3124 NULL }, 3125 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 3126 NULL }, 3127 }; 3128 3129 static int 3130 pci_conf_find_extcap(const pcireg_t *regs, int capoff, unsigned int capid, 3131 int *offsetp) 3132 { 3133 int off; 3134 pcireg_t rval; 3135 3136 for (off = PCI_EXTCAPLIST_BASE; 3137 off != 0; 3138 off = PCI_EXTCAPLIST_NEXT(rval)) { 3139 rval = regs[o2i(off)]; 3140 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 3141 if (offsetp != NULL) 3142 *offsetp = off; 3143 return 1; 3144 } 3145 } 3146 return 0; 3147 } 3148 3149 static void 3150 pci_conf_print_extcaplist( 3151 #ifdef _KERNEL 3152 pci_chipset_tag_t pc, pcitag_t tag, 3153 #endif 3154 const pcireg_t *regs, int capoff) 3155 { 3156 int off; 3157 pcireg_t foundcap; 3158 pcireg_t rval; 3159 bool foundtable[__arraycount(pci_extcaptab)]; 3160 unsigned int i; 3161 3162 /* Check Extended capability structure */ 3163 off = PCI_EXTCAPLIST_BASE; 3164 rval = regs[o2i(off)]; 3165 if (rval == 0xffffffff || rval == 0) 3166 return; 3167 3168 /* Clear table */ 3169 for (i = 0; i < __arraycount(pci_extcaptab); i++) 3170 foundtable[i] = false; 3171 3172 /* Print extended capability register's offset and the type first */ 3173 for (;;) { 3174 printf(" Extended Capability Register at 0x%02x\n", off); 3175 3176 foundcap = PCI_EXTCAPLIST_CAP(rval); 3177 printf(" type: 0x%04x (", foundcap); 3178 if (foundcap < __arraycount(pci_extcaptab)) { 3179 printf("%s)\n", pci_extcaptab[foundcap].name); 3180 /* Mark as found */ 3181 foundtable[foundcap] = true; 3182 } else 3183 printf("unknown)\n"); 3184 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 3185 3186 off = PCI_EXTCAPLIST_NEXT(rval); 3187 if (off == 0) 3188 break; 3189 rval = regs[o2i(off)]; 3190 } 3191 3192 /* 3193 * And then, print the detail of each capability registers 3194 * in capability value's order. 3195 */ 3196 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 3197 if (foundtable[i] == false) 3198 continue; 3199 3200 /* 3201 * The type was found. Search capability list again and 3202 * print all capabilities that the capabiliy type is 3203 * the same. 3204 */ 3205 if (pci_conf_find_extcap(regs, capoff, i, &off) == 0) 3206 continue; 3207 rval = regs[o2i(off)]; 3208 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 3209 || (pci_extcaptab[i].printfunc == NULL)) 3210 continue; 3211 3212 pci_extcaptab[i].printfunc(regs, capoff, off); 3213 3214 } 3215 } 3216 3217 /* Print the Secondary Status Register. */ 3218 static void 3219 pci_conf_print_ssr(pcireg_t rval) 3220 { 3221 pcireg_t devsel; 3222 3223 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 3224 onoff("66 MHz capable", rval, __BIT(5)); 3225 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 3226 onoff("Fast back-to-back capable", rval, __BIT(7)); 3227 onoff("Data parity error detected", rval, __BIT(8)); 3228 3229 printf(" DEVSEL timing: "); 3230 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 3231 switch (devsel) { 3232 case 0: 3233 printf("fast"); 3234 break; 3235 case 1: 3236 printf("medium"); 3237 break; 3238 case 2: 3239 printf("slow"); 3240 break; 3241 default: 3242 printf("unknown/reserved"); /* XXX */ 3243 break; 3244 } 3245 printf(" (0x%x)\n", devsel); 3246 3247 onoff("Signalled target abort", rval, __BIT(11)); 3248 onoff("Received target abort", rval, __BIT(12)); 3249 onoff("Received master abort", rval, __BIT(13)); 3250 onoff("Received system error", rval, __BIT(14)); 3251 onoff("Detected parity error", rval, __BIT(15)); 3252 } 3253 3254 static void 3255 pci_conf_print_type0( 3256 #ifdef _KERNEL 3257 pci_chipset_tag_t pc, pcitag_t tag, 3258 #endif 3259 const pcireg_t *regs 3260 #ifdef _KERNEL 3261 , int sizebars 3262 #endif 3263 ) 3264 { 3265 int off, width; 3266 pcireg_t rval; 3267 3268 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 3269 #ifdef _KERNEL 3270 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3271 #else 3272 width = pci_conf_print_bar(regs, off, NULL); 3273 #endif 3274 } 3275 3276 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 3277 3278 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 3279 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 3280 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 3281 3282 /* XXX */ 3283 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 3284 3285 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3286 printf(" Capability list pointer: 0x%02x\n", 3287 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 3288 else 3289 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 3290 3291 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 3292 3293 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3294 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 3295 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 3296 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 3297 switch (PCI_INTERRUPT_PIN(rval)) { 3298 case PCI_INTERRUPT_PIN_NONE: 3299 printf("(none)"); 3300 break; 3301 case PCI_INTERRUPT_PIN_A: 3302 printf("(pin A)"); 3303 break; 3304 case PCI_INTERRUPT_PIN_B: 3305 printf("(pin B)"); 3306 break; 3307 case PCI_INTERRUPT_PIN_C: 3308 printf("(pin C)"); 3309 break; 3310 case PCI_INTERRUPT_PIN_D: 3311 printf("(pin D)"); 3312 break; 3313 default: 3314 printf("(? ? ?)"); 3315 break; 3316 } 3317 printf("\n"); 3318 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 3319 } 3320 3321 static void 3322 pci_conf_print_type1( 3323 #ifdef _KERNEL 3324 pci_chipset_tag_t pc, pcitag_t tag, 3325 #endif 3326 const pcireg_t *regs 3327 #ifdef _KERNEL 3328 , int sizebars 3329 #endif 3330 ) 3331 { 3332 int off, width; 3333 pcireg_t rval; 3334 uint32_t base, limit; 3335 uint32_t base_h, limit_h; 3336 uint64_t pbase, plimit; 3337 int use_upper; 3338 3339 /* 3340 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 3341 * Bridge chip documentation, and may not be correct with 3342 * respect to various standards. (XXX) 3343 */ 3344 3345 for (off = 0x10; off < 0x18; off += width) { 3346 #ifdef _KERNEL 3347 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3348 #else 3349 width = pci_conf_print_bar(regs, off, NULL); 3350 #endif 3351 } 3352 3353 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 3354 printf(" Primary bus number: 0x%02x\n", 3355 PCI_BRIDGE_BUS_PRIMARY(rval)); 3356 printf(" Secondary bus number: 0x%02x\n", 3357 PCI_BRIDGE_BUS_SECONDARY(rval)); 3358 printf(" Subordinate bus number: 0x%02x\n", 3359 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 3360 printf(" Secondary bus latency timer: 0x%02x\n", 3361 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 3362 3363 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 3364 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 3365 3366 /* I/O region */ 3367 printf(" I/O region:\n"); 3368 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 3369 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 3370 if (PCI_BRIDGE_IO_32BITS(rval)) 3371 use_upper = 1; 3372 else 3373 use_upper = 0; 3374 onoff("32bit I/O", rval, use_upper); 3375 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 3376 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 3377 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 3378 limit |= 0x00000fff; 3379 3380 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 3381 base_h = (rval >> 0) & 0xffff; 3382 limit_h = (rval >> 16) & 0xffff; 3383 printf(" base upper 16 bits register: 0x%04x\n", base_h); 3384 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 3385 3386 if (use_upper == 1) { 3387 base |= base_h << 16; 3388 limit |= limit_h << 16; 3389 } 3390 if (base < limit) { 3391 if (use_upper == 1) 3392 printf(" range: 0x%08x-0x%08x\n", base, limit); 3393 else 3394 printf(" range: 0x%04x-0x%04x\n", base, limit); 3395 } else 3396 printf(" range: not set\n"); 3397 3398 /* Non-prefetchable memory region */ 3399 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 3400 printf(" Memory region:\n"); 3401 printf(" base register: 0x%04x\n", 3402 (rval >> 0) & 0xffff); 3403 printf(" limit register: 0x%04x\n", 3404 (rval >> 16) & 0xffff); 3405 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 3406 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 3407 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 3408 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 3409 if (base < limit) 3410 printf(" range: 0x%08x-0x%08x\n", base, limit); 3411 else 3412 printf(" range: not set\n"); 3413 3414 /* Prefetchable memory region */ 3415 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 3416 printf(" Prefetchable memory region:\n"); 3417 printf(" base register: 0x%04x\n", 3418 (rval >> 0) & 0xffff); 3419 printf(" limit register: 0x%04x\n", 3420 (rval >> 16) & 0xffff); 3421 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 3422 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 3423 printf(" base upper 32 bits register: 0x%08x\n", 3424 base_h); 3425 printf(" limit upper 32 bits register: 0x%08x\n", 3426 limit_h); 3427 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 3428 use_upper = 1; 3429 else 3430 use_upper = 0; 3431 onoff("64bit memory address", rval, use_upper); 3432 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 3433 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 3434 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 3435 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 3436 if (use_upper == 1) { 3437 pbase |= (uint64_t)base_h << 32; 3438 plimit |= (uint64_t)limit_h << 32; 3439 } 3440 if (pbase < plimit) { 3441 if (use_upper == 1) 3442 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 3443 "\n", pbase, plimit); 3444 else 3445 printf(" range: 0x%08x-0x%08x\n", 3446 (uint32_t)pbase, (uint32_t)plimit); 3447 } else 3448 printf(" range: not set\n"); 3449 3450 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3451 printf(" Capability list pointer: 0x%02x\n", 3452 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 3453 else 3454 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 3455 3456 /* XXX */ 3457 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 3458 3459 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3460 printf(" Interrupt line: 0x%02x\n", 3461 (rval >> 0) & 0xff); 3462 printf(" Interrupt pin: 0x%02x ", 3463 (rval >> 8) & 0xff); 3464 switch ((rval >> 8) & 0xff) { 3465 case PCI_INTERRUPT_PIN_NONE: 3466 printf("(none)"); 3467 break; 3468 case PCI_INTERRUPT_PIN_A: 3469 printf("(pin A)"); 3470 break; 3471 case PCI_INTERRUPT_PIN_B: 3472 printf("(pin B)"); 3473 break; 3474 case PCI_INTERRUPT_PIN_C: 3475 printf("(pin C)"); 3476 break; 3477 case PCI_INTERRUPT_PIN_D: 3478 printf("(pin D)"); 3479 break; 3480 default: 3481 printf("(? ? ?)"); 3482 break; 3483 } 3484 printf("\n"); 3485 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 3486 & PCI_BRIDGE_CONTROL_MASK; 3487 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 3488 onoff("Parity error response", rval, 0x0001); 3489 onoff("Secondary SERR forwarding", rval, 0x0002); 3490 onoff("ISA enable", rval, 0x0004); 3491 onoff("VGA enable", rval, 0x0008); 3492 onoff("Master abort reporting", rval, 0x0020); 3493 onoff("Secondary bus reset", rval, 0x0040); 3494 onoff("Fast back-to-back capable", rval, 0x0080); 3495 } 3496 3497 static void 3498 pci_conf_print_type2( 3499 #ifdef _KERNEL 3500 pci_chipset_tag_t pc, pcitag_t tag, 3501 #endif 3502 const pcireg_t *regs 3503 #ifdef _KERNEL 3504 , int sizebars 3505 #endif 3506 ) 3507 { 3508 pcireg_t rval; 3509 3510 /* 3511 * XXX these need to be printed in more detail, need to be 3512 * XXX checked against specs/docs, etc. 3513 * 3514 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 3515 * controller chip documentation, and may not be correct with 3516 * respect to various standards. (XXX) 3517 */ 3518 3519 #ifdef _KERNEL 3520 pci_conf_print_bar(pc, tag, regs, 0x10, 3521 "CardBus socket/ExCA registers", sizebars); 3522 #else 3523 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 3524 #endif 3525 3526 /* Capability list pointer and secondary status register */ 3527 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 3528 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3529 printf(" Capability list pointer: 0x%02x\n", 3530 PCI_CAPLIST_PTR(rval)); 3531 else 3532 printf(" Reserved @ 0x14: 0x%04x\n", 3533 (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0))); 3534 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 3535 3536 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 3537 printf(" PCI bus number: 0x%02x\n", 3538 (rval >> 0) & 0xff); 3539 printf(" CardBus bus number: 0x%02x\n", 3540 (rval >> 8) & 0xff); 3541 printf(" Subordinate bus number: 0x%02x\n", 3542 (rval >> 16) & 0xff); 3543 printf(" CardBus latency timer: 0x%02x\n", 3544 (rval >> 24) & 0xff); 3545 3546 /* XXX Print more prettily */ 3547 printf(" CardBus memory region 0:\n"); 3548 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 3549 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 3550 printf(" CardBus memory region 1:\n"); 3551 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 3552 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 3553 printf(" CardBus I/O region 0:\n"); 3554 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 3555 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 3556 printf(" CardBus I/O region 1:\n"); 3557 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 3558 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 3559 3560 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3561 printf(" Interrupt line: 0x%02x\n", 3562 (rval >> 0) & 0xff); 3563 printf(" Interrupt pin: 0x%02x ", 3564 (rval >> 8) & 0xff); 3565 switch ((rval >> 8) & 0xff) { 3566 case PCI_INTERRUPT_PIN_NONE: 3567 printf("(none)"); 3568 break; 3569 case PCI_INTERRUPT_PIN_A: 3570 printf("(pin A)"); 3571 break; 3572 case PCI_INTERRUPT_PIN_B: 3573 printf("(pin B)"); 3574 break; 3575 case PCI_INTERRUPT_PIN_C: 3576 printf("(pin C)"); 3577 break; 3578 case PCI_INTERRUPT_PIN_D: 3579 printf("(pin D)"); 3580 break; 3581 default: 3582 printf("(? ? ?)"); 3583 break; 3584 } 3585 printf("\n"); 3586 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 3587 printf(" Bridge control register: 0x%04x\n", rval); 3588 onoff("Parity error response", rval, __BIT(0)); 3589 onoff("SERR# enable", rval, __BIT(1)); 3590 onoff("ISA enable", rval, __BIT(2)); 3591 onoff("VGA enable", rval, __BIT(3)); 3592 onoff("Master abort mode", rval, __BIT(5)); 3593 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 3594 onoff("Functional interrupts routed by ExCA registers", rval, 3595 __BIT(7)); 3596 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 3597 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 3598 onoff("Write posting enable", rval, __BIT(10)); 3599 3600 rval = regs[o2i(0x40)]; 3601 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 3602 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 3603 3604 #ifdef _KERNEL 3605 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 3606 sizebars); 3607 #else 3608 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 3609 #endif 3610 } 3611 3612 void 3613 pci_conf_print( 3614 #ifdef _KERNEL 3615 pci_chipset_tag_t pc, pcitag_t tag, 3616 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 3617 #else 3618 int pcifd, u_int bus, u_int dev, u_int func 3619 #endif 3620 ) 3621 { 3622 pcireg_t regs[o2i(PCI_EXTCONF_SIZE)]; 3623 int off, capoff, endoff, hdrtype; 3624 const char *type_name; 3625 #ifdef _KERNEL 3626 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, 3627 int); 3628 int sizebars; 3629 #else 3630 void (*type_printfn)(const pcireg_t *); 3631 #endif 3632 3633 printf("PCI configuration registers:\n"); 3634 3635 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 3636 #ifdef _KERNEL 3637 regs[o2i(off)] = pci_conf_read(pc, tag, off); 3638 #else 3639 if (pcibus_conf_read(pcifd, bus, dev, func, off, 3640 ®s[o2i(off)]) == -1) 3641 regs[o2i(off)] = 0; 3642 #endif 3643 } 3644 3645 #ifdef _KERNEL 3646 sizebars = 1; 3647 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 3648 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 3649 sizebars = 0; 3650 #endif 3651 3652 /* common header */ 3653 printf(" Common header:\n"); 3654 pci_conf_print_regs(regs, 0, 16); 3655 3656 printf("\n"); 3657 #ifdef _KERNEL 3658 pci_conf_print_common(pc, tag, regs); 3659 #else 3660 pci_conf_print_common(regs); 3661 #endif 3662 printf("\n"); 3663 3664 /* type-dependent header */ 3665 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 3666 switch (hdrtype) { /* XXX make a table, eventually */ 3667 case 0: 3668 /* Standard device header */ 3669 type_name = "\"normal\" device"; 3670 type_printfn = &pci_conf_print_type0; 3671 capoff = PCI_CAPLISTPTR_REG; 3672 endoff = 64; 3673 break; 3674 case 1: 3675 /* PCI-PCI bridge header */ 3676 type_name = "PCI-PCI bridge"; 3677 type_printfn = &pci_conf_print_type1; 3678 capoff = PCI_CAPLISTPTR_REG; 3679 endoff = 64; 3680 break; 3681 case 2: 3682 /* PCI-CardBus bridge header */ 3683 type_name = "PCI-CardBus bridge"; 3684 type_printfn = &pci_conf_print_type2; 3685 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 3686 endoff = 72; 3687 break; 3688 default: 3689 type_name = NULL; 3690 type_printfn = 0; 3691 capoff = -1; 3692 endoff = 64; 3693 break; 3694 } 3695 printf(" Type %d ", hdrtype); 3696 if (type_name != NULL) 3697 printf("(%s) ", type_name); 3698 printf("header:\n"); 3699 pci_conf_print_regs(regs, 16, endoff); 3700 printf("\n"); 3701 if (type_printfn) { 3702 #ifdef _KERNEL 3703 (*type_printfn)(pc, tag, regs, sizebars); 3704 #else 3705 (*type_printfn)(regs); 3706 #endif 3707 } else 3708 printf(" Don't know how to pretty-print type %d header.\n", 3709 hdrtype); 3710 printf("\n"); 3711 3712 /* capability list, if present */ 3713 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3714 && (capoff > 0)) { 3715 #ifdef _KERNEL 3716 pci_conf_print_caplist(pc, tag, regs, capoff); 3717 #else 3718 pci_conf_print_caplist(regs, capoff); 3719 #endif 3720 printf("\n"); 3721 } 3722 3723 /* device-dependent header */ 3724 printf(" Device-dependent header:\n"); 3725 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 3726 printf("\n"); 3727 #ifdef _KERNEL 3728 if (printfn) 3729 (*printfn)(pc, tag, regs); 3730 else 3731 printf(" Don't know how to pretty-print device-dependent header.\n"); 3732 printf("\n"); 3733 #endif /* _KERNEL */ 3734 3735 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 3736 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 3737 return; 3738 3739 #ifdef _KERNEL 3740 pci_conf_print_extcaplist(pc, tag, regs, capoff); 3741 #else 3742 pci_conf_print_extcaplist(regs, capoff); 3743 #endif 3744 printf("\n"); 3745 3746 /* Extended Configuration Space, if present */ 3747 printf(" Extended Configuration Space:\n"); 3748 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 3749 } 3750
Indexes created Thu Sep 25 16:09:42 GMT 2025