pci_subr.c revision 1.145
1 /* $NetBSD: pci_subr.c,v 1.145 2015/11/17 18:26:50 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.145 2015/11/17 18:26:50 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdbool.h> 58 #include <stdio.h> 59 #include <stdlib.h> 60 #include <string.h> 61 #endif 62 63 #include <dev/pci/pcireg.h> 64 #ifdef _KERNEL 65 #include <dev/pci/pcivar.h> 66 #else 67 #include <dev/pci/pci_verbose.h> 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcidevs_data.h> 70 #endif 71 72 /* 73 * Descriptions of known PCI classes and subclasses. 74 * 75 * Subclasses are described in the same way as classes, but have a 76 * NULL subclass pointer. 77 */ 78 struct pci_class { 79 const char *name; 80 u_int val; /* as wide as pci_{,sub}class_t */ 81 const struct pci_class *subclasses; 82 }; 83 84 /* 85 * Class 0x00. 86 * Before rev. 2.0. 87 */ 88 static const struct pci_class pci_subclass_prehistoric[] = { 89 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 90 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 91 { NULL, 0, NULL, }, 92 }; 93 94 /* 95 * Class 0x01. 96 * Mass storage controller 97 */ 98 99 /* ATA programming interface */ 100 static const struct pci_class pci_interface_ata[] = { 101 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 102 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 103 { NULL, 0, NULL, }, 104 }; 105 106 /* SATA programming interface */ 107 static const struct pci_class pci_interface_sata[] = { 108 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 109 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 110 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 111 { NULL, 0, NULL, }, 112 }; 113 114 /* Flash programming interface */ 115 static const struct pci_class pci_interface_nvm[] = { 116 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 117 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 118 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 119 { NULL, 0, NULL, }, 120 }; 121 122 /* Subclasses */ 123 static const struct pci_class pci_subclass_mass_storage[] = { 124 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 125 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 126 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 127 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 128 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 129 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 130 pci_interface_ata, }, 131 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 132 pci_interface_sata, }, 133 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 134 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 135 pci_interface_nvm, }, 136 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 137 { NULL, 0, NULL, }, 138 }; 139 140 /* 141 * Class 0x02. 142 * Network controller. 143 */ 144 static const struct pci_class pci_subclass_network[] = { 145 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 146 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 147 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 148 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 149 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 150 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 151 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 152 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 153 { NULL, 0, NULL, }, 154 }; 155 156 /* 157 * Class 0x03. 158 * Display controller. 159 */ 160 161 /* VGA programming interface */ 162 static const struct pci_class pci_interface_vga[] = { 163 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 164 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 165 { NULL, 0, NULL, }, 166 }; 167 /* Subclasses */ 168 static const struct pci_class pci_subclass_display[] = { 169 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 170 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 171 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 172 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 173 { NULL, 0, NULL, }, 174 }; 175 176 /* 177 * Class 0x04. 178 * Multimedia device. 179 */ 180 static const struct pci_class pci_subclass_multimedia[] = { 181 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 182 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 183 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 184 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 185 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 186 { NULL, 0, NULL, }, 187 }; 188 189 /* 190 * Class 0x05. 191 * Memory controller. 192 */ 193 static const struct pci_class pci_subclass_memory[] = { 194 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 195 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 196 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 197 { NULL, 0, NULL, }, 198 }; 199 200 /* 201 * Class 0x06. 202 * Bridge device. 203 */ 204 205 /* PCI bridge programming interface */ 206 static const struct pci_class pci_interface_pcibridge[] = { 207 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 208 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 209 { NULL, 0, NULL, }, 210 }; 211 212 /* Semi-transparent PCI-to-PCI bridge programming interface */ 213 static const struct pci_class pci_interface_stpci[] = { 214 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 215 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 216 { NULL, 0, NULL, }, 217 }; 218 219 /* Advanced Switching programming interface */ 220 static const struct pci_class pci_interface_advsw[] = { 221 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 222 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 223 { NULL, 0, NULL, }, 224 }; 225 226 /* Subclasses */ 227 static const struct pci_class pci_subclass_bridge[] = { 228 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 229 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 230 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 231 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 232 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 233 pci_interface_pcibridge, }, 234 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 235 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 236 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 237 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 238 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 239 pci_interface_stpci, }, 240 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 241 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 242 pci_interface_advsw, }, 243 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 244 { NULL, 0, NULL, }, 245 }; 246 247 /* 248 * Class 0x07. 249 * Simple communications controller. 250 */ 251 252 /* Serial controller programming interface */ 253 static const struct pci_class pci_interface_serial[] = { 254 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 255 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 256 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 257 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 258 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 259 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 260 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 261 { NULL, 0, NULL, }, 262 }; 263 264 /* Parallel controller programming interface */ 265 static const struct pci_class pci_interface_parallel[] = { 266 { "", PCI_INTERFACE_PARALLEL, NULL,}, 267 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 268 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 269 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 270 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 271 { NULL, 0, NULL,}, 272 }; 273 274 /* Modem programming interface */ 275 static const struct pci_class pci_interface_modem[] = { 276 { "", PCI_INTERFACE_MODEM, NULL,}, 277 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 278 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 279 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 280 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 281 { NULL, 0, NULL,}, 282 }; 283 284 /* Subclasses */ 285 static const struct pci_class pci_subclass_communications[] = { 286 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 287 pci_interface_serial, }, 288 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 289 pci_interface_parallel, }, 290 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 291 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 292 pci_interface_modem, }, 293 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 294 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 295 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 296 { NULL, 0, NULL,}, 297 }; 298 299 /* 300 * Class 0x08. 301 * Base system peripheral. 302 */ 303 304 /* PIC programming interface */ 305 static const struct pci_class pci_interface_pic[] = { 306 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 307 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 308 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 309 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 310 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 311 { NULL, 0, NULL, }, 312 }; 313 314 /* DMA programming interface */ 315 static const struct pci_class pci_interface_dma[] = { 316 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 317 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 318 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 319 { NULL, 0, NULL, }, 320 }; 321 322 /* Timer programming interface */ 323 static const struct pci_class pci_interface_tmr[] = { 324 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 325 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 326 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 327 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 328 { NULL, 0, NULL, }, 329 }; 330 331 /* RTC programming interface */ 332 static const struct pci_class pci_interface_rtc[] = { 333 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 334 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 335 { NULL, 0, NULL, }, 336 }; 337 338 /* Subclasses */ 339 static const struct pci_class pci_subclass_system[] = { 340 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 341 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 342 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 343 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 344 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 345 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 346 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 347 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 348 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 349 { NULL, 0, NULL, }, 350 }; 351 352 /* 353 * Class 0x09. 354 * Input device. 355 */ 356 357 /* Gameport programming interface */ 358 static const struct pci_class pci_interface_game[] = { 359 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 360 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 361 { NULL, 0, NULL, }, 362 }; 363 364 /* Subclasses */ 365 static const struct pci_class pci_subclass_input[] = { 366 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 367 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 368 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 369 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 370 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 371 pci_interface_game, }, 372 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 373 { NULL, 0, NULL, }, 374 }; 375 376 /* 377 * Class 0x0a. 378 * Docking station. 379 */ 380 static const struct pci_class pci_subclass_dock[] = { 381 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 382 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 383 { NULL, 0, NULL, }, 384 }; 385 386 /* 387 * Class 0x0b. 388 * Processor. 389 */ 390 static const struct pci_class pci_subclass_processor[] = { 391 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 392 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 393 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 394 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 395 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 396 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 397 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 398 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 399 { NULL, 0, NULL, }, 400 }; 401 402 /* 403 * Class 0x0c. 404 * Serial bus controller. 405 */ 406 407 /* IEEE1394 programming interface */ 408 static const struct pci_class pci_interface_ieee1394[] = { 409 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 410 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 411 { NULL, 0, NULL,}, 412 }; 413 414 /* USB programming interface */ 415 static const struct pci_class pci_interface_usb[] = { 416 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 417 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 418 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 419 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 420 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 421 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 422 { NULL, 0, NULL, }, 423 }; 424 425 /* IPMI programming interface */ 426 static const struct pci_class pci_interface_ipmi[] = { 427 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 428 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 429 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 430 { NULL, 0, NULL,}, 431 }; 432 433 /* Subclasses */ 434 static const struct pci_class pci_subclass_serialbus[] = { 435 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 436 pci_interface_ieee1394, }, 437 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 438 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 439 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 440 pci_interface_usb, }, 441 /* XXX Fiber Channel/_FIBRECHANNEL */ 442 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 443 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 444 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 445 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 446 pci_interface_ipmi, }, 447 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 448 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 449 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 450 { NULL, 0, NULL, }, 451 }; 452 453 /* 454 * Class 0x0d. 455 * Wireless Controller. 456 */ 457 static const struct pci_class pci_subclass_wireless[] = { 458 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 459 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 460 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 461 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 462 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 463 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 464 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 465 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 466 { NULL, 0, NULL, }, 467 }; 468 469 /* 470 * Class 0x0e. 471 * Intelligent IO controller. 472 */ 473 474 /* Intelligent IO programming interface */ 475 static const struct pci_class pci_interface_i2o[] = { 476 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 477 { NULL, 0, NULL,}, 478 }; 479 480 /* Subclasses */ 481 static const struct pci_class pci_subclass_i2o[] = { 482 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 483 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 484 { NULL, 0, NULL, }, 485 }; 486 487 /* 488 * Class 0x0f. 489 * Satellite communication controller. 490 */ 491 static const struct pci_class pci_subclass_satcom[] = { 492 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 493 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 494 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 495 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 496 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 497 { NULL, 0, NULL, }, 498 }; 499 500 /* 501 * Class 0x10. 502 * Encryption/Decryption controller. 503 */ 504 static const struct pci_class pci_subclass_crypto[] = { 505 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 506 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 507 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 508 { NULL, 0, NULL, }, 509 }; 510 511 /* 512 * Class 0x11. 513 * Data aquuisition and signal processing controller. 514 */ 515 static const struct pci_class pci_subclass_dasp[] = { 516 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 517 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 518 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 519 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 520 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 521 { NULL, 0, NULL, }, 522 }; 523 524 /* List of classes */ 525 static const struct pci_class pci_class[] = { 526 { "prehistoric", PCI_CLASS_PREHISTORIC, 527 pci_subclass_prehistoric, }, 528 { "mass storage", PCI_CLASS_MASS_STORAGE, 529 pci_subclass_mass_storage, }, 530 { "network", PCI_CLASS_NETWORK, 531 pci_subclass_network, }, 532 { "display", PCI_CLASS_DISPLAY, 533 pci_subclass_display, }, 534 { "multimedia", PCI_CLASS_MULTIMEDIA, 535 pci_subclass_multimedia, }, 536 { "memory", PCI_CLASS_MEMORY, 537 pci_subclass_memory, }, 538 { "bridge", PCI_CLASS_BRIDGE, 539 pci_subclass_bridge, }, 540 { "communications", PCI_CLASS_COMMUNICATIONS, 541 pci_subclass_communications, }, 542 { "system", PCI_CLASS_SYSTEM, 543 pci_subclass_system, }, 544 { "input", PCI_CLASS_INPUT, 545 pci_subclass_input, }, 546 { "dock", PCI_CLASS_DOCK, 547 pci_subclass_dock, }, 548 { "processor", PCI_CLASS_PROCESSOR, 549 pci_subclass_processor, }, 550 { "serial bus", PCI_CLASS_SERIALBUS, 551 pci_subclass_serialbus, }, 552 { "wireless", PCI_CLASS_WIRELESS, 553 pci_subclass_wireless, }, 554 { "I2O", PCI_CLASS_I2O, 555 pci_subclass_i2o, }, 556 { "satellite comm", PCI_CLASS_SATCOM, 557 pci_subclass_satcom, }, 558 { "crypto", PCI_CLASS_CRYPTO, 559 pci_subclass_crypto, }, 560 { "DASP", PCI_CLASS_DASP, 561 pci_subclass_dasp, }, 562 { "undefined", PCI_CLASS_UNDEFINED, 563 NULL, }, 564 { NULL, 0, 565 NULL, }, 566 }; 567 568 DEV_VERBOSE_DEFINE(pci); 569 570 void 571 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 572 size_t l) 573 { 574 pci_class_t pciclass; 575 pci_subclass_t subclass; 576 pci_interface_t interface; 577 pci_revision_t revision; 578 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 579 const struct pci_class *classp, *subclassp, *interfacep; 580 char *ep; 581 582 ep = cp + l; 583 584 pciclass = PCI_CLASS(class_reg); 585 subclass = PCI_SUBCLASS(class_reg); 586 interface = PCI_INTERFACE(class_reg); 587 revision = PCI_REVISION(class_reg); 588 589 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 590 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 591 PCI_PRODUCT(id_reg)); 592 593 classp = pci_class; 594 while (classp->name != NULL) { 595 if (pciclass == classp->val) 596 break; 597 classp++; 598 } 599 600 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 601 while (subclassp && subclassp->name != NULL) { 602 if (subclass == subclassp->val) 603 break; 604 subclassp++; 605 } 606 607 interfacep = (subclassp && subclassp->name != NULL) ? 608 subclassp->subclasses : NULL; 609 while (interfacep && interfacep->name != NULL) { 610 if (interface == interfacep->val) 611 break; 612 interfacep++; 613 } 614 615 cp += snprintf(cp, ep - cp, "%s %s", vendor, product); 616 if (showclass) { 617 cp += snprintf(cp, ep - cp, " ("); 618 if (classp->name == NULL) 619 cp += snprintf(cp, ep - cp, 620 "class 0x%02x, subclass 0x%02x", pciclass, subclass); 621 else { 622 if (subclassp == NULL || subclassp->name == NULL) 623 cp += snprintf(cp, ep - cp, 624 "%s, subclass 0x%02x", 625 classp->name, subclass); 626 else 627 cp += snprintf(cp, ep - cp, "%s %s", 628 subclassp->name, classp->name); 629 } 630 if ((interfacep == NULL) || (interfacep->name == NULL)) { 631 if (interface != 0) 632 cp += snprintf(cp, ep - cp, 633 ", interface 0x%02x", interface); 634 } else if (strncmp(interfacep->name, "", 1) != 0) 635 cp += snprintf(cp, ep - cp, ", %s", 636 interfacep->name); 637 if (revision != 0) 638 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 639 revision); 640 cp += snprintf(cp, ep - cp, ")"); 641 } 642 } 643 644 #ifdef _KERNEL 645 void 646 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 647 const char *known, int addrev) 648 { 649 char devinfo[256]; 650 651 if (known) { 652 aprint_normal(": %s", known); 653 if (addrev) 654 aprint_normal(" (rev. 0x%02x)", 655 PCI_REVISION(pa->pa_class)); 656 aprint_normal("\n"); 657 } else { 658 pci_devinfo(pa->pa_id, pa->pa_class, 0, 659 devinfo, sizeof(devinfo)); 660 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 661 PCI_REVISION(pa->pa_class)); 662 } 663 if (naive) 664 aprint_naive(": %s\n", naive); 665 else 666 aprint_naive("\n"); 667 } 668 #endif 669 670 /* 671 * Print out most of the PCI configuration registers. Typically used 672 * in a device attach routine like this: 673 * 674 * #ifdef MYDEV_DEBUG 675 * printf("%s: ", device_xname(sc->sc_dev)); 676 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 677 * #endif 678 */ 679 680 #define i2o(i) ((i) * 4) 681 #define o2i(o) ((o) / 4) 682 #define onoff2(str, rval, bit, onstr, offstr) \ 683 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 684 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 685 686 static void 687 pci_conf_print_common( 688 #ifdef _KERNEL 689 pci_chipset_tag_t pc, pcitag_t tag, 690 #endif 691 const pcireg_t *regs) 692 { 693 const char *name; 694 const struct pci_class *classp, *subclassp; 695 char vendor[PCI_VENDORSTR_LEN]; 696 char product[PCI_PRODUCTSTR_LEN]; 697 pcireg_t rval; 698 unsigned int num; 699 700 rval = regs[o2i(PCI_ID_REG)]; 701 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 702 if (name) 703 printf(" Vendor Name: %s (0x%04x)\n", name, 704 PCI_VENDOR(rval)); 705 else 706 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 707 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 708 PCI_PRODUCT(rval)); 709 if (name) 710 printf(" Device Name: %s (0x%04x)\n", name, 711 PCI_PRODUCT(rval)); 712 else 713 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 714 715 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 716 717 printf(" Command register: 0x%04x\n", rval & 0xffff); 718 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 719 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 720 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 721 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 722 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 723 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 724 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 725 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 726 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 727 onoff("Fast back-to-back transactions", rval, 728 PCI_COMMAND_BACKTOBACK_ENABLE); 729 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 730 731 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 732 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 733 "inactive"); 734 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 735 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 736 onoff("User Definable Features (UDF) support", rval, 737 PCI_STATUS_UDF_SUPPORT); 738 onoff("Fast back-to-back capable", rval, 739 PCI_STATUS_BACKTOBACK_SUPPORT); 740 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 741 742 printf(" DEVSEL timing: "); 743 switch (rval & PCI_STATUS_DEVSEL_MASK) { 744 case PCI_STATUS_DEVSEL_FAST: 745 printf("fast"); 746 break; 747 case PCI_STATUS_DEVSEL_MEDIUM: 748 printf("medium"); 749 break; 750 case PCI_STATUS_DEVSEL_SLOW: 751 printf("slow"); 752 break; 753 default: 754 printf("unknown/reserved"); /* XXX */ 755 break; 756 } 757 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 758 759 onoff("Slave signaled Target Abort", rval, 760 PCI_STATUS_TARGET_TARGET_ABORT); 761 onoff("Master received Target Abort", rval, 762 PCI_STATUS_MASTER_TARGET_ABORT); 763 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 764 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 765 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 766 767 rval = regs[o2i(PCI_CLASS_REG)]; 768 for (classp = pci_class; classp->name != NULL; classp++) { 769 if (PCI_CLASS(rval) == classp->val) 770 break; 771 } 772 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 773 while (subclassp && subclassp->name != NULL) { 774 if (PCI_SUBCLASS(rval) == subclassp->val) 775 break; 776 subclassp++; 777 } 778 if (classp->name != NULL) { 779 printf(" Class Name: %s (0x%02x)\n", classp->name, 780 PCI_CLASS(rval)); 781 if (subclassp != NULL && subclassp->name != NULL) 782 printf(" Subclass Name: %s (0x%02x)\n", 783 subclassp->name, PCI_SUBCLASS(rval)); 784 else 785 printf(" Subclass ID: 0x%02x\n", 786 PCI_SUBCLASS(rval)); 787 } else { 788 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 789 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 790 } 791 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 792 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 793 794 rval = regs[o2i(PCI_BHLC_REG)]; 795 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 796 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 797 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 798 PCI_HDRTYPE(rval)); 799 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 800 num = PCI_CACHELINE(rval); 801 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 802 } 803 804 static int 805 pci_conf_print_bar( 806 #ifdef _KERNEL 807 pci_chipset_tag_t pc, pcitag_t tag, 808 #endif 809 const pcireg_t *regs, int reg, const char *name 810 #ifdef _KERNEL 811 , int sizebar 812 #endif 813 ) 814 { 815 int width; 816 pcireg_t rval, rval64h; 817 #ifdef _KERNEL 818 int s; 819 pcireg_t mask, mask64h; 820 #endif 821 822 width = 4; 823 824 /* 825 * Section 6.2.5.1, `Address Maps', tells us that: 826 * 827 * 1) The builtin software should have already mapped the 828 * device in a reasonable way. 829 * 830 * 2) A device which wants 2^n bytes of memory will hardwire 831 * the bottom n bits of the address to 0. As recommended, 832 * we write all 1s and see what we get back. 833 */ 834 835 rval = regs[o2i(reg)]; 836 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 837 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 838 rval64h = regs[o2i(reg + 4)]; 839 width = 8; 840 } else 841 rval64h = 0; 842 843 #ifdef _KERNEL 844 /* XXX don't size unknown memory type? */ 845 if (rval != 0 && sizebar) { 846 /* 847 * The following sequence seems to make some devices 848 * (e.g. host bus bridges, which don't normally 849 * have their space mapped) very unhappy, to 850 * the point of crashing the system. 851 * 852 * Therefore, if the mapping register is zero to 853 * start out with, don't bother trying. 854 */ 855 s = splhigh(); 856 pci_conf_write(pc, tag, reg, 0xffffffff); 857 mask = pci_conf_read(pc, tag, reg); 858 pci_conf_write(pc, tag, reg, rval); 859 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 860 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 861 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 862 mask64h = pci_conf_read(pc, tag, reg + 4); 863 pci_conf_write(pc, tag, reg + 4, rval64h); 864 } else 865 mask64h = 0; 866 splx(s); 867 } else 868 mask = mask64h = 0; 869 #endif /* _KERNEL */ 870 871 printf(" Base address register at 0x%02x", reg); 872 if (name) 873 printf(" (%s)", name); 874 printf("\n "); 875 if (rval == 0) { 876 printf("not implemented(?)\n"); 877 return width; 878 } 879 printf("type: "); 880 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 881 const char *type, *prefetch; 882 883 switch (PCI_MAPREG_MEM_TYPE(rval)) { 884 case PCI_MAPREG_MEM_TYPE_32BIT: 885 type = "32-bit"; 886 break; 887 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 888 type = "32-bit-1M"; 889 break; 890 case PCI_MAPREG_MEM_TYPE_64BIT: 891 type = "64-bit"; 892 break; 893 default: 894 type = "unknown (XXX)"; 895 break; 896 } 897 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 898 prefetch = ""; 899 else 900 prefetch = "non"; 901 printf("%s %sprefetchable memory\n", type, prefetch); 902 switch (PCI_MAPREG_MEM_TYPE(rval)) { 903 case PCI_MAPREG_MEM_TYPE_64BIT: 904 printf(" base: 0x%016llx, ", 905 PCI_MAPREG_MEM64_ADDR( 906 ((((long long) rval64h) << 32) | rval))); 907 #ifdef _KERNEL 908 if (sizebar) 909 printf("size: 0x%016llx", 910 PCI_MAPREG_MEM64_SIZE( 911 ((((long long) mask64h) << 32) | mask))); 912 else 913 #endif /* _KERNEL */ 914 printf("not sized"); 915 printf("\n"); 916 break; 917 case PCI_MAPREG_MEM_TYPE_32BIT: 918 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 919 default: 920 printf(" base: 0x%08x, ", 921 PCI_MAPREG_MEM_ADDR(rval)); 922 #ifdef _KERNEL 923 if (sizebar) 924 printf("size: 0x%08x", 925 PCI_MAPREG_MEM_SIZE(mask)); 926 else 927 #endif /* _KERNEL */ 928 printf("not sized"); 929 printf("\n"); 930 break; 931 } 932 } else { 933 #ifdef _KERNEL 934 if (sizebar) 935 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 936 #endif /* _KERNEL */ 937 printf("i/o\n"); 938 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 939 #ifdef _KERNEL 940 if (sizebar) 941 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 942 else 943 #endif /* _KERNEL */ 944 printf("not sized"); 945 printf("\n"); 946 } 947 948 return width; 949 } 950 951 static void 952 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 953 { 954 int off, needaddr, neednl; 955 956 needaddr = 1; 957 neednl = 0; 958 for (off = first; off < pastlast; off += 4) { 959 if ((off % 16) == 0 || needaddr) { 960 printf(" 0x%02x:", off); 961 needaddr = 0; 962 } 963 printf(" 0x%08x", regs[o2i(off)]); 964 neednl = 1; 965 if ((off % 16) == 12) { 966 printf("\n"); 967 neednl = 0; 968 } 969 } 970 if (neednl) 971 printf("\n"); 972 } 973 974 static void 975 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 976 { 977 pcireg_t rval; 978 979 printf("\n AGP Capabilities Register\n"); 980 981 rval = regs[o2i(capoff)]; 982 printf(" Revision: %d.%d\n", 983 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 984 985 /* XXX need more */ 986 } 987 988 static const char * 989 pci_conf_print_pcipm_cap_aux(uint16_t caps) 990 { 991 992 switch ((caps >> 6) & 7) { 993 case 0: return "self-powered"; 994 case 1: return "55 mA"; 995 case 2: return "100 mA"; 996 case 3: return "160 mA"; 997 case 4: return "220 mA"; 998 case 5: return "270 mA"; 999 case 6: return "320 mA"; 1000 case 7: 1001 default: return "375 mA"; 1002 } 1003 } 1004 1005 static const char * 1006 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1007 { 1008 static const char unk[] = "unknown"; 1009 static const char *pmrev[8] = { 1010 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1011 }; 1012 if (val > 7) 1013 return unk; 1014 return pmrev[val]; 1015 } 1016 1017 static void 1018 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1019 { 1020 uint16_t caps, pmcsr; 1021 pcireg_t reg; 1022 1023 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1024 reg = regs[o2i(capoff + PCI_PMCSR)]; 1025 pmcsr = reg & 0xffff; 1026 1027 printf("\n PCI Power Management Capabilities Register\n"); 1028 1029 printf(" Capabilities register: 0x%04x\n", caps); 1030 printf(" Version: %s\n", 1031 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1032 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1033 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1034 printf(" 3.3V auxiliary current: %s\n", 1035 pci_conf_print_pcipm_cap_aux(caps)); 1036 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1037 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1038 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1039 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1040 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1041 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1042 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1043 1044 printf(" Control/status register: 0x%04x\n", pmcsr); 1045 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1046 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1047 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1048 printf(" PME# assertion: %sabled\n", 1049 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1050 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1051 printf(" Bridge Support Extensions register: 0x%02x\n", 1052 (reg >> 16) & 0xff); 1053 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1054 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1055 printf(" Data register: 0x%02x\n", (reg >> 24) & 0xff); 1056 1057 } 1058 1059 /* XXX pci_conf_print_vpd_cap */ 1060 /* XXX pci_conf_print_slotid_cap */ 1061 1062 static void 1063 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1064 { 1065 uint32_t ctl, mmc, mme; 1066 1067 regs += o2i(capoff); 1068 ctl = *regs++; 1069 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1070 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1071 1072 printf("\n PCI Message Signaled Interrupt\n"); 1073 1074 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1075 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1076 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1077 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1078 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1079 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1080 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1081 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1082 printf(" Message Address %sregister: 0x%08x\n", 1083 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1084 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1085 printf(" Message Address %sregister: 0x%08x\n", 1086 "(upper) ", *regs++); 1087 } 1088 printf(" Message Data register: 0x%08x\n", *regs++); 1089 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1090 printf(" Vector Mask register: 0x%08x\n", *regs++); 1091 printf(" Vector Pending register: 0x%08x\n", *regs++); 1092 } 1093 } 1094 1095 /* XXX pci_conf_print_cpci_hostwap_cap */ 1096 1097 /* 1098 * For both command register and status register. 1099 * The argument "idx" is index number (0 to 7). 1100 */ 1101 static int 1102 pcix_split_trans(unsigned int idx) 1103 { 1104 static int table[8] = { 1105 1, 2, 3, 4, 8, 12, 16, 32 1106 }; 1107 1108 if (idx >= __arraycount(table)) 1109 return -1; 1110 return table[idx]; 1111 } 1112 1113 static void 1114 pci_conf_print_pcix_cap_2ndbusmode(int num) 1115 { 1116 const char *maxfreq, *maxperiod; 1117 1118 printf(" Mode: "); 1119 if (num <= 0x07) 1120 printf("PCI-X Mode 1\n"); 1121 else if (num <= 0x0b) 1122 printf("PCI-X 266 (Mode 2)\n"); 1123 else 1124 printf("PCI-X 533 (Mode 2)\n"); 1125 1126 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1127 switch (num & 0x03) { 1128 default: 1129 case 0: 1130 maxfreq = "N/A"; 1131 maxperiod = "N/A"; 1132 break; 1133 case 1: 1134 maxfreq = "66MHz"; 1135 maxperiod = "15ns"; 1136 break; 1137 case 2: 1138 maxfreq = "100MHz"; 1139 maxperiod = "10ns"; 1140 break; 1141 case 3: 1142 maxfreq = "133MHz"; 1143 maxperiod = "7.5ns"; 1144 break; 1145 } 1146 printf(" Max Clock Freq: %s\n", maxfreq); 1147 printf(" Min Clock Period: %s\n", maxperiod); 1148 } 1149 1150 static void 1151 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1152 { 1153 pcireg_t reg; 1154 int isbridge; 1155 int i; 1156 1157 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1158 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1159 printf("\n PCI-X %s Capabilities Register\n", 1160 isbridge ? "Bridge" : "Non-bridge"); 1161 1162 reg = regs[o2i(capoff)]; 1163 if (isbridge != 0) { 1164 printf(" Secondary status register: 0x%04x\n", 1165 (reg & 0xffff0000) >> 16); 1166 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1167 onoff("133MHz capable", reg, PCIX_STATUS_133); 1168 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1169 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1170 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1171 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1172 pci_conf_print_pcix_cap_2ndbusmode( 1173 __SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1174 printf(" Version: 0x%x\n", 1175 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1176 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1177 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1178 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1179 } else { 1180 printf(" Command register: 0x%04x\n", 1181 (reg & 0xffff0000) >> 16); 1182 onoff("Data Parity Error Recovery", reg, 1183 PCIX_CMD_PERR_RECOVER); 1184 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1185 printf(" Maximum Burst Read Count: %u\n", 1186 PCIX_CMD_BYTECNT(reg)); 1187 printf(" Maximum Split Transactions: %d\n", 1188 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1189 >> PCIX_CMD_SPLTRANS_SHIFT)); 1190 } 1191 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1192 printf(" %sStatus register: 0x%08x\n", 1193 isbridge ? "Bridge " : "", reg); 1194 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1195 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1196 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1197 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1198 onoff("133MHz capable", reg, PCIX_STATUS_133); 1199 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1200 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1201 if (isbridge != 0) { 1202 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1203 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1204 } else { 1205 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1206 "bridge device", "simple device"); 1207 printf(" Designed max memory read byte count: %d\n", 1208 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1209 >> PCIX_STATUS_MAXB_SHIFT)); 1210 printf(" Designed max outstanding split transaction: %d\n", 1211 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1212 >> PCIX_STATUS_MAXST_SHIFT)); 1213 printf(" MAX cumulative Read Size: %u\n", 1214 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1215 onoff("Received split completion error", reg, 1216 PCIX_STATUS_SCERR); 1217 } 1218 onoff("266MHz capable", reg, PCIX_STATUS_266); 1219 onoff("533MHz capable", reg, PCIX_STATUS_533); 1220 1221 if (isbridge == 0) 1222 return; 1223 1224 /* Only for bridge */ 1225 for (i = 0; i < 2; i++) { 1226 reg = regs[o2i(capoff+PCIX_BRIDGE_UP_STCR + (4 * i))]; 1227 printf(" %s split transaction control register: 0x%08x\n", 1228 (i == 0) ? "Upstream" : "Downstream", reg); 1229 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1230 printf(" Commitment Limit: %d\n", 1231 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1232 } 1233 } 1234 1235 /* pci_conf_print_ht_slave_cap */ 1236 /* pci_conf_print_ht_host_cap */ 1237 /* pci_conf_print_ht_switch_cap */ 1238 /* pci_conf_print_ht_intr_cap */ 1239 /* pci_conf_print_ht_revid_cap */ 1240 /* pci_conf_print_ht_unitid_cap */ 1241 /* pci_conf_print_ht_extcnf_cap */ 1242 /* pci_conf_print_ht_addrmap_cap */ 1243 /* pci_conf_print_ht_msimap_cap */ 1244 1245 static void 1246 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1247 { 1248 pcireg_t val; 1249 uint32_t lo, hi; 1250 1251 /* 1252 * Print the rest of the command register bits. Others are 1253 * printed in pci_conf_print_ht_cap(). 1254 */ 1255 val = regs[o2i(capoff + PCI_HT_CMD)]; 1256 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1257 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1258 1259 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1260 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1261 printf(" Address Low register: 0x%08x\n", lo); 1262 printf(" Address high register: 0x%08x\n", hi); 1263 printf(" Address: 0x%016" PRIx64 "\n", 1264 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1265 } 1266 1267 /* pci_conf_print_ht_droute_cap */ 1268 /* pci_conf_print_ht_vcset_cap */ 1269 /* pci_conf_print_ht_retry_cap */ 1270 /* pci_conf_print_ht_x86enc_cap */ 1271 /* pci_conf_print_ht_gen3_cap */ 1272 /* pci_conf_print_ht_fle_cap */ 1273 /* pci_conf_print_ht_pm_cap */ 1274 /* pci_conf_print_ht_hnc_cap */ 1275 1276 static const struct ht_types { 1277 pcireg_t cap; 1278 const char *name; 1279 void (*printfunc)(const pcireg_t *, int); 1280 } ht_captab[] = { 1281 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1282 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1283 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1284 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1285 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1286 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1287 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1288 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1289 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1290 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1291 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1292 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1293 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1294 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1295 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1296 {PCI_HT_CAP_PM, "Power Management", NULL }, 1297 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1298 }; 1299 1300 static void 1301 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1302 { 1303 pcireg_t val, foundcap; 1304 unsigned int off; 1305 1306 val = regs[o2i(capoff + PCI_HT_CMD)]; 1307 1308 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1309 1310 printf(" Command register: 0x%04x\n", val >> 16); 1311 foundcap = PCI_HT_CAP(val); 1312 for (off = 0; off < __arraycount(ht_captab); off++) { 1313 if (ht_captab[off].cap == foundcap) 1314 break; 1315 } 1316 printf(" Capability Type: 0x%02x ", foundcap); 1317 if (off >= __arraycount(ht_captab)) { 1318 printf("(unknown)\n"); 1319 return; 1320 } 1321 printf("(%s)\n", ht_captab[off].name); 1322 if (ht_captab[off].printfunc != NULL) 1323 ht_captab[off].printfunc(regs, capoff); 1324 } 1325 1326 static void 1327 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1328 { 1329 uint16_t caps; 1330 1331 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1332 1333 printf("\n PCI Vendor Specific Capabilities Register\n"); 1334 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1335 } 1336 1337 static void 1338 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1339 { 1340 pcireg_t val; 1341 1342 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1343 1344 printf("\n Debugport Capability Register\n"); 1345 printf(" Debug base Register: 0x%04x\n", 1346 val >> PCI_DEBUG_BASER_SHIFT); 1347 printf(" port offset: 0x%04x\n", 1348 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1349 printf(" BAR number: %u\n", 1350 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1351 } 1352 1353 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1354 /* XXX pci_conf_print_hotplug_cap */ 1355 1356 static void 1357 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1358 { 1359 pcireg_t reg; 1360 1361 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1362 1363 printf("\n Subsystem ID Capability Register\n"); 1364 printf(" Subsystem ID : 0x%08x\n", reg); 1365 } 1366 1367 /* XXX pci_conf_print_agp8_cap */ 1368 /* XXX pci_conf_print_secure_cap */ 1369 1370 static void 1371 pci_print_pcie_L0s_latency(uint32_t val) 1372 { 1373 1374 switch (val) { 1375 case 0x0: 1376 printf("Less than 64ns\n"); 1377 break; 1378 case 0x1: 1379 case 0x2: 1380 case 0x3: 1381 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1382 break; 1383 case 0x4: 1384 printf("512ns to less than 1us\n"); 1385 break; 1386 case 0x5: 1387 printf("1us to less than 2us\n"); 1388 break; 1389 case 0x6: 1390 printf("2us - 4us\n"); 1391 break; 1392 case 0x7: 1393 printf("More than 4us\n"); 1394 break; 1395 } 1396 } 1397 1398 static void 1399 pci_print_pcie_L1_latency(uint32_t val) 1400 { 1401 1402 switch (val) { 1403 case 0x0: 1404 printf("Less than 1us\n"); 1405 break; 1406 case 0x6: 1407 printf("32us - 64us\n"); 1408 break; 1409 case 0x7: 1410 printf("More than 64us\n"); 1411 break; 1412 default: 1413 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1414 break; 1415 } 1416 } 1417 1418 static void 1419 pci_print_pcie_compl_timeout(uint32_t val) 1420 { 1421 1422 switch (val) { 1423 case 0x0: 1424 printf("50us to 50ms\n"); 1425 break; 1426 case 0x5: 1427 printf("16ms to 55ms\n"); 1428 break; 1429 case 0x6: 1430 printf("65ms to 210ms\n"); 1431 break; 1432 case 0x9: 1433 printf("260ms to 900ms\n"); 1434 break; 1435 case 0xa: 1436 printf("1s to 3.5s\n"); 1437 break; 1438 default: 1439 printf("unknown %u value\n", val); 1440 break; 1441 } 1442 } 1443 1444 static void 1445 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1446 { 1447 pcireg_t reg; /* for each register */ 1448 pcireg_t val; /* for each bitfield */ 1449 bool check_link = false; 1450 bool check_slot = false; 1451 bool check_rootport = false; 1452 unsigned int pciever; 1453 static const char * const linkspeeds[] = {"2.5", "5.0", "8.0"}; 1454 int i; 1455 1456 printf("\n PCI Express Capabilities Register\n"); 1457 /* Capability Register */ 1458 reg = regs[o2i(capoff)]; 1459 printf(" Capability register: %04x\n", reg >> 16); 1460 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1461 printf(" Capability version: %u\n", pciever); 1462 printf(" Device type: "); 1463 switch ((reg & 0x00f00000) >> 20) { 1464 case 0x0: 1465 printf("PCI Express Endpoint device\n"); 1466 check_link = true; 1467 break; 1468 case 0x1: 1469 printf("Legacy PCI Express Endpoint device\n"); 1470 check_link = true; 1471 break; 1472 case 0x4: 1473 printf("Root Port of PCI Express Root Complex\n"); 1474 check_link = true; 1475 check_slot = true; 1476 check_rootport = true; 1477 break; 1478 case 0x5: 1479 printf("Upstream Port of PCI Express Switch\n"); 1480 break; 1481 case 0x6: 1482 printf("Downstream Port of PCI Express Switch\n"); 1483 check_slot = true; 1484 check_rootport = true; 1485 break; 1486 case 0x7: 1487 printf("PCI Express to PCI/PCI-X Bridge\n"); 1488 break; 1489 case 0x8: 1490 printf("PCI/PCI-X to PCI Express Bridge\n"); 1491 break; 1492 case 0x9: 1493 printf("Root Complex Integrated Endpoint\n"); 1494 break; 1495 case 0xa: 1496 check_rootport = true; 1497 printf("Root Complex Event Collector\n"); 1498 break; 1499 default: 1500 printf("unknown\n"); 1501 break; 1502 } 1503 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1504 printf(" Interrupt Message Number: %x\n", 1505 (unsigned int)((reg & PCIE_XCAP_IRQ) >> 27)); 1506 1507 /* Device Capability Register */ 1508 reg = regs[o2i(capoff + PCIE_DCAP)]; 1509 printf(" Device Capabilities Register: 0x%08x\n", reg); 1510 printf(" Max Payload Size Supported: %u bytes max\n", 1511 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1512 printf(" Phantom Functions Supported: "); 1513 switch ((reg & PCIE_DCAP_PHANTOM_FUNCS) >> 3) { 1514 case 0x0: 1515 printf("not available\n"); 1516 break; 1517 case 0x1: 1518 printf("MSB\n"); 1519 break; 1520 case 0x2: 1521 printf("two MSB\n"); 1522 break; 1523 case 0x3: 1524 printf("All three bits\n"); 1525 break; 1526 } 1527 printf(" Extended Tag Field Supported: %dbit\n", 1528 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1529 printf(" Endpoint L0 Acceptable Latency: "); 1530 pci_print_pcie_L0s_latency((reg & PCIE_DCAP_L0S_LATENCY) >> 6); 1531 printf(" Endpoint L1 Acceptable Latency: "); 1532 pci_print_pcie_L1_latency((reg & PCIE_DCAP_L1_LATENCY) >> 9); 1533 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1534 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1535 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1536 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1537 printf(" Captured Slot Power Limit Value: %d\n", 1538 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18); 1539 printf(" Captured Slot Power Limit Scale: %d\n", 1540 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26); 1541 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1542 1543 /* Device Control Register */ 1544 reg = regs[o2i(capoff + PCIE_DCSR)]; 1545 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1546 onoff("Correctable Error Reporting Enable", reg, 1547 PCIE_DCSR_ENA_COR_ERR); 1548 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1549 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1550 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1551 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1552 printf(" Max Payload Size: %d byte\n", 1553 128 << (((unsigned int)(reg & PCIE_DCSR_MAX_PAYLOAD) >> 5))); 1554 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1555 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1556 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1557 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1558 printf(" Max Read Request Size: %d byte\n", 1559 128 << ((unsigned int)(reg & PCIE_DCSR_MAX_READ_REQ) >> 12)); 1560 1561 /* Device Status Register */ 1562 reg = regs[o2i(capoff + PCIE_DCSR)]; 1563 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1564 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1565 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1566 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1567 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1568 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1569 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1570 1571 if (check_link) { 1572 /* Link Capability Register */ 1573 reg = regs[o2i(capoff + PCIE_LCAP)]; 1574 printf(" Link Capabilities Register: 0x%08x\n", reg); 1575 printf(" Maximum Link Speed: "); 1576 val = reg & PCIE_LCAP_MAX_SPEED; 1577 if (val < 1 || val > 3) { 1578 printf("unknown %u value\n", val); 1579 } else { 1580 printf("%sGT/s\n", linkspeeds[val - 1]); 1581 } 1582 printf(" Maximum Link Width: x%u lanes\n", 1583 (unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4); 1584 printf(" Active State PM Support: "); 1585 val = (reg & PCIE_LCAP_ASPM) >> 10; 1586 switch (val) { 1587 case 0x0: 1588 printf("No ASPM support\n"); 1589 break; 1590 case 0x1: 1591 printf("L0s supported\n"); 1592 break; 1593 case 0x2: 1594 printf("L1 supported\n"); 1595 break; 1596 case 0x3: 1597 printf("L0s and L1 supported\n"); 1598 break; 1599 } 1600 printf(" L0 Exit Latency: "); 1601 pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12); 1602 printf(" L1 Exit Latency: "); 1603 pci_print_pcie_L1_latency((reg & PCIE_LCAP_L1_EXIT) >> 15); 1604 printf(" Port Number: %u\n", reg >> 24); 1605 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1606 onoff("Surprise Down Error Report", reg, 1607 PCIE_LCAP_SURPRISE_DOWN); 1608 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1609 onoff("Link BW Notification Capable", reg, 1610 PCIE_LCAP_LINK_BW_NOTIFY); 1611 onoff("ASPM Optionally Compliance", reg, 1612 PCIE_LCAP_ASPM_COMPLIANCE); 1613 1614 /* Link Control Register */ 1615 reg = regs[o2i(capoff + PCIE_LCSR)]; 1616 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1617 printf(" Active State PM Control: "); 1618 val = reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S); 1619 switch (val) { 1620 case 0: 1621 printf("disabled\n"); 1622 break; 1623 case 1: 1624 printf("L0s Entry Enabled\n"); 1625 break; 1626 case 2: 1627 printf("L1 Entry Enabled\n"); 1628 break; 1629 case 3: 1630 printf("L0s and L1 Entry Enabled\n"); 1631 break; 1632 } 1633 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1634 "128bytes", "64bytes"); 1635 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1636 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1637 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1638 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1639 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1640 onoff("Hardware Autonomous Width Disable", reg, 1641 PCIE_LCSR_HAWD); 1642 onoff("Link Bandwidth Management Interrupt Enable", reg, 1643 PCIE_LCSR_LBMIE); 1644 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1645 PCIE_LCSR_LABIE); 1646 1647 /* Link Status Register */ 1648 reg = regs[o2i(capoff + PCIE_LCSR)]; 1649 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1650 printf(" Negotiated Link Speed: "); 1651 if (((reg >> 16) & 0x000f) < 1 || 1652 ((reg >> 16) & 0x000f) > 3) { 1653 printf("unknown %u value\n", 1654 (unsigned int)(reg & PCIE_LCSR_LINKSPEED) >> 16); 1655 } else { 1656 printf("%sGT/s\n", 1657 linkspeeds[((reg & PCIE_LCSR_LINKSPEED) >> 16)-1]); 1658 } 1659 printf(" Negotiated Link Width: x%u lanes\n", 1660 (reg >> 20) & 0x003f); 1661 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1662 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1663 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1664 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1665 onoff("Link Bandwidth Management Status", reg, 1666 PCIE_LCSR_LINK_BW_MGMT); 1667 onoff("Link Autonomous Bandwidth Status", reg, 1668 PCIE_LCSR_LINK_AUTO_BW); 1669 } 1670 1671 if (check_slot == true) { 1672 /* Slot Capability Register */ 1673 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1674 printf(" Slot Capability Register: %08x\n", reg); 1675 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1676 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1677 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1678 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1679 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1680 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1681 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1682 printf(" Slot Power Limit Value: %d\n", 1683 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1684 printf(" Slot Power Limit Scale: %d\n", 1685 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1686 onoff("Electromechanical Interlock Present", reg, 1687 PCIE_SLCAP_EIP); 1688 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1689 printf(" Physical Slot Number: %d\n", 1690 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1691 1692 /* Slot Control Register */ 1693 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1694 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1695 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1696 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1697 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1698 onoff("Presense Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1699 onoff("Command Completed Interrupt Enabled", reg, 1700 PCIE_SLCSR_CCE); 1701 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1702 printf(" Attention Indicator Control: "); 1703 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1704 case 0x0: 1705 printf("reserved\n"); 1706 break; 1707 case 0x1: 1708 printf("on\n"); 1709 break; 1710 case 0x2: 1711 printf("blink\n"); 1712 break; 1713 case 0x3: 1714 printf("off\n"); 1715 break; 1716 } 1717 printf(" Power Indicator Control: "); 1718 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1719 case 0x0: 1720 printf("reserved\n"); 1721 break; 1722 case 0x1: 1723 printf("on\n"); 1724 break; 1725 case 0x2: 1726 printf("blink\n"); 1727 break; 1728 case 0x3: 1729 printf("off\n"); 1730 break; 1731 } 1732 onoff("Power Controller Control", reg, PCIE_SLCSR_PCC); 1733 onoff("Electromechanical Interlock Control", 1734 reg, PCIE_SLCSR_EIC); 1735 onoff("Data Link Layer State Changed Enable", reg, 1736 PCIE_SLCSR_DLLSCE); 1737 1738 /* Slot Status Register */ 1739 printf(" Slot Status Register: %04x\n", reg >> 16); 1740 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1741 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1742 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1743 onoff("Presense Detect Changed", reg, PCIE_SLCSR_PDC); 1744 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1745 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1746 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1747 onoff("Electromechanical Interlock engaged", reg, 1748 PCIE_SLCSR_EIS); 1749 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 1750 } 1751 1752 if (check_rootport == true) { 1753 /* Root Control Register */ 1754 reg = regs[o2i(capoff + PCIE_RCR)]; 1755 printf(" Root Control Register: %04x\n", reg & 0xffff); 1756 onoff("SERR on Correctable Error Enable", reg, 1757 PCIE_RCR_SERR_CER); 1758 onoff("SERR on Non-Fatal Error Enable", reg, 1759 PCIE_RCR_SERR_NFER); 1760 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 1761 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 1762 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 1763 1764 /* Root Capability Register */ 1765 printf(" Root Capability Register: %04x\n", 1766 reg >> 16); 1767 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 1768 1769 /* Root Status Register */ 1770 reg = regs[o2i(capoff + PCIE_RSR)]; 1771 printf(" Root Status Register: %08x\n", reg); 1772 printf(" PME Requester ID: %04x\n", 1773 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1774 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 1775 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 1776 } 1777 1778 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1779 if (pciever < 2) 1780 return; 1781 1782 /* Device Capabilities 2 */ 1783 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1784 printf(" Device Capabilities 2: 0x%08x\n", reg); 1785 printf(" Completion Timeout Ranges Supported: %u \n", 1786 (unsigned int)(reg & PCIE_DCAP2_COMPT_RANGE)); 1787 onoff("Completion Timeout Disable Supported", reg, 1788 PCIE_DCAP2_COMPT_DIS); 1789 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 1790 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 1791 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 1792 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 1793 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 1794 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 1795 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 1796 printf(" TPH Completer Supported: %u\n", 1797 (unsigned int)(reg & PCIE_DCAP2_TPH_COMP) >> 12); 1798 printf(" LN System CLS: "); 1799 switch (__SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 1800 case 0x0: 1801 printf("Not supported or not in effect\n"); 1802 break; 1803 case 0x1: 1804 printf("64byte cachelines in effect\n"); 1805 break; 1806 case 0x2: 1807 printf("128byte cachelines in effect\n"); 1808 break; 1809 case 0x3: 1810 printf("Reserved\n"); 1811 break; 1812 } 1813 printf(" OBFF Supported: "); 1814 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 1815 case 0x0: 1816 printf("Not supported\n"); 1817 break; 1818 case 0x1: 1819 printf("Message only\n"); 1820 break; 1821 case 0x2: 1822 printf("WAKE# only\n"); 1823 break; 1824 case 0x3: 1825 printf("Both\n"); 1826 break; 1827 } 1828 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 1829 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 1830 printf(" Max End-End TLP Prefixes: %u\n", 1831 (unsigned int)(reg & PCIE_DCAP2_MAX_EETLP) >> 22); 1832 1833 /* Device Control 2 */ 1834 reg = regs[o2i(capoff + PCIE_DCSR2)]; 1835 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 1836 printf(" Completion Timeout Value: "); 1837 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 1838 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 1839 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 1840 onoff("AtomicOp Rquester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 1841 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 1842 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 1843 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 1844 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 1845 printf(" OBFF: "); 1846 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 1847 case 0x0: 1848 printf("Disabled\n"); 1849 break; 1850 case 0x1: 1851 printf("Enabled with Message Signaling Variation A\n"); 1852 break; 1853 case 0x2: 1854 printf("Enabled with Message Signaling Variation B\n"); 1855 break; 1856 case 0x3: 1857 printf("Enabled using WAKE# signaling\n"); 1858 break; 1859 } 1860 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 1861 1862 if (check_link) { 1863 /* Link Capability 2 */ 1864 reg = regs[o2i(capoff + PCIE_LCAP2)]; 1865 printf(" Link Capabilities 2: 0x%08x\n", reg); 1866 val = (reg & PCIE_LCAP2_SUP_LNKSV) >> 1; 1867 printf(" Supported Link Speed Vector:"); 1868 for (i = 0; i <= 2; i++) { 1869 if (((val >> i) & 0x01) != 0) 1870 printf(" %sGT/s", linkspeeds[i]); 1871 } 1872 printf("\n"); 1873 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 1874 1875 /* Link Control 2 */ 1876 reg = regs[o2i(capoff + PCIE_LCSR2)]; 1877 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 1878 printf(" Target Link Speed: "); 1879 val = reg & PCIE_LCSR2_TGT_LSPEED; 1880 if (val < 1 || val > 3) 1881 printf("unknown %u value\n", val); 1882 else 1883 printf("%sGT/s\n", linkspeeds[val - 1]); 1884 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 1885 onoff("HW Autonomous Speed Disabled", reg, 1886 PCIE_LCSR2_HW_AS_DIS); 1887 onoff("Selectable De-emphasis", reg, PCIE_LCSR2_SEL_DEEMP); 1888 printf(" Transmit Margin: %u\n", 1889 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 1890 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 1891 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 1892 printf(" Compliance Present/De-emphasis: %u\n", 1893 (unsigned int)(reg & PCIE_LCSR2_COMP_DEEMP) >> 12); 1894 1895 /* Link Status 2 */ 1896 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 1897 onoff("Current De-emphasis Level", reg, PCIE_LCSR2_DEEMP_LVL); 1898 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 1899 onoff("Equalization Phase 1 Successful", reg, 1900 PCIE_LCSR2_EQP1_SUC); 1901 onoff("Equalization Phase 2 Successful", reg, 1902 PCIE_LCSR2_EQP2_SUC); 1903 onoff("Equalization Phase 3 Successful", reg, 1904 PCIE_LCSR2_EQP3_SUC); 1905 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 1906 } 1907 1908 /* Slot Capability 2 */ 1909 /* Slot Control 2 */ 1910 /* Slot Status 2 */ 1911 } 1912 1913 static void 1914 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 1915 { 1916 pcireg_t reg; 1917 1918 printf("\n MSI-X Capability Register\n"); 1919 1920 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 1921 printf(" Message Control register: 0x%04x\n", 1922 (reg >> 16) & 0xff); 1923 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 1924 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 1925 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 1926 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 1927 printf(" Table offset register: 0x%08x\n", reg); 1928 printf(" Table offset: %08x\n", 1929 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 1930 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 1931 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 1932 printf(" Pending bit array register: 0x%08x\n", reg); 1933 printf(" Pending bit array offset: %08x\n", 1934 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 1935 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 1936 } 1937 1938 static void 1939 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 1940 { 1941 pcireg_t reg; 1942 1943 printf("\n Serial ATA Capability Register\n"); 1944 1945 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 1946 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 1947 printf(" Revision: %u.%u\n", 1948 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 1949 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 1950 1951 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 1952 1953 printf(" BAR Register: 0x%08x\n", reg); 1954 printf(" Register location: "); 1955 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 1956 printf("in config space\n"); 1957 else { 1958 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 1959 printf(" BAR offset: 0x%08x\n", 1960 (pcireg_t)__SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 1961 } 1962 } 1963 1964 static void 1965 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 1966 { 1967 pcireg_t reg; 1968 1969 printf("\n Advanced Features Capability Register\n"); 1970 1971 reg = regs[o2i(capoff + PCI_AFCAPR)]; 1972 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 1973 printf(" AF Structure Length: 0x%02x\n", 1974 (pcireg_t)__SHIFTOUT(reg, PCI_AF_LENGTH)); 1975 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 1976 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 1977 reg = regs[o2i(capoff + PCI_AFCSR)]; 1978 printf(" AF Control register: 0x%02x\n", reg & 0xff); 1979 /* 1980 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 1981 * and it's always 0 on read 1982 */ 1983 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 1984 onoff("Transaction Pending", reg, PCI_AFSR_TP); 1985 } 1986 1987 static struct { 1988 pcireg_t cap; 1989 const char *name; 1990 void (*printfunc)(const pcireg_t *, int); 1991 } pci_captab[] = { 1992 { PCI_CAP_RESERVED0, "reserved", NULL }, 1993 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 1994 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 1995 { PCI_CAP_VPD, "VPD", NULL }, 1996 { PCI_CAP_SLOTID, "SlotID", NULL }, 1997 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 1998 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 1999 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2000 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2001 { PCI_CAP_VENDSPEC, "Vendor-specific", 2002 pci_conf_print_vendspec_cap }, 2003 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2004 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2005 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2006 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2007 pci_conf_print_subsystem_cap }, 2008 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2009 { PCI_CAP_SECURE, "Secure Device", NULL }, 2010 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2011 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2012 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2013 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2014 { PCI_CAP_EA, "Enhanced Allocation", NULL } 2015 }; 2016 2017 static int 2018 pci_conf_find_cap(const pcireg_t *regs, int capoff, unsigned int capid, 2019 int *offsetp) 2020 { 2021 pcireg_t rval; 2022 int off; 2023 2024 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2025 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2026 rval = regs[o2i(off)]; 2027 if (capid == PCI_CAPLIST_CAP(rval)) { 2028 if (offsetp != NULL) 2029 *offsetp = off; 2030 return 1; 2031 } 2032 } 2033 return 0; 2034 } 2035 2036 static void 2037 pci_conf_print_caplist( 2038 #ifdef _KERNEL 2039 pci_chipset_tag_t pc, pcitag_t tag, 2040 #endif 2041 const pcireg_t *regs, int capoff) 2042 { 2043 int off; 2044 pcireg_t foundcap; 2045 pcireg_t rval; 2046 bool foundtable[__arraycount(pci_captab)]; 2047 unsigned int i; 2048 2049 /* Clear table */ 2050 for (i = 0; i < __arraycount(pci_captab); i++) 2051 foundtable[i] = false; 2052 2053 /* Print capability register's offset and the type first */ 2054 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2055 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2056 rval = regs[o2i(off)]; 2057 printf(" Capability register at 0x%02x\n", off); 2058 2059 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2060 foundcap = PCI_CAPLIST_CAP(rval); 2061 if (foundcap < __arraycount(pci_captab)) { 2062 printf("%s)\n", pci_captab[foundcap].name); 2063 /* Mark as found */ 2064 foundtable[foundcap] = true; 2065 } else 2066 printf("unknown)\n"); 2067 } 2068 2069 /* 2070 * And then, print the detail of each capability registers 2071 * in capability value's order. 2072 */ 2073 for (i = 0; i < __arraycount(pci_captab); i++) { 2074 if (foundtable[i] == false) 2075 continue; 2076 2077 /* 2078 * The type was found. Search capability list again and 2079 * print all capabilities that the capabiliy type is 2080 * the same. This is required because some capabilities 2081 * appear multiple times (e.g. HyperTransport capability). 2082 */ 2083 #if 0 2084 if (pci_conf_find_cap(regs, capoff, i, &off)) { 2085 rval = regs[o2i(off)]; 2086 if (pci_captab[i].printfunc != NULL) 2087 pci_captab[i].printfunc(regs, off); 2088 } 2089 #else 2090 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2091 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2092 rval = regs[o2i(off)]; 2093 if ((PCI_CAPLIST_CAP(rval) == i) 2094 && (pci_captab[i].printfunc != NULL)) 2095 pci_captab[i].printfunc(regs, off); 2096 } 2097 #endif 2098 } 2099 } 2100 2101 /* Extended Capability */ 2102 2103 static void 2104 pci_conf_print_aer_cap_uc(pcireg_t reg) 2105 { 2106 2107 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2108 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2109 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2110 onoff("Poisoned TLP", reg, PCI_AER_UC_POISONED_TLP); 2111 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2112 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2113 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2114 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2115 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2116 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2117 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2118 onoff("Unsupported Request Error", reg, 2119 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2120 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2121 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2122 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2123 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2124 onoff("TLP Prefix Blocked Error", reg, 2125 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2126 } 2127 2128 static void 2129 pci_conf_print_aer_cap_cor(pcireg_t reg) 2130 { 2131 2132 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2133 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2134 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2135 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2136 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2137 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2138 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2139 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2140 } 2141 2142 static void 2143 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2144 { 2145 2146 printf(" First Error Pointer: 0x%04x\n", 2147 (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2148 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2149 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2150 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2151 onoff("ECRC Check Enab", reg, PCI_AER_ECRC_CHECK_ENABLE); 2152 onoff("Multiple Header Recording Capable", reg, 2153 PCI_AER_MULT_HDR_CAPABLE); 2154 onoff("Multiple Header Recording Enable", reg, PCI_AER_MULT_HDR_ENABLE); 2155 2156 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2157 if (!tlp_prefix_log) 2158 return; 2159 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2160 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2161 } 2162 2163 static void 2164 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2165 { 2166 2167 onoff("Correctable Error Reporting Enable", reg, 2168 PCI_AER_ROOTERR_COR_ENABLE); 2169 onoff("Non-Fatal Error Reporting Enable", reg, 2170 PCI_AER_ROOTERR_NF_ENABLE); 2171 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2172 } 2173 2174 static void 2175 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2176 { 2177 2178 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2179 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2180 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2181 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2182 PCI_AER_ROOTERR_MULTI_UC_ERR); 2183 onoff("First Uncorrectable Fatal", reg, PCI_AER_ROOTERR_FIRST_UC_FATAL); 2184 onoff("Non-Fatal Error Messages Received", reg, PCI_AER_ROOTERR_NF_ERR); 2185 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2186 printf(" Advanced Error Interrupt Message Number: 0x%u\n", 2187 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2188 } 2189 2190 static void 2191 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2192 { 2193 2194 printf(" Correctable Source ID: 0x%04x\n", 2195 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2196 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2197 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2198 } 2199 2200 static void 2201 pci_conf_print_aer_cap(const pcireg_t *regs, int capoff, int extcapoff) 2202 { 2203 pcireg_t reg; 2204 int pcie_capoff; 2205 int pcie_devtype = -1; 2206 bool tlp_prefix_log = false; 2207 2208 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2209 reg = regs[o2i(pcie_capoff)]; 2210 pcie_devtype = PCIE_XCAP_TYPE(reg); 2211 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2212 if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2213 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2214 /* End-End TLP Prefix Supported */ 2215 if (reg & PCIE_DCAP2_EETLP_PREF) { 2216 tlp_prefix_log = true; 2217 } 2218 } 2219 } 2220 2221 printf("\n Advanced Error Reporting Register\n"); 2222 2223 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2224 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2225 pci_conf_print_aer_cap_uc(reg); 2226 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2227 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2228 pci_conf_print_aer_cap_uc(reg); 2229 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2230 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2231 pci_conf_print_aer_cap_uc(reg); 2232 2233 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2234 printf(" Correctable Error Status register: 0x%08x\n", reg); 2235 pci_conf_print_aer_cap_cor(reg); 2236 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2237 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2238 pci_conf_print_aer_cap_cor(reg); 2239 2240 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2241 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2242 reg); 2243 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2244 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2245 printf(" Header Log register:\n"); 2246 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2247 extcapoff + PCI_AER_ROOTERR_CMD); 2248 2249 switch (pcie_devtype) { 2250 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ 2251 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ 2252 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2253 printf(" Root Error Command register: 0x%08x\n", reg); 2254 pci_conf_print_aer_cap_rooterr_cmd(reg); 2255 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2256 printf(" Root Error Status register: 0x%08x\n", reg); 2257 pci_conf_print_aer_cap_rooterr_status(reg); 2258 2259 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2260 printf(" Error Source Identification: 0x%04x\n", reg); 2261 pci_conf_print_aer_cap_errsrc_id(reg); 2262 break; 2263 } 2264 2265 if (tlp_prefix_log) { 2266 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2267 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2268 } 2269 } 2270 2271 static void 2272 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2273 pcireg_t parbsel, int parbsize) 2274 { 2275 pcireg_t reg; 2276 int num = 16 << parbsel; 2277 int num_per_reg = sizeof(pcireg_t) / parbsize; 2278 int i, j; 2279 2280 /* First, dump the table */ 2281 for (i = 0; i < num; i += num_per_reg) { 2282 reg = regs[o2i(off + i / num_per_reg)]; 2283 printf(" %s Arbitration Table: 0x%08x\n", name, reg); 2284 } 2285 /* And then, decode each entry */ 2286 for (i = 0; i < num; i += num_per_reg) { 2287 reg = regs[o2i(off + i / num_per_reg)]; 2288 for (j = 0; j < num_per_reg; j++) 2289 printf(" Phase[%d]: %d\n", j, reg); 2290 } 2291 } 2292 2293 static void 2294 pci_conf_print_vc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2295 { 2296 pcireg_t reg, n; 2297 int parbtab, parbsize; 2298 pcireg_t parbsel; 2299 int varbtab, varbsize; 2300 pcireg_t varbsel; 2301 int i, count; 2302 2303 printf("\n Virtual Channel Register\n"); 2304 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2305 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2306 count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2307 printf(" Extended VC Count: %d\n", count); 2308 n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2309 printf(" Low Priority Extended VC Count: %u\n", n); 2310 n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2311 printf(" Reference Clock: %s\n", 2312 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 2313 parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2314 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2315 2316 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 2317 printf(" Port VC Capability register 2: 0x%08x\n", reg); 2318 onoff("Hardware fixed arbitration scheme", 2319 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 2320 onoff("WRR arbitration with 32 phases", 2321 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 2322 onoff("WRR arbitration with 64 phases", 2323 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 2324 onoff("WRR arbitration with 128 phases", 2325 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 2326 varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 2327 printf(" VC Arbitration Table Offset: 0x%x\n", varbtab); 2328 2329 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 2330 printf(" Port VC Control register: 0x%04x\n", reg); 2331 varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 2332 printf(" VC Arbitration Select: 0x%x\n", varbsel); 2333 2334 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 2335 printf(" Port VC Status register: 0x%04x\n", reg); 2336 onoff("VC Arbitration Table Status", 2337 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 2338 2339 for (i = 0; i < count + 1; i++) { 2340 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 2341 printf(" VC number %d\n", i); 2342 printf(" VC Resource Capability Register: 0x%08x\n", reg); 2343 onoff(" Non-configurable Hardware fixed arbitration scheme", 2344 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 2345 onoff(" WRR arbitration with 32 phases", 2346 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 2347 onoff(" WRR arbitration with 64 phases", 2348 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 2349 onoff(" WRR arbitration with 128 phases", 2350 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 2351 onoff(" Time-based WRR arbitration with 128 phases", 2352 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 2353 onoff(" WRR arbitration with 256 phases", 2354 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 2355 onoff(" Advanced Packet Switching", 2356 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 2357 onoff(" Reject Snoop Transaction", 2358 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 2359 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 2360 printf(" Maximum Time Slots: %d\n", n); 2361 parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S; 2362 printf(" Port Arbitration Table offset: 0x%02x\n", 2363 parbtab); 2364 2365 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 2366 printf(" VC Resource Control Register: 0x%08x\n", reg); 2367 printf(" TC/VC Map: %02x\n", 2368 (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 2369 /* 2370 * The load Port Arbitration Table bit is used to update 2371 * the Port Arbitration logic and it's always 0 on read, so 2372 * we don't print it. 2373 */ 2374 parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 2375 printf(" Port Arbitration Select: %x\n", parbsel); 2376 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 2377 printf(" VC ID %d\n", n); 2378 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 2379 2380 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 2381 printf(" VC Resource Status Register: 0x%08x\n", reg); 2382 onoff(" Port Arbitration Table Status", 2383 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 2384 onoff(" VC Negotiation Pending", 2385 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 2386 2387 if ((parbtab != 0) && (parbsel != 0)) 2388 pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab, 2389 "Port", parbsel, parbsize); 2390 } 2391 2392 varbsize = 8; 2393 if ((varbtab != 0) && (varbsel != 0)) 2394 pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab, 2395 " VC", varbsel, varbsize); 2396 } 2397 2398 static const char * 2399 pci_conf_print_pwrbdgt_base_power(uint8_t reg) 2400 { 2401 2402 switch (reg) { 2403 case 0xf0: 2404 return "250W"; 2405 case 0xf1: 2406 return "275W"; 2407 case 0xf2: 2408 return "300W"; 2409 default: 2410 return "Unknown"; 2411 } 2412 } 2413 2414 static const char * 2415 pci_conf_print_pwrbdgt_data_scale(uint8_t reg) 2416 { 2417 2418 switch (reg) { 2419 case 0x00: 2420 return "1.0x"; 2421 case 0x01: 2422 return "0.1x"; 2423 case 0x02: 2424 return "0.01x"; 2425 case 0x03: 2426 return "0.001x"; 2427 default: 2428 return "wrong value!"; 2429 } 2430 } 2431 2432 static const char * 2433 pci_conf_print_pwrbdgt_type(uint8_t reg) 2434 { 2435 2436 switch (reg) { 2437 case 0x00: 2438 return "PME Aux"; 2439 case 0x01: 2440 return "Auxilary"; 2441 case 0x02: 2442 return "Idle"; 2443 case 0x03: 2444 return "Sustained"; 2445 case 0x07: 2446 return "Maximun"; 2447 default: 2448 return "Unknown"; 2449 } 2450 } 2451 2452 static const char * 2453 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 2454 { 2455 2456 switch (reg) { 2457 case 0x00: 2458 return "Power(12V)"; 2459 case 0x01: 2460 return "Power(3.3V)"; 2461 case 0x02: 2462 return "Power(1.5V or 1.8V)"; 2463 case 0x07: 2464 return "Thermal"; 2465 default: 2466 return "Unknown"; 2467 } 2468 } 2469 2470 static void 2471 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff) 2472 { 2473 pcireg_t reg; 2474 2475 printf("\n Power Budget Register\n"); 2476 2477 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 2478 printf(" Data Select register: 0x%08x\n", reg); 2479 2480 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 2481 printf(" Data register: 0x%08x\n", reg); 2482 printf(" Base Power: %s\n", 2483 pci_conf_print_pwrbdgt_base_power((uint8_t)reg)); 2484 printf(" Data Scale: %s\n", 2485 pci_conf_print_pwrbdgt_data_scale( 2486 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE)))); 2487 printf(" PM Sub State: 0x%hhx\n", 2488 (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 2489 printf(" PM State: D%u\n", 2490 (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 2491 printf(" Type: %s\n", 2492 pci_conf_print_pwrbdgt_type( 2493 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 2494 printf(" Power Rail: %s\n", 2495 pci_conf_print_pwrbdgt_pwrrail( 2496 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 2497 2498 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 2499 printf(" Power Budget Capability register: 0x%08x\n", reg); 2500 onoff("System Allocated", 2501 reg, PCI_PWRBDGT_CAP_SYSALLOC); 2502 } 2503 2504 static const char * 2505 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 2506 { 2507 2508 switch (type) { 2509 case 0x00: 2510 return "Configuration Space Element"; 2511 case 0x01: 2512 return "System Egress Port or internal sink (memory)"; 2513 case 0x02: 2514 return "Internal Root Complex Link"; 2515 default: 2516 return "Unknown"; 2517 } 2518 } 2519 2520 static void 2521 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int capoff, int extcapoff) 2522 { 2523 pcireg_t reg; 2524 unsigned char nent, linktype; 2525 int i; 2526 2527 printf("\n Root Complex Link Declaration\n"); 2528 2529 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 2530 printf(" Element Self Description Register: 0x%08x\n", reg); 2531 printf(" Element Type: %s\n", 2532 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 2533 nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 2534 printf(" Number of Link Entries: %hhu\n", nent); 2535 printf(" Component ID: %hhu\n", 2536 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 2537 printf(" Port Number: %hhu\n", 2538 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 2539 for (i = 0; i < nent; i++) { 2540 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 2541 printf(" Link Entry %d:\n", i + 1); 2542 printf(" Link Description Register: 0x%08x\n", reg); 2543 onoff(" Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID); 2544 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 2545 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 2546 "Configuration Space", "Memory-Mapped Space"); 2547 onoff(" Associated RCRB Header", reg, 2548 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 2549 printf(" Target Component ID: %hhu\n", 2550 (unsigned char)__SHIFTOUT(reg, 2551 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 2552 printf(" Target Port Number: %hhu\n", 2553 (unsigned char)__SHIFTOUT(reg, 2554 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 2555 2556 if (linktype == 0) { 2557 /* Memory-Mapped Space */ 2558 reg = regs[o2i(extcapoff 2559 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 2560 printf(" Link Address Low Register: 0x%08x\n", 2561 reg); 2562 reg = regs[o2i(extcapoff 2563 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 2564 printf(" Link Address High Register: 0x%08x\n", 2565 reg); 2566 } else { 2567 unsigned int nb; 2568 pcireg_t lo, hi; 2569 2570 /* Configuration Space */ 2571 lo = regs[o2i(extcapoff 2572 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 2573 printf(" Configuration Space Low Register: " 2574 "0x%08x\n", lo); 2575 hi = regs[o2i(extcapoff 2576 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 2577 printf(" Configuration Space High Register: " 2578 "0x%08x\n", hi); 2579 nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 2580 printf(" N: %u\n", nb); 2581 printf(" Func: %hhu\n", 2582 (unsigned char)__SHIFTOUT(lo, 2583 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 2584 printf(" Dev: %hhu\n", 2585 (unsigned char)__SHIFTOUT(lo, 2586 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 2587 printf(" Bus: %hhu\n", 2588 (unsigned char)__SHIFTOUT(lo, 2589 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 2590 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 2591 printf(" Configuration Space Base Address: " 2592 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 2593 } 2594 } 2595 } 2596 2597 /* XXX pci_conf_print_rclink_ctl_cap */ 2598 2599 static void 2600 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2601 { 2602 pcireg_t reg; 2603 2604 printf("\n Root Complex Event Collector Association\n"); 2605 2606 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 2607 printf(" Association Bitmap for Root Complex Integrated Devices:" 2608 " 0x%08x\n", reg); 2609 } 2610 2611 /* XXX pci_conf_print_mfvc_cap */ 2612 /* XXX pci_conf_print_vc2_cap */ 2613 /* XXX pci_conf_print_rcrb_cap */ 2614 /* XXX pci_conf_print_vendor_cap */ 2615 /* XXX pci_conf_print_cac_cap */ 2616 2617 static void 2618 pci_conf_print_acs_cap(const pcireg_t *regs, int capoff, int extcapoff) 2619 { 2620 pcireg_t reg, cap, ctl; 2621 unsigned int size, i; 2622 2623 printf("\n Access Control Services\n"); 2624 2625 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 2626 cap = reg & 0xffff; 2627 ctl = reg >> 16; 2628 printf(" ACS Capability register: 0x%08x\n", cap); 2629 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 2630 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 2631 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 2632 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 2633 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 2634 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 2635 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 2636 size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 2637 if (size == 0) 2638 size = 256; 2639 printf(" Egress Control Vector Size: %u\n", size); 2640 printf(" ACS Control register: 0x%08x\n", ctl); 2641 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 2642 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 2643 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 2644 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 2645 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 2646 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 2647 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 2648 2649 /* 2650 * If the P2P Egress Control Capability bit is 0, ignore the Egress 2651 * Control vector. 2652 */ 2653 if ((cap & PCI_ACS_CAP_E) == 0) 2654 return; 2655 for (i = 0; i < size; i += 32) 2656 printf(" Egress Control Vector [%u..%u]: %x\n", i + 31, 2657 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 2658 } 2659 2660 static void 2661 pci_conf_print_ari_cap(const pcireg_t *regs, int capoff, int extcapoff) 2662 { 2663 pcireg_t reg, cap, ctl; 2664 2665 printf("\n Alternative Routing-ID Interpretation Register\n"); 2666 2667 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2668 cap = reg & 0xffff; 2669 ctl = reg >> 16; 2670 printf(" Capability register: 0x%08x\n", cap); 2671 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 2672 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 2673 printf(" Next Function Number: %u\n", 2674 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 2675 printf(" Control register: 0x%08x\n", ctl); 2676 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 2677 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 2678 printf(" Function Group: %u\n", 2679 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 2680 } 2681 2682 static void 2683 pci_conf_print_ats_cap(const pcireg_t *regs, int capoff, int extcapoff) 2684 { 2685 pcireg_t reg, cap, ctl; 2686 unsigned int num; 2687 2688 printf("\n Address Translation Services\n"); 2689 2690 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2691 cap = reg & 0xffff; 2692 ctl = reg >> 16; 2693 printf(" Capability register: 0x%04x\n", cap); 2694 num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 2695 if (num == 0) 2696 num = 32; 2697 printf(" Invalidate Queue Depth: %u\n", num); 2698 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 2699 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 2700 2701 printf(" Control register: 0x%04x\n", ctl); 2702 printf(" Smallest Translation Unit: %u\n", 2703 (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU)); 2704 onoff("Enable", reg, PCI_ATS_CTL_EN); 2705 } 2706 2707 static void 2708 pci_conf_print_sernum_cap(const pcireg_t *regs, int capoff, int extcapoff) 2709 { 2710 pcireg_t lo, hi; 2711 2712 printf("\n Device Serial Number Register\n"); 2713 2714 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 2715 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 2716 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 2717 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 2718 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 2719 } 2720 2721 static void 2722 pci_conf_print_sriov_cap(const pcireg_t *regs, int capoff, int extcapoff) 2723 { 2724 char buf[sizeof("99999 MB")]; 2725 pcireg_t reg; 2726 pcireg_t total_vfs; 2727 int i; 2728 bool first; 2729 2730 printf("\n Single Root IO Virtualization Register\n"); 2731 2732 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 2733 printf(" Capabilities register: 0x%08x\n", reg); 2734 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 2735 onoff("ARI Capable Hierarchy Preserved", reg, 2736 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 2737 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 2738 printf(" VF Migration Interrupt Message Number: 0x%u\n", 2739 (pcireg_t)__SHIFTOUT(reg, 2740 PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 2741 } 2742 2743 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 2744 printf(" Control register: 0x%04x\n", reg); 2745 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 2746 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 2747 onoff("VF Migration Interrupt Enable", reg, 2748 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 2749 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 2750 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 2751 2752 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 2753 printf(" Status register: 0x%04x\n", reg); 2754 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 2755 2756 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 2757 printf(" InitialVFs register: 0x%04x\n", reg); 2758 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 2759 printf(" TotalVFs register: 0x%04x\n", reg); 2760 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 2761 printf(" NumVFs register: 0x%04x\n", reg); 2762 2763 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 2764 printf(" Function Dependency Link register: 0x%04x\n", reg); 2765 2766 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 2767 printf(" First VF Offset register: 0x%04x\n", reg); 2768 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 2769 printf(" VF Stride register: 0x%04x\n", reg); 2770 2771 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 2772 printf(" Supported Page Sizes register: 0x%08x\n", reg); 2773 printf(" Supported Page Size:"); 2774 for (i = 0, first = true; i < 32; i++) { 2775 if (reg & __BIT(i)) { 2776 #ifdef _KERNEL 2777 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 2778 #else 2779 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 2780 HN_AUTOSCALE, 0); 2781 #endif 2782 printf("%s %s", first ? "" : ",", buf); 2783 first = false; 2784 } 2785 } 2786 printf("\n"); 2787 2788 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 2789 printf(" System Page Sizes register: 0x%08x\n", reg); 2790 printf(" Page Size: "); 2791 if (reg != 0) { 2792 #ifdef _KERNEL 2793 format_bytes(buf, sizeof(buf), 1LL << (ffs(reg) + 12)); 2794 #else 2795 humanize_number(buf, sizeof(buf), 1LL << (ffs(reg) + 12), "B", 2796 HN_AUTOSCALE, 0); 2797 #endif 2798 printf("%s", buf); 2799 } else { 2800 printf("unknown"); 2801 } 2802 printf("\n"); 2803 2804 for (i = 0; i < 6; i++) { 2805 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 2806 printf(" VF BAR%d register: 0x%08x\n", i, reg); 2807 } 2808 2809 if (total_vfs > 0) { 2810 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 2811 printf(" VF Migration State Array Offset register: 0x%08x\n", 2812 reg); 2813 printf(" VF Migration State Offset: 0x%08x\n", 2814 (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 2815 i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 2816 printf(" VF Migration State BIR: "); 2817 if (i >= 0 && i <= 5) { 2818 printf("BAR%d", i); 2819 } else { 2820 printf("unknown BAR (%d)", i); 2821 } 2822 printf("\n"); 2823 } 2824 } 2825 2826 /* XXX pci_conf_print_mriov_cap */ 2827 2828 static void 2829 pci_conf_print_multicast_cap(const pcireg_t *regs, int capoff, int extcapoff) 2830 { 2831 pcireg_t reg, cap, ctl; 2832 pcireg_t regl, regh; 2833 uint64_t addr; 2834 int n; 2835 2836 printf("\n Multicast\n"); 2837 2838 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 2839 cap = reg & 0xffff; 2840 ctl = reg >> 16; 2841 printf(" Capability Register: 0x%04x\n", cap); 2842 printf(" Max Group: %u\n", 2843 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 2844 2845 /* Endpoint Only */ 2846 n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 2847 if (n > 0) 2848 printf(" Windw Size Requested: %d\n", 1 << (n - 1)); 2849 2850 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 2851 2852 printf(" Control Register: 0x%04x\n", ctl); 2853 printf(" Num Group: %u\n", 2854 (unsigned int)__SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 2855 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 2856 2857 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 2858 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 2859 printf(" Base Address Register 0: 0x%08x\n", regl); 2860 printf(" Base Address Register 1: 0x%08x\n", regh); 2861 printf(" Index Position: %u\n", 2862 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 2863 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 2864 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 2865 2866 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 2867 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 2868 printf(" Receive Register 0: 0x%08x\n", regl); 2869 printf(" Receive Register 1: 0x%08x\n", regh); 2870 2871 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 2872 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 2873 printf(" Block All Register 0: 0x%08x\n", regl); 2874 printf(" Block All Register 1: 0x%08x\n", regh); 2875 2876 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 2877 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 2878 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 2879 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 2880 2881 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 2882 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 2883 printf(" Overlay BAR 0: 0x%08x\n", regl); 2884 printf(" Overlay BAR 1: 0x%08x\n", regh); 2885 2886 n = regl & PCI_MCAST_OVERLAYL_SIZE; 2887 printf(" Overlay Size: "); 2888 if (n >= 6) 2889 printf("%d\n", n); 2890 else 2891 printf("off\n"); 2892 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 2893 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 2894 } 2895 2896 static void 2897 pci_conf_print_page_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 2898 { 2899 pcireg_t reg, ctl, sta; 2900 2901 printf("\n Page Request\n"); 2902 2903 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 2904 ctl = reg & 0xffff; 2905 sta = reg >> 16; 2906 printf(" Control Register: 0x%04x\n", ctl); 2907 onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E); 2908 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 2909 2910 printf(" Status Register: 0x%04x\n", sta); 2911 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 2912 onoff("Unexpected Page Request Group Index", reg, 2913 PCI_PAGE_REQ_STA_UPRGI); 2914 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 2915 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 2916 2917 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 2918 printf(" Outstanding Page Request Capacity: %u\n", reg); 2919 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 2920 printf(" Outstanding Page Request Allocation: %u\n", reg); 2921 } 2922 2923 /* XXX pci_conf_print_amd_cap */ 2924 /* XXX pci_conf_print_resiz_bar_cap */ 2925 /* XXX pci_conf_print_dpa_cap */ 2926 2927 static const char * 2928 pci_conf_print_tph_req_cap_sttabloc(unsigned char val) 2929 { 2930 2931 switch (val) { 2932 case 0x0: 2933 return "Not Present"; 2934 case 0x1: 2935 return "in the TPH Requester Capability Structure"; 2936 case 0x2: 2937 return "in the MSI-X Table"; 2938 default: 2939 return "Unknown"; 2940 } 2941 } 2942 2943 static void 2944 pci_conf_print_tph_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 2945 { 2946 pcireg_t reg; 2947 int size, i, j; 2948 2949 printf("\n TPH Requester Extended Capability\n"); 2950 2951 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 2952 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 2953 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 2954 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 2955 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 2956 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 2957 printf(" ST Table Location: %s\n", 2958 pci_conf_print_tph_req_cap_sttabloc( 2959 (unsigned char)__SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC))); 2960 size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 2961 printf(" ST Table Size: %d\n", size); 2962 for (i = 0; i < size ; i += 2) { 2963 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 2964 for (j = 0; j < 2 ; j++) { 2965 uint32_t entry = reg; 2966 2967 if (j != 0) 2968 entry >>= 16; 2969 entry &= 0xffff; 2970 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 2971 i + j, entry); 2972 } 2973 } 2974 } 2975 2976 static void 2977 pci_conf_print_ltr_cap(const pcireg_t *regs, int capoff, int extcapoff) 2978 { 2979 pcireg_t reg; 2980 2981 printf("\n Latency Tolerance Reporting\n"); 2982 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)] & 0xffff; 2983 printf(" Max Snoop Latency Register: 0x%04x\n", reg); 2984 printf(" Max Snoop LatencyValue: %u\n", 2985 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL)); 2986 printf(" Max Snoop LatencyScale: %uns\n", 2987 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE))); 2988 reg = regs[o2i(extcapoff + PCI_LTR_MAXNOSNOOPLAT)] >> 16; 2989 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg); 2990 printf(" Max No-Snoop LatencyValue: %u\n", 2991 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL)); 2992 printf(" Max No-Snoop LatencyScale: %uns\n", 2993 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE))); 2994 } 2995 2996 static void 2997 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int capoff, int extcapoff) 2998 { 2999 int pcie_capoff; 3000 pcireg_t reg; 3001 int i, maxlinkwidth; 3002 3003 printf("\n Secondary PCI Express Register\n"); 3004 3005 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3006 printf(" Link Control 3 register: 0x%08x\n", reg); 3007 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3008 onoff("Link Equalization Request Interrupt Enable", 3009 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3010 3011 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3012 printf(" Lane Error Status register: 0x%08x\n", reg); 3013 3014 /* Get Max Link Width */ 3015 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)){ 3016 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3017 maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3018 } else { 3019 printf("error: falied to get PCIe capablity\n"); 3020 return; 3021 } 3022 for (i = 0; i < maxlinkwidth; i++) { 3023 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3024 if (i % 2 != 0) 3025 reg >>= 16; 3026 else 3027 reg &= 0xffff; 3028 printf(" Equalization Control Register (Link %d): %04x\n", 3029 i, reg); 3030 printf(" Downstream Port Transmit Preset: 0x%x\n", 3031 (pcireg_t)__SHIFTOUT(reg, 3032 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3033 printf(" Downstream Port Receive Hint: 0x%x\n", 3034 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3035 printf(" Upstream Port Transmit Preset: 0x%x\n", 3036 (pcireg_t)__SHIFTOUT(reg, 3037 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3038 printf(" Upstream Port Receive Hint: 0x%x\n", 3039 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3040 } 3041 } 3042 3043 /* XXX pci_conf_print_pmux_cap */ 3044 3045 static void 3046 pci_conf_print_pasid_cap(const pcireg_t *regs, int capoff, int extcapoff) 3047 { 3048 pcireg_t reg, cap, ctl; 3049 unsigned int num; 3050 3051 printf("\n Process Address Space ID\n"); 3052 3053 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3054 cap = reg & 0xffff; 3055 ctl = reg >> 16; 3056 printf(" PASID Capability Register: 0x%04x\n", cap); 3057 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3058 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3059 num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3060 printf(" Max PASID Width: %u\n", num); 3061 3062 printf(" PASID Control Register: 0x%04x\n", ctl); 3063 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3064 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3065 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 3066 } 3067 3068 static void 3069 pci_conf_print_lnr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3070 { 3071 pcireg_t reg, cap, ctl; 3072 unsigned int num; 3073 3074 printf("\n LN Requester\n"); 3075 3076 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 3077 cap = reg & 0xffff; 3078 ctl = reg >> 16; 3079 printf(" LNR Capability register: 0x%04x\n", cap); 3080 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 3081 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 3082 num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 3083 printf(" LNR Registration MAX: %u\n", num); 3084 3085 printf(" LNR Control register: 0x%04x\n", ctl); 3086 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 3087 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 3088 num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 3089 printf(" LNR Registration Limit: %u\n", num); 3090 } 3091 3092 /* XXX pci_conf_print_dpc_cap */ 3093 3094 static int 3095 pci_conf_l1pm_cap_tposcale(unsigned char scale) 3096 { 3097 3098 /* Return scale in us */ 3099 switch (scale) { 3100 case 0x0: 3101 return 2; 3102 case 0x1: 3103 return 10; 3104 case 0x2: 3105 return 100; 3106 default: 3107 return -1; 3108 } 3109 } 3110 3111 static void 3112 pci_conf_print_l1pm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3113 { 3114 pcireg_t reg; 3115 int scale, val; 3116 3117 printf("\n L1 PM Substates\n"); 3118 3119 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 3120 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 3121 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 3122 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 3123 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 3124 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 3125 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 3126 printf(" Port Common Mode Restore Time: %uus\n", 3127 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 3128 scale = pci_conf_l1pm_cap_tposcale( 3129 __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 3130 val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 3131 printf(" Port T_POWER_ON: "); 3132 if (scale == -1) 3133 printf("unknown\n"); 3134 else 3135 printf("%dus\n", val * scale); 3136 3137 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 3138 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 3139 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 3140 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 3141 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 3142 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 3143 printf(" Common Mode Restore Time: %uus\n", 3144 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 3145 scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 3146 val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 3147 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 3148 3149 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 3150 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 3151 scale = pci_conf_l1pm_cap_tposcale( 3152 __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 3153 val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 3154 printf(" T_POWER_ON: "); 3155 if (scale == -1) 3156 printf("unknown\n"); 3157 else 3158 printf("%dus\n", val * scale); 3159 } 3160 3161 /* XXX pci_conf_print_ptm_cap */ 3162 /* XXX pci_conf_print_mpcie_cap */ 3163 /* XXX pci_conf_print_frsq_cap */ 3164 /* XXX pci_conf_print_rtr_cap */ 3165 /* XXX pci_conf_print_desigvndsp_cap */ 3166 3167 #undef MS 3168 #undef SM 3169 #undef RW 3170 3171 static struct { 3172 pcireg_t cap; 3173 const char *name; 3174 void (*printfunc)(const pcireg_t *, int, int); 3175 } pci_extcaptab[] = { 3176 { 0, "reserved", 3177 NULL }, 3178 { PCI_EXTCAP_AER, "Advanced Error Reporting", 3179 pci_conf_print_aer_cap }, 3180 { PCI_EXTCAP_VC, "Virtual Channel", 3181 pci_conf_print_vc_cap }, 3182 { PCI_EXTCAP_SERNUM, "Device Serial Number", 3183 pci_conf_print_sernum_cap }, 3184 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 3185 pci_conf_print_pwrbdgt_cap }, 3186 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 3187 pci_conf_print_rclink_dcl_cap }, 3188 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 3189 NULL }, 3190 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 3191 pci_conf_print_rcec_assoc_cap }, 3192 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 3193 NULL }, 3194 { PCI_EXTCAP_VC2, "Virtual Channel", 3195 NULL }, 3196 { PCI_EXTCAP_RCRB, "RCRB Header", 3197 NULL }, 3198 { PCI_EXTCAP_VENDOR, "Vendor Unique", 3199 NULL }, 3200 { PCI_EXTCAP_CAC, "Configuration Access Correction", 3201 NULL }, 3202 { PCI_EXTCAP_ACS, "Access Control Services", 3203 pci_conf_print_acs_cap }, 3204 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 3205 pci_conf_print_ari_cap }, 3206 { PCI_EXTCAP_ATS, "Address Translation Services", 3207 pci_conf_print_ats_cap }, 3208 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 3209 pci_conf_print_sriov_cap }, 3210 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 3211 NULL }, 3212 { PCI_EXTCAP_MCAST, "Multicast", 3213 pci_conf_print_multicast_cap }, 3214 { PCI_EXTCAP_PAGE_REQ, "Page Request", 3215 pci_conf_print_page_req_cap }, 3216 { PCI_EXTCAP_AMD, "Reserved for AMD", 3217 NULL }, 3218 { PCI_EXTCAP_RESIZ_BAR, "Resizable BAR", 3219 NULL }, 3220 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 3221 NULL }, 3222 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 3223 pci_conf_print_tph_req_cap }, 3224 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 3225 pci_conf_print_ltr_cap }, 3226 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 3227 pci_conf_print_sec_pcie_cap }, 3228 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 3229 NULL }, 3230 { PCI_EXTCAP_PASID, "Process Address Space ID", 3231 pci_conf_print_pasid_cap }, 3232 { PCI_EXTCAP_LN_REQ, "LN Requester", 3233 pci_conf_print_lnr_cap }, 3234 { PCI_EXTCAP_DPC, "Downstream Port Containment", 3235 NULL }, 3236 { PCI_EXTCAP_L1PM, "L1 PM Substates", 3237 pci_conf_print_l1pm_cap }, 3238 { PCI_EXTCAP_PTM, "Precision Time Management", 3239 NULL }, 3240 { PCI_EXTCAP_MPCIE, "M-PCIe", 3241 NULL }, 3242 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 3243 NULL }, 3244 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 3245 NULL }, 3246 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 3247 NULL }, 3248 }; 3249 3250 static int 3251 pci_conf_find_extcap(const pcireg_t *regs, int capoff, unsigned int capid, 3252 int *offsetp) 3253 { 3254 int off; 3255 pcireg_t rval; 3256 3257 for (off = PCI_EXTCAPLIST_BASE; 3258 off != 0; 3259 off = PCI_EXTCAPLIST_NEXT(rval)) { 3260 rval = regs[o2i(off)]; 3261 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 3262 if (offsetp != NULL) 3263 *offsetp = off; 3264 return 1; 3265 } 3266 } 3267 return 0; 3268 } 3269 3270 static void 3271 pci_conf_print_extcaplist( 3272 #ifdef _KERNEL 3273 pci_chipset_tag_t pc, pcitag_t tag, 3274 #endif 3275 const pcireg_t *regs, int capoff) 3276 { 3277 int off; 3278 pcireg_t foundcap; 3279 pcireg_t rval; 3280 bool foundtable[__arraycount(pci_extcaptab)]; 3281 unsigned int i; 3282 3283 /* Check Extended capability structure */ 3284 off = PCI_EXTCAPLIST_BASE; 3285 rval = regs[o2i(off)]; 3286 if (rval == 0xffffffff || rval == 0) 3287 return; 3288 3289 /* Clear table */ 3290 for (i = 0; i < __arraycount(pci_extcaptab); i++) 3291 foundtable[i] = false; 3292 3293 /* Print extended capability register's offset and the type first */ 3294 for (;;) { 3295 printf(" Extended Capability Register at 0x%02x\n", off); 3296 3297 foundcap = PCI_EXTCAPLIST_CAP(rval); 3298 printf(" type: 0x%04x (", foundcap); 3299 if (foundcap < __arraycount(pci_extcaptab)) { 3300 printf("%s)\n", pci_extcaptab[foundcap].name); 3301 /* Mark as found */ 3302 foundtable[foundcap] = true; 3303 } else 3304 printf("unknown)\n"); 3305 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 3306 3307 off = PCI_EXTCAPLIST_NEXT(rval); 3308 if (off == 0) 3309 break; 3310 rval = regs[o2i(off)]; 3311 } 3312 3313 /* 3314 * And then, print the detail of each capability registers 3315 * in capability value's order. 3316 */ 3317 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 3318 if (foundtable[i] == false) 3319 continue; 3320 3321 /* 3322 * The type was found. Search capability list again and 3323 * print all capabilities that the capabiliy type is 3324 * the same. 3325 */ 3326 if (pci_conf_find_extcap(regs, capoff, i, &off) == 0) 3327 continue; 3328 rval = regs[o2i(off)]; 3329 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 3330 || (pci_extcaptab[i].printfunc == NULL)) 3331 continue; 3332 3333 pci_extcaptab[i].printfunc(regs, capoff, off); 3334 3335 } 3336 } 3337 3338 /* Print the Secondary Status Register. */ 3339 static void 3340 pci_conf_print_ssr(pcireg_t rval) 3341 { 3342 pcireg_t devsel; 3343 3344 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 3345 onoff("66 MHz capable", rval, __BIT(5)); 3346 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 3347 onoff("Fast back-to-back capable", rval, __BIT(7)); 3348 onoff("Data parity error detected", rval, __BIT(8)); 3349 3350 printf(" DEVSEL timing: "); 3351 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 3352 switch (devsel) { 3353 case 0: 3354 printf("fast"); 3355 break; 3356 case 1: 3357 printf("medium"); 3358 break; 3359 case 2: 3360 printf("slow"); 3361 break; 3362 default: 3363 printf("unknown/reserved"); /* XXX */ 3364 break; 3365 } 3366 printf(" (0x%x)\n", devsel); 3367 3368 onoff("Signalled target abort", rval, __BIT(11)); 3369 onoff("Received target abort", rval, __BIT(12)); 3370 onoff("Received master abort", rval, __BIT(13)); 3371 onoff("Received system error", rval, __BIT(14)); 3372 onoff("Detected parity error", rval, __BIT(15)); 3373 } 3374 3375 static void 3376 pci_conf_print_type0( 3377 #ifdef _KERNEL 3378 pci_chipset_tag_t pc, pcitag_t tag, 3379 #endif 3380 const pcireg_t *regs 3381 #ifdef _KERNEL 3382 , int sizebars 3383 #endif 3384 ) 3385 { 3386 int off, width; 3387 pcireg_t rval; 3388 3389 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 3390 #ifdef _KERNEL 3391 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3392 #else 3393 width = pci_conf_print_bar(regs, off, NULL); 3394 #endif 3395 } 3396 3397 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 3398 3399 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 3400 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 3401 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 3402 3403 /* XXX */ 3404 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 3405 3406 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3407 printf(" Capability list pointer: 0x%02x\n", 3408 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 3409 else 3410 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 3411 3412 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 3413 3414 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3415 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 3416 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 3417 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 3418 switch (PCI_INTERRUPT_PIN(rval)) { 3419 case PCI_INTERRUPT_PIN_NONE: 3420 printf("(none)"); 3421 break; 3422 case PCI_INTERRUPT_PIN_A: 3423 printf("(pin A)"); 3424 break; 3425 case PCI_INTERRUPT_PIN_B: 3426 printf("(pin B)"); 3427 break; 3428 case PCI_INTERRUPT_PIN_C: 3429 printf("(pin C)"); 3430 break; 3431 case PCI_INTERRUPT_PIN_D: 3432 printf("(pin D)"); 3433 break; 3434 default: 3435 printf("(? ? ?)"); 3436 break; 3437 } 3438 printf("\n"); 3439 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 3440 } 3441 3442 static void 3443 pci_conf_print_type1( 3444 #ifdef _KERNEL 3445 pci_chipset_tag_t pc, pcitag_t tag, 3446 #endif 3447 const pcireg_t *regs 3448 #ifdef _KERNEL 3449 , int sizebars 3450 #endif 3451 ) 3452 { 3453 int off, width; 3454 pcireg_t rval; 3455 uint32_t base, limit; 3456 uint32_t base_h, limit_h; 3457 uint64_t pbase, plimit; 3458 int use_upper; 3459 3460 /* 3461 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 3462 * Bridge chip documentation, and may not be correct with 3463 * respect to various standards. (XXX) 3464 */ 3465 3466 for (off = 0x10; off < 0x18; off += width) { 3467 #ifdef _KERNEL 3468 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3469 #else 3470 width = pci_conf_print_bar(regs, off, NULL); 3471 #endif 3472 } 3473 3474 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 3475 printf(" Primary bus number: 0x%02x\n", 3476 PCI_BRIDGE_BUS_PRIMARY(rval)); 3477 printf(" Secondary bus number: 0x%02x\n", 3478 PCI_BRIDGE_BUS_SECONDARY(rval)); 3479 printf(" Subordinate bus number: 0x%02x\n", 3480 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 3481 printf(" Secondary bus latency timer: 0x%02x\n", 3482 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 3483 3484 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 3485 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 3486 3487 /* I/O region */ 3488 printf(" I/O region:\n"); 3489 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 3490 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 3491 if (PCI_BRIDGE_IO_32BITS(rval)) 3492 use_upper = 1; 3493 else 3494 use_upper = 0; 3495 onoff("32bit I/O", rval, use_upper); 3496 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 3497 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 3498 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 3499 limit |= 0x00000fff; 3500 3501 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 3502 base_h = (rval >> 0) & 0xffff; 3503 limit_h = (rval >> 16) & 0xffff; 3504 printf(" base upper 16 bits register: 0x%04x\n", base_h); 3505 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 3506 3507 if (use_upper == 1) { 3508 base |= base_h << 16; 3509 limit |= limit_h << 16; 3510 } 3511 if (base < limit) { 3512 if (use_upper == 1) 3513 printf(" range: 0x%08x-0x%08x\n", base, limit); 3514 else 3515 printf(" range: 0x%04x-0x%04x\n", base, limit); 3516 } else 3517 printf(" range: not set\n"); 3518 3519 /* Non-prefetchable memory region */ 3520 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 3521 printf(" Memory region:\n"); 3522 printf(" base register: 0x%04x\n", 3523 (rval >> 0) & 0xffff); 3524 printf(" limit register: 0x%04x\n", 3525 (rval >> 16) & 0xffff); 3526 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 3527 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 3528 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 3529 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 3530 if (base < limit) 3531 printf(" range: 0x%08x-0x%08x\n", base, limit); 3532 else 3533 printf(" range: not set\n"); 3534 3535 /* Prefetchable memory region */ 3536 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 3537 printf(" Prefetchable memory region:\n"); 3538 printf(" base register: 0x%04x\n", 3539 (rval >> 0) & 0xffff); 3540 printf(" limit register: 0x%04x\n", 3541 (rval >> 16) & 0xffff); 3542 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 3543 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 3544 printf(" base upper 32 bits register: 0x%08x\n", 3545 base_h); 3546 printf(" limit upper 32 bits register: 0x%08x\n", 3547 limit_h); 3548 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 3549 use_upper = 1; 3550 else 3551 use_upper = 0; 3552 onoff("64bit memory address", rval, use_upper); 3553 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 3554 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 3555 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 3556 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 3557 if (use_upper == 1) { 3558 pbase |= (uint64_t)base_h << 32; 3559 plimit |= (uint64_t)limit_h << 32; 3560 } 3561 if (pbase < plimit) { 3562 if (use_upper == 1) 3563 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 3564 "\n", pbase, plimit); 3565 else 3566 printf(" range: 0x%08x-0x%08x\n", 3567 (uint32_t)pbase, (uint32_t)plimit); 3568 } else 3569 printf(" range: not set\n"); 3570 3571 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3572 printf(" Capability list pointer: 0x%02x\n", 3573 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 3574 else 3575 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 3576 3577 /* XXX */ 3578 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 3579 3580 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3581 printf(" Interrupt line: 0x%02x\n", 3582 (rval >> 0) & 0xff); 3583 printf(" Interrupt pin: 0x%02x ", 3584 (rval >> 8) & 0xff); 3585 switch ((rval >> 8) & 0xff) { 3586 case PCI_INTERRUPT_PIN_NONE: 3587 printf("(none)"); 3588 break; 3589 case PCI_INTERRUPT_PIN_A: 3590 printf("(pin A)"); 3591 break; 3592 case PCI_INTERRUPT_PIN_B: 3593 printf("(pin B)"); 3594 break; 3595 case PCI_INTERRUPT_PIN_C: 3596 printf("(pin C)"); 3597 break; 3598 case PCI_INTERRUPT_PIN_D: 3599 printf("(pin D)"); 3600 break; 3601 default: 3602 printf("(? ? ?)"); 3603 break; 3604 } 3605 printf("\n"); 3606 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 3607 & PCI_BRIDGE_CONTROL_MASK; 3608 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 3609 onoff("Parity error response", rval, 0x0001); 3610 onoff("Secondary SERR forwarding", rval, 0x0002); 3611 onoff("ISA enable", rval, 0x0004); 3612 onoff("VGA enable", rval, 0x0008); 3613 onoff("Master abort reporting", rval, 0x0020); 3614 onoff("Secondary bus reset", rval, 0x0040); 3615 onoff("Fast back-to-back capable", rval, 0x0080); 3616 } 3617 3618 static void 3619 pci_conf_print_type2( 3620 #ifdef _KERNEL 3621 pci_chipset_tag_t pc, pcitag_t tag, 3622 #endif 3623 const pcireg_t *regs 3624 #ifdef _KERNEL 3625 , int sizebars 3626 #endif 3627 ) 3628 { 3629 pcireg_t rval; 3630 3631 /* 3632 * XXX these need to be printed in more detail, need to be 3633 * XXX checked against specs/docs, etc. 3634 * 3635 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 3636 * controller chip documentation, and may not be correct with 3637 * respect to various standards. (XXX) 3638 */ 3639 3640 #ifdef _KERNEL 3641 pci_conf_print_bar(pc, tag, regs, 0x10, 3642 "CardBus socket/ExCA registers", sizebars); 3643 #else 3644 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 3645 #endif 3646 3647 /* Capability list pointer and secondary status register */ 3648 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 3649 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3650 printf(" Capability list pointer: 0x%02x\n", 3651 PCI_CAPLIST_PTR(rval)); 3652 else 3653 printf(" Reserved @ 0x14: 0x%04x\n", 3654 (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0))); 3655 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 3656 3657 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 3658 printf(" PCI bus number: 0x%02x\n", 3659 (rval >> 0) & 0xff); 3660 printf(" CardBus bus number: 0x%02x\n", 3661 (rval >> 8) & 0xff); 3662 printf(" Subordinate bus number: 0x%02x\n", 3663 (rval >> 16) & 0xff); 3664 printf(" CardBus latency timer: 0x%02x\n", 3665 (rval >> 24) & 0xff); 3666 3667 /* XXX Print more prettily */ 3668 printf(" CardBus memory region 0:\n"); 3669 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 3670 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 3671 printf(" CardBus memory region 1:\n"); 3672 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 3673 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 3674 printf(" CardBus I/O region 0:\n"); 3675 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 3676 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 3677 printf(" CardBus I/O region 1:\n"); 3678 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 3679 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 3680 3681 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3682 printf(" Interrupt line: 0x%02x\n", 3683 (rval >> 0) & 0xff); 3684 printf(" Interrupt pin: 0x%02x ", 3685 (rval >> 8) & 0xff); 3686 switch ((rval >> 8) & 0xff) { 3687 case PCI_INTERRUPT_PIN_NONE: 3688 printf("(none)"); 3689 break; 3690 case PCI_INTERRUPT_PIN_A: 3691 printf("(pin A)"); 3692 break; 3693 case PCI_INTERRUPT_PIN_B: 3694 printf("(pin B)"); 3695 break; 3696 case PCI_INTERRUPT_PIN_C: 3697 printf("(pin C)"); 3698 break; 3699 case PCI_INTERRUPT_PIN_D: 3700 printf("(pin D)"); 3701 break; 3702 default: 3703 printf("(? ? ?)"); 3704 break; 3705 } 3706 printf("\n"); 3707 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 3708 printf(" Bridge control register: 0x%04x\n", rval); 3709 onoff("Parity error response", rval, __BIT(0)); 3710 onoff("SERR# enable", rval, __BIT(1)); 3711 onoff("ISA enable", rval, __BIT(2)); 3712 onoff("VGA enable", rval, __BIT(3)); 3713 onoff("Master abort mode", rval, __BIT(5)); 3714 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 3715 onoff("Functional interrupts routed by ExCA registers", rval, 3716 __BIT(7)); 3717 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 3718 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 3719 onoff("Write posting enable", rval, __BIT(10)); 3720 3721 rval = regs[o2i(0x40)]; 3722 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 3723 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 3724 3725 #ifdef _KERNEL 3726 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 3727 sizebars); 3728 #else 3729 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 3730 #endif 3731 } 3732 3733 void 3734 pci_conf_print( 3735 #ifdef _KERNEL 3736 pci_chipset_tag_t pc, pcitag_t tag, 3737 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 3738 #else 3739 int pcifd, u_int bus, u_int dev, u_int func 3740 #endif 3741 ) 3742 { 3743 pcireg_t regs[o2i(PCI_EXTCONF_SIZE)]; 3744 int off, capoff, endoff, hdrtype; 3745 const char *type_name; 3746 #ifdef _KERNEL 3747 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, 3748 int); 3749 int sizebars; 3750 #else 3751 void (*type_printfn)(const pcireg_t *); 3752 #endif 3753 3754 printf("PCI configuration registers:\n"); 3755 3756 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 3757 #ifdef _KERNEL 3758 regs[o2i(off)] = pci_conf_read(pc, tag, off); 3759 #else 3760 if (pcibus_conf_read(pcifd, bus, dev, func, off, 3761 ®s[o2i(off)]) == -1) 3762 regs[o2i(off)] = 0; 3763 #endif 3764 } 3765 3766 #ifdef _KERNEL 3767 sizebars = 1; 3768 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 3769 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 3770 sizebars = 0; 3771 #endif 3772 3773 /* common header */ 3774 printf(" Common header:\n"); 3775 pci_conf_print_regs(regs, 0, 16); 3776 3777 printf("\n"); 3778 #ifdef _KERNEL 3779 pci_conf_print_common(pc, tag, regs); 3780 #else 3781 pci_conf_print_common(regs); 3782 #endif 3783 printf("\n"); 3784 3785 /* type-dependent header */ 3786 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 3787 switch (hdrtype) { /* XXX make a table, eventually */ 3788 case 0: 3789 /* Standard device header */ 3790 type_name = "\"normal\" device"; 3791 type_printfn = &pci_conf_print_type0; 3792 capoff = PCI_CAPLISTPTR_REG; 3793 endoff = 64; 3794 break; 3795 case 1: 3796 /* PCI-PCI bridge header */ 3797 type_name = "PCI-PCI bridge"; 3798 type_printfn = &pci_conf_print_type1; 3799 capoff = PCI_CAPLISTPTR_REG; 3800 endoff = 64; 3801 break; 3802 case 2: 3803 /* PCI-CardBus bridge header */ 3804 type_name = "PCI-CardBus bridge"; 3805 type_printfn = &pci_conf_print_type2; 3806 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 3807 endoff = 72; 3808 break; 3809 default: 3810 type_name = NULL; 3811 type_printfn = 0; 3812 capoff = -1; 3813 endoff = 64; 3814 break; 3815 } 3816 printf(" Type %d ", hdrtype); 3817 if (type_name != NULL) 3818 printf("(%s) ", type_name); 3819 printf("header:\n"); 3820 pci_conf_print_regs(regs, 16, endoff); 3821 printf("\n"); 3822 if (type_printfn) { 3823 #ifdef _KERNEL 3824 (*type_printfn)(pc, tag, regs, sizebars); 3825 #else 3826 (*type_printfn)(regs); 3827 #endif 3828 } else 3829 printf(" Don't know how to pretty-print type %d header.\n", 3830 hdrtype); 3831 printf("\n"); 3832 3833 /* capability list, if present */ 3834 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3835 && (capoff > 0)) { 3836 #ifdef _KERNEL 3837 pci_conf_print_caplist(pc, tag, regs, capoff); 3838 #else 3839 pci_conf_print_caplist(regs, capoff); 3840 #endif 3841 printf("\n"); 3842 } 3843 3844 /* device-dependent header */ 3845 printf(" Device-dependent header:\n"); 3846 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 3847 printf("\n"); 3848 #ifdef _KERNEL 3849 if (printfn) 3850 (*printfn)(pc, tag, regs); 3851 else 3852 printf(" Don't know how to pretty-print device-dependent header.\n"); 3853 printf("\n"); 3854 #endif /* _KERNEL */ 3855 3856 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 3857 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 3858 return; 3859 3860 #ifdef _KERNEL 3861 pci_conf_print_extcaplist(pc, tag, regs, capoff); 3862 #else 3863 pci_conf_print_extcaplist(regs, capoff); 3864 #endif 3865 printf("\n"); 3866 3867 /* Extended Configuration Space, if present */ 3868 printf(" Extended Configuration Space:\n"); 3869 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 3870 } 3871
Indexes created Tue Sep 23 23:09:58 GMT 2025