pci_subr.c revision 1.148
1 /* $NetBSD: pci_subr.c,v 1.148 2016/06/20 10:02:43 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.148 2016/06/20 10:02:43 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdbool.h> 58 #include <stdio.h> 59 #include <stdlib.h> 60 #include <string.h> 61 #endif 62 63 #include <dev/pci/pcireg.h> 64 #ifdef _KERNEL 65 #include <dev/pci/pcivar.h> 66 #else 67 #include <dev/pci/pci_verbose.h> 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcidevs_data.h> 70 #endif 71 72 /* 73 * Descriptions of known PCI classes and subclasses. 74 * 75 * Subclasses are described in the same way as classes, but have a 76 * NULL subclass pointer. 77 */ 78 struct pci_class { 79 const char *name; 80 u_int val; /* as wide as pci_{,sub}class_t */ 81 const struct pci_class *subclasses; 82 }; 83 84 /* 85 * Class 0x00. 86 * Before rev. 2.0. 87 */ 88 static const struct pci_class pci_subclass_prehistoric[] = { 89 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 90 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 91 { NULL, 0, NULL, }, 92 }; 93 94 /* 95 * Class 0x01. 96 * Mass storage controller 97 */ 98 99 /* ATA programming interface */ 100 static const struct pci_class pci_interface_ata[] = { 101 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 102 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 103 { NULL, 0, NULL, }, 104 }; 105 106 /* SATA programming interface */ 107 static const struct pci_class pci_interface_sata[] = { 108 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 109 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 110 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 111 { NULL, 0, NULL, }, 112 }; 113 114 /* Flash programming interface */ 115 static const struct pci_class pci_interface_nvm[] = { 116 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 117 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 118 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 119 { NULL, 0, NULL, }, 120 }; 121 122 /* Subclasses */ 123 static const struct pci_class pci_subclass_mass_storage[] = { 124 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 125 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 126 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 127 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 128 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 129 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 130 pci_interface_ata, }, 131 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 132 pci_interface_sata, }, 133 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 134 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 135 pci_interface_nvm, }, 136 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 137 { NULL, 0, NULL, }, 138 }; 139 140 /* 141 * Class 0x02. 142 * Network controller. 143 */ 144 static const struct pci_class pci_subclass_network[] = { 145 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 146 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 147 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 148 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 149 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 150 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 151 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 152 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 153 { NULL, 0, NULL, }, 154 }; 155 156 /* 157 * Class 0x03. 158 * Display controller. 159 */ 160 161 /* VGA programming interface */ 162 static const struct pci_class pci_interface_vga[] = { 163 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 164 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 165 { NULL, 0, NULL, }, 166 }; 167 /* Subclasses */ 168 static const struct pci_class pci_subclass_display[] = { 169 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 170 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 171 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 172 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 173 { NULL, 0, NULL, }, 174 }; 175 176 /* 177 * Class 0x04. 178 * Multimedia device. 179 */ 180 static const struct pci_class pci_subclass_multimedia[] = { 181 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 182 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 183 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 184 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 185 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 186 { NULL, 0, NULL, }, 187 }; 188 189 /* 190 * Class 0x05. 191 * Memory controller. 192 */ 193 static const struct pci_class pci_subclass_memory[] = { 194 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 195 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 196 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 197 { NULL, 0, NULL, }, 198 }; 199 200 /* 201 * Class 0x06. 202 * Bridge device. 203 */ 204 205 /* PCI bridge programming interface */ 206 static const struct pci_class pci_interface_pcibridge[] = { 207 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 208 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 209 { NULL, 0, NULL, }, 210 }; 211 212 /* Semi-transparent PCI-to-PCI bridge programming interface */ 213 static const struct pci_class pci_interface_stpci[] = { 214 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 215 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 216 { NULL, 0, NULL, }, 217 }; 218 219 /* Advanced Switching programming interface */ 220 static const struct pci_class pci_interface_advsw[] = { 221 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 222 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 223 { NULL, 0, NULL, }, 224 }; 225 226 /* Subclasses */ 227 static const struct pci_class pci_subclass_bridge[] = { 228 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 229 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 230 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 231 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 232 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 233 pci_interface_pcibridge, }, 234 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 235 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 236 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 237 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 238 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 239 pci_interface_stpci, }, 240 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 241 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 242 pci_interface_advsw, }, 243 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 244 { NULL, 0, NULL, }, 245 }; 246 247 /* 248 * Class 0x07. 249 * Simple communications controller. 250 */ 251 252 /* Serial controller programming interface */ 253 static const struct pci_class pci_interface_serial[] = { 254 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 255 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 256 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 257 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 258 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 259 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 260 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 261 { NULL, 0, NULL, }, 262 }; 263 264 /* Parallel controller programming interface */ 265 static const struct pci_class pci_interface_parallel[] = { 266 { "", PCI_INTERFACE_PARALLEL, NULL,}, 267 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 268 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 269 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 270 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 271 { NULL, 0, NULL,}, 272 }; 273 274 /* Modem programming interface */ 275 static const struct pci_class pci_interface_modem[] = { 276 { "", PCI_INTERFACE_MODEM, NULL,}, 277 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 278 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 279 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 280 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 281 { NULL, 0, NULL,}, 282 }; 283 284 /* Subclasses */ 285 static const struct pci_class pci_subclass_communications[] = { 286 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 287 pci_interface_serial, }, 288 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 289 pci_interface_parallel, }, 290 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 291 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 292 pci_interface_modem, }, 293 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 294 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 295 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 296 { NULL, 0, NULL,}, 297 }; 298 299 /* 300 * Class 0x08. 301 * Base system peripheral. 302 */ 303 304 /* PIC programming interface */ 305 static const struct pci_class pci_interface_pic[] = { 306 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 307 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 308 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 309 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 310 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 311 { NULL, 0, NULL, }, 312 }; 313 314 /* DMA programming interface */ 315 static const struct pci_class pci_interface_dma[] = { 316 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 317 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 318 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 319 { NULL, 0, NULL, }, 320 }; 321 322 /* Timer programming interface */ 323 static const struct pci_class pci_interface_tmr[] = { 324 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 325 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 326 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 327 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 328 { NULL, 0, NULL, }, 329 }; 330 331 /* RTC programming interface */ 332 static const struct pci_class pci_interface_rtc[] = { 333 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 334 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 335 { NULL, 0, NULL, }, 336 }; 337 338 /* Subclasses */ 339 static const struct pci_class pci_subclass_system[] = { 340 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 341 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 342 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 343 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 344 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 345 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 346 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 347 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 348 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 349 { NULL, 0, NULL, }, 350 }; 351 352 /* 353 * Class 0x09. 354 * Input device. 355 */ 356 357 /* Gameport programming interface */ 358 static const struct pci_class pci_interface_game[] = { 359 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 360 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 361 { NULL, 0, NULL, }, 362 }; 363 364 /* Subclasses */ 365 static const struct pci_class pci_subclass_input[] = { 366 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 367 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 368 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 369 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 370 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 371 pci_interface_game, }, 372 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 373 { NULL, 0, NULL, }, 374 }; 375 376 /* 377 * Class 0x0a. 378 * Docking station. 379 */ 380 static const struct pci_class pci_subclass_dock[] = { 381 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 382 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 383 { NULL, 0, NULL, }, 384 }; 385 386 /* 387 * Class 0x0b. 388 * Processor. 389 */ 390 static const struct pci_class pci_subclass_processor[] = { 391 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 392 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 393 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 394 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 395 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 396 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 397 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 398 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 399 { NULL, 0, NULL, }, 400 }; 401 402 /* 403 * Class 0x0c. 404 * Serial bus controller. 405 */ 406 407 /* IEEE1394 programming interface */ 408 static const struct pci_class pci_interface_ieee1394[] = { 409 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 410 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 411 { NULL, 0, NULL,}, 412 }; 413 414 /* USB programming interface */ 415 static const struct pci_class pci_interface_usb[] = { 416 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 417 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 418 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 419 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 420 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 421 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 422 { NULL, 0, NULL, }, 423 }; 424 425 /* IPMI programming interface */ 426 static const struct pci_class pci_interface_ipmi[] = { 427 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 428 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 429 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 430 { NULL, 0, NULL,}, 431 }; 432 433 /* Subclasses */ 434 static const struct pci_class pci_subclass_serialbus[] = { 435 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 436 pci_interface_ieee1394, }, 437 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 438 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 439 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 440 pci_interface_usb, }, 441 /* XXX Fiber Channel/_FIBRECHANNEL */ 442 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 443 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 444 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 445 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 446 pci_interface_ipmi, }, 447 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 448 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 449 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 450 { NULL, 0, NULL, }, 451 }; 452 453 /* 454 * Class 0x0d. 455 * Wireless Controller. 456 */ 457 static const struct pci_class pci_subclass_wireless[] = { 458 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 459 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 460 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 461 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 462 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 463 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 464 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 465 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 466 { NULL, 0, NULL, }, 467 }; 468 469 /* 470 * Class 0x0e. 471 * Intelligent IO controller. 472 */ 473 474 /* Intelligent IO programming interface */ 475 static const struct pci_class pci_interface_i2o[] = { 476 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 477 { NULL, 0, NULL,}, 478 }; 479 480 /* Subclasses */ 481 static const struct pci_class pci_subclass_i2o[] = { 482 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 483 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 484 { NULL, 0, NULL, }, 485 }; 486 487 /* 488 * Class 0x0f. 489 * Satellite communication controller. 490 */ 491 static const struct pci_class pci_subclass_satcom[] = { 492 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 493 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 494 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 495 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 496 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 497 { NULL, 0, NULL, }, 498 }; 499 500 /* 501 * Class 0x10. 502 * Encryption/Decryption controller. 503 */ 504 static const struct pci_class pci_subclass_crypto[] = { 505 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 506 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 507 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 508 { NULL, 0, NULL, }, 509 }; 510 511 /* 512 * Class 0x11. 513 * Data aquuisition and signal processing controller. 514 */ 515 static const struct pci_class pci_subclass_dasp[] = { 516 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 517 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 518 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 519 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 520 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 521 { NULL, 0, NULL, }, 522 }; 523 524 /* List of classes */ 525 static const struct pci_class pci_class[] = { 526 { "prehistoric", PCI_CLASS_PREHISTORIC, 527 pci_subclass_prehistoric, }, 528 { "mass storage", PCI_CLASS_MASS_STORAGE, 529 pci_subclass_mass_storage, }, 530 { "network", PCI_CLASS_NETWORK, 531 pci_subclass_network, }, 532 { "display", PCI_CLASS_DISPLAY, 533 pci_subclass_display, }, 534 { "multimedia", PCI_CLASS_MULTIMEDIA, 535 pci_subclass_multimedia, }, 536 { "memory", PCI_CLASS_MEMORY, 537 pci_subclass_memory, }, 538 { "bridge", PCI_CLASS_BRIDGE, 539 pci_subclass_bridge, }, 540 { "communications", PCI_CLASS_COMMUNICATIONS, 541 pci_subclass_communications, }, 542 { "system", PCI_CLASS_SYSTEM, 543 pci_subclass_system, }, 544 { "input", PCI_CLASS_INPUT, 545 pci_subclass_input, }, 546 { "dock", PCI_CLASS_DOCK, 547 pci_subclass_dock, }, 548 { "processor", PCI_CLASS_PROCESSOR, 549 pci_subclass_processor, }, 550 { "serial bus", PCI_CLASS_SERIALBUS, 551 pci_subclass_serialbus, }, 552 { "wireless", PCI_CLASS_WIRELESS, 553 pci_subclass_wireless, }, 554 { "I2O", PCI_CLASS_I2O, 555 pci_subclass_i2o, }, 556 { "satellite comm", PCI_CLASS_SATCOM, 557 pci_subclass_satcom, }, 558 { "crypto", PCI_CLASS_CRYPTO, 559 pci_subclass_crypto, }, 560 { "DASP", PCI_CLASS_DASP, 561 pci_subclass_dasp, }, 562 { "undefined", PCI_CLASS_UNDEFINED, 563 NULL, }, 564 { NULL, 0, 565 NULL, }, 566 }; 567 568 DEV_VERBOSE_DEFINE(pci); 569 570 void 571 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 572 size_t l) 573 { 574 pci_class_t pciclass; 575 pci_subclass_t subclass; 576 pci_interface_t interface; 577 pci_revision_t revision; 578 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 579 const struct pci_class *classp, *subclassp, *interfacep; 580 char *ep; 581 582 ep = cp + l; 583 584 pciclass = PCI_CLASS(class_reg); 585 subclass = PCI_SUBCLASS(class_reg); 586 interface = PCI_INTERFACE(class_reg); 587 revision = PCI_REVISION(class_reg); 588 589 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 590 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 591 PCI_PRODUCT(id_reg)); 592 593 classp = pci_class; 594 while (classp->name != NULL) { 595 if (pciclass == classp->val) 596 break; 597 classp++; 598 } 599 600 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 601 while (subclassp && subclassp->name != NULL) { 602 if (subclass == subclassp->val) 603 break; 604 subclassp++; 605 } 606 607 interfacep = (subclassp && subclassp->name != NULL) ? 608 subclassp->subclasses : NULL; 609 while (interfacep && interfacep->name != NULL) { 610 if (interface == interfacep->val) 611 break; 612 interfacep++; 613 } 614 615 cp += snprintf(cp, ep - cp, "%s %s", vendor, product); 616 if (showclass) { 617 cp += snprintf(cp, ep - cp, " ("); 618 if (classp->name == NULL) 619 cp += snprintf(cp, ep - cp, 620 "class 0x%02x, subclass 0x%02x", pciclass, subclass); 621 else { 622 if (subclassp == NULL || subclassp->name == NULL) 623 cp += snprintf(cp, ep - cp, 624 "%s, subclass 0x%02x", 625 classp->name, subclass); 626 else 627 cp += snprintf(cp, ep - cp, "%s %s", 628 subclassp->name, classp->name); 629 } 630 if ((interfacep == NULL) || (interfacep->name == NULL)) { 631 if (interface != 0) 632 cp += snprintf(cp, ep - cp, 633 ", interface 0x%02x", interface); 634 } else if (strncmp(interfacep->name, "", 1) != 0) 635 cp += snprintf(cp, ep - cp, ", %s", 636 interfacep->name); 637 if (revision != 0) 638 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 639 revision); 640 cp += snprintf(cp, ep - cp, ")"); 641 } 642 } 643 644 #ifdef _KERNEL 645 void 646 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 647 const char *known, int addrev) 648 { 649 char devinfo[256]; 650 651 if (known) { 652 aprint_normal(": %s", known); 653 if (addrev) 654 aprint_normal(" (rev. 0x%02x)", 655 PCI_REVISION(pa->pa_class)); 656 aprint_normal("\n"); 657 } else { 658 pci_devinfo(pa->pa_id, pa->pa_class, 0, 659 devinfo, sizeof(devinfo)); 660 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 661 PCI_REVISION(pa->pa_class)); 662 } 663 if (naive) 664 aprint_naive(": %s\n", naive); 665 else 666 aprint_naive("\n"); 667 } 668 #endif 669 670 /* 671 * Print out most of the PCI configuration registers. Typically used 672 * in a device attach routine like this: 673 * 674 * #ifdef MYDEV_DEBUG 675 * printf("%s: ", device_xname(sc->sc_dev)); 676 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 677 * #endif 678 */ 679 680 #define i2o(i) ((i) * 4) 681 #define o2i(o) ((o) / 4) 682 #define onoff2(str, rval, bit, onstr, offstr) \ 683 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 684 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 685 686 static void 687 pci_conf_print_common( 688 #ifdef _KERNEL 689 pci_chipset_tag_t pc, pcitag_t tag, 690 #endif 691 const pcireg_t *regs) 692 { 693 const char *name; 694 const struct pci_class *classp, *subclassp; 695 char vendor[PCI_VENDORSTR_LEN]; 696 char product[PCI_PRODUCTSTR_LEN]; 697 pcireg_t rval; 698 unsigned int num; 699 700 rval = regs[o2i(PCI_ID_REG)]; 701 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 702 if (name) 703 printf(" Vendor Name: %s (0x%04x)\n", name, 704 PCI_VENDOR(rval)); 705 else 706 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 707 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 708 PCI_PRODUCT(rval)); 709 if (name) 710 printf(" Device Name: %s (0x%04x)\n", name, 711 PCI_PRODUCT(rval)); 712 else 713 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 714 715 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 716 717 printf(" Command register: 0x%04x\n", rval & 0xffff); 718 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 719 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 720 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 721 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 722 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 723 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 724 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 725 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 726 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 727 onoff("Fast back-to-back transactions", rval, 728 PCI_COMMAND_BACKTOBACK_ENABLE); 729 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 730 731 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 732 onoff("Immediate Readness", rval, PCI_STATUS_IMMD_READNESS); 733 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 734 "inactive"); 735 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 736 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 737 onoff("User Definable Features (UDF) support", rval, 738 PCI_STATUS_UDF_SUPPORT); 739 onoff("Fast back-to-back capable", rval, 740 PCI_STATUS_BACKTOBACK_SUPPORT); 741 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 742 743 printf(" DEVSEL timing: "); 744 switch (rval & PCI_STATUS_DEVSEL_MASK) { 745 case PCI_STATUS_DEVSEL_FAST: 746 printf("fast"); 747 break; 748 case PCI_STATUS_DEVSEL_MEDIUM: 749 printf("medium"); 750 break; 751 case PCI_STATUS_DEVSEL_SLOW: 752 printf("slow"); 753 break; 754 default: 755 printf("unknown/reserved"); /* XXX */ 756 break; 757 } 758 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 759 760 onoff("Slave signaled Target Abort", rval, 761 PCI_STATUS_TARGET_TARGET_ABORT); 762 onoff("Master received Target Abort", rval, 763 PCI_STATUS_MASTER_TARGET_ABORT); 764 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 765 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 766 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 767 768 rval = regs[o2i(PCI_CLASS_REG)]; 769 for (classp = pci_class; classp->name != NULL; classp++) { 770 if (PCI_CLASS(rval) == classp->val) 771 break; 772 } 773 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 774 while (subclassp && subclassp->name != NULL) { 775 if (PCI_SUBCLASS(rval) == subclassp->val) 776 break; 777 subclassp++; 778 } 779 if (classp->name != NULL) { 780 printf(" Class Name: %s (0x%02x)\n", classp->name, 781 PCI_CLASS(rval)); 782 if (subclassp != NULL && subclassp->name != NULL) 783 printf(" Subclass Name: %s (0x%02x)\n", 784 subclassp->name, PCI_SUBCLASS(rval)); 785 else 786 printf(" Subclass ID: 0x%02x\n", 787 PCI_SUBCLASS(rval)); 788 } else { 789 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 790 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 791 } 792 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 793 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 794 795 rval = regs[o2i(PCI_BHLC_REG)]; 796 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 797 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 798 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 799 PCI_HDRTYPE(rval)); 800 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 801 num = PCI_CACHELINE(rval); 802 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 803 } 804 805 static int 806 pci_conf_print_bar( 807 #ifdef _KERNEL 808 pci_chipset_tag_t pc, pcitag_t tag, 809 #endif 810 const pcireg_t *regs, int reg, const char *name 811 #ifdef _KERNEL 812 , int sizebar 813 #endif 814 ) 815 { 816 int width; 817 pcireg_t rval, rval64h; 818 #ifdef _KERNEL 819 int s; 820 pcireg_t mask, mask64h; 821 #endif 822 823 width = 4; 824 825 /* 826 * Section 6.2.5.1, `Address Maps', tells us that: 827 * 828 * 1) The builtin software should have already mapped the 829 * device in a reasonable way. 830 * 831 * 2) A device which wants 2^n bytes of memory will hardwire 832 * the bottom n bits of the address to 0. As recommended, 833 * we write all 1s and see what we get back. 834 */ 835 836 rval = regs[o2i(reg)]; 837 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 838 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 839 rval64h = regs[o2i(reg + 4)]; 840 width = 8; 841 } else 842 rval64h = 0; 843 844 #ifdef _KERNEL 845 /* XXX don't size unknown memory type? */ 846 if (rval != 0 && sizebar) { 847 /* 848 * The following sequence seems to make some devices 849 * (e.g. host bus bridges, which don't normally 850 * have their space mapped) very unhappy, to 851 * the point of crashing the system. 852 * 853 * Therefore, if the mapping register is zero to 854 * start out with, don't bother trying. 855 */ 856 s = splhigh(); 857 pci_conf_write(pc, tag, reg, 0xffffffff); 858 mask = pci_conf_read(pc, tag, reg); 859 pci_conf_write(pc, tag, reg, rval); 860 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 861 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 862 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 863 mask64h = pci_conf_read(pc, tag, reg + 4); 864 pci_conf_write(pc, tag, reg + 4, rval64h); 865 } else 866 mask64h = 0; 867 splx(s); 868 } else 869 mask = mask64h = 0; 870 #endif /* _KERNEL */ 871 872 printf(" Base address register at 0x%02x", reg); 873 if (name) 874 printf(" (%s)", name); 875 printf("\n "); 876 if (rval == 0) { 877 printf("not implemented(?)\n"); 878 return width; 879 } 880 printf("type: "); 881 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 882 const char *type, *prefetch; 883 884 switch (PCI_MAPREG_MEM_TYPE(rval)) { 885 case PCI_MAPREG_MEM_TYPE_32BIT: 886 type = "32-bit"; 887 break; 888 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 889 type = "32-bit-1M"; 890 break; 891 case PCI_MAPREG_MEM_TYPE_64BIT: 892 type = "64-bit"; 893 break; 894 default: 895 type = "unknown (XXX)"; 896 break; 897 } 898 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 899 prefetch = ""; 900 else 901 prefetch = "non"; 902 printf("%s %sprefetchable memory\n", type, prefetch); 903 switch (PCI_MAPREG_MEM_TYPE(rval)) { 904 case PCI_MAPREG_MEM_TYPE_64BIT: 905 printf(" base: 0x%016llx, ", 906 PCI_MAPREG_MEM64_ADDR( 907 ((((long long) rval64h) << 32) | rval))); 908 #ifdef _KERNEL 909 if (sizebar) 910 printf("size: 0x%016llx", 911 PCI_MAPREG_MEM64_SIZE( 912 ((((long long) mask64h) << 32) | mask))); 913 else 914 #endif /* _KERNEL */ 915 printf("not sized"); 916 printf("\n"); 917 break; 918 case PCI_MAPREG_MEM_TYPE_32BIT: 919 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 920 default: 921 printf(" base: 0x%08x, ", 922 PCI_MAPREG_MEM_ADDR(rval)); 923 #ifdef _KERNEL 924 if (sizebar) 925 printf("size: 0x%08x", 926 PCI_MAPREG_MEM_SIZE(mask)); 927 else 928 #endif /* _KERNEL */ 929 printf("not sized"); 930 printf("\n"); 931 break; 932 } 933 } else { 934 #ifdef _KERNEL 935 if (sizebar) 936 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 937 #endif /* _KERNEL */ 938 printf("i/o\n"); 939 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 940 #ifdef _KERNEL 941 if (sizebar) 942 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 943 else 944 #endif /* _KERNEL */ 945 printf("not sized"); 946 printf("\n"); 947 } 948 949 return width; 950 } 951 952 static void 953 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 954 { 955 int off, needaddr, neednl; 956 957 needaddr = 1; 958 neednl = 0; 959 for (off = first; off < pastlast; off += 4) { 960 if ((off % 16) == 0 || needaddr) { 961 printf(" 0x%02x:", off); 962 needaddr = 0; 963 } 964 printf(" 0x%08x", regs[o2i(off)]); 965 neednl = 1; 966 if ((off % 16) == 12) { 967 printf("\n"); 968 neednl = 0; 969 } 970 } 971 if (neednl) 972 printf("\n"); 973 } 974 975 static void 976 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 977 { 978 pcireg_t rval; 979 980 printf("\n AGP Capabilities Register\n"); 981 982 rval = regs[o2i(capoff)]; 983 printf(" Revision: %d.%d\n", 984 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 985 986 /* XXX need more */ 987 } 988 989 static const char * 990 pci_conf_print_pcipm_cap_aux(uint16_t caps) 991 { 992 993 switch ((caps >> 6) & 7) { 994 case 0: return "self-powered"; 995 case 1: return "55 mA"; 996 case 2: return "100 mA"; 997 case 3: return "160 mA"; 998 case 4: return "220 mA"; 999 case 5: return "270 mA"; 1000 case 6: return "320 mA"; 1001 case 7: 1002 default: return "375 mA"; 1003 } 1004 } 1005 1006 static const char * 1007 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1008 { 1009 static const char unk[] = "unknown"; 1010 static const char *pmrev[8] = { 1011 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1012 }; 1013 if (val > 7) 1014 return unk; 1015 return pmrev[val]; 1016 } 1017 1018 static void 1019 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1020 { 1021 uint16_t caps, pmcsr; 1022 pcireg_t reg; 1023 1024 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1025 reg = regs[o2i(capoff + PCI_PMCSR)]; 1026 pmcsr = reg & 0xffff; 1027 1028 printf("\n PCI Power Management Capabilities Register\n"); 1029 1030 printf(" Capabilities register: 0x%04x\n", caps); 1031 printf(" Version: %s\n", 1032 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1033 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1034 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1035 printf(" 3.3V auxiliary current: %s\n", 1036 pci_conf_print_pcipm_cap_aux(caps)); 1037 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1038 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1039 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1040 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1041 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1042 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1043 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1044 1045 printf(" Control/status register: 0x%04x\n", pmcsr); 1046 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1047 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1048 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1049 printf(" PME# assertion: %sabled\n", 1050 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1051 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1052 printf(" Bridge Support Extensions register: 0x%02x\n", 1053 (reg >> 16) & 0xff); 1054 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1055 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1056 printf(" Data register: 0x%02x\n", (reg >> 24) & 0xff); 1057 1058 } 1059 1060 /* XXX pci_conf_print_vpd_cap */ 1061 /* XXX pci_conf_print_slotid_cap */ 1062 1063 static void 1064 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1065 { 1066 uint32_t ctl, mmc, mme; 1067 1068 regs += o2i(capoff); 1069 ctl = *regs++; 1070 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1071 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1072 1073 printf("\n PCI Message Signaled Interrupt\n"); 1074 1075 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1076 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1077 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1078 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1079 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1080 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1081 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1082 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1083 printf(" Message Address %sregister: 0x%08x\n", 1084 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1085 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1086 printf(" Message Address %sregister: 0x%08x\n", 1087 "(upper) ", *regs++); 1088 } 1089 printf(" Message Data register: 0x%08x\n", *regs++); 1090 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1091 printf(" Vector Mask register: 0x%08x\n", *regs++); 1092 printf(" Vector Pending register: 0x%08x\n", *regs++); 1093 } 1094 } 1095 1096 /* XXX pci_conf_print_cpci_hostwap_cap */ 1097 1098 /* 1099 * For both command register and status register. 1100 * The argument "idx" is index number (0 to 7). 1101 */ 1102 static int 1103 pcix_split_trans(unsigned int idx) 1104 { 1105 static int table[8] = { 1106 1, 2, 3, 4, 8, 12, 16, 32 1107 }; 1108 1109 if (idx >= __arraycount(table)) 1110 return -1; 1111 return table[idx]; 1112 } 1113 1114 static void 1115 pci_conf_print_pcix_cap_2ndbusmode(int num) 1116 { 1117 const char *maxfreq, *maxperiod; 1118 1119 printf(" Mode: "); 1120 if (num <= 0x07) 1121 printf("PCI-X Mode 1\n"); 1122 else if (num <= 0x0b) 1123 printf("PCI-X 266 (Mode 2)\n"); 1124 else 1125 printf("PCI-X 533 (Mode 2)\n"); 1126 1127 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1128 switch (num & 0x03) { 1129 default: 1130 case 0: 1131 maxfreq = "N/A"; 1132 maxperiod = "N/A"; 1133 break; 1134 case 1: 1135 maxfreq = "66MHz"; 1136 maxperiod = "15ns"; 1137 break; 1138 case 2: 1139 maxfreq = "100MHz"; 1140 maxperiod = "10ns"; 1141 break; 1142 case 3: 1143 maxfreq = "133MHz"; 1144 maxperiod = "7.5ns"; 1145 break; 1146 } 1147 printf(" Max Clock Freq: %s\n", maxfreq); 1148 printf(" Min Clock Period: %s\n", maxperiod); 1149 } 1150 1151 static void 1152 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1153 { 1154 pcireg_t reg; 1155 int isbridge; 1156 int i; 1157 1158 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1159 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1160 printf("\n PCI-X %s Capabilities Register\n", 1161 isbridge ? "Bridge" : "Non-bridge"); 1162 1163 reg = regs[o2i(capoff)]; 1164 if (isbridge != 0) { 1165 printf(" Secondary status register: 0x%04x\n", 1166 (reg & 0xffff0000) >> 16); 1167 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1168 onoff("133MHz capable", reg, PCIX_STATUS_133); 1169 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1170 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1171 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1172 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1173 pci_conf_print_pcix_cap_2ndbusmode( 1174 __SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1175 printf(" Version: 0x%x\n", 1176 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1177 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1178 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1179 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1180 } else { 1181 printf(" Command register: 0x%04x\n", 1182 (reg & 0xffff0000) >> 16); 1183 onoff("Data Parity Error Recovery", reg, 1184 PCIX_CMD_PERR_RECOVER); 1185 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1186 printf(" Maximum Burst Read Count: %u\n", 1187 PCIX_CMD_BYTECNT(reg)); 1188 printf(" Maximum Split Transactions: %d\n", 1189 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1190 >> PCIX_CMD_SPLTRANS_SHIFT)); 1191 } 1192 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1193 printf(" %sStatus register: 0x%08x\n", 1194 isbridge ? "Bridge " : "", reg); 1195 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1196 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1197 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1198 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1199 onoff("133MHz capable", reg, PCIX_STATUS_133); 1200 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1201 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1202 if (isbridge != 0) { 1203 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1204 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1205 } else { 1206 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1207 "bridge device", "simple device"); 1208 printf(" Designed max memory read byte count: %d\n", 1209 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1210 >> PCIX_STATUS_MAXB_SHIFT)); 1211 printf(" Designed max outstanding split transaction: %d\n", 1212 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1213 >> PCIX_STATUS_MAXST_SHIFT)); 1214 printf(" MAX cumulative Read Size: %u\n", 1215 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1216 onoff("Received split completion error", reg, 1217 PCIX_STATUS_SCERR); 1218 } 1219 onoff("266MHz capable", reg, PCIX_STATUS_266); 1220 onoff("533MHz capable", reg, PCIX_STATUS_533); 1221 1222 if (isbridge == 0) 1223 return; 1224 1225 /* Only for bridge */ 1226 for (i = 0; i < 2; i++) { 1227 reg = regs[o2i(capoff+PCIX_BRIDGE_UP_STCR + (4 * i))]; 1228 printf(" %s split transaction control register: 0x%08x\n", 1229 (i == 0) ? "Upstream" : "Downstream", reg); 1230 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1231 printf(" Commitment Limit: %d\n", 1232 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1233 } 1234 } 1235 1236 /* pci_conf_print_ht_slave_cap */ 1237 /* pci_conf_print_ht_host_cap */ 1238 /* pci_conf_print_ht_switch_cap */ 1239 /* pci_conf_print_ht_intr_cap */ 1240 /* pci_conf_print_ht_revid_cap */ 1241 /* pci_conf_print_ht_unitid_cap */ 1242 /* pci_conf_print_ht_extcnf_cap */ 1243 /* pci_conf_print_ht_addrmap_cap */ 1244 /* pci_conf_print_ht_msimap_cap */ 1245 1246 static void 1247 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1248 { 1249 pcireg_t val; 1250 uint32_t lo, hi; 1251 1252 /* 1253 * Print the rest of the command register bits. Others are 1254 * printed in pci_conf_print_ht_cap(). 1255 */ 1256 val = regs[o2i(capoff + PCI_HT_CMD)]; 1257 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1258 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1259 1260 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1261 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1262 printf(" Address Low register: 0x%08x\n", lo); 1263 printf(" Address high register: 0x%08x\n", hi); 1264 printf(" Address: 0x%016" PRIx64 "\n", 1265 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1266 } 1267 1268 /* pci_conf_print_ht_droute_cap */ 1269 /* pci_conf_print_ht_vcset_cap */ 1270 /* pci_conf_print_ht_retry_cap */ 1271 /* pci_conf_print_ht_x86enc_cap */ 1272 /* pci_conf_print_ht_gen3_cap */ 1273 /* pci_conf_print_ht_fle_cap */ 1274 /* pci_conf_print_ht_pm_cap */ 1275 /* pci_conf_print_ht_hnc_cap */ 1276 1277 static const struct ht_types { 1278 pcireg_t cap; 1279 const char *name; 1280 void (*printfunc)(const pcireg_t *, int); 1281 } ht_captab[] = { 1282 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1283 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1284 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1285 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1286 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1287 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1288 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1289 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1290 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1291 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1292 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1293 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1294 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1295 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1296 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1297 {PCI_HT_CAP_PM, "Power Management", NULL }, 1298 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1299 }; 1300 1301 static void 1302 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1303 { 1304 pcireg_t val, foundcap; 1305 unsigned int off; 1306 1307 val = regs[o2i(capoff + PCI_HT_CMD)]; 1308 1309 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1310 1311 printf(" Command register: 0x%04x\n", val >> 16); 1312 foundcap = PCI_HT_CAP(val); 1313 for (off = 0; off < __arraycount(ht_captab); off++) { 1314 if (ht_captab[off].cap == foundcap) 1315 break; 1316 } 1317 printf(" Capability Type: 0x%02x ", foundcap); 1318 if (off >= __arraycount(ht_captab)) { 1319 printf("(unknown)\n"); 1320 return; 1321 } 1322 printf("(%s)\n", ht_captab[off].name); 1323 if (ht_captab[off].printfunc != NULL) 1324 ht_captab[off].printfunc(regs, capoff); 1325 } 1326 1327 static void 1328 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1329 { 1330 uint16_t caps; 1331 1332 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1333 1334 printf("\n PCI Vendor Specific Capabilities Register\n"); 1335 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1336 } 1337 1338 static void 1339 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1340 { 1341 pcireg_t val; 1342 1343 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1344 1345 printf("\n Debugport Capability Register\n"); 1346 printf(" Debug base Register: 0x%04x\n", 1347 val >> PCI_DEBUG_BASER_SHIFT); 1348 printf(" port offset: 0x%04x\n", 1349 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1350 printf(" BAR number: %u\n", 1351 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1352 } 1353 1354 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1355 /* XXX pci_conf_print_hotplug_cap */ 1356 1357 static void 1358 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1359 { 1360 pcireg_t reg; 1361 1362 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1363 1364 printf("\n Subsystem ID Capability Register\n"); 1365 printf(" Subsystem ID : 0x%08x\n", reg); 1366 } 1367 1368 /* XXX pci_conf_print_agp8_cap */ 1369 /* XXX pci_conf_print_secure_cap */ 1370 1371 static void 1372 pci_print_pcie_L0s_latency(uint32_t val) 1373 { 1374 1375 switch (val) { 1376 case 0x0: 1377 printf("Less than 64ns\n"); 1378 break; 1379 case 0x1: 1380 case 0x2: 1381 case 0x3: 1382 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1383 break; 1384 case 0x4: 1385 printf("512ns to less than 1us\n"); 1386 break; 1387 case 0x5: 1388 printf("1us to less than 2us\n"); 1389 break; 1390 case 0x6: 1391 printf("2us - 4us\n"); 1392 break; 1393 case 0x7: 1394 printf("More than 4us\n"); 1395 break; 1396 } 1397 } 1398 1399 static void 1400 pci_print_pcie_L1_latency(uint32_t val) 1401 { 1402 1403 switch (val) { 1404 case 0x0: 1405 printf("Less than 1us\n"); 1406 break; 1407 case 0x6: 1408 printf("32us - 64us\n"); 1409 break; 1410 case 0x7: 1411 printf("More than 64us\n"); 1412 break; 1413 default: 1414 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1415 break; 1416 } 1417 } 1418 1419 static void 1420 pci_print_pcie_compl_timeout(uint32_t val) 1421 { 1422 1423 switch (val) { 1424 case 0x0: 1425 printf("50us to 50ms\n"); 1426 break; 1427 case 0x5: 1428 printf("16ms to 55ms\n"); 1429 break; 1430 case 0x6: 1431 printf("65ms to 210ms\n"); 1432 break; 1433 case 0x9: 1434 printf("260ms to 900ms\n"); 1435 break; 1436 case 0xa: 1437 printf("1s to 3.5s\n"); 1438 break; 1439 default: 1440 printf("unknown %u value\n", val); 1441 break; 1442 } 1443 } 1444 1445 static const char * const pcie_linkspeeds[] = {"2.5", "5.0", "8.0"}; 1446 1447 static void 1448 pci_print_pcie_linkspeed(pcireg_t val) 1449 { 1450 1451 /* Start from 1 */ 1452 if (val < 1 || val > __arraycount(pcie_linkspeeds)) 1453 printf("unknown value (%u)\n", val); 1454 else 1455 printf("%sGT/s\n", pcie_linkspeeds[val - 1]); 1456 } 1457 1458 static void 1459 pci_print_pcie_linkspeedvector(pcireg_t val) 1460 { 1461 unsigned int i; 1462 1463 /* Start from 0 */ 1464 for (i = 0; i < 16; i++) 1465 if (((val >> i) & 0x01) != 0) { 1466 if (i >= __arraycount(pcie_linkspeeds)) 1467 printf(" unknown vector (%x)", 1 << i); 1468 else 1469 printf(" %sGT/s", pcie_linkspeeds[i]); 1470 } 1471 } 1472 1473 static void 1474 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1475 { 1476 pcireg_t reg; /* for each register */ 1477 pcireg_t val; /* for each bitfield */ 1478 bool check_link = false; 1479 bool check_slot = false; 1480 bool check_rootport = false; 1481 unsigned int pciever; 1482 1483 printf("\n PCI Express Capabilities Register\n"); 1484 /* Capability Register */ 1485 reg = regs[o2i(capoff)]; 1486 printf(" Capability register: %04x\n", reg >> 16); 1487 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1488 printf(" Capability version: %u\n", pciever); 1489 printf(" Device type: "); 1490 switch ((reg & 0x00f00000) >> 20) { 1491 case 0x0: 1492 printf("PCI Express Endpoint device\n"); 1493 check_link = true; 1494 break; 1495 case 0x1: 1496 printf("Legacy PCI Express Endpoint device\n"); 1497 check_link = true; 1498 break; 1499 case 0x4: 1500 printf("Root Port of PCI Express Root Complex\n"); 1501 check_link = true; 1502 check_slot = true; 1503 check_rootport = true; 1504 break; 1505 case 0x5: 1506 printf("Upstream Port of PCI Express Switch\n"); 1507 break; 1508 case 0x6: 1509 printf("Downstream Port of PCI Express Switch\n"); 1510 check_slot = true; 1511 check_rootport = true; 1512 break; 1513 case 0x7: 1514 printf("PCI Express to PCI/PCI-X Bridge\n"); 1515 break; 1516 case 0x8: 1517 printf("PCI/PCI-X to PCI Express Bridge\n"); 1518 break; 1519 case 0x9: 1520 printf("Root Complex Integrated Endpoint\n"); 1521 break; 1522 case 0xa: 1523 check_rootport = true; 1524 printf("Root Complex Event Collector\n"); 1525 break; 1526 default: 1527 printf("unknown\n"); 1528 break; 1529 } 1530 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1531 printf(" Interrupt Message Number: %x\n", 1532 (unsigned int)((reg & PCIE_XCAP_IRQ) >> 27)); 1533 1534 /* Device Capability Register */ 1535 reg = regs[o2i(capoff + PCIE_DCAP)]; 1536 printf(" Device Capabilities Register: 0x%08x\n", reg); 1537 printf(" Max Payload Size Supported: %u bytes max\n", 1538 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1539 printf(" Phantom Functions Supported: "); 1540 switch ((reg & PCIE_DCAP_PHANTOM_FUNCS) >> 3) { 1541 case 0x0: 1542 printf("not available\n"); 1543 break; 1544 case 0x1: 1545 printf("MSB\n"); 1546 break; 1547 case 0x2: 1548 printf("two MSB\n"); 1549 break; 1550 case 0x3: 1551 printf("All three bits\n"); 1552 break; 1553 } 1554 printf(" Extended Tag Field Supported: %dbit\n", 1555 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1556 printf(" Endpoint L0 Acceptable Latency: "); 1557 pci_print_pcie_L0s_latency((reg & PCIE_DCAP_L0S_LATENCY) >> 6); 1558 printf(" Endpoint L1 Acceptable Latency: "); 1559 pci_print_pcie_L1_latency((reg & PCIE_DCAP_L1_LATENCY) >> 9); 1560 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1561 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1562 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1563 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1564 printf(" Captured Slot Power Limit Value: %d\n", 1565 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18); 1566 printf(" Captured Slot Power Limit Scale: %d\n", 1567 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26); 1568 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1569 1570 /* Device Control Register */ 1571 reg = regs[o2i(capoff + PCIE_DCSR)]; 1572 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1573 onoff("Correctable Error Reporting Enable", reg, 1574 PCIE_DCSR_ENA_COR_ERR); 1575 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1576 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1577 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1578 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1579 printf(" Max Payload Size: %d byte\n", 1580 128 << (((unsigned int)(reg & PCIE_DCSR_MAX_PAYLOAD) >> 5))); 1581 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1582 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1583 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1584 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1585 printf(" Max Read Request Size: %d byte\n", 1586 128 << ((unsigned int)(reg & PCIE_DCSR_MAX_READ_REQ) >> 12)); 1587 1588 /* Device Status Register */ 1589 reg = regs[o2i(capoff + PCIE_DCSR)]; 1590 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1591 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1592 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1593 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1594 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1595 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1596 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1597 1598 if (check_link) { 1599 /* Link Capability Register */ 1600 reg = regs[o2i(capoff + PCIE_LCAP)]; 1601 printf(" Link Capabilities Register: 0x%08x\n", reg); 1602 printf(" Maximum Link Speed: "); 1603 pci_print_pcie_linkspeed(reg & PCIE_LCAP_MAX_SPEED); 1604 printf(" Maximum Link Width: x%u lanes\n", 1605 (unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4); 1606 printf(" Active State PM Support: "); 1607 val = (reg & PCIE_LCAP_ASPM) >> 10; 1608 switch (val) { 1609 case 0x0: 1610 printf("No ASPM support\n"); 1611 break; 1612 case 0x1: 1613 printf("L0s supported\n"); 1614 break; 1615 case 0x2: 1616 printf("L1 supported\n"); 1617 break; 1618 case 0x3: 1619 printf("L0s and L1 supported\n"); 1620 break; 1621 } 1622 printf(" L0 Exit Latency: "); 1623 pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12); 1624 printf(" L1 Exit Latency: "); 1625 pci_print_pcie_L1_latency((reg & PCIE_LCAP_L1_EXIT) >> 15); 1626 printf(" Port Number: %u\n", reg >> 24); 1627 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1628 onoff("Surprise Down Error Report", reg, 1629 PCIE_LCAP_SURPRISE_DOWN); 1630 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1631 onoff("Link BW Notification Capable", reg, 1632 PCIE_LCAP_LINK_BW_NOTIFY); 1633 onoff("ASPM Optionally Compliance", reg, 1634 PCIE_LCAP_ASPM_COMPLIANCE); 1635 1636 /* Link Control Register */ 1637 reg = regs[o2i(capoff + PCIE_LCSR)]; 1638 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1639 printf(" Active State PM Control: "); 1640 val = reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S); 1641 switch (val) { 1642 case 0: 1643 printf("disabled\n"); 1644 break; 1645 case 1: 1646 printf("L0s Entry Enabled\n"); 1647 break; 1648 case 2: 1649 printf("L1 Entry Enabled\n"); 1650 break; 1651 case 3: 1652 printf("L0s and L1 Entry Enabled\n"); 1653 break; 1654 } 1655 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1656 "128bytes", "64bytes"); 1657 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1658 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1659 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1660 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1661 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1662 onoff("Hardware Autonomous Width Disable", reg, 1663 PCIE_LCSR_HAWD); 1664 onoff("Link Bandwidth Management Interrupt Enable", reg, 1665 PCIE_LCSR_LBMIE); 1666 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1667 PCIE_LCSR_LABIE); 1668 printf(" DRS Signaling Control: "); 1669 val = __SHIFTOUT(reg, PCIE_LCSR_DRSSGNL); 1670 switch (val) { 1671 case 0: 1672 printf("not reported\n"); 1673 break; 1674 case 1: 1675 printf("Interrupt Enabled\n"); 1676 break; 1677 case 2: 1678 printf("DRS to FRS Signaling Enabled\n"); 1679 break; 1680 default: 1681 printf("reserved\n"); 1682 break; 1683 } 1684 1685 /* Link Status Register */ 1686 reg = regs[o2i(capoff + PCIE_LCSR)]; 1687 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1688 printf(" Negotiated Link Speed: "); 1689 pci_print_pcie_linkspeed(__SHIFTOUT(reg, PCIE_LCSR_LINKSPEED)); 1690 printf(" Negotiated Link Width: x%u lanes\n", 1691 (reg >> 20) & 0x003f); 1692 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1693 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1694 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1695 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1696 onoff("Link Bandwidth Management Status", reg, 1697 PCIE_LCSR_LINK_BW_MGMT); 1698 onoff("Link Autonomous Bandwidth Status", reg, 1699 PCIE_LCSR_LINK_AUTO_BW); 1700 } 1701 1702 if (check_slot == true) { 1703 /* Slot Capability Register */ 1704 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1705 printf(" Slot Capability Register: %08x\n", reg); 1706 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1707 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1708 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1709 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1710 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1711 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1712 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1713 printf(" Slot Power Limit Value: %d\n", 1714 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1715 printf(" Slot Power Limit Scale: %d\n", 1716 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1717 onoff("Electromechanical Interlock Present", reg, 1718 PCIE_SLCAP_EIP); 1719 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1720 printf(" Physical Slot Number: %d\n", 1721 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1722 1723 /* Slot Control Register */ 1724 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1725 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1726 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1727 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1728 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1729 onoff("Presense Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1730 onoff("Command Completed Interrupt Enabled", reg, 1731 PCIE_SLCSR_CCE); 1732 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1733 printf(" Attention Indicator Control: "); 1734 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1735 case 0x0: 1736 printf("reserved\n"); 1737 break; 1738 case 0x1: 1739 printf("on\n"); 1740 break; 1741 case 0x2: 1742 printf("blink\n"); 1743 break; 1744 case 0x3: 1745 printf("off\n"); 1746 break; 1747 } 1748 printf(" Power Indicator Control: "); 1749 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1750 case 0x0: 1751 printf("reserved\n"); 1752 break; 1753 case 0x1: 1754 printf("on\n"); 1755 break; 1756 case 0x2: 1757 printf("blink\n"); 1758 break; 1759 case 0x3: 1760 printf("off\n"); 1761 break; 1762 } 1763 onoff("Power Controller Control", reg, PCIE_SLCSR_PCC); 1764 onoff("Electromechanical Interlock Control", 1765 reg, PCIE_SLCSR_EIC); 1766 onoff("Data Link Layer State Changed Enable", reg, 1767 PCIE_SLCSR_DLLSCE); 1768 onoff("Auto Slot Power Limit Disable", reg, 1769 PCIE_SLCSR_AUTOSPLDIS); 1770 1771 /* Slot Status Register */ 1772 printf(" Slot Status Register: %04x\n", reg >> 16); 1773 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1774 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1775 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1776 onoff("Presense Detect Changed", reg, PCIE_SLCSR_PDC); 1777 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1778 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1779 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1780 onoff("Electromechanical Interlock engaged", reg, 1781 PCIE_SLCSR_EIS); 1782 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 1783 } 1784 1785 if (check_rootport == true) { 1786 /* Root Control Register */ 1787 reg = regs[o2i(capoff + PCIE_RCR)]; 1788 printf(" Root Control Register: %04x\n", reg & 0xffff); 1789 onoff("SERR on Correctable Error Enable", reg, 1790 PCIE_RCR_SERR_CER); 1791 onoff("SERR on Non-Fatal Error Enable", reg, 1792 PCIE_RCR_SERR_NFER); 1793 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 1794 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 1795 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 1796 1797 /* Root Capability Register */ 1798 printf(" Root Capability Register: %04x\n", 1799 reg >> 16); 1800 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 1801 1802 /* Root Status Register */ 1803 reg = regs[o2i(capoff + PCIE_RSR)]; 1804 printf(" Root Status Register: %08x\n", reg); 1805 printf(" PME Requester ID: %04x\n", 1806 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1807 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 1808 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 1809 } 1810 1811 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1812 if (pciever < 2) 1813 return; 1814 1815 /* Device Capabilities 2 */ 1816 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1817 printf(" Device Capabilities 2: 0x%08x\n", reg); 1818 printf(" Completion Timeout Ranges Supported: %u \n", 1819 (unsigned int)(reg & PCIE_DCAP2_COMPT_RANGE)); 1820 onoff("Completion Timeout Disable Supported", reg, 1821 PCIE_DCAP2_COMPT_DIS); 1822 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 1823 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 1824 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 1825 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 1826 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 1827 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 1828 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 1829 printf(" TPH Completer Supported: %u\n", 1830 (unsigned int)(reg & PCIE_DCAP2_TPH_COMP) >> 12); 1831 printf(" LN System CLS: "); 1832 switch (__SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 1833 case 0x0: 1834 printf("Not supported or not in effect\n"); 1835 break; 1836 case 0x1: 1837 printf("64byte cachelines in effect\n"); 1838 break; 1839 case 0x2: 1840 printf("128byte cachelines in effect\n"); 1841 break; 1842 case 0x3: 1843 printf("Reserved\n"); 1844 break; 1845 } 1846 printf(" OBFF Supported: "); 1847 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 1848 case 0x0: 1849 printf("Not supported\n"); 1850 break; 1851 case 0x1: 1852 printf("Message only\n"); 1853 break; 1854 case 0x2: 1855 printf("WAKE# only\n"); 1856 break; 1857 case 0x3: 1858 printf("Both\n"); 1859 break; 1860 } 1861 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 1862 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 1863 printf(" Max End-End TLP Prefixes: %u\n", 1864 (unsigned int)(reg & PCIE_DCAP2_MAX_EETLP) >> 22); 1865 onoff("FRS Supported", reg, PCIE_DCAP2_FRS); 1866 1867 /* Device Control 2 */ 1868 reg = regs[o2i(capoff + PCIE_DCSR2)]; 1869 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 1870 printf(" Completion Timeout Value: "); 1871 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 1872 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 1873 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 1874 onoff("AtomicOp Rquester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 1875 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 1876 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 1877 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 1878 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 1879 printf(" OBFF: "); 1880 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 1881 case 0x0: 1882 printf("Disabled\n"); 1883 break; 1884 case 0x1: 1885 printf("Enabled with Message Signaling Variation A\n"); 1886 break; 1887 case 0x2: 1888 printf("Enabled with Message Signaling Variation B\n"); 1889 break; 1890 case 0x3: 1891 printf("Enabled using WAKE# signaling\n"); 1892 break; 1893 } 1894 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 1895 1896 if (check_link) { 1897 bool drs_supported; 1898 1899 /* Link Capability 2 */ 1900 reg = regs[o2i(capoff + PCIE_LCAP2)]; 1901 printf(" Link Capabilities 2: 0x%08x\n", reg); 1902 printf(" Supported Link Speed Vector:"); 1903 pci_print_pcie_linkspeedvector( 1904 __SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV)); 1905 printf("\n"); 1906 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 1907 printf(" Lower SKP OS Generation Supported Speed Vector:"); 1908 pci_print_pcie_linkspeedvector( 1909 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV)); 1910 printf("\n"); 1911 printf(" Lower SKP OS Reception Supported Speed Vector:"); 1912 pci_print_pcie_linkspeedvector( 1913 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV)); 1914 printf("\n"); 1915 onoff("DRS Supported", reg, PCIE_LCAP2_DRS); 1916 drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false; 1917 1918 /* Link Control 2 */ 1919 reg = regs[o2i(capoff + PCIE_LCSR2)]; 1920 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 1921 printf(" Target Link Speed: "); 1922 pci_print_pcie_linkspeed(__SHIFTOUT(reg, 1923 PCIE_LCSR2_TGT_LSPEED)); 1924 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 1925 onoff("HW Autonomous Speed Disabled", reg, 1926 PCIE_LCSR2_HW_AS_DIS); 1927 onoff("Selectable De-emphasis", reg, PCIE_LCSR2_SEL_DEEMP); 1928 printf(" Transmit Margin: %u\n", 1929 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 1930 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 1931 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 1932 printf(" Compliance Present/De-emphasis: %u\n", 1933 (unsigned int)(reg & PCIE_LCSR2_COMP_DEEMP) >> 12); 1934 1935 /* Link Status 2 */ 1936 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 1937 onoff("Current De-emphasis Level", reg, PCIE_LCSR2_DEEMP_LVL); 1938 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 1939 onoff("Equalization Phase 1 Successful", reg, 1940 PCIE_LCSR2_EQP1_SUC); 1941 onoff("Equalization Phase 2 Successful", reg, 1942 PCIE_LCSR2_EQP2_SUC); 1943 onoff("Equalization Phase 3 Successful", reg, 1944 PCIE_LCSR2_EQP3_SUC); 1945 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 1946 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD); 1947 if (drs_supported) { 1948 printf(" Downstream Component Presence: "); 1949 switch (__SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) { 1950 case PCIE_DSCOMPN_DOWN_NOTDETERM: 1951 printf("Link Down - Presence Not" 1952 " Determined\n"); 1953 break; 1954 case PCIE_DSCOMPN_DOWN_NOTPRES: 1955 printf("Link Down - Component Not Present\n"); 1956 break; 1957 case PCIE_DSCOMPN_DOWN_PRES: 1958 printf("Link Down - Component Present\n"); 1959 break; 1960 case PCIE_DSCOMPN_UP_PRES: 1961 printf("Link Up - Component Present\n"); 1962 break; 1963 case PCIE_DSCOMPN_UP_PRES_DRS: 1964 printf("Link Up - Component Present and DRS" 1965 " received\n"); 1966 break; 1967 default: 1968 printf("reserved\n"); 1969 break; 1970 } 1971 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV); 1972 } 1973 } 1974 1975 /* Slot Capability 2 */ 1976 /* Slot Control 2 */ 1977 /* Slot Status 2 */ 1978 } 1979 1980 static void 1981 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 1982 { 1983 pcireg_t reg; 1984 1985 printf("\n MSI-X Capability Register\n"); 1986 1987 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 1988 printf(" Message Control register: 0x%04x\n", 1989 (reg >> 16) & 0xff); 1990 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 1991 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 1992 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 1993 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 1994 printf(" Table offset register: 0x%08x\n", reg); 1995 printf(" Table offset: %08x\n", 1996 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 1997 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 1998 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 1999 printf(" Pending bit array register: 0x%08x\n", reg); 2000 printf(" Pending bit array offset: %08x\n", 2001 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 2002 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 2003 } 2004 2005 static void 2006 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 2007 { 2008 pcireg_t reg; 2009 2010 printf("\n Serial ATA Capability Register\n"); 2011 2012 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2013 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 2014 printf(" Revision: %u.%u\n", 2015 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 2016 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 2017 2018 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 2019 2020 printf(" BAR Register: 0x%08x\n", reg); 2021 printf(" Register location: "); 2022 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 2023 printf("in config space\n"); 2024 else { 2025 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 2026 printf(" BAR offset: 0x%08x\n", 2027 (pcireg_t)__SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 2028 } 2029 } 2030 2031 static void 2032 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 2033 { 2034 pcireg_t reg; 2035 2036 printf("\n Advanced Features Capability Register\n"); 2037 2038 reg = regs[o2i(capoff + PCI_AFCAPR)]; 2039 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 2040 printf(" AF Structure Length: 0x%02x\n", 2041 (pcireg_t)__SHIFTOUT(reg, PCI_AF_LENGTH)); 2042 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 2043 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 2044 reg = regs[o2i(capoff + PCI_AFCSR)]; 2045 printf(" AF Control register: 0x%02x\n", reg & 0xff); 2046 /* 2047 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 2048 * and it's always 0 on read 2049 */ 2050 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 2051 onoff("Transaction Pending", reg, PCI_AFSR_TP); 2052 } 2053 2054 static struct { 2055 pcireg_t cap; 2056 const char *name; 2057 void (*printfunc)(const pcireg_t *, int); 2058 } pci_captab[] = { 2059 { PCI_CAP_RESERVED0, "reserved", NULL }, 2060 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 2061 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 2062 { PCI_CAP_VPD, "VPD", NULL }, 2063 { PCI_CAP_SLOTID, "SlotID", NULL }, 2064 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 2065 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 2066 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2067 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2068 { PCI_CAP_VENDSPEC, "Vendor-specific", 2069 pci_conf_print_vendspec_cap }, 2070 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2071 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2072 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2073 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2074 pci_conf_print_subsystem_cap }, 2075 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2076 { PCI_CAP_SECURE, "Secure Device", NULL }, 2077 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2078 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2079 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2080 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2081 { PCI_CAP_EA, "Enhanced Allocation", NULL } 2082 }; 2083 2084 static int 2085 pci_conf_find_cap(const pcireg_t *regs, int capoff, unsigned int capid, 2086 int *offsetp) 2087 { 2088 pcireg_t rval; 2089 int off; 2090 2091 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2092 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2093 rval = regs[o2i(off)]; 2094 if (capid == PCI_CAPLIST_CAP(rval)) { 2095 if (offsetp != NULL) 2096 *offsetp = off; 2097 return 1; 2098 } 2099 } 2100 return 0; 2101 } 2102 2103 static void 2104 pci_conf_print_caplist( 2105 #ifdef _KERNEL 2106 pci_chipset_tag_t pc, pcitag_t tag, 2107 #endif 2108 const pcireg_t *regs, int capoff) 2109 { 2110 int off; 2111 pcireg_t foundcap; 2112 pcireg_t rval; 2113 bool foundtable[__arraycount(pci_captab)]; 2114 unsigned int i; 2115 2116 /* Clear table */ 2117 for (i = 0; i < __arraycount(pci_captab); i++) 2118 foundtable[i] = false; 2119 2120 /* Print capability register's offset and the type first */ 2121 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2122 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2123 rval = regs[o2i(off)]; 2124 printf(" Capability register at 0x%02x\n", off); 2125 2126 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2127 foundcap = PCI_CAPLIST_CAP(rval); 2128 if (foundcap < __arraycount(pci_captab)) { 2129 printf("%s)\n", pci_captab[foundcap].name); 2130 /* Mark as found */ 2131 foundtable[foundcap] = true; 2132 } else 2133 printf("unknown)\n"); 2134 } 2135 2136 /* 2137 * And then, print the detail of each capability registers 2138 * in capability value's order. 2139 */ 2140 for (i = 0; i < __arraycount(pci_captab); i++) { 2141 if (foundtable[i] == false) 2142 continue; 2143 2144 /* 2145 * The type was found. Search capability list again and 2146 * print all capabilities that the capabiliy type is 2147 * the same. This is required because some capabilities 2148 * appear multiple times (e.g. HyperTransport capability). 2149 */ 2150 #if 0 2151 if (pci_conf_find_cap(regs, capoff, i, &off)) { 2152 rval = regs[o2i(off)]; 2153 if (pci_captab[i].printfunc != NULL) 2154 pci_captab[i].printfunc(regs, off); 2155 } 2156 #else 2157 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2158 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2159 rval = regs[o2i(off)]; 2160 if ((PCI_CAPLIST_CAP(rval) == i) 2161 && (pci_captab[i].printfunc != NULL)) 2162 pci_captab[i].printfunc(regs, off); 2163 } 2164 #endif 2165 } 2166 } 2167 2168 /* Extended Capability */ 2169 2170 static void 2171 pci_conf_print_aer_cap_uc(pcireg_t reg) 2172 { 2173 2174 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2175 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2176 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2177 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP); 2178 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2179 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2180 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2181 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2182 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2183 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2184 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2185 onoff("Unsupported Request Error", reg, 2186 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2187 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2188 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2189 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2190 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2191 onoff("TLP Prefix Blocked Error", reg, 2192 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2193 onoff("Poisoned TLP Egress Blocked", reg, 2194 PCI_AER_UC_POISONTLP_EGRESS_BLOCKED); 2195 } 2196 2197 static void 2198 pci_conf_print_aer_cap_cor(pcireg_t reg) 2199 { 2200 2201 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2202 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2203 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2204 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2205 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2206 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2207 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2208 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2209 } 2210 2211 static void 2212 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2213 { 2214 2215 printf(" First Error Pointer: 0x%04x\n", 2216 (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2217 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2218 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2219 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2220 onoff("ECRC Check Enab", reg, PCI_AER_ECRC_CHECK_ENABLE); 2221 onoff("Multiple Header Recording Capable", reg, 2222 PCI_AER_MULT_HDR_CAPABLE); 2223 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE); 2224 onoff("Completion Timeout Prefix/Header Log Capable", reg, 2225 PCI_AER_COMPTOUTPRFXHDRLOG_CAP); 2226 2227 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2228 if (!tlp_prefix_log) 2229 return; 2230 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2231 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2232 } 2233 2234 static void 2235 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2236 { 2237 2238 onoff("Correctable Error Reporting Enable", reg, 2239 PCI_AER_ROOTERR_COR_ENABLE); 2240 onoff("Non-Fatal Error Reporting Enable", reg, 2241 PCI_AER_ROOTERR_NF_ENABLE); 2242 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2243 } 2244 2245 static void 2246 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2247 { 2248 2249 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2250 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2251 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2252 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2253 PCI_AER_ROOTERR_MULTI_UC_ERR); 2254 onoff("First Uncorrectable Fatal", reg, PCI_AER_ROOTERR_FIRST_UC_FATAL); 2255 onoff("Non-Fatal Error Messages Received", reg, PCI_AER_ROOTERR_NF_ERR); 2256 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2257 printf(" Advanced Error Interrupt Message Number: 0x%u\n", 2258 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2259 } 2260 2261 static void 2262 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2263 { 2264 2265 printf(" Correctable Source ID: 0x%04x\n", 2266 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2267 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2268 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2269 } 2270 2271 static void 2272 pci_conf_print_aer_cap(const pcireg_t *regs, int capoff, int extcapoff) 2273 { 2274 pcireg_t reg; 2275 int pcie_capoff; 2276 int pcie_devtype = -1; 2277 bool tlp_prefix_log = false; 2278 2279 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2280 reg = regs[o2i(pcie_capoff)]; 2281 pcie_devtype = PCIE_XCAP_TYPE(reg); 2282 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2283 if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2284 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2285 /* End-End TLP Prefix Supported */ 2286 if (reg & PCIE_DCAP2_EETLP_PREF) { 2287 tlp_prefix_log = true; 2288 } 2289 } 2290 } 2291 2292 printf("\n Advanced Error Reporting Register\n"); 2293 2294 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2295 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2296 pci_conf_print_aer_cap_uc(reg); 2297 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2298 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2299 pci_conf_print_aer_cap_uc(reg); 2300 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2301 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2302 pci_conf_print_aer_cap_uc(reg); 2303 2304 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2305 printf(" Correctable Error Status register: 0x%08x\n", reg); 2306 pci_conf_print_aer_cap_cor(reg); 2307 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2308 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2309 pci_conf_print_aer_cap_cor(reg); 2310 2311 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2312 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2313 reg); 2314 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2315 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2316 printf(" Header Log register:\n"); 2317 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2318 extcapoff + PCI_AER_ROOTERR_CMD); 2319 2320 switch (pcie_devtype) { 2321 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ 2322 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ 2323 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2324 printf(" Root Error Command register: 0x%08x\n", reg); 2325 pci_conf_print_aer_cap_rooterr_cmd(reg); 2326 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2327 printf(" Root Error Status register: 0x%08x\n", reg); 2328 pci_conf_print_aer_cap_rooterr_status(reg); 2329 2330 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2331 printf(" Error Source Identification: 0x%04x\n", reg); 2332 pci_conf_print_aer_cap_errsrc_id(reg); 2333 break; 2334 } 2335 2336 if (tlp_prefix_log) { 2337 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2338 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2339 } 2340 } 2341 2342 static void 2343 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2344 pcireg_t parbsel, int parbsize) 2345 { 2346 pcireg_t reg; 2347 int num = 16 << parbsel; 2348 int num_per_reg = sizeof(pcireg_t) / parbsize; 2349 int i, j; 2350 2351 /* First, dump the table */ 2352 for (i = 0; i < num; i += num_per_reg) { 2353 reg = regs[o2i(off + i / num_per_reg)]; 2354 printf(" %s Arbitration Table: 0x%08x\n", name, reg); 2355 } 2356 /* And then, decode each entry */ 2357 for (i = 0; i < num; i += num_per_reg) { 2358 reg = regs[o2i(off + i / num_per_reg)]; 2359 for (j = 0; j < num_per_reg; j++) 2360 printf(" Phase[%d]: %d\n", j, reg); 2361 } 2362 } 2363 2364 static void 2365 pci_conf_print_vc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2366 { 2367 pcireg_t reg, n; 2368 int parbtab, parbsize; 2369 pcireg_t parbsel; 2370 int varbtab, varbsize; 2371 pcireg_t varbsel; 2372 int i, count; 2373 2374 printf("\n Virtual Channel Register\n"); 2375 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2376 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2377 count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2378 printf(" Extended VC Count: %d\n", count); 2379 n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2380 printf(" Low Priority Extended VC Count: %u\n", n); 2381 n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2382 printf(" Reference Clock: %s\n", 2383 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 2384 parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2385 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2386 2387 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 2388 printf(" Port VC Capability register 2: 0x%08x\n", reg); 2389 onoff("Hardware fixed arbitration scheme", 2390 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 2391 onoff("WRR arbitration with 32 phases", 2392 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 2393 onoff("WRR arbitration with 64 phases", 2394 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 2395 onoff("WRR arbitration with 128 phases", 2396 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 2397 varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 2398 printf(" VC Arbitration Table Offset: 0x%x\n", varbtab); 2399 2400 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 2401 printf(" Port VC Control register: 0x%04x\n", reg); 2402 varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 2403 printf(" VC Arbitration Select: 0x%x\n", varbsel); 2404 2405 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 2406 printf(" Port VC Status register: 0x%04x\n", reg); 2407 onoff("VC Arbitration Table Status", 2408 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 2409 2410 for (i = 0; i < count + 1; i++) { 2411 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 2412 printf(" VC number %d\n", i); 2413 printf(" VC Resource Capability Register: 0x%08x\n", reg); 2414 onoff(" Non-configurable Hardware fixed arbitration scheme", 2415 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 2416 onoff(" WRR arbitration with 32 phases", 2417 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 2418 onoff(" WRR arbitration with 64 phases", 2419 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 2420 onoff(" WRR arbitration with 128 phases", 2421 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 2422 onoff(" Time-based WRR arbitration with 128 phases", 2423 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 2424 onoff(" WRR arbitration with 256 phases", 2425 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 2426 onoff(" Advanced Packet Switching", 2427 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 2428 onoff(" Reject Snoop Transaction", 2429 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 2430 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 2431 printf(" Maximum Time Slots: %d\n", n); 2432 parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S; 2433 printf(" Port Arbitration Table offset: 0x%02x\n", 2434 parbtab); 2435 2436 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 2437 printf(" VC Resource Control Register: 0x%08x\n", reg); 2438 printf(" TC/VC Map: %02x\n", 2439 (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 2440 /* 2441 * The load Port Arbitration Table bit is used to update 2442 * the Port Arbitration logic and it's always 0 on read, so 2443 * we don't print it. 2444 */ 2445 parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 2446 printf(" Port Arbitration Select: %x\n", parbsel); 2447 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 2448 printf(" VC ID %d\n", n); 2449 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 2450 2451 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 2452 printf(" VC Resource Status Register: 0x%08x\n", reg); 2453 onoff(" Port Arbitration Table Status", 2454 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 2455 onoff(" VC Negotiation Pending", 2456 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 2457 2458 if ((parbtab != 0) && (parbsel != 0)) 2459 pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab, 2460 "Port", parbsel, parbsize); 2461 } 2462 2463 varbsize = 8; 2464 if ((varbtab != 0) && (varbsel != 0)) 2465 pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab, 2466 " VC", varbsel, varbsize); 2467 } 2468 2469 static const char * 2470 pci_conf_print_pwrbdgt_base_power(uint8_t reg) 2471 { 2472 2473 switch (reg) { 2474 case 0xf0: 2475 return "239W < x <= 250W"; 2476 case 0xf1: 2477 return "250W < x <= 275W"; 2478 case 0xf2: 2479 return "275W < x <= 300W"; 2480 default: 2481 return "Unknown"; 2482 } 2483 } 2484 2485 static const char * 2486 pci_conf_print_pwrbdgt_data_scale(uint8_t reg) 2487 { 2488 2489 switch (reg) { 2490 case 0x00: 2491 return "1.0x"; 2492 case 0x01: 2493 return "0.1x"; 2494 case 0x02: 2495 return "0.01x"; 2496 case 0x03: 2497 return "0.001x"; 2498 default: 2499 return "wrong value!"; 2500 } 2501 } 2502 2503 static const char * 2504 pci_conf_print_pwrbdgt_type(uint8_t reg) 2505 { 2506 2507 switch (reg) { 2508 case 0x00: 2509 return "PME Aux"; 2510 case 0x01: 2511 return "Auxilary"; 2512 case 0x02: 2513 return "Idle"; 2514 case 0x03: 2515 return "Sustained"; 2516 case 0x07: 2517 return "Maximun"; 2518 default: 2519 return "Unknown"; 2520 } 2521 } 2522 2523 static const char * 2524 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 2525 { 2526 2527 switch (reg) { 2528 case 0x00: 2529 return "Power(12V)"; 2530 case 0x01: 2531 return "Power(3.3V)"; 2532 case 0x02: 2533 return "Power(1.5V or 1.8V)"; 2534 case 0x07: 2535 return "Thermal"; 2536 default: 2537 return "Unknown"; 2538 } 2539 } 2540 2541 static void 2542 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff) 2543 { 2544 pcireg_t reg; 2545 2546 printf("\n Power Budget Register\n"); 2547 2548 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 2549 printf(" Data Select register: 0x%08x\n", reg); 2550 2551 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 2552 printf(" Data register: 0x%08x\n", reg); 2553 printf(" Base Power: %s\n", 2554 pci_conf_print_pwrbdgt_base_power((uint8_t)reg)); 2555 printf(" Data Scale: %s\n", 2556 pci_conf_print_pwrbdgt_data_scale( 2557 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE)))); 2558 printf(" PM Sub State: 0x%hhx\n", 2559 (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 2560 printf(" PM State: D%u\n", 2561 (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 2562 printf(" Type: %s\n", 2563 pci_conf_print_pwrbdgt_type( 2564 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 2565 printf(" Power Rail: %s\n", 2566 pci_conf_print_pwrbdgt_pwrrail( 2567 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 2568 2569 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 2570 printf(" Power Budget Capability register: 0x%08x\n", reg); 2571 onoff("System Allocated", 2572 reg, PCI_PWRBDGT_CAP_SYSALLOC); 2573 } 2574 2575 static const char * 2576 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 2577 { 2578 2579 switch (type) { 2580 case 0x00: 2581 return "Configuration Space Element"; 2582 case 0x01: 2583 return "System Egress Port or internal sink (memory)"; 2584 case 0x02: 2585 return "Internal Root Complex Link"; 2586 default: 2587 return "Unknown"; 2588 } 2589 } 2590 2591 static void 2592 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int capoff, int extcapoff) 2593 { 2594 pcireg_t reg; 2595 unsigned char nent, linktype; 2596 int i; 2597 2598 printf("\n Root Complex Link Declaration\n"); 2599 2600 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 2601 printf(" Element Self Description Register: 0x%08x\n", reg); 2602 printf(" Element Type: %s\n", 2603 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 2604 nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 2605 printf(" Number of Link Entries: %hhu\n", nent); 2606 printf(" Component ID: %hhu\n", 2607 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 2608 printf(" Port Number: %hhu\n", 2609 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 2610 for (i = 0; i < nent; i++) { 2611 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 2612 printf(" Link Entry %d:\n", i + 1); 2613 printf(" Link Description Register: 0x%08x\n", reg); 2614 onoff(" Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID); 2615 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 2616 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 2617 "Configuration Space", "Memory-Mapped Space"); 2618 onoff(" Associated RCRB Header", reg, 2619 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 2620 printf(" Target Component ID: %hhu\n", 2621 (unsigned char)__SHIFTOUT(reg, 2622 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 2623 printf(" Target Port Number: %hhu\n", 2624 (unsigned char)__SHIFTOUT(reg, 2625 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 2626 2627 if (linktype == 0) { 2628 /* Memory-Mapped Space */ 2629 reg = regs[o2i(extcapoff 2630 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 2631 printf(" Link Address Low Register: 0x%08x\n", 2632 reg); 2633 reg = regs[o2i(extcapoff 2634 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 2635 printf(" Link Address High Register: 0x%08x\n", 2636 reg); 2637 } else { 2638 unsigned int nb; 2639 pcireg_t lo, hi; 2640 2641 /* Configuration Space */ 2642 lo = regs[o2i(extcapoff 2643 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 2644 printf(" Configuration Space Low Register: " 2645 "0x%08x\n", lo); 2646 hi = regs[o2i(extcapoff 2647 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 2648 printf(" Configuration Space High Register: " 2649 "0x%08x\n", hi); 2650 nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 2651 printf(" N: %u\n", nb); 2652 printf(" Func: %hhu\n", 2653 (unsigned char)__SHIFTOUT(lo, 2654 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 2655 printf(" Dev: %hhu\n", 2656 (unsigned char)__SHIFTOUT(lo, 2657 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 2658 printf(" Bus: %hhu\n", 2659 (unsigned char)__SHIFTOUT(lo, 2660 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 2661 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 2662 printf(" Configuration Space Base Address: " 2663 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 2664 } 2665 } 2666 } 2667 2668 /* XXX pci_conf_print_rclink_ctl_cap */ 2669 2670 static void 2671 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2672 { 2673 pcireg_t reg; 2674 2675 printf("\n Root Complex Event Collector Association\n"); 2676 2677 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 2678 printf(" Association Bitmap for Root Complex Integrated Devices:" 2679 " 0x%08x\n", reg); 2680 } 2681 2682 /* XXX pci_conf_print_mfvc_cap */ 2683 /* XXX pci_conf_print_vc2_cap */ 2684 /* XXX pci_conf_print_rcrb_cap */ 2685 /* XXX pci_conf_print_vendor_cap */ 2686 /* XXX pci_conf_print_cac_cap */ 2687 2688 static void 2689 pci_conf_print_acs_cap(const pcireg_t *regs, int capoff, int extcapoff) 2690 { 2691 pcireg_t reg, cap, ctl; 2692 unsigned int size, i; 2693 2694 printf("\n Access Control Services\n"); 2695 2696 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 2697 cap = reg & 0xffff; 2698 ctl = reg >> 16; 2699 printf(" ACS Capability register: 0x%08x\n", cap); 2700 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 2701 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 2702 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 2703 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 2704 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 2705 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 2706 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 2707 size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 2708 if (size == 0) 2709 size = 256; 2710 printf(" Egress Control Vector Size: %u\n", size); 2711 printf(" ACS Control register: 0x%08x\n", ctl); 2712 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 2713 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 2714 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 2715 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 2716 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 2717 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 2718 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 2719 2720 /* 2721 * If the P2P Egress Control Capability bit is 0, ignore the Egress 2722 * Control vector. 2723 */ 2724 if ((cap & PCI_ACS_CAP_E) == 0) 2725 return; 2726 for (i = 0; i < size; i += 32) 2727 printf(" Egress Control Vector [%u..%u]: %x\n", i + 31, 2728 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 2729 } 2730 2731 static void 2732 pci_conf_print_ari_cap(const pcireg_t *regs, int capoff, int extcapoff) 2733 { 2734 pcireg_t reg, cap, ctl; 2735 2736 printf("\n Alternative Routing-ID Interpretation Register\n"); 2737 2738 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2739 cap = reg & 0xffff; 2740 ctl = reg >> 16; 2741 printf(" Capability register: 0x%08x\n", cap); 2742 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 2743 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 2744 printf(" Next Function Number: %u\n", 2745 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 2746 printf(" Control register: 0x%08x\n", ctl); 2747 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 2748 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 2749 printf(" Function Group: %u\n", 2750 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 2751 } 2752 2753 static void 2754 pci_conf_print_ats_cap(const pcireg_t *regs, int capoff, int extcapoff) 2755 { 2756 pcireg_t reg, cap, ctl; 2757 unsigned int num; 2758 2759 printf("\n Address Translation Services\n"); 2760 2761 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2762 cap = reg & 0xffff; 2763 ctl = reg >> 16; 2764 printf(" Capability register: 0x%04x\n", cap); 2765 num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 2766 if (num == 0) 2767 num = 32; 2768 printf(" Invalidate Queue Depth: %u\n", num); 2769 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 2770 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 2771 2772 printf(" Control register: 0x%04x\n", ctl); 2773 printf(" Smallest Translation Unit: %u\n", 2774 (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU)); 2775 onoff("Enable", reg, PCI_ATS_CTL_EN); 2776 } 2777 2778 static void 2779 pci_conf_print_sernum_cap(const pcireg_t *regs, int capoff, int extcapoff) 2780 { 2781 pcireg_t lo, hi; 2782 2783 printf("\n Device Serial Number Register\n"); 2784 2785 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 2786 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 2787 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 2788 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 2789 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 2790 } 2791 2792 static void 2793 pci_conf_print_sriov_cap(const pcireg_t *regs, int capoff, int extcapoff) 2794 { 2795 char buf[sizeof("99999 MB")]; 2796 pcireg_t reg; 2797 pcireg_t total_vfs; 2798 int i; 2799 bool first; 2800 2801 printf("\n Single Root IO Virtualization Register\n"); 2802 2803 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 2804 printf(" Capabilities register: 0x%08x\n", reg); 2805 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 2806 onoff("ARI Capable Hierarchy Preserved", reg, 2807 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 2808 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 2809 printf(" VF Migration Interrupt Message Number: 0x%u\n", 2810 (pcireg_t)__SHIFTOUT(reg, 2811 PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 2812 } 2813 2814 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 2815 printf(" Control register: 0x%04x\n", reg); 2816 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 2817 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 2818 onoff("VF Migration Interrupt Enable", reg, 2819 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 2820 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 2821 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 2822 2823 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 2824 printf(" Status register: 0x%04x\n", reg); 2825 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 2826 2827 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 2828 printf(" InitialVFs register: 0x%04x\n", reg); 2829 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 2830 printf(" TotalVFs register: 0x%04x\n", reg); 2831 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 2832 printf(" NumVFs register: 0x%04x\n", reg); 2833 2834 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 2835 printf(" Function Dependency Link register: 0x%04x\n", reg); 2836 2837 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 2838 printf(" First VF Offset register: 0x%04x\n", reg); 2839 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 2840 printf(" VF Stride register: 0x%04x\n", reg); 2841 2842 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 2843 printf(" Supported Page Sizes register: 0x%08x\n", reg); 2844 printf(" Supported Page Size:"); 2845 for (i = 0, first = true; i < 32; i++) { 2846 if (reg & __BIT(i)) { 2847 #ifdef _KERNEL 2848 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 2849 #else 2850 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 2851 HN_AUTOSCALE, 0); 2852 #endif 2853 printf("%s %s", first ? "" : ",", buf); 2854 first = false; 2855 } 2856 } 2857 printf("\n"); 2858 2859 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 2860 printf(" System Page Sizes register: 0x%08x\n", reg); 2861 printf(" Page Size: "); 2862 if (reg != 0) { 2863 #ifdef _KERNEL 2864 format_bytes(buf, sizeof(buf), 1LL << (ffs(reg) + 12)); 2865 #else 2866 humanize_number(buf, sizeof(buf), 1LL << (ffs(reg) + 12), "B", 2867 HN_AUTOSCALE, 0); 2868 #endif 2869 printf("%s", buf); 2870 } else { 2871 printf("unknown"); 2872 } 2873 printf("\n"); 2874 2875 for (i = 0; i < 6; i++) { 2876 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 2877 printf(" VF BAR%d register: 0x%08x\n", i, reg); 2878 } 2879 2880 if (total_vfs > 0) { 2881 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 2882 printf(" VF Migration State Array Offset register: 0x%08x\n", 2883 reg); 2884 printf(" VF Migration State Offset: 0x%08x\n", 2885 (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 2886 i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 2887 printf(" VF Migration State BIR: "); 2888 if (i >= 0 && i <= 5) { 2889 printf("BAR%d", i); 2890 } else { 2891 printf("unknown BAR (%d)", i); 2892 } 2893 printf("\n"); 2894 } 2895 } 2896 2897 /* XXX pci_conf_print_mriov_cap */ 2898 2899 static void 2900 pci_conf_print_multicast_cap(const pcireg_t *regs, int capoff, int extcapoff) 2901 { 2902 pcireg_t reg, cap, ctl; 2903 pcireg_t regl, regh; 2904 uint64_t addr; 2905 int n; 2906 2907 printf("\n Multicast\n"); 2908 2909 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 2910 cap = reg & 0xffff; 2911 ctl = reg >> 16; 2912 printf(" Capability Register: 0x%04x\n", cap); 2913 printf(" Max Group: %u\n", 2914 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 2915 2916 /* Endpoint Only */ 2917 n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 2918 if (n > 0) 2919 printf(" Windw Size Requested: %d\n", 1 << (n - 1)); 2920 2921 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 2922 2923 printf(" Control Register: 0x%04x\n", ctl); 2924 printf(" Num Group: %u\n", 2925 (unsigned int)__SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 2926 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 2927 2928 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 2929 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 2930 printf(" Base Address Register 0: 0x%08x\n", regl); 2931 printf(" Base Address Register 1: 0x%08x\n", regh); 2932 printf(" Index Position: %u\n", 2933 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 2934 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 2935 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 2936 2937 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 2938 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 2939 printf(" Receive Register 0: 0x%08x\n", regl); 2940 printf(" Receive Register 1: 0x%08x\n", regh); 2941 2942 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 2943 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 2944 printf(" Block All Register 0: 0x%08x\n", regl); 2945 printf(" Block All Register 1: 0x%08x\n", regh); 2946 2947 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 2948 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 2949 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 2950 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 2951 2952 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 2953 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 2954 printf(" Overlay BAR 0: 0x%08x\n", regl); 2955 printf(" Overlay BAR 1: 0x%08x\n", regh); 2956 2957 n = regl & PCI_MCAST_OVERLAYL_SIZE; 2958 printf(" Overlay Size: "); 2959 if (n >= 6) 2960 printf("%d\n", n); 2961 else 2962 printf("off\n"); 2963 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 2964 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 2965 } 2966 2967 static void 2968 pci_conf_print_page_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 2969 { 2970 pcireg_t reg, ctl, sta; 2971 2972 printf("\n Page Request\n"); 2973 2974 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 2975 ctl = reg & 0xffff; 2976 sta = reg >> 16; 2977 printf(" Control Register: 0x%04x\n", ctl); 2978 onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E); 2979 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 2980 2981 printf(" Status Register: 0x%04x\n", sta); 2982 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 2983 onoff("Unexpected Page Request Group Index", reg, 2984 PCI_PAGE_REQ_STA_UPRGI); 2985 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 2986 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 2987 2988 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 2989 printf(" Outstanding Page Request Capacity: %u\n", reg); 2990 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 2991 printf(" Outstanding Page Request Allocation: %u\n", reg); 2992 } 2993 2994 /* XXX pci_conf_print_amd_cap */ 2995 /* XXX pci_conf_print_resiz_bar_cap */ 2996 /* XXX pci_conf_print_dpa_cap */ 2997 2998 static const char * 2999 pci_conf_print_tph_req_cap_sttabloc(unsigned char val) 3000 { 3001 3002 switch (val) { 3003 case 0x0: 3004 return "Not Present"; 3005 case 0x1: 3006 return "in the TPH Requester Capability Structure"; 3007 case 0x2: 3008 return "in the MSI-X Table"; 3009 default: 3010 return "Unknown"; 3011 } 3012 } 3013 3014 static void 3015 pci_conf_print_tph_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3016 { 3017 pcireg_t reg; 3018 int size, i, j; 3019 3020 printf("\n TPH Requester Extended Capability\n"); 3021 3022 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 3023 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 3024 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 3025 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 3026 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 3027 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 3028 printf(" ST Table Location: %s\n", 3029 pci_conf_print_tph_req_cap_sttabloc( 3030 (unsigned char)__SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC))); 3031 size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 3032 printf(" ST Table Size: %d\n", size); 3033 for (i = 0; i < size ; i += 2) { 3034 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 3035 for (j = 0; j < 2 ; j++) { 3036 uint32_t entry = reg; 3037 3038 if (j != 0) 3039 entry >>= 16; 3040 entry &= 0xffff; 3041 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 3042 i + j, entry); 3043 } 3044 } 3045 } 3046 3047 static void 3048 pci_conf_print_ltr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3049 { 3050 pcireg_t reg; 3051 3052 printf("\n Latency Tolerance Reporting\n"); 3053 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)] & 0xffff; 3054 printf(" Max Snoop Latency Register: 0x%04x\n", reg); 3055 printf(" Max Snoop LatencyValue: %u\n", 3056 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL)); 3057 printf(" Max Snoop LatencyScale: %uns\n", 3058 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE))); 3059 reg = regs[o2i(extcapoff + PCI_LTR_MAXNOSNOOPLAT)] >> 16; 3060 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg); 3061 printf(" Max No-Snoop LatencyValue: %u\n", 3062 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL)); 3063 printf(" Max No-Snoop LatencyScale: %uns\n", 3064 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE))); 3065 } 3066 3067 static void 3068 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int capoff, int extcapoff) 3069 { 3070 int pcie_capoff; 3071 pcireg_t reg; 3072 int i, maxlinkwidth; 3073 3074 printf("\n Secondary PCI Express Register\n"); 3075 3076 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3077 printf(" Link Control 3 register: 0x%08x\n", reg); 3078 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3079 onoff("Link Equalization Request Interrupt Enable", 3080 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3081 printf(" Enable Lower SKP OS Generation Vector:"); 3082 pci_print_pcie_linkspeedvector( 3083 __SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV)); 3084 printf("\n"); 3085 3086 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3087 printf(" Lane Error Status register: 0x%08x\n", reg); 3088 3089 /* Get Max Link Width */ 3090 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)){ 3091 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3092 maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3093 } else { 3094 printf("error: falied to get PCIe capablity\n"); 3095 return; 3096 } 3097 for (i = 0; i < maxlinkwidth; i++) { 3098 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3099 if (i % 2 != 0) 3100 reg >>= 16; 3101 else 3102 reg &= 0xffff; 3103 printf(" Equalization Control Register (Link %d): %04x\n", 3104 i, reg); 3105 printf(" Downstream Port Transmit Preset: 0x%x\n", 3106 (pcireg_t)__SHIFTOUT(reg, 3107 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3108 printf(" Downstream Port Receive Hint: 0x%x\n", 3109 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3110 printf(" Upstream Port Transmit Preset: 0x%x\n", 3111 (pcireg_t)__SHIFTOUT(reg, 3112 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3113 printf(" Upstream Port Receive Hint: 0x%x\n", 3114 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3115 } 3116 } 3117 3118 /* XXX pci_conf_print_pmux_cap */ 3119 3120 static void 3121 pci_conf_print_pasid_cap(const pcireg_t *regs, int capoff, int extcapoff) 3122 { 3123 pcireg_t reg, cap, ctl; 3124 unsigned int num; 3125 3126 printf("\n Process Address Space ID\n"); 3127 3128 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3129 cap = reg & 0xffff; 3130 ctl = reg >> 16; 3131 printf(" PASID Capability Register: 0x%04x\n", cap); 3132 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3133 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3134 num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3135 printf(" Max PASID Width: %u\n", num); 3136 3137 printf(" PASID Control Register: 0x%04x\n", ctl); 3138 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3139 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3140 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 3141 } 3142 3143 static void 3144 pci_conf_print_lnr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3145 { 3146 pcireg_t reg, cap, ctl; 3147 unsigned int num; 3148 3149 printf("\n LN Requester\n"); 3150 3151 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 3152 cap = reg & 0xffff; 3153 ctl = reg >> 16; 3154 printf(" LNR Capability register: 0x%04x\n", cap); 3155 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 3156 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 3157 num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 3158 printf(" LNR Registration MAX: %u\n", num); 3159 3160 printf(" LNR Control register: 0x%04x\n", ctl); 3161 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 3162 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 3163 num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 3164 printf(" LNR Registration Limit: %u\n", num); 3165 } 3166 3167 /* XXX pci_conf_print_dpc_cap */ 3168 3169 static int 3170 pci_conf_l1pm_cap_tposcale(unsigned char scale) 3171 { 3172 3173 /* Return scale in us */ 3174 switch (scale) { 3175 case 0x0: 3176 return 2; 3177 case 0x1: 3178 return 10; 3179 case 0x2: 3180 return 100; 3181 default: 3182 return -1; 3183 } 3184 } 3185 3186 static void 3187 pci_conf_print_l1pm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3188 { 3189 pcireg_t reg; 3190 int scale, val; 3191 3192 printf("\n L1 PM Substates\n"); 3193 3194 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 3195 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 3196 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 3197 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 3198 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 3199 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 3200 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 3201 printf(" Port Common Mode Restore Time: %uus\n", 3202 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 3203 scale = pci_conf_l1pm_cap_tposcale( 3204 __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 3205 val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 3206 printf(" Port T_POWER_ON: "); 3207 if (scale == -1) 3208 printf("unknown\n"); 3209 else 3210 printf("%dus\n", val * scale); 3211 3212 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 3213 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 3214 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 3215 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 3216 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 3217 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 3218 printf(" Common Mode Restore Time: %uus\n", 3219 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 3220 scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 3221 val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 3222 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 3223 3224 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 3225 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 3226 scale = pci_conf_l1pm_cap_tposcale( 3227 __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 3228 val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 3229 printf(" T_POWER_ON: "); 3230 if (scale == -1) 3231 printf("unknown\n"); 3232 else 3233 printf("%dus\n", val * scale); 3234 } 3235 3236 static void 3237 pci_conf_print_ptm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3238 { 3239 pcireg_t reg; 3240 uint32_t val; 3241 3242 printf("\n Precision Time Management\n"); 3243 3244 reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; 3245 printf(" PTM Capability register: 0x%08x\n", reg); 3246 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ); 3247 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP); 3248 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT); 3249 printf(" Local Clock Granularity: "); 3250 val = __SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL); 3251 switch (val) { 3252 case 0: 3253 printf("Not implemented\n"); 3254 break; 3255 case 0xffff: 3256 printf("> 254ns\n"); 3257 break; 3258 default: 3259 printf("%uns\n", val); 3260 break; 3261 } 3262 3263 reg = regs[o2i(extcapoff + PCI_PTM_CTL)]; 3264 printf(" PTM Control register: 0x%08x\n", reg); 3265 onoff("PTM Enable", reg, PCI_PTM_CTL_EN); 3266 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL); 3267 printf(" Effective Granularity: "); 3268 val = __SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL); 3269 switch (val) { 3270 case 0: 3271 printf("Unknown\n"); 3272 break; 3273 case 0xffff: 3274 printf("> 254ns\n"); 3275 break; 3276 default: 3277 printf("%uns\n", val); 3278 break; 3279 } 3280 } 3281 3282 /* XXX pci_conf_print_mpcie_cap */ 3283 /* XXX pci_conf_print_frsq_cap */ 3284 /* XXX pci_conf_print_rtr_cap */ 3285 /* XXX pci_conf_print_desigvndsp_cap */ 3286 3287 #undef MS 3288 #undef SM 3289 #undef RW 3290 3291 static struct { 3292 pcireg_t cap; 3293 const char *name; 3294 void (*printfunc)(const pcireg_t *, int, int); 3295 } pci_extcaptab[] = { 3296 { 0, "reserved", 3297 NULL }, 3298 { PCI_EXTCAP_AER, "Advanced Error Reporting", 3299 pci_conf_print_aer_cap }, 3300 { PCI_EXTCAP_VC, "Virtual Channel", 3301 pci_conf_print_vc_cap }, 3302 { PCI_EXTCAP_SERNUM, "Device Serial Number", 3303 pci_conf_print_sernum_cap }, 3304 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 3305 pci_conf_print_pwrbdgt_cap }, 3306 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 3307 pci_conf_print_rclink_dcl_cap }, 3308 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 3309 NULL }, 3310 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 3311 pci_conf_print_rcec_assoc_cap }, 3312 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 3313 NULL }, 3314 { PCI_EXTCAP_VC2, "Virtual Channel", 3315 NULL }, 3316 { PCI_EXTCAP_RCRB, "RCRB Header", 3317 NULL }, 3318 { PCI_EXTCAP_VENDOR, "Vendor Unique", 3319 NULL }, 3320 { PCI_EXTCAP_CAC, "Configuration Access Correction", 3321 NULL }, 3322 { PCI_EXTCAP_ACS, "Access Control Services", 3323 pci_conf_print_acs_cap }, 3324 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 3325 pci_conf_print_ari_cap }, 3326 { PCI_EXTCAP_ATS, "Address Translation Services", 3327 pci_conf_print_ats_cap }, 3328 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 3329 pci_conf_print_sriov_cap }, 3330 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 3331 NULL }, 3332 { PCI_EXTCAP_MCAST, "Multicast", 3333 pci_conf_print_multicast_cap }, 3334 { PCI_EXTCAP_PAGE_REQ, "Page Request", 3335 pci_conf_print_page_req_cap }, 3336 { PCI_EXTCAP_AMD, "Reserved for AMD", 3337 NULL }, 3338 { PCI_EXTCAP_RESIZ_BAR, "Resizable BAR", 3339 NULL }, 3340 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 3341 NULL }, 3342 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 3343 pci_conf_print_tph_req_cap }, 3344 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 3345 pci_conf_print_ltr_cap }, 3346 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 3347 pci_conf_print_sec_pcie_cap }, 3348 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 3349 NULL }, 3350 { PCI_EXTCAP_PASID, "Process Address Space ID", 3351 pci_conf_print_pasid_cap }, 3352 { PCI_EXTCAP_LN_REQ, "LN Requester", 3353 pci_conf_print_lnr_cap }, 3354 { PCI_EXTCAP_DPC, "Downstream Port Containment", 3355 NULL }, 3356 { PCI_EXTCAP_L1PM, "L1 PM Substates", 3357 pci_conf_print_l1pm_cap }, 3358 { PCI_EXTCAP_PTM, "Precision Time Management", 3359 pci_conf_print_ptm_cap }, 3360 { PCI_EXTCAP_MPCIE, "M-PCIe", 3361 NULL }, 3362 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 3363 NULL }, 3364 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 3365 NULL }, 3366 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 3367 NULL }, 3368 }; 3369 3370 static int 3371 pci_conf_find_extcap(const pcireg_t *regs, int capoff, unsigned int capid, 3372 int *offsetp) 3373 { 3374 int off; 3375 pcireg_t rval; 3376 3377 for (off = PCI_EXTCAPLIST_BASE; 3378 off != 0; 3379 off = PCI_EXTCAPLIST_NEXT(rval)) { 3380 rval = regs[o2i(off)]; 3381 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 3382 if (offsetp != NULL) 3383 *offsetp = off; 3384 return 1; 3385 } 3386 } 3387 return 0; 3388 } 3389 3390 static void 3391 pci_conf_print_extcaplist( 3392 #ifdef _KERNEL 3393 pci_chipset_tag_t pc, pcitag_t tag, 3394 #endif 3395 const pcireg_t *regs, int capoff) 3396 { 3397 int off; 3398 pcireg_t foundcap; 3399 pcireg_t rval; 3400 bool foundtable[__arraycount(pci_extcaptab)]; 3401 unsigned int i; 3402 3403 /* Check Extended capability structure */ 3404 off = PCI_EXTCAPLIST_BASE; 3405 rval = regs[o2i(off)]; 3406 if (rval == 0xffffffff || rval == 0) 3407 return; 3408 3409 /* Clear table */ 3410 for (i = 0; i < __arraycount(pci_extcaptab); i++) 3411 foundtable[i] = false; 3412 3413 /* Print extended capability register's offset and the type first */ 3414 for (;;) { 3415 printf(" Extended Capability Register at 0x%02x\n", off); 3416 3417 foundcap = PCI_EXTCAPLIST_CAP(rval); 3418 printf(" type: 0x%04x (", foundcap); 3419 if (foundcap < __arraycount(pci_extcaptab)) { 3420 printf("%s)\n", pci_extcaptab[foundcap].name); 3421 /* Mark as found */ 3422 foundtable[foundcap] = true; 3423 } else 3424 printf("unknown)\n"); 3425 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 3426 3427 off = PCI_EXTCAPLIST_NEXT(rval); 3428 if (off == 0) 3429 break; 3430 rval = regs[o2i(off)]; 3431 } 3432 3433 /* 3434 * And then, print the detail of each capability registers 3435 * in capability value's order. 3436 */ 3437 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 3438 if (foundtable[i] == false) 3439 continue; 3440 3441 /* 3442 * The type was found. Search capability list again and 3443 * print all capabilities that the capabiliy type is 3444 * the same. 3445 */ 3446 if (pci_conf_find_extcap(regs, capoff, i, &off) == 0) 3447 continue; 3448 rval = regs[o2i(off)]; 3449 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 3450 || (pci_extcaptab[i].printfunc == NULL)) 3451 continue; 3452 3453 pci_extcaptab[i].printfunc(regs, capoff, off); 3454 3455 } 3456 } 3457 3458 /* Print the Secondary Status Register. */ 3459 static void 3460 pci_conf_print_ssr(pcireg_t rval) 3461 { 3462 pcireg_t devsel; 3463 3464 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 3465 onoff("66 MHz capable", rval, __BIT(5)); 3466 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 3467 onoff("Fast back-to-back capable", rval, __BIT(7)); 3468 onoff("Data parity error detected", rval, __BIT(8)); 3469 3470 printf(" DEVSEL timing: "); 3471 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 3472 switch (devsel) { 3473 case 0: 3474 printf("fast"); 3475 break; 3476 case 1: 3477 printf("medium"); 3478 break; 3479 case 2: 3480 printf("slow"); 3481 break; 3482 default: 3483 printf("unknown/reserved"); /* XXX */ 3484 break; 3485 } 3486 printf(" (0x%x)\n", devsel); 3487 3488 onoff("Signalled target abort", rval, __BIT(11)); 3489 onoff("Received target abort", rval, __BIT(12)); 3490 onoff("Received master abort", rval, __BIT(13)); 3491 onoff("Received system error", rval, __BIT(14)); 3492 onoff("Detected parity error", rval, __BIT(15)); 3493 } 3494 3495 static void 3496 pci_conf_print_type0( 3497 #ifdef _KERNEL 3498 pci_chipset_tag_t pc, pcitag_t tag, 3499 #endif 3500 const pcireg_t *regs 3501 #ifdef _KERNEL 3502 , int sizebars 3503 #endif 3504 ) 3505 { 3506 int off, width; 3507 pcireg_t rval; 3508 3509 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 3510 #ifdef _KERNEL 3511 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3512 #else 3513 width = pci_conf_print_bar(regs, off, NULL); 3514 #endif 3515 } 3516 3517 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 3518 3519 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 3520 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 3521 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 3522 3523 /* XXX */ 3524 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 3525 3526 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3527 printf(" Capability list pointer: 0x%02x\n", 3528 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 3529 else 3530 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 3531 3532 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 3533 3534 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3535 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 3536 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 3537 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 3538 switch (PCI_INTERRUPT_PIN(rval)) { 3539 case PCI_INTERRUPT_PIN_NONE: 3540 printf("(none)"); 3541 break; 3542 case PCI_INTERRUPT_PIN_A: 3543 printf("(pin A)"); 3544 break; 3545 case PCI_INTERRUPT_PIN_B: 3546 printf("(pin B)"); 3547 break; 3548 case PCI_INTERRUPT_PIN_C: 3549 printf("(pin C)"); 3550 break; 3551 case PCI_INTERRUPT_PIN_D: 3552 printf("(pin D)"); 3553 break; 3554 default: 3555 printf("(? ? ?)"); 3556 break; 3557 } 3558 printf("\n"); 3559 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 3560 } 3561 3562 static void 3563 pci_conf_print_type1( 3564 #ifdef _KERNEL 3565 pci_chipset_tag_t pc, pcitag_t tag, 3566 #endif 3567 const pcireg_t *regs 3568 #ifdef _KERNEL 3569 , int sizebars 3570 #endif 3571 ) 3572 { 3573 int off, width; 3574 pcireg_t rval; 3575 uint32_t base, limit; 3576 uint32_t base_h, limit_h; 3577 uint64_t pbase, plimit; 3578 int use_upper; 3579 3580 /* 3581 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 3582 * Bridge chip documentation, and may not be correct with 3583 * respect to various standards. (XXX) 3584 */ 3585 3586 for (off = 0x10; off < 0x18; off += width) { 3587 #ifdef _KERNEL 3588 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3589 #else 3590 width = pci_conf_print_bar(regs, off, NULL); 3591 #endif 3592 } 3593 3594 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 3595 printf(" Primary bus number: 0x%02x\n", 3596 PCI_BRIDGE_BUS_PRIMARY(rval)); 3597 printf(" Secondary bus number: 0x%02x\n", 3598 PCI_BRIDGE_BUS_SECONDARY(rval)); 3599 printf(" Subordinate bus number: 0x%02x\n", 3600 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 3601 printf(" Secondary bus latency timer: 0x%02x\n", 3602 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 3603 3604 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 3605 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 3606 3607 /* I/O region */ 3608 printf(" I/O region:\n"); 3609 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 3610 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 3611 if (PCI_BRIDGE_IO_32BITS(rval)) 3612 use_upper = 1; 3613 else 3614 use_upper = 0; 3615 onoff("32bit I/O", rval, use_upper); 3616 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 3617 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 3618 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 3619 limit |= 0x00000fff; 3620 3621 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 3622 base_h = (rval >> 0) & 0xffff; 3623 limit_h = (rval >> 16) & 0xffff; 3624 printf(" base upper 16 bits register: 0x%04x\n", base_h); 3625 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 3626 3627 if (use_upper == 1) { 3628 base |= base_h << 16; 3629 limit |= limit_h << 16; 3630 } 3631 if (base < limit) { 3632 if (use_upper == 1) 3633 printf(" range: 0x%08x-0x%08x\n", base, limit); 3634 else 3635 printf(" range: 0x%04x-0x%04x\n", base, limit); 3636 } else 3637 printf(" range: not set\n"); 3638 3639 /* Non-prefetchable memory region */ 3640 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 3641 printf(" Memory region:\n"); 3642 printf(" base register: 0x%04x\n", 3643 (rval >> 0) & 0xffff); 3644 printf(" limit register: 0x%04x\n", 3645 (rval >> 16) & 0xffff); 3646 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 3647 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 3648 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 3649 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 3650 if (base < limit) 3651 printf(" range: 0x%08x-0x%08x\n", base, limit); 3652 else 3653 printf(" range: not set\n"); 3654 3655 /* Prefetchable memory region */ 3656 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 3657 printf(" Prefetchable memory region:\n"); 3658 printf(" base register: 0x%04x\n", 3659 (rval >> 0) & 0xffff); 3660 printf(" limit register: 0x%04x\n", 3661 (rval >> 16) & 0xffff); 3662 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 3663 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 3664 printf(" base upper 32 bits register: 0x%08x\n", 3665 base_h); 3666 printf(" limit upper 32 bits register: 0x%08x\n", 3667 limit_h); 3668 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 3669 use_upper = 1; 3670 else 3671 use_upper = 0; 3672 onoff("64bit memory address", rval, use_upper); 3673 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 3674 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 3675 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 3676 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 3677 if (use_upper == 1) { 3678 pbase |= (uint64_t)base_h << 32; 3679 plimit |= (uint64_t)limit_h << 32; 3680 } 3681 if (pbase < plimit) { 3682 if (use_upper == 1) 3683 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 3684 "\n", pbase, plimit); 3685 else 3686 printf(" range: 0x%08x-0x%08x\n", 3687 (uint32_t)pbase, (uint32_t)plimit); 3688 } else 3689 printf(" range: not set\n"); 3690 3691 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3692 printf(" Capability list pointer: 0x%02x\n", 3693 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 3694 else 3695 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 3696 3697 /* XXX */ 3698 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 3699 3700 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3701 printf(" Interrupt line: 0x%02x\n", 3702 (rval >> 0) & 0xff); 3703 printf(" Interrupt pin: 0x%02x ", 3704 (rval >> 8) & 0xff); 3705 switch ((rval >> 8) & 0xff) { 3706 case PCI_INTERRUPT_PIN_NONE: 3707 printf("(none)"); 3708 break; 3709 case PCI_INTERRUPT_PIN_A: 3710 printf("(pin A)"); 3711 break; 3712 case PCI_INTERRUPT_PIN_B: 3713 printf("(pin B)"); 3714 break; 3715 case PCI_INTERRUPT_PIN_C: 3716 printf("(pin C)"); 3717 break; 3718 case PCI_INTERRUPT_PIN_D: 3719 printf("(pin D)"); 3720 break; 3721 default: 3722 printf("(? ? ?)"); 3723 break; 3724 } 3725 printf("\n"); 3726 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 3727 & PCI_BRIDGE_CONTROL_MASK; 3728 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 3729 onoff("Parity error response", rval, 0x0001); 3730 onoff("Secondary SERR forwarding", rval, 0x0002); 3731 onoff("ISA enable", rval, 0x0004); 3732 onoff("VGA enable", rval, 0x0008); 3733 onoff("Master abort reporting", rval, 0x0020); 3734 onoff("Secondary bus reset", rval, 0x0040); 3735 onoff("Fast back-to-back capable", rval, 0x0080); 3736 } 3737 3738 static void 3739 pci_conf_print_type2( 3740 #ifdef _KERNEL 3741 pci_chipset_tag_t pc, pcitag_t tag, 3742 #endif 3743 const pcireg_t *regs 3744 #ifdef _KERNEL 3745 , int sizebars 3746 #endif 3747 ) 3748 { 3749 pcireg_t rval; 3750 3751 /* 3752 * XXX these need to be printed in more detail, need to be 3753 * XXX checked against specs/docs, etc. 3754 * 3755 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 3756 * controller chip documentation, and may not be correct with 3757 * respect to various standards. (XXX) 3758 */ 3759 3760 #ifdef _KERNEL 3761 pci_conf_print_bar(pc, tag, regs, 0x10, 3762 "CardBus socket/ExCA registers", sizebars); 3763 #else 3764 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 3765 #endif 3766 3767 /* Capability list pointer and secondary status register */ 3768 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 3769 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3770 printf(" Capability list pointer: 0x%02x\n", 3771 PCI_CAPLIST_PTR(rval)); 3772 else 3773 printf(" Reserved @ 0x14: 0x%04x\n", 3774 (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0))); 3775 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 3776 3777 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 3778 printf(" PCI bus number: 0x%02x\n", 3779 (rval >> 0) & 0xff); 3780 printf(" CardBus bus number: 0x%02x\n", 3781 (rval >> 8) & 0xff); 3782 printf(" Subordinate bus number: 0x%02x\n", 3783 (rval >> 16) & 0xff); 3784 printf(" CardBus latency timer: 0x%02x\n", 3785 (rval >> 24) & 0xff); 3786 3787 /* XXX Print more prettily */ 3788 printf(" CardBus memory region 0:\n"); 3789 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 3790 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 3791 printf(" CardBus memory region 1:\n"); 3792 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 3793 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 3794 printf(" CardBus I/O region 0:\n"); 3795 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 3796 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 3797 printf(" CardBus I/O region 1:\n"); 3798 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 3799 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 3800 3801 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3802 printf(" Interrupt line: 0x%02x\n", 3803 (rval >> 0) & 0xff); 3804 printf(" Interrupt pin: 0x%02x ", 3805 (rval >> 8) & 0xff); 3806 switch ((rval >> 8) & 0xff) { 3807 case PCI_INTERRUPT_PIN_NONE: 3808 printf("(none)"); 3809 break; 3810 case PCI_INTERRUPT_PIN_A: 3811 printf("(pin A)"); 3812 break; 3813 case PCI_INTERRUPT_PIN_B: 3814 printf("(pin B)"); 3815 break; 3816 case PCI_INTERRUPT_PIN_C: 3817 printf("(pin C)"); 3818 break; 3819 case PCI_INTERRUPT_PIN_D: 3820 printf("(pin D)"); 3821 break; 3822 default: 3823 printf("(? ? ?)"); 3824 break; 3825 } 3826 printf("\n"); 3827 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 3828 printf(" Bridge control register: 0x%04x\n", rval); 3829 onoff("Parity error response", rval, __BIT(0)); 3830 onoff("SERR# enable", rval, __BIT(1)); 3831 onoff("ISA enable", rval, __BIT(2)); 3832 onoff("VGA enable", rval, __BIT(3)); 3833 onoff("Master abort mode", rval, __BIT(5)); 3834 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 3835 onoff("Functional interrupts routed by ExCA registers", rval, 3836 __BIT(7)); 3837 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 3838 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 3839 onoff("Write posting enable", rval, __BIT(10)); 3840 3841 rval = regs[o2i(0x40)]; 3842 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 3843 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 3844 3845 #ifdef _KERNEL 3846 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 3847 sizebars); 3848 #else 3849 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 3850 #endif 3851 } 3852 3853 void 3854 pci_conf_print( 3855 #ifdef _KERNEL 3856 pci_chipset_tag_t pc, pcitag_t tag, 3857 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 3858 #else 3859 int pcifd, u_int bus, u_int dev, u_int func 3860 #endif 3861 ) 3862 { 3863 pcireg_t regs[o2i(PCI_EXTCONF_SIZE)]; 3864 int off, capoff, endoff, hdrtype; 3865 const char *type_name; 3866 #ifdef _KERNEL 3867 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, 3868 int); 3869 int sizebars; 3870 #else 3871 void (*type_printfn)(const pcireg_t *); 3872 #endif 3873 3874 printf("PCI configuration registers:\n"); 3875 3876 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 3877 #ifdef _KERNEL 3878 regs[o2i(off)] = pci_conf_read(pc, tag, off); 3879 #else 3880 if (pcibus_conf_read(pcifd, bus, dev, func, off, 3881 ®s[o2i(off)]) == -1) 3882 regs[o2i(off)] = 0; 3883 #endif 3884 } 3885 3886 #ifdef _KERNEL 3887 sizebars = 1; 3888 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 3889 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 3890 sizebars = 0; 3891 #endif 3892 3893 /* common header */ 3894 printf(" Common header:\n"); 3895 pci_conf_print_regs(regs, 0, 16); 3896 3897 printf("\n"); 3898 #ifdef _KERNEL 3899 pci_conf_print_common(pc, tag, regs); 3900 #else 3901 pci_conf_print_common(regs); 3902 #endif 3903 printf("\n"); 3904 3905 /* type-dependent header */ 3906 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 3907 switch (hdrtype) { /* XXX make a table, eventually */ 3908 case 0: 3909 /* Standard device header */ 3910 type_name = "\"normal\" device"; 3911 type_printfn = &pci_conf_print_type0; 3912 capoff = PCI_CAPLISTPTR_REG; 3913 endoff = 64; 3914 break; 3915 case 1: 3916 /* PCI-PCI bridge header */ 3917 type_name = "PCI-PCI bridge"; 3918 type_printfn = &pci_conf_print_type1; 3919 capoff = PCI_CAPLISTPTR_REG; 3920 endoff = 64; 3921 break; 3922 case 2: 3923 /* PCI-CardBus bridge header */ 3924 type_name = "PCI-CardBus bridge"; 3925 type_printfn = &pci_conf_print_type2; 3926 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 3927 endoff = 72; 3928 break; 3929 default: 3930 type_name = NULL; 3931 type_printfn = 0; 3932 capoff = -1; 3933 endoff = 64; 3934 break; 3935 } 3936 printf(" Type %d ", hdrtype); 3937 if (type_name != NULL) 3938 printf("(%s) ", type_name); 3939 printf("header:\n"); 3940 pci_conf_print_regs(regs, 16, endoff); 3941 printf("\n"); 3942 if (type_printfn) { 3943 #ifdef _KERNEL 3944 (*type_printfn)(pc, tag, regs, sizebars); 3945 #else 3946 (*type_printfn)(regs); 3947 #endif 3948 } else 3949 printf(" Don't know how to pretty-print type %d header.\n", 3950 hdrtype); 3951 printf("\n"); 3952 3953 /* capability list, if present */ 3954 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3955 && (capoff > 0)) { 3956 #ifdef _KERNEL 3957 pci_conf_print_caplist(pc, tag, regs, capoff); 3958 #else 3959 pci_conf_print_caplist(regs, capoff); 3960 #endif 3961 printf("\n"); 3962 } 3963 3964 /* device-dependent header */ 3965 printf(" Device-dependent header:\n"); 3966 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 3967 printf("\n"); 3968 #ifdef _KERNEL 3969 if (printfn) 3970 (*printfn)(pc, tag, regs); 3971 else 3972 printf(" Don't know how to pretty-print device-dependent header.\n"); 3973 printf("\n"); 3974 #endif /* _KERNEL */ 3975 3976 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 3977 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 3978 return; 3979 3980 #ifdef _KERNEL 3981 pci_conf_print_extcaplist(pc, tag, regs, capoff); 3982 #else 3983 pci_conf_print_extcaplist(regs, capoff); 3984 #endif 3985 printf("\n"); 3986 3987 /* Extended Configuration Space, if present */ 3988 printf(" Extended Configuration Space:\n"); 3989 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 3990 } 3991
Indexes created Tue Sep 23 22:09:46 GMT 2025