pci_subr.c revision 1.154
1 /* $NetBSD: pci_subr.c,v 1.154 2016/10/31 09:13:20 martin Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.154 2016/10/31 09:13:20 martin Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdbool.h> 58 #include <stdio.h> 59 #include <stdlib.h> 60 #include <string.h> 61 #endif 62 63 #include <dev/pci/pcireg.h> 64 #ifdef _KERNEL 65 #include <dev/pci/pcivar.h> 66 #else 67 #include <dev/pci/pci_verbose.h> 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcidevs_data.h> 70 #endif 71 72 /* 73 * Descriptions of known PCI classes and subclasses. 74 * 75 * Subclasses are described in the same way as classes, but have a 76 * NULL subclass pointer. 77 */ 78 struct pci_class { 79 const char *name; 80 u_int val; /* as wide as pci_{,sub}class_t */ 81 const struct pci_class *subclasses; 82 }; 83 84 /* 85 * Class 0x00. 86 * Before rev. 2.0. 87 */ 88 static const struct pci_class pci_subclass_prehistoric[] = { 89 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 90 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 91 { NULL, 0, NULL, }, 92 }; 93 94 /* 95 * Class 0x01. 96 * Mass storage controller 97 */ 98 99 /* ATA programming interface */ 100 static const struct pci_class pci_interface_ata[] = { 101 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 102 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 103 { NULL, 0, NULL, }, 104 }; 105 106 /* SATA programming interface */ 107 static const struct pci_class pci_interface_sata[] = { 108 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 109 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 110 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 111 { NULL, 0, NULL, }, 112 }; 113 114 /* Flash programming interface */ 115 static const struct pci_class pci_interface_nvm[] = { 116 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 117 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 118 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 119 { NULL, 0, NULL, }, 120 }; 121 122 /* Subclasses */ 123 static const struct pci_class pci_subclass_mass_storage[] = { 124 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 125 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 126 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 127 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 128 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 129 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 130 pci_interface_ata, }, 131 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 132 pci_interface_sata, }, 133 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 134 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 135 pci_interface_nvm, }, 136 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 137 { NULL, 0, NULL, }, 138 }; 139 140 /* 141 * Class 0x02. 142 * Network controller. 143 */ 144 static const struct pci_class pci_subclass_network[] = { 145 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 146 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 147 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 148 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 149 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 150 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 151 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 152 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 153 { NULL, 0, NULL, }, 154 }; 155 156 /* 157 * Class 0x03. 158 * Display controller. 159 */ 160 161 /* VGA programming interface */ 162 static const struct pci_class pci_interface_vga[] = { 163 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 164 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 165 { NULL, 0, NULL, }, 166 }; 167 /* Subclasses */ 168 static const struct pci_class pci_subclass_display[] = { 169 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 170 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 171 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 172 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 173 { NULL, 0, NULL, }, 174 }; 175 176 /* 177 * Class 0x04. 178 * Multimedia device. 179 */ 180 static const struct pci_class pci_subclass_multimedia[] = { 181 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 182 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 183 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 184 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 185 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 186 { NULL, 0, NULL, }, 187 }; 188 189 /* 190 * Class 0x05. 191 * Memory controller. 192 */ 193 static const struct pci_class pci_subclass_memory[] = { 194 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 195 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 196 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 197 { NULL, 0, NULL, }, 198 }; 199 200 /* 201 * Class 0x06. 202 * Bridge device. 203 */ 204 205 /* PCI bridge programming interface */ 206 static const struct pci_class pci_interface_pcibridge[] = { 207 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 208 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 209 { NULL, 0, NULL, }, 210 }; 211 212 /* Semi-transparent PCI-to-PCI bridge programming interface */ 213 static const struct pci_class pci_interface_stpci[] = { 214 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 215 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 216 { NULL, 0, NULL, }, 217 }; 218 219 /* Advanced Switching programming interface */ 220 static const struct pci_class pci_interface_advsw[] = { 221 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 222 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 223 { NULL, 0, NULL, }, 224 }; 225 226 /* Subclasses */ 227 static const struct pci_class pci_subclass_bridge[] = { 228 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 229 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 230 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 231 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 232 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 233 pci_interface_pcibridge, }, 234 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 235 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 236 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 237 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 238 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 239 pci_interface_stpci, }, 240 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 241 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 242 pci_interface_advsw, }, 243 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 244 { NULL, 0, NULL, }, 245 }; 246 247 /* 248 * Class 0x07. 249 * Simple communications controller. 250 */ 251 252 /* Serial controller programming interface */ 253 static const struct pci_class pci_interface_serial[] = { 254 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 255 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 256 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 257 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 258 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 259 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 260 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 261 { NULL, 0, NULL, }, 262 }; 263 264 /* Parallel controller programming interface */ 265 static const struct pci_class pci_interface_parallel[] = { 266 { "", PCI_INTERFACE_PARALLEL, NULL,}, 267 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 268 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 269 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 270 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 271 { NULL, 0, NULL,}, 272 }; 273 274 /* Modem programming interface */ 275 static const struct pci_class pci_interface_modem[] = { 276 { "", PCI_INTERFACE_MODEM, NULL,}, 277 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 278 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 279 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 280 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 281 { NULL, 0, NULL,}, 282 }; 283 284 /* Subclasses */ 285 static const struct pci_class pci_subclass_communications[] = { 286 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 287 pci_interface_serial, }, 288 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 289 pci_interface_parallel, }, 290 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 291 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 292 pci_interface_modem, }, 293 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 294 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 295 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 296 { NULL, 0, NULL,}, 297 }; 298 299 /* 300 * Class 0x08. 301 * Base system peripheral. 302 */ 303 304 /* PIC programming interface */ 305 static const struct pci_class pci_interface_pic[] = { 306 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 307 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 308 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 309 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 310 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 311 { NULL, 0, NULL, }, 312 }; 313 314 /* DMA programming interface */ 315 static const struct pci_class pci_interface_dma[] = { 316 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 317 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 318 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 319 { NULL, 0, NULL, }, 320 }; 321 322 /* Timer programming interface */ 323 static const struct pci_class pci_interface_tmr[] = { 324 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 325 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 326 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 327 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 328 { NULL, 0, NULL, }, 329 }; 330 331 /* RTC programming interface */ 332 static const struct pci_class pci_interface_rtc[] = { 333 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 334 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 335 { NULL, 0, NULL, }, 336 }; 337 338 /* Subclasses */ 339 static const struct pci_class pci_subclass_system[] = { 340 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 341 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 342 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 343 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 344 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 345 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 346 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 347 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 348 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 349 { NULL, 0, NULL, }, 350 }; 351 352 /* 353 * Class 0x09. 354 * Input device. 355 */ 356 357 /* Gameport programming interface */ 358 static const struct pci_class pci_interface_game[] = { 359 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 360 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 361 { NULL, 0, NULL, }, 362 }; 363 364 /* Subclasses */ 365 static const struct pci_class pci_subclass_input[] = { 366 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 367 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 368 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 369 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 370 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 371 pci_interface_game, }, 372 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 373 { NULL, 0, NULL, }, 374 }; 375 376 /* 377 * Class 0x0a. 378 * Docking station. 379 */ 380 static const struct pci_class pci_subclass_dock[] = { 381 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 382 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 383 { NULL, 0, NULL, }, 384 }; 385 386 /* 387 * Class 0x0b. 388 * Processor. 389 */ 390 static const struct pci_class pci_subclass_processor[] = { 391 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 392 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 393 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 394 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 395 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 396 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 397 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 398 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 399 { NULL, 0, NULL, }, 400 }; 401 402 /* 403 * Class 0x0c. 404 * Serial bus controller. 405 */ 406 407 /* IEEE1394 programming interface */ 408 static const struct pci_class pci_interface_ieee1394[] = { 409 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 410 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 411 { NULL, 0, NULL,}, 412 }; 413 414 /* USB programming interface */ 415 static const struct pci_class pci_interface_usb[] = { 416 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 417 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 418 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 419 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 420 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 421 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 422 { NULL, 0, NULL, }, 423 }; 424 425 /* IPMI programming interface */ 426 static const struct pci_class pci_interface_ipmi[] = { 427 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 428 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 429 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 430 { NULL, 0, NULL,}, 431 }; 432 433 /* Subclasses */ 434 static const struct pci_class pci_subclass_serialbus[] = { 435 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 436 pci_interface_ieee1394, }, 437 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 438 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 439 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 440 pci_interface_usb, }, 441 /* XXX Fiber Channel/_FIBRECHANNEL */ 442 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 443 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 444 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 445 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 446 pci_interface_ipmi, }, 447 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 448 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 449 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 450 { NULL, 0, NULL, }, 451 }; 452 453 /* 454 * Class 0x0d. 455 * Wireless Controller. 456 */ 457 static const struct pci_class pci_subclass_wireless[] = { 458 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 459 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 460 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 461 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 462 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 463 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 464 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 465 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 466 { NULL, 0, NULL, }, 467 }; 468 469 /* 470 * Class 0x0e. 471 * Intelligent IO controller. 472 */ 473 474 /* Intelligent IO programming interface */ 475 static const struct pci_class pci_interface_i2o[] = { 476 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 477 { NULL, 0, NULL,}, 478 }; 479 480 /* Subclasses */ 481 static const struct pci_class pci_subclass_i2o[] = { 482 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 483 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 484 { NULL, 0, NULL, }, 485 }; 486 487 /* 488 * Class 0x0f. 489 * Satellite communication controller. 490 */ 491 static const struct pci_class pci_subclass_satcom[] = { 492 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 493 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 494 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 495 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 496 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 497 { NULL, 0, NULL, }, 498 }; 499 500 /* 501 * Class 0x10. 502 * Encryption/Decryption controller. 503 */ 504 static const struct pci_class pci_subclass_crypto[] = { 505 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 506 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 507 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 508 { NULL, 0, NULL, }, 509 }; 510 511 /* 512 * Class 0x11. 513 * Data aquuisition and signal processing controller. 514 */ 515 static const struct pci_class pci_subclass_dasp[] = { 516 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 517 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 518 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 519 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 520 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 521 { NULL, 0, NULL, }, 522 }; 523 524 /* List of classes */ 525 static const struct pci_class pci_class[] = { 526 { "prehistoric", PCI_CLASS_PREHISTORIC, 527 pci_subclass_prehistoric, }, 528 { "mass storage", PCI_CLASS_MASS_STORAGE, 529 pci_subclass_mass_storage, }, 530 { "network", PCI_CLASS_NETWORK, 531 pci_subclass_network, }, 532 { "display", PCI_CLASS_DISPLAY, 533 pci_subclass_display, }, 534 { "multimedia", PCI_CLASS_MULTIMEDIA, 535 pci_subclass_multimedia, }, 536 { "memory", PCI_CLASS_MEMORY, 537 pci_subclass_memory, }, 538 { "bridge", PCI_CLASS_BRIDGE, 539 pci_subclass_bridge, }, 540 { "communications", PCI_CLASS_COMMUNICATIONS, 541 pci_subclass_communications, }, 542 { "system", PCI_CLASS_SYSTEM, 543 pci_subclass_system, }, 544 { "input", PCI_CLASS_INPUT, 545 pci_subclass_input, }, 546 { "dock", PCI_CLASS_DOCK, 547 pci_subclass_dock, }, 548 { "processor", PCI_CLASS_PROCESSOR, 549 pci_subclass_processor, }, 550 { "serial bus", PCI_CLASS_SERIALBUS, 551 pci_subclass_serialbus, }, 552 { "wireless", PCI_CLASS_WIRELESS, 553 pci_subclass_wireless, }, 554 { "I2O", PCI_CLASS_I2O, 555 pci_subclass_i2o, }, 556 { "satellite comm", PCI_CLASS_SATCOM, 557 pci_subclass_satcom, }, 558 { "crypto", PCI_CLASS_CRYPTO, 559 pci_subclass_crypto, }, 560 { "DASP", PCI_CLASS_DASP, 561 pci_subclass_dasp, }, 562 { "undefined", PCI_CLASS_UNDEFINED, 563 NULL, }, 564 { NULL, 0, 565 NULL, }, 566 }; 567 568 DEV_VERBOSE_DEFINE(pci); 569 570 void 571 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 572 size_t l) 573 { 574 pci_class_t pciclass; 575 pci_subclass_t subclass; 576 pci_interface_t interface; 577 pci_revision_t revision; 578 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 579 const struct pci_class *classp, *subclassp, *interfacep; 580 char *ep; 581 582 ep = cp + l; 583 584 pciclass = PCI_CLASS(class_reg); 585 subclass = PCI_SUBCLASS(class_reg); 586 interface = PCI_INTERFACE(class_reg); 587 revision = PCI_REVISION(class_reg); 588 589 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 590 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 591 PCI_PRODUCT(id_reg)); 592 593 classp = pci_class; 594 while (classp->name != NULL) { 595 if (pciclass == classp->val) 596 break; 597 classp++; 598 } 599 600 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 601 while (subclassp && subclassp->name != NULL) { 602 if (subclass == subclassp->val) 603 break; 604 subclassp++; 605 } 606 607 interfacep = (subclassp && subclassp->name != NULL) ? 608 subclassp->subclasses : NULL; 609 while (interfacep && interfacep->name != NULL) { 610 if (interface == interfacep->val) 611 break; 612 interfacep++; 613 } 614 615 cp += snprintf(cp, ep - cp, "%s %s", vendor, product); 616 if (showclass) { 617 cp += snprintf(cp, ep - cp, " ("); 618 if (classp->name == NULL) 619 cp += snprintf(cp, ep - cp, 620 "class 0x%02x, subclass 0x%02x", pciclass, subclass); 621 else { 622 if (subclassp == NULL || subclassp->name == NULL) 623 cp += snprintf(cp, ep - cp, 624 "%s, subclass 0x%02x", 625 classp->name, subclass); 626 else 627 cp += snprintf(cp, ep - cp, "%s %s", 628 subclassp->name, classp->name); 629 } 630 if ((interfacep == NULL) || (interfacep->name == NULL)) { 631 if (interface != 0) 632 cp += snprintf(cp, ep - cp, 633 ", interface 0x%02x", interface); 634 } else if (strncmp(interfacep->name, "", 1) != 0) 635 cp += snprintf(cp, ep - cp, ", %s", 636 interfacep->name); 637 if (revision != 0) 638 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 639 revision); 640 cp += snprintf(cp, ep - cp, ")"); 641 } 642 } 643 644 #ifdef _KERNEL 645 void 646 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 647 const char *known, int addrev) 648 { 649 char devinfo[256]; 650 651 if (known) { 652 aprint_normal(": %s", known); 653 if (addrev) 654 aprint_normal(" (rev. 0x%02x)", 655 PCI_REVISION(pa->pa_class)); 656 aprint_normal("\n"); 657 } else { 658 pci_devinfo(pa->pa_id, pa->pa_class, 0, 659 devinfo, sizeof(devinfo)); 660 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 661 PCI_REVISION(pa->pa_class)); 662 } 663 if (naive) 664 aprint_naive(": %s\n", naive); 665 else 666 aprint_naive("\n"); 667 } 668 #endif 669 670 /* 671 * Print out most of the PCI configuration registers. Typically used 672 * in a device attach routine like this: 673 * 674 * #ifdef MYDEV_DEBUG 675 * printf("%s: ", device_xname(sc->sc_dev)); 676 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 677 * #endif 678 */ 679 680 #define i2o(i) ((i) * 4) 681 #define o2i(o) ((o) / 4) 682 #define onoff2(str, rval, bit, onstr, offstr) \ 683 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 684 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 685 686 static void 687 pci_conf_print_common( 688 #ifdef _KERNEL 689 pci_chipset_tag_t pc, pcitag_t tag, 690 #endif 691 const pcireg_t *regs) 692 { 693 const char *name; 694 const struct pci_class *classp, *subclassp; 695 char vendor[PCI_VENDORSTR_LEN]; 696 char product[PCI_PRODUCTSTR_LEN]; 697 pcireg_t rval; 698 unsigned int num; 699 700 rval = regs[o2i(PCI_ID_REG)]; 701 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 702 if (name) 703 printf(" Vendor Name: %s (0x%04x)\n", name, 704 PCI_VENDOR(rval)); 705 else 706 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 707 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 708 PCI_PRODUCT(rval)); 709 if (name) 710 printf(" Device Name: %s (0x%04x)\n", name, 711 PCI_PRODUCT(rval)); 712 else 713 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 714 715 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 716 717 printf(" Command register: 0x%04x\n", rval & 0xffff); 718 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 719 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 720 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 721 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 722 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 723 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 724 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 725 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 726 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 727 onoff("Fast back-to-back transactions", rval, 728 PCI_COMMAND_BACKTOBACK_ENABLE); 729 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 730 731 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 732 onoff("Immediate Readness", rval, PCI_STATUS_IMMD_READNESS); 733 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 734 "inactive"); 735 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 736 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 737 onoff("User Definable Features (UDF) support", rval, 738 PCI_STATUS_UDF_SUPPORT); 739 onoff("Fast back-to-back capable", rval, 740 PCI_STATUS_BACKTOBACK_SUPPORT); 741 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 742 743 printf(" DEVSEL timing: "); 744 switch (rval & PCI_STATUS_DEVSEL_MASK) { 745 case PCI_STATUS_DEVSEL_FAST: 746 printf("fast"); 747 break; 748 case PCI_STATUS_DEVSEL_MEDIUM: 749 printf("medium"); 750 break; 751 case PCI_STATUS_DEVSEL_SLOW: 752 printf("slow"); 753 break; 754 default: 755 printf("unknown/reserved"); /* XXX */ 756 break; 757 } 758 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 759 760 onoff("Slave signaled Target Abort", rval, 761 PCI_STATUS_TARGET_TARGET_ABORT); 762 onoff("Master received Target Abort", rval, 763 PCI_STATUS_MASTER_TARGET_ABORT); 764 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 765 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 766 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 767 768 rval = regs[o2i(PCI_CLASS_REG)]; 769 for (classp = pci_class; classp->name != NULL; classp++) { 770 if (PCI_CLASS(rval) == classp->val) 771 break; 772 } 773 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 774 while (subclassp && subclassp->name != NULL) { 775 if (PCI_SUBCLASS(rval) == subclassp->val) 776 break; 777 subclassp++; 778 } 779 if (classp->name != NULL) { 780 printf(" Class Name: %s (0x%02x)\n", classp->name, 781 PCI_CLASS(rval)); 782 if (subclassp != NULL && subclassp->name != NULL) 783 printf(" Subclass Name: %s (0x%02x)\n", 784 subclassp->name, PCI_SUBCLASS(rval)); 785 else 786 printf(" Subclass ID: 0x%02x\n", 787 PCI_SUBCLASS(rval)); 788 } else { 789 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 790 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 791 } 792 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 793 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 794 795 rval = regs[o2i(PCI_BHLC_REG)]; 796 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 797 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 798 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 799 PCI_HDRTYPE(rval)); 800 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 801 num = PCI_CACHELINE(rval); 802 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 803 } 804 805 static int 806 pci_conf_print_bar( 807 #ifdef _KERNEL 808 pci_chipset_tag_t pc, pcitag_t tag, 809 #endif 810 const pcireg_t *regs, int reg, const char *name 811 #ifdef _KERNEL 812 , int sizebar 813 #endif 814 ) 815 { 816 int width; 817 pcireg_t rval, rval64h; 818 #ifdef _KERNEL 819 int s; 820 pcireg_t mask, mask64h; 821 #endif 822 823 width = 4; 824 825 /* 826 * Section 6.2.5.1, `Address Maps', tells us that: 827 * 828 * 1) The builtin software should have already mapped the 829 * device in a reasonable way. 830 * 831 * 2) A device which wants 2^n bytes of memory will hardwire 832 * the bottom n bits of the address to 0. As recommended, 833 * we write all 1s and see what we get back. 834 */ 835 836 rval = regs[o2i(reg)]; 837 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 838 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 839 rval64h = regs[o2i(reg + 4)]; 840 width = 8; 841 } else 842 rval64h = 0; 843 844 #ifdef _KERNEL 845 /* XXX don't size unknown memory type? */ 846 if (rval != 0 && sizebar) { 847 /* 848 * The following sequence seems to make some devices 849 * (e.g. host bus bridges, which don't normally 850 * have their space mapped) very unhappy, to 851 * the point of crashing the system. 852 * 853 * Therefore, if the mapping register is zero to 854 * start out with, don't bother trying. 855 */ 856 s = splhigh(); 857 pci_conf_write(pc, tag, reg, 0xffffffff); 858 mask = pci_conf_read(pc, tag, reg); 859 pci_conf_write(pc, tag, reg, rval); 860 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 861 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 862 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 863 mask64h = pci_conf_read(pc, tag, reg + 4); 864 pci_conf_write(pc, tag, reg + 4, rval64h); 865 } else 866 mask64h = 0; 867 splx(s); 868 } else 869 mask = mask64h = 0; 870 #endif /* _KERNEL */ 871 872 printf(" Base address register at 0x%02x", reg); 873 if (name) 874 printf(" (%s)", name); 875 printf("\n "); 876 if (rval == 0) { 877 printf("not implemented(?)\n"); 878 return width; 879 } 880 printf("type: "); 881 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 882 const char *type, *prefetch; 883 884 switch (PCI_MAPREG_MEM_TYPE(rval)) { 885 case PCI_MAPREG_MEM_TYPE_32BIT: 886 type = "32-bit"; 887 break; 888 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 889 type = "32-bit-1M"; 890 break; 891 case PCI_MAPREG_MEM_TYPE_64BIT: 892 type = "64-bit"; 893 break; 894 default: 895 type = "unknown (XXX)"; 896 break; 897 } 898 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 899 prefetch = ""; 900 else 901 prefetch = "non"; 902 printf("%s %sprefetchable memory\n", type, prefetch); 903 switch (PCI_MAPREG_MEM_TYPE(rval)) { 904 case PCI_MAPREG_MEM_TYPE_64BIT: 905 printf(" base: 0x%016llx, ", 906 PCI_MAPREG_MEM64_ADDR( 907 ((((long long) rval64h) << 32) | rval))); 908 #ifdef _KERNEL 909 if (sizebar) 910 printf("size: 0x%016llx", 911 PCI_MAPREG_MEM64_SIZE( 912 ((((long long) mask64h) << 32) | mask))); 913 else 914 #endif /* _KERNEL */ 915 printf("not sized"); 916 printf("\n"); 917 break; 918 case PCI_MAPREG_MEM_TYPE_32BIT: 919 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 920 default: 921 printf(" base: 0x%08x, ", 922 PCI_MAPREG_MEM_ADDR(rval)); 923 #ifdef _KERNEL 924 if (sizebar) 925 printf("size: 0x%08x", 926 PCI_MAPREG_MEM_SIZE(mask)); 927 else 928 #endif /* _KERNEL */ 929 printf("not sized"); 930 printf("\n"); 931 break; 932 } 933 } else { 934 #ifdef _KERNEL 935 if (sizebar) 936 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 937 #endif /* _KERNEL */ 938 printf("i/o\n"); 939 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 940 #ifdef _KERNEL 941 if (sizebar) 942 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 943 else 944 #endif /* _KERNEL */ 945 printf("not sized"); 946 printf("\n"); 947 } 948 949 return width; 950 } 951 952 static void 953 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 954 { 955 int off, needaddr, neednl; 956 957 needaddr = 1; 958 neednl = 0; 959 for (off = first; off < pastlast; off += 4) { 960 if ((off % 16) == 0 || needaddr) { 961 printf(" 0x%02x:", off); 962 needaddr = 0; 963 } 964 printf(" 0x%08x", regs[o2i(off)]); 965 neednl = 1; 966 if ((off % 16) == 12) { 967 printf("\n"); 968 neednl = 0; 969 } 970 } 971 if (neednl) 972 printf("\n"); 973 } 974 975 static void 976 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 977 { 978 pcireg_t rval; 979 980 printf("\n AGP Capabilities Register\n"); 981 982 rval = regs[o2i(capoff)]; 983 printf(" Revision: %d.%d\n", 984 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 985 986 /* XXX need more */ 987 } 988 989 static const char * 990 pci_conf_print_pcipm_cap_aux(uint16_t caps) 991 { 992 993 switch ((caps >> 6) & 7) { 994 case 0: return "self-powered"; 995 case 1: return "55 mA"; 996 case 2: return "100 mA"; 997 case 3: return "160 mA"; 998 case 4: return "220 mA"; 999 case 5: return "270 mA"; 1000 case 6: return "320 mA"; 1001 case 7: 1002 default: return "375 mA"; 1003 } 1004 } 1005 1006 static const char * 1007 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1008 { 1009 static const char unk[] = "unknown"; 1010 static const char *pmrev[8] = { 1011 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1012 }; 1013 if (val > 7) 1014 return unk; 1015 return pmrev[val]; 1016 } 1017 1018 static void 1019 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1020 { 1021 uint16_t caps, pmcsr; 1022 pcireg_t reg; 1023 1024 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1025 reg = regs[o2i(capoff + PCI_PMCSR)]; 1026 pmcsr = reg & 0xffff; 1027 1028 printf("\n PCI Power Management Capabilities Register\n"); 1029 1030 printf(" Capabilities register: 0x%04x\n", caps); 1031 printf(" Version: %s\n", 1032 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1033 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1034 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1035 printf(" 3.3V auxiliary current: %s\n", 1036 pci_conf_print_pcipm_cap_aux(caps)); 1037 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1038 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1039 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1040 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1041 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1042 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1043 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1044 1045 printf(" Control/status register: 0x%04x\n", pmcsr); 1046 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1047 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1048 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1049 printf(" PME# assertion: %sabled\n", 1050 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1051 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1052 printf(" Bridge Support Extensions register: 0x%02x\n", 1053 (reg >> 16) & 0xff); 1054 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1055 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1056 printf(" Data register: 0x%02x\n", (reg >> 24) & 0xff); 1057 1058 } 1059 1060 /* XXX pci_conf_print_vpd_cap */ 1061 /* XXX pci_conf_print_slotid_cap */ 1062 1063 static void 1064 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1065 { 1066 uint32_t ctl, mmc, mme; 1067 1068 regs += o2i(capoff); 1069 ctl = *regs++; 1070 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1071 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1072 1073 printf("\n PCI Message Signaled Interrupt\n"); 1074 1075 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1076 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1077 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1078 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1079 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1080 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1081 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1082 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1083 onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP); 1084 onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN); 1085 printf(" Message Address %sregister: 0x%08x\n", 1086 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1087 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1088 printf(" Message Address %sregister: 0x%08x\n", 1089 "(upper) ", *regs++); 1090 } 1091 printf(" Message Data register: 0x%08x\n", *regs++); 1092 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1093 printf(" Vector Mask register: 0x%08x\n", *regs++); 1094 printf(" Vector Pending register: 0x%08x\n", *regs++); 1095 } 1096 } 1097 1098 /* XXX pci_conf_print_cpci_hostwap_cap */ 1099 1100 /* 1101 * For both command register and status register. 1102 * The argument "idx" is index number (0 to 7). 1103 */ 1104 static int 1105 pcix_split_trans(unsigned int idx) 1106 { 1107 static int table[8] = { 1108 1, 2, 3, 4, 8, 12, 16, 32 1109 }; 1110 1111 if (idx >= __arraycount(table)) 1112 return -1; 1113 return table[idx]; 1114 } 1115 1116 static void 1117 pci_conf_print_pcix_cap_2ndbusmode(int num) 1118 { 1119 const char *maxfreq, *maxperiod; 1120 1121 printf(" Mode: "); 1122 if (num <= 0x07) 1123 printf("PCI-X Mode 1\n"); 1124 else if (num <= 0x0b) 1125 printf("PCI-X 266 (Mode 2)\n"); 1126 else 1127 printf("PCI-X 533 (Mode 2)\n"); 1128 1129 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1130 switch (num & 0x03) { 1131 default: 1132 case 0: 1133 maxfreq = "N/A"; 1134 maxperiod = "N/A"; 1135 break; 1136 case 1: 1137 maxfreq = "66MHz"; 1138 maxperiod = "15ns"; 1139 break; 1140 case 2: 1141 maxfreq = "100MHz"; 1142 maxperiod = "10ns"; 1143 break; 1144 case 3: 1145 maxfreq = "133MHz"; 1146 maxperiod = "7.5ns"; 1147 break; 1148 } 1149 printf(" Max Clock Freq: %s\n", maxfreq); 1150 printf(" Min Clock Period: %s\n", maxperiod); 1151 } 1152 1153 static void 1154 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1155 { 1156 pcireg_t reg; 1157 int isbridge; 1158 int i; 1159 1160 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1161 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1162 printf("\n PCI-X %s Capabilities Register\n", 1163 isbridge ? "Bridge" : "Non-bridge"); 1164 1165 reg = regs[o2i(capoff)]; 1166 if (isbridge != 0) { 1167 printf(" Secondary status register: 0x%04x\n", 1168 (reg & 0xffff0000) >> 16); 1169 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1170 onoff("133MHz capable", reg, PCIX_STATUS_133); 1171 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1172 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1173 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1174 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1175 pci_conf_print_pcix_cap_2ndbusmode( 1176 __SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1177 printf(" Version: 0x%x\n", 1178 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1179 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1180 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1181 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1182 } else { 1183 printf(" Command register: 0x%04x\n", 1184 (reg & 0xffff0000) >> 16); 1185 onoff("Data Parity Error Recovery", reg, 1186 PCIX_CMD_PERR_RECOVER); 1187 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1188 printf(" Maximum Burst Read Count: %u\n", 1189 PCIX_CMD_BYTECNT(reg)); 1190 printf(" Maximum Split Transactions: %d\n", 1191 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1192 >> PCIX_CMD_SPLTRANS_SHIFT)); 1193 } 1194 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1195 printf(" %sStatus register: 0x%08x\n", 1196 isbridge ? "Bridge " : "", reg); 1197 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1198 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1199 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1200 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1201 onoff("133MHz capable", reg, PCIX_STATUS_133); 1202 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1203 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1204 if (isbridge != 0) { 1205 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1206 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1207 } else { 1208 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1209 "bridge device", "simple device"); 1210 printf(" Designed max memory read byte count: %d\n", 1211 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1212 >> PCIX_STATUS_MAXB_SHIFT)); 1213 printf(" Designed max outstanding split transaction: %d\n", 1214 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1215 >> PCIX_STATUS_MAXST_SHIFT)); 1216 printf(" MAX cumulative Read Size: %u\n", 1217 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1218 onoff("Received split completion error", reg, 1219 PCIX_STATUS_SCERR); 1220 } 1221 onoff("266MHz capable", reg, PCIX_STATUS_266); 1222 onoff("533MHz capable", reg, PCIX_STATUS_533); 1223 1224 if (isbridge == 0) 1225 return; 1226 1227 /* Only for bridge */ 1228 for (i = 0; i < 2; i++) { 1229 reg = regs[o2i(capoff+PCIX_BRIDGE_UP_STCR + (4 * i))]; 1230 printf(" %s split transaction control register: 0x%08x\n", 1231 (i == 0) ? "Upstream" : "Downstream", reg); 1232 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1233 printf(" Commitment Limit: %d\n", 1234 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1235 } 1236 } 1237 1238 /* pci_conf_print_ht_slave_cap */ 1239 /* pci_conf_print_ht_host_cap */ 1240 /* pci_conf_print_ht_switch_cap */ 1241 /* pci_conf_print_ht_intr_cap */ 1242 /* pci_conf_print_ht_revid_cap */ 1243 /* pci_conf_print_ht_unitid_cap */ 1244 /* pci_conf_print_ht_extcnf_cap */ 1245 /* pci_conf_print_ht_addrmap_cap */ 1246 /* pci_conf_print_ht_msimap_cap */ 1247 1248 static void 1249 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1250 { 1251 pcireg_t val; 1252 uint32_t lo, hi; 1253 1254 /* 1255 * Print the rest of the command register bits. Others are 1256 * printed in pci_conf_print_ht_cap(). 1257 */ 1258 val = regs[o2i(capoff + PCI_HT_CMD)]; 1259 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1260 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1261 1262 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1263 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1264 printf(" Address Low register: 0x%08x\n", lo); 1265 printf(" Address high register: 0x%08x\n", hi); 1266 printf(" Address: 0x%016" PRIx64 "\n", 1267 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1268 } 1269 1270 /* pci_conf_print_ht_droute_cap */ 1271 /* pci_conf_print_ht_vcset_cap */ 1272 /* pci_conf_print_ht_retry_cap */ 1273 /* pci_conf_print_ht_x86enc_cap */ 1274 /* pci_conf_print_ht_gen3_cap */ 1275 /* pci_conf_print_ht_fle_cap */ 1276 /* pci_conf_print_ht_pm_cap */ 1277 /* pci_conf_print_ht_hnc_cap */ 1278 1279 static const struct ht_types { 1280 pcireg_t cap; 1281 const char *name; 1282 void (*printfunc)(const pcireg_t *, int); 1283 } ht_captab[] = { 1284 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1285 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1286 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1287 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1288 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1289 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1290 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1291 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1292 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1293 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1294 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1295 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1296 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1297 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1298 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1299 {PCI_HT_CAP_PM, "Power Management", NULL }, 1300 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1301 }; 1302 1303 static void 1304 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1305 { 1306 pcireg_t val, foundcap; 1307 unsigned int off; 1308 1309 val = regs[o2i(capoff + PCI_HT_CMD)]; 1310 1311 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1312 1313 printf(" Command register: 0x%04x\n", val >> 16); 1314 foundcap = PCI_HT_CAP(val); 1315 for (off = 0; off < __arraycount(ht_captab); off++) { 1316 if (ht_captab[off].cap == foundcap) 1317 break; 1318 } 1319 printf(" Capability Type: 0x%02x ", foundcap); 1320 if (off >= __arraycount(ht_captab)) { 1321 printf("(unknown)\n"); 1322 return; 1323 } 1324 printf("(%s)\n", ht_captab[off].name); 1325 if (ht_captab[off].printfunc != NULL) 1326 ht_captab[off].printfunc(regs, capoff); 1327 } 1328 1329 static void 1330 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1331 { 1332 uint16_t caps; 1333 1334 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1335 1336 printf("\n PCI Vendor Specific Capabilities Register\n"); 1337 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1338 } 1339 1340 static void 1341 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1342 { 1343 pcireg_t val; 1344 1345 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1346 1347 printf("\n Debugport Capability Register\n"); 1348 printf(" Debug base Register: 0x%04x\n", 1349 val >> PCI_DEBUG_BASER_SHIFT); 1350 printf(" port offset: 0x%04x\n", 1351 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1352 printf(" BAR number: %u\n", 1353 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1354 } 1355 1356 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1357 /* XXX pci_conf_print_hotplug_cap */ 1358 1359 static void 1360 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1361 { 1362 pcireg_t reg; 1363 1364 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1365 1366 printf("\n Subsystem ID Capability Register\n"); 1367 printf(" Subsystem ID : 0x%08x\n", reg); 1368 } 1369 1370 /* XXX pci_conf_print_agp8_cap */ 1371 /* XXX pci_conf_print_secure_cap */ 1372 1373 static void 1374 pci_print_pcie_L0s_latency(uint32_t val) 1375 { 1376 1377 switch (val) { 1378 case 0x0: 1379 printf("Less than 64ns\n"); 1380 break; 1381 case 0x1: 1382 case 0x2: 1383 case 0x3: 1384 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1385 break; 1386 case 0x4: 1387 printf("512ns to less than 1us\n"); 1388 break; 1389 case 0x5: 1390 printf("1us to less than 2us\n"); 1391 break; 1392 case 0x6: 1393 printf("2us - 4us\n"); 1394 break; 1395 case 0x7: 1396 printf("More than 4us\n"); 1397 break; 1398 } 1399 } 1400 1401 static void 1402 pci_print_pcie_L1_latency(uint32_t val) 1403 { 1404 1405 switch (val) { 1406 case 0x0: 1407 printf("Less than 1us\n"); 1408 break; 1409 case 0x6: 1410 printf("32us - 64us\n"); 1411 break; 1412 case 0x7: 1413 printf("More than 64us\n"); 1414 break; 1415 default: 1416 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1417 break; 1418 } 1419 } 1420 1421 static void 1422 pci_print_pcie_compl_timeout(uint32_t val) 1423 { 1424 1425 switch (val) { 1426 case 0x0: 1427 printf("50us to 50ms\n"); 1428 break; 1429 case 0x5: 1430 printf("16ms to 55ms\n"); 1431 break; 1432 case 0x6: 1433 printf("65ms to 210ms\n"); 1434 break; 1435 case 0x9: 1436 printf("260ms to 900ms\n"); 1437 break; 1438 case 0xa: 1439 printf("1s to 3.5s\n"); 1440 break; 1441 default: 1442 printf("unknown %u value\n", val); 1443 break; 1444 } 1445 } 1446 1447 static const char * const pcie_linkspeeds[] = {"2.5", "5.0", "8.0"}; 1448 1449 static void 1450 pci_print_pcie_linkspeed(pcireg_t val) 1451 { 1452 1453 /* Start from 1 */ 1454 if (val < 1 || val > __arraycount(pcie_linkspeeds)) 1455 printf("unknown value (%u)\n", val); 1456 else 1457 printf("%sGT/s\n", pcie_linkspeeds[val - 1]); 1458 } 1459 1460 static void 1461 pci_print_pcie_linkspeedvector(pcireg_t val) 1462 { 1463 unsigned int i; 1464 1465 /* Start from 0 */ 1466 for (i = 0; i < 16; i++) 1467 if (((val >> i) & 0x01) != 0) { 1468 if (i >= __arraycount(pcie_linkspeeds)) 1469 printf(" unknown vector (%x)", 1 << i); 1470 else 1471 printf(" %sGT/s", pcie_linkspeeds[i]); 1472 } 1473 } 1474 1475 static void 1476 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1477 { 1478 pcireg_t reg; /* for each register */ 1479 pcireg_t val; /* for each bitfield */ 1480 bool check_link = false; 1481 bool check_slot = false; 1482 bool check_rootport = false; 1483 unsigned int pciever; 1484 1485 printf("\n PCI Express Capabilities Register\n"); 1486 /* Capability Register */ 1487 reg = regs[o2i(capoff)]; 1488 printf(" Capability register: %04x\n", reg >> 16); 1489 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1490 printf(" Capability version: %u\n", pciever); 1491 printf(" Device type: "); 1492 switch ((reg & 0x00f00000) >> 20) { 1493 case 0x0: 1494 printf("PCI Express Endpoint device\n"); 1495 check_link = true; 1496 break; 1497 case 0x1: 1498 printf("Legacy PCI Express Endpoint device\n"); 1499 check_link = true; 1500 break; 1501 case 0x4: 1502 printf("Root Port of PCI Express Root Complex\n"); 1503 check_link = true; 1504 check_slot = true; 1505 check_rootport = true; 1506 break; 1507 case 0x5: 1508 printf("Upstream Port of PCI Express Switch\n"); 1509 break; 1510 case 0x6: 1511 printf("Downstream Port of PCI Express Switch\n"); 1512 check_slot = true; 1513 check_rootport = true; 1514 break; 1515 case 0x7: 1516 printf("PCI Express to PCI/PCI-X Bridge\n"); 1517 break; 1518 case 0x8: 1519 printf("PCI/PCI-X to PCI Express Bridge\n"); 1520 break; 1521 case 0x9: 1522 printf("Root Complex Integrated Endpoint\n"); 1523 break; 1524 case 0xa: 1525 check_rootport = true; 1526 printf("Root Complex Event Collector\n"); 1527 break; 1528 default: 1529 printf("unknown\n"); 1530 break; 1531 } 1532 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1533 printf(" Interrupt Message Number: %x\n", 1534 (unsigned int)((reg & PCIE_XCAP_IRQ) >> 27)); 1535 1536 /* Device Capability Register */ 1537 reg = regs[o2i(capoff + PCIE_DCAP)]; 1538 printf(" Device Capabilities Register: 0x%08x\n", reg); 1539 printf(" Max Payload Size Supported: %u bytes max\n", 1540 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1541 printf(" Phantom Functions Supported: "); 1542 switch ((reg & PCIE_DCAP_PHANTOM_FUNCS) >> 3) { 1543 case 0x0: 1544 printf("not available\n"); 1545 break; 1546 case 0x1: 1547 printf("MSB\n"); 1548 break; 1549 case 0x2: 1550 printf("two MSB\n"); 1551 break; 1552 case 0x3: 1553 printf("All three bits\n"); 1554 break; 1555 } 1556 printf(" Extended Tag Field Supported: %dbit\n", 1557 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1558 printf(" Endpoint L0 Acceptable Latency: "); 1559 pci_print_pcie_L0s_latency((reg & PCIE_DCAP_L0S_LATENCY) >> 6); 1560 printf(" Endpoint L1 Acceptable Latency: "); 1561 pci_print_pcie_L1_latency((reg & PCIE_DCAP_L1_LATENCY) >> 9); 1562 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1563 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1564 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1565 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1566 printf(" Captured Slot Power Limit Value: %d\n", 1567 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18); 1568 printf(" Captured Slot Power Limit Scale: %d\n", 1569 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26); 1570 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1571 1572 /* Device Control Register */ 1573 reg = regs[o2i(capoff + PCIE_DCSR)]; 1574 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1575 onoff("Correctable Error Reporting Enable", reg, 1576 PCIE_DCSR_ENA_COR_ERR); 1577 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1578 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1579 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1580 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1581 printf(" Max Payload Size: %d byte\n", 1582 128 << (((unsigned int)(reg & PCIE_DCSR_MAX_PAYLOAD) >> 5))); 1583 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1584 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1585 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1586 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1587 printf(" Max Read Request Size: %d byte\n", 1588 128 << ((unsigned int)(reg & PCIE_DCSR_MAX_READ_REQ) >> 12)); 1589 1590 /* Device Status Register */ 1591 reg = regs[o2i(capoff + PCIE_DCSR)]; 1592 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1593 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1594 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1595 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1596 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1597 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1598 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1599 onoff("Emergency Power Reduction Detected", reg, 1600 PCIE_DCSR_EMGPWRREDD); 1601 1602 if (check_link) { 1603 /* Link Capability Register */ 1604 reg = regs[o2i(capoff + PCIE_LCAP)]; 1605 printf(" Link Capabilities Register: 0x%08x\n", reg); 1606 printf(" Maximum Link Speed: "); 1607 pci_print_pcie_linkspeed(reg & PCIE_LCAP_MAX_SPEED); 1608 printf(" Maximum Link Width: x%u lanes\n", 1609 (unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4); 1610 printf(" Active State PM Support: "); 1611 val = (reg & PCIE_LCAP_ASPM) >> 10; 1612 switch (val) { 1613 case 0x0: 1614 printf("No ASPM support\n"); 1615 break; 1616 case 0x1: 1617 printf("L0s supported\n"); 1618 break; 1619 case 0x2: 1620 printf("L1 supported\n"); 1621 break; 1622 case 0x3: 1623 printf("L0s and L1 supported\n"); 1624 break; 1625 } 1626 printf(" L0 Exit Latency: "); 1627 pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12); 1628 printf(" L1 Exit Latency: "); 1629 pci_print_pcie_L1_latency((reg & PCIE_LCAP_L1_EXIT) >> 15); 1630 printf(" Port Number: %u\n", reg >> 24); 1631 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1632 onoff("Surprise Down Error Report", reg, 1633 PCIE_LCAP_SURPRISE_DOWN); 1634 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1635 onoff("Link BW Notification Capable", reg, 1636 PCIE_LCAP_LINK_BW_NOTIFY); 1637 onoff("ASPM Optionally Compliance", reg, 1638 PCIE_LCAP_ASPM_COMPLIANCE); 1639 1640 /* Link Control Register */ 1641 reg = regs[o2i(capoff + PCIE_LCSR)]; 1642 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1643 printf(" Active State PM Control: "); 1644 val = reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S); 1645 switch (val) { 1646 case 0: 1647 printf("disabled\n"); 1648 break; 1649 case 1: 1650 printf("L0s Entry Enabled\n"); 1651 break; 1652 case 2: 1653 printf("L1 Entry Enabled\n"); 1654 break; 1655 case 3: 1656 printf("L0s and L1 Entry Enabled\n"); 1657 break; 1658 } 1659 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1660 "128bytes", "64bytes"); 1661 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1662 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1663 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1664 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1665 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1666 onoff("Hardware Autonomous Width Disable", reg, 1667 PCIE_LCSR_HAWD); 1668 onoff("Link Bandwidth Management Interrupt Enable", reg, 1669 PCIE_LCSR_LBMIE); 1670 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1671 PCIE_LCSR_LABIE); 1672 printf(" DRS Signaling Control: "); 1673 val = __SHIFTOUT(reg, PCIE_LCSR_DRSSGNL); 1674 switch (val) { 1675 case 0: 1676 printf("not reported\n"); 1677 break; 1678 case 1: 1679 printf("Interrupt Enabled\n"); 1680 break; 1681 case 2: 1682 printf("DRS to FRS Signaling Enabled\n"); 1683 break; 1684 default: 1685 printf("reserved\n"); 1686 break; 1687 } 1688 1689 /* Link Status Register */ 1690 reg = regs[o2i(capoff + PCIE_LCSR)]; 1691 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1692 printf(" Negotiated Link Speed: "); 1693 pci_print_pcie_linkspeed(__SHIFTOUT(reg, PCIE_LCSR_LINKSPEED)); 1694 printf(" Negotiated Link Width: x%u lanes\n", 1695 (reg >> 20) & 0x003f); 1696 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1697 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1698 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1699 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1700 onoff("Link Bandwidth Management Status", reg, 1701 PCIE_LCSR_LINK_BW_MGMT); 1702 onoff("Link Autonomous Bandwidth Status", reg, 1703 PCIE_LCSR_LINK_AUTO_BW); 1704 } 1705 1706 if (check_slot == true) { 1707 /* Slot Capability Register */ 1708 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1709 printf(" Slot Capability Register: %08x\n", reg); 1710 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1711 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1712 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1713 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1714 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1715 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1716 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1717 printf(" Slot Power Limit Value: %d\n", 1718 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1719 printf(" Slot Power Limit Scale: %d\n", 1720 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1721 onoff("Electromechanical Interlock Present", reg, 1722 PCIE_SLCAP_EIP); 1723 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1724 printf(" Physical Slot Number: %d\n", 1725 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1726 1727 /* Slot Control Register */ 1728 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1729 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1730 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1731 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1732 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1733 onoff("Presense Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1734 onoff("Command Completed Interrupt Enabled", reg, 1735 PCIE_SLCSR_CCE); 1736 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1737 printf(" Attention Indicator Control: "); 1738 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1739 case 0x0: 1740 printf("reserved\n"); 1741 break; 1742 case 0x1: 1743 printf("on\n"); 1744 break; 1745 case 0x2: 1746 printf("blink\n"); 1747 break; 1748 case 0x3: 1749 printf("off\n"); 1750 break; 1751 } 1752 printf(" Power Indicator Control: "); 1753 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1754 case 0x0: 1755 printf("reserved\n"); 1756 break; 1757 case 0x1: 1758 printf("on\n"); 1759 break; 1760 case 0x2: 1761 printf("blink\n"); 1762 break; 1763 case 0x3: 1764 printf("off\n"); 1765 break; 1766 } 1767 onoff("Power Controller Control", reg, PCIE_SLCSR_PCC); 1768 onoff("Electromechanical Interlock Control", 1769 reg, PCIE_SLCSR_EIC); 1770 onoff("Data Link Layer State Changed Enable", reg, 1771 PCIE_SLCSR_DLLSCE); 1772 onoff("Auto Slot Power Limit Disable", reg, 1773 PCIE_SLCSR_AUTOSPLDIS); 1774 1775 /* Slot Status Register */ 1776 printf(" Slot Status Register: %04x\n", reg >> 16); 1777 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1778 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1779 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1780 onoff("Presense Detect Changed", reg, PCIE_SLCSR_PDC); 1781 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1782 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1783 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1784 onoff("Electromechanical Interlock engaged", reg, 1785 PCIE_SLCSR_EIS); 1786 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 1787 } 1788 1789 if (check_rootport == true) { 1790 /* Root Control Register */ 1791 reg = regs[o2i(capoff + PCIE_RCR)]; 1792 printf(" Root Control Register: %04x\n", reg & 0xffff); 1793 onoff("SERR on Correctable Error Enable", reg, 1794 PCIE_RCR_SERR_CER); 1795 onoff("SERR on Non-Fatal Error Enable", reg, 1796 PCIE_RCR_SERR_NFER); 1797 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 1798 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 1799 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 1800 1801 /* Root Capability Register */ 1802 printf(" Root Capability Register: %04x\n", 1803 reg >> 16); 1804 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 1805 1806 /* Root Status Register */ 1807 reg = regs[o2i(capoff + PCIE_RSR)]; 1808 printf(" Root Status Register: %08x\n", reg); 1809 printf(" PME Requester ID: %04x\n", 1810 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1811 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 1812 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 1813 } 1814 1815 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1816 if (pciever < 2) 1817 return; 1818 1819 /* Device Capabilities 2 */ 1820 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1821 printf(" Device Capabilities 2: 0x%08x\n", reg); 1822 printf(" Completion Timeout Ranges Supported: %u \n", 1823 (unsigned int)(reg & PCIE_DCAP2_COMPT_RANGE)); 1824 onoff("Completion Timeout Disable Supported", reg, 1825 PCIE_DCAP2_COMPT_DIS); 1826 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 1827 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 1828 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 1829 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 1830 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 1831 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 1832 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 1833 printf(" TPH Completer Supported: %u\n", 1834 (unsigned int)(reg & PCIE_DCAP2_TPH_COMP) >> 12); 1835 printf(" LN System CLS: "); 1836 switch (__SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 1837 case 0x0: 1838 printf("Not supported or not in effect\n"); 1839 break; 1840 case 0x1: 1841 printf("64byte cachelines in effect\n"); 1842 break; 1843 case 0x2: 1844 printf("128byte cachelines in effect\n"); 1845 break; 1846 case 0x3: 1847 printf("Reserved\n"); 1848 break; 1849 } 1850 printf(" OBFF Supported: "); 1851 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 1852 case 0x0: 1853 printf("Not supported\n"); 1854 break; 1855 case 0x1: 1856 printf("Message only\n"); 1857 break; 1858 case 0x2: 1859 printf("WAKE# only\n"); 1860 break; 1861 case 0x3: 1862 printf("Both\n"); 1863 break; 1864 } 1865 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 1866 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 1867 printf(" Max End-End TLP Prefixes: %u\n", 1868 (unsigned int)(reg & PCIE_DCAP2_MAX_EETLP) >> 22); 1869 printf(" Emergency Power Reduction Supported: "); 1870 switch (__SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) { 1871 case 0x0: 1872 printf("Not supported\n"); 1873 break; 1874 case 0x1: 1875 printf("Device Specific mechanism\n"); 1876 break; 1877 case 0x2: 1878 printf("Form Factor spec or Device Specific mechanism\n"); 1879 break; 1880 case 0x3: 1881 printf("Reserved\n"); 1882 break; 1883 } 1884 onoff("Emergency Power Reduction Initialization Required", reg, 1885 PCIE_DCAP2_EMGPWRRED_INI); 1886 onoff("FRS Supported", reg, PCIE_DCAP2_FRS); 1887 1888 /* Device Control 2 */ 1889 reg = regs[o2i(capoff + PCIE_DCSR2)]; 1890 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 1891 printf(" Completion Timeout Value: "); 1892 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 1893 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 1894 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 1895 onoff("AtomicOp Rquester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 1896 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 1897 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 1898 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 1899 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 1900 onoff("Emergency Power Reduction Request", reg, 1901 PCIE_DCSR2_EMGPWRRED_REQ); 1902 printf(" OBFF: "); 1903 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 1904 case 0x0: 1905 printf("Disabled\n"); 1906 break; 1907 case 0x1: 1908 printf("Enabled with Message Signaling Variation A\n"); 1909 break; 1910 case 0x2: 1911 printf("Enabled with Message Signaling Variation B\n"); 1912 break; 1913 case 0x3: 1914 printf("Enabled using WAKE# signaling\n"); 1915 break; 1916 } 1917 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 1918 1919 if (check_link) { 1920 bool drs_supported; 1921 1922 /* Link Capability 2 */ 1923 reg = regs[o2i(capoff + PCIE_LCAP2)]; 1924 printf(" Link Capabilities 2: 0x%08x\n", reg); 1925 printf(" Supported Link Speed Vector:"); 1926 pci_print_pcie_linkspeedvector( 1927 __SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV)); 1928 printf("\n"); 1929 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 1930 printf(" Lower SKP OS Generation Supported Speed Vector:"); 1931 pci_print_pcie_linkspeedvector( 1932 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV)); 1933 printf("\n"); 1934 printf(" Lower SKP OS Reception Supported Speed Vector:"); 1935 pci_print_pcie_linkspeedvector( 1936 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV)); 1937 printf("\n"); 1938 onoff("DRS Supported", reg, PCIE_LCAP2_DRS); 1939 drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false; 1940 1941 /* Link Control 2 */ 1942 reg = regs[o2i(capoff + PCIE_LCSR2)]; 1943 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 1944 printf(" Target Link Speed: "); 1945 pci_print_pcie_linkspeed(__SHIFTOUT(reg, 1946 PCIE_LCSR2_TGT_LSPEED)); 1947 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 1948 onoff("HW Autonomous Speed Disabled", reg, 1949 PCIE_LCSR2_HW_AS_DIS); 1950 onoff("Selectable De-emphasis", reg, PCIE_LCSR2_SEL_DEEMP); 1951 printf(" Transmit Margin: %u\n", 1952 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 1953 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 1954 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 1955 printf(" Compliance Present/De-emphasis: %u\n", 1956 (unsigned int)(reg & PCIE_LCSR2_COMP_DEEMP) >> 12); 1957 1958 /* Link Status 2 */ 1959 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 1960 onoff("Current De-emphasis Level", reg, PCIE_LCSR2_DEEMP_LVL); 1961 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 1962 onoff("Equalization Phase 1 Successful", reg, 1963 PCIE_LCSR2_EQP1_SUC); 1964 onoff("Equalization Phase 2 Successful", reg, 1965 PCIE_LCSR2_EQP2_SUC); 1966 onoff("Equalization Phase 3 Successful", reg, 1967 PCIE_LCSR2_EQP3_SUC); 1968 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 1969 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD); 1970 if (drs_supported) { 1971 printf(" Downstream Component Presence: "); 1972 switch (__SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) { 1973 case PCIE_DSCOMPN_DOWN_NOTDETERM: 1974 printf("Link Down - Presence Not" 1975 " Determined\n"); 1976 break; 1977 case PCIE_DSCOMPN_DOWN_NOTPRES: 1978 printf("Link Down - Component Not Present\n"); 1979 break; 1980 case PCIE_DSCOMPN_DOWN_PRES: 1981 printf("Link Down - Component Present\n"); 1982 break; 1983 case PCIE_DSCOMPN_UP_PRES: 1984 printf("Link Up - Component Present\n"); 1985 break; 1986 case PCIE_DSCOMPN_UP_PRES_DRS: 1987 printf("Link Up - Component Present and DRS" 1988 " received\n"); 1989 break; 1990 default: 1991 printf("reserved\n"); 1992 break; 1993 } 1994 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV); 1995 } 1996 } 1997 1998 /* Slot Capability 2 */ 1999 /* Slot Control 2 */ 2000 /* Slot Status 2 */ 2001 } 2002 2003 static void 2004 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 2005 { 2006 pcireg_t reg; 2007 2008 printf("\n MSI-X Capability Register\n"); 2009 2010 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2011 printf(" Message Control register: 0x%04x\n", 2012 (reg >> 16) & 0xff); 2013 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 2014 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 2015 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 2016 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 2017 printf(" Table offset register: 0x%08x\n", reg); 2018 printf(" Table offset: %08x\n", 2019 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 2020 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 2021 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 2022 printf(" Pending bit array register: 0x%08x\n", reg); 2023 printf(" Pending bit array offset: %08x\n", 2024 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 2025 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 2026 } 2027 2028 static void 2029 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 2030 { 2031 pcireg_t reg; 2032 2033 printf("\n Serial ATA Capability Register\n"); 2034 2035 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2036 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 2037 printf(" Revision: %u.%u\n", 2038 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 2039 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 2040 2041 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 2042 2043 printf(" BAR Register: 0x%08x\n", reg); 2044 printf(" Register location: "); 2045 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 2046 printf("in config space\n"); 2047 else { 2048 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 2049 printf(" BAR offset: 0x%08x\n", 2050 (pcireg_t)__SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 2051 } 2052 } 2053 2054 static void 2055 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 2056 { 2057 pcireg_t reg; 2058 2059 printf("\n Advanced Features Capability Register\n"); 2060 2061 reg = regs[o2i(capoff + PCI_AFCAPR)]; 2062 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 2063 printf(" AF Structure Length: 0x%02x\n", 2064 (pcireg_t)__SHIFTOUT(reg, PCI_AF_LENGTH)); 2065 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 2066 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 2067 reg = regs[o2i(capoff + PCI_AFCSR)]; 2068 printf(" AF Control register: 0x%02x\n", reg & 0xff); 2069 /* 2070 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 2071 * and it's always 0 on read 2072 */ 2073 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 2074 onoff("Transaction Pending", reg, PCI_AFSR_TP); 2075 } 2076 2077 static struct { 2078 pcireg_t cap; 2079 const char *name; 2080 void (*printfunc)(const pcireg_t *, int); 2081 } pci_captab[] = { 2082 { PCI_CAP_RESERVED0, "reserved", NULL }, 2083 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 2084 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 2085 { PCI_CAP_VPD, "VPD", NULL }, 2086 { PCI_CAP_SLOTID, "SlotID", NULL }, 2087 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 2088 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 2089 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2090 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2091 { PCI_CAP_VENDSPEC, "Vendor-specific", 2092 pci_conf_print_vendspec_cap }, 2093 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2094 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2095 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2096 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2097 pci_conf_print_subsystem_cap }, 2098 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2099 { PCI_CAP_SECURE, "Secure Device", NULL }, 2100 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2101 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2102 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2103 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2104 { PCI_CAP_EA, "Enhanced Allocation", NULL } 2105 }; 2106 2107 static int 2108 pci_conf_find_cap(const pcireg_t *regs, int capoff, unsigned int capid, 2109 int *offsetp) 2110 { 2111 pcireg_t rval; 2112 int off; 2113 2114 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2115 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2116 rval = regs[o2i(off)]; 2117 if (capid == PCI_CAPLIST_CAP(rval)) { 2118 if (offsetp != NULL) 2119 *offsetp = off; 2120 return 1; 2121 } 2122 } 2123 return 0; 2124 } 2125 2126 static void 2127 pci_conf_print_caplist( 2128 #ifdef _KERNEL 2129 pci_chipset_tag_t pc, pcitag_t tag, 2130 #endif 2131 const pcireg_t *regs, int capoff) 2132 { 2133 int off; 2134 pcireg_t foundcap; 2135 pcireg_t rval; 2136 bool foundtable[__arraycount(pci_captab)]; 2137 unsigned int i; 2138 2139 /* Clear table */ 2140 for (i = 0; i < __arraycount(pci_captab); i++) 2141 foundtable[i] = false; 2142 2143 /* Print capability register's offset and the type first */ 2144 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2145 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2146 rval = regs[o2i(off)]; 2147 printf(" Capability register at 0x%02x\n", off); 2148 2149 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2150 foundcap = PCI_CAPLIST_CAP(rval); 2151 if (foundcap < __arraycount(pci_captab)) { 2152 printf("%s)\n", pci_captab[foundcap].name); 2153 /* Mark as found */ 2154 foundtable[foundcap] = true; 2155 } else 2156 printf("unknown)\n"); 2157 } 2158 2159 /* 2160 * And then, print the detail of each capability registers 2161 * in capability value's order. 2162 */ 2163 for (i = 0; i < __arraycount(pci_captab); i++) { 2164 if (foundtable[i] == false) 2165 continue; 2166 2167 /* 2168 * The type was found. Search capability list again and 2169 * print all capabilities that the capabiliy type is 2170 * the same. This is required because some capabilities 2171 * appear multiple times (e.g. HyperTransport capability). 2172 */ 2173 #if 0 2174 if (pci_conf_find_cap(regs, capoff, i, &off)) { 2175 rval = regs[o2i(off)]; 2176 if (pci_captab[i].printfunc != NULL) 2177 pci_captab[i].printfunc(regs, off); 2178 } 2179 #else 2180 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2181 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2182 rval = regs[o2i(off)]; 2183 if ((PCI_CAPLIST_CAP(rval) == i) 2184 && (pci_captab[i].printfunc != NULL)) 2185 pci_captab[i].printfunc(regs, off); 2186 } 2187 #endif 2188 } 2189 } 2190 2191 /* Extended Capability */ 2192 2193 static void 2194 pci_conf_print_aer_cap_uc(pcireg_t reg) 2195 { 2196 2197 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2198 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2199 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2200 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP); 2201 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2202 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2203 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2204 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2205 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2206 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2207 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2208 onoff("Unsupported Request Error", reg, 2209 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2210 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2211 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2212 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2213 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2214 onoff("TLP Prefix Blocked Error", reg, 2215 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2216 onoff("Poisoned TLP Egress Blocked", reg, 2217 PCI_AER_UC_POISONTLP_EGRESS_BLOCKED); 2218 } 2219 2220 static void 2221 pci_conf_print_aer_cap_cor(pcireg_t reg) 2222 { 2223 2224 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2225 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2226 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2227 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2228 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2229 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2230 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2231 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2232 } 2233 2234 static void 2235 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2236 { 2237 2238 printf(" First Error Pointer: 0x%04x\n", 2239 (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2240 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2241 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2242 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2243 onoff("ECRC Check Enab", reg, PCI_AER_ECRC_CHECK_ENABLE); 2244 onoff("Multiple Header Recording Capable", reg, 2245 PCI_AER_MULT_HDR_CAPABLE); 2246 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE); 2247 onoff("Completion Timeout Prefix/Header Log Capable", reg, 2248 PCI_AER_COMPTOUTPRFXHDRLOG_CAP); 2249 2250 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2251 if (!tlp_prefix_log) 2252 return; 2253 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2254 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2255 } 2256 2257 static void 2258 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2259 { 2260 2261 onoff("Correctable Error Reporting Enable", reg, 2262 PCI_AER_ROOTERR_COR_ENABLE); 2263 onoff("Non-Fatal Error Reporting Enable", reg, 2264 PCI_AER_ROOTERR_NF_ENABLE); 2265 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2266 } 2267 2268 static void 2269 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2270 { 2271 2272 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2273 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2274 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2275 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2276 PCI_AER_ROOTERR_MULTI_UC_ERR); 2277 onoff("First Uncorrectable Fatal", reg, PCI_AER_ROOTERR_FIRST_UC_FATAL); 2278 onoff("Non-Fatal Error Messages Received", reg, PCI_AER_ROOTERR_NF_ERR); 2279 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2280 printf(" Advanced Error Interrupt Message Number: 0x%u\n", 2281 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2282 } 2283 2284 static void 2285 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2286 { 2287 2288 printf(" Correctable Source ID: 0x%04x\n", 2289 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2290 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2291 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2292 } 2293 2294 static void 2295 pci_conf_print_aer_cap(const pcireg_t *regs, int capoff, int extcapoff) 2296 { 2297 pcireg_t reg; 2298 int pcie_capoff; 2299 int pcie_devtype = -1; 2300 bool tlp_prefix_log = false; 2301 2302 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2303 reg = regs[o2i(pcie_capoff)]; 2304 pcie_devtype = PCIE_XCAP_TYPE(reg); 2305 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2306 if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2307 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2308 /* End-End TLP Prefix Supported */ 2309 if (reg & PCIE_DCAP2_EETLP_PREF) { 2310 tlp_prefix_log = true; 2311 } 2312 } 2313 } 2314 2315 printf("\n Advanced Error Reporting Register\n"); 2316 2317 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2318 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2319 pci_conf_print_aer_cap_uc(reg); 2320 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2321 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2322 pci_conf_print_aer_cap_uc(reg); 2323 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2324 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2325 pci_conf_print_aer_cap_uc(reg); 2326 2327 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2328 printf(" Correctable Error Status register: 0x%08x\n", reg); 2329 pci_conf_print_aer_cap_cor(reg); 2330 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2331 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2332 pci_conf_print_aer_cap_cor(reg); 2333 2334 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2335 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2336 reg); 2337 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2338 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2339 printf(" Header Log register:\n"); 2340 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2341 extcapoff + PCI_AER_ROOTERR_CMD); 2342 2343 switch (pcie_devtype) { 2344 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ 2345 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ 2346 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2347 printf(" Root Error Command register: 0x%08x\n", reg); 2348 pci_conf_print_aer_cap_rooterr_cmd(reg); 2349 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2350 printf(" Root Error Status register: 0x%08x\n", reg); 2351 pci_conf_print_aer_cap_rooterr_status(reg); 2352 2353 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2354 printf(" Error Source Identification: 0x%04x\n", reg); 2355 pci_conf_print_aer_cap_errsrc_id(reg); 2356 break; 2357 } 2358 2359 if (tlp_prefix_log) { 2360 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2361 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2362 } 2363 } 2364 2365 static void 2366 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2367 pcireg_t parbsel, int parbsize) 2368 { 2369 pcireg_t reg; 2370 int num = 16 << parbsel; 2371 int num_per_reg = sizeof(pcireg_t) / parbsize; 2372 int i, j; 2373 2374 /* First, dump the table */ 2375 for (i = 0; i < num; i += num_per_reg) { 2376 reg = regs[o2i(off + i / num_per_reg)]; 2377 printf(" %s Arbitration Table: 0x%08x\n", name, reg); 2378 } 2379 /* And then, decode each entry */ 2380 for (i = 0; i < num; i += num_per_reg) { 2381 reg = regs[o2i(off + i / num_per_reg)]; 2382 for (j = 0; j < num_per_reg; j++) 2383 printf(" Phase[%d]: %d\n", j, reg); 2384 } 2385 } 2386 2387 static void 2388 pci_conf_print_vc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2389 { 2390 pcireg_t reg, n; 2391 int parbtab, parbsize; 2392 pcireg_t parbsel; 2393 int varbtab, varbsize; 2394 pcireg_t varbsel; 2395 int i, count; 2396 2397 printf("\n Virtual Channel Register\n"); 2398 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2399 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2400 count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2401 printf(" Extended VC Count: %d\n", count); 2402 n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2403 printf(" Low Priority Extended VC Count: %u\n", n); 2404 n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2405 printf(" Reference Clock: %s\n", 2406 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 2407 parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2408 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2409 2410 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 2411 printf(" Port VC Capability register 2: 0x%08x\n", reg); 2412 onoff("Hardware fixed arbitration scheme", 2413 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 2414 onoff("WRR arbitration with 32 phases", 2415 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 2416 onoff("WRR arbitration with 64 phases", 2417 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 2418 onoff("WRR arbitration with 128 phases", 2419 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 2420 varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 2421 printf(" VC Arbitration Table Offset: 0x%x\n", varbtab); 2422 2423 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 2424 printf(" Port VC Control register: 0x%04x\n", reg); 2425 varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 2426 printf(" VC Arbitration Select: 0x%x\n", varbsel); 2427 2428 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 2429 printf(" Port VC Status register: 0x%04x\n", reg); 2430 onoff("VC Arbitration Table Status", 2431 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 2432 2433 for (i = 0; i < count + 1; i++) { 2434 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 2435 printf(" VC number %d\n", i); 2436 printf(" VC Resource Capability Register: 0x%08x\n", reg); 2437 onoff(" Non-configurable Hardware fixed arbitration scheme", 2438 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 2439 onoff(" WRR arbitration with 32 phases", 2440 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 2441 onoff(" WRR arbitration with 64 phases", 2442 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 2443 onoff(" WRR arbitration with 128 phases", 2444 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 2445 onoff(" Time-based WRR arbitration with 128 phases", 2446 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 2447 onoff(" WRR arbitration with 256 phases", 2448 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 2449 onoff(" Advanced Packet Switching", 2450 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 2451 onoff(" Reject Snoop Transaction", 2452 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 2453 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 2454 printf(" Maximum Time Slots: %d\n", n); 2455 parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S; 2456 printf(" Port Arbitration Table offset: 0x%02x\n", 2457 parbtab); 2458 2459 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 2460 printf(" VC Resource Control Register: 0x%08x\n", reg); 2461 printf(" TC/VC Map: %02x\n", 2462 (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 2463 /* 2464 * The load Port Arbitration Table bit is used to update 2465 * the Port Arbitration logic and it's always 0 on read, so 2466 * we don't print it. 2467 */ 2468 parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 2469 printf(" Port Arbitration Select: %x\n", parbsel); 2470 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 2471 printf(" VC ID %d\n", n); 2472 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 2473 2474 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 2475 printf(" VC Resource Status Register: 0x%08x\n", reg); 2476 onoff(" Port Arbitration Table Status", 2477 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 2478 onoff(" VC Negotiation Pending", 2479 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 2480 2481 if ((parbtab != 0) && (parbsel != 0)) 2482 pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab, 2483 "Port", parbsel, parbsize); 2484 } 2485 2486 varbsize = 8; 2487 if ((varbtab != 0) && (varbsel != 0)) 2488 pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab, 2489 " VC", varbsel, varbsize); 2490 } 2491 2492 static const char * 2493 pci_conf_print_pwrbdgt_base_power(uint8_t reg) 2494 { 2495 2496 switch (reg) { 2497 case 0xf0: 2498 return "239W < x <= 250W"; 2499 case 0xf1: 2500 return "250W < x <= 275W"; 2501 case 0xf2: 2502 return "275W < x <= 300W"; 2503 default: 2504 break; 2505 } 2506 if (reg >= 0xf3) 2507 return "reserved for above 300W"; 2508 2509 return "Unknown"; 2510 } 2511 2512 static const char * 2513 pci_conf_print_pwrbdgt_data_scale(uint8_t reg) 2514 { 2515 2516 switch (reg) { 2517 case 0x00: 2518 return "1.0x"; 2519 case 0x01: 2520 return "0.1x"; 2521 case 0x02: 2522 return "0.01x"; 2523 case 0x03: 2524 return "0.001x"; 2525 default: 2526 return "wrong value!"; 2527 } 2528 } 2529 2530 static const char * 2531 pci_conf_print_pwrbdgt_type(uint8_t reg) 2532 { 2533 2534 switch (reg) { 2535 case 0x00: 2536 return "PME Aux"; 2537 case 0x01: 2538 return "Auxilary"; 2539 case 0x02: 2540 return "Idle"; 2541 case 0x03: 2542 return "Sustained"; 2543 case 0x04: 2544 return "Sustained (Emergency Power Reduction)"; 2545 case 0x05: 2546 return "Maximum (Emergency Power Reduction)"; 2547 case 0x07: 2548 return "Maximun"; 2549 default: 2550 return "Unknown"; 2551 } 2552 } 2553 2554 static const char * 2555 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 2556 { 2557 2558 switch (reg) { 2559 case 0x00: 2560 return "Power(12V)"; 2561 case 0x01: 2562 return "Power(3.3V)"; 2563 case 0x02: 2564 return "Power(1.5V or 1.8V)"; 2565 case 0x07: 2566 return "Thermal"; 2567 default: 2568 return "Unknown"; 2569 } 2570 } 2571 2572 static void 2573 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff) 2574 { 2575 pcireg_t reg; 2576 2577 printf("\n Power Budget Register\n"); 2578 2579 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 2580 printf(" Data Select register: 0x%08x\n", reg); 2581 2582 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 2583 printf(" Data register: 0x%08x\n", reg); 2584 printf(" Base Power: %s\n", 2585 pci_conf_print_pwrbdgt_base_power((uint8_t)reg)); 2586 printf(" Data Scale: %s\n", 2587 pci_conf_print_pwrbdgt_data_scale( 2588 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE)))); 2589 printf(" PM Sub State: 0x%hhx\n", 2590 (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 2591 printf(" PM State: D%u\n", 2592 (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 2593 printf(" Type: %s\n", 2594 pci_conf_print_pwrbdgt_type( 2595 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 2596 printf(" Power Rail: %s\n", 2597 pci_conf_print_pwrbdgt_pwrrail( 2598 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 2599 2600 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 2601 printf(" Power Budget Capability register: 0x%08x\n", reg); 2602 onoff("System Allocated", 2603 reg, PCI_PWRBDGT_CAP_SYSALLOC); 2604 } 2605 2606 static const char * 2607 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 2608 { 2609 2610 switch (type) { 2611 case 0x00: 2612 return "Configuration Space Element"; 2613 case 0x01: 2614 return "System Egress Port or internal sink (memory)"; 2615 case 0x02: 2616 return "Internal Root Complex Link"; 2617 default: 2618 return "Unknown"; 2619 } 2620 } 2621 2622 static void 2623 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int capoff, int extcapoff) 2624 { 2625 pcireg_t reg; 2626 unsigned char nent, linktype; 2627 int i; 2628 2629 printf("\n Root Complex Link Declaration\n"); 2630 2631 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 2632 printf(" Element Self Description Register: 0x%08x\n", reg); 2633 printf(" Element Type: %s\n", 2634 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 2635 nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 2636 printf(" Number of Link Entries: %hhu\n", nent); 2637 printf(" Component ID: %hhu\n", 2638 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 2639 printf(" Port Number: %hhu\n", 2640 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 2641 for (i = 0; i < nent; i++) { 2642 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 2643 printf(" Link Entry %d:\n", i + 1); 2644 printf(" Link Description Register: 0x%08x\n", reg); 2645 onoff(" Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID); 2646 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 2647 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 2648 "Configuration Space", "Memory-Mapped Space"); 2649 onoff(" Associated RCRB Header", reg, 2650 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 2651 printf(" Target Component ID: %hhu\n", 2652 (unsigned char)__SHIFTOUT(reg, 2653 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 2654 printf(" Target Port Number: %hhu\n", 2655 (unsigned char)__SHIFTOUT(reg, 2656 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 2657 2658 if (linktype == 0) { 2659 /* Memory-Mapped Space */ 2660 reg = regs[o2i(extcapoff 2661 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 2662 printf(" Link Address Low Register: 0x%08x\n", 2663 reg); 2664 reg = regs[o2i(extcapoff 2665 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 2666 printf(" Link Address High Register: 0x%08x\n", 2667 reg); 2668 } else { 2669 unsigned int nb; 2670 pcireg_t lo, hi; 2671 2672 /* Configuration Space */ 2673 lo = regs[o2i(extcapoff 2674 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 2675 printf(" Configuration Space Low Register: " 2676 "0x%08x\n", lo); 2677 hi = regs[o2i(extcapoff 2678 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 2679 printf(" Configuration Space High Register: " 2680 "0x%08x\n", hi); 2681 nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 2682 printf(" N: %u\n", nb); 2683 printf(" Func: %hhu\n", 2684 (unsigned char)__SHIFTOUT(lo, 2685 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 2686 printf(" Dev: %hhu\n", 2687 (unsigned char)__SHIFTOUT(lo, 2688 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 2689 printf(" Bus: %hhu\n", 2690 (unsigned char)__SHIFTOUT(lo, 2691 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 2692 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 2693 printf(" Configuration Space Base Address: " 2694 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 2695 } 2696 } 2697 } 2698 2699 /* XXX pci_conf_print_rclink_ctl_cap */ 2700 2701 static void 2702 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2703 { 2704 pcireg_t reg; 2705 2706 printf("\n Root Complex Event Collector Association\n"); 2707 2708 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 2709 printf(" Association Bitmap for Root Complex Integrated Devices:" 2710 " 0x%08x\n", reg); 2711 } 2712 2713 /* XXX pci_conf_print_mfvc_cap */ 2714 /* XXX pci_conf_print_vc2_cap */ 2715 /* XXX pci_conf_print_rcrb_cap */ 2716 /* XXX pci_conf_print_vendor_cap */ 2717 /* XXX pci_conf_print_cac_cap */ 2718 2719 static void 2720 pci_conf_print_acs_cap(const pcireg_t *regs, int capoff, int extcapoff) 2721 { 2722 pcireg_t reg, cap, ctl; 2723 unsigned int size, i; 2724 2725 printf("\n Access Control Services\n"); 2726 2727 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 2728 cap = reg & 0xffff; 2729 ctl = reg >> 16; 2730 printf(" ACS Capability register: 0x%08x\n", cap); 2731 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 2732 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 2733 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 2734 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 2735 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 2736 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 2737 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 2738 size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 2739 if (size == 0) 2740 size = 256; 2741 printf(" Egress Control Vector Size: %u\n", size); 2742 printf(" ACS Control register: 0x%08x\n", ctl); 2743 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 2744 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 2745 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 2746 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 2747 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 2748 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 2749 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 2750 2751 /* 2752 * If the P2P Egress Control Capability bit is 0, ignore the Egress 2753 * Control vector. 2754 */ 2755 if ((cap & PCI_ACS_CAP_E) == 0) 2756 return; 2757 for (i = 0; i < size; i += 32) 2758 printf(" Egress Control Vector [%u..%u]: %x\n", i + 31, 2759 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 2760 } 2761 2762 static void 2763 pci_conf_print_ari_cap(const pcireg_t *regs, int capoff, int extcapoff) 2764 { 2765 pcireg_t reg, cap, ctl; 2766 2767 printf("\n Alternative Routing-ID Interpretation Register\n"); 2768 2769 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2770 cap = reg & 0xffff; 2771 ctl = reg >> 16; 2772 printf(" Capability register: 0x%08x\n", cap); 2773 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 2774 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 2775 printf(" Next Function Number: %u\n", 2776 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 2777 printf(" Control register: 0x%08x\n", ctl); 2778 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 2779 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 2780 printf(" Function Group: %u\n", 2781 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 2782 } 2783 2784 static void 2785 pci_conf_print_ats_cap(const pcireg_t *regs, int capoff, int extcapoff) 2786 { 2787 pcireg_t reg, cap, ctl; 2788 unsigned int num; 2789 2790 printf("\n Address Translation Services\n"); 2791 2792 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2793 cap = reg & 0xffff; 2794 ctl = reg >> 16; 2795 printf(" Capability register: 0x%04x\n", cap); 2796 num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 2797 if (num == 0) 2798 num = 32; 2799 printf(" Invalidate Queue Depth: %u\n", num); 2800 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 2801 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 2802 2803 printf(" Control register: 0x%04x\n", ctl); 2804 printf(" Smallest Translation Unit: %u\n", 2805 (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU)); 2806 onoff("Enable", reg, PCI_ATS_CTL_EN); 2807 } 2808 2809 static void 2810 pci_conf_print_sernum_cap(const pcireg_t *regs, int capoff, int extcapoff) 2811 { 2812 pcireg_t lo, hi; 2813 2814 printf("\n Device Serial Number Register\n"); 2815 2816 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 2817 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 2818 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 2819 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 2820 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 2821 } 2822 2823 static void 2824 pci_conf_print_sriov_cap(const pcireg_t *regs, int capoff, int extcapoff) 2825 { 2826 char buf[sizeof("99999 MB")]; 2827 pcireg_t reg; 2828 pcireg_t total_vfs; 2829 int i; 2830 bool first; 2831 2832 printf("\n Single Root IO Virtualization Register\n"); 2833 2834 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 2835 printf(" Capabilities register: 0x%08x\n", reg); 2836 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 2837 onoff("ARI Capable Hierarchy Preserved", reg, 2838 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 2839 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 2840 printf(" VF Migration Interrupt Message Number: 0x%u\n", 2841 (pcireg_t)__SHIFTOUT(reg, 2842 PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 2843 } 2844 2845 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 2846 printf(" Control register: 0x%04x\n", reg); 2847 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 2848 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 2849 onoff("VF Migration Interrupt Enable", reg, 2850 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 2851 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 2852 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 2853 2854 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 2855 printf(" Status register: 0x%04x\n", reg); 2856 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 2857 2858 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 2859 printf(" InitialVFs register: 0x%04x\n", reg); 2860 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 2861 printf(" TotalVFs register: 0x%04x\n", reg); 2862 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 2863 printf(" NumVFs register: 0x%04x\n", reg); 2864 2865 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 2866 printf(" Function Dependency Link register: 0x%04x\n", reg); 2867 2868 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 2869 printf(" First VF Offset register: 0x%04x\n", reg); 2870 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 2871 printf(" VF Stride register: 0x%04x\n", reg); 2872 2873 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 2874 printf(" Supported Page Sizes register: 0x%08x\n", reg); 2875 printf(" Supported Page Size:"); 2876 for (i = 0, first = true; i < 32; i++) { 2877 if (reg & __BIT(i)) { 2878 #ifdef _KERNEL 2879 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 2880 #else 2881 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 2882 HN_AUTOSCALE, 0); 2883 #endif 2884 printf("%s %s", first ? "" : ",", buf); 2885 first = false; 2886 } 2887 } 2888 printf("\n"); 2889 2890 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 2891 printf(" System Page Sizes register: 0x%08x\n", reg); 2892 printf(" Page Size: "); 2893 if (reg != 0) { 2894 #ifdef _KERNEL 2895 format_bytes(buf, sizeof(buf), 1LL << (ffs(reg) + 12)); 2896 #else 2897 humanize_number(buf, sizeof(buf), 1LL << (ffs(reg) + 12), "B", 2898 HN_AUTOSCALE, 0); 2899 #endif 2900 printf("%s", buf); 2901 } else { 2902 printf("unknown"); 2903 } 2904 printf("\n"); 2905 2906 for (i = 0; i < 6; i++) { 2907 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 2908 printf(" VF BAR%d register: 0x%08x\n", i, reg); 2909 } 2910 2911 if (total_vfs > 0) { 2912 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 2913 printf(" VF Migration State Array Offset register: 0x%08x\n", 2914 reg); 2915 printf(" VF Migration State Offset: 0x%08x\n", 2916 (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 2917 i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 2918 printf(" VF Migration State BIR: "); 2919 if (i >= 0 && i <= 5) { 2920 printf("BAR%d", i); 2921 } else { 2922 printf("unknown BAR (%d)", i); 2923 } 2924 printf("\n"); 2925 } 2926 } 2927 2928 /* XXX pci_conf_print_mriov_cap */ 2929 2930 static void 2931 pci_conf_print_multicast_cap(const pcireg_t *regs, int capoff, int extcapoff) 2932 { 2933 pcireg_t reg, cap, ctl; 2934 pcireg_t regl, regh; 2935 uint64_t addr; 2936 int n; 2937 2938 printf("\n Multicast\n"); 2939 2940 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 2941 cap = reg & 0xffff; 2942 ctl = reg >> 16; 2943 printf(" Capability Register: 0x%04x\n", cap); 2944 printf(" Max Group: %u\n", 2945 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 2946 2947 /* Endpoint Only */ 2948 n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 2949 if (n > 0) 2950 printf(" Windw Size Requested: %d\n", 1 << (n - 1)); 2951 2952 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 2953 2954 printf(" Control Register: 0x%04x\n", ctl); 2955 printf(" Num Group: %u\n", 2956 (unsigned int)__SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 2957 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 2958 2959 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 2960 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 2961 printf(" Base Address Register 0: 0x%08x\n", regl); 2962 printf(" Base Address Register 1: 0x%08x\n", regh); 2963 printf(" Index Position: %u\n", 2964 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 2965 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 2966 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 2967 2968 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 2969 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 2970 printf(" Receive Register 0: 0x%08x\n", regl); 2971 printf(" Receive Register 1: 0x%08x\n", regh); 2972 2973 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 2974 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 2975 printf(" Block All Register 0: 0x%08x\n", regl); 2976 printf(" Block All Register 1: 0x%08x\n", regh); 2977 2978 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 2979 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 2980 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 2981 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 2982 2983 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 2984 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 2985 printf(" Overlay BAR 0: 0x%08x\n", regl); 2986 printf(" Overlay BAR 1: 0x%08x\n", regh); 2987 2988 n = regl & PCI_MCAST_OVERLAYL_SIZE; 2989 printf(" Overlay Size: "); 2990 if (n >= 6) 2991 printf("%d\n", n); 2992 else 2993 printf("off\n"); 2994 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 2995 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 2996 } 2997 2998 static void 2999 pci_conf_print_page_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3000 { 3001 pcireg_t reg, ctl, sta; 3002 3003 printf("\n Page Request\n"); 3004 3005 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 3006 ctl = reg & 0xffff; 3007 sta = reg >> 16; 3008 printf(" Control Register: 0x%04x\n", ctl); 3009 onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E); 3010 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 3011 3012 printf(" Status Register: 0x%04x\n", sta); 3013 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 3014 onoff("Unexpected Page Request Group Index", reg, 3015 PCI_PAGE_REQ_STA_UPRGI); 3016 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 3017 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 3018 3019 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 3020 printf(" Outstanding Page Request Capacity: %u\n", reg); 3021 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 3022 printf(" Outstanding Page Request Allocation: %u\n", reg); 3023 } 3024 3025 /* XXX pci_conf_print_amd_cap */ 3026 3027 #define MEM_PBUFSIZE sizeof("999GB") 3028 3029 static void 3030 pci_conf_print_resizbar_cap(const pcireg_t *regs, int capoff, int extcapoff) 3031 { 3032 pcireg_t cap, ctl; 3033 unsigned int bars, i, n; 3034 char pbuf[MEM_PBUFSIZE]; 3035 3036 printf("\n Resizable BAR\n"); 3037 3038 /* Get Number of Resizable BARs */ 3039 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))]; 3040 bars = __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR); 3041 printf(" Number of Resizable BARs: "); 3042 if (bars <= 6) 3043 printf("%u\n", bars); 3044 else { 3045 printf("incorrect (%u)\n", bars); 3046 return; 3047 } 3048 3049 for (n = 0; n < 6; n++) { 3050 cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))]; 3051 printf(" Capability register(%u): 0x%08x\n", n, cap); 3052 if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0) 3053 continue; /* Not Used */ 3054 printf(" Acceptable BAR sizes:"); 3055 for (i = 4; i <= 23; i++) { 3056 if ((cap & (1 << i)) != 0) { 3057 humanize_number(pbuf, MEM_PBUFSIZE, 3058 (int64_t)1024 * 1024 << (i - 4), "B", 3059 #ifdef _KERNEL 3060 1); 3061 #else 3062 HN_AUTOSCALE, HN_NOSPACE); 3063 #endif 3064 printf(" %s", pbuf); 3065 } 3066 } 3067 printf("\n"); 3068 3069 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))]; 3070 printf(" Control register(%u): 0x%08x\n", n, ctl); 3071 printf(" BAR Index: %u\n", 3072 (unsigned int)__SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX)); 3073 humanize_number(pbuf, MEM_PBUFSIZE, 3074 (int64_t)1024 * 1024 3075 << __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ), 3076 "B", 3077 #ifdef _KERNEL 3078 1); 3079 #else 3080 HN_AUTOSCALE, HN_NOSPACE); 3081 #endif 3082 printf(" BAR Size: %s\n", pbuf); 3083 } 3084 } 3085 3086 static void 3087 pci_conf_print_dpa_cap(const pcireg_t *regs, int capoff, int extcapoff) 3088 { 3089 pcireg_t reg; 3090 unsigned int substmax, i; 3091 3092 printf("\n Dynamic Power Allocation\n"); 3093 3094 reg = regs[o2i(extcapoff + PCI_DPA_CAP)]; 3095 printf(" Capability register: 0x%08x\n", reg); 3096 substmax = __SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX); 3097 printf(" Substate Max: %u\n", substmax); 3098 printf(" Transition Latency Unit: "); 3099 switch (__SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) { 3100 case 0: 3101 printf("1ms\n"); 3102 break; 3103 case 1: 3104 printf("10ms\n"); 3105 break; 3106 case 2: 3107 printf("100ms\n"); 3108 break; 3109 default: 3110 printf("reserved\n"); 3111 break; 3112 } 3113 printf(" Power Allocation Scale: "); 3114 switch (__SHIFTOUT(reg, PCI_DPA_CAP_PAS)) { 3115 case 0: 3116 printf("10.0x\n"); 3117 break; 3118 case 1: 3119 printf("1.0x\n"); 3120 break; 3121 case 2: 3122 printf("0.1x\n"); 3123 break; 3124 case 3: 3125 printf("0.01x\n"); 3126 break; 3127 } 3128 printf(" Transition Latency Value 0: %u\n", 3129 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY0)); 3130 printf(" Transition Latency Value 1: %u\n", 3131 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY1)); 3132 3133 reg = regs[o2i(extcapoff + PCI_DPA_LATIND)]; 3134 printf(" Latency Indicatior register: 0x%08x\n", reg); 3135 3136 reg = regs[o2i(extcapoff + PCI_DPA_CS)]; 3137 printf(" Status register: 0x%04x\n", reg & 0xffff); 3138 printf(" Substate Status: %02x\n", 3139 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT)); 3140 onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN); 3141 printf(" Control register: 0x%04x\n", reg >> 16); 3142 printf(" Substate Control: %02x\n", 3143 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL)); 3144 3145 for (i = 0; i <= substmax; i++) 3146 printf(" Substate Power Allocation register %d: 0x%02x\n", 3147 i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff)); 3148 } 3149 3150 static const char * 3151 pci_conf_print_tph_req_cap_sttabloc(unsigned char val) 3152 { 3153 3154 switch (val) { 3155 case 0x0: 3156 return "Not Present"; 3157 case 0x1: 3158 return "in the TPH Requester Capability Structure"; 3159 case 0x2: 3160 return "in the MSI-X Table"; 3161 default: 3162 return "Unknown"; 3163 } 3164 } 3165 3166 static void 3167 pci_conf_print_tph_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3168 { 3169 pcireg_t reg; 3170 int size, i, j; 3171 3172 printf("\n TPH Requester Extended Capability\n"); 3173 3174 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 3175 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 3176 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 3177 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 3178 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 3179 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 3180 printf(" ST Table Location: %s\n", 3181 pci_conf_print_tph_req_cap_sttabloc( 3182 (unsigned char)__SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC))); 3183 size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 3184 printf(" ST Table Size: %d\n", size); 3185 for (i = 0; i < size ; i += 2) { 3186 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 3187 for (j = 0; j < 2 ; j++) { 3188 uint32_t entry = reg; 3189 3190 if (j != 0) 3191 entry >>= 16; 3192 entry &= 0xffff; 3193 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 3194 i + j, entry); 3195 } 3196 } 3197 } 3198 3199 static void 3200 pci_conf_print_ltr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3201 { 3202 pcireg_t reg; 3203 3204 printf("\n Latency Tolerance Reporting\n"); 3205 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)] & 0xffff; 3206 printf(" Max Snoop Latency Register: 0x%04x\n", reg); 3207 printf(" Max Snoop LatencyValue: %u\n", 3208 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL)); 3209 printf(" Max Snoop LatencyScale: %uns\n", 3210 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE))); 3211 reg = regs[o2i(extcapoff + PCI_LTR_MAXNOSNOOPLAT)] >> 16; 3212 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg); 3213 printf(" Max No-Snoop LatencyValue: %u\n", 3214 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL)); 3215 printf(" Max No-Snoop LatencyScale: %uns\n", 3216 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE))); 3217 } 3218 3219 static void 3220 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int capoff, int extcapoff) 3221 { 3222 int pcie_capoff; 3223 pcireg_t reg; 3224 int i, maxlinkwidth; 3225 3226 printf("\n Secondary PCI Express Register\n"); 3227 3228 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3229 printf(" Link Control 3 register: 0x%08x\n", reg); 3230 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3231 onoff("Link Equalization Request Interrupt Enable", 3232 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3233 printf(" Enable Lower SKP OS Generation Vector:"); 3234 pci_print_pcie_linkspeedvector( 3235 __SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV)); 3236 printf("\n"); 3237 3238 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3239 printf(" Lane Error Status register: 0x%08x\n", reg); 3240 3241 /* Get Max Link Width */ 3242 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)){ 3243 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3244 maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3245 } else { 3246 printf("error: falied to get PCIe capablity\n"); 3247 return; 3248 } 3249 for (i = 0; i < maxlinkwidth; i++) { 3250 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3251 if (i % 2 != 0) 3252 reg >>= 16; 3253 else 3254 reg &= 0xffff; 3255 printf(" Equalization Control Register (Link %d): %04x\n", 3256 i, reg); 3257 printf(" Downstream Port Transmit Preset: 0x%x\n", 3258 (pcireg_t)__SHIFTOUT(reg, 3259 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3260 printf(" Downstream Port Receive Hint: 0x%x\n", 3261 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3262 printf(" Upstream Port Transmit Preset: 0x%x\n", 3263 (pcireg_t)__SHIFTOUT(reg, 3264 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3265 printf(" Upstream Port Receive Hint: 0x%x\n", 3266 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3267 } 3268 } 3269 3270 /* XXX pci_conf_print_pmux_cap */ 3271 3272 static void 3273 pci_conf_print_pasid_cap(const pcireg_t *regs, int capoff, int extcapoff) 3274 { 3275 pcireg_t reg, cap, ctl; 3276 unsigned int num; 3277 3278 printf("\n Process Address Space ID\n"); 3279 3280 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3281 cap = reg & 0xffff; 3282 ctl = reg >> 16; 3283 printf(" PASID Capability Register: 0x%04x\n", cap); 3284 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3285 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3286 num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3287 printf(" Max PASID Width: %u\n", num); 3288 3289 printf(" PASID Control Register: 0x%04x\n", ctl); 3290 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3291 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3292 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 3293 } 3294 3295 static void 3296 pci_conf_print_lnr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3297 { 3298 pcireg_t reg, cap, ctl; 3299 unsigned int num; 3300 3301 printf("\n LN Requester\n"); 3302 3303 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 3304 cap = reg & 0xffff; 3305 ctl = reg >> 16; 3306 printf(" LNR Capability register: 0x%04x\n", cap); 3307 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 3308 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 3309 num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 3310 printf(" LNR Registration MAX: %u\n", num); 3311 3312 printf(" LNR Control register: 0x%04x\n", ctl); 3313 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 3314 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 3315 num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 3316 printf(" LNR Registration Limit: %u\n", num); 3317 } 3318 3319 /* XXX pci_conf_print_dpc_cap */ 3320 3321 static int 3322 pci_conf_l1pm_cap_tposcale(unsigned char scale) 3323 { 3324 3325 /* Return scale in us */ 3326 switch (scale) { 3327 case 0x0: 3328 return 2; 3329 case 0x1: 3330 return 10; 3331 case 0x2: 3332 return 100; 3333 default: 3334 return -1; 3335 } 3336 } 3337 3338 static void 3339 pci_conf_print_l1pm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3340 { 3341 pcireg_t reg; 3342 int scale, val; 3343 3344 printf("\n L1 PM Substates\n"); 3345 3346 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 3347 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 3348 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 3349 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 3350 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 3351 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 3352 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 3353 printf(" Port Common Mode Restore Time: %uus\n", 3354 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 3355 scale = pci_conf_l1pm_cap_tposcale( 3356 __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 3357 val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 3358 printf(" Port T_POWER_ON: "); 3359 if (scale == -1) 3360 printf("unknown\n"); 3361 else 3362 printf("%dus\n", val * scale); 3363 3364 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 3365 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 3366 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 3367 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 3368 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 3369 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 3370 printf(" Common Mode Restore Time: %uus\n", 3371 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 3372 scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 3373 val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 3374 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 3375 3376 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 3377 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 3378 scale = pci_conf_l1pm_cap_tposcale( 3379 __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 3380 val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 3381 printf(" T_POWER_ON: "); 3382 if (scale == -1) 3383 printf("unknown\n"); 3384 else 3385 printf("%dus\n", val * scale); 3386 } 3387 3388 static void 3389 pci_conf_print_ptm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3390 { 3391 pcireg_t reg; 3392 uint32_t val; 3393 3394 printf("\n Precision Time Management\n"); 3395 3396 reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; 3397 printf(" PTM Capability register: 0x%08x\n", reg); 3398 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ); 3399 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP); 3400 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT); 3401 printf(" Local Clock Granularity: "); 3402 val = __SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL); 3403 switch (val) { 3404 case 0: 3405 printf("Not implemented\n"); 3406 break; 3407 case 0xffff: 3408 printf("> 254ns\n"); 3409 break; 3410 default: 3411 printf("%uns\n", val); 3412 break; 3413 } 3414 3415 reg = regs[o2i(extcapoff + PCI_PTM_CTL)]; 3416 printf(" PTM Control register: 0x%08x\n", reg); 3417 onoff("PTM Enable", reg, PCI_PTM_CTL_EN); 3418 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL); 3419 printf(" Effective Granularity: "); 3420 val = __SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL); 3421 switch (val) { 3422 case 0: 3423 printf("Unknown\n"); 3424 break; 3425 case 0xffff: 3426 printf("> 254ns\n"); 3427 break; 3428 default: 3429 printf("%uns\n", val); 3430 break; 3431 } 3432 } 3433 3434 /* XXX pci_conf_print_mpcie_cap */ 3435 /* XXX pci_conf_print_frsq_cap */ 3436 /* XXX pci_conf_print_rtr_cap */ 3437 /* XXX pci_conf_print_desigvndsp_cap */ 3438 /* XXX pci_conf_print_vf_resizbar_cap */ 3439 3440 #undef MS 3441 #undef SM 3442 #undef RW 3443 3444 static struct { 3445 pcireg_t cap; 3446 const char *name; 3447 void (*printfunc)(const pcireg_t *, int, int); 3448 } pci_extcaptab[] = { 3449 { 0, "reserved", 3450 NULL }, 3451 { PCI_EXTCAP_AER, "Advanced Error Reporting", 3452 pci_conf_print_aer_cap }, 3453 { PCI_EXTCAP_VC, "Virtual Channel", 3454 pci_conf_print_vc_cap }, 3455 { PCI_EXTCAP_SERNUM, "Device Serial Number", 3456 pci_conf_print_sernum_cap }, 3457 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 3458 pci_conf_print_pwrbdgt_cap }, 3459 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 3460 pci_conf_print_rclink_dcl_cap }, 3461 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 3462 NULL }, 3463 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 3464 pci_conf_print_rcec_assoc_cap }, 3465 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 3466 NULL }, 3467 { PCI_EXTCAP_VC2, "Virtual Channel", 3468 NULL }, 3469 { PCI_EXTCAP_RCRB, "RCRB Header", 3470 NULL }, 3471 { PCI_EXTCAP_VENDOR, "Vendor Unique", 3472 NULL }, 3473 { PCI_EXTCAP_CAC, "Configuration Access Correction", 3474 NULL }, 3475 { PCI_EXTCAP_ACS, "Access Control Services", 3476 pci_conf_print_acs_cap }, 3477 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 3478 pci_conf_print_ari_cap }, 3479 { PCI_EXTCAP_ATS, "Address Translation Services", 3480 pci_conf_print_ats_cap }, 3481 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 3482 pci_conf_print_sriov_cap }, 3483 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 3484 NULL }, 3485 { PCI_EXTCAP_MCAST, "Multicast", 3486 pci_conf_print_multicast_cap }, 3487 { PCI_EXTCAP_PAGE_REQ, "Page Request", 3488 pci_conf_print_page_req_cap }, 3489 { PCI_EXTCAP_AMD, "Reserved for AMD", 3490 NULL }, 3491 { PCI_EXTCAP_RESIZBAR, "Resizable BAR", 3492 pci_conf_print_resizbar_cap }, 3493 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 3494 pci_conf_print_dpa_cap }, 3495 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 3496 pci_conf_print_tph_req_cap }, 3497 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 3498 pci_conf_print_ltr_cap }, 3499 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 3500 pci_conf_print_sec_pcie_cap }, 3501 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 3502 NULL }, 3503 { PCI_EXTCAP_PASID, "Process Address Space ID", 3504 pci_conf_print_pasid_cap }, 3505 { PCI_EXTCAP_LN_REQ, "LN Requester", 3506 pci_conf_print_lnr_cap }, 3507 { PCI_EXTCAP_DPC, "Downstream Port Containment", 3508 NULL }, 3509 { PCI_EXTCAP_L1PM, "L1 PM Substates", 3510 pci_conf_print_l1pm_cap }, 3511 { PCI_EXTCAP_PTM, "Precision Time Management", 3512 pci_conf_print_ptm_cap }, 3513 { PCI_EXTCAP_MPCIE, "M-PCIe", 3514 NULL }, 3515 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 3516 NULL }, 3517 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 3518 NULL }, 3519 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 3520 NULL }, 3521 { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs", 3522 NULL }, 3523 }; 3524 3525 static int 3526 pci_conf_find_extcap(const pcireg_t *regs, int capoff, unsigned int capid, 3527 int *offsetp) 3528 { 3529 int off; 3530 pcireg_t rval; 3531 3532 for (off = PCI_EXTCAPLIST_BASE; 3533 off != 0; 3534 off = PCI_EXTCAPLIST_NEXT(rval)) { 3535 rval = regs[o2i(off)]; 3536 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 3537 if (offsetp != NULL) 3538 *offsetp = off; 3539 return 1; 3540 } 3541 } 3542 return 0; 3543 } 3544 3545 static void 3546 pci_conf_print_extcaplist( 3547 #ifdef _KERNEL 3548 pci_chipset_tag_t pc, pcitag_t tag, 3549 #endif 3550 const pcireg_t *regs, int capoff) 3551 { 3552 int off; 3553 pcireg_t foundcap; 3554 pcireg_t rval; 3555 bool foundtable[__arraycount(pci_extcaptab)]; 3556 unsigned int i; 3557 3558 /* Check Extended capability structure */ 3559 off = PCI_EXTCAPLIST_BASE; 3560 rval = regs[o2i(off)]; 3561 if (rval == 0xffffffff || rval == 0) 3562 return; 3563 3564 /* Clear table */ 3565 for (i = 0; i < __arraycount(pci_extcaptab); i++) 3566 foundtable[i] = false; 3567 3568 /* Print extended capability register's offset and the type first */ 3569 for (;;) { 3570 printf(" Extended Capability Register at 0x%02x\n", off); 3571 3572 foundcap = PCI_EXTCAPLIST_CAP(rval); 3573 printf(" type: 0x%04x (", foundcap); 3574 if (foundcap < __arraycount(pci_extcaptab)) { 3575 printf("%s)\n", pci_extcaptab[foundcap].name); 3576 /* Mark as found */ 3577 foundtable[foundcap] = true; 3578 } else 3579 printf("unknown)\n"); 3580 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 3581 3582 off = PCI_EXTCAPLIST_NEXT(rval); 3583 if (off == 0) 3584 break; 3585 else if (off <= PCI_CONF_SIZE) { 3586 printf(" next pointer: 0x%03x (incorrect)\n", off); 3587 return; 3588 } 3589 rval = regs[o2i(off)]; 3590 } 3591 3592 /* 3593 * And then, print the detail of each capability registers 3594 * in capability value's order. 3595 */ 3596 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 3597 if (foundtable[i] == false) 3598 continue; 3599 3600 /* 3601 * The type was found. Search capability list again and 3602 * print all capabilities that the capabiliy type is 3603 * the same. 3604 */ 3605 if (pci_conf_find_extcap(regs, capoff, i, &off) == 0) 3606 continue; 3607 rval = regs[o2i(off)]; 3608 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 3609 || (pci_extcaptab[i].printfunc == NULL)) 3610 continue; 3611 3612 pci_extcaptab[i].printfunc(regs, capoff, off); 3613 3614 } 3615 } 3616 3617 /* Print the Secondary Status Register. */ 3618 static void 3619 pci_conf_print_ssr(pcireg_t rval) 3620 { 3621 pcireg_t devsel; 3622 3623 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 3624 onoff("66 MHz capable", rval, __BIT(5)); 3625 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 3626 onoff("Fast back-to-back capable", rval, __BIT(7)); 3627 onoff("Data parity error detected", rval, __BIT(8)); 3628 3629 printf(" DEVSEL timing: "); 3630 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 3631 switch (devsel) { 3632 case 0: 3633 printf("fast"); 3634 break; 3635 case 1: 3636 printf("medium"); 3637 break; 3638 case 2: 3639 printf("slow"); 3640 break; 3641 default: 3642 printf("unknown/reserved"); /* XXX */ 3643 break; 3644 } 3645 printf(" (0x%x)\n", devsel); 3646 3647 onoff("Signalled target abort", rval, __BIT(11)); 3648 onoff("Received target abort", rval, __BIT(12)); 3649 onoff("Received master abort", rval, __BIT(13)); 3650 onoff("Received system error", rval, __BIT(14)); 3651 onoff("Detected parity error", rval, __BIT(15)); 3652 } 3653 3654 static void 3655 pci_conf_print_type0( 3656 #ifdef _KERNEL 3657 pci_chipset_tag_t pc, pcitag_t tag, 3658 #endif 3659 const pcireg_t *regs 3660 #ifdef _KERNEL 3661 , int sizebars 3662 #endif 3663 ) 3664 { 3665 int off, width; 3666 pcireg_t rval; 3667 3668 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 3669 #ifdef _KERNEL 3670 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3671 #else 3672 width = pci_conf_print_bar(regs, off, NULL); 3673 #endif 3674 } 3675 3676 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 3677 3678 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 3679 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 3680 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 3681 3682 /* XXX */ 3683 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 3684 3685 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3686 printf(" Capability list pointer: 0x%02x\n", 3687 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 3688 else 3689 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 3690 3691 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 3692 3693 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3694 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 3695 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 3696 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 3697 switch (PCI_INTERRUPT_PIN(rval)) { 3698 case PCI_INTERRUPT_PIN_NONE: 3699 printf("(none)"); 3700 break; 3701 case PCI_INTERRUPT_PIN_A: 3702 printf("(pin A)"); 3703 break; 3704 case PCI_INTERRUPT_PIN_B: 3705 printf("(pin B)"); 3706 break; 3707 case PCI_INTERRUPT_PIN_C: 3708 printf("(pin C)"); 3709 break; 3710 case PCI_INTERRUPT_PIN_D: 3711 printf("(pin D)"); 3712 break; 3713 default: 3714 printf("(? ? ?)"); 3715 break; 3716 } 3717 printf("\n"); 3718 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 3719 } 3720 3721 static void 3722 pci_conf_print_type1( 3723 #ifdef _KERNEL 3724 pci_chipset_tag_t pc, pcitag_t tag, 3725 #endif 3726 const pcireg_t *regs 3727 #ifdef _KERNEL 3728 , int sizebars 3729 #endif 3730 ) 3731 { 3732 int off, width; 3733 pcireg_t rval; 3734 uint32_t base, limit; 3735 uint32_t base_h, limit_h; 3736 uint64_t pbase, plimit; 3737 int use_upper; 3738 3739 /* 3740 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 3741 * Bridge chip documentation, and may not be correct with 3742 * respect to various standards. (XXX) 3743 */ 3744 3745 for (off = 0x10; off < 0x18; off += width) { 3746 #ifdef _KERNEL 3747 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3748 #else 3749 width = pci_conf_print_bar(regs, off, NULL); 3750 #endif 3751 } 3752 3753 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 3754 printf(" Primary bus number: 0x%02x\n", 3755 PCI_BRIDGE_BUS_PRIMARY(rval)); 3756 printf(" Secondary bus number: 0x%02x\n", 3757 PCI_BRIDGE_BUS_SECONDARY(rval)); 3758 printf(" Subordinate bus number: 0x%02x\n", 3759 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 3760 printf(" Secondary bus latency timer: 0x%02x\n", 3761 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 3762 3763 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 3764 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 3765 3766 /* I/O region */ 3767 printf(" I/O region:\n"); 3768 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 3769 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 3770 if (PCI_BRIDGE_IO_32BITS(rval)) 3771 use_upper = 1; 3772 else 3773 use_upper = 0; 3774 onoff("32bit I/O", rval, use_upper); 3775 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 3776 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 3777 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 3778 limit |= 0x00000fff; 3779 3780 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 3781 base_h = (rval >> 0) & 0xffff; 3782 limit_h = (rval >> 16) & 0xffff; 3783 printf(" base upper 16 bits register: 0x%04x\n", base_h); 3784 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 3785 3786 if (use_upper == 1) { 3787 base |= base_h << 16; 3788 limit |= limit_h << 16; 3789 } 3790 if (base < limit) { 3791 if (use_upper == 1) 3792 printf(" range: 0x%08x-0x%08x\n", base, limit); 3793 else 3794 printf(" range: 0x%04x-0x%04x\n", base, limit); 3795 } else 3796 printf(" range: not set\n"); 3797 3798 /* Non-prefetchable memory region */ 3799 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 3800 printf(" Memory region:\n"); 3801 printf(" base register: 0x%04x\n", 3802 (rval >> 0) & 0xffff); 3803 printf(" limit register: 0x%04x\n", 3804 (rval >> 16) & 0xffff); 3805 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 3806 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 3807 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 3808 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 3809 if (base < limit) 3810 printf(" range: 0x%08x-0x%08x\n", base, limit); 3811 else 3812 printf(" range: not set\n"); 3813 3814 /* Prefetchable memory region */ 3815 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 3816 printf(" Prefetchable memory region:\n"); 3817 printf(" base register: 0x%04x\n", 3818 (rval >> 0) & 0xffff); 3819 printf(" limit register: 0x%04x\n", 3820 (rval >> 16) & 0xffff); 3821 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 3822 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 3823 printf(" base upper 32 bits register: 0x%08x\n", 3824 base_h); 3825 printf(" limit upper 32 bits register: 0x%08x\n", 3826 limit_h); 3827 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 3828 use_upper = 1; 3829 else 3830 use_upper = 0; 3831 onoff("64bit memory address", rval, use_upper); 3832 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 3833 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 3834 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 3835 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 3836 if (use_upper == 1) { 3837 pbase |= (uint64_t)base_h << 32; 3838 plimit |= (uint64_t)limit_h << 32; 3839 } 3840 if (pbase < plimit) { 3841 if (use_upper == 1) 3842 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 3843 "\n", pbase, plimit); 3844 else 3845 printf(" range: 0x%08x-0x%08x\n", 3846 (uint32_t)pbase, (uint32_t)plimit); 3847 } else 3848 printf(" range: not set\n"); 3849 3850 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3851 printf(" Capability list pointer: 0x%02x\n", 3852 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 3853 else 3854 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 3855 3856 /* XXX */ 3857 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 3858 3859 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3860 printf(" Interrupt line: 0x%02x\n", 3861 (rval >> 0) & 0xff); 3862 printf(" Interrupt pin: 0x%02x ", 3863 (rval >> 8) & 0xff); 3864 switch ((rval >> 8) & 0xff) { 3865 case PCI_INTERRUPT_PIN_NONE: 3866 printf("(none)"); 3867 break; 3868 case PCI_INTERRUPT_PIN_A: 3869 printf("(pin A)"); 3870 break; 3871 case PCI_INTERRUPT_PIN_B: 3872 printf("(pin B)"); 3873 break; 3874 case PCI_INTERRUPT_PIN_C: 3875 printf("(pin C)"); 3876 break; 3877 case PCI_INTERRUPT_PIN_D: 3878 printf("(pin D)"); 3879 break; 3880 default: 3881 printf("(? ? ?)"); 3882 break; 3883 } 3884 printf("\n"); 3885 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 3886 & PCI_BRIDGE_CONTROL_MASK; 3887 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 3888 onoff("Parity error response", rval, 0x0001); 3889 onoff("Secondary SERR forwarding", rval, 0x0002); 3890 onoff("ISA enable", rval, 0x0004); 3891 onoff("VGA enable", rval, 0x0008); 3892 onoff("Master abort reporting", rval, 0x0020); 3893 onoff("Secondary bus reset", rval, 0x0040); 3894 onoff("Fast back-to-back capable", rval, 0x0080); 3895 } 3896 3897 static void 3898 pci_conf_print_type2( 3899 #ifdef _KERNEL 3900 pci_chipset_tag_t pc, pcitag_t tag, 3901 #endif 3902 const pcireg_t *regs 3903 #ifdef _KERNEL 3904 , int sizebars 3905 #endif 3906 ) 3907 { 3908 pcireg_t rval; 3909 3910 /* 3911 * XXX these need to be printed in more detail, need to be 3912 * XXX checked against specs/docs, etc. 3913 * 3914 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 3915 * controller chip documentation, and may not be correct with 3916 * respect to various standards. (XXX) 3917 */ 3918 3919 #ifdef _KERNEL 3920 pci_conf_print_bar(pc, tag, regs, 0x10, 3921 "CardBus socket/ExCA registers", sizebars); 3922 #else 3923 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 3924 #endif 3925 3926 /* Capability list pointer and secondary status register */ 3927 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 3928 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3929 printf(" Capability list pointer: 0x%02x\n", 3930 PCI_CAPLIST_PTR(rval)); 3931 else 3932 printf(" Reserved @ 0x14: 0x%04x\n", 3933 (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0))); 3934 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 3935 3936 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 3937 printf(" PCI bus number: 0x%02x\n", 3938 (rval >> 0) & 0xff); 3939 printf(" CardBus bus number: 0x%02x\n", 3940 (rval >> 8) & 0xff); 3941 printf(" Subordinate bus number: 0x%02x\n", 3942 (rval >> 16) & 0xff); 3943 printf(" CardBus latency timer: 0x%02x\n", 3944 (rval >> 24) & 0xff); 3945 3946 /* XXX Print more prettily */ 3947 printf(" CardBus memory region 0:\n"); 3948 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 3949 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 3950 printf(" CardBus memory region 1:\n"); 3951 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 3952 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 3953 printf(" CardBus I/O region 0:\n"); 3954 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 3955 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 3956 printf(" CardBus I/O region 1:\n"); 3957 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 3958 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 3959 3960 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3961 printf(" Interrupt line: 0x%02x\n", 3962 (rval >> 0) & 0xff); 3963 printf(" Interrupt pin: 0x%02x ", 3964 (rval >> 8) & 0xff); 3965 switch ((rval >> 8) & 0xff) { 3966 case PCI_INTERRUPT_PIN_NONE: 3967 printf("(none)"); 3968 break; 3969 case PCI_INTERRUPT_PIN_A: 3970 printf("(pin A)"); 3971 break; 3972 case PCI_INTERRUPT_PIN_B: 3973 printf("(pin B)"); 3974 break; 3975 case PCI_INTERRUPT_PIN_C: 3976 printf("(pin C)"); 3977 break; 3978 case PCI_INTERRUPT_PIN_D: 3979 printf("(pin D)"); 3980 break; 3981 default: 3982 printf("(? ? ?)"); 3983 break; 3984 } 3985 printf("\n"); 3986 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 3987 printf(" Bridge control register: 0x%04x\n", rval); 3988 onoff("Parity error response", rval, __BIT(0)); 3989 onoff("SERR# enable", rval, __BIT(1)); 3990 onoff("ISA enable", rval, __BIT(2)); 3991 onoff("VGA enable", rval, __BIT(3)); 3992 onoff("Master abort mode", rval, __BIT(5)); 3993 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 3994 onoff("Functional interrupts routed by ExCA registers", rval, 3995 __BIT(7)); 3996 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 3997 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 3998 onoff("Write posting enable", rval, __BIT(10)); 3999 4000 rval = regs[o2i(0x40)]; 4001 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4002 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4003 4004 #ifdef _KERNEL 4005 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 4006 sizebars); 4007 #else 4008 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 4009 #endif 4010 } 4011 4012 void 4013 pci_conf_print( 4014 #ifdef _KERNEL 4015 pci_chipset_tag_t pc, pcitag_t tag, 4016 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 4017 #else 4018 int pcifd, u_int bus, u_int dev, u_int func 4019 #endif 4020 ) 4021 { 4022 pcireg_t regs[o2i(PCI_EXTCONF_SIZE)]; 4023 int off, capoff, endoff, hdrtype; 4024 const char *type_name; 4025 #ifdef _KERNEL 4026 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, 4027 int); 4028 int sizebars; 4029 #else 4030 void (*type_printfn)(const pcireg_t *); 4031 #endif 4032 4033 printf("PCI configuration registers:\n"); 4034 4035 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 4036 #ifdef _KERNEL 4037 regs[o2i(off)] = pci_conf_read(pc, tag, off); 4038 #else 4039 if (pcibus_conf_read(pcifd, bus, dev, func, off, 4040 ®s[o2i(off)]) == -1) 4041 regs[o2i(off)] = 0; 4042 #endif 4043 } 4044 4045 #ifdef _KERNEL 4046 sizebars = 1; 4047 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 4048 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 4049 sizebars = 0; 4050 #endif 4051 4052 /* common header */ 4053 printf(" Common header:\n"); 4054 pci_conf_print_regs(regs, 0, 16); 4055 4056 printf("\n"); 4057 #ifdef _KERNEL 4058 pci_conf_print_common(pc, tag, regs); 4059 #else 4060 pci_conf_print_common(regs); 4061 #endif 4062 printf("\n"); 4063 4064 /* type-dependent header */ 4065 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 4066 switch (hdrtype) { /* XXX make a table, eventually */ 4067 case 0: 4068 /* Standard device header */ 4069 type_name = "\"normal\" device"; 4070 type_printfn = &pci_conf_print_type0; 4071 capoff = PCI_CAPLISTPTR_REG; 4072 endoff = 64; 4073 break; 4074 case 1: 4075 /* PCI-PCI bridge header */ 4076 type_name = "PCI-PCI bridge"; 4077 type_printfn = &pci_conf_print_type1; 4078 capoff = PCI_CAPLISTPTR_REG; 4079 endoff = 64; 4080 break; 4081 case 2: 4082 /* PCI-CardBus bridge header */ 4083 type_name = "PCI-CardBus bridge"; 4084 type_printfn = &pci_conf_print_type2; 4085 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 4086 endoff = 72; 4087 break; 4088 default: 4089 type_name = NULL; 4090 type_printfn = 0; 4091 capoff = -1; 4092 endoff = 64; 4093 break; 4094 } 4095 printf(" Type %d ", hdrtype); 4096 if (type_name != NULL) 4097 printf("(%s) ", type_name); 4098 printf("header:\n"); 4099 pci_conf_print_regs(regs, 16, endoff); 4100 printf("\n"); 4101 if (type_printfn) { 4102 #ifdef _KERNEL 4103 (*type_printfn)(pc, tag, regs, sizebars); 4104 #else 4105 (*type_printfn)(regs); 4106 #endif 4107 } else 4108 printf(" Don't know how to pretty-print type %d header.\n", 4109 hdrtype); 4110 printf("\n"); 4111 4112 /* capability list, if present */ 4113 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4114 && (capoff > 0)) { 4115 #ifdef _KERNEL 4116 pci_conf_print_caplist(pc, tag, regs, capoff); 4117 #else 4118 pci_conf_print_caplist(regs, capoff); 4119 #endif 4120 printf("\n"); 4121 } 4122 4123 /* device-dependent header */ 4124 printf(" Device-dependent header:\n"); 4125 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 4126 printf("\n"); 4127 #ifdef _KERNEL 4128 if (printfn) 4129 (*printfn)(pc, tag, regs); 4130 else 4131 printf(" Don't know how to pretty-print device-dependent header.\n"); 4132 printf("\n"); 4133 #endif /* _KERNEL */ 4134 4135 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 4136 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 4137 return; 4138 4139 #ifdef _KERNEL 4140 pci_conf_print_extcaplist(pc, tag, regs, capoff); 4141 #else 4142 pci_conf_print_extcaplist(regs, capoff); 4143 #endif 4144 printf("\n"); 4145 4146 /* Extended Configuration Space, if present */ 4147 printf(" Extended Configuration Space:\n"); 4148 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 4149 } 4150
Indexes created Wed Sep 24 05:09:52 GMT 2025