pci_subr.c revision 1.155
1 /* $NetBSD: pci_subr.c,v 1.155 2016/11/02 00:39:56 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.155 2016/11/02 00:39:56 pgoyette Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdarg.h> 58 #include <stdbool.h> 59 #include <stdio.h> 60 #include <stdlib.h> 61 #include <string.h> 62 #endif 63 64 #include <dev/pci/pcireg.h> 65 #ifdef _KERNEL 66 #include <dev/pci/pcivar.h> 67 #else 68 #include <dev/pci/pci_verbose.h> 69 #include <dev/pci/pcidevs.h> 70 #include <dev/pci/pcidevs_data.h> 71 #endif 72 73 /* 74 * Descriptions of known PCI classes and subclasses. 75 * 76 * Subclasses are described in the same way as classes, but have a 77 * NULL subclass pointer. 78 */ 79 struct pci_class { 80 const char *name; 81 u_int val; /* as wide as pci_{,sub}class_t */ 82 const struct pci_class *subclasses; 83 }; 84 85 /* 86 * Class 0x00. 87 * Before rev. 2.0. 88 */ 89 static const struct pci_class pci_subclass_prehistoric[] = { 90 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 91 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 92 { NULL, 0, NULL, }, 93 }; 94 95 /* 96 * Class 0x01. 97 * Mass storage controller 98 */ 99 100 /* ATA programming interface */ 101 static const struct pci_class pci_interface_ata[] = { 102 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 103 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 104 { NULL, 0, NULL, }, 105 }; 106 107 /* SATA programming interface */ 108 static const struct pci_class pci_interface_sata[] = { 109 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 110 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 111 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 112 { NULL, 0, NULL, }, 113 }; 114 115 /* Flash programming interface */ 116 static const struct pci_class pci_interface_nvm[] = { 117 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 118 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 119 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 120 { NULL, 0, NULL, }, 121 }; 122 123 /* Subclasses */ 124 static const struct pci_class pci_subclass_mass_storage[] = { 125 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 126 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 127 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 128 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 129 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 130 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 131 pci_interface_ata, }, 132 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 133 pci_interface_sata, }, 134 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 135 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 136 pci_interface_nvm, }, 137 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 138 { NULL, 0, NULL, }, 139 }; 140 141 /* 142 * Class 0x02. 143 * Network controller. 144 */ 145 static const struct pci_class pci_subclass_network[] = { 146 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 147 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 148 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 149 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 150 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 151 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 152 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 153 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 154 { NULL, 0, NULL, }, 155 }; 156 157 /* 158 * Class 0x03. 159 * Display controller. 160 */ 161 162 /* VGA programming interface */ 163 static const struct pci_class pci_interface_vga[] = { 164 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 165 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 166 { NULL, 0, NULL, }, 167 }; 168 /* Subclasses */ 169 static const struct pci_class pci_subclass_display[] = { 170 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 171 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 172 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 173 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 174 { NULL, 0, NULL, }, 175 }; 176 177 /* 178 * Class 0x04. 179 * Multimedia device. 180 */ 181 static const struct pci_class pci_subclass_multimedia[] = { 182 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 183 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 184 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 185 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 186 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 187 { NULL, 0, NULL, }, 188 }; 189 190 /* 191 * Class 0x05. 192 * Memory controller. 193 */ 194 static const struct pci_class pci_subclass_memory[] = { 195 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 196 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 197 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 198 { NULL, 0, NULL, }, 199 }; 200 201 /* 202 * Class 0x06. 203 * Bridge device. 204 */ 205 206 /* PCI bridge programming interface */ 207 static const struct pci_class pci_interface_pcibridge[] = { 208 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 209 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 210 { NULL, 0, NULL, }, 211 }; 212 213 /* Semi-transparent PCI-to-PCI bridge programming interface */ 214 static const struct pci_class pci_interface_stpci[] = { 215 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 216 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 217 { NULL, 0, NULL, }, 218 }; 219 220 /* Advanced Switching programming interface */ 221 static const struct pci_class pci_interface_advsw[] = { 222 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 223 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 224 { NULL, 0, NULL, }, 225 }; 226 227 /* Subclasses */ 228 static const struct pci_class pci_subclass_bridge[] = { 229 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 230 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 231 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 232 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 233 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 234 pci_interface_pcibridge, }, 235 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 236 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 237 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 238 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 239 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 240 pci_interface_stpci, }, 241 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 242 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 243 pci_interface_advsw, }, 244 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 245 { NULL, 0, NULL, }, 246 }; 247 248 /* 249 * Class 0x07. 250 * Simple communications controller. 251 */ 252 253 /* Serial controller programming interface */ 254 static const struct pci_class pci_interface_serial[] = { 255 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 256 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 257 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 258 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 259 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 260 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 261 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 262 { NULL, 0, NULL, }, 263 }; 264 265 /* Parallel controller programming interface */ 266 static const struct pci_class pci_interface_parallel[] = { 267 { "", PCI_INTERFACE_PARALLEL, NULL,}, 268 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 269 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 270 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 271 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 272 { NULL, 0, NULL,}, 273 }; 274 275 /* Modem programming interface */ 276 static const struct pci_class pci_interface_modem[] = { 277 { "", PCI_INTERFACE_MODEM, NULL,}, 278 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 279 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 280 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 281 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 282 { NULL, 0, NULL,}, 283 }; 284 285 /* Subclasses */ 286 static const struct pci_class pci_subclass_communications[] = { 287 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 288 pci_interface_serial, }, 289 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 290 pci_interface_parallel, }, 291 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 292 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 293 pci_interface_modem, }, 294 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 295 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 296 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 297 { NULL, 0, NULL,}, 298 }; 299 300 /* 301 * Class 0x08. 302 * Base system peripheral. 303 */ 304 305 /* PIC programming interface */ 306 static const struct pci_class pci_interface_pic[] = { 307 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 308 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 309 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 310 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 311 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 312 { NULL, 0, NULL, }, 313 }; 314 315 /* DMA programming interface */ 316 static const struct pci_class pci_interface_dma[] = { 317 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 318 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 319 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 320 { NULL, 0, NULL, }, 321 }; 322 323 /* Timer programming interface */ 324 static const struct pci_class pci_interface_tmr[] = { 325 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 326 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 327 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 328 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 329 { NULL, 0, NULL, }, 330 }; 331 332 /* RTC programming interface */ 333 static const struct pci_class pci_interface_rtc[] = { 334 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 335 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 336 { NULL, 0, NULL, }, 337 }; 338 339 /* Subclasses */ 340 static const struct pci_class pci_subclass_system[] = { 341 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 342 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 343 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 344 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 345 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 346 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 347 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 348 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 349 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 350 { NULL, 0, NULL, }, 351 }; 352 353 /* 354 * Class 0x09. 355 * Input device. 356 */ 357 358 /* Gameport programming interface */ 359 static const struct pci_class pci_interface_game[] = { 360 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 361 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 362 { NULL, 0, NULL, }, 363 }; 364 365 /* Subclasses */ 366 static const struct pci_class pci_subclass_input[] = { 367 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 368 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 369 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 370 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 371 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 372 pci_interface_game, }, 373 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 374 { NULL, 0, NULL, }, 375 }; 376 377 /* 378 * Class 0x0a. 379 * Docking station. 380 */ 381 static const struct pci_class pci_subclass_dock[] = { 382 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 383 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 384 { NULL, 0, NULL, }, 385 }; 386 387 /* 388 * Class 0x0b. 389 * Processor. 390 */ 391 static const struct pci_class pci_subclass_processor[] = { 392 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 393 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 394 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 395 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 396 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 397 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 398 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 399 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 400 { NULL, 0, NULL, }, 401 }; 402 403 /* 404 * Class 0x0c. 405 * Serial bus controller. 406 */ 407 408 /* IEEE1394 programming interface */ 409 static const struct pci_class pci_interface_ieee1394[] = { 410 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 411 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 412 { NULL, 0, NULL,}, 413 }; 414 415 /* USB programming interface */ 416 static const struct pci_class pci_interface_usb[] = { 417 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 418 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 419 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 420 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 421 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 422 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 423 { NULL, 0, NULL, }, 424 }; 425 426 /* IPMI programming interface */ 427 static const struct pci_class pci_interface_ipmi[] = { 428 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 429 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 430 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 431 { NULL, 0, NULL,}, 432 }; 433 434 /* Subclasses */ 435 static const struct pci_class pci_subclass_serialbus[] = { 436 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 437 pci_interface_ieee1394, }, 438 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 439 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 440 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 441 pci_interface_usb, }, 442 /* XXX Fiber Channel/_FIBRECHANNEL */ 443 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 444 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 445 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 446 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 447 pci_interface_ipmi, }, 448 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 449 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 450 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 451 { NULL, 0, NULL, }, 452 }; 453 454 /* 455 * Class 0x0d. 456 * Wireless Controller. 457 */ 458 static const struct pci_class pci_subclass_wireless[] = { 459 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 460 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 461 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 462 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 463 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 464 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 465 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 466 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 467 { NULL, 0, NULL, }, 468 }; 469 470 /* 471 * Class 0x0e. 472 * Intelligent IO controller. 473 */ 474 475 /* Intelligent IO programming interface */ 476 static const struct pci_class pci_interface_i2o[] = { 477 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 478 { NULL, 0, NULL,}, 479 }; 480 481 /* Subclasses */ 482 static const struct pci_class pci_subclass_i2o[] = { 483 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 484 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 485 { NULL, 0, NULL, }, 486 }; 487 488 /* 489 * Class 0x0f. 490 * Satellite communication controller. 491 */ 492 static const struct pci_class pci_subclass_satcom[] = { 493 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 494 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 495 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 496 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 497 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 498 { NULL, 0, NULL, }, 499 }; 500 501 /* 502 * Class 0x10. 503 * Encryption/Decryption controller. 504 */ 505 static const struct pci_class pci_subclass_crypto[] = { 506 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 507 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 508 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 509 { NULL, 0, NULL, }, 510 }; 511 512 /* 513 * Class 0x11. 514 * Data aquuisition and signal processing controller. 515 */ 516 static const struct pci_class pci_subclass_dasp[] = { 517 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 518 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 519 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 520 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 521 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 522 { NULL, 0, NULL, }, 523 }; 524 525 /* List of classes */ 526 static const struct pci_class pci_class[] = { 527 { "prehistoric", PCI_CLASS_PREHISTORIC, 528 pci_subclass_prehistoric, }, 529 { "mass storage", PCI_CLASS_MASS_STORAGE, 530 pci_subclass_mass_storage, }, 531 { "network", PCI_CLASS_NETWORK, 532 pci_subclass_network, }, 533 { "display", PCI_CLASS_DISPLAY, 534 pci_subclass_display, }, 535 { "multimedia", PCI_CLASS_MULTIMEDIA, 536 pci_subclass_multimedia, }, 537 { "memory", PCI_CLASS_MEMORY, 538 pci_subclass_memory, }, 539 { "bridge", PCI_CLASS_BRIDGE, 540 pci_subclass_bridge, }, 541 { "communications", PCI_CLASS_COMMUNICATIONS, 542 pci_subclass_communications, }, 543 { "system", PCI_CLASS_SYSTEM, 544 pci_subclass_system, }, 545 { "input", PCI_CLASS_INPUT, 546 pci_subclass_input, }, 547 { "dock", PCI_CLASS_DOCK, 548 pci_subclass_dock, }, 549 { "processor", PCI_CLASS_PROCESSOR, 550 pci_subclass_processor, }, 551 { "serial bus", PCI_CLASS_SERIALBUS, 552 pci_subclass_serialbus, }, 553 { "wireless", PCI_CLASS_WIRELESS, 554 pci_subclass_wireless, }, 555 { "I2O", PCI_CLASS_I2O, 556 pci_subclass_i2o, }, 557 { "satellite comm", PCI_CLASS_SATCOM, 558 pci_subclass_satcom, }, 559 { "crypto", PCI_CLASS_CRYPTO, 560 pci_subclass_crypto, }, 561 { "DASP", PCI_CLASS_DASP, 562 pci_subclass_dasp, }, 563 { "undefined", PCI_CLASS_UNDEFINED, 564 NULL, }, 565 { NULL, 0, 566 NULL, }, 567 }; 568 569 DEV_VERBOSE_DEFINE(pci); 570 571 /* 572 * Append a formatted string to dest without writing more than len 573 * characters (including the trailing NUL character). dest and len 574 * are updated for use in subsequent calls to snappendf(). 575 * 576 * Returns 0 on success, a negative value if vnsprintf() fails, or 577 * a positive value if the dest buffer would have overflowed. 578 */ 579 580 static int __printflike(3,4) 581 snappendf(char **dest, size_t *len, const char * restrict fmt, ...) 582 { 583 va_list ap; 584 int count; 585 586 va_start(ap, fmt); 587 count = vsnprintf(*dest, *len, fmt, ap); 588 va_end(ap); 589 590 /* Let vsnprintf() errors bubble up to caller */ 591 if (count < 0 || *len == 0) 592 return count; 593 594 /* Handle overflow */ 595 if ((size_t)count >= *len) { 596 *dest += *len - 1; 597 *len = 1; 598 return 1; 599 } 600 601 /* Update dest & len to point at trailing NUL */ 602 *dest += count; 603 *len -= count; 604 605 return 0; 606 } 607 608 void 609 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 610 size_t l) 611 { 612 pci_class_t pciclass; 613 pci_subclass_t subclass; 614 pci_interface_t interface; 615 pci_revision_t revision; 616 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 617 const struct pci_class *classp, *subclassp, *interfacep; 618 619 pciclass = PCI_CLASS(class_reg); 620 subclass = PCI_SUBCLASS(class_reg); 621 interface = PCI_INTERFACE(class_reg); 622 revision = PCI_REVISION(class_reg); 623 624 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 625 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 626 PCI_PRODUCT(id_reg)); 627 628 classp = pci_class; 629 while (classp->name != NULL) { 630 if (pciclass == classp->val) 631 break; 632 classp++; 633 } 634 635 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 636 while (subclassp && subclassp->name != NULL) { 637 if (subclass == subclassp->val) 638 break; 639 subclassp++; 640 } 641 642 interfacep = (subclassp && subclassp->name != NULL) ? 643 subclassp->subclasses : NULL; 644 while (interfacep && interfacep->name != NULL) { 645 if (interface == interfacep->val) 646 break; 647 interfacep++; 648 } 649 650 (void)snappendf(&cp, &l, "%s %s", vendor, product); 651 if (showclass) { 652 (void)snappendf(&cp, &l, " ("); 653 if (classp->name == NULL) 654 (void)snappendf(&cp, &l, 655 "class 0x%02x, subclass 0x%02x", 656 pciclass, subclass); 657 else { 658 if (subclassp == NULL || subclassp->name == NULL) 659 (void)snappendf(&cp, &l, 660 "%s, subclass 0x%02x", 661 classp->name, subclass); 662 else 663 (void)snappendf(&cp, &l, "%s %s", 664 subclassp->name, classp->name); 665 } 666 if ((interfacep == NULL) || (interfacep->name == NULL)) { 667 if (interface != 0) 668 (void)snappendf(&cp, &l, ", interface 0x%02x", 669 interface); 670 } else if (strncmp(interfacep->name, "", 1) != 0) 671 (void)snappendf(&cp, &l, ", %s", interfacep->name); 672 if (revision != 0) 673 (void)snappendf(&cp, &l, ", revision 0x%02x", revision); 674 (void)snappendf(&cp, &l, ")"); 675 } 676 } 677 678 #ifdef _KERNEL 679 void 680 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 681 const char *known, int addrev) 682 { 683 char devinfo[256]; 684 685 if (known) { 686 aprint_normal(": %s", known); 687 if (addrev) 688 aprint_normal(" (rev. 0x%02x)", 689 PCI_REVISION(pa->pa_class)); 690 aprint_normal("\n"); 691 } else { 692 pci_devinfo(pa->pa_id, pa->pa_class, 0, 693 devinfo, sizeof(devinfo)); 694 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 695 PCI_REVISION(pa->pa_class)); 696 } 697 if (naive) 698 aprint_naive(": %s\n", naive); 699 else 700 aprint_naive("\n"); 701 } 702 #endif 703 704 /* 705 * Print out most of the PCI configuration registers. Typically used 706 * in a device attach routine like this: 707 * 708 * #ifdef MYDEV_DEBUG 709 * printf("%s: ", device_xname(sc->sc_dev)); 710 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 711 * #endif 712 */ 713 714 #define i2o(i) ((i) * 4) 715 #define o2i(o) ((o) / 4) 716 #define onoff2(str, rval, bit, onstr, offstr) \ 717 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 718 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 719 720 static void 721 pci_conf_print_common( 722 #ifdef _KERNEL 723 pci_chipset_tag_t pc, pcitag_t tag, 724 #endif 725 const pcireg_t *regs) 726 { 727 const char *name; 728 const struct pci_class *classp, *subclassp; 729 char vendor[PCI_VENDORSTR_LEN]; 730 char product[PCI_PRODUCTSTR_LEN]; 731 pcireg_t rval; 732 unsigned int num; 733 734 rval = regs[o2i(PCI_ID_REG)]; 735 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 736 if (name) 737 printf(" Vendor Name: %s (0x%04x)\n", name, 738 PCI_VENDOR(rval)); 739 else 740 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 741 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 742 PCI_PRODUCT(rval)); 743 if (name) 744 printf(" Device Name: %s (0x%04x)\n", name, 745 PCI_PRODUCT(rval)); 746 else 747 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 748 749 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 750 751 printf(" Command register: 0x%04x\n", rval & 0xffff); 752 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 753 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 754 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 755 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 756 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 757 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 758 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 759 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 760 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 761 onoff("Fast back-to-back transactions", rval, 762 PCI_COMMAND_BACKTOBACK_ENABLE); 763 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 764 765 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 766 onoff("Immediate Readness", rval, PCI_STATUS_IMMD_READNESS); 767 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 768 "inactive"); 769 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 770 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 771 onoff("User Definable Features (UDF) support", rval, 772 PCI_STATUS_UDF_SUPPORT); 773 onoff("Fast back-to-back capable", rval, 774 PCI_STATUS_BACKTOBACK_SUPPORT); 775 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 776 777 printf(" DEVSEL timing: "); 778 switch (rval & PCI_STATUS_DEVSEL_MASK) { 779 case PCI_STATUS_DEVSEL_FAST: 780 printf("fast"); 781 break; 782 case PCI_STATUS_DEVSEL_MEDIUM: 783 printf("medium"); 784 break; 785 case PCI_STATUS_DEVSEL_SLOW: 786 printf("slow"); 787 break; 788 default: 789 printf("unknown/reserved"); /* XXX */ 790 break; 791 } 792 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 793 794 onoff("Slave signaled Target Abort", rval, 795 PCI_STATUS_TARGET_TARGET_ABORT); 796 onoff("Master received Target Abort", rval, 797 PCI_STATUS_MASTER_TARGET_ABORT); 798 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 799 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 800 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 801 802 rval = regs[o2i(PCI_CLASS_REG)]; 803 for (classp = pci_class; classp->name != NULL; classp++) { 804 if (PCI_CLASS(rval) == classp->val) 805 break; 806 } 807 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 808 while (subclassp && subclassp->name != NULL) { 809 if (PCI_SUBCLASS(rval) == subclassp->val) 810 break; 811 subclassp++; 812 } 813 if (classp->name != NULL) { 814 printf(" Class Name: %s (0x%02x)\n", classp->name, 815 PCI_CLASS(rval)); 816 if (subclassp != NULL && subclassp->name != NULL) 817 printf(" Subclass Name: %s (0x%02x)\n", 818 subclassp->name, PCI_SUBCLASS(rval)); 819 else 820 printf(" Subclass ID: 0x%02x\n", 821 PCI_SUBCLASS(rval)); 822 } else { 823 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 824 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 825 } 826 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 827 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 828 829 rval = regs[o2i(PCI_BHLC_REG)]; 830 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 831 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 832 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 833 PCI_HDRTYPE(rval)); 834 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 835 num = PCI_CACHELINE(rval); 836 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 837 } 838 839 static int 840 pci_conf_print_bar( 841 #ifdef _KERNEL 842 pci_chipset_tag_t pc, pcitag_t tag, 843 #endif 844 const pcireg_t *regs, int reg, const char *name 845 #ifdef _KERNEL 846 , int sizebar 847 #endif 848 ) 849 { 850 int width; 851 pcireg_t rval, rval64h; 852 #ifdef _KERNEL 853 int s; 854 pcireg_t mask, mask64h; 855 #endif 856 857 width = 4; 858 859 /* 860 * Section 6.2.5.1, `Address Maps', tells us that: 861 * 862 * 1) The builtin software should have already mapped the 863 * device in a reasonable way. 864 * 865 * 2) A device which wants 2^n bytes of memory will hardwire 866 * the bottom n bits of the address to 0. As recommended, 867 * we write all 1s and see what we get back. 868 */ 869 870 rval = regs[o2i(reg)]; 871 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 872 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 873 rval64h = regs[o2i(reg + 4)]; 874 width = 8; 875 } else 876 rval64h = 0; 877 878 #ifdef _KERNEL 879 /* XXX don't size unknown memory type? */ 880 if (rval != 0 && sizebar) { 881 /* 882 * The following sequence seems to make some devices 883 * (e.g. host bus bridges, which don't normally 884 * have their space mapped) very unhappy, to 885 * the point of crashing the system. 886 * 887 * Therefore, if the mapping register is zero to 888 * start out with, don't bother trying. 889 */ 890 s = splhigh(); 891 pci_conf_write(pc, tag, reg, 0xffffffff); 892 mask = pci_conf_read(pc, tag, reg); 893 pci_conf_write(pc, tag, reg, rval); 894 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 895 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 896 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 897 mask64h = pci_conf_read(pc, tag, reg + 4); 898 pci_conf_write(pc, tag, reg + 4, rval64h); 899 } else 900 mask64h = 0; 901 splx(s); 902 } else 903 mask = mask64h = 0; 904 #endif /* _KERNEL */ 905 906 printf(" Base address register at 0x%02x", reg); 907 if (name) 908 printf(" (%s)", name); 909 printf("\n "); 910 if (rval == 0) { 911 printf("not implemented(?)\n"); 912 return width; 913 } 914 printf("type: "); 915 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 916 const char *type, *prefetch; 917 918 switch (PCI_MAPREG_MEM_TYPE(rval)) { 919 case PCI_MAPREG_MEM_TYPE_32BIT: 920 type = "32-bit"; 921 break; 922 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 923 type = "32-bit-1M"; 924 break; 925 case PCI_MAPREG_MEM_TYPE_64BIT: 926 type = "64-bit"; 927 break; 928 default: 929 type = "unknown (XXX)"; 930 break; 931 } 932 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 933 prefetch = ""; 934 else 935 prefetch = "non"; 936 printf("%s %sprefetchable memory\n", type, prefetch); 937 switch (PCI_MAPREG_MEM_TYPE(rval)) { 938 case PCI_MAPREG_MEM_TYPE_64BIT: 939 printf(" base: 0x%016llx, ", 940 PCI_MAPREG_MEM64_ADDR( 941 ((((long long) rval64h) << 32) | rval))); 942 #ifdef _KERNEL 943 if (sizebar) 944 printf("size: 0x%016llx", 945 PCI_MAPREG_MEM64_SIZE( 946 ((((long long) mask64h) << 32) | mask))); 947 else 948 #endif /* _KERNEL */ 949 printf("not sized"); 950 printf("\n"); 951 break; 952 case PCI_MAPREG_MEM_TYPE_32BIT: 953 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 954 default: 955 printf(" base: 0x%08x, ", 956 PCI_MAPREG_MEM_ADDR(rval)); 957 #ifdef _KERNEL 958 if (sizebar) 959 printf("size: 0x%08x", 960 PCI_MAPREG_MEM_SIZE(mask)); 961 else 962 #endif /* _KERNEL */ 963 printf("not sized"); 964 printf("\n"); 965 break; 966 } 967 } else { 968 #ifdef _KERNEL 969 if (sizebar) 970 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 971 #endif /* _KERNEL */ 972 printf("i/o\n"); 973 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 974 #ifdef _KERNEL 975 if (sizebar) 976 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 977 else 978 #endif /* _KERNEL */ 979 printf("not sized"); 980 printf("\n"); 981 } 982 983 return width; 984 } 985 986 static void 987 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 988 { 989 int off, needaddr, neednl; 990 991 needaddr = 1; 992 neednl = 0; 993 for (off = first; off < pastlast; off += 4) { 994 if ((off % 16) == 0 || needaddr) { 995 printf(" 0x%02x:", off); 996 needaddr = 0; 997 } 998 printf(" 0x%08x", regs[o2i(off)]); 999 neednl = 1; 1000 if ((off % 16) == 12) { 1001 printf("\n"); 1002 neednl = 0; 1003 } 1004 } 1005 if (neednl) 1006 printf("\n"); 1007 } 1008 1009 static void 1010 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1011 { 1012 pcireg_t rval; 1013 1014 printf("\n AGP Capabilities Register\n"); 1015 1016 rval = regs[o2i(capoff)]; 1017 printf(" Revision: %d.%d\n", 1018 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1019 1020 /* XXX need more */ 1021 } 1022 1023 static const char * 1024 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1025 { 1026 1027 switch ((caps >> 6) & 7) { 1028 case 0: return "self-powered"; 1029 case 1: return "55 mA"; 1030 case 2: return "100 mA"; 1031 case 3: return "160 mA"; 1032 case 4: return "220 mA"; 1033 case 5: return "270 mA"; 1034 case 6: return "320 mA"; 1035 case 7: 1036 default: return "375 mA"; 1037 } 1038 } 1039 1040 static const char * 1041 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1042 { 1043 static const char unk[] = "unknown"; 1044 static const char *pmrev[8] = { 1045 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1046 }; 1047 if (val > 7) 1048 return unk; 1049 return pmrev[val]; 1050 } 1051 1052 static void 1053 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1054 { 1055 uint16_t caps, pmcsr; 1056 pcireg_t reg; 1057 1058 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1059 reg = regs[o2i(capoff + PCI_PMCSR)]; 1060 pmcsr = reg & 0xffff; 1061 1062 printf("\n PCI Power Management Capabilities Register\n"); 1063 1064 printf(" Capabilities register: 0x%04x\n", caps); 1065 printf(" Version: %s\n", 1066 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1067 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1068 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1069 printf(" 3.3V auxiliary current: %s\n", 1070 pci_conf_print_pcipm_cap_aux(caps)); 1071 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1072 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1073 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1074 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1075 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1076 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1077 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1078 1079 printf(" Control/status register: 0x%04x\n", pmcsr); 1080 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1081 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1082 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1083 printf(" PME# assertion: %sabled\n", 1084 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1085 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1086 printf(" Bridge Support Extensions register: 0x%02x\n", 1087 (reg >> 16) & 0xff); 1088 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1089 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1090 printf(" Data register: 0x%02x\n", (reg >> 24) & 0xff); 1091 1092 } 1093 1094 /* XXX pci_conf_print_vpd_cap */ 1095 /* XXX pci_conf_print_slotid_cap */ 1096 1097 static void 1098 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1099 { 1100 uint32_t ctl, mmc, mme; 1101 1102 regs += o2i(capoff); 1103 ctl = *regs++; 1104 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1105 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1106 1107 printf("\n PCI Message Signaled Interrupt\n"); 1108 1109 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1110 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1111 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1112 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1113 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1114 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1115 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1116 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1117 onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP); 1118 onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN); 1119 printf(" Message Address %sregister: 0x%08x\n", 1120 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1121 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1122 printf(" Message Address %sregister: 0x%08x\n", 1123 "(upper) ", *regs++); 1124 } 1125 printf(" Message Data register: 0x%08x\n", *regs++); 1126 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1127 printf(" Vector Mask register: 0x%08x\n", *regs++); 1128 printf(" Vector Pending register: 0x%08x\n", *regs++); 1129 } 1130 } 1131 1132 /* XXX pci_conf_print_cpci_hostwap_cap */ 1133 1134 /* 1135 * For both command register and status register. 1136 * The argument "idx" is index number (0 to 7). 1137 */ 1138 static int 1139 pcix_split_trans(unsigned int idx) 1140 { 1141 static int table[8] = { 1142 1, 2, 3, 4, 8, 12, 16, 32 1143 }; 1144 1145 if (idx >= __arraycount(table)) 1146 return -1; 1147 return table[idx]; 1148 } 1149 1150 static void 1151 pci_conf_print_pcix_cap_2ndbusmode(int num) 1152 { 1153 const char *maxfreq, *maxperiod; 1154 1155 printf(" Mode: "); 1156 if (num <= 0x07) 1157 printf("PCI-X Mode 1\n"); 1158 else if (num <= 0x0b) 1159 printf("PCI-X 266 (Mode 2)\n"); 1160 else 1161 printf("PCI-X 533 (Mode 2)\n"); 1162 1163 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1164 switch (num & 0x03) { 1165 default: 1166 case 0: 1167 maxfreq = "N/A"; 1168 maxperiod = "N/A"; 1169 break; 1170 case 1: 1171 maxfreq = "66MHz"; 1172 maxperiod = "15ns"; 1173 break; 1174 case 2: 1175 maxfreq = "100MHz"; 1176 maxperiod = "10ns"; 1177 break; 1178 case 3: 1179 maxfreq = "133MHz"; 1180 maxperiod = "7.5ns"; 1181 break; 1182 } 1183 printf(" Max Clock Freq: %s\n", maxfreq); 1184 printf(" Min Clock Period: %s\n", maxperiod); 1185 } 1186 1187 static void 1188 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1189 { 1190 pcireg_t reg; 1191 int isbridge; 1192 int i; 1193 1194 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1195 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1196 printf("\n PCI-X %s Capabilities Register\n", 1197 isbridge ? "Bridge" : "Non-bridge"); 1198 1199 reg = regs[o2i(capoff)]; 1200 if (isbridge != 0) { 1201 printf(" Secondary status register: 0x%04x\n", 1202 (reg & 0xffff0000) >> 16); 1203 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1204 onoff("133MHz capable", reg, PCIX_STATUS_133); 1205 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1206 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1207 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1208 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1209 pci_conf_print_pcix_cap_2ndbusmode( 1210 __SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1211 printf(" Version: 0x%x\n", 1212 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1213 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1214 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1215 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1216 } else { 1217 printf(" Command register: 0x%04x\n", 1218 (reg & 0xffff0000) >> 16); 1219 onoff("Data Parity Error Recovery", reg, 1220 PCIX_CMD_PERR_RECOVER); 1221 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1222 printf(" Maximum Burst Read Count: %u\n", 1223 PCIX_CMD_BYTECNT(reg)); 1224 printf(" Maximum Split Transactions: %d\n", 1225 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1226 >> PCIX_CMD_SPLTRANS_SHIFT)); 1227 } 1228 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1229 printf(" %sStatus register: 0x%08x\n", 1230 isbridge ? "Bridge " : "", reg); 1231 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1232 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1233 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1234 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1235 onoff("133MHz capable", reg, PCIX_STATUS_133); 1236 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1237 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1238 if (isbridge != 0) { 1239 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1240 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1241 } else { 1242 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1243 "bridge device", "simple device"); 1244 printf(" Designed max memory read byte count: %d\n", 1245 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1246 >> PCIX_STATUS_MAXB_SHIFT)); 1247 printf(" Designed max outstanding split transaction: %d\n", 1248 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1249 >> PCIX_STATUS_MAXST_SHIFT)); 1250 printf(" MAX cumulative Read Size: %u\n", 1251 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1252 onoff("Received split completion error", reg, 1253 PCIX_STATUS_SCERR); 1254 } 1255 onoff("266MHz capable", reg, PCIX_STATUS_266); 1256 onoff("533MHz capable", reg, PCIX_STATUS_533); 1257 1258 if (isbridge == 0) 1259 return; 1260 1261 /* Only for bridge */ 1262 for (i = 0; i < 2; i++) { 1263 reg = regs[o2i(capoff+PCIX_BRIDGE_UP_STCR + (4 * i))]; 1264 printf(" %s split transaction control register: 0x%08x\n", 1265 (i == 0) ? "Upstream" : "Downstream", reg); 1266 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1267 printf(" Commitment Limit: %d\n", 1268 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1269 } 1270 } 1271 1272 /* pci_conf_print_ht_slave_cap */ 1273 /* pci_conf_print_ht_host_cap */ 1274 /* pci_conf_print_ht_switch_cap */ 1275 /* pci_conf_print_ht_intr_cap */ 1276 /* pci_conf_print_ht_revid_cap */ 1277 /* pci_conf_print_ht_unitid_cap */ 1278 /* pci_conf_print_ht_extcnf_cap */ 1279 /* pci_conf_print_ht_addrmap_cap */ 1280 /* pci_conf_print_ht_msimap_cap */ 1281 1282 static void 1283 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1284 { 1285 pcireg_t val; 1286 uint32_t lo, hi; 1287 1288 /* 1289 * Print the rest of the command register bits. Others are 1290 * printed in pci_conf_print_ht_cap(). 1291 */ 1292 val = regs[o2i(capoff + PCI_HT_CMD)]; 1293 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1294 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1295 1296 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1297 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1298 printf(" Address Low register: 0x%08x\n", lo); 1299 printf(" Address high register: 0x%08x\n", hi); 1300 printf(" Address: 0x%016" PRIx64 "\n", 1301 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1302 } 1303 1304 /* pci_conf_print_ht_droute_cap */ 1305 /* pci_conf_print_ht_vcset_cap */ 1306 /* pci_conf_print_ht_retry_cap */ 1307 /* pci_conf_print_ht_x86enc_cap */ 1308 /* pci_conf_print_ht_gen3_cap */ 1309 /* pci_conf_print_ht_fle_cap */ 1310 /* pci_conf_print_ht_pm_cap */ 1311 /* pci_conf_print_ht_hnc_cap */ 1312 1313 static const struct ht_types { 1314 pcireg_t cap; 1315 const char *name; 1316 void (*printfunc)(const pcireg_t *, int); 1317 } ht_captab[] = { 1318 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1319 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1320 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1321 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1322 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1323 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1324 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1325 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1326 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1327 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1328 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1329 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1330 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1331 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1332 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1333 {PCI_HT_CAP_PM, "Power Management", NULL }, 1334 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1335 }; 1336 1337 static void 1338 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1339 { 1340 pcireg_t val, foundcap; 1341 unsigned int off; 1342 1343 val = regs[o2i(capoff + PCI_HT_CMD)]; 1344 1345 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1346 1347 printf(" Command register: 0x%04x\n", val >> 16); 1348 foundcap = PCI_HT_CAP(val); 1349 for (off = 0; off < __arraycount(ht_captab); off++) { 1350 if (ht_captab[off].cap == foundcap) 1351 break; 1352 } 1353 printf(" Capability Type: 0x%02x ", foundcap); 1354 if (off >= __arraycount(ht_captab)) { 1355 printf("(unknown)\n"); 1356 return; 1357 } 1358 printf("(%s)\n", ht_captab[off].name); 1359 if (ht_captab[off].printfunc != NULL) 1360 ht_captab[off].printfunc(regs, capoff); 1361 } 1362 1363 static void 1364 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1365 { 1366 uint16_t caps; 1367 1368 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1369 1370 printf("\n PCI Vendor Specific Capabilities Register\n"); 1371 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1372 } 1373 1374 static void 1375 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1376 { 1377 pcireg_t val; 1378 1379 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1380 1381 printf("\n Debugport Capability Register\n"); 1382 printf(" Debug base Register: 0x%04x\n", 1383 val >> PCI_DEBUG_BASER_SHIFT); 1384 printf(" port offset: 0x%04x\n", 1385 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1386 printf(" BAR number: %u\n", 1387 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1388 } 1389 1390 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1391 /* XXX pci_conf_print_hotplug_cap */ 1392 1393 static void 1394 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1395 { 1396 pcireg_t reg; 1397 1398 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1399 1400 printf("\n Subsystem ID Capability Register\n"); 1401 printf(" Subsystem ID : 0x%08x\n", reg); 1402 } 1403 1404 /* XXX pci_conf_print_agp8_cap */ 1405 /* XXX pci_conf_print_secure_cap */ 1406 1407 static void 1408 pci_print_pcie_L0s_latency(uint32_t val) 1409 { 1410 1411 switch (val) { 1412 case 0x0: 1413 printf("Less than 64ns\n"); 1414 break; 1415 case 0x1: 1416 case 0x2: 1417 case 0x3: 1418 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1419 break; 1420 case 0x4: 1421 printf("512ns to less than 1us\n"); 1422 break; 1423 case 0x5: 1424 printf("1us to less than 2us\n"); 1425 break; 1426 case 0x6: 1427 printf("2us - 4us\n"); 1428 break; 1429 case 0x7: 1430 printf("More than 4us\n"); 1431 break; 1432 } 1433 } 1434 1435 static void 1436 pci_print_pcie_L1_latency(uint32_t val) 1437 { 1438 1439 switch (val) { 1440 case 0x0: 1441 printf("Less than 1us\n"); 1442 break; 1443 case 0x6: 1444 printf("32us - 64us\n"); 1445 break; 1446 case 0x7: 1447 printf("More than 64us\n"); 1448 break; 1449 default: 1450 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1451 break; 1452 } 1453 } 1454 1455 static void 1456 pci_print_pcie_compl_timeout(uint32_t val) 1457 { 1458 1459 switch (val) { 1460 case 0x0: 1461 printf("50us to 50ms\n"); 1462 break; 1463 case 0x5: 1464 printf("16ms to 55ms\n"); 1465 break; 1466 case 0x6: 1467 printf("65ms to 210ms\n"); 1468 break; 1469 case 0x9: 1470 printf("260ms to 900ms\n"); 1471 break; 1472 case 0xa: 1473 printf("1s to 3.5s\n"); 1474 break; 1475 default: 1476 printf("unknown %u value\n", val); 1477 break; 1478 } 1479 } 1480 1481 static const char * const pcie_linkspeeds[] = {"2.5", "5.0", "8.0"}; 1482 1483 static void 1484 pci_print_pcie_linkspeed(pcireg_t val) 1485 { 1486 1487 /* Start from 1 */ 1488 if (val < 1 || val > __arraycount(pcie_linkspeeds)) 1489 printf("unknown value (%u)\n", val); 1490 else 1491 printf("%sGT/s\n", pcie_linkspeeds[val - 1]); 1492 } 1493 1494 static void 1495 pci_print_pcie_linkspeedvector(pcireg_t val) 1496 { 1497 unsigned int i; 1498 1499 /* Start from 0 */ 1500 for (i = 0; i < 16; i++) 1501 if (((val >> i) & 0x01) != 0) { 1502 if (i >= __arraycount(pcie_linkspeeds)) 1503 printf(" unknown vector (%x)", 1 << i); 1504 else 1505 printf(" %sGT/s", pcie_linkspeeds[i]); 1506 } 1507 } 1508 1509 static void 1510 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1511 { 1512 pcireg_t reg; /* for each register */ 1513 pcireg_t val; /* for each bitfield */ 1514 bool check_link = false; 1515 bool check_slot = false; 1516 bool check_rootport = false; 1517 unsigned int pciever; 1518 1519 printf("\n PCI Express Capabilities Register\n"); 1520 /* Capability Register */ 1521 reg = regs[o2i(capoff)]; 1522 printf(" Capability register: %04x\n", reg >> 16); 1523 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1524 printf(" Capability version: %u\n", pciever); 1525 printf(" Device type: "); 1526 switch ((reg & 0x00f00000) >> 20) { 1527 case 0x0: 1528 printf("PCI Express Endpoint device\n"); 1529 check_link = true; 1530 break; 1531 case 0x1: 1532 printf("Legacy PCI Express Endpoint device\n"); 1533 check_link = true; 1534 break; 1535 case 0x4: 1536 printf("Root Port of PCI Express Root Complex\n"); 1537 check_link = true; 1538 check_slot = true; 1539 check_rootport = true; 1540 break; 1541 case 0x5: 1542 printf("Upstream Port of PCI Express Switch\n"); 1543 break; 1544 case 0x6: 1545 printf("Downstream Port of PCI Express Switch\n"); 1546 check_slot = true; 1547 check_rootport = true; 1548 break; 1549 case 0x7: 1550 printf("PCI Express to PCI/PCI-X Bridge\n"); 1551 break; 1552 case 0x8: 1553 printf("PCI/PCI-X to PCI Express Bridge\n"); 1554 break; 1555 case 0x9: 1556 printf("Root Complex Integrated Endpoint\n"); 1557 break; 1558 case 0xa: 1559 check_rootport = true; 1560 printf("Root Complex Event Collector\n"); 1561 break; 1562 default: 1563 printf("unknown\n"); 1564 break; 1565 } 1566 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1567 printf(" Interrupt Message Number: %x\n", 1568 (unsigned int)((reg & PCIE_XCAP_IRQ) >> 27)); 1569 1570 /* Device Capability Register */ 1571 reg = regs[o2i(capoff + PCIE_DCAP)]; 1572 printf(" Device Capabilities Register: 0x%08x\n", reg); 1573 printf(" Max Payload Size Supported: %u bytes max\n", 1574 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1575 printf(" Phantom Functions Supported: "); 1576 switch ((reg & PCIE_DCAP_PHANTOM_FUNCS) >> 3) { 1577 case 0x0: 1578 printf("not available\n"); 1579 break; 1580 case 0x1: 1581 printf("MSB\n"); 1582 break; 1583 case 0x2: 1584 printf("two MSB\n"); 1585 break; 1586 case 0x3: 1587 printf("All three bits\n"); 1588 break; 1589 } 1590 printf(" Extended Tag Field Supported: %dbit\n", 1591 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1592 printf(" Endpoint L0 Acceptable Latency: "); 1593 pci_print_pcie_L0s_latency((reg & PCIE_DCAP_L0S_LATENCY) >> 6); 1594 printf(" Endpoint L1 Acceptable Latency: "); 1595 pci_print_pcie_L1_latency((reg & PCIE_DCAP_L1_LATENCY) >> 9); 1596 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1597 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1598 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1599 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1600 printf(" Captured Slot Power Limit Value: %d\n", 1601 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18); 1602 printf(" Captured Slot Power Limit Scale: %d\n", 1603 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26); 1604 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1605 1606 /* Device Control Register */ 1607 reg = regs[o2i(capoff + PCIE_DCSR)]; 1608 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1609 onoff("Correctable Error Reporting Enable", reg, 1610 PCIE_DCSR_ENA_COR_ERR); 1611 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1612 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1613 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1614 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1615 printf(" Max Payload Size: %d byte\n", 1616 128 << (((unsigned int)(reg & PCIE_DCSR_MAX_PAYLOAD) >> 5))); 1617 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1618 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1619 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1620 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1621 printf(" Max Read Request Size: %d byte\n", 1622 128 << ((unsigned int)(reg & PCIE_DCSR_MAX_READ_REQ) >> 12)); 1623 1624 /* Device Status Register */ 1625 reg = regs[o2i(capoff + PCIE_DCSR)]; 1626 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1627 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1628 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1629 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1630 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1631 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1632 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1633 onoff("Emergency Power Reduction Detected", reg, 1634 PCIE_DCSR_EMGPWRREDD); 1635 1636 if (check_link) { 1637 /* Link Capability Register */ 1638 reg = regs[o2i(capoff + PCIE_LCAP)]; 1639 printf(" Link Capabilities Register: 0x%08x\n", reg); 1640 printf(" Maximum Link Speed: "); 1641 pci_print_pcie_linkspeed(reg & PCIE_LCAP_MAX_SPEED); 1642 printf(" Maximum Link Width: x%u lanes\n", 1643 (unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4); 1644 printf(" Active State PM Support: "); 1645 val = (reg & PCIE_LCAP_ASPM) >> 10; 1646 switch (val) { 1647 case 0x0: 1648 printf("No ASPM support\n"); 1649 break; 1650 case 0x1: 1651 printf("L0s supported\n"); 1652 break; 1653 case 0x2: 1654 printf("L1 supported\n"); 1655 break; 1656 case 0x3: 1657 printf("L0s and L1 supported\n"); 1658 break; 1659 } 1660 printf(" L0 Exit Latency: "); 1661 pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12); 1662 printf(" L1 Exit Latency: "); 1663 pci_print_pcie_L1_latency((reg & PCIE_LCAP_L1_EXIT) >> 15); 1664 printf(" Port Number: %u\n", reg >> 24); 1665 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1666 onoff("Surprise Down Error Report", reg, 1667 PCIE_LCAP_SURPRISE_DOWN); 1668 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1669 onoff("Link BW Notification Capable", reg, 1670 PCIE_LCAP_LINK_BW_NOTIFY); 1671 onoff("ASPM Optionally Compliance", reg, 1672 PCIE_LCAP_ASPM_COMPLIANCE); 1673 1674 /* Link Control Register */ 1675 reg = regs[o2i(capoff + PCIE_LCSR)]; 1676 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1677 printf(" Active State PM Control: "); 1678 val = reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S); 1679 switch (val) { 1680 case 0: 1681 printf("disabled\n"); 1682 break; 1683 case 1: 1684 printf("L0s Entry Enabled\n"); 1685 break; 1686 case 2: 1687 printf("L1 Entry Enabled\n"); 1688 break; 1689 case 3: 1690 printf("L0s and L1 Entry Enabled\n"); 1691 break; 1692 } 1693 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1694 "128bytes", "64bytes"); 1695 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1696 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1697 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1698 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1699 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1700 onoff("Hardware Autonomous Width Disable", reg, 1701 PCIE_LCSR_HAWD); 1702 onoff("Link Bandwidth Management Interrupt Enable", reg, 1703 PCIE_LCSR_LBMIE); 1704 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1705 PCIE_LCSR_LABIE); 1706 printf(" DRS Signaling Control: "); 1707 val = __SHIFTOUT(reg, PCIE_LCSR_DRSSGNL); 1708 switch (val) { 1709 case 0: 1710 printf("not reported\n"); 1711 break; 1712 case 1: 1713 printf("Interrupt Enabled\n"); 1714 break; 1715 case 2: 1716 printf("DRS to FRS Signaling Enabled\n"); 1717 break; 1718 default: 1719 printf("reserved\n"); 1720 break; 1721 } 1722 1723 /* Link Status Register */ 1724 reg = regs[o2i(capoff + PCIE_LCSR)]; 1725 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1726 printf(" Negotiated Link Speed: "); 1727 pci_print_pcie_linkspeed(__SHIFTOUT(reg, PCIE_LCSR_LINKSPEED)); 1728 printf(" Negotiated Link Width: x%u lanes\n", 1729 (reg >> 20) & 0x003f); 1730 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1731 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1732 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1733 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1734 onoff("Link Bandwidth Management Status", reg, 1735 PCIE_LCSR_LINK_BW_MGMT); 1736 onoff("Link Autonomous Bandwidth Status", reg, 1737 PCIE_LCSR_LINK_AUTO_BW); 1738 } 1739 1740 if (check_slot == true) { 1741 /* Slot Capability Register */ 1742 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1743 printf(" Slot Capability Register: %08x\n", reg); 1744 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1745 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1746 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1747 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1748 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1749 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1750 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1751 printf(" Slot Power Limit Value: %d\n", 1752 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1753 printf(" Slot Power Limit Scale: %d\n", 1754 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1755 onoff("Electromechanical Interlock Present", reg, 1756 PCIE_SLCAP_EIP); 1757 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1758 printf(" Physical Slot Number: %d\n", 1759 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1760 1761 /* Slot Control Register */ 1762 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1763 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1764 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1765 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1766 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1767 onoff("Presense Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1768 onoff("Command Completed Interrupt Enabled", reg, 1769 PCIE_SLCSR_CCE); 1770 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1771 printf(" Attention Indicator Control: "); 1772 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1773 case 0x0: 1774 printf("reserved\n"); 1775 break; 1776 case 0x1: 1777 printf("on\n"); 1778 break; 1779 case 0x2: 1780 printf("blink\n"); 1781 break; 1782 case 0x3: 1783 printf("off\n"); 1784 break; 1785 } 1786 printf(" Power Indicator Control: "); 1787 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1788 case 0x0: 1789 printf("reserved\n"); 1790 break; 1791 case 0x1: 1792 printf("on\n"); 1793 break; 1794 case 0x2: 1795 printf("blink\n"); 1796 break; 1797 case 0x3: 1798 printf("off\n"); 1799 break; 1800 } 1801 onoff("Power Controller Control", reg, PCIE_SLCSR_PCC); 1802 onoff("Electromechanical Interlock Control", 1803 reg, PCIE_SLCSR_EIC); 1804 onoff("Data Link Layer State Changed Enable", reg, 1805 PCIE_SLCSR_DLLSCE); 1806 onoff("Auto Slot Power Limit Disable", reg, 1807 PCIE_SLCSR_AUTOSPLDIS); 1808 1809 /* Slot Status Register */ 1810 printf(" Slot Status Register: %04x\n", reg >> 16); 1811 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1812 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1813 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1814 onoff("Presense Detect Changed", reg, PCIE_SLCSR_PDC); 1815 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1816 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1817 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1818 onoff("Electromechanical Interlock engaged", reg, 1819 PCIE_SLCSR_EIS); 1820 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 1821 } 1822 1823 if (check_rootport == true) { 1824 /* Root Control Register */ 1825 reg = regs[o2i(capoff + PCIE_RCR)]; 1826 printf(" Root Control Register: %04x\n", reg & 0xffff); 1827 onoff("SERR on Correctable Error Enable", reg, 1828 PCIE_RCR_SERR_CER); 1829 onoff("SERR on Non-Fatal Error Enable", reg, 1830 PCIE_RCR_SERR_NFER); 1831 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 1832 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 1833 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 1834 1835 /* Root Capability Register */ 1836 printf(" Root Capability Register: %04x\n", 1837 reg >> 16); 1838 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 1839 1840 /* Root Status Register */ 1841 reg = regs[o2i(capoff + PCIE_RSR)]; 1842 printf(" Root Status Register: %08x\n", reg); 1843 printf(" PME Requester ID: %04x\n", 1844 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1845 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 1846 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 1847 } 1848 1849 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1850 if (pciever < 2) 1851 return; 1852 1853 /* Device Capabilities 2 */ 1854 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1855 printf(" Device Capabilities 2: 0x%08x\n", reg); 1856 printf(" Completion Timeout Ranges Supported: %u \n", 1857 (unsigned int)(reg & PCIE_DCAP2_COMPT_RANGE)); 1858 onoff("Completion Timeout Disable Supported", reg, 1859 PCIE_DCAP2_COMPT_DIS); 1860 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 1861 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 1862 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 1863 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 1864 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 1865 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 1866 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 1867 printf(" TPH Completer Supported: %u\n", 1868 (unsigned int)(reg & PCIE_DCAP2_TPH_COMP) >> 12); 1869 printf(" LN System CLS: "); 1870 switch (__SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 1871 case 0x0: 1872 printf("Not supported or not in effect\n"); 1873 break; 1874 case 0x1: 1875 printf("64byte cachelines in effect\n"); 1876 break; 1877 case 0x2: 1878 printf("128byte cachelines in effect\n"); 1879 break; 1880 case 0x3: 1881 printf("Reserved\n"); 1882 break; 1883 } 1884 printf(" OBFF Supported: "); 1885 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 1886 case 0x0: 1887 printf("Not supported\n"); 1888 break; 1889 case 0x1: 1890 printf("Message only\n"); 1891 break; 1892 case 0x2: 1893 printf("WAKE# only\n"); 1894 break; 1895 case 0x3: 1896 printf("Both\n"); 1897 break; 1898 } 1899 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 1900 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 1901 printf(" Max End-End TLP Prefixes: %u\n", 1902 (unsigned int)(reg & PCIE_DCAP2_MAX_EETLP) >> 22); 1903 printf(" Emergency Power Reduction Supported: "); 1904 switch (__SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) { 1905 case 0x0: 1906 printf("Not supported\n"); 1907 break; 1908 case 0x1: 1909 printf("Device Specific mechanism\n"); 1910 break; 1911 case 0x2: 1912 printf("Form Factor spec or Device Specific mechanism\n"); 1913 break; 1914 case 0x3: 1915 printf("Reserved\n"); 1916 break; 1917 } 1918 onoff("Emergency Power Reduction Initialization Required", reg, 1919 PCIE_DCAP2_EMGPWRRED_INI); 1920 onoff("FRS Supported", reg, PCIE_DCAP2_FRS); 1921 1922 /* Device Control 2 */ 1923 reg = regs[o2i(capoff + PCIE_DCSR2)]; 1924 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 1925 printf(" Completion Timeout Value: "); 1926 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 1927 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 1928 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 1929 onoff("AtomicOp Rquester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 1930 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 1931 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 1932 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 1933 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 1934 onoff("Emergency Power Reduction Request", reg, 1935 PCIE_DCSR2_EMGPWRRED_REQ); 1936 printf(" OBFF: "); 1937 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 1938 case 0x0: 1939 printf("Disabled\n"); 1940 break; 1941 case 0x1: 1942 printf("Enabled with Message Signaling Variation A\n"); 1943 break; 1944 case 0x2: 1945 printf("Enabled with Message Signaling Variation B\n"); 1946 break; 1947 case 0x3: 1948 printf("Enabled using WAKE# signaling\n"); 1949 break; 1950 } 1951 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 1952 1953 if (check_link) { 1954 bool drs_supported; 1955 1956 /* Link Capability 2 */ 1957 reg = regs[o2i(capoff + PCIE_LCAP2)]; 1958 printf(" Link Capabilities 2: 0x%08x\n", reg); 1959 printf(" Supported Link Speed Vector:"); 1960 pci_print_pcie_linkspeedvector( 1961 __SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV)); 1962 printf("\n"); 1963 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 1964 printf(" Lower SKP OS Generation Supported Speed Vector:"); 1965 pci_print_pcie_linkspeedvector( 1966 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV)); 1967 printf("\n"); 1968 printf(" Lower SKP OS Reception Supported Speed Vector:"); 1969 pci_print_pcie_linkspeedvector( 1970 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV)); 1971 printf("\n"); 1972 onoff("DRS Supported", reg, PCIE_LCAP2_DRS); 1973 drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false; 1974 1975 /* Link Control 2 */ 1976 reg = regs[o2i(capoff + PCIE_LCSR2)]; 1977 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 1978 printf(" Target Link Speed: "); 1979 pci_print_pcie_linkspeed(__SHIFTOUT(reg, 1980 PCIE_LCSR2_TGT_LSPEED)); 1981 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 1982 onoff("HW Autonomous Speed Disabled", reg, 1983 PCIE_LCSR2_HW_AS_DIS); 1984 onoff("Selectable De-emphasis", reg, PCIE_LCSR2_SEL_DEEMP); 1985 printf(" Transmit Margin: %u\n", 1986 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 1987 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 1988 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 1989 printf(" Compliance Present/De-emphasis: %u\n", 1990 (unsigned int)(reg & PCIE_LCSR2_COMP_DEEMP) >> 12); 1991 1992 /* Link Status 2 */ 1993 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 1994 onoff("Current De-emphasis Level", reg, PCIE_LCSR2_DEEMP_LVL); 1995 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 1996 onoff("Equalization Phase 1 Successful", reg, 1997 PCIE_LCSR2_EQP1_SUC); 1998 onoff("Equalization Phase 2 Successful", reg, 1999 PCIE_LCSR2_EQP2_SUC); 2000 onoff("Equalization Phase 3 Successful", reg, 2001 PCIE_LCSR2_EQP3_SUC); 2002 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 2003 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD); 2004 if (drs_supported) { 2005 printf(" Downstream Component Presence: "); 2006 switch (__SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) { 2007 case PCIE_DSCOMPN_DOWN_NOTDETERM: 2008 printf("Link Down - Presence Not" 2009 " Determined\n"); 2010 break; 2011 case PCIE_DSCOMPN_DOWN_NOTPRES: 2012 printf("Link Down - Component Not Present\n"); 2013 break; 2014 case PCIE_DSCOMPN_DOWN_PRES: 2015 printf("Link Down - Component Present\n"); 2016 break; 2017 case PCIE_DSCOMPN_UP_PRES: 2018 printf("Link Up - Component Present\n"); 2019 break; 2020 case PCIE_DSCOMPN_UP_PRES_DRS: 2021 printf("Link Up - Component Present and DRS" 2022 " received\n"); 2023 break; 2024 default: 2025 printf("reserved\n"); 2026 break; 2027 } 2028 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV); 2029 } 2030 } 2031 2032 /* Slot Capability 2 */ 2033 /* Slot Control 2 */ 2034 /* Slot Status 2 */ 2035 } 2036 2037 static void 2038 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 2039 { 2040 pcireg_t reg; 2041 2042 printf("\n MSI-X Capability Register\n"); 2043 2044 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2045 printf(" Message Control register: 0x%04x\n", 2046 (reg >> 16) & 0xff); 2047 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 2048 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 2049 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 2050 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 2051 printf(" Table offset register: 0x%08x\n", reg); 2052 printf(" Table offset: %08x\n", 2053 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 2054 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 2055 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 2056 printf(" Pending bit array register: 0x%08x\n", reg); 2057 printf(" Pending bit array offset: %08x\n", 2058 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 2059 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 2060 } 2061 2062 static void 2063 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 2064 { 2065 pcireg_t reg; 2066 2067 printf("\n Serial ATA Capability Register\n"); 2068 2069 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2070 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 2071 printf(" Revision: %u.%u\n", 2072 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 2073 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 2074 2075 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 2076 2077 printf(" BAR Register: 0x%08x\n", reg); 2078 printf(" Register location: "); 2079 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 2080 printf("in config space\n"); 2081 else { 2082 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 2083 printf(" BAR offset: 0x%08x\n", 2084 (pcireg_t)__SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 2085 } 2086 } 2087 2088 static void 2089 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 2090 { 2091 pcireg_t reg; 2092 2093 printf("\n Advanced Features Capability Register\n"); 2094 2095 reg = regs[o2i(capoff + PCI_AFCAPR)]; 2096 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 2097 printf(" AF Structure Length: 0x%02x\n", 2098 (pcireg_t)__SHIFTOUT(reg, PCI_AF_LENGTH)); 2099 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 2100 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 2101 reg = regs[o2i(capoff + PCI_AFCSR)]; 2102 printf(" AF Control register: 0x%02x\n", reg & 0xff); 2103 /* 2104 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 2105 * and it's always 0 on read 2106 */ 2107 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 2108 onoff("Transaction Pending", reg, PCI_AFSR_TP); 2109 } 2110 2111 static struct { 2112 pcireg_t cap; 2113 const char *name; 2114 void (*printfunc)(const pcireg_t *, int); 2115 } pci_captab[] = { 2116 { PCI_CAP_RESERVED0, "reserved", NULL }, 2117 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 2118 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 2119 { PCI_CAP_VPD, "VPD", NULL }, 2120 { PCI_CAP_SLOTID, "SlotID", NULL }, 2121 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 2122 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 2123 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2124 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2125 { PCI_CAP_VENDSPEC, "Vendor-specific", 2126 pci_conf_print_vendspec_cap }, 2127 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2128 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2129 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2130 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2131 pci_conf_print_subsystem_cap }, 2132 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2133 { PCI_CAP_SECURE, "Secure Device", NULL }, 2134 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2135 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2136 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2137 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2138 { PCI_CAP_EA, "Enhanced Allocation", NULL } 2139 }; 2140 2141 static int 2142 pci_conf_find_cap(const pcireg_t *regs, int capoff, unsigned int capid, 2143 int *offsetp) 2144 { 2145 pcireg_t rval; 2146 int off; 2147 2148 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2149 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2150 rval = regs[o2i(off)]; 2151 if (capid == PCI_CAPLIST_CAP(rval)) { 2152 if (offsetp != NULL) 2153 *offsetp = off; 2154 return 1; 2155 } 2156 } 2157 return 0; 2158 } 2159 2160 static void 2161 pci_conf_print_caplist( 2162 #ifdef _KERNEL 2163 pci_chipset_tag_t pc, pcitag_t tag, 2164 #endif 2165 const pcireg_t *regs, int capoff) 2166 { 2167 int off; 2168 pcireg_t foundcap; 2169 pcireg_t rval; 2170 bool foundtable[__arraycount(pci_captab)]; 2171 unsigned int i; 2172 2173 /* Clear table */ 2174 for (i = 0; i < __arraycount(pci_captab); i++) 2175 foundtable[i] = false; 2176 2177 /* Print capability register's offset and the type first */ 2178 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2179 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2180 rval = regs[o2i(off)]; 2181 printf(" Capability register at 0x%02x\n", off); 2182 2183 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2184 foundcap = PCI_CAPLIST_CAP(rval); 2185 if (foundcap < __arraycount(pci_captab)) { 2186 printf("%s)\n", pci_captab[foundcap].name); 2187 /* Mark as found */ 2188 foundtable[foundcap] = true; 2189 } else 2190 printf("unknown)\n"); 2191 } 2192 2193 /* 2194 * And then, print the detail of each capability registers 2195 * in capability value's order. 2196 */ 2197 for (i = 0; i < __arraycount(pci_captab); i++) { 2198 if (foundtable[i] == false) 2199 continue; 2200 2201 /* 2202 * The type was found. Search capability list again and 2203 * print all capabilities that the capabiliy type is 2204 * the same. This is required because some capabilities 2205 * appear multiple times (e.g. HyperTransport capability). 2206 */ 2207 #if 0 2208 if (pci_conf_find_cap(regs, capoff, i, &off)) { 2209 rval = regs[o2i(off)]; 2210 if (pci_captab[i].printfunc != NULL) 2211 pci_captab[i].printfunc(regs, off); 2212 } 2213 #else 2214 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2215 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2216 rval = regs[o2i(off)]; 2217 if ((PCI_CAPLIST_CAP(rval) == i) 2218 && (pci_captab[i].printfunc != NULL)) 2219 pci_captab[i].printfunc(regs, off); 2220 } 2221 #endif 2222 } 2223 } 2224 2225 /* Extended Capability */ 2226 2227 static void 2228 pci_conf_print_aer_cap_uc(pcireg_t reg) 2229 { 2230 2231 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2232 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2233 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2234 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP); 2235 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2236 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2237 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2238 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2239 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2240 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2241 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2242 onoff("Unsupported Request Error", reg, 2243 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2244 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2245 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2246 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2247 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2248 onoff("TLP Prefix Blocked Error", reg, 2249 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2250 onoff("Poisoned TLP Egress Blocked", reg, 2251 PCI_AER_UC_POISONTLP_EGRESS_BLOCKED); 2252 } 2253 2254 static void 2255 pci_conf_print_aer_cap_cor(pcireg_t reg) 2256 { 2257 2258 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2259 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2260 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2261 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2262 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2263 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2264 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2265 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2266 } 2267 2268 static void 2269 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2270 { 2271 2272 printf(" First Error Pointer: 0x%04x\n", 2273 (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2274 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2275 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2276 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2277 onoff("ECRC Check Enab", reg, PCI_AER_ECRC_CHECK_ENABLE); 2278 onoff("Multiple Header Recording Capable", reg, 2279 PCI_AER_MULT_HDR_CAPABLE); 2280 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE); 2281 onoff("Completion Timeout Prefix/Header Log Capable", reg, 2282 PCI_AER_COMPTOUTPRFXHDRLOG_CAP); 2283 2284 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2285 if (!tlp_prefix_log) 2286 return; 2287 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2288 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2289 } 2290 2291 static void 2292 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2293 { 2294 2295 onoff("Correctable Error Reporting Enable", reg, 2296 PCI_AER_ROOTERR_COR_ENABLE); 2297 onoff("Non-Fatal Error Reporting Enable", reg, 2298 PCI_AER_ROOTERR_NF_ENABLE); 2299 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2300 } 2301 2302 static void 2303 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2304 { 2305 2306 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2307 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2308 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2309 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2310 PCI_AER_ROOTERR_MULTI_UC_ERR); 2311 onoff("First Uncorrectable Fatal", reg, PCI_AER_ROOTERR_FIRST_UC_FATAL); 2312 onoff("Non-Fatal Error Messages Received", reg, PCI_AER_ROOTERR_NF_ERR); 2313 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2314 printf(" Advanced Error Interrupt Message Number: 0x%u\n", 2315 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2316 } 2317 2318 static void 2319 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2320 { 2321 2322 printf(" Correctable Source ID: 0x%04x\n", 2323 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2324 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2325 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2326 } 2327 2328 static void 2329 pci_conf_print_aer_cap(const pcireg_t *regs, int capoff, int extcapoff) 2330 { 2331 pcireg_t reg; 2332 int pcie_capoff; 2333 int pcie_devtype = -1; 2334 bool tlp_prefix_log = false; 2335 2336 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2337 reg = regs[o2i(pcie_capoff)]; 2338 pcie_devtype = PCIE_XCAP_TYPE(reg); 2339 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2340 if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2341 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2342 /* End-End TLP Prefix Supported */ 2343 if (reg & PCIE_DCAP2_EETLP_PREF) { 2344 tlp_prefix_log = true; 2345 } 2346 } 2347 } 2348 2349 printf("\n Advanced Error Reporting Register\n"); 2350 2351 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2352 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2353 pci_conf_print_aer_cap_uc(reg); 2354 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2355 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2356 pci_conf_print_aer_cap_uc(reg); 2357 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2358 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2359 pci_conf_print_aer_cap_uc(reg); 2360 2361 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2362 printf(" Correctable Error Status register: 0x%08x\n", reg); 2363 pci_conf_print_aer_cap_cor(reg); 2364 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2365 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2366 pci_conf_print_aer_cap_cor(reg); 2367 2368 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2369 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2370 reg); 2371 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2372 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2373 printf(" Header Log register:\n"); 2374 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2375 extcapoff + PCI_AER_ROOTERR_CMD); 2376 2377 switch (pcie_devtype) { 2378 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ 2379 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ 2380 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2381 printf(" Root Error Command register: 0x%08x\n", reg); 2382 pci_conf_print_aer_cap_rooterr_cmd(reg); 2383 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2384 printf(" Root Error Status register: 0x%08x\n", reg); 2385 pci_conf_print_aer_cap_rooterr_status(reg); 2386 2387 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2388 printf(" Error Source Identification: 0x%04x\n", reg); 2389 pci_conf_print_aer_cap_errsrc_id(reg); 2390 break; 2391 } 2392 2393 if (tlp_prefix_log) { 2394 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2395 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2396 } 2397 } 2398 2399 static void 2400 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2401 pcireg_t parbsel, int parbsize) 2402 { 2403 pcireg_t reg; 2404 int num = 16 << parbsel; 2405 int num_per_reg = sizeof(pcireg_t) / parbsize; 2406 int i, j; 2407 2408 /* First, dump the table */ 2409 for (i = 0; i < num; i += num_per_reg) { 2410 reg = regs[o2i(off + i / num_per_reg)]; 2411 printf(" %s Arbitration Table: 0x%08x\n", name, reg); 2412 } 2413 /* And then, decode each entry */ 2414 for (i = 0; i < num; i += num_per_reg) { 2415 reg = regs[o2i(off + i / num_per_reg)]; 2416 for (j = 0; j < num_per_reg; j++) 2417 printf(" Phase[%d]: %d\n", j, reg); 2418 } 2419 } 2420 2421 static void 2422 pci_conf_print_vc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2423 { 2424 pcireg_t reg, n; 2425 int parbtab, parbsize; 2426 pcireg_t parbsel; 2427 int varbtab, varbsize; 2428 pcireg_t varbsel; 2429 int i, count; 2430 2431 printf("\n Virtual Channel Register\n"); 2432 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2433 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2434 count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2435 printf(" Extended VC Count: %d\n", count); 2436 n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2437 printf(" Low Priority Extended VC Count: %u\n", n); 2438 n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2439 printf(" Reference Clock: %s\n", 2440 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 2441 parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2442 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2443 2444 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 2445 printf(" Port VC Capability register 2: 0x%08x\n", reg); 2446 onoff("Hardware fixed arbitration scheme", 2447 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 2448 onoff("WRR arbitration with 32 phases", 2449 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 2450 onoff("WRR arbitration with 64 phases", 2451 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 2452 onoff("WRR arbitration with 128 phases", 2453 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 2454 varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 2455 printf(" VC Arbitration Table Offset: 0x%x\n", varbtab); 2456 2457 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 2458 printf(" Port VC Control register: 0x%04x\n", reg); 2459 varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 2460 printf(" VC Arbitration Select: 0x%x\n", varbsel); 2461 2462 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 2463 printf(" Port VC Status register: 0x%04x\n", reg); 2464 onoff("VC Arbitration Table Status", 2465 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 2466 2467 for (i = 0; i < count + 1; i++) { 2468 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 2469 printf(" VC number %d\n", i); 2470 printf(" VC Resource Capability Register: 0x%08x\n", reg); 2471 onoff(" Non-configurable Hardware fixed arbitration scheme", 2472 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 2473 onoff(" WRR arbitration with 32 phases", 2474 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 2475 onoff(" WRR arbitration with 64 phases", 2476 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 2477 onoff(" WRR arbitration with 128 phases", 2478 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 2479 onoff(" Time-based WRR arbitration with 128 phases", 2480 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 2481 onoff(" WRR arbitration with 256 phases", 2482 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 2483 onoff(" Advanced Packet Switching", 2484 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 2485 onoff(" Reject Snoop Transaction", 2486 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 2487 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 2488 printf(" Maximum Time Slots: %d\n", n); 2489 parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S; 2490 printf(" Port Arbitration Table offset: 0x%02x\n", 2491 parbtab); 2492 2493 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 2494 printf(" VC Resource Control Register: 0x%08x\n", reg); 2495 printf(" TC/VC Map: %02x\n", 2496 (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 2497 /* 2498 * The load Port Arbitration Table bit is used to update 2499 * the Port Arbitration logic and it's always 0 on read, so 2500 * we don't print it. 2501 */ 2502 parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 2503 printf(" Port Arbitration Select: %x\n", parbsel); 2504 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 2505 printf(" VC ID %d\n", n); 2506 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 2507 2508 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 2509 printf(" VC Resource Status Register: 0x%08x\n", reg); 2510 onoff(" Port Arbitration Table Status", 2511 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 2512 onoff(" VC Negotiation Pending", 2513 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 2514 2515 if ((parbtab != 0) && (parbsel != 0)) 2516 pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab, 2517 "Port", parbsel, parbsize); 2518 } 2519 2520 varbsize = 8; 2521 if ((varbtab != 0) && (varbsel != 0)) 2522 pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab, 2523 " VC", varbsel, varbsize); 2524 } 2525 2526 static const char * 2527 pci_conf_print_pwrbdgt_base_power(uint8_t reg) 2528 { 2529 2530 switch (reg) { 2531 case 0xf0: 2532 return "239W < x <= 250W"; 2533 case 0xf1: 2534 return "250W < x <= 275W"; 2535 case 0xf2: 2536 return "275W < x <= 300W"; 2537 default: 2538 break; 2539 } 2540 if (reg >= 0xf3) 2541 return "reserved for above 300W"; 2542 2543 return "Unknown"; 2544 } 2545 2546 static const char * 2547 pci_conf_print_pwrbdgt_data_scale(uint8_t reg) 2548 { 2549 2550 switch (reg) { 2551 case 0x00: 2552 return "1.0x"; 2553 case 0x01: 2554 return "0.1x"; 2555 case 0x02: 2556 return "0.01x"; 2557 case 0x03: 2558 return "0.001x"; 2559 default: 2560 return "wrong value!"; 2561 } 2562 } 2563 2564 static const char * 2565 pci_conf_print_pwrbdgt_type(uint8_t reg) 2566 { 2567 2568 switch (reg) { 2569 case 0x00: 2570 return "PME Aux"; 2571 case 0x01: 2572 return "Auxilary"; 2573 case 0x02: 2574 return "Idle"; 2575 case 0x03: 2576 return "Sustained"; 2577 case 0x04: 2578 return "Sustained (Emergency Power Reduction)"; 2579 case 0x05: 2580 return "Maximum (Emergency Power Reduction)"; 2581 case 0x07: 2582 return "Maximun"; 2583 default: 2584 return "Unknown"; 2585 } 2586 } 2587 2588 static const char * 2589 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 2590 { 2591 2592 switch (reg) { 2593 case 0x00: 2594 return "Power(12V)"; 2595 case 0x01: 2596 return "Power(3.3V)"; 2597 case 0x02: 2598 return "Power(1.5V or 1.8V)"; 2599 case 0x07: 2600 return "Thermal"; 2601 default: 2602 return "Unknown"; 2603 } 2604 } 2605 2606 static void 2607 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff) 2608 { 2609 pcireg_t reg; 2610 2611 printf("\n Power Budget Register\n"); 2612 2613 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 2614 printf(" Data Select register: 0x%08x\n", reg); 2615 2616 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 2617 printf(" Data register: 0x%08x\n", reg); 2618 printf(" Base Power: %s\n", 2619 pci_conf_print_pwrbdgt_base_power((uint8_t)reg)); 2620 printf(" Data Scale: %s\n", 2621 pci_conf_print_pwrbdgt_data_scale( 2622 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE)))); 2623 printf(" PM Sub State: 0x%hhx\n", 2624 (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 2625 printf(" PM State: D%u\n", 2626 (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 2627 printf(" Type: %s\n", 2628 pci_conf_print_pwrbdgt_type( 2629 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 2630 printf(" Power Rail: %s\n", 2631 pci_conf_print_pwrbdgt_pwrrail( 2632 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 2633 2634 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 2635 printf(" Power Budget Capability register: 0x%08x\n", reg); 2636 onoff("System Allocated", 2637 reg, PCI_PWRBDGT_CAP_SYSALLOC); 2638 } 2639 2640 static const char * 2641 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 2642 { 2643 2644 switch (type) { 2645 case 0x00: 2646 return "Configuration Space Element"; 2647 case 0x01: 2648 return "System Egress Port or internal sink (memory)"; 2649 case 0x02: 2650 return "Internal Root Complex Link"; 2651 default: 2652 return "Unknown"; 2653 } 2654 } 2655 2656 static void 2657 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int capoff, int extcapoff) 2658 { 2659 pcireg_t reg; 2660 unsigned char nent, linktype; 2661 int i; 2662 2663 printf("\n Root Complex Link Declaration\n"); 2664 2665 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 2666 printf(" Element Self Description Register: 0x%08x\n", reg); 2667 printf(" Element Type: %s\n", 2668 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 2669 nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 2670 printf(" Number of Link Entries: %hhu\n", nent); 2671 printf(" Component ID: %hhu\n", 2672 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 2673 printf(" Port Number: %hhu\n", 2674 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 2675 for (i = 0; i < nent; i++) { 2676 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 2677 printf(" Link Entry %d:\n", i + 1); 2678 printf(" Link Description Register: 0x%08x\n", reg); 2679 onoff(" Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID); 2680 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 2681 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 2682 "Configuration Space", "Memory-Mapped Space"); 2683 onoff(" Associated RCRB Header", reg, 2684 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 2685 printf(" Target Component ID: %hhu\n", 2686 (unsigned char)__SHIFTOUT(reg, 2687 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 2688 printf(" Target Port Number: %hhu\n", 2689 (unsigned char)__SHIFTOUT(reg, 2690 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 2691 2692 if (linktype == 0) { 2693 /* Memory-Mapped Space */ 2694 reg = regs[o2i(extcapoff 2695 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 2696 printf(" Link Address Low Register: 0x%08x\n", 2697 reg); 2698 reg = regs[o2i(extcapoff 2699 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 2700 printf(" Link Address High Register: 0x%08x\n", 2701 reg); 2702 } else { 2703 unsigned int nb; 2704 pcireg_t lo, hi; 2705 2706 /* Configuration Space */ 2707 lo = regs[o2i(extcapoff 2708 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 2709 printf(" Configuration Space Low Register: " 2710 "0x%08x\n", lo); 2711 hi = regs[o2i(extcapoff 2712 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 2713 printf(" Configuration Space High Register: " 2714 "0x%08x\n", hi); 2715 nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 2716 printf(" N: %u\n", nb); 2717 printf(" Func: %hhu\n", 2718 (unsigned char)__SHIFTOUT(lo, 2719 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 2720 printf(" Dev: %hhu\n", 2721 (unsigned char)__SHIFTOUT(lo, 2722 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 2723 printf(" Bus: %hhu\n", 2724 (unsigned char)__SHIFTOUT(lo, 2725 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 2726 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 2727 printf(" Configuration Space Base Address: " 2728 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 2729 } 2730 } 2731 } 2732 2733 /* XXX pci_conf_print_rclink_ctl_cap */ 2734 2735 static void 2736 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2737 { 2738 pcireg_t reg; 2739 2740 printf("\n Root Complex Event Collector Association\n"); 2741 2742 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 2743 printf(" Association Bitmap for Root Complex Integrated Devices:" 2744 " 0x%08x\n", reg); 2745 } 2746 2747 /* XXX pci_conf_print_mfvc_cap */ 2748 /* XXX pci_conf_print_vc2_cap */ 2749 /* XXX pci_conf_print_rcrb_cap */ 2750 /* XXX pci_conf_print_vendor_cap */ 2751 /* XXX pci_conf_print_cac_cap */ 2752 2753 static void 2754 pci_conf_print_acs_cap(const pcireg_t *regs, int capoff, int extcapoff) 2755 { 2756 pcireg_t reg, cap, ctl; 2757 unsigned int size, i; 2758 2759 printf("\n Access Control Services\n"); 2760 2761 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 2762 cap = reg & 0xffff; 2763 ctl = reg >> 16; 2764 printf(" ACS Capability register: 0x%08x\n", cap); 2765 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 2766 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 2767 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 2768 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 2769 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 2770 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 2771 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 2772 size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 2773 if (size == 0) 2774 size = 256; 2775 printf(" Egress Control Vector Size: %u\n", size); 2776 printf(" ACS Control register: 0x%08x\n", ctl); 2777 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 2778 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 2779 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 2780 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 2781 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 2782 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 2783 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 2784 2785 /* 2786 * If the P2P Egress Control Capability bit is 0, ignore the Egress 2787 * Control vector. 2788 */ 2789 if ((cap & PCI_ACS_CAP_E) == 0) 2790 return; 2791 for (i = 0; i < size; i += 32) 2792 printf(" Egress Control Vector [%u..%u]: %x\n", i + 31, 2793 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 2794 } 2795 2796 static void 2797 pci_conf_print_ari_cap(const pcireg_t *regs, int capoff, int extcapoff) 2798 { 2799 pcireg_t reg, cap, ctl; 2800 2801 printf("\n Alternative Routing-ID Interpretation Register\n"); 2802 2803 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2804 cap = reg & 0xffff; 2805 ctl = reg >> 16; 2806 printf(" Capability register: 0x%08x\n", cap); 2807 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 2808 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 2809 printf(" Next Function Number: %u\n", 2810 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 2811 printf(" Control register: 0x%08x\n", ctl); 2812 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 2813 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 2814 printf(" Function Group: %u\n", 2815 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 2816 } 2817 2818 static void 2819 pci_conf_print_ats_cap(const pcireg_t *regs, int capoff, int extcapoff) 2820 { 2821 pcireg_t reg, cap, ctl; 2822 unsigned int num; 2823 2824 printf("\n Address Translation Services\n"); 2825 2826 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2827 cap = reg & 0xffff; 2828 ctl = reg >> 16; 2829 printf(" Capability register: 0x%04x\n", cap); 2830 num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 2831 if (num == 0) 2832 num = 32; 2833 printf(" Invalidate Queue Depth: %u\n", num); 2834 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 2835 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 2836 2837 printf(" Control register: 0x%04x\n", ctl); 2838 printf(" Smallest Translation Unit: %u\n", 2839 (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU)); 2840 onoff("Enable", reg, PCI_ATS_CTL_EN); 2841 } 2842 2843 static void 2844 pci_conf_print_sernum_cap(const pcireg_t *regs, int capoff, int extcapoff) 2845 { 2846 pcireg_t lo, hi; 2847 2848 printf("\n Device Serial Number Register\n"); 2849 2850 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 2851 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 2852 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 2853 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 2854 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 2855 } 2856 2857 static void 2858 pci_conf_print_sriov_cap(const pcireg_t *regs, int capoff, int extcapoff) 2859 { 2860 char buf[sizeof("99999 MB")]; 2861 pcireg_t reg; 2862 pcireg_t total_vfs; 2863 int i; 2864 bool first; 2865 2866 printf("\n Single Root IO Virtualization Register\n"); 2867 2868 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 2869 printf(" Capabilities register: 0x%08x\n", reg); 2870 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 2871 onoff("ARI Capable Hierarchy Preserved", reg, 2872 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 2873 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 2874 printf(" VF Migration Interrupt Message Number: 0x%u\n", 2875 (pcireg_t)__SHIFTOUT(reg, 2876 PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 2877 } 2878 2879 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 2880 printf(" Control register: 0x%04x\n", reg); 2881 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 2882 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 2883 onoff("VF Migration Interrupt Enable", reg, 2884 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 2885 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 2886 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 2887 2888 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 2889 printf(" Status register: 0x%04x\n", reg); 2890 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 2891 2892 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 2893 printf(" InitialVFs register: 0x%04x\n", reg); 2894 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 2895 printf(" TotalVFs register: 0x%04x\n", reg); 2896 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 2897 printf(" NumVFs register: 0x%04x\n", reg); 2898 2899 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 2900 printf(" Function Dependency Link register: 0x%04x\n", reg); 2901 2902 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 2903 printf(" First VF Offset register: 0x%04x\n", reg); 2904 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 2905 printf(" VF Stride register: 0x%04x\n", reg); 2906 2907 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 2908 printf(" Supported Page Sizes register: 0x%08x\n", reg); 2909 printf(" Supported Page Size:"); 2910 for (i = 0, first = true; i < 32; i++) { 2911 if (reg & __BIT(i)) { 2912 #ifdef _KERNEL 2913 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 2914 #else 2915 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 2916 HN_AUTOSCALE, 0); 2917 #endif 2918 printf("%s %s", first ? "" : ",", buf); 2919 first = false; 2920 } 2921 } 2922 printf("\n"); 2923 2924 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 2925 printf(" System Page Sizes register: 0x%08x\n", reg); 2926 printf(" Page Size: "); 2927 if (reg != 0) { 2928 #ifdef _KERNEL 2929 format_bytes(buf, sizeof(buf), 1LL << (ffs(reg) + 12)); 2930 #else 2931 humanize_number(buf, sizeof(buf), 1LL << (ffs(reg) + 12), "B", 2932 HN_AUTOSCALE, 0); 2933 #endif 2934 printf("%s", buf); 2935 } else { 2936 printf("unknown"); 2937 } 2938 printf("\n"); 2939 2940 for (i = 0; i < 6; i++) { 2941 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 2942 printf(" VF BAR%d register: 0x%08x\n", i, reg); 2943 } 2944 2945 if (total_vfs > 0) { 2946 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 2947 printf(" VF Migration State Array Offset register: 0x%08x\n", 2948 reg); 2949 printf(" VF Migration State Offset: 0x%08x\n", 2950 (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 2951 i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 2952 printf(" VF Migration State BIR: "); 2953 if (i >= 0 && i <= 5) { 2954 printf("BAR%d", i); 2955 } else { 2956 printf("unknown BAR (%d)", i); 2957 } 2958 printf("\n"); 2959 } 2960 } 2961 2962 /* XXX pci_conf_print_mriov_cap */ 2963 2964 static void 2965 pci_conf_print_multicast_cap(const pcireg_t *regs, int capoff, int extcapoff) 2966 { 2967 pcireg_t reg, cap, ctl; 2968 pcireg_t regl, regh; 2969 uint64_t addr; 2970 int n; 2971 2972 printf("\n Multicast\n"); 2973 2974 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 2975 cap = reg & 0xffff; 2976 ctl = reg >> 16; 2977 printf(" Capability Register: 0x%04x\n", cap); 2978 printf(" Max Group: %u\n", 2979 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 2980 2981 /* Endpoint Only */ 2982 n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 2983 if (n > 0) 2984 printf(" Windw Size Requested: %d\n", 1 << (n - 1)); 2985 2986 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 2987 2988 printf(" Control Register: 0x%04x\n", ctl); 2989 printf(" Num Group: %u\n", 2990 (unsigned int)__SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 2991 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 2992 2993 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 2994 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 2995 printf(" Base Address Register 0: 0x%08x\n", regl); 2996 printf(" Base Address Register 1: 0x%08x\n", regh); 2997 printf(" Index Position: %u\n", 2998 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 2999 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 3000 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 3001 3002 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 3003 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 3004 printf(" Receive Register 0: 0x%08x\n", regl); 3005 printf(" Receive Register 1: 0x%08x\n", regh); 3006 3007 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 3008 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 3009 printf(" Block All Register 0: 0x%08x\n", regl); 3010 printf(" Block All Register 1: 0x%08x\n", regh); 3011 3012 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 3013 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 3014 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 3015 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 3016 3017 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 3018 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 3019 printf(" Overlay BAR 0: 0x%08x\n", regl); 3020 printf(" Overlay BAR 1: 0x%08x\n", regh); 3021 3022 n = regl & PCI_MCAST_OVERLAYL_SIZE; 3023 printf(" Overlay Size: "); 3024 if (n >= 6) 3025 printf("%d\n", n); 3026 else 3027 printf("off\n"); 3028 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 3029 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 3030 } 3031 3032 static void 3033 pci_conf_print_page_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3034 { 3035 pcireg_t reg, ctl, sta; 3036 3037 printf("\n Page Request\n"); 3038 3039 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 3040 ctl = reg & 0xffff; 3041 sta = reg >> 16; 3042 printf(" Control Register: 0x%04x\n", ctl); 3043 onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E); 3044 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 3045 3046 printf(" Status Register: 0x%04x\n", sta); 3047 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 3048 onoff("Unexpected Page Request Group Index", reg, 3049 PCI_PAGE_REQ_STA_UPRGI); 3050 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 3051 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 3052 3053 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 3054 printf(" Outstanding Page Request Capacity: %u\n", reg); 3055 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 3056 printf(" Outstanding Page Request Allocation: %u\n", reg); 3057 } 3058 3059 /* XXX pci_conf_print_amd_cap */ 3060 3061 #define MEM_PBUFSIZE sizeof("999GB") 3062 3063 static void 3064 pci_conf_print_resizbar_cap(const pcireg_t *regs, int capoff, int extcapoff) 3065 { 3066 pcireg_t cap, ctl; 3067 unsigned int bars, i, n; 3068 char pbuf[MEM_PBUFSIZE]; 3069 3070 printf("\n Resizable BAR\n"); 3071 3072 /* Get Number of Resizable BARs */ 3073 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))]; 3074 bars = __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR); 3075 printf(" Number of Resizable BARs: "); 3076 if (bars <= 6) 3077 printf("%u\n", bars); 3078 else { 3079 printf("incorrect (%u)\n", bars); 3080 return; 3081 } 3082 3083 for (n = 0; n < 6; n++) { 3084 cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))]; 3085 printf(" Capability register(%u): 0x%08x\n", n, cap); 3086 if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0) 3087 continue; /* Not Used */ 3088 printf(" Acceptable BAR sizes:"); 3089 for (i = 4; i <= 23; i++) { 3090 if ((cap & (1 << i)) != 0) { 3091 humanize_number(pbuf, MEM_PBUFSIZE, 3092 (int64_t)1024 * 1024 << (i - 4), "B", 3093 #ifdef _KERNEL 3094 1); 3095 #else 3096 HN_AUTOSCALE, HN_NOSPACE); 3097 #endif 3098 printf(" %s", pbuf); 3099 } 3100 } 3101 printf("\n"); 3102 3103 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))]; 3104 printf(" Control register(%u): 0x%08x\n", n, ctl); 3105 printf(" BAR Index: %u\n", 3106 (unsigned int)__SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX)); 3107 humanize_number(pbuf, MEM_PBUFSIZE, 3108 (int64_t)1024 * 1024 3109 << __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ), 3110 "B", 3111 #ifdef _KERNEL 3112 1); 3113 #else 3114 HN_AUTOSCALE, HN_NOSPACE); 3115 #endif 3116 printf(" BAR Size: %s\n", pbuf); 3117 } 3118 } 3119 3120 static void 3121 pci_conf_print_dpa_cap(const pcireg_t *regs, int capoff, int extcapoff) 3122 { 3123 pcireg_t reg; 3124 unsigned int substmax, i; 3125 3126 printf("\n Dynamic Power Allocation\n"); 3127 3128 reg = regs[o2i(extcapoff + PCI_DPA_CAP)]; 3129 printf(" Capability register: 0x%08x\n", reg); 3130 substmax = __SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX); 3131 printf(" Substate Max: %u\n", substmax); 3132 printf(" Transition Latency Unit: "); 3133 switch (__SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) { 3134 case 0: 3135 printf("1ms\n"); 3136 break; 3137 case 1: 3138 printf("10ms\n"); 3139 break; 3140 case 2: 3141 printf("100ms\n"); 3142 break; 3143 default: 3144 printf("reserved\n"); 3145 break; 3146 } 3147 printf(" Power Allocation Scale: "); 3148 switch (__SHIFTOUT(reg, PCI_DPA_CAP_PAS)) { 3149 case 0: 3150 printf("10.0x\n"); 3151 break; 3152 case 1: 3153 printf("1.0x\n"); 3154 break; 3155 case 2: 3156 printf("0.1x\n"); 3157 break; 3158 case 3: 3159 printf("0.01x\n"); 3160 break; 3161 } 3162 printf(" Transition Latency Value 0: %u\n", 3163 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY0)); 3164 printf(" Transition Latency Value 1: %u\n", 3165 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY1)); 3166 3167 reg = regs[o2i(extcapoff + PCI_DPA_LATIND)]; 3168 printf(" Latency Indicatior register: 0x%08x\n", reg); 3169 3170 reg = regs[o2i(extcapoff + PCI_DPA_CS)]; 3171 printf(" Status register: 0x%04x\n", reg & 0xffff); 3172 printf(" Substate Status: %02x\n", 3173 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT)); 3174 onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN); 3175 printf(" Control register: 0x%04x\n", reg >> 16); 3176 printf(" Substate Control: %02x\n", 3177 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL)); 3178 3179 for (i = 0; i <= substmax; i++) 3180 printf(" Substate Power Allocation register %d: 0x%02x\n", 3181 i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff)); 3182 } 3183 3184 static const char * 3185 pci_conf_print_tph_req_cap_sttabloc(unsigned char val) 3186 { 3187 3188 switch (val) { 3189 case 0x0: 3190 return "Not Present"; 3191 case 0x1: 3192 return "in the TPH Requester Capability Structure"; 3193 case 0x2: 3194 return "in the MSI-X Table"; 3195 default: 3196 return "Unknown"; 3197 } 3198 } 3199 3200 static void 3201 pci_conf_print_tph_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3202 { 3203 pcireg_t reg; 3204 int size, i, j; 3205 3206 printf("\n TPH Requester Extended Capability\n"); 3207 3208 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 3209 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 3210 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 3211 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 3212 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 3213 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 3214 printf(" ST Table Location: %s\n", 3215 pci_conf_print_tph_req_cap_sttabloc( 3216 (unsigned char)__SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC))); 3217 size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 3218 printf(" ST Table Size: %d\n", size); 3219 for (i = 0; i < size ; i += 2) { 3220 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 3221 for (j = 0; j < 2 ; j++) { 3222 uint32_t entry = reg; 3223 3224 if (j != 0) 3225 entry >>= 16; 3226 entry &= 0xffff; 3227 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 3228 i + j, entry); 3229 } 3230 } 3231 } 3232 3233 static void 3234 pci_conf_print_ltr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3235 { 3236 pcireg_t reg; 3237 3238 printf("\n Latency Tolerance Reporting\n"); 3239 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)] & 0xffff; 3240 printf(" Max Snoop Latency Register: 0x%04x\n", reg); 3241 printf(" Max Snoop LatencyValue: %u\n", 3242 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL)); 3243 printf(" Max Snoop LatencyScale: %uns\n", 3244 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE))); 3245 reg = regs[o2i(extcapoff + PCI_LTR_MAXNOSNOOPLAT)] >> 16; 3246 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg); 3247 printf(" Max No-Snoop LatencyValue: %u\n", 3248 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL)); 3249 printf(" Max No-Snoop LatencyScale: %uns\n", 3250 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE))); 3251 } 3252 3253 static void 3254 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int capoff, int extcapoff) 3255 { 3256 int pcie_capoff; 3257 pcireg_t reg; 3258 int i, maxlinkwidth; 3259 3260 printf("\n Secondary PCI Express Register\n"); 3261 3262 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3263 printf(" Link Control 3 register: 0x%08x\n", reg); 3264 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3265 onoff("Link Equalization Request Interrupt Enable", 3266 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3267 printf(" Enable Lower SKP OS Generation Vector:"); 3268 pci_print_pcie_linkspeedvector( 3269 __SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV)); 3270 printf("\n"); 3271 3272 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3273 printf(" Lane Error Status register: 0x%08x\n", reg); 3274 3275 /* Get Max Link Width */ 3276 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)){ 3277 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3278 maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3279 } else { 3280 printf("error: falied to get PCIe capablity\n"); 3281 return; 3282 } 3283 for (i = 0; i < maxlinkwidth; i++) { 3284 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3285 if (i % 2 != 0) 3286 reg >>= 16; 3287 else 3288 reg &= 0xffff; 3289 printf(" Equalization Control Register (Link %d): %04x\n", 3290 i, reg); 3291 printf(" Downstream Port Transmit Preset: 0x%x\n", 3292 (pcireg_t)__SHIFTOUT(reg, 3293 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3294 printf(" Downstream Port Receive Hint: 0x%x\n", 3295 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3296 printf(" Upstream Port Transmit Preset: 0x%x\n", 3297 (pcireg_t)__SHIFTOUT(reg, 3298 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3299 printf(" Upstream Port Receive Hint: 0x%x\n", 3300 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3301 } 3302 } 3303 3304 /* XXX pci_conf_print_pmux_cap */ 3305 3306 static void 3307 pci_conf_print_pasid_cap(const pcireg_t *regs, int capoff, int extcapoff) 3308 { 3309 pcireg_t reg, cap, ctl; 3310 unsigned int num; 3311 3312 printf("\n Process Address Space ID\n"); 3313 3314 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3315 cap = reg & 0xffff; 3316 ctl = reg >> 16; 3317 printf(" PASID Capability Register: 0x%04x\n", cap); 3318 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3319 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3320 num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3321 printf(" Max PASID Width: %u\n", num); 3322 3323 printf(" PASID Control Register: 0x%04x\n", ctl); 3324 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3325 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3326 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 3327 } 3328 3329 static void 3330 pci_conf_print_lnr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3331 { 3332 pcireg_t reg, cap, ctl; 3333 unsigned int num; 3334 3335 printf("\n LN Requester\n"); 3336 3337 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 3338 cap = reg & 0xffff; 3339 ctl = reg >> 16; 3340 printf(" LNR Capability register: 0x%04x\n", cap); 3341 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 3342 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 3343 num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 3344 printf(" LNR Registration MAX: %u\n", num); 3345 3346 printf(" LNR Control register: 0x%04x\n", ctl); 3347 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 3348 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 3349 num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 3350 printf(" LNR Registration Limit: %u\n", num); 3351 } 3352 3353 /* XXX pci_conf_print_dpc_cap */ 3354 3355 static int 3356 pci_conf_l1pm_cap_tposcale(unsigned char scale) 3357 { 3358 3359 /* Return scale in us */ 3360 switch (scale) { 3361 case 0x0: 3362 return 2; 3363 case 0x1: 3364 return 10; 3365 case 0x2: 3366 return 100; 3367 default: 3368 return -1; 3369 } 3370 } 3371 3372 static void 3373 pci_conf_print_l1pm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3374 { 3375 pcireg_t reg; 3376 int scale, val; 3377 3378 printf("\n L1 PM Substates\n"); 3379 3380 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 3381 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 3382 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 3383 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 3384 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 3385 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 3386 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 3387 printf(" Port Common Mode Restore Time: %uus\n", 3388 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 3389 scale = pci_conf_l1pm_cap_tposcale( 3390 __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 3391 val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 3392 printf(" Port T_POWER_ON: "); 3393 if (scale == -1) 3394 printf("unknown\n"); 3395 else 3396 printf("%dus\n", val * scale); 3397 3398 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 3399 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 3400 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 3401 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 3402 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 3403 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 3404 printf(" Common Mode Restore Time: %uus\n", 3405 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 3406 scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 3407 val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 3408 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 3409 3410 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 3411 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 3412 scale = pci_conf_l1pm_cap_tposcale( 3413 __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 3414 val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 3415 printf(" T_POWER_ON: "); 3416 if (scale == -1) 3417 printf("unknown\n"); 3418 else 3419 printf("%dus\n", val * scale); 3420 } 3421 3422 static void 3423 pci_conf_print_ptm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3424 { 3425 pcireg_t reg; 3426 uint32_t val; 3427 3428 printf("\n Precision Time Management\n"); 3429 3430 reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; 3431 printf(" PTM Capability register: 0x%08x\n", reg); 3432 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ); 3433 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP); 3434 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT); 3435 printf(" Local Clock Granularity: "); 3436 val = __SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL); 3437 switch (val) { 3438 case 0: 3439 printf("Not implemented\n"); 3440 break; 3441 case 0xffff: 3442 printf("> 254ns\n"); 3443 break; 3444 default: 3445 printf("%uns\n", val); 3446 break; 3447 } 3448 3449 reg = regs[o2i(extcapoff + PCI_PTM_CTL)]; 3450 printf(" PTM Control register: 0x%08x\n", reg); 3451 onoff("PTM Enable", reg, PCI_PTM_CTL_EN); 3452 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL); 3453 printf(" Effective Granularity: "); 3454 val = __SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL); 3455 switch (val) { 3456 case 0: 3457 printf("Unknown\n"); 3458 break; 3459 case 0xffff: 3460 printf("> 254ns\n"); 3461 break; 3462 default: 3463 printf("%uns\n", val); 3464 break; 3465 } 3466 } 3467 3468 /* XXX pci_conf_print_mpcie_cap */ 3469 /* XXX pci_conf_print_frsq_cap */ 3470 /* XXX pci_conf_print_rtr_cap */ 3471 /* XXX pci_conf_print_desigvndsp_cap */ 3472 /* XXX pci_conf_print_vf_resizbar_cap */ 3473 3474 #undef MS 3475 #undef SM 3476 #undef RW 3477 3478 static struct { 3479 pcireg_t cap; 3480 const char *name; 3481 void (*printfunc)(const pcireg_t *, int, int); 3482 } pci_extcaptab[] = { 3483 { 0, "reserved", 3484 NULL }, 3485 { PCI_EXTCAP_AER, "Advanced Error Reporting", 3486 pci_conf_print_aer_cap }, 3487 { PCI_EXTCAP_VC, "Virtual Channel", 3488 pci_conf_print_vc_cap }, 3489 { PCI_EXTCAP_SERNUM, "Device Serial Number", 3490 pci_conf_print_sernum_cap }, 3491 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 3492 pci_conf_print_pwrbdgt_cap }, 3493 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 3494 pci_conf_print_rclink_dcl_cap }, 3495 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 3496 NULL }, 3497 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 3498 pci_conf_print_rcec_assoc_cap }, 3499 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 3500 NULL }, 3501 { PCI_EXTCAP_VC2, "Virtual Channel", 3502 NULL }, 3503 { PCI_EXTCAP_RCRB, "RCRB Header", 3504 NULL }, 3505 { PCI_EXTCAP_VENDOR, "Vendor Unique", 3506 NULL }, 3507 { PCI_EXTCAP_CAC, "Configuration Access Correction", 3508 NULL }, 3509 { PCI_EXTCAP_ACS, "Access Control Services", 3510 pci_conf_print_acs_cap }, 3511 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 3512 pci_conf_print_ari_cap }, 3513 { PCI_EXTCAP_ATS, "Address Translation Services", 3514 pci_conf_print_ats_cap }, 3515 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 3516 pci_conf_print_sriov_cap }, 3517 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 3518 NULL }, 3519 { PCI_EXTCAP_MCAST, "Multicast", 3520 pci_conf_print_multicast_cap }, 3521 { PCI_EXTCAP_PAGE_REQ, "Page Request", 3522 pci_conf_print_page_req_cap }, 3523 { PCI_EXTCAP_AMD, "Reserved for AMD", 3524 NULL }, 3525 { PCI_EXTCAP_RESIZBAR, "Resizable BAR", 3526 pci_conf_print_resizbar_cap }, 3527 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 3528 pci_conf_print_dpa_cap }, 3529 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 3530 pci_conf_print_tph_req_cap }, 3531 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 3532 pci_conf_print_ltr_cap }, 3533 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 3534 pci_conf_print_sec_pcie_cap }, 3535 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 3536 NULL }, 3537 { PCI_EXTCAP_PASID, "Process Address Space ID", 3538 pci_conf_print_pasid_cap }, 3539 { PCI_EXTCAP_LN_REQ, "LN Requester", 3540 pci_conf_print_lnr_cap }, 3541 { PCI_EXTCAP_DPC, "Downstream Port Containment", 3542 NULL }, 3543 { PCI_EXTCAP_L1PM, "L1 PM Substates", 3544 pci_conf_print_l1pm_cap }, 3545 { PCI_EXTCAP_PTM, "Precision Time Management", 3546 pci_conf_print_ptm_cap }, 3547 { PCI_EXTCAP_MPCIE, "M-PCIe", 3548 NULL }, 3549 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 3550 NULL }, 3551 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 3552 NULL }, 3553 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 3554 NULL }, 3555 { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs", 3556 NULL }, 3557 }; 3558 3559 static int 3560 pci_conf_find_extcap(const pcireg_t *regs, int capoff, unsigned int capid, 3561 int *offsetp) 3562 { 3563 int off; 3564 pcireg_t rval; 3565 3566 for (off = PCI_EXTCAPLIST_BASE; 3567 off != 0; 3568 off = PCI_EXTCAPLIST_NEXT(rval)) { 3569 rval = regs[o2i(off)]; 3570 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 3571 if (offsetp != NULL) 3572 *offsetp = off; 3573 return 1; 3574 } 3575 } 3576 return 0; 3577 } 3578 3579 static void 3580 pci_conf_print_extcaplist( 3581 #ifdef _KERNEL 3582 pci_chipset_tag_t pc, pcitag_t tag, 3583 #endif 3584 const pcireg_t *regs, int capoff) 3585 { 3586 int off; 3587 pcireg_t foundcap; 3588 pcireg_t rval; 3589 bool foundtable[__arraycount(pci_extcaptab)]; 3590 unsigned int i; 3591 3592 /* Check Extended capability structure */ 3593 off = PCI_EXTCAPLIST_BASE; 3594 rval = regs[o2i(off)]; 3595 if (rval == 0xffffffff || rval == 0) 3596 return; 3597 3598 /* Clear table */ 3599 for (i = 0; i < __arraycount(pci_extcaptab); i++) 3600 foundtable[i] = false; 3601 3602 /* Print extended capability register's offset and the type first */ 3603 for (;;) { 3604 printf(" Extended Capability Register at 0x%02x\n", off); 3605 3606 foundcap = PCI_EXTCAPLIST_CAP(rval); 3607 printf(" type: 0x%04x (", foundcap); 3608 if (foundcap < __arraycount(pci_extcaptab)) { 3609 printf("%s)\n", pci_extcaptab[foundcap].name); 3610 /* Mark as found */ 3611 foundtable[foundcap] = true; 3612 } else 3613 printf("unknown)\n"); 3614 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 3615 3616 off = PCI_EXTCAPLIST_NEXT(rval); 3617 if (off == 0) 3618 break; 3619 else if (off <= PCI_CONF_SIZE) { 3620 printf(" next pointer: 0x%03x (incorrect)\n", off); 3621 return; 3622 } 3623 rval = regs[o2i(off)]; 3624 } 3625 3626 /* 3627 * And then, print the detail of each capability registers 3628 * in capability value's order. 3629 */ 3630 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 3631 if (foundtable[i] == false) 3632 continue; 3633 3634 /* 3635 * The type was found. Search capability list again and 3636 * print all capabilities that the capabiliy type is 3637 * the same. 3638 */ 3639 if (pci_conf_find_extcap(regs, capoff, i, &off) == 0) 3640 continue; 3641 rval = regs[o2i(off)]; 3642 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 3643 || (pci_extcaptab[i].printfunc == NULL)) 3644 continue; 3645 3646 pci_extcaptab[i].printfunc(regs, capoff, off); 3647 3648 } 3649 } 3650 3651 /* Print the Secondary Status Register. */ 3652 static void 3653 pci_conf_print_ssr(pcireg_t rval) 3654 { 3655 pcireg_t devsel; 3656 3657 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 3658 onoff("66 MHz capable", rval, __BIT(5)); 3659 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 3660 onoff("Fast back-to-back capable", rval, __BIT(7)); 3661 onoff("Data parity error detected", rval, __BIT(8)); 3662 3663 printf(" DEVSEL timing: "); 3664 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 3665 switch (devsel) { 3666 case 0: 3667 printf("fast"); 3668 break; 3669 case 1: 3670 printf("medium"); 3671 break; 3672 case 2: 3673 printf("slow"); 3674 break; 3675 default: 3676 printf("unknown/reserved"); /* XXX */ 3677 break; 3678 } 3679 printf(" (0x%x)\n", devsel); 3680 3681 onoff("Signalled target abort", rval, __BIT(11)); 3682 onoff("Received target abort", rval, __BIT(12)); 3683 onoff("Received master abort", rval, __BIT(13)); 3684 onoff("Received system error", rval, __BIT(14)); 3685 onoff("Detected parity error", rval, __BIT(15)); 3686 } 3687 3688 static void 3689 pci_conf_print_type0( 3690 #ifdef _KERNEL 3691 pci_chipset_tag_t pc, pcitag_t tag, 3692 #endif 3693 const pcireg_t *regs 3694 #ifdef _KERNEL 3695 , int sizebars 3696 #endif 3697 ) 3698 { 3699 int off, width; 3700 pcireg_t rval; 3701 3702 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 3703 #ifdef _KERNEL 3704 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3705 #else 3706 width = pci_conf_print_bar(regs, off, NULL); 3707 #endif 3708 } 3709 3710 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 3711 3712 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 3713 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 3714 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 3715 3716 /* XXX */ 3717 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 3718 3719 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3720 printf(" Capability list pointer: 0x%02x\n", 3721 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 3722 else 3723 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 3724 3725 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 3726 3727 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3728 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 3729 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 3730 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 3731 switch (PCI_INTERRUPT_PIN(rval)) { 3732 case PCI_INTERRUPT_PIN_NONE: 3733 printf("(none)"); 3734 break; 3735 case PCI_INTERRUPT_PIN_A: 3736 printf("(pin A)"); 3737 break; 3738 case PCI_INTERRUPT_PIN_B: 3739 printf("(pin B)"); 3740 break; 3741 case PCI_INTERRUPT_PIN_C: 3742 printf("(pin C)"); 3743 break; 3744 case PCI_INTERRUPT_PIN_D: 3745 printf("(pin D)"); 3746 break; 3747 default: 3748 printf("(? ? ?)"); 3749 break; 3750 } 3751 printf("\n"); 3752 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 3753 } 3754 3755 static void 3756 pci_conf_print_type1( 3757 #ifdef _KERNEL 3758 pci_chipset_tag_t pc, pcitag_t tag, 3759 #endif 3760 const pcireg_t *regs 3761 #ifdef _KERNEL 3762 , int sizebars 3763 #endif 3764 ) 3765 { 3766 int off, width; 3767 pcireg_t rval; 3768 uint32_t base, limit; 3769 uint32_t base_h, limit_h; 3770 uint64_t pbase, plimit; 3771 int use_upper; 3772 3773 /* 3774 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 3775 * Bridge chip documentation, and may not be correct with 3776 * respect to various standards. (XXX) 3777 */ 3778 3779 for (off = 0x10; off < 0x18; off += width) { 3780 #ifdef _KERNEL 3781 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3782 #else 3783 width = pci_conf_print_bar(regs, off, NULL); 3784 #endif 3785 } 3786 3787 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 3788 printf(" Primary bus number: 0x%02x\n", 3789 PCI_BRIDGE_BUS_PRIMARY(rval)); 3790 printf(" Secondary bus number: 0x%02x\n", 3791 PCI_BRIDGE_BUS_SECONDARY(rval)); 3792 printf(" Subordinate bus number: 0x%02x\n", 3793 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 3794 printf(" Secondary bus latency timer: 0x%02x\n", 3795 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 3796 3797 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 3798 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 3799 3800 /* I/O region */ 3801 printf(" I/O region:\n"); 3802 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 3803 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 3804 if (PCI_BRIDGE_IO_32BITS(rval)) 3805 use_upper = 1; 3806 else 3807 use_upper = 0; 3808 onoff("32bit I/O", rval, use_upper); 3809 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 3810 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 3811 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 3812 limit |= 0x00000fff; 3813 3814 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 3815 base_h = (rval >> 0) & 0xffff; 3816 limit_h = (rval >> 16) & 0xffff; 3817 printf(" base upper 16 bits register: 0x%04x\n", base_h); 3818 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 3819 3820 if (use_upper == 1) { 3821 base |= base_h << 16; 3822 limit |= limit_h << 16; 3823 } 3824 if (base < limit) { 3825 if (use_upper == 1) 3826 printf(" range: 0x%08x-0x%08x\n", base, limit); 3827 else 3828 printf(" range: 0x%04x-0x%04x\n", base, limit); 3829 } else 3830 printf(" range: not set\n"); 3831 3832 /* Non-prefetchable memory region */ 3833 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 3834 printf(" Memory region:\n"); 3835 printf(" base register: 0x%04x\n", 3836 (rval >> 0) & 0xffff); 3837 printf(" limit register: 0x%04x\n", 3838 (rval >> 16) & 0xffff); 3839 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 3840 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 3841 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 3842 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 3843 if (base < limit) 3844 printf(" range: 0x%08x-0x%08x\n", base, limit); 3845 else 3846 printf(" range: not set\n"); 3847 3848 /* Prefetchable memory region */ 3849 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 3850 printf(" Prefetchable memory region:\n"); 3851 printf(" base register: 0x%04x\n", 3852 (rval >> 0) & 0xffff); 3853 printf(" limit register: 0x%04x\n", 3854 (rval >> 16) & 0xffff); 3855 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 3856 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 3857 printf(" base upper 32 bits register: 0x%08x\n", 3858 base_h); 3859 printf(" limit upper 32 bits register: 0x%08x\n", 3860 limit_h); 3861 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 3862 use_upper = 1; 3863 else 3864 use_upper = 0; 3865 onoff("64bit memory address", rval, use_upper); 3866 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 3867 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 3868 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 3869 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 3870 if (use_upper == 1) { 3871 pbase |= (uint64_t)base_h << 32; 3872 plimit |= (uint64_t)limit_h << 32; 3873 } 3874 if (pbase < plimit) { 3875 if (use_upper == 1) 3876 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 3877 "\n", pbase, plimit); 3878 else 3879 printf(" range: 0x%08x-0x%08x\n", 3880 (uint32_t)pbase, (uint32_t)plimit); 3881 } else 3882 printf(" range: not set\n"); 3883 3884 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3885 printf(" Capability list pointer: 0x%02x\n", 3886 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 3887 else 3888 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 3889 3890 /* XXX */ 3891 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 3892 3893 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3894 printf(" Interrupt line: 0x%02x\n", 3895 (rval >> 0) & 0xff); 3896 printf(" Interrupt pin: 0x%02x ", 3897 (rval >> 8) & 0xff); 3898 switch ((rval >> 8) & 0xff) { 3899 case PCI_INTERRUPT_PIN_NONE: 3900 printf("(none)"); 3901 break; 3902 case PCI_INTERRUPT_PIN_A: 3903 printf("(pin A)"); 3904 break; 3905 case PCI_INTERRUPT_PIN_B: 3906 printf("(pin B)"); 3907 break; 3908 case PCI_INTERRUPT_PIN_C: 3909 printf("(pin C)"); 3910 break; 3911 case PCI_INTERRUPT_PIN_D: 3912 printf("(pin D)"); 3913 break; 3914 default: 3915 printf("(? ? ?)"); 3916 break; 3917 } 3918 printf("\n"); 3919 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 3920 & PCI_BRIDGE_CONTROL_MASK; 3921 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 3922 onoff("Parity error response", rval, 0x0001); 3923 onoff("Secondary SERR forwarding", rval, 0x0002); 3924 onoff("ISA enable", rval, 0x0004); 3925 onoff("VGA enable", rval, 0x0008); 3926 onoff("Master abort reporting", rval, 0x0020); 3927 onoff("Secondary bus reset", rval, 0x0040); 3928 onoff("Fast back-to-back capable", rval, 0x0080); 3929 } 3930 3931 static void 3932 pci_conf_print_type2( 3933 #ifdef _KERNEL 3934 pci_chipset_tag_t pc, pcitag_t tag, 3935 #endif 3936 const pcireg_t *regs 3937 #ifdef _KERNEL 3938 , int sizebars 3939 #endif 3940 ) 3941 { 3942 pcireg_t rval; 3943 3944 /* 3945 * XXX these need to be printed in more detail, need to be 3946 * XXX checked against specs/docs, etc. 3947 * 3948 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 3949 * controller chip documentation, and may not be correct with 3950 * respect to various standards. (XXX) 3951 */ 3952 3953 #ifdef _KERNEL 3954 pci_conf_print_bar(pc, tag, regs, 0x10, 3955 "CardBus socket/ExCA registers", sizebars); 3956 #else 3957 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 3958 #endif 3959 3960 /* Capability list pointer and secondary status register */ 3961 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 3962 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3963 printf(" Capability list pointer: 0x%02x\n", 3964 PCI_CAPLIST_PTR(rval)); 3965 else 3966 printf(" Reserved @ 0x14: 0x%04x\n", 3967 (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0))); 3968 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 3969 3970 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 3971 printf(" PCI bus number: 0x%02x\n", 3972 (rval >> 0) & 0xff); 3973 printf(" CardBus bus number: 0x%02x\n", 3974 (rval >> 8) & 0xff); 3975 printf(" Subordinate bus number: 0x%02x\n", 3976 (rval >> 16) & 0xff); 3977 printf(" CardBus latency timer: 0x%02x\n", 3978 (rval >> 24) & 0xff); 3979 3980 /* XXX Print more prettily */ 3981 printf(" CardBus memory region 0:\n"); 3982 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 3983 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 3984 printf(" CardBus memory region 1:\n"); 3985 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 3986 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 3987 printf(" CardBus I/O region 0:\n"); 3988 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 3989 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 3990 printf(" CardBus I/O region 1:\n"); 3991 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 3992 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 3993 3994 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3995 printf(" Interrupt line: 0x%02x\n", 3996 (rval >> 0) & 0xff); 3997 printf(" Interrupt pin: 0x%02x ", 3998 (rval >> 8) & 0xff); 3999 switch ((rval >> 8) & 0xff) { 4000 case PCI_INTERRUPT_PIN_NONE: 4001 printf("(none)"); 4002 break; 4003 case PCI_INTERRUPT_PIN_A: 4004 printf("(pin A)"); 4005 break; 4006 case PCI_INTERRUPT_PIN_B: 4007 printf("(pin B)"); 4008 break; 4009 case PCI_INTERRUPT_PIN_C: 4010 printf("(pin C)"); 4011 break; 4012 case PCI_INTERRUPT_PIN_D: 4013 printf("(pin D)"); 4014 break; 4015 default: 4016 printf("(? ? ?)"); 4017 break; 4018 } 4019 printf("\n"); 4020 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 4021 printf(" Bridge control register: 0x%04x\n", rval); 4022 onoff("Parity error response", rval, __BIT(0)); 4023 onoff("SERR# enable", rval, __BIT(1)); 4024 onoff("ISA enable", rval, __BIT(2)); 4025 onoff("VGA enable", rval, __BIT(3)); 4026 onoff("Master abort mode", rval, __BIT(5)); 4027 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 4028 onoff("Functional interrupts routed by ExCA registers", rval, 4029 __BIT(7)); 4030 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 4031 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 4032 onoff("Write posting enable", rval, __BIT(10)); 4033 4034 rval = regs[o2i(0x40)]; 4035 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4036 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4037 4038 #ifdef _KERNEL 4039 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 4040 sizebars); 4041 #else 4042 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 4043 #endif 4044 } 4045 4046 void 4047 pci_conf_print( 4048 #ifdef _KERNEL 4049 pci_chipset_tag_t pc, pcitag_t tag, 4050 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 4051 #else 4052 int pcifd, u_int bus, u_int dev, u_int func 4053 #endif 4054 ) 4055 { 4056 pcireg_t regs[o2i(PCI_EXTCONF_SIZE)]; 4057 int off, capoff, endoff, hdrtype; 4058 const char *type_name; 4059 #ifdef _KERNEL 4060 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, 4061 int); 4062 int sizebars; 4063 #else 4064 void (*type_printfn)(const pcireg_t *); 4065 #endif 4066 4067 printf("PCI configuration registers:\n"); 4068 4069 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 4070 #ifdef _KERNEL 4071 regs[o2i(off)] = pci_conf_read(pc, tag, off); 4072 #else 4073 if (pcibus_conf_read(pcifd, bus, dev, func, off, 4074 ®s[o2i(off)]) == -1) 4075 regs[o2i(off)] = 0; 4076 #endif 4077 } 4078 4079 #ifdef _KERNEL 4080 sizebars = 1; 4081 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 4082 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 4083 sizebars = 0; 4084 #endif 4085 4086 /* common header */ 4087 printf(" Common header:\n"); 4088 pci_conf_print_regs(regs, 0, 16); 4089 4090 printf("\n"); 4091 #ifdef _KERNEL 4092 pci_conf_print_common(pc, tag, regs); 4093 #else 4094 pci_conf_print_common(regs); 4095 #endif 4096 printf("\n"); 4097 4098 /* type-dependent header */ 4099 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 4100 switch (hdrtype) { /* XXX make a table, eventually */ 4101 case 0: 4102 /* Standard device header */ 4103 type_name = "\"normal\" device"; 4104 type_printfn = &pci_conf_print_type0; 4105 capoff = PCI_CAPLISTPTR_REG; 4106 endoff = 64; 4107 break; 4108 case 1: 4109 /* PCI-PCI bridge header */ 4110 type_name = "PCI-PCI bridge"; 4111 type_printfn = &pci_conf_print_type1; 4112 capoff = PCI_CAPLISTPTR_REG; 4113 endoff = 64; 4114 break; 4115 case 2: 4116 /* PCI-CardBus bridge header */ 4117 type_name = "PCI-CardBus bridge"; 4118 type_printfn = &pci_conf_print_type2; 4119 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 4120 endoff = 72; 4121 break; 4122 default: 4123 type_name = NULL; 4124 type_printfn = 0; 4125 capoff = -1; 4126 endoff = 64; 4127 break; 4128 } 4129 printf(" Type %d ", hdrtype); 4130 if (type_name != NULL) 4131 printf("(%s) ", type_name); 4132 printf("header:\n"); 4133 pci_conf_print_regs(regs, 16, endoff); 4134 printf("\n"); 4135 if (type_printfn) { 4136 #ifdef _KERNEL 4137 (*type_printfn)(pc, tag, regs, sizebars); 4138 #else 4139 (*type_printfn)(regs); 4140 #endif 4141 } else 4142 printf(" Don't know how to pretty-print type %d header.\n", 4143 hdrtype); 4144 printf("\n"); 4145 4146 /* capability list, if present */ 4147 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4148 && (capoff > 0)) { 4149 #ifdef _KERNEL 4150 pci_conf_print_caplist(pc, tag, regs, capoff); 4151 #else 4152 pci_conf_print_caplist(regs, capoff); 4153 #endif 4154 printf("\n"); 4155 } 4156 4157 /* device-dependent header */ 4158 printf(" Device-dependent header:\n"); 4159 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 4160 printf("\n"); 4161 #ifdef _KERNEL 4162 if (printfn) 4163 (*printfn)(pc, tag, regs); 4164 else 4165 printf(" Don't know how to pretty-print device-dependent header.\n"); 4166 printf("\n"); 4167 #endif /* _KERNEL */ 4168 4169 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 4170 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 4171 return; 4172 4173 #ifdef _KERNEL 4174 pci_conf_print_extcaplist(pc, tag, regs, capoff); 4175 #else 4176 pci_conf_print_extcaplist(regs, capoff); 4177 #endif 4178 printf("\n"); 4179 4180 /* Extended Configuration Space, if present */ 4181 printf(" Extended Configuration Space:\n"); 4182 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 4183 } 4184
Indexes created Wed Sep 24 05:09:52 GMT 2025