pci_subr.c revision 1.158
1 /* $NetBSD: pci_subr.c,v 1.158 2017/02/24 05:04:46 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.158 2017/02/24 05:04:46 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdarg.h> 58 #include <stdbool.h> 59 #include <stdio.h> 60 #include <stdlib.h> 61 #include <string.h> 62 #endif 63 64 #include <dev/pci/pcireg.h> 65 #ifdef _KERNEL 66 #include <dev/pci/pcivar.h> 67 #else 68 #include <dev/pci/pci_verbose.h> 69 #include <dev/pci/pcidevs.h> 70 #include <dev/pci/pcidevs_data.h> 71 #endif 72 73 /* 74 * Descriptions of known PCI classes and subclasses. 75 * 76 * Subclasses are described in the same way as classes, but have a 77 * NULL subclass pointer. 78 */ 79 struct pci_class { 80 const char *name; 81 u_int val; /* as wide as pci_{,sub}class_t */ 82 const struct pci_class *subclasses; 83 }; 84 85 /* 86 * Class 0x00. 87 * Before rev. 2.0. 88 */ 89 static const struct pci_class pci_subclass_prehistoric[] = { 90 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 91 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 92 { NULL, 0, NULL, }, 93 }; 94 95 /* 96 * Class 0x01. 97 * Mass storage controller 98 */ 99 100 /* ATA programming interface */ 101 static const struct pci_class pci_interface_ata[] = { 102 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 103 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 104 { NULL, 0, NULL, }, 105 }; 106 107 /* SATA programming interface */ 108 static const struct pci_class pci_interface_sata[] = { 109 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 110 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 111 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 112 { NULL, 0, NULL, }, 113 }; 114 115 /* Flash programming interface */ 116 static const struct pci_class pci_interface_nvm[] = { 117 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 118 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 119 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 120 { NULL, 0, NULL, }, 121 }; 122 123 /* Subclasses */ 124 static const struct pci_class pci_subclass_mass_storage[] = { 125 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 126 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 127 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 128 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 129 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 130 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 131 pci_interface_ata, }, 132 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 133 pci_interface_sata, }, 134 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 135 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 136 pci_interface_nvm, }, 137 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 138 { NULL, 0, NULL, }, 139 }; 140 141 /* 142 * Class 0x02. 143 * Network controller. 144 */ 145 static const struct pci_class pci_subclass_network[] = { 146 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 147 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 148 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 149 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 150 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 151 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 152 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 153 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 154 { NULL, 0, NULL, }, 155 }; 156 157 /* 158 * Class 0x03. 159 * Display controller. 160 */ 161 162 /* VGA programming interface */ 163 static const struct pci_class pci_interface_vga[] = { 164 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 165 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 166 { NULL, 0, NULL, }, 167 }; 168 /* Subclasses */ 169 static const struct pci_class pci_subclass_display[] = { 170 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 171 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 172 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 173 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 174 { NULL, 0, NULL, }, 175 }; 176 177 /* 178 * Class 0x04. 179 * Multimedia device. 180 */ 181 static const struct pci_class pci_subclass_multimedia[] = { 182 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 183 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 184 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 185 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 186 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 187 { NULL, 0, NULL, }, 188 }; 189 190 /* 191 * Class 0x05. 192 * Memory controller. 193 */ 194 static const struct pci_class pci_subclass_memory[] = { 195 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 196 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 197 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 198 { NULL, 0, NULL, }, 199 }; 200 201 /* 202 * Class 0x06. 203 * Bridge device. 204 */ 205 206 /* PCI bridge programming interface */ 207 static const struct pci_class pci_interface_pcibridge[] = { 208 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 209 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 210 { NULL, 0, NULL, }, 211 }; 212 213 /* Semi-transparent PCI-to-PCI bridge programming interface */ 214 static const struct pci_class pci_interface_stpci[] = { 215 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 216 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 217 { NULL, 0, NULL, }, 218 }; 219 220 /* Advanced Switching programming interface */ 221 static const struct pci_class pci_interface_advsw[] = { 222 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 223 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 224 { NULL, 0, NULL, }, 225 }; 226 227 /* Subclasses */ 228 static const struct pci_class pci_subclass_bridge[] = { 229 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 230 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 231 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 232 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 233 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 234 pci_interface_pcibridge, }, 235 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 236 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 237 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 238 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 239 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 240 pci_interface_stpci, }, 241 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 242 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 243 pci_interface_advsw, }, 244 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 245 { NULL, 0, NULL, }, 246 }; 247 248 /* 249 * Class 0x07. 250 * Simple communications controller. 251 */ 252 253 /* Serial controller programming interface */ 254 static const struct pci_class pci_interface_serial[] = { 255 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 256 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 257 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 258 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 259 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 260 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 261 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 262 { NULL, 0, NULL, }, 263 }; 264 265 /* Parallel controller programming interface */ 266 static const struct pci_class pci_interface_parallel[] = { 267 { "", PCI_INTERFACE_PARALLEL, NULL,}, 268 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 269 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 270 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 271 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 272 { NULL, 0, NULL,}, 273 }; 274 275 /* Modem programming interface */ 276 static const struct pci_class pci_interface_modem[] = { 277 { "", PCI_INTERFACE_MODEM, NULL,}, 278 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 279 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 280 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 281 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 282 { NULL, 0, NULL,}, 283 }; 284 285 /* Subclasses */ 286 static const struct pci_class pci_subclass_communications[] = { 287 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 288 pci_interface_serial, }, 289 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 290 pci_interface_parallel, }, 291 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 292 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 293 pci_interface_modem, }, 294 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 295 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 296 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 297 { NULL, 0, NULL,}, 298 }; 299 300 /* 301 * Class 0x08. 302 * Base system peripheral. 303 */ 304 305 /* PIC programming interface */ 306 static const struct pci_class pci_interface_pic[] = { 307 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 308 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 309 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 310 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 311 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 312 { NULL, 0, NULL, }, 313 }; 314 315 /* DMA programming interface */ 316 static const struct pci_class pci_interface_dma[] = { 317 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 318 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 319 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 320 { NULL, 0, NULL, }, 321 }; 322 323 /* Timer programming interface */ 324 static const struct pci_class pci_interface_tmr[] = { 325 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 326 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 327 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 328 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 329 { NULL, 0, NULL, }, 330 }; 331 332 /* RTC programming interface */ 333 static const struct pci_class pci_interface_rtc[] = { 334 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 335 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 336 { NULL, 0, NULL, }, 337 }; 338 339 /* Subclasses */ 340 static const struct pci_class pci_subclass_system[] = { 341 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 342 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 343 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 344 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 345 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 346 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 347 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 348 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 349 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 350 { NULL, 0, NULL, }, 351 }; 352 353 /* 354 * Class 0x09. 355 * Input device. 356 */ 357 358 /* Gameport programming interface */ 359 static const struct pci_class pci_interface_game[] = { 360 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 361 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 362 { NULL, 0, NULL, }, 363 }; 364 365 /* Subclasses */ 366 static const struct pci_class pci_subclass_input[] = { 367 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 368 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 369 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 370 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 371 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 372 pci_interface_game, }, 373 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 374 { NULL, 0, NULL, }, 375 }; 376 377 /* 378 * Class 0x0a. 379 * Docking station. 380 */ 381 static const struct pci_class pci_subclass_dock[] = { 382 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 383 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 384 { NULL, 0, NULL, }, 385 }; 386 387 /* 388 * Class 0x0b. 389 * Processor. 390 */ 391 static const struct pci_class pci_subclass_processor[] = { 392 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 393 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 394 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 395 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 396 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 397 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 398 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 399 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 400 { NULL, 0, NULL, }, 401 }; 402 403 /* 404 * Class 0x0c. 405 * Serial bus controller. 406 */ 407 408 /* IEEE1394 programming interface */ 409 static const struct pci_class pci_interface_ieee1394[] = { 410 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 411 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 412 { NULL, 0, NULL,}, 413 }; 414 415 /* USB programming interface */ 416 static const struct pci_class pci_interface_usb[] = { 417 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 418 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 419 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 420 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 421 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 422 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 423 { NULL, 0, NULL, }, 424 }; 425 426 /* IPMI programming interface */ 427 static const struct pci_class pci_interface_ipmi[] = { 428 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 429 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 430 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 431 { NULL, 0, NULL,}, 432 }; 433 434 /* Subclasses */ 435 static const struct pci_class pci_subclass_serialbus[] = { 436 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 437 pci_interface_ieee1394, }, 438 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 439 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 440 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 441 pci_interface_usb, }, 442 /* XXX Fiber Channel/_FIBRECHANNEL */ 443 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 444 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 445 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 446 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 447 pci_interface_ipmi, }, 448 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 449 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 450 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 451 { NULL, 0, NULL, }, 452 }; 453 454 /* 455 * Class 0x0d. 456 * Wireless Controller. 457 */ 458 static const struct pci_class pci_subclass_wireless[] = { 459 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 460 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 461 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 462 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 463 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 464 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 465 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 466 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 467 { NULL, 0, NULL, }, 468 }; 469 470 /* 471 * Class 0x0e. 472 * Intelligent IO controller. 473 */ 474 475 /* Intelligent IO programming interface */ 476 static const struct pci_class pci_interface_i2o[] = { 477 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 478 { NULL, 0, NULL,}, 479 }; 480 481 /* Subclasses */ 482 static const struct pci_class pci_subclass_i2o[] = { 483 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 484 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 485 { NULL, 0, NULL, }, 486 }; 487 488 /* 489 * Class 0x0f. 490 * Satellite communication controller. 491 */ 492 static const struct pci_class pci_subclass_satcom[] = { 493 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 494 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 495 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 496 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 497 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 498 { NULL, 0, NULL, }, 499 }; 500 501 /* 502 * Class 0x10. 503 * Encryption/Decryption controller. 504 */ 505 static const struct pci_class pci_subclass_crypto[] = { 506 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 507 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 508 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 509 { NULL, 0, NULL, }, 510 }; 511 512 /* 513 * Class 0x11. 514 * Data aquuisition and signal processing controller. 515 */ 516 static const struct pci_class pci_subclass_dasp[] = { 517 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 518 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 519 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 520 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 521 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 522 { NULL, 0, NULL, }, 523 }; 524 525 /* List of classes */ 526 static const struct pci_class pci_class[] = { 527 { "prehistoric", PCI_CLASS_PREHISTORIC, 528 pci_subclass_prehistoric, }, 529 { "mass storage", PCI_CLASS_MASS_STORAGE, 530 pci_subclass_mass_storage, }, 531 { "network", PCI_CLASS_NETWORK, 532 pci_subclass_network, }, 533 { "display", PCI_CLASS_DISPLAY, 534 pci_subclass_display, }, 535 { "multimedia", PCI_CLASS_MULTIMEDIA, 536 pci_subclass_multimedia, }, 537 { "memory", PCI_CLASS_MEMORY, 538 pci_subclass_memory, }, 539 { "bridge", PCI_CLASS_BRIDGE, 540 pci_subclass_bridge, }, 541 { "communications", PCI_CLASS_COMMUNICATIONS, 542 pci_subclass_communications, }, 543 { "system", PCI_CLASS_SYSTEM, 544 pci_subclass_system, }, 545 { "input", PCI_CLASS_INPUT, 546 pci_subclass_input, }, 547 { "dock", PCI_CLASS_DOCK, 548 pci_subclass_dock, }, 549 { "processor", PCI_CLASS_PROCESSOR, 550 pci_subclass_processor, }, 551 { "serial bus", PCI_CLASS_SERIALBUS, 552 pci_subclass_serialbus, }, 553 { "wireless", PCI_CLASS_WIRELESS, 554 pci_subclass_wireless, }, 555 { "I2O", PCI_CLASS_I2O, 556 pci_subclass_i2o, }, 557 { "satellite comm", PCI_CLASS_SATCOM, 558 pci_subclass_satcom, }, 559 { "crypto", PCI_CLASS_CRYPTO, 560 pci_subclass_crypto, }, 561 { "DASP", PCI_CLASS_DASP, 562 pci_subclass_dasp, }, 563 { "undefined", PCI_CLASS_UNDEFINED, 564 NULL, }, 565 { NULL, 0, 566 NULL, }, 567 }; 568 569 DEV_VERBOSE_DEFINE(pci); 570 571 /* 572 * Append a formatted string to dest without writing more than len 573 * characters (including the trailing NUL character). dest and len 574 * are updated for use in subsequent calls to snappendf(). 575 * 576 * Returns 0 on success, a negative value if vnsprintf() fails, or 577 * a positive value if the dest buffer would have overflowed. 578 */ 579 580 static int __printflike(3,4) 581 snappendf(char **dest, size_t *len, const char * restrict fmt, ...) 582 { 583 va_list ap; 584 int count; 585 586 va_start(ap, fmt); 587 count = vsnprintf(*dest, *len, fmt, ap); 588 va_end(ap); 589 590 /* Let vsnprintf() errors bubble up to caller */ 591 if (count < 0 || *len == 0) 592 return count; 593 594 /* Handle overflow */ 595 if ((size_t)count >= *len) { 596 *dest += *len - 1; 597 *len = 1; 598 return 1; 599 } 600 601 /* Update dest & len to point at trailing NUL */ 602 *dest += count; 603 *len -= count; 604 605 return 0; 606 } 607 608 void 609 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 610 size_t l) 611 { 612 pci_class_t pciclass; 613 pci_subclass_t subclass; 614 pci_interface_t interface; 615 pci_revision_t revision; 616 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 617 const struct pci_class *classp, *subclassp, *interfacep; 618 619 pciclass = PCI_CLASS(class_reg); 620 subclass = PCI_SUBCLASS(class_reg); 621 interface = PCI_INTERFACE(class_reg); 622 revision = PCI_REVISION(class_reg); 623 624 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 625 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 626 PCI_PRODUCT(id_reg)); 627 628 classp = pci_class; 629 while (classp->name != NULL) { 630 if (pciclass == classp->val) 631 break; 632 classp++; 633 } 634 635 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 636 while (subclassp && subclassp->name != NULL) { 637 if (subclass == subclassp->val) 638 break; 639 subclassp++; 640 } 641 642 interfacep = (subclassp && subclassp->name != NULL) ? 643 subclassp->subclasses : NULL; 644 while (interfacep && interfacep->name != NULL) { 645 if (interface == interfacep->val) 646 break; 647 interfacep++; 648 } 649 650 (void)snappendf(&cp, &l, "%s %s", vendor, product); 651 if (showclass) { 652 (void)snappendf(&cp, &l, " ("); 653 if (classp->name == NULL) 654 (void)snappendf(&cp, &l, 655 "class 0x%02x, subclass 0x%02x", 656 pciclass, subclass); 657 else { 658 if (subclassp == NULL || subclassp->name == NULL) 659 (void)snappendf(&cp, &l, 660 "%s, subclass 0x%02x", 661 classp->name, subclass); 662 else 663 (void)snappendf(&cp, &l, "%s %s", 664 subclassp->name, classp->name); 665 } 666 if ((interfacep == NULL) || (interfacep->name == NULL)) { 667 if (interface != 0) 668 (void)snappendf(&cp, &l, ", interface 0x%02x", 669 interface); 670 } else if (strncmp(interfacep->name, "", 1) != 0) 671 (void)snappendf(&cp, &l, ", %s", interfacep->name); 672 if (revision != 0) 673 (void)snappendf(&cp, &l, ", revision 0x%02x", revision); 674 (void)snappendf(&cp, &l, ")"); 675 } 676 } 677 678 #ifdef _KERNEL 679 void 680 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 681 const char *known, int addrev) 682 { 683 char devinfo[256]; 684 685 if (known) { 686 aprint_normal(": %s", known); 687 if (addrev) 688 aprint_normal(" (rev. 0x%02x)", 689 PCI_REVISION(pa->pa_class)); 690 aprint_normal("\n"); 691 } else { 692 pci_devinfo(pa->pa_id, pa->pa_class, 0, 693 devinfo, sizeof(devinfo)); 694 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 695 PCI_REVISION(pa->pa_class)); 696 } 697 if (naive) 698 aprint_naive(": %s\n", naive); 699 else 700 aprint_naive("\n"); 701 } 702 #endif 703 704 /* 705 * Print out most of the PCI configuration registers. Typically used 706 * in a device attach routine like this: 707 * 708 * #ifdef MYDEV_DEBUG 709 * printf("%s: ", device_xname(sc->sc_dev)); 710 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 711 * #endif 712 */ 713 714 #define i2o(i) ((i) * 4) 715 #define o2i(o) ((o) / 4) 716 #define onoff2(str, rval, bit, onstr, offstr) \ 717 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 718 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 719 720 static void 721 pci_conf_print_common( 722 #ifdef _KERNEL 723 pci_chipset_tag_t pc, pcitag_t tag, 724 #endif 725 const pcireg_t *regs) 726 { 727 const char *name; 728 const struct pci_class *classp, *subclassp; 729 char vendor[PCI_VENDORSTR_LEN]; 730 char product[PCI_PRODUCTSTR_LEN]; 731 pcireg_t rval; 732 unsigned int num; 733 734 rval = regs[o2i(PCI_ID_REG)]; 735 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 736 if (name) 737 printf(" Vendor Name: %s (0x%04x)\n", name, 738 PCI_VENDOR(rval)); 739 else 740 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 741 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 742 PCI_PRODUCT(rval)); 743 if (name) 744 printf(" Device Name: %s (0x%04x)\n", name, 745 PCI_PRODUCT(rval)); 746 else 747 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 748 749 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 750 751 printf(" Command register: 0x%04x\n", rval & 0xffff); 752 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 753 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 754 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 755 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 756 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 757 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 758 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 759 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 760 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 761 onoff("Fast back-to-back transactions", rval, 762 PCI_COMMAND_BACKTOBACK_ENABLE); 763 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 764 765 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 766 onoff("Immediate Readness", rval, PCI_STATUS_IMMD_READNESS); 767 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 768 "inactive"); 769 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 770 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 771 onoff("User Definable Features (UDF) support", rval, 772 PCI_STATUS_UDF_SUPPORT); 773 onoff("Fast back-to-back capable", rval, 774 PCI_STATUS_BACKTOBACK_SUPPORT); 775 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 776 777 printf(" DEVSEL timing: "); 778 switch (rval & PCI_STATUS_DEVSEL_MASK) { 779 case PCI_STATUS_DEVSEL_FAST: 780 printf("fast"); 781 break; 782 case PCI_STATUS_DEVSEL_MEDIUM: 783 printf("medium"); 784 break; 785 case PCI_STATUS_DEVSEL_SLOW: 786 printf("slow"); 787 break; 788 default: 789 printf("unknown/reserved"); /* XXX */ 790 break; 791 } 792 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 793 794 onoff("Slave signaled Target Abort", rval, 795 PCI_STATUS_TARGET_TARGET_ABORT); 796 onoff("Master received Target Abort", rval, 797 PCI_STATUS_MASTER_TARGET_ABORT); 798 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 799 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 800 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 801 802 rval = regs[o2i(PCI_CLASS_REG)]; 803 for (classp = pci_class; classp->name != NULL; classp++) { 804 if (PCI_CLASS(rval) == classp->val) 805 break; 806 } 807 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 808 while (subclassp && subclassp->name != NULL) { 809 if (PCI_SUBCLASS(rval) == subclassp->val) 810 break; 811 subclassp++; 812 } 813 if (classp->name != NULL) { 814 printf(" Class Name: %s (0x%02x)\n", classp->name, 815 PCI_CLASS(rval)); 816 if (subclassp != NULL && subclassp->name != NULL) 817 printf(" Subclass Name: %s (0x%02x)\n", 818 subclassp->name, PCI_SUBCLASS(rval)); 819 else 820 printf(" Subclass ID: 0x%02x\n", 821 PCI_SUBCLASS(rval)); 822 } else { 823 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 824 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 825 } 826 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 827 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 828 829 rval = regs[o2i(PCI_BHLC_REG)]; 830 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 831 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 832 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 833 PCI_HDRTYPE(rval)); 834 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 835 num = PCI_CACHELINE(rval); 836 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 837 } 838 839 static int 840 pci_conf_print_bar( 841 #ifdef _KERNEL 842 pci_chipset_tag_t pc, pcitag_t tag, 843 #endif 844 const pcireg_t *regs, int reg, const char *name 845 #ifdef _KERNEL 846 , int sizebar 847 #endif 848 ) 849 { 850 int width; 851 pcireg_t rval, rval64h; 852 #ifdef _KERNEL 853 int s; 854 pcireg_t mask, mask64h; 855 #endif 856 857 width = 4; 858 859 /* 860 * Section 6.2.5.1, `Address Maps', tells us that: 861 * 862 * 1) The builtin software should have already mapped the 863 * device in a reasonable way. 864 * 865 * 2) A device which wants 2^n bytes of memory will hardwire 866 * the bottom n bits of the address to 0. As recommended, 867 * we write all 1s and see what we get back. 868 */ 869 870 rval = regs[o2i(reg)]; 871 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 872 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 873 rval64h = regs[o2i(reg + 4)]; 874 width = 8; 875 } else 876 rval64h = 0; 877 878 #ifdef _KERNEL 879 /* XXX don't size unknown memory type? */ 880 if (rval != 0 && sizebar) { 881 /* 882 * The following sequence seems to make some devices 883 * (e.g. host bus bridges, which don't normally 884 * have their space mapped) very unhappy, to 885 * the point of crashing the system. 886 * 887 * Therefore, if the mapping register is zero to 888 * start out with, don't bother trying. 889 */ 890 s = splhigh(); 891 pci_conf_write(pc, tag, reg, 0xffffffff); 892 mask = pci_conf_read(pc, tag, reg); 893 pci_conf_write(pc, tag, reg, rval); 894 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 895 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 896 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 897 mask64h = pci_conf_read(pc, tag, reg + 4); 898 pci_conf_write(pc, tag, reg + 4, rval64h); 899 } else 900 mask64h = 0; 901 splx(s); 902 } else 903 mask = mask64h = 0; 904 #endif /* _KERNEL */ 905 906 printf(" Base address register at 0x%02x", reg); 907 if (name) 908 printf(" (%s)", name); 909 printf("\n "); 910 if (rval == 0) { 911 printf("not implemented(?)\n"); 912 return width; 913 } 914 printf("type: "); 915 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 916 const char *type, *prefetch; 917 918 switch (PCI_MAPREG_MEM_TYPE(rval)) { 919 case PCI_MAPREG_MEM_TYPE_32BIT: 920 type = "32-bit"; 921 break; 922 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 923 type = "32-bit-1M"; 924 break; 925 case PCI_MAPREG_MEM_TYPE_64BIT: 926 type = "64-bit"; 927 break; 928 default: 929 type = "unknown (XXX)"; 930 break; 931 } 932 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 933 prefetch = ""; 934 else 935 prefetch = "non"; 936 printf("%s %sprefetchable memory\n", type, prefetch); 937 switch (PCI_MAPREG_MEM_TYPE(rval)) { 938 case PCI_MAPREG_MEM_TYPE_64BIT: 939 printf(" base: 0x%016llx, ", 940 PCI_MAPREG_MEM64_ADDR( 941 ((((long long) rval64h) << 32) | rval))); 942 #ifdef _KERNEL 943 if (sizebar) 944 printf("size: 0x%016llx", 945 PCI_MAPREG_MEM64_SIZE( 946 ((((long long) mask64h) << 32) | mask))); 947 else 948 #endif /* _KERNEL */ 949 printf("not sized"); 950 printf("\n"); 951 break; 952 case PCI_MAPREG_MEM_TYPE_32BIT: 953 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 954 default: 955 printf(" base: 0x%08x, ", 956 PCI_MAPREG_MEM_ADDR(rval)); 957 #ifdef _KERNEL 958 if (sizebar) 959 printf("size: 0x%08x", 960 PCI_MAPREG_MEM_SIZE(mask)); 961 else 962 #endif /* _KERNEL */ 963 printf("not sized"); 964 printf("\n"); 965 break; 966 } 967 } else { 968 #ifdef _KERNEL 969 if (sizebar) 970 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 971 #endif /* _KERNEL */ 972 printf("i/o\n"); 973 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 974 #ifdef _KERNEL 975 if (sizebar) 976 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 977 else 978 #endif /* _KERNEL */ 979 printf("not sized"); 980 printf("\n"); 981 } 982 983 return width; 984 } 985 986 static void 987 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 988 { 989 int off, needaddr, neednl; 990 991 needaddr = 1; 992 neednl = 0; 993 for (off = first; off < pastlast; off += 4) { 994 if ((off % 16) == 0 || needaddr) { 995 printf(" 0x%02x:", off); 996 needaddr = 0; 997 } 998 printf(" 0x%08x", regs[o2i(off)]); 999 neednl = 1; 1000 if ((off % 16) == 12) { 1001 printf("\n"); 1002 neednl = 0; 1003 } 1004 } 1005 if (neednl) 1006 printf("\n"); 1007 } 1008 1009 static void 1010 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1011 { 1012 pcireg_t rval; 1013 1014 printf("\n AGP Capabilities Register\n"); 1015 1016 rval = regs[o2i(capoff)]; 1017 printf(" Revision: %d.%d\n", 1018 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1019 1020 /* XXX need more */ 1021 } 1022 1023 static const char * 1024 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1025 { 1026 1027 switch ((caps >> 6) & 7) { 1028 case 0: return "self-powered"; 1029 case 1: return "55 mA"; 1030 case 2: return "100 mA"; 1031 case 3: return "160 mA"; 1032 case 4: return "220 mA"; 1033 case 5: return "270 mA"; 1034 case 6: return "320 mA"; 1035 case 7: 1036 default: return "375 mA"; 1037 } 1038 } 1039 1040 static const char * 1041 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1042 { 1043 static const char unk[] = "unknown"; 1044 static const char *pmrev[8] = { 1045 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1046 }; 1047 if (val > 7) 1048 return unk; 1049 return pmrev[val]; 1050 } 1051 1052 static void 1053 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1054 { 1055 uint16_t caps, pmcsr; 1056 pcireg_t reg; 1057 1058 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1059 reg = regs[o2i(capoff + PCI_PMCSR)]; 1060 pmcsr = reg & 0xffff; 1061 1062 printf("\n PCI Power Management Capabilities Register\n"); 1063 1064 printf(" Capabilities register: 0x%04x\n", caps); 1065 printf(" Version: %s\n", 1066 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1067 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1068 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1069 printf(" 3.3V auxiliary current: %s\n", 1070 pci_conf_print_pcipm_cap_aux(caps)); 1071 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1072 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1073 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1074 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1075 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1076 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1077 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1078 1079 printf(" Control/status register: 0x%04x\n", pmcsr); 1080 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1081 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1082 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1083 printf(" PME# assertion: %sabled\n", 1084 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1085 printf(" Data Select: %d\n", 1086 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK)); 1087 printf(" Data Scale: %d\n", 1088 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK)); 1089 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1090 printf(" Bridge Support Extensions register: 0x%02x\n", 1091 (reg >> 16) & 0xff); 1092 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1093 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1094 printf(" Data register: 0x%02x\n", __SHIFTOUT(reg, PCI_PMCSR_DATA)); 1095 1096 } 1097 1098 /* XXX pci_conf_print_vpd_cap */ 1099 /* XXX pci_conf_print_slotid_cap */ 1100 1101 static void 1102 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1103 { 1104 uint32_t ctl, mmc, mme; 1105 1106 regs += o2i(capoff); 1107 ctl = *regs++; 1108 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1109 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1110 1111 printf("\n PCI Message Signaled Interrupt\n"); 1112 1113 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1114 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1115 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1116 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1117 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1118 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1119 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1120 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1121 onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP); 1122 onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN); 1123 printf(" Message Address %sregister: 0x%08x\n", 1124 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1125 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1126 printf(" Message Address %sregister: 0x%08x\n", 1127 "(upper) ", *regs++); 1128 } 1129 printf(" Message Data register: 0x%04x\n", *regs & 0xffff); 1130 regs++; 1131 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1132 printf(" Vector Mask register: 0x%08x\n", *regs++); 1133 printf(" Vector Pending register: 0x%08x\n", *regs++); 1134 } 1135 } 1136 1137 /* XXX pci_conf_print_cpci_hostwap_cap */ 1138 1139 /* 1140 * For both command register and status register. 1141 * The argument "idx" is index number (0 to 7). 1142 */ 1143 static int 1144 pcix_split_trans(unsigned int idx) 1145 { 1146 static int table[8] = { 1147 1, 2, 3, 4, 8, 12, 16, 32 1148 }; 1149 1150 if (idx >= __arraycount(table)) 1151 return -1; 1152 return table[idx]; 1153 } 1154 1155 static void 1156 pci_conf_print_pcix_cap_2ndbusmode(int num) 1157 { 1158 const char *maxfreq, *maxperiod; 1159 1160 printf(" Mode: "); 1161 if (num <= 0x07) 1162 printf("PCI-X Mode 1\n"); 1163 else if (num <= 0x0b) 1164 printf("PCI-X 266 (Mode 2)\n"); 1165 else 1166 printf("PCI-X 533 (Mode 2)\n"); 1167 1168 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1169 switch (num & 0x03) { 1170 default: 1171 case 0: 1172 maxfreq = "N/A"; 1173 maxperiod = "N/A"; 1174 break; 1175 case 1: 1176 maxfreq = "66MHz"; 1177 maxperiod = "15ns"; 1178 break; 1179 case 2: 1180 maxfreq = "100MHz"; 1181 maxperiod = "10ns"; 1182 break; 1183 case 3: 1184 maxfreq = "133MHz"; 1185 maxperiod = "7.5ns"; 1186 break; 1187 } 1188 printf(" Max Clock Freq: %s\n", maxfreq); 1189 printf(" Min Clock Period: %s\n", maxperiod); 1190 } 1191 1192 static void 1193 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1194 { 1195 pcireg_t reg; 1196 int isbridge; 1197 int i; 1198 1199 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1200 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1201 printf("\n PCI-X %s Capabilities Register\n", 1202 isbridge ? "Bridge" : "Non-bridge"); 1203 1204 reg = regs[o2i(capoff)]; 1205 if (isbridge != 0) { 1206 printf(" Secondary status register: 0x%04x\n", 1207 (reg & 0xffff0000) >> 16); 1208 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1209 onoff("133MHz capable", reg, PCIX_STATUS_133); 1210 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1211 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1212 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1213 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1214 pci_conf_print_pcix_cap_2ndbusmode( 1215 __SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1216 printf(" Version: 0x%x\n", 1217 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1218 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1219 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1220 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1221 } else { 1222 printf(" Command register: 0x%04x\n", 1223 (reg & 0xffff0000) >> 16); 1224 onoff("Data Parity Error Recovery", reg, 1225 PCIX_CMD_PERR_RECOVER); 1226 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1227 printf(" Maximum Burst Read Count: %u\n", 1228 PCIX_CMD_BYTECNT(reg)); 1229 printf(" Maximum Split Transactions: %d\n", 1230 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1231 >> PCIX_CMD_SPLTRANS_SHIFT)); 1232 } 1233 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1234 printf(" %sStatus register: 0x%08x\n", 1235 isbridge ? "Bridge " : "", reg); 1236 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1237 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1238 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1239 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1240 onoff("133MHz capable", reg, PCIX_STATUS_133); 1241 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1242 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1243 if (isbridge != 0) { 1244 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1245 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1246 } else { 1247 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1248 "bridge device", "simple device"); 1249 printf(" Designed max memory read byte count: %d\n", 1250 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1251 >> PCIX_STATUS_MAXB_SHIFT)); 1252 printf(" Designed max outstanding split transaction: %d\n", 1253 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1254 >> PCIX_STATUS_MAXST_SHIFT)); 1255 printf(" MAX cumulative Read Size: %u\n", 1256 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1257 onoff("Received split completion error", reg, 1258 PCIX_STATUS_SCERR); 1259 } 1260 onoff("266MHz capable", reg, PCIX_STATUS_266); 1261 onoff("533MHz capable", reg, PCIX_STATUS_533); 1262 1263 if (isbridge == 0) 1264 return; 1265 1266 /* Only for bridge */ 1267 for (i = 0; i < 2; i++) { 1268 reg = regs[o2i(capoff+PCIX_BRIDGE_UP_STCR + (4 * i))]; 1269 printf(" %s split transaction control register: 0x%08x\n", 1270 (i == 0) ? "Upstream" : "Downstream", reg); 1271 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1272 printf(" Commitment Limit: %d\n", 1273 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1274 } 1275 } 1276 1277 /* pci_conf_print_ht_slave_cap */ 1278 /* pci_conf_print_ht_host_cap */ 1279 /* pci_conf_print_ht_switch_cap */ 1280 /* pci_conf_print_ht_intr_cap */ 1281 /* pci_conf_print_ht_revid_cap */ 1282 /* pci_conf_print_ht_unitid_cap */ 1283 /* pci_conf_print_ht_extcnf_cap */ 1284 /* pci_conf_print_ht_addrmap_cap */ 1285 /* pci_conf_print_ht_msimap_cap */ 1286 1287 static void 1288 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1289 { 1290 pcireg_t val; 1291 uint32_t lo, hi; 1292 1293 /* 1294 * Print the rest of the command register bits. Others are 1295 * printed in pci_conf_print_ht_cap(). 1296 */ 1297 val = regs[o2i(capoff + PCI_HT_CMD)]; 1298 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1299 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1300 1301 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1302 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1303 printf(" Address Low register: 0x%08x\n", lo); 1304 printf(" Address high register: 0x%08x\n", hi); 1305 printf(" Address: 0x%016" PRIx64 "\n", 1306 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1307 } 1308 1309 /* pci_conf_print_ht_droute_cap */ 1310 /* pci_conf_print_ht_vcset_cap */ 1311 /* pci_conf_print_ht_retry_cap */ 1312 /* pci_conf_print_ht_x86enc_cap */ 1313 /* pci_conf_print_ht_gen3_cap */ 1314 /* pci_conf_print_ht_fle_cap */ 1315 /* pci_conf_print_ht_pm_cap */ 1316 /* pci_conf_print_ht_hnc_cap */ 1317 1318 static const struct ht_types { 1319 pcireg_t cap; 1320 const char *name; 1321 void (*printfunc)(const pcireg_t *, int); 1322 } ht_captab[] = { 1323 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1324 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1325 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1326 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1327 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1328 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1329 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1330 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1331 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1332 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1333 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1334 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1335 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1336 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1337 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1338 {PCI_HT_CAP_PM, "Power Management", NULL }, 1339 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1340 }; 1341 1342 static void 1343 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1344 { 1345 pcireg_t val, foundcap; 1346 unsigned int off; 1347 1348 val = regs[o2i(capoff + PCI_HT_CMD)]; 1349 1350 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1351 1352 printf(" Command register: 0x%04x\n", val >> 16); 1353 foundcap = PCI_HT_CAP(val); 1354 for (off = 0; off < __arraycount(ht_captab); off++) { 1355 if (ht_captab[off].cap == foundcap) 1356 break; 1357 } 1358 printf(" Capability Type: 0x%02x ", foundcap); 1359 if (off >= __arraycount(ht_captab)) { 1360 printf("(unknown)\n"); 1361 return; 1362 } 1363 printf("(%s)\n", ht_captab[off].name); 1364 if (ht_captab[off].printfunc != NULL) 1365 ht_captab[off].printfunc(regs, capoff); 1366 } 1367 1368 static void 1369 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1370 { 1371 uint16_t caps; 1372 1373 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1374 1375 printf("\n PCI Vendor Specific Capabilities Register\n"); 1376 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1377 } 1378 1379 static void 1380 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1381 { 1382 pcireg_t val; 1383 1384 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1385 1386 printf("\n Debugport Capability Register\n"); 1387 printf(" Debug base Register: 0x%04x\n", 1388 val >> PCI_DEBUG_BASER_SHIFT); 1389 printf(" port offset: 0x%04x\n", 1390 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1391 printf(" BAR number: %u\n", 1392 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1393 } 1394 1395 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1396 /* XXX pci_conf_print_hotplug_cap */ 1397 1398 static void 1399 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1400 { 1401 pcireg_t reg; 1402 1403 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1404 1405 printf("\n Subsystem ID Capability Register\n"); 1406 printf(" Subsystem ID : 0x%08x\n", reg); 1407 } 1408 1409 /* XXX pci_conf_print_agp8_cap */ 1410 /* XXX pci_conf_print_secure_cap */ 1411 1412 static void 1413 pci_print_pcie_L0s_latency(uint32_t val) 1414 { 1415 1416 switch (val) { 1417 case 0x0: 1418 printf("Less than 64ns\n"); 1419 break; 1420 case 0x1: 1421 case 0x2: 1422 case 0x3: 1423 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1424 break; 1425 case 0x4: 1426 printf("512ns to less than 1us\n"); 1427 break; 1428 case 0x5: 1429 printf("1us to less than 2us\n"); 1430 break; 1431 case 0x6: 1432 printf("2us - 4us\n"); 1433 break; 1434 case 0x7: 1435 printf("More than 4us\n"); 1436 break; 1437 } 1438 } 1439 1440 static void 1441 pci_print_pcie_L1_latency(uint32_t val) 1442 { 1443 1444 switch (val) { 1445 case 0x0: 1446 printf("Less than 1us\n"); 1447 break; 1448 case 0x6: 1449 printf("32us - 64us\n"); 1450 break; 1451 case 0x7: 1452 printf("More than 64us\n"); 1453 break; 1454 default: 1455 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1456 break; 1457 } 1458 } 1459 1460 static void 1461 pci_print_pcie_compl_timeout(uint32_t val) 1462 { 1463 1464 switch (val) { 1465 case 0x0: 1466 printf("50us to 50ms\n"); 1467 break; 1468 case 0x5: 1469 printf("16ms to 55ms\n"); 1470 break; 1471 case 0x6: 1472 printf("65ms to 210ms\n"); 1473 break; 1474 case 0x9: 1475 printf("260ms to 900ms\n"); 1476 break; 1477 case 0xa: 1478 printf("1s to 3.5s\n"); 1479 break; 1480 default: 1481 printf("unknown %u value\n", val); 1482 break; 1483 } 1484 } 1485 1486 static const char * const pcie_linkspeeds[] = {"2.5", "2.5", "5.0", "8.0"}; 1487 1488 static void 1489 pci_print_pcie_linkspeed(pcireg_t val) 1490 { 1491 1492 if (val > __arraycount(pcie_linkspeeds)) 1493 printf("unknown value (%u)\n", val); 1494 else 1495 printf("%sGT/s\n", pcie_linkspeeds[val]); 1496 } 1497 1498 static void 1499 pci_print_pcie_linkspeedvector(pcireg_t val) 1500 { 1501 unsigned int i; 1502 1503 /* Start from 0 */ 1504 for (i = 0; i < 16; i++) 1505 if (((val >> i) & 0x01) != 0) { 1506 if (i >= __arraycount(pcie_linkspeeds)) 1507 printf(" unknown vector (0x%x)", 1 << i); 1508 else 1509 printf(" %sGT/s", pcie_linkspeeds[i]); 1510 } 1511 } 1512 1513 static void 1514 pci_print_pcie_link_deemphasis(pcireg_t val) 1515 { 1516 switch (val) { 1517 case 0: 1518 printf("-6dB"); 1519 break; 1520 case 1: 1521 printf("-3.5dB"); 1522 break; 1523 default: 1524 printf("(reserved value)"); 1525 } 1526 } 1527 1528 static void 1529 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1530 { 1531 pcireg_t reg; /* for each register */ 1532 pcireg_t val; /* for each bitfield */ 1533 bool check_link = false; 1534 bool check_slot = false; 1535 bool check_rootport = false; 1536 unsigned int pciever; 1537 unsigned int i; 1538 1539 printf("\n PCI Express Capabilities Register\n"); 1540 /* Capability Register */ 1541 reg = regs[o2i(capoff)]; 1542 printf(" Capability register: 0x%04x\n", reg >> 16); 1543 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1544 printf(" Capability version: %u\n", pciever); 1545 printf(" Device type: "); 1546 switch ((reg & 0x00f00000) >> 20) { 1547 case 0x0: 1548 printf("PCI Express Endpoint device\n"); 1549 check_link = true; 1550 break; 1551 case 0x1: 1552 printf("Legacy PCI Express Endpoint device\n"); 1553 check_link = true; 1554 break; 1555 case 0x4: 1556 printf("Root Port of PCI Express Root Complex\n"); 1557 check_link = true; 1558 check_slot = true; 1559 check_rootport = true; 1560 break; 1561 case 0x5: 1562 printf("Upstream Port of PCI Express Switch\n"); 1563 break; 1564 case 0x6: 1565 printf("Downstream Port of PCI Express Switch\n"); 1566 check_slot = true; 1567 check_rootport = true; 1568 break; 1569 case 0x7: 1570 printf("PCI Express to PCI/PCI-X Bridge\n"); 1571 break; 1572 case 0x8: 1573 printf("PCI/PCI-X to PCI Express Bridge\n"); 1574 break; 1575 case 0x9: 1576 printf("Root Complex Integrated Endpoint\n"); 1577 break; 1578 case 0xa: 1579 check_rootport = true; 1580 printf("Root Complex Event Collector\n"); 1581 break; 1582 default: 1583 printf("unknown\n"); 1584 break; 1585 } 1586 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1587 printf(" Interrupt Message Number: 0x%02x\n", 1588 (unsigned int)((reg & PCIE_XCAP_IRQ) >> 27)); 1589 1590 /* Device Capability Register */ 1591 reg = regs[o2i(capoff + PCIE_DCAP)]; 1592 printf(" Device Capabilities Register: 0x%08x\n", reg); 1593 printf(" Max Payload Size Supported: %u bytes max\n", 1594 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1595 printf(" Phantom Functions Supported: "); 1596 switch ((reg & PCIE_DCAP_PHANTOM_FUNCS) >> 3) { 1597 case 0x0: 1598 printf("not available\n"); 1599 break; 1600 case 0x1: 1601 printf("MSB\n"); 1602 break; 1603 case 0x2: 1604 printf("two MSB\n"); 1605 break; 1606 case 0x3: 1607 printf("All three bits\n"); 1608 break; 1609 } 1610 printf(" Extended Tag Field Supported: %dbit\n", 1611 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1612 printf(" Endpoint L0 Acceptable Latency: "); 1613 pci_print_pcie_L0s_latency((reg & PCIE_DCAP_L0S_LATENCY) >> 6); 1614 printf(" Endpoint L1 Acceptable Latency: "); 1615 pci_print_pcie_L1_latency((reg & PCIE_DCAP_L1_LATENCY) >> 9); 1616 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1617 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1618 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1619 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1620 printf(" Captured Slot Power Limit Value: %d\n", 1621 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18); 1622 printf(" Captured Slot Power Limit Scale: %d\n", 1623 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26); 1624 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1625 1626 /* Device Control Register */ 1627 reg = regs[o2i(capoff + PCIE_DCSR)]; 1628 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1629 onoff("Correctable Error Reporting Enable", reg, 1630 PCIE_DCSR_ENA_COR_ERR); 1631 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1632 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1633 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1634 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1635 printf(" Max Payload Size: %d byte\n", 1636 128 << (((unsigned int)(reg & PCIE_DCSR_MAX_PAYLOAD) >> 5))); 1637 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1638 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1639 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1640 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1641 printf(" Max Read Request Size: %d byte\n", 1642 128 << ((unsigned int)(reg & PCIE_DCSR_MAX_READ_REQ) >> 12)); 1643 1644 /* Device Status Register */ 1645 reg = regs[o2i(capoff + PCIE_DCSR)]; 1646 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1647 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1648 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1649 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1650 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1651 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1652 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1653 onoff("Emergency Power Reduction Detected", reg, 1654 PCIE_DCSR_EMGPWRREDD); 1655 1656 if (check_link) { 1657 /* Link Capability Register */ 1658 reg = regs[o2i(capoff + PCIE_LCAP)]; 1659 printf(" Link Capabilities Register: 0x%08x\n", reg); 1660 printf(" Maximum Link Speed: "); 1661 pci_print_pcie_linkspeed(reg & PCIE_LCAP_MAX_SPEED); 1662 printf(" Maximum Link Width: x%u lanes\n", 1663 (unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4); 1664 printf(" Active State PM Support: "); 1665 val = (reg & PCIE_LCAP_ASPM) >> 10; 1666 switch (val) { 1667 case 0x0: 1668 printf("No ASPM support\n"); 1669 break; 1670 case 0x1: 1671 printf("L0s supported\n"); 1672 break; 1673 case 0x2: 1674 printf("L1 supported\n"); 1675 break; 1676 case 0x3: 1677 printf("L0s and L1 supported\n"); 1678 break; 1679 } 1680 printf(" L0 Exit Latency: "); 1681 pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12); 1682 printf(" L1 Exit Latency: "); 1683 pci_print_pcie_L1_latency((reg & PCIE_LCAP_L1_EXIT) >> 15); 1684 printf(" Port Number: %u\n", reg >> 24); 1685 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1686 onoff("Surprise Down Error Report", reg, 1687 PCIE_LCAP_SURPRISE_DOWN); 1688 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1689 onoff("Link BW Notification Capable", reg, 1690 PCIE_LCAP_LINK_BW_NOTIFY); 1691 onoff("ASPM Optionally Compliance", reg, 1692 PCIE_LCAP_ASPM_COMPLIANCE); 1693 1694 /* Link Control Register */ 1695 reg = regs[o2i(capoff + PCIE_LCSR)]; 1696 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1697 printf(" Active State PM Control: "); 1698 val = reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S); 1699 switch (val) { 1700 case 0: 1701 printf("disabled\n"); 1702 break; 1703 case 1: 1704 printf("L0s Entry Enabled\n"); 1705 break; 1706 case 2: 1707 printf("L1 Entry Enabled\n"); 1708 break; 1709 case 3: 1710 printf("L0s and L1 Entry Enabled\n"); 1711 break; 1712 } 1713 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1714 "128bytes", "64bytes"); 1715 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1716 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1717 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1718 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1719 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1720 onoff("Hardware Autonomous Width Disable", reg, 1721 PCIE_LCSR_HAWD); 1722 onoff("Link Bandwidth Management Interrupt Enable", reg, 1723 PCIE_LCSR_LBMIE); 1724 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1725 PCIE_LCSR_LABIE); 1726 printf(" DRS Signaling Control: "); 1727 val = __SHIFTOUT(reg, PCIE_LCSR_DRSSGNL); 1728 switch (val) { 1729 case 0: 1730 printf("not reported\n"); 1731 break; 1732 case 1: 1733 printf("Interrupt Enabled\n"); 1734 break; 1735 case 2: 1736 printf("DRS to FRS Signaling Enabled\n"); 1737 break; 1738 default: 1739 printf("reserved\n"); 1740 break; 1741 } 1742 1743 /* Link Status Register */ 1744 reg = regs[o2i(capoff + PCIE_LCSR)]; 1745 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1746 printf(" Negotiated Link Speed: "); 1747 pci_print_pcie_linkspeed(__SHIFTOUT(reg, PCIE_LCSR_LINKSPEED)); 1748 printf(" Negotiated Link Width: x%u lanes\n", 1749 (reg >> 20) & 0x003f); 1750 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1751 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1752 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1753 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1754 onoff("Link Bandwidth Management Status", reg, 1755 PCIE_LCSR_LINK_BW_MGMT); 1756 onoff("Link Autonomous Bandwidth Status", reg, 1757 PCIE_LCSR_LINK_AUTO_BW); 1758 } 1759 1760 if (check_slot == true) { 1761 /* Slot Capability Register */ 1762 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1763 printf(" Slot Capability Register: 0x%08x\n", reg); 1764 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1765 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1766 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1767 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1768 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1769 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1770 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1771 printf(" Slot Power Limit Value: %d\n", 1772 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1773 printf(" Slot Power Limit Scale: %d\n", 1774 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1775 onoff("Electromechanical Interlock Present", reg, 1776 PCIE_SLCAP_EIP); 1777 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1778 printf(" Physical Slot Number: %d\n", 1779 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1780 1781 /* Slot Control Register */ 1782 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1783 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1784 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1785 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1786 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1787 onoff("Presense Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1788 onoff("Command Completed Interrupt Enabled", reg, 1789 PCIE_SLCSR_CCE); 1790 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1791 printf(" Attention Indicator Control: "); 1792 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1793 case 0x0: 1794 printf("reserved\n"); 1795 break; 1796 case 0x1: 1797 printf("on\n"); 1798 break; 1799 case 0x2: 1800 printf("blink\n"); 1801 break; 1802 case 0x3: 1803 printf("off\n"); 1804 break; 1805 } 1806 printf(" Power Indicator Control: "); 1807 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1808 case 0x0: 1809 printf("reserved\n"); 1810 break; 1811 case 0x1: 1812 printf("on\n"); 1813 break; 1814 case 0x2: 1815 printf("blink\n"); 1816 break; 1817 case 0x3: 1818 printf("off\n"); 1819 break; 1820 } 1821 printf(" Power Controller Control: Power %s\n", 1822 reg & PCIE_SLCSR_PCC ? "off" : "on"); 1823 onoff("Electromechanical Interlock Control", 1824 reg, PCIE_SLCSR_EIC); 1825 onoff("Data Link Layer State Changed Enable", reg, 1826 PCIE_SLCSR_DLLSCE); 1827 onoff("Auto Slot Power Limit Disable", reg, 1828 PCIE_SLCSR_AUTOSPLDIS); 1829 1830 /* Slot Status Register */ 1831 printf(" Slot Status Register: 0x%04x\n", reg >> 16); 1832 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1833 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1834 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1835 onoff("Presense Detect Changed", reg, PCIE_SLCSR_PDC); 1836 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1837 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1838 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1839 onoff("Electromechanical Interlock engaged", reg, 1840 PCIE_SLCSR_EIS); 1841 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 1842 } 1843 1844 if (check_rootport == true) { 1845 /* Root Control Register */ 1846 reg = regs[o2i(capoff + PCIE_RCR)]; 1847 printf(" Root Control Register: %04x\n", reg & 0xffff); 1848 onoff("SERR on Correctable Error Enable", reg, 1849 PCIE_RCR_SERR_CER); 1850 onoff("SERR on Non-Fatal Error Enable", reg, 1851 PCIE_RCR_SERR_NFER); 1852 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 1853 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 1854 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 1855 1856 /* Root Capability Register */ 1857 printf(" Root Capability Register: 0x%04x\n", 1858 reg >> 16); 1859 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 1860 1861 /* Root Status Register */ 1862 reg = regs[o2i(capoff + PCIE_RSR)]; 1863 printf(" Root Status Register: 0x%08x\n", reg); 1864 printf(" PME Requester ID: 0x%04x\n", 1865 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1866 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 1867 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 1868 } 1869 1870 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1871 if (pciever < 2) 1872 return; 1873 1874 /* Device Capabilities 2 */ 1875 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1876 printf(" Device Capabilities 2: 0x%08x\n", reg); 1877 printf(" Completion Timeout Ranges Supported: "); 1878 val = reg & PCIE_DCAP2_COMPT_RANGE; 1879 switch (val) { 1880 case 0: 1881 printf("not supported\n"); 1882 break; 1883 default: 1884 for (i = 0; i <= 3; i++) { 1885 if (((val >> i) & 0x01) != 0) 1886 printf("%c", 'A' + i); 1887 } 1888 printf("\n"); 1889 } 1890 onoff("Completion Timeout Disable Supported", reg, 1891 PCIE_DCAP2_COMPT_DIS); 1892 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 1893 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 1894 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 1895 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 1896 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 1897 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 1898 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 1899 printf(" TPH Completer Supported: "); 1900 switch (__SHIFTOUT(reg, PCIE_DCAP2_TPH_COMP)) { 1901 case 0: 1902 printf("Not supportted\n"); 1903 break; 1904 case 1: 1905 printf("TPH\n"); 1906 break; 1907 case 3: 1908 printf("TPH and Extended TPH\n"); 1909 break; 1910 default: 1911 printf("(reserved value)\n"); 1912 break; 1913 1914 } 1915 printf(" LN System CLS: "); 1916 switch (__SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 1917 case 0x0: 1918 printf("Not supported or not in effect\n"); 1919 break; 1920 case 0x1: 1921 printf("64byte cachelines in effect\n"); 1922 break; 1923 case 0x2: 1924 printf("128byte cachelines in effect\n"); 1925 break; 1926 case 0x3: 1927 printf("Reserved\n"); 1928 break; 1929 } 1930 printf(" OBFF Supported: "); 1931 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 1932 case 0x0: 1933 printf("Not supported\n"); 1934 break; 1935 case 0x1: 1936 printf("Message only\n"); 1937 break; 1938 case 0x2: 1939 printf("WAKE# only\n"); 1940 break; 1941 case 0x3: 1942 printf("Both\n"); 1943 break; 1944 } 1945 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 1946 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 1947 val = __SHIFTOUT(reg, PCIE_DCAP2_MAX_EETLP); 1948 printf(" Max End-End TLP Prefixes: %u\n", (val == 0) ? 4 : val); 1949 printf(" Emergency Power Reduction Supported: "); 1950 switch (__SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) { 1951 case 0x0: 1952 printf("Not supported\n"); 1953 break; 1954 case 0x1: 1955 printf("Device Specific mechanism\n"); 1956 break; 1957 case 0x2: 1958 printf("Form Factor spec or Device Specific mechanism\n"); 1959 break; 1960 case 0x3: 1961 printf("Reserved\n"); 1962 break; 1963 } 1964 onoff("Emergency Power Reduction Initialization Required", reg, 1965 PCIE_DCAP2_EMGPWRRED_INI); 1966 onoff("FRS Supported", reg, PCIE_DCAP2_FRS); 1967 1968 /* Device Control 2 */ 1969 reg = regs[o2i(capoff + PCIE_DCSR2)]; 1970 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 1971 printf(" Completion Timeout Value: "); 1972 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 1973 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 1974 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 1975 onoff("AtomicOp Rquester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 1976 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 1977 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 1978 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 1979 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 1980 onoff("Emergency Power Reduction Request", reg, 1981 PCIE_DCSR2_EMGPWRRED_REQ); 1982 printf(" OBFF: "); 1983 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 1984 case 0x0: 1985 printf("Disabled\n"); 1986 break; 1987 case 0x1: 1988 printf("Enabled with Message Signaling Variation A\n"); 1989 break; 1990 case 0x2: 1991 printf("Enabled with Message Signaling Variation B\n"); 1992 break; 1993 case 0x3: 1994 printf("Enabled using WAKE# signaling\n"); 1995 break; 1996 } 1997 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 1998 1999 if (check_link) { 2000 bool drs_supported = false; 2001 2002 /* Link Capability 2 */ 2003 reg = regs[o2i(capoff + PCIE_LCAP2)]; 2004 /* If the vector is 0, LCAP2 is not implemented */ 2005 if ((reg & PCIE_LCAP2_SUP_LNKSV) != 0) { 2006 printf(" Link Capabilities 2: 0x%08x\n", reg); 2007 printf(" Supported Link Speeds Vector:"); 2008 pci_print_pcie_linkspeedvector( 2009 __SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV)); 2010 printf("\n"); 2011 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 2012 printf(" " 2013 "Lower SKP OS Generation Supported Speed Vector:"); 2014 pci_print_pcie_linkspeedvector( 2015 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV)); 2016 printf("\n"); 2017 printf(" " 2018 "Lower SKP OS Reception Supported Speed Vector:"); 2019 pci_print_pcie_linkspeedvector( 2020 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV)); 2021 printf("\n"); 2022 onoff("DRS Supported", reg, PCIE_LCAP2_DRS); 2023 drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false; 2024 } 2025 2026 /* Link Control 2 */ 2027 reg = regs[o2i(capoff + PCIE_LCSR2)]; 2028 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 2029 printf(" Target Link Speed: "); 2030 pci_print_pcie_linkspeed(__SHIFTOUT(reg, 2031 PCIE_LCSR2_TGT_LSPEED)); 2032 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 2033 onoff("HW Autonomous Speed Disabled", reg, 2034 PCIE_LCSR2_HW_AS_DIS); 2035 printf(" Selectable De-emphasis: "); 2036 pci_print_pcie_link_deemphasis( 2037 __SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP)); 2038 printf("\n"); 2039 printf(" Transmit Margin: %u\n", 2040 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 2041 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 2042 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 2043 printf(" Compliance Present/De-emphasis: "); 2044 pci_print_pcie_link_deemphasis( 2045 __SHIFTOUT(reg, PCIE_LCSR2_COMP_DEEMP)); 2046 printf("\n"); 2047 2048 /* Link Status 2 */ 2049 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 2050 printf(" Current De-emphasis Level: "); 2051 pci_print_pcie_link_deemphasis( 2052 __SHIFTOUT(reg, PCIE_LCSR2_DEEMP_LVL)); 2053 printf("\n"); 2054 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 2055 onoff("Equalization Phase 1 Successful", reg, 2056 PCIE_LCSR2_EQP1_SUC); 2057 onoff("Equalization Phase 2 Successful", reg, 2058 PCIE_LCSR2_EQP2_SUC); 2059 onoff("Equalization Phase 3 Successful", reg, 2060 PCIE_LCSR2_EQP3_SUC); 2061 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 2062 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD); 2063 if (drs_supported) { 2064 printf(" Downstream Component Presence: "); 2065 switch (__SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) { 2066 case PCIE_DSCOMPN_DOWN_NOTDETERM: 2067 printf("Link Down - Presence Not" 2068 " Determined\n"); 2069 break; 2070 case PCIE_DSCOMPN_DOWN_NOTPRES: 2071 printf("Link Down - Component Not Present\n"); 2072 break; 2073 case PCIE_DSCOMPN_DOWN_PRES: 2074 printf("Link Down - Component Present\n"); 2075 break; 2076 case PCIE_DSCOMPN_UP_PRES: 2077 printf("Link Up - Component Present\n"); 2078 break; 2079 case PCIE_DSCOMPN_UP_PRES_DRS: 2080 printf("Link Up - Component Present and DRS" 2081 " received\n"); 2082 break; 2083 default: 2084 printf("reserved\n"); 2085 break; 2086 } 2087 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV); 2088 } 2089 } 2090 2091 /* Slot Capability 2 */ 2092 /* Slot Control 2 */ 2093 /* Slot Status 2 */ 2094 } 2095 2096 static void 2097 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 2098 { 2099 pcireg_t reg; 2100 2101 printf("\n MSI-X Capability Register\n"); 2102 2103 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2104 printf(" Message Control register: 0x%04x\n", 2105 (reg >> 16) & 0xff); 2106 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 2107 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 2108 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 2109 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 2110 printf(" Table offset register: 0x%08x\n", reg); 2111 printf(" Table offset: 0x%08x\n", 2112 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 2113 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 2114 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 2115 printf(" Pending bit array register: 0x%08x\n", reg); 2116 printf(" Pending bit array offset: 0x%08x\n", 2117 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 2118 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 2119 } 2120 2121 static void 2122 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 2123 { 2124 pcireg_t reg; 2125 2126 printf("\n Serial ATA Capability Register\n"); 2127 2128 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2129 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 2130 printf(" Revision: %u.%u\n", 2131 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 2132 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 2133 2134 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 2135 2136 printf(" BAR Register: 0x%08x\n", reg); 2137 printf(" Register location: "); 2138 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 2139 printf("in config space\n"); 2140 else { 2141 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 2142 printf(" BAR offset: 0x%08x\n", 2143 (pcireg_t)__SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 2144 } 2145 } 2146 2147 static void 2148 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 2149 { 2150 pcireg_t reg; 2151 2152 printf("\n Advanced Features Capability Register\n"); 2153 2154 reg = regs[o2i(capoff + PCI_AFCAPR)]; 2155 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 2156 printf(" AF Structure Length: 0x%02x\n", 2157 (pcireg_t)__SHIFTOUT(reg, PCI_AF_LENGTH)); 2158 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 2159 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 2160 reg = regs[o2i(capoff + PCI_AFCSR)]; 2161 printf(" AF Control register: 0x%02x\n", reg & 0xff); 2162 /* 2163 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 2164 * and it's always 0 on read 2165 */ 2166 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 2167 onoff("Transaction Pending", reg, PCI_AFSR_TP); 2168 } 2169 2170 static struct { 2171 pcireg_t cap; 2172 const char *name; 2173 void (*printfunc)(const pcireg_t *, int); 2174 } pci_captab[] = { 2175 { PCI_CAP_RESERVED0, "reserved", NULL }, 2176 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 2177 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 2178 { PCI_CAP_VPD, "VPD", NULL }, 2179 { PCI_CAP_SLOTID, "SlotID", NULL }, 2180 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 2181 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 2182 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2183 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2184 { PCI_CAP_VENDSPEC, "Vendor-specific", 2185 pci_conf_print_vendspec_cap }, 2186 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2187 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2188 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2189 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2190 pci_conf_print_subsystem_cap }, 2191 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2192 { PCI_CAP_SECURE, "Secure Device", NULL }, 2193 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2194 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2195 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2196 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2197 { PCI_CAP_EA, "Enhanced Allocation", NULL } 2198 }; 2199 2200 static int 2201 pci_conf_find_cap(const pcireg_t *regs, int capoff, unsigned int capid, 2202 int *offsetp) 2203 { 2204 pcireg_t rval; 2205 int off; 2206 2207 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2208 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2209 rval = regs[o2i(off)]; 2210 if (capid == PCI_CAPLIST_CAP(rval)) { 2211 if (offsetp != NULL) 2212 *offsetp = off; 2213 return 1; 2214 } 2215 } 2216 return 0; 2217 } 2218 2219 static void 2220 pci_conf_print_caplist( 2221 #ifdef _KERNEL 2222 pci_chipset_tag_t pc, pcitag_t tag, 2223 #endif 2224 const pcireg_t *regs, int capoff) 2225 { 2226 int off; 2227 pcireg_t foundcap; 2228 pcireg_t rval; 2229 bool foundtable[__arraycount(pci_captab)]; 2230 unsigned int i; 2231 2232 /* Clear table */ 2233 for (i = 0; i < __arraycount(pci_captab); i++) 2234 foundtable[i] = false; 2235 2236 /* Print capability register's offset and the type first */ 2237 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2238 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2239 rval = regs[o2i(off)]; 2240 printf(" Capability register at 0x%02x\n", off); 2241 2242 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2243 foundcap = PCI_CAPLIST_CAP(rval); 2244 if (foundcap < __arraycount(pci_captab)) { 2245 printf("%s)\n", pci_captab[foundcap].name); 2246 /* Mark as found */ 2247 foundtable[foundcap] = true; 2248 } else 2249 printf("unknown)\n"); 2250 } 2251 2252 /* 2253 * And then, print the detail of each capability registers 2254 * in capability value's order. 2255 */ 2256 for (i = 0; i < __arraycount(pci_captab); i++) { 2257 if (foundtable[i] == false) 2258 continue; 2259 2260 /* 2261 * The type was found. Search capability list again and 2262 * print all capabilities that the capabiliy type is 2263 * the same. This is required because some capabilities 2264 * appear multiple times (e.g. HyperTransport capability). 2265 */ 2266 #if 0 2267 if (pci_conf_find_cap(regs, capoff, i, &off)) { 2268 rval = regs[o2i(off)]; 2269 if (pci_captab[i].printfunc != NULL) 2270 pci_captab[i].printfunc(regs, off); 2271 } 2272 #else 2273 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2274 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2275 rval = regs[o2i(off)]; 2276 if ((PCI_CAPLIST_CAP(rval) == i) 2277 && (pci_captab[i].printfunc != NULL)) 2278 pci_captab[i].printfunc(regs, off); 2279 } 2280 #endif 2281 } 2282 } 2283 2284 /* Extended Capability */ 2285 2286 static void 2287 pci_conf_print_aer_cap_uc(pcireg_t reg) 2288 { 2289 2290 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2291 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2292 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2293 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP); 2294 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2295 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2296 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2297 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2298 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2299 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2300 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2301 onoff("Unsupported Request Error", reg, 2302 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2303 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2304 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2305 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2306 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2307 onoff("TLP Prefix Blocked Error", reg, 2308 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2309 onoff("Poisoned TLP Egress Blocked", reg, 2310 PCI_AER_UC_POISONTLP_EGRESS_BLOCKED); 2311 } 2312 2313 static void 2314 pci_conf_print_aer_cap_cor(pcireg_t reg) 2315 { 2316 2317 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2318 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2319 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2320 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2321 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2322 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2323 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2324 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2325 } 2326 2327 static void 2328 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2329 { 2330 2331 printf(" First Error Pointer: 0x%04x\n", 2332 (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2333 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2334 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2335 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2336 onoff("ECRC Check Enab", reg, PCI_AER_ECRC_CHECK_ENABLE); 2337 onoff("Multiple Header Recording Capable", reg, 2338 PCI_AER_MULT_HDR_CAPABLE); 2339 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE); 2340 onoff("Completion Timeout Prefix/Header Log Capable", reg, 2341 PCI_AER_COMPTOUTPRFXHDRLOG_CAP); 2342 2343 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2344 if (!tlp_prefix_log) 2345 return; 2346 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2347 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2348 } 2349 2350 static void 2351 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2352 { 2353 2354 onoff("Correctable Error Reporting Enable", reg, 2355 PCI_AER_ROOTERR_COR_ENABLE); 2356 onoff("Non-Fatal Error Reporting Enable", reg, 2357 PCI_AER_ROOTERR_NF_ENABLE); 2358 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2359 } 2360 2361 static void 2362 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2363 { 2364 2365 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2366 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2367 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2368 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2369 PCI_AER_ROOTERR_MULTI_UC_ERR); 2370 onoff("First Uncorrectable Fatal", reg, PCI_AER_ROOTERR_FIRST_UC_FATAL); 2371 onoff("Non-Fatal Error Messages Received", reg, PCI_AER_ROOTERR_NF_ERR); 2372 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2373 printf(" Advanced Error Interrupt Message Number: 0x%02x\n", 2374 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2375 } 2376 2377 static void 2378 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2379 { 2380 2381 printf(" Correctable Source ID: 0x%04x\n", 2382 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2383 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2384 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2385 } 2386 2387 static void 2388 pci_conf_print_aer_cap(const pcireg_t *regs, int capoff, int extcapoff) 2389 { 2390 pcireg_t reg; 2391 int pcie_capoff; 2392 int pcie_devtype = -1; 2393 bool tlp_prefix_log = false; 2394 2395 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2396 reg = regs[o2i(pcie_capoff)]; 2397 pcie_devtype = PCIE_XCAP_TYPE(reg); 2398 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2399 if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2400 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2401 /* End-End TLP Prefix Supported */ 2402 if (reg & PCIE_DCAP2_EETLP_PREF) { 2403 tlp_prefix_log = true; 2404 } 2405 } 2406 } 2407 2408 printf("\n Advanced Error Reporting Register\n"); 2409 2410 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2411 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2412 pci_conf_print_aer_cap_uc(reg); 2413 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2414 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2415 pci_conf_print_aer_cap_uc(reg); 2416 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2417 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2418 pci_conf_print_aer_cap_uc(reg); 2419 2420 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2421 printf(" Correctable Error Status register: 0x%08x\n", reg); 2422 pci_conf_print_aer_cap_cor(reg); 2423 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2424 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2425 pci_conf_print_aer_cap_cor(reg); 2426 2427 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2428 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2429 reg); 2430 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2431 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2432 printf(" Header Log register:\n"); 2433 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2434 extcapoff + PCI_AER_ROOTERR_CMD); 2435 2436 switch (pcie_devtype) { 2437 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ 2438 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ 2439 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2440 printf(" Root Error Command register: 0x%08x\n", reg); 2441 pci_conf_print_aer_cap_rooterr_cmd(reg); 2442 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2443 printf(" Root Error Status register: 0x%08x\n", reg); 2444 pci_conf_print_aer_cap_rooterr_status(reg); 2445 2446 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2447 printf(" Error Source Identification: 0x%04x\n", reg); 2448 pci_conf_print_aer_cap_errsrc_id(reg); 2449 break; 2450 } 2451 2452 if (tlp_prefix_log) { 2453 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2454 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2455 } 2456 } 2457 2458 static void 2459 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2460 pcireg_t parbsel, int parbsize) 2461 { 2462 pcireg_t reg; 2463 int num = 16 << parbsel; 2464 int num_per_reg = sizeof(pcireg_t) / parbsize; 2465 int i, j; 2466 2467 /* First, dump the table */ 2468 for (i = 0; i < num; i += num_per_reg) { 2469 reg = regs[o2i(off + i / num_per_reg)]; 2470 printf(" %s Arbitration Table: 0x%08x\n", name, reg); 2471 } 2472 /* And then, decode each entry */ 2473 for (i = 0; i < num; i += num_per_reg) { 2474 reg = regs[o2i(off + i / num_per_reg)]; 2475 for (j = 0; j < num_per_reg; j++) 2476 printf(" Phase[%d]: %d\n", j, reg); 2477 } 2478 } 2479 2480 static void 2481 pci_conf_print_vc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2482 { 2483 pcireg_t reg, n; 2484 int parbtab, parbsize; 2485 pcireg_t parbsel; 2486 int varbtab, varbsize; 2487 pcireg_t varbsel; 2488 int i, count; 2489 2490 printf("\n Virtual Channel Register\n"); 2491 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2492 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2493 count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2494 printf(" Extended VC Count: %d\n", count); 2495 n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2496 printf(" Low Priority Extended VC Count: %u\n", n); 2497 n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2498 printf(" Reference Clock: %s\n", 2499 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 2500 parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2501 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2502 2503 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 2504 printf(" Port VC Capability register 2: 0x%08x\n", reg); 2505 onoff("Hardware fixed arbitration scheme", 2506 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 2507 onoff("WRR arbitration with 32 phases", 2508 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 2509 onoff("WRR arbitration with 64 phases", 2510 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 2511 onoff("WRR arbitration with 128 phases", 2512 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 2513 varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 2514 printf(" VC Arbitration Table Offset: 0x%x\n", varbtab); 2515 2516 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 2517 printf(" Port VC Control register: 0x%04x\n", reg); 2518 varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 2519 printf(" VC Arbitration Select: 0x%x\n", varbsel); 2520 2521 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 2522 printf(" Port VC Status register: 0x%04x\n", reg); 2523 onoff("VC Arbitration Table Status", 2524 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 2525 2526 for (i = 0; i < count + 1; i++) { 2527 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 2528 printf(" VC number %d\n", i); 2529 printf(" VC Resource Capability Register: 0x%08x\n", reg); 2530 onoff(" Non-configurable Hardware fixed arbitration scheme", 2531 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 2532 onoff(" WRR arbitration with 32 phases", 2533 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 2534 onoff(" WRR arbitration with 64 phases", 2535 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 2536 onoff(" WRR arbitration with 128 phases", 2537 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 2538 onoff(" Time-based WRR arbitration with 128 phases", 2539 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 2540 onoff(" WRR arbitration with 256 phases", 2541 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 2542 onoff(" Advanced Packet Switching", 2543 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 2544 onoff(" Reject Snoop Transaction", 2545 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 2546 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 2547 printf(" Maximum Time Slots: %d\n", n); 2548 parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S; 2549 printf(" Port Arbitration Table offset: 0x%02x\n", 2550 parbtab); 2551 2552 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 2553 printf(" VC Resource Control Register: 0x%08x\n", reg); 2554 printf(" TC/VC Map: 0x%02x\n", 2555 (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 2556 /* 2557 * The load Port Arbitration Table bit is used to update 2558 * the Port Arbitration logic and it's always 0 on read, so 2559 * we don't print it. 2560 */ 2561 parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 2562 printf(" Port Arbitration Select: 0x%x\n", parbsel); 2563 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 2564 printf(" VC ID %d\n", n); 2565 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 2566 2567 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 2568 printf(" VC Resource Status Register: 0x%08x\n", reg); 2569 onoff(" Port Arbitration Table Status", 2570 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 2571 onoff(" VC Negotiation Pending", 2572 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 2573 2574 if ((parbtab != 0) && (parbsel != 0)) 2575 pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab, 2576 "Port", parbsel, parbsize); 2577 } 2578 2579 varbsize = 8; 2580 if ((varbtab != 0) && (varbsel != 0)) 2581 pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab, 2582 " VC", varbsel, varbsize); 2583 } 2584 2585 static const char * 2586 pci_conf_print_pwrbdgt_base_power(uint8_t reg) 2587 { 2588 2589 switch (reg) { 2590 case 0xf0: 2591 return "239W < x <= 250W"; 2592 case 0xf1: 2593 return "250W < x <= 275W"; 2594 case 0xf2: 2595 return "275W < x <= 300W"; 2596 default: 2597 break; 2598 } 2599 if (reg >= 0xf3) 2600 return "reserved for above 300W"; 2601 2602 return "Unknown"; 2603 } 2604 2605 static const char * 2606 pci_conf_print_pwrbdgt_data_scale(uint8_t reg) 2607 { 2608 2609 switch (reg) { 2610 case 0x00: 2611 return "1.0x"; 2612 case 0x01: 2613 return "0.1x"; 2614 case 0x02: 2615 return "0.01x"; 2616 case 0x03: 2617 return "0.001x"; 2618 default: 2619 return "wrong value!"; 2620 } 2621 } 2622 2623 static const char * 2624 pci_conf_print_pwrbdgt_type(uint8_t reg) 2625 { 2626 2627 switch (reg) { 2628 case 0x00: 2629 return "PME Aux"; 2630 case 0x01: 2631 return "Auxilary"; 2632 case 0x02: 2633 return "Idle"; 2634 case 0x03: 2635 return "Sustained"; 2636 case 0x04: 2637 return "Sustained (Emergency Power Reduction)"; 2638 case 0x05: 2639 return "Maximum (Emergency Power Reduction)"; 2640 case 0x07: 2641 return "Maximun"; 2642 default: 2643 return "Unknown"; 2644 } 2645 } 2646 2647 static const char * 2648 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 2649 { 2650 2651 switch (reg) { 2652 case 0x00: 2653 return "Power(12V)"; 2654 case 0x01: 2655 return "Power(3.3V)"; 2656 case 0x02: 2657 return "Power(1.5V or 1.8V)"; 2658 case 0x07: 2659 return "Thermal"; 2660 default: 2661 return "Unknown"; 2662 } 2663 } 2664 2665 static void 2666 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff) 2667 { 2668 pcireg_t reg; 2669 2670 printf("\n Power Budget Register\n"); 2671 2672 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 2673 printf(" Data Select register: 0x%08x\n", reg); 2674 2675 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 2676 printf(" Data register: 0x%08x\n", reg); 2677 printf(" Base Power: %s\n", 2678 pci_conf_print_pwrbdgt_base_power((uint8_t)reg)); 2679 printf(" Data Scale: %s\n", 2680 pci_conf_print_pwrbdgt_data_scale( 2681 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE)))); 2682 printf(" PM Sub State: 0x%hhx\n", 2683 (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 2684 printf(" PM State: D%u\n", 2685 (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 2686 printf(" Type: %s\n", 2687 pci_conf_print_pwrbdgt_type( 2688 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 2689 printf(" Power Rail: %s\n", 2690 pci_conf_print_pwrbdgt_pwrrail( 2691 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 2692 2693 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 2694 printf(" Power Budget Capability register: 0x%08x\n", reg); 2695 onoff("System Allocated", 2696 reg, PCI_PWRBDGT_CAP_SYSALLOC); 2697 } 2698 2699 static const char * 2700 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 2701 { 2702 2703 switch (type) { 2704 case 0x00: 2705 return "Configuration Space Element"; 2706 case 0x01: 2707 return "System Egress Port or internal sink (memory)"; 2708 case 0x02: 2709 return "Internal Root Complex Link"; 2710 default: 2711 return "Unknown"; 2712 } 2713 } 2714 2715 static void 2716 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int capoff, int extcapoff) 2717 { 2718 pcireg_t reg; 2719 unsigned char nent, linktype; 2720 int i; 2721 2722 printf("\n Root Complex Link Declaration\n"); 2723 2724 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 2725 printf(" Element Self Description Register: 0x%08x\n", reg); 2726 printf(" Element Type: %s\n", 2727 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 2728 nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 2729 printf(" Number of Link Entries: %hhu\n", nent); 2730 printf(" Component ID: %hhu\n", 2731 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 2732 printf(" Port Number: %hhu\n", 2733 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 2734 for (i = 0; i < nent; i++) { 2735 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 2736 printf(" Link Entry %d:\n", i + 1); 2737 printf(" Link Description Register: 0x%08x\n", reg); 2738 onoff(" Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID); 2739 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 2740 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 2741 "Configuration Space", "Memory-Mapped Space"); 2742 onoff(" Associated RCRB Header", reg, 2743 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 2744 printf(" Target Component ID: %hhu\n", 2745 (unsigned char)__SHIFTOUT(reg, 2746 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 2747 printf(" Target Port Number: %hhu\n", 2748 (unsigned char)__SHIFTOUT(reg, 2749 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 2750 2751 if (linktype == 0) { 2752 /* Memory-Mapped Space */ 2753 reg = regs[o2i(extcapoff 2754 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 2755 printf(" Link Address Low Register: 0x%08x\n", 2756 reg); 2757 reg = regs[o2i(extcapoff 2758 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 2759 printf(" Link Address High Register: 0x%08x\n", 2760 reg); 2761 } else { 2762 unsigned int nb; 2763 pcireg_t lo, hi; 2764 2765 /* Configuration Space */ 2766 lo = regs[o2i(extcapoff 2767 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 2768 printf(" Configuration Space Low Register: " 2769 "0x%08x\n", lo); 2770 hi = regs[o2i(extcapoff 2771 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 2772 printf(" Configuration Space High Register: " 2773 "0x%08x\n", hi); 2774 nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 2775 printf(" N: %u\n", nb); 2776 printf(" Func: %hhu\n", 2777 (unsigned char)__SHIFTOUT(lo, 2778 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 2779 printf(" Dev: %hhu\n", 2780 (unsigned char)__SHIFTOUT(lo, 2781 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 2782 printf(" Bus: %hhu\n", 2783 (unsigned char)__SHIFTOUT(lo, 2784 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 2785 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 2786 printf(" Configuration Space Base Address: " 2787 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 2788 } 2789 } 2790 } 2791 2792 /* XXX pci_conf_print_rclink_ctl_cap */ 2793 2794 static void 2795 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2796 { 2797 pcireg_t reg; 2798 2799 printf("\n Root Complex Event Collector Association\n"); 2800 2801 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 2802 printf(" Association Bitmap for Root Complex Integrated Devices:" 2803 " 0x%08x\n", reg); 2804 } 2805 2806 /* XXX pci_conf_print_mfvc_cap */ 2807 /* XXX pci_conf_print_vc2_cap */ 2808 /* XXX pci_conf_print_rcrb_cap */ 2809 /* XXX pci_conf_print_vendor_cap */ 2810 /* XXX pci_conf_print_cac_cap */ 2811 2812 static void 2813 pci_conf_print_acs_cap(const pcireg_t *regs, int capoff, int extcapoff) 2814 { 2815 pcireg_t reg, cap, ctl; 2816 unsigned int size, i; 2817 2818 printf("\n Access Control Services\n"); 2819 2820 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 2821 cap = reg & 0xffff; 2822 ctl = reg >> 16; 2823 printf(" ACS Capability register: 0x%08x\n", cap); 2824 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 2825 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 2826 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 2827 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 2828 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 2829 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 2830 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 2831 size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 2832 if (size == 0) 2833 size = 256; 2834 printf(" Egress Control Vector Size: %u\n", size); 2835 printf(" ACS Control register: 0x%08x\n", ctl); 2836 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 2837 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 2838 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 2839 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 2840 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 2841 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 2842 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 2843 2844 /* 2845 * If the P2P Egress Control Capability bit is 0, ignore the Egress 2846 * Control vector. 2847 */ 2848 if ((cap & PCI_ACS_CAP_E) == 0) 2849 return; 2850 for (i = 0; i < size; i += 32) 2851 printf(" Egress Control Vector [%u..%u]: 0x%08x\n", i + 31, 2852 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 2853 } 2854 2855 static void 2856 pci_conf_print_ari_cap(const pcireg_t *regs, int capoff, int extcapoff) 2857 { 2858 pcireg_t reg, cap, ctl; 2859 2860 printf("\n Alternative Routing-ID Interpretation Register\n"); 2861 2862 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2863 cap = reg & 0xffff; 2864 ctl = reg >> 16; 2865 printf(" Capability register: 0x%08x\n", cap); 2866 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 2867 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 2868 printf(" Next Function Number: %u\n", 2869 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 2870 printf(" Control register: 0x%08x\n", ctl); 2871 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 2872 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 2873 printf(" Function Group: %u\n", 2874 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 2875 } 2876 2877 static void 2878 pci_conf_print_ats_cap(const pcireg_t *regs, int capoff, int extcapoff) 2879 { 2880 pcireg_t reg, cap, ctl; 2881 unsigned int num; 2882 2883 printf("\n Address Translation Services\n"); 2884 2885 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2886 cap = reg & 0xffff; 2887 ctl = reg >> 16; 2888 printf(" Capability register: 0x%04x\n", cap); 2889 num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 2890 if (num == 0) 2891 num = 32; 2892 printf(" Invalidate Queue Depth: %u\n", num); 2893 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 2894 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 2895 2896 printf(" Control register: 0x%04x\n", ctl); 2897 printf(" Smallest Translation Unit: %u\n", 2898 (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU)); 2899 onoff("Enable", reg, PCI_ATS_CTL_EN); 2900 } 2901 2902 static void 2903 pci_conf_print_sernum_cap(const pcireg_t *regs, int capoff, int extcapoff) 2904 { 2905 pcireg_t lo, hi; 2906 2907 printf("\n Device Serial Number Register\n"); 2908 2909 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 2910 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 2911 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 2912 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 2913 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 2914 } 2915 2916 static void 2917 pci_conf_print_sriov_cap(const pcireg_t *regs, int capoff, int extcapoff) 2918 { 2919 char buf[sizeof("99999 MB")]; 2920 pcireg_t reg; 2921 pcireg_t total_vfs; 2922 int i; 2923 bool first; 2924 2925 printf("\n Single Root IO Virtualization Register\n"); 2926 2927 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 2928 printf(" Capabilities register: 0x%08x\n", reg); 2929 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 2930 onoff("ARI Capable Hierarchy Preserved", reg, 2931 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 2932 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 2933 printf(" VF Migration Interrupt Message Number: 0x%03x\n", 2934 (pcireg_t)__SHIFTOUT(reg, 2935 PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 2936 } 2937 2938 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 2939 printf(" Control register: 0x%04x\n", reg); 2940 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 2941 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 2942 onoff("VF Migration Interrupt Enable", reg, 2943 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 2944 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 2945 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 2946 2947 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 2948 printf(" Status register: 0x%04x\n", reg); 2949 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 2950 2951 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 2952 printf(" InitialVFs register: 0x%04x\n", reg); 2953 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 2954 printf(" TotalVFs register: 0x%04x\n", reg); 2955 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 2956 printf(" NumVFs register: 0x%04x\n", reg); 2957 2958 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 2959 printf(" Function Dependency Link register: 0x%04x\n", reg); 2960 2961 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 2962 printf(" First VF Offset register: 0x%04x\n", reg); 2963 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 2964 printf(" VF Stride register: 0x%04x\n", reg); 2965 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_DID)] >> 16; 2966 printf(" Device ID: 0x%04x\n", reg); 2967 2968 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 2969 printf(" Supported Page Sizes register: 0x%08x\n", reg); 2970 printf(" Supported Page Size:"); 2971 for (i = 0, first = true; i < 32; i++) { 2972 if (reg & __BIT(i)) { 2973 #ifdef _KERNEL 2974 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 2975 #else 2976 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 2977 HN_AUTOSCALE, 0); 2978 #endif 2979 printf("%s %s", first ? "" : ",", buf); 2980 first = false; 2981 } 2982 } 2983 printf("\n"); 2984 2985 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 2986 printf(" System Page Sizes register: 0x%08x\n", reg); 2987 printf(" Page Size: "); 2988 if (reg != 0) { 2989 #ifdef _KERNEL 2990 format_bytes(buf, sizeof(buf), 1LL << (ffs(reg) + 12)); 2991 #else 2992 humanize_number(buf, sizeof(buf), 1LL << (ffs(reg) + 12), "B", 2993 HN_AUTOSCALE, 0); 2994 #endif 2995 printf("%s", buf); 2996 } else { 2997 printf("unknown"); 2998 } 2999 printf("\n"); 3000 3001 for (i = 0; i < 6; i++) { 3002 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 3003 printf(" VF BAR%d register: 0x%08x\n", i, reg); 3004 } 3005 3006 if (total_vfs > 0) { 3007 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 3008 printf(" VF Migration State Array Offset register: 0x%08x\n", 3009 reg); 3010 printf(" VF Migration State Offset: 0x%08x\n", 3011 (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 3012 i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 3013 printf(" VF Migration State BIR: "); 3014 if (i >= 0 && i <= 5) { 3015 printf("BAR%d", i); 3016 } else { 3017 printf("unknown BAR (%d)", i); 3018 } 3019 printf("\n"); 3020 } 3021 } 3022 3023 /* XXX pci_conf_print_mriov_cap */ 3024 3025 static void 3026 pci_conf_print_multicast_cap(const pcireg_t *regs, int capoff, int extcapoff) 3027 { 3028 pcireg_t reg, cap, ctl; 3029 pcireg_t regl, regh; 3030 uint64_t addr; 3031 int n; 3032 3033 printf("\n Multicast\n"); 3034 3035 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 3036 cap = reg & 0xffff; 3037 ctl = reg >> 16; 3038 printf(" Capability Register: 0x%04x\n", cap); 3039 printf(" Max Group: %u\n", 3040 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 3041 3042 /* Endpoint Only */ 3043 n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 3044 if (n > 0) 3045 printf(" Windw Size Requested: %d\n", 1 << (n - 1)); 3046 3047 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 3048 3049 printf(" Control Register: 0x%04x\n", ctl); 3050 printf(" Num Group: %u\n", 3051 (unsigned int)__SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 3052 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 3053 3054 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 3055 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 3056 printf(" Base Address Register 0: 0x%08x\n", regl); 3057 printf(" Base Address Register 1: 0x%08x\n", regh); 3058 printf(" Index Position: %u\n", 3059 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 3060 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 3061 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 3062 3063 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 3064 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 3065 printf(" Receive Register 0: 0x%08x\n", regl); 3066 printf(" Receive Register 1: 0x%08x\n", regh); 3067 3068 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 3069 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 3070 printf(" Block All Register 0: 0x%08x\n", regl); 3071 printf(" Block All Register 1: 0x%08x\n", regh); 3072 3073 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 3074 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 3075 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 3076 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 3077 3078 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 3079 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 3080 printf(" Overlay BAR 0: 0x%08x\n", regl); 3081 printf(" Overlay BAR 1: 0x%08x\n", regh); 3082 3083 n = regl & PCI_MCAST_OVERLAYL_SIZE; 3084 printf(" Overlay Size: "); 3085 if (n >= 6) 3086 printf("%d\n", n); 3087 else 3088 printf("off\n"); 3089 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 3090 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 3091 } 3092 3093 static void 3094 pci_conf_print_page_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3095 { 3096 pcireg_t reg, ctl, sta; 3097 3098 printf("\n Page Request\n"); 3099 3100 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 3101 ctl = reg & 0xffff; 3102 sta = reg >> 16; 3103 printf(" Control Register: 0x%04x\n", ctl); 3104 onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E); 3105 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 3106 3107 printf(" Status Register: 0x%04x\n", sta); 3108 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 3109 onoff("Unexpected Page Request Group Index", reg, 3110 PCI_PAGE_REQ_STA_UPRGI); 3111 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 3112 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 3113 3114 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 3115 printf(" Outstanding Page Request Capacity: %u\n", reg); 3116 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 3117 printf(" Outstanding Page Request Allocation: %u\n", reg); 3118 } 3119 3120 /* XXX pci_conf_print_amd_cap */ 3121 3122 #define MEM_PBUFSIZE sizeof("999GB") 3123 3124 static void 3125 pci_conf_print_resizbar_cap(const pcireg_t *regs, int capoff, int extcapoff) 3126 { 3127 pcireg_t cap, ctl; 3128 unsigned int bars, i, n; 3129 char pbuf[MEM_PBUFSIZE]; 3130 3131 printf("\n Resizable BAR\n"); 3132 3133 /* Get Number of Resizable BARs */ 3134 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))]; 3135 bars = __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR); 3136 printf(" Number of Resizable BARs: "); 3137 if (bars <= 6) 3138 printf("%u\n", bars); 3139 else { 3140 printf("incorrect (%u)\n", bars); 3141 return; 3142 } 3143 3144 for (n = 0; n < 6; n++) { 3145 cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))]; 3146 printf(" Capability register(%u): 0x%08x\n", n, cap); 3147 if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0) 3148 continue; /* Not Used */ 3149 printf(" Acceptable BAR sizes:"); 3150 for (i = 4; i <= 23; i++) { 3151 if ((cap & (1 << i)) != 0) { 3152 humanize_number(pbuf, MEM_PBUFSIZE, 3153 (int64_t)1024 * 1024 << (i - 4), "B", 3154 #ifdef _KERNEL 3155 1); 3156 #else 3157 HN_AUTOSCALE, HN_NOSPACE); 3158 #endif 3159 printf(" %s", pbuf); 3160 } 3161 } 3162 printf("\n"); 3163 3164 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))]; 3165 printf(" Control register(%u): 0x%08x\n", n, ctl); 3166 printf(" BAR Index: %u\n", 3167 (unsigned int)__SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX)); 3168 humanize_number(pbuf, MEM_PBUFSIZE, 3169 (int64_t)1024 * 1024 3170 << __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ), 3171 "B", 3172 #ifdef _KERNEL 3173 1); 3174 #else 3175 HN_AUTOSCALE, HN_NOSPACE); 3176 #endif 3177 printf(" BAR Size: %s\n", pbuf); 3178 } 3179 } 3180 3181 static void 3182 pci_conf_print_dpa_cap(const pcireg_t *regs, int capoff, int extcapoff) 3183 { 3184 pcireg_t reg; 3185 unsigned int substmax, i; 3186 3187 printf("\n Dynamic Power Allocation\n"); 3188 3189 reg = regs[o2i(extcapoff + PCI_DPA_CAP)]; 3190 printf(" Capability register: 0x%08x\n", reg); 3191 substmax = __SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX); 3192 printf(" Substate Max: %u\n", substmax); 3193 printf(" Transition Latency Unit: "); 3194 switch (__SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) { 3195 case 0: 3196 printf("1ms\n"); 3197 break; 3198 case 1: 3199 printf("10ms\n"); 3200 break; 3201 case 2: 3202 printf("100ms\n"); 3203 break; 3204 default: 3205 printf("reserved\n"); 3206 break; 3207 } 3208 printf(" Power Allocation Scale: "); 3209 switch (__SHIFTOUT(reg, PCI_DPA_CAP_PAS)) { 3210 case 0: 3211 printf("10.0x\n"); 3212 break; 3213 case 1: 3214 printf("1.0x\n"); 3215 break; 3216 case 2: 3217 printf("0.1x\n"); 3218 break; 3219 case 3: 3220 printf("0.01x\n"); 3221 break; 3222 } 3223 printf(" Transition Latency Value 0: %u\n", 3224 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY0)); 3225 printf(" Transition Latency Value 1: %u\n", 3226 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY1)); 3227 3228 reg = regs[o2i(extcapoff + PCI_DPA_LATIND)]; 3229 printf(" Latency Indicatior register: 0x%08x\n", reg); 3230 3231 reg = regs[o2i(extcapoff + PCI_DPA_CS)]; 3232 printf(" Status register: 0x%04x\n", reg & 0xffff); 3233 printf(" Substate Status: 0x%02x\n", 3234 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT)); 3235 onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN); 3236 printf(" Control register: 0x%04x\n", reg >> 16); 3237 printf(" Substate Control: 0x%02x\n", 3238 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL)); 3239 3240 for (i = 0; i <= substmax; i++) 3241 printf(" Substate Power Allocation register %d: 0x%02x\n", 3242 i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff)); 3243 } 3244 3245 static const char * 3246 pci_conf_print_tph_req_cap_sttabloc(unsigned char val) 3247 { 3248 3249 switch (val) { 3250 case 0x0: 3251 return "Not Present"; 3252 case 0x1: 3253 return "in the TPH Requester Capability Structure"; 3254 case 0x2: 3255 return "in the MSI-X Table"; 3256 default: 3257 return "Unknown"; 3258 } 3259 } 3260 3261 static void 3262 pci_conf_print_tph_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3263 { 3264 pcireg_t reg; 3265 int size, i, j; 3266 3267 printf("\n TPH Requester Extended Capability\n"); 3268 3269 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 3270 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 3271 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 3272 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 3273 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 3274 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 3275 printf(" ST Table Location: %s\n", 3276 pci_conf_print_tph_req_cap_sttabloc( 3277 (unsigned char)__SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC))); 3278 size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 3279 printf(" ST Table Size: %d\n", size); 3280 for (i = 0; i < size ; i += 2) { 3281 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 3282 for (j = 0; j < 2 ; j++) { 3283 uint32_t entry = reg; 3284 3285 if (j != 0) 3286 entry >>= 16; 3287 entry &= 0xffff; 3288 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 3289 i + j, entry); 3290 } 3291 } 3292 } 3293 3294 static void 3295 pci_conf_print_ltr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3296 { 3297 pcireg_t reg; 3298 3299 printf("\n Latency Tolerance Reporting\n"); 3300 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)] & 0xffff; 3301 printf(" Max Snoop Latency Register: 0x%04x\n", reg); 3302 printf(" Max Snoop LatencyValue: %u\n", 3303 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL)); 3304 printf(" Max Snoop LatencyScale: %uns\n", 3305 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE))); 3306 reg = regs[o2i(extcapoff + PCI_LTR_MAXNOSNOOPLAT)] >> 16; 3307 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg); 3308 printf(" Max No-Snoop LatencyValue: %u\n", 3309 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL)); 3310 printf(" Max No-Snoop LatencyScale: %uns\n", 3311 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE))); 3312 } 3313 3314 static void 3315 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int capoff, int extcapoff) 3316 { 3317 int pcie_capoff; 3318 pcireg_t reg; 3319 int i, maxlinkwidth; 3320 3321 printf("\n Secondary PCI Express Register\n"); 3322 3323 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3324 printf(" Link Control 3 register: 0x%08x\n", reg); 3325 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3326 onoff("Link Equalization Request Interrupt Enable", 3327 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3328 printf(" Enable Lower SKP OS Generation Vector:"); 3329 pci_print_pcie_linkspeedvector( 3330 __SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV)); 3331 printf("\n"); 3332 3333 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3334 printf(" Lane Error Status register: 0x%08x\n", reg); 3335 3336 /* Get Max Link Width */ 3337 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)){ 3338 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3339 maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3340 } else { 3341 printf("error: falied to get PCIe capablity\n"); 3342 return; 3343 } 3344 for (i = 0; i < maxlinkwidth; i++) { 3345 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3346 if (i % 2 != 0) 3347 reg >>= 16; 3348 else 3349 reg &= 0xffff; 3350 printf(" Equalization Control Register (Link %d): 0x%04x\n", 3351 i, reg); 3352 printf(" Downstream Port Transmit Preset: 0x%x\n", 3353 (pcireg_t)__SHIFTOUT(reg, 3354 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3355 printf(" Downstream Port Receive Hint: 0x%x\n", 3356 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3357 printf(" Upstream Port Transmit Preset: 0x%x\n", 3358 (pcireg_t)__SHIFTOUT(reg, 3359 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3360 printf(" Upstream Port Receive Hint: 0x%x\n", 3361 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3362 } 3363 } 3364 3365 /* XXX pci_conf_print_pmux_cap */ 3366 3367 static void 3368 pci_conf_print_pasid_cap(const pcireg_t *regs, int capoff, int extcapoff) 3369 { 3370 pcireg_t reg, cap, ctl; 3371 unsigned int num; 3372 3373 printf("\n Process Address Space ID\n"); 3374 3375 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3376 cap = reg & 0xffff; 3377 ctl = reg >> 16; 3378 printf(" PASID Capability Register: 0x%04x\n", cap); 3379 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3380 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3381 num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3382 printf(" Max PASID Width: %u\n", num); 3383 3384 printf(" PASID Control Register: 0x%04x\n", ctl); 3385 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3386 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3387 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 3388 } 3389 3390 static void 3391 pci_conf_print_lnr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3392 { 3393 pcireg_t reg, cap, ctl; 3394 unsigned int num; 3395 3396 printf("\n LN Requester\n"); 3397 3398 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 3399 cap = reg & 0xffff; 3400 ctl = reg >> 16; 3401 printf(" LNR Capability register: 0x%04x\n", cap); 3402 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 3403 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 3404 num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 3405 printf(" LNR Registration MAX: %u\n", num); 3406 3407 printf(" LNR Control register: 0x%04x\n", ctl); 3408 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 3409 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 3410 num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 3411 printf(" LNR Registration Limit: %u\n", num); 3412 } 3413 3414 /* XXX pci_conf_print_dpc_cap */ 3415 3416 static int 3417 pci_conf_l1pm_cap_tposcale(unsigned char scale) 3418 { 3419 3420 /* Return scale in us */ 3421 switch (scale) { 3422 case 0x0: 3423 return 2; 3424 case 0x1: 3425 return 10; 3426 case 0x2: 3427 return 100; 3428 default: 3429 return -1; 3430 } 3431 } 3432 3433 static void 3434 pci_conf_print_l1pm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3435 { 3436 pcireg_t reg; 3437 int scale, val; 3438 3439 printf("\n L1 PM Substates\n"); 3440 3441 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 3442 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 3443 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 3444 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 3445 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 3446 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 3447 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 3448 printf(" Port Common Mode Restore Time: %uus\n", 3449 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 3450 scale = pci_conf_l1pm_cap_tposcale( 3451 __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 3452 val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 3453 printf(" Port T_POWER_ON: "); 3454 if (scale == -1) 3455 printf("unknown\n"); 3456 else 3457 printf("%dus\n", val * scale); 3458 3459 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 3460 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 3461 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 3462 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 3463 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 3464 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 3465 printf(" Common Mode Restore Time: %uus\n", 3466 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 3467 scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 3468 val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 3469 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 3470 3471 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 3472 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 3473 scale = pci_conf_l1pm_cap_tposcale( 3474 __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 3475 val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 3476 printf(" T_POWER_ON: "); 3477 if (scale == -1) 3478 printf("unknown\n"); 3479 else 3480 printf("%dus\n", val * scale); 3481 } 3482 3483 static void 3484 pci_conf_print_ptm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3485 { 3486 pcireg_t reg; 3487 uint32_t val; 3488 3489 printf("\n Precision Time Management\n"); 3490 3491 reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; 3492 printf(" PTM Capability register: 0x%08x\n", reg); 3493 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ); 3494 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP); 3495 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT); 3496 printf(" Local Clock Granularity: "); 3497 val = __SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL); 3498 switch (val) { 3499 case 0: 3500 printf("Not implemented\n"); 3501 break; 3502 case 0xffff: 3503 printf("> 254ns\n"); 3504 break; 3505 default: 3506 printf("%uns\n", val); 3507 break; 3508 } 3509 3510 reg = regs[o2i(extcapoff + PCI_PTM_CTL)]; 3511 printf(" PTM Control register: 0x%08x\n", reg); 3512 onoff("PTM Enable", reg, PCI_PTM_CTL_EN); 3513 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL); 3514 printf(" Effective Granularity: "); 3515 val = __SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL); 3516 switch (val) { 3517 case 0: 3518 printf("Unknown\n"); 3519 break; 3520 case 0xffff: 3521 printf("> 254ns\n"); 3522 break; 3523 default: 3524 printf("%uns\n", val); 3525 break; 3526 } 3527 } 3528 3529 /* XXX pci_conf_print_mpcie_cap */ 3530 /* XXX pci_conf_print_frsq_cap */ 3531 /* XXX pci_conf_print_rtr_cap */ 3532 /* XXX pci_conf_print_desigvndsp_cap */ 3533 /* XXX pci_conf_print_vf_resizbar_cap */ 3534 3535 #undef MS 3536 #undef SM 3537 #undef RW 3538 3539 static struct { 3540 pcireg_t cap; 3541 const char *name; 3542 void (*printfunc)(const pcireg_t *, int, int); 3543 } pci_extcaptab[] = { 3544 { 0, "reserved", 3545 NULL }, 3546 { PCI_EXTCAP_AER, "Advanced Error Reporting", 3547 pci_conf_print_aer_cap }, 3548 { PCI_EXTCAP_VC, "Virtual Channel", 3549 pci_conf_print_vc_cap }, 3550 { PCI_EXTCAP_SERNUM, "Device Serial Number", 3551 pci_conf_print_sernum_cap }, 3552 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 3553 pci_conf_print_pwrbdgt_cap }, 3554 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 3555 pci_conf_print_rclink_dcl_cap }, 3556 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 3557 NULL }, 3558 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 3559 pci_conf_print_rcec_assoc_cap }, 3560 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 3561 NULL }, 3562 { PCI_EXTCAP_VC2, "Virtual Channel", 3563 NULL }, 3564 { PCI_EXTCAP_RCRB, "RCRB Header", 3565 NULL }, 3566 { PCI_EXTCAP_VENDOR, "Vendor Unique", 3567 NULL }, 3568 { PCI_EXTCAP_CAC, "Configuration Access Correction", 3569 NULL }, 3570 { PCI_EXTCAP_ACS, "Access Control Services", 3571 pci_conf_print_acs_cap }, 3572 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 3573 pci_conf_print_ari_cap }, 3574 { PCI_EXTCAP_ATS, "Address Translation Services", 3575 pci_conf_print_ats_cap }, 3576 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 3577 pci_conf_print_sriov_cap }, 3578 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 3579 NULL }, 3580 { PCI_EXTCAP_MCAST, "Multicast", 3581 pci_conf_print_multicast_cap }, 3582 { PCI_EXTCAP_PAGE_REQ, "Page Request", 3583 pci_conf_print_page_req_cap }, 3584 { PCI_EXTCAP_AMD, "Reserved for AMD", 3585 NULL }, 3586 { PCI_EXTCAP_RESIZBAR, "Resizable BAR", 3587 pci_conf_print_resizbar_cap }, 3588 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 3589 pci_conf_print_dpa_cap }, 3590 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 3591 pci_conf_print_tph_req_cap }, 3592 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 3593 pci_conf_print_ltr_cap }, 3594 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 3595 pci_conf_print_sec_pcie_cap }, 3596 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 3597 NULL }, 3598 { PCI_EXTCAP_PASID, "Process Address Space ID", 3599 pci_conf_print_pasid_cap }, 3600 { PCI_EXTCAP_LN_REQ, "LN Requester", 3601 pci_conf_print_lnr_cap }, 3602 { PCI_EXTCAP_DPC, "Downstream Port Containment", 3603 NULL }, 3604 { PCI_EXTCAP_L1PM, "L1 PM Substates", 3605 pci_conf_print_l1pm_cap }, 3606 { PCI_EXTCAP_PTM, "Precision Time Management", 3607 pci_conf_print_ptm_cap }, 3608 { PCI_EXTCAP_MPCIE, "M-PCIe", 3609 NULL }, 3610 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 3611 NULL }, 3612 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 3613 NULL }, 3614 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 3615 NULL }, 3616 { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs", 3617 NULL }, 3618 }; 3619 3620 static int 3621 pci_conf_find_extcap(const pcireg_t *regs, int capoff, unsigned int capid, 3622 int *offsetp) 3623 { 3624 int off; 3625 pcireg_t rval; 3626 3627 for (off = PCI_EXTCAPLIST_BASE; 3628 off != 0; 3629 off = PCI_EXTCAPLIST_NEXT(rval)) { 3630 rval = regs[o2i(off)]; 3631 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 3632 if (offsetp != NULL) 3633 *offsetp = off; 3634 return 1; 3635 } 3636 } 3637 return 0; 3638 } 3639 3640 static void 3641 pci_conf_print_extcaplist( 3642 #ifdef _KERNEL 3643 pci_chipset_tag_t pc, pcitag_t tag, 3644 #endif 3645 const pcireg_t *regs, int capoff) 3646 { 3647 int off; 3648 pcireg_t foundcap; 3649 pcireg_t rval; 3650 bool foundtable[__arraycount(pci_extcaptab)]; 3651 unsigned int i; 3652 3653 /* Check Extended capability structure */ 3654 off = PCI_EXTCAPLIST_BASE; 3655 rval = regs[o2i(off)]; 3656 if (rval == 0xffffffff || rval == 0) 3657 return; 3658 3659 /* Clear table */ 3660 for (i = 0; i < __arraycount(pci_extcaptab); i++) 3661 foundtable[i] = false; 3662 3663 /* Print extended capability register's offset and the type first */ 3664 for (;;) { 3665 printf(" Extended Capability Register at 0x%02x\n", off); 3666 3667 foundcap = PCI_EXTCAPLIST_CAP(rval); 3668 printf(" type: 0x%04x (", foundcap); 3669 if (foundcap < __arraycount(pci_extcaptab)) { 3670 printf("%s)\n", pci_extcaptab[foundcap].name); 3671 /* Mark as found */ 3672 foundtable[foundcap] = true; 3673 } else 3674 printf("unknown)\n"); 3675 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 3676 3677 off = PCI_EXTCAPLIST_NEXT(rval); 3678 if (off == 0) 3679 break; 3680 else if (off <= PCI_CONF_SIZE) { 3681 printf(" next pointer: 0x%03x (incorrect)\n", off); 3682 return; 3683 } 3684 rval = regs[o2i(off)]; 3685 } 3686 3687 /* 3688 * And then, print the detail of each capability registers 3689 * in capability value's order. 3690 */ 3691 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 3692 if (foundtable[i] == false) 3693 continue; 3694 3695 /* 3696 * The type was found. Search capability list again and 3697 * print all capabilities that the capabiliy type is 3698 * the same. 3699 */ 3700 if (pci_conf_find_extcap(regs, capoff, i, &off) == 0) 3701 continue; 3702 rval = regs[o2i(off)]; 3703 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 3704 || (pci_extcaptab[i].printfunc == NULL)) 3705 continue; 3706 3707 pci_extcaptab[i].printfunc(regs, capoff, off); 3708 3709 } 3710 } 3711 3712 /* Print the Secondary Status Register. */ 3713 static void 3714 pci_conf_print_ssr(pcireg_t rval) 3715 { 3716 pcireg_t devsel; 3717 3718 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 3719 onoff("66 MHz capable", rval, __BIT(5)); 3720 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 3721 onoff("Fast back-to-back capable", rval, __BIT(7)); 3722 onoff("Data parity error detected", rval, __BIT(8)); 3723 3724 printf(" DEVSEL timing: "); 3725 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 3726 switch (devsel) { 3727 case 0: 3728 printf("fast"); 3729 break; 3730 case 1: 3731 printf("medium"); 3732 break; 3733 case 2: 3734 printf("slow"); 3735 break; 3736 default: 3737 printf("unknown/reserved"); /* XXX */ 3738 break; 3739 } 3740 printf(" (0x%x)\n", devsel); 3741 3742 onoff("Signalled target abort", rval, __BIT(11)); 3743 onoff("Received target abort", rval, __BIT(12)); 3744 onoff("Received master abort", rval, __BIT(13)); 3745 onoff("Received system error", rval, __BIT(14)); 3746 onoff("Detected parity error", rval, __BIT(15)); 3747 } 3748 3749 static void 3750 pci_conf_print_type0( 3751 #ifdef _KERNEL 3752 pci_chipset_tag_t pc, pcitag_t tag, 3753 #endif 3754 const pcireg_t *regs 3755 #ifdef _KERNEL 3756 , int sizebars 3757 #endif 3758 ) 3759 { 3760 int off, width; 3761 pcireg_t rval; 3762 3763 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 3764 #ifdef _KERNEL 3765 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3766 #else 3767 width = pci_conf_print_bar(regs, off, NULL); 3768 #endif 3769 } 3770 3771 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 3772 3773 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 3774 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 3775 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 3776 3777 /* XXX */ 3778 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 3779 3780 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3781 printf(" Capability list pointer: 0x%02x\n", 3782 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 3783 else 3784 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 3785 3786 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 3787 3788 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3789 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 3790 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 3791 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 3792 switch (PCI_INTERRUPT_PIN(rval)) { 3793 case PCI_INTERRUPT_PIN_NONE: 3794 printf("(none)"); 3795 break; 3796 case PCI_INTERRUPT_PIN_A: 3797 printf("(pin A)"); 3798 break; 3799 case PCI_INTERRUPT_PIN_B: 3800 printf("(pin B)"); 3801 break; 3802 case PCI_INTERRUPT_PIN_C: 3803 printf("(pin C)"); 3804 break; 3805 case PCI_INTERRUPT_PIN_D: 3806 printf("(pin D)"); 3807 break; 3808 default: 3809 printf("(? ? ?)"); 3810 break; 3811 } 3812 printf("\n"); 3813 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 3814 } 3815 3816 static void 3817 pci_conf_print_type1( 3818 #ifdef _KERNEL 3819 pci_chipset_tag_t pc, pcitag_t tag, 3820 #endif 3821 const pcireg_t *regs 3822 #ifdef _KERNEL 3823 , int sizebars 3824 #endif 3825 ) 3826 { 3827 int off, width; 3828 pcireg_t rval; 3829 uint32_t base, limit; 3830 uint32_t base_h, limit_h; 3831 uint64_t pbase, plimit; 3832 int use_upper; 3833 3834 /* 3835 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 3836 * Bridge chip documentation, and may not be correct with 3837 * respect to various standards. (XXX) 3838 */ 3839 3840 for (off = 0x10; off < 0x18; off += width) { 3841 #ifdef _KERNEL 3842 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3843 #else 3844 width = pci_conf_print_bar(regs, off, NULL); 3845 #endif 3846 } 3847 3848 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 3849 printf(" Primary bus number: 0x%02x\n", 3850 PCI_BRIDGE_BUS_PRIMARY(rval)); 3851 printf(" Secondary bus number: 0x%02x\n", 3852 PCI_BRIDGE_BUS_SECONDARY(rval)); 3853 printf(" Subordinate bus number: 0x%02x\n", 3854 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 3855 printf(" Secondary bus latency timer: 0x%02x\n", 3856 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 3857 3858 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 3859 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 3860 3861 /* I/O region */ 3862 printf(" I/O region:\n"); 3863 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 3864 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 3865 if (PCI_BRIDGE_IO_32BITS(rval)) 3866 use_upper = 1; 3867 else 3868 use_upper = 0; 3869 onoff("32bit I/O", rval, use_upper); 3870 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 3871 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 3872 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 3873 limit |= 0x00000fff; 3874 3875 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 3876 base_h = (rval >> 0) & 0xffff; 3877 limit_h = (rval >> 16) & 0xffff; 3878 printf(" base upper 16 bits register: 0x%04x\n", base_h); 3879 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 3880 3881 if (use_upper == 1) { 3882 base |= base_h << 16; 3883 limit |= limit_h << 16; 3884 } 3885 if (base < limit) { 3886 if (use_upper == 1) 3887 printf(" range: 0x%08x-0x%08x\n", base, limit); 3888 else 3889 printf(" range: 0x%04x-0x%04x\n", base, limit); 3890 } else 3891 printf(" range: not set\n"); 3892 3893 /* Non-prefetchable memory region */ 3894 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 3895 printf(" Memory region:\n"); 3896 printf(" base register: 0x%04x\n", 3897 (rval >> 0) & 0xffff); 3898 printf(" limit register: 0x%04x\n", 3899 (rval >> 16) & 0xffff); 3900 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 3901 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 3902 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 3903 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 3904 if (base < limit) 3905 printf(" range: 0x%08x-0x%08x\n", base, limit); 3906 else 3907 printf(" range: not set\n"); 3908 3909 /* Prefetchable memory region */ 3910 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 3911 printf(" Prefetchable memory region:\n"); 3912 printf(" base register: 0x%04x\n", 3913 (rval >> 0) & 0xffff); 3914 printf(" limit register: 0x%04x\n", 3915 (rval >> 16) & 0xffff); 3916 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 3917 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 3918 printf(" base upper 32 bits register: 0x%08x\n", 3919 base_h); 3920 printf(" limit upper 32 bits register: 0x%08x\n", 3921 limit_h); 3922 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 3923 use_upper = 1; 3924 else 3925 use_upper = 0; 3926 onoff("64bit memory address", rval, use_upper); 3927 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 3928 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 3929 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 3930 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 3931 if (use_upper == 1) { 3932 pbase |= (uint64_t)base_h << 32; 3933 plimit |= (uint64_t)limit_h << 32; 3934 } 3935 if (pbase < plimit) { 3936 if (use_upper == 1) 3937 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 3938 "\n", pbase, plimit); 3939 else 3940 printf(" range: 0x%08x-0x%08x\n", 3941 (uint32_t)pbase, (uint32_t)plimit); 3942 } else 3943 printf(" range: not set\n"); 3944 3945 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3946 printf(" Capability list pointer: 0x%02x\n", 3947 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 3948 else 3949 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 3950 3951 /* XXX */ 3952 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 3953 3954 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3955 printf(" Interrupt line: 0x%02x\n", 3956 (rval >> 0) & 0xff); 3957 printf(" Interrupt pin: 0x%02x ", 3958 (rval >> 8) & 0xff); 3959 switch ((rval >> 8) & 0xff) { 3960 case PCI_INTERRUPT_PIN_NONE: 3961 printf("(none)"); 3962 break; 3963 case PCI_INTERRUPT_PIN_A: 3964 printf("(pin A)"); 3965 break; 3966 case PCI_INTERRUPT_PIN_B: 3967 printf("(pin B)"); 3968 break; 3969 case PCI_INTERRUPT_PIN_C: 3970 printf("(pin C)"); 3971 break; 3972 case PCI_INTERRUPT_PIN_D: 3973 printf("(pin D)"); 3974 break; 3975 default: 3976 printf("(? ? ?)"); 3977 break; 3978 } 3979 printf("\n"); 3980 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 3981 & PCI_BRIDGE_CONTROL_MASK; 3982 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 3983 onoff("Parity error response", rval, 0x0001); 3984 onoff("Secondary SERR forwarding", rval, 0x0002); 3985 onoff("ISA enable", rval, 0x0004); 3986 onoff("VGA enable", rval, 0x0008); 3987 onoff("Master abort reporting", rval, 0x0020); 3988 onoff("Secondary bus reset", rval, 0x0040); 3989 onoff("Fast back-to-back capable", rval, 0x0080); 3990 } 3991 3992 static void 3993 pci_conf_print_type2( 3994 #ifdef _KERNEL 3995 pci_chipset_tag_t pc, pcitag_t tag, 3996 #endif 3997 const pcireg_t *regs 3998 #ifdef _KERNEL 3999 , int sizebars 4000 #endif 4001 ) 4002 { 4003 pcireg_t rval; 4004 4005 /* 4006 * XXX these need to be printed in more detail, need to be 4007 * XXX checked against specs/docs, etc. 4008 * 4009 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 4010 * controller chip documentation, and may not be correct with 4011 * respect to various standards. (XXX) 4012 */ 4013 4014 #ifdef _KERNEL 4015 pci_conf_print_bar(pc, tag, regs, 0x10, 4016 "CardBus socket/ExCA registers", sizebars); 4017 #else 4018 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 4019 #endif 4020 4021 /* Capability list pointer and secondary status register */ 4022 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 4023 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4024 printf(" Capability list pointer: 0x%02x\n", 4025 PCI_CAPLIST_PTR(rval)); 4026 else 4027 printf(" Reserved @ 0x14: 0x%04x\n", 4028 (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0))); 4029 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 4030 4031 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4032 printf(" PCI bus number: 0x%02x\n", 4033 (rval >> 0) & 0xff); 4034 printf(" CardBus bus number: 0x%02x\n", 4035 (rval >> 8) & 0xff); 4036 printf(" Subordinate bus number: 0x%02x\n", 4037 (rval >> 16) & 0xff); 4038 printf(" CardBus latency timer: 0x%02x\n", 4039 (rval >> 24) & 0xff); 4040 4041 /* XXX Print more prettily */ 4042 printf(" CardBus memory region 0:\n"); 4043 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 4044 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 4045 printf(" CardBus memory region 1:\n"); 4046 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 4047 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 4048 printf(" CardBus I/O region 0:\n"); 4049 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 4050 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 4051 printf(" CardBus I/O region 1:\n"); 4052 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 4053 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 4054 4055 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4056 printf(" Interrupt line: 0x%02x\n", 4057 (rval >> 0) & 0xff); 4058 printf(" Interrupt pin: 0x%02x ", 4059 (rval >> 8) & 0xff); 4060 switch ((rval >> 8) & 0xff) { 4061 case PCI_INTERRUPT_PIN_NONE: 4062 printf("(none)"); 4063 break; 4064 case PCI_INTERRUPT_PIN_A: 4065 printf("(pin A)"); 4066 break; 4067 case PCI_INTERRUPT_PIN_B: 4068 printf("(pin B)"); 4069 break; 4070 case PCI_INTERRUPT_PIN_C: 4071 printf("(pin C)"); 4072 break; 4073 case PCI_INTERRUPT_PIN_D: 4074 printf("(pin D)"); 4075 break; 4076 default: 4077 printf("(? ? ?)"); 4078 break; 4079 } 4080 printf("\n"); 4081 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 4082 printf(" Bridge control register: 0x%04x\n", rval); 4083 onoff("Parity error response", rval, __BIT(0)); 4084 onoff("SERR# enable", rval, __BIT(1)); 4085 onoff("ISA enable", rval, __BIT(2)); 4086 onoff("VGA enable", rval, __BIT(3)); 4087 onoff("Master abort mode", rval, __BIT(5)); 4088 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 4089 onoff("Functional interrupts routed by ExCA registers", rval, 4090 __BIT(7)); 4091 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 4092 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 4093 onoff("Write posting enable", rval, __BIT(10)); 4094 4095 rval = regs[o2i(0x40)]; 4096 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4097 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4098 4099 #ifdef _KERNEL 4100 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 4101 sizebars); 4102 #else 4103 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 4104 #endif 4105 } 4106 4107 void 4108 pci_conf_print( 4109 #ifdef _KERNEL 4110 pci_chipset_tag_t pc, pcitag_t tag, 4111 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 4112 #else 4113 int pcifd, u_int bus, u_int dev, u_int func 4114 #endif 4115 ) 4116 { 4117 pcireg_t regs[o2i(PCI_EXTCONF_SIZE)]; 4118 int off, capoff, endoff, hdrtype; 4119 const char *type_name; 4120 #ifdef _KERNEL 4121 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, 4122 int); 4123 int sizebars; 4124 #else 4125 void (*type_printfn)(const pcireg_t *); 4126 #endif 4127 4128 printf("PCI configuration registers:\n"); 4129 4130 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 4131 #ifdef _KERNEL 4132 regs[o2i(off)] = pci_conf_read(pc, tag, off); 4133 #else 4134 if (pcibus_conf_read(pcifd, bus, dev, func, off, 4135 ®s[o2i(off)]) == -1) 4136 regs[o2i(off)] = 0; 4137 #endif 4138 } 4139 4140 #ifdef _KERNEL 4141 sizebars = 1; 4142 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 4143 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 4144 sizebars = 0; 4145 #endif 4146 4147 /* common header */ 4148 printf(" Common header:\n"); 4149 pci_conf_print_regs(regs, 0, 16); 4150 4151 printf("\n"); 4152 #ifdef _KERNEL 4153 pci_conf_print_common(pc, tag, regs); 4154 #else 4155 pci_conf_print_common(regs); 4156 #endif 4157 printf("\n"); 4158 4159 /* type-dependent header */ 4160 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 4161 switch (hdrtype) { /* XXX make a table, eventually */ 4162 case 0: 4163 /* Standard device header */ 4164 type_name = "\"normal\" device"; 4165 type_printfn = &pci_conf_print_type0; 4166 capoff = PCI_CAPLISTPTR_REG; 4167 endoff = 64; 4168 break; 4169 case 1: 4170 /* PCI-PCI bridge header */ 4171 type_name = "PCI-PCI bridge"; 4172 type_printfn = &pci_conf_print_type1; 4173 capoff = PCI_CAPLISTPTR_REG; 4174 endoff = 64; 4175 break; 4176 case 2: 4177 /* PCI-CardBus bridge header */ 4178 type_name = "PCI-CardBus bridge"; 4179 type_printfn = &pci_conf_print_type2; 4180 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 4181 endoff = 72; 4182 break; 4183 default: 4184 type_name = NULL; 4185 type_printfn = 0; 4186 capoff = -1; 4187 endoff = 64; 4188 break; 4189 } 4190 printf(" Type %d ", hdrtype); 4191 if (type_name != NULL) 4192 printf("(%s) ", type_name); 4193 printf("header:\n"); 4194 pci_conf_print_regs(regs, 16, endoff); 4195 printf("\n"); 4196 if (type_printfn) { 4197 #ifdef _KERNEL 4198 (*type_printfn)(pc, tag, regs, sizebars); 4199 #else 4200 (*type_printfn)(regs); 4201 #endif 4202 } else 4203 printf(" Don't know how to pretty-print type %d header.\n", 4204 hdrtype); 4205 printf("\n"); 4206 4207 /* capability list, if present */ 4208 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4209 && (capoff > 0)) { 4210 #ifdef _KERNEL 4211 pci_conf_print_caplist(pc, tag, regs, capoff); 4212 #else 4213 pci_conf_print_caplist(regs, capoff); 4214 #endif 4215 printf("\n"); 4216 } 4217 4218 /* device-dependent header */ 4219 printf(" Device-dependent header:\n"); 4220 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 4221 printf("\n"); 4222 #ifdef _KERNEL 4223 if (printfn) 4224 (*printfn)(pc, tag, regs); 4225 else 4226 printf(" Don't know how to pretty-print device-dependent header.\n"); 4227 printf("\n"); 4228 #endif /* _KERNEL */ 4229 4230 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 4231 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 4232 return; 4233 4234 #ifdef _KERNEL 4235 pci_conf_print_extcaplist(pc, tag, regs, capoff); 4236 #else 4237 pci_conf_print_extcaplist(regs, capoff); 4238 #endif 4239 printf("\n"); 4240 4241 /* Extended Configuration Space, if present */ 4242 printf(" Extended Configuration Space:\n"); 4243 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 4244 } 4245
Indexes created Wed Sep 24 22:09:59 GMT 2025