pci_subr.c revision 1.161
1 /* $NetBSD: pci_subr.c,v 1.161 2017/02/27 14:13:56 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.161 2017/02/27 14:13:56 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdarg.h> 58 #include <stdbool.h> 59 #include <stdio.h> 60 #include <stdlib.h> 61 #include <string.h> 62 #endif 63 64 #include <dev/pci/pcireg.h> 65 #ifdef _KERNEL 66 #include <dev/pci/pcivar.h> 67 #else 68 #include <dev/pci/pci_verbose.h> 69 #include <dev/pci/pcidevs.h> 70 #include <dev/pci/pcidevs_data.h> 71 #endif 72 73 /* 74 * Descriptions of known PCI classes and subclasses. 75 * 76 * Subclasses are described in the same way as classes, but have a 77 * NULL subclass pointer. 78 */ 79 struct pci_class { 80 const char *name; 81 u_int val; /* as wide as pci_{,sub}class_t */ 82 const struct pci_class *subclasses; 83 }; 84 85 /* 86 * Class 0x00. 87 * Before rev. 2.0. 88 */ 89 static const struct pci_class pci_subclass_prehistoric[] = { 90 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 91 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 92 { NULL, 0, NULL, }, 93 }; 94 95 /* 96 * Class 0x01. 97 * Mass storage controller 98 */ 99 100 /* ATA programming interface */ 101 static const struct pci_class pci_interface_ata[] = { 102 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 103 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 104 { NULL, 0, NULL, }, 105 }; 106 107 /* SATA programming interface */ 108 static const struct pci_class pci_interface_sata[] = { 109 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 110 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 111 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 112 { NULL, 0, NULL, }, 113 }; 114 115 /* Flash programming interface */ 116 static const struct pci_class pci_interface_nvm[] = { 117 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 118 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 119 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 120 { NULL, 0, NULL, }, 121 }; 122 123 /* Subclasses */ 124 static const struct pci_class pci_subclass_mass_storage[] = { 125 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 126 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 127 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 128 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 129 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 130 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 131 pci_interface_ata, }, 132 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 133 pci_interface_sata, }, 134 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 135 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 136 pci_interface_nvm, }, 137 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 138 { NULL, 0, NULL, }, 139 }; 140 141 /* 142 * Class 0x02. 143 * Network controller. 144 */ 145 static const struct pci_class pci_subclass_network[] = { 146 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 147 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 148 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 149 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 150 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 151 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 152 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 153 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 154 { NULL, 0, NULL, }, 155 }; 156 157 /* 158 * Class 0x03. 159 * Display controller. 160 */ 161 162 /* VGA programming interface */ 163 static const struct pci_class pci_interface_vga[] = { 164 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 165 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 166 { NULL, 0, NULL, }, 167 }; 168 /* Subclasses */ 169 static const struct pci_class pci_subclass_display[] = { 170 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 171 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 172 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 173 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 174 { NULL, 0, NULL, }, 175 }; 176 177 /* 178 * Class 0x04. 179 * Multimedia device. 180 */ 181 static const struct pci_class pci_subclass_multimedia[] = { 182 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 183 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 184 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 185 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 186 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 187 { NULL, 0, NULL, }, 188 }; 189 190 /* 191 * Class 0x05. 192 * Memory controller. 193 */ 194 static const struct pci_class pci_subclass_memory[] = { 195 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 196 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 197 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 198 { NULL, 0, NULL, }, 199 }; 200 201 /* 202 * Class 0x06. 203 * Bridge device. 204 */ 205 206 /* PCI bridge programming interface */ 207 static const struct pci_class pci_interface_pcibridge[] = { 208 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 209 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 210 { NULL, 0, NULL, }, 211 }; 212 213 /* Semi-transparent PCI-to-PCI bridge programming interface */ 214 static const struct pci_class pci_interface_stpci[] = { 215 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 216 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 217 { NULL, 0, NULL, }, 218 }; 219 220 /* Advanced Switching programming interface */ 221 static const struct pci_class pci_interface_advsw[] = { 222 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 223 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 224 { NULL, 0, NULL, }, 225 }; 226 227 /* Subclasses */ 228 static const struct pci_class pci_subclass_bridge[] = { 229 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 230 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 231 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 232 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 233 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 234 pci_interface_pcibridge, }, 235 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 236 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 237 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 238 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 239 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 240 pci_interface_stpci, }, 241 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 242 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 243 pci_interface_advsw, }, 244 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 245 { NULL, 0, NULL, }, 246 }; 247 248 /* 249 * Class 0x07. 250 * Simple communications controller. 251 */ 252 253 /* Serial controller programming interface */ 254 static const struct pci_class pci_interface_serial[] = { 255 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 256 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 257 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 258 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 259 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 260 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 261 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 262 { NULL, 0, NULL, }, 263 }; 264 265 /* Parallel controller programming interface */ 266 static const struct pci_class pci_interface_parallel[] = { 267 { "", PCI_INTERFACE_PARALLEL, NULL,}, 268 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 269 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 270 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 271 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 272 { NULL, 0, NULL,}, 273 }; 274 275 /* Modem programming interface */ 276 static const struct pci_class pci_interface_modem[] = { 277 { "", PCI_INTERFACE_MODEM, NULL,}, 278 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 279 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 280 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 281 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 282 { NULL, 0, NULL,}, 283 }; 284 285 /* Subclasses */ 286 static const struct pci_class pci_subclass_communications[] = { 287 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 288 pci_interface_serial, }, 289 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 290 pci_interface_parallel, }, 291 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 292 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 293 pci_interface_modem, }, 294 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 295 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 296 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 297 { NULL, 0, NULL,}, 298 }; 299 300 /* 301 * Class 0x08. 302 * Base system peripheral. 303 */ 304 305 /* PIC programming interface */ 306 static const struct pci_class pci_interface_pic[] = { 307 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 308 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 309 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 310 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 311 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 312 { NULL, 0, NULL, }, 313 }; 314 315 /* DMA programming interface */ 316 static const struct pci_class pci_interface_dma[] = { 317 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 318 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 319 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 320 { NULL, 0, NULL, }, 321 }; 322 323 /* Timer programming interface */ 324 static const struct pci_class pci_interface_tmr[] = { 325 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 326 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 327 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 328 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 329 { NULL, 0, NULL, }, 330 }; 331 332 /* RTC programming interface */ 333 static const struct pci_class pci_interface_rtc[] = { 334 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 335 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 336 { NULL, 0, NULL, }, 337 }; 338 339 /* Subclasses */ 340 static const struct pci_class pci_subclass_system[] = { 341 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 342 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 343 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 344 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 345 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 346 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 347 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 348 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 349 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 350 { NULL, 0, NULL, }, 351 }; 352 353 /* 354 * Class 0x09. 355 * Input device. 356 */ 357 358 /* Gameport programming interface */ 359 static const struct pci_class pci_interface_game[] = { 360 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 361 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 362 { NULL, 0, NULL, }, 363 }; 364 365 /* Subclasses */ 366 static const struct pci_class pci_subclass_input[] = { 367 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 368 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 369 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 370 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 371 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 372 pci_interface_game, }, 373 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 374 { NULL, 0, NULL, }, 375 }; 376 377 /* 378 * Class 0x0a. 379 * Docking station. 380 */ 381 static const struct pci_class pci_subclass_dock[] = { 382 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 383 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 384 { NULL, 0, NULL, }, 385 }; 386 387 /* 388 * Class 0x0b. 389 * Processor. 390 */ 391 static const struct pci_class pci_subclass_processor[] = { 392 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 393 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 394 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 395 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 396 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 397 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 398 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 399 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 400 { NULL, 0, NULL, }, 401 }; 402 403 /* 404 * Class 0x0c. 405 * Serial bus controller. 406 */ 407 408 /* IEEE1394 programming interface */ 409 static const struct pci_class pci_interface_ieee1394[] = { 410 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 411 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 412 { NULL, 0, NULL,}, 413 }; 414 415 /* USB programming interface */ 416 static const struct pci_class pci_interface_usb[] = { 417 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 418 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 419 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 420 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 421 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 422 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 423 { NULL, 0, NULL, }, 424 }; 425 426 /* IPMI programming interface */ 427 static const struct pci_class pci_interface_ipmi[] = { 428 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 429 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 430 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 431 { NULL, 0, NULL,}, 432 }; 433 434 /* Subclasses */ 435 static const struct pci_class pci_subclass_serialbus[] = { 436 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 437 pci_interface_ieee1394, }, 438 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 439 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 440 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 441 pci_interface_usb, }, 442 /* XXX Fiber Channel/_FIBRECHANNEL */ 443 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 444 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 445 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 446 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 447 pci_interface_ipmi, }, 448 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 449 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 450 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 451 { NULL, 0, NULL, }, 452 }; 453 454 /* 455 * Class 0x0d. 456 * Wireless Controller. 457 */ 458 static const struct pci_class pci_subclass_wireless[] = { 459 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 460 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 461 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 462 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 463 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 464 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 465 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 466 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 467 { NULL, 0, NULL, }, 468 }; 469 470 /* 471 * Class 0x0e. 472 * Intelligent IO controller. 473 */ 474 475 /* Intelligent IO programming interface */ 476 static const struct pci_class pci_interface_i2o[] = { 477 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 478 { NULL, 0, NULL,}, 479 }; 480 481 /* Subclasses */ 482 static const struct pci_class pci_subclass_i2o[] = { 483 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 484 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 485 { NULL, 0, NULL, }, 486 }; 487 488 /* 489 * Class 0x0f. 490 * Satellite communication controller. 491 */ 492 static const struct pci_class pci_subclass_satcom[] = { 493 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 494 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 495 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 496 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 497 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 498 { NULL, 0, NULL, }, 499 }; 500 501 /* 502 * Class 0x10. 503 * Encryption/Decryption controller. 504 */ 505 static const struct pci_class pci_subclass_crypto[] = { 506 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 507 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 508 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 509 { NULL, 0, NULL, }, 510 }; 511 512 /* 513 * Class 0x11. 514 * Data aquuisition and signal processing controller. 515 */ 516 static const struct pci_class pci_subclass_dasp[] = { 517 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 518 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 519 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 520 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 521 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 522 { NULL, 0, NULL, }, 523 }; 524 525 /* List of classes */ 526 static const struct pci_class pci_class[] = { 527 { "prehistoric", PCI_CLASS_PREHISTORIC, 528 pci_subclass_prehistoric, }, 529 { "mass storage", PCI_CLASS_MASS_STORAGE, 530 pci_subclass_mass_storage, }, 531 { "network", PCI_CLASS_NETWORK, 532 pci_subclass_network, }, 533 { "display", PCI_CLASS_DISPLAY, 534 pci_subclass_display, }, 535 { "multimedia", PCI_CLASS_MULTIMEDIA, 536 pci_subclass_multimedia, }, 537 { "memory", PCI_CLASS_MEMORY, 538 pci_subclass_memory, }, 539 { "bridge", PCI_CLASS_BRIDGE, 540 pci_subclass_bridge, }, 541 { "communications", PCI_CLASS_COMMUNICATIONS, 542 pci_subclass_communications, }, 543 { "system", PCI_CLASS_SYSTEM, 544 pci_subclass_system, }, 545 { "input", PCI_CLASS_INPUT, 546 pci_subclass_input, }, 547 { "dock", PCI_CLASS_DOCK, 548 pci_subclass_dock, }, 549 { "processor", PCI_CLASS_PROCESSOR, 550 pci_subclass_processor, }, 551 { "serial bus", PCI_CLASS_SERIALBUS, 552 pci_subclass_serialbus, }, 553 { "wireless", PCI_CLASS_WIRELESS, 554 pci_subclass_wireless, }, 555 { "I2O", PCI_CLASS_I2O, 556 pci_subclass_i2o, }, 557 { "satellite comm", PCI_CLASS_SATCOM, 558 pci_subclass_satcom, }, 559 { "crypto", PCI_CLASS_CRYPTO, 560 pci_subclass_crypto, }, 561 { "DASP", PCI_CLASS_DASP, 562 pci_subclass_dasp, }, 563 { "undefined", PCI_CLASS_UNDEFINED, 564 NULL, }, 565 { NULL, 0, 566 NULL, }, 567 }; 568 569 DEV_VERBOSE_DEFINE(pci); 570 571 /* 572 * Append a formatted string to dest without writing more than len 573 * characters (including the trailing NUL character). dest and len 574 * are updated for use in subsequent calls to snappendf(). 575 * 576 * Returns 0 on success, a negative value if vnsprintf() fails, or 577 * a positive value if the dest buffer would have overflowed. 578 */ 579 580 static int __printflike(3,4) 581 snappendf(char **dest, size_t *len, const char * restrict fmt, ...) 582 { 583 va_list ap; 584 int count; 585 586 va_start(ap, fmt); 587 count = vsnprintf(*dest, *len, fmt, ap); 588 va_end(ap); 589 590 /* Let vsnprintf() errors bubble up to caller */ 591 if (count < 0 || *len == 0) 592 return count; 593 594 /* Handle overflow */ 595 if ((size_t)count >= *len) { 596 *dest += *len - 1; 597 *len = 1; 598 return 1; 599 } 600 601 /* Update dest & len to point at trailing NUL */ 602 *dest += count; 603 *len -= count; 604 605 return 0; 606 } 607 608 void 609 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 610 size_t l) 611 { 612 pci_class_t pciclass; 613 pci_subclass_t subclass; 614 pci_interface_t interface; 615 pci_revision_t revision; 616 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 617 const struct pci_class *classp, *subclassp, *interfacep; 618 619 pciclass = PCI_CLASS(class_reg); 620 subclass = PCI_SUBCLASS(class_reg); 621 interface = PCI_INTERFACE(class_reg); 622 revision = PCI_REVISION(class_reg); 623 624 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 625 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 626 PCI_PRODUCT(id_reg)); 627 628 classp = pci_class; 629 while (classp->name != NULL) { 630 if (pciclass == classp->val) 631 break; 632 classp++; 633 } 634 635 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 636 while (subclassp && subclassp->name != NULL) { 637 if (subclass == subclassp->val) 638 break; 639 subclassp++; 640 } 641 642 interfacep = (subclassp && subclassp->name != NULL) ? 643 subclassp->subclasses : NULL; 644 while (interfacep && interfacep->name != NULL) { 645 if (interface == interfacep->val) 646 break; 647 interfacep++; 648 } 649 650 (void)snappendf(&cp, &l, "%s %s", vendor, product); 651 if (showclass) { 652 (void)snappendf(&cp, &l, " ("); 653 if (classp->name == NULL) 654 (void)snappendf(&cp, &l, 655 "class 0x%02x, subclass 0x%02x", 656 pciclass, subclass); 657 else { 658 if (subclassp == NULL || subclassp->name == NULL) 659 (void)snappendf(&cp, &l, 660 "%s, subclass 0x%02x", 661 classp->name, subclass); 662 else 663 (void)snappendf(&cp, &l, "%s %s", 664 subclassp->name, classp->name); 665 } 666 if ((interfacep == NULL) || (interfacep->name == NULL)) { 667 if (interface != 0) 668 (void)snappendf(&cp, &l, ", interface 0x%02x", 669 interface); 670 } else if (strncmp(interfacep->name, "", 1) != 0) 671 (void)snappendf(&cp, &l, ", %s", interfacep->name); 672 if (revision != 0) 673 (void)snappendf(&cp, &l, ", revision 0x%02x", revision); 674 (void)snappendf(&cp, &l, ")"); 675 } 676 } 677 678 #ifdef _KERNEL 679 void 680 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 681 const char *known, int addrev) 682 { 683 char devinfo[256]; 684 685 if (known) { 686 aprint_normal(": %s", known); 687 if (addrev) 688 aprint_normal(" (rev. 0x%02x)", 689 PCI_REVISION(pa->pa_class)); 690 aprint_normal("\n"); 691 } else { 692 pci_devinfo(pa->pa_id, pa->pa_class, 0, 693 devinfo, sizeof(devinfo)); 694 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 695 PCI_REVISION(pa->pa_class)); 696 } 697 if (naive) 698 aprint_naive(": %s\n", naive); 699 else 700 aprint_naive("\n"); 701 } 702 #endif 703 704 /* 705 * Print out most of the PCI configuration registers. Typically used 706 * in a device attach routine like this: 707 * 708 * #ifdef MYDEV_DEBUG 709 * printf("%s: ", device_xname(sc->sc_dev)); 710 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 711 * #endif 712 */ 713 714 #define i2o(i) ((i) * 4) 715 #define o2i(o) ((o) / 4) 716 #define onoff2(str, rval, bit, onstr, offstr) \ 717 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 718 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 719 720 static void 721 pci_conf_print_common( 722 #ifdef _KERNEL 723 pci_chipset_tag_t pc, pcitag_t tag, 724 #endif 725 const pcireg_t *regs) 726 { 727 const char *name; 728 const struct pci_class *classp, *subclassp; 729 char vendor[PCI_VENDORSTR_LEN]; 730 char product[PCI_PRODUCTSTR_LEN]; 731 pcireg_t rval; 732 unsigned int num; 733 734 rval = regs[o2i(PCI_ID_REG)]; 735 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 736 if (name) 737 printf(" Vendor Name: %s (0x%04x)\n", name, 738 PCI_VENDOR(rval)); 739 else 740 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 741 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 742 PCI_PRODUCT(rval)); 743 if (name) 744 printf(" Device Name: %s (0x%04x)\n", name, 745 PCI_PRODUCT(rval)); 746 else 747 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 748 749 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 750 751 printf(" Command register: 0x%04x\n", rval & 0xffff); 752 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 753 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 754 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 755 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 756 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 757 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 758 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 759 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 760 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 761 onoff("Fast back-to-back transactions", rval, 762 PCI_COMMAND_BACKTOBACK_ENABLE); 763 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 764 765 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 766 onoff("Immediate Readness", rval, PCI_STATUS_IMMD_READNESS); 767 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 768 "inactive"); 769 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 770 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 771 onoff("User Definable Features (UDF) support", rval, 772 PCI_STATUS_UDF_SUPPORT); 773 onoff("Fast back-to-back capable", rval, 774 PCI_STATUS_BACKTOBACK_SUPPORT); 775 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 776 777 printf(" DEVSEL timing: "); 778 switch (rval & PCI_STATUS_DEVSEL_MASK) { 779 case PCI_STATUS_DEVSEL_FAST: 780 printf("fast"); 781 break; 782 case PCI_STATUS_DEVSEL_MEDIUM: 783 printf("medium"); 784 break; 785 case PCI_STATUS_DEVSEL_SLOW: 786 printf("slow"); 787 break; 788 default: 789 printf("unknown/reserved"); /* XXX */ 790 break; 791 } 792 printf(" (0x%x)\n", __SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK)); 793 794 onoff("Slave signaled Target Abort", rval, 795 PCI_STATUS_TARGET_TARGET_ABORT); 796 onoff("Master received Target Abort", rval, 797 PCI_STATUS_MASTER_TARGET_ABORT); 798 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 799 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 800 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 801 802 rval = regs[o2i(PCI_CLASS_REG)]; 803 for (classp = pci_class; classp->name != NULL; classp++) { 804 if (PCI_CLASS(rval) == classp->val) 805 break; 806 } 807 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 808 while (subclassp && subclassp->name != NULL) { 809 if (PCI_SUBCLASS(rval) == subclassp->val) 810 break; 811 subclassp++; 812 } 813 if (classp->name != NULL) { 814 printf(" Class Name: %s (0x%02x)\n", classp->name, 815 PCI_CLASS(rval)); 816 if (subclassp != NULL && subclassp->name != NULL) 817 printf(" Subclass Name: %s (0x%02x)\n", 818 subclassp->name, PCI_SUBCLASS(rval)); 819 else 820 printf(" Subclass ID: 0x%02x\n", 821 PCI_SUBCLASS(rval)); 822 } else { 823 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 824 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 825 } 826 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 827 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 828 829 rval = regs[o2i(PCI_BHLC_REG)]; 830 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 831 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 832 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 833 PCI_HDRTYPE(rval)); 834 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 835 num = PCI_CACHELINE(rval); 836 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 837 } 838 839 static int 840 pci_conf_print_bar( 841 #ifdef _KERNEL 842 pci_chipset_tag_t pc, pcitag_t tag, 843 #endif 844 const pcireg_t *regs, int reg, const char *name 845 #ifdef _KERNEL 846 , int sizebar 847 #endif 848 ) 849 { 850 int width; 851 pcireg_t rval, rval64h; 852 #ifdef _KERNEL 853 int s; 854 pcireg_t mask, mask64h; 855 #endif 856 857 width = 4; 858 859 /* 860 * Section 6.2.5.1, `Address Maps', tells us that: 861 * 862 * 1) The builtin software should have already mapped the 863 * device in a reasonable way. 864 * 865 * 2) A device which wants 2^n bytes of memory will hardwire 866 * the bottom n bits of the address to 0. As recommended, 867 * we write all 1s and see what we get back. 868 */ 869 870 rval = regs[o2i(reg)]; 871 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 872 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 873 rval64h = regs[o2i(reg + 4)]; 874 width = 8; 875 } else 876 rval64h = 0; 877 878 #ifdef _KERNEL 879 /* XXX don't size unknown memory type? */ 880 if (rval != 0 && sizebar) { 881 /* 882 * The following sequence seems to make some devices 883 * (e.g. host bus bridges, which don't normally 884 * have their space mapped) very unhappy, to 885 * the point of crashing the system. 886 * 887 * Therefore, if the mapping register is zero to 888 * start out with, don't bother trying. 889 */ 890 s = splhigh(); 891 pci_conf_write(pc, tag, reg, 0xffffffff); 892 mask = pci_conf_read(pc, tag, reg); 893 pci_conf_write(pc, tag, reg, rval); 894 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 895 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 896 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 897 mask64h = pci_conf_read(pc, tag, reg + 4); 898 pci_conf_write(pc, tag, reg + 4, rval64h); 899 } else 900 mask64h = 0; 901 splx(s); 902 } else 903 mask = mask64h = 0; 904 #endif /* _KERNEL */ 905 906 printf(" Base address register at 0x%02x", reg); 907 if (name) 908 printf(" (%s)", name); 909 printf("\n "); 910 if (rval == 0) { 911 printf("not implemented(?)\n"); 912 return width; 913 } 914 printf("type: "); 915 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 916 const char *type, *prefetch; 917 918 switch (PCI_MAPREG_MEM_TYPE(rval)) { 919 case PCI_MAPREG_MEM_TYPE_32BIT: 920 type = "32-bit"; 921 break; 922 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 923 type = "32-bit-1M"; 924 break; 925 case PCI_MAPREG_MEM_TYPE_64BIT: 926 type = "64-bit"; 927 break; 928 default: 929 type = "unknown (XXX)"; 930 break; 931 } 932 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 933 prefetch = ""; 934 else 935 prefetch = "non"; 936 printf("%s %sprefetchable memory\n", type, prefetch); 937 switch (PCI_MAPREG_MEM_TYPE(rval)) { 938 case PCI_MAPREG_MEM_TYPE_64BIT: 939 printf(" base: 0x%016llx, ", 940 PCI_MAPREG_MEM64_ADDR( 941 ((((long long) rval64h) << 32) | rval))); 942 #ifdef _KERNEL 943 if (sizebar) 944 printf("size: 0x%016llx", 945 PCI_MAPREG_MEM64_SIZE( 946 ((((long long) mask64h) << 32) | mask))); 947 else 948 #endif /* _KERNEL */ 949 printf("not sized"); 950 printf("\n"); 951 break; 952 case PCI_MAPREG_MEM_TYPE_32BIT: 953 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 954 default: 955 printf(" base: 0x%08x, ", 956 PCI_MAPREG_MEM_ADDR(rval)); 957 #ifdef _KERNEL 958 if (sizebar) 959 printf("size: 0x%08x", 960 PCI_MAPREG_MEM_SIZE(mask)); 961 else 962 #endif /* _KERNEL */ 963 printf("not sized"); 964 printf("\n"); 965 break; 966 } 967 } else { 968 #ifdef _KERNEL 969 if (sizebar) 970 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 971 #endif /* _KERNEL */ 972 printf("i/o\n"); 973 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 974 #ifdef _KERNEL 975 if (sizebar) 976 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 977 else 978 #endif /* _KERNEL */ 979 printf("not sized"); 980 printf("\n"); 981 } 982 983 return width; 984 } 985 986 static void 987 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 988 { 989 int off, needaddr, neednl; 990 991 needaddr = 1; 992 neednl = 0; 993 for (off = first; off < pastlast; off += 4) { 994 if ((off % 16) == 0 || needaddr) { 995 printf(" 0x%02x:", off); 996 needaddr = 0; 997 } 998 printf(" 0x%08x", regs[o2i(off)]); 999 neednl = 1; 1000 if ((off % 16) == 12) { 1001 printf("\n"); 1002 neednl = 0; 1003 } 1004 } 1005 if (neednl) 1006 printf("\n"); 1007 } 1008 1009 static const char * 1010 pci_conf_print_agp_calcycle(uint8_t cal) 1011 { 1012 1013 switch (cal) { 1014 case 0x0: 1015 return "4ms"; 1016 case 0x1: 1017 return "16ms"; 1018 case 0x2: 1019 return "64ms"; 1020 case 0x3: 1021 return "256ms"; 1022 case 0x7: 1023 return "Calibration Cycle Not Needed"; 1024 default: 1025 return "(reserved)"; 1026 } 1027 } 1028 1029 static void 1030 pci_conf_print_agp_datarate(pcireg_t reg, bool isagp3) 1031 { 1032 if (isagp3) { 1033 /* AGP 3.0 */ 1034 if (reg & AGP_MODE_V3_RATE_4x) 1035 printf("x4"); 1036 if (reg & AGP_MODE_V3_RATE_8x) 1037 printf("x8"); 1038 } else { 1039 /* AGP 2.0 */ 1040 if (reg & AGP_MODE_V2_RATE_1x) 1041 printf("x1"); 1042 if (reg & AGP_MODE_V2_RATE_2x) 1043 printf("x2"); 1044 if (reg & AGP_MODE_V2_RATE_4x) 1045 printf("x4"); 1046 } 1047 printf("\n"); 1048 } 1049 1050 static void 1051 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1052 { 1053 pcireg_t rval; 1054 bool isagp3; 1055 1056 printf("\n AGP Capabilities Register\n"); 1057 1058 rval = regs[o2i(capoff)]; 1059 printf(" Revision: %d.%d\n", 1060 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1061 1062 rval = regs[o2i(capoff + PCI_AGP_STATUS)]; 1063 printf(" Status register: 0x%04x\n", rval); 1064 printf(" RQ: %d\n", 1065 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1066 printf(" ARQSZ: %d\n", 1067 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1068 printf(" CAL cycle: %s\n", 1069 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1070 onoff("SBA", rval, AGP_MODE_SBA); 1071 onoff("htrans#", rval, AGP_MODE_HTRANS); 1072 onoff("Over 4G", rval, AGP_MODE_4G); 1073 onoff("Fast Write", rval, AGP_MODE_FW); 1074 onoff("AGP 3.0 Mode", rval, AGP_MODE_MODE_3); 1075 isagp3 = rval & AGP_MODE_MODE_3; 1076 printf(" Data Rate Support: "); 1077 pci_conf_print_agp_datarate(rval, isagp3); 1078 1079 rval = regs[o2i(capoff + PCI_AGP_COMMAND)]; 1080 printf(" Command register: 0x%08x\n", rval); 1081 printf(" PRQ: %d\n", 1082 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1083 printf(" PARQSZ: %d\n", 1084 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1085 printf(" PCAL cycle: %s\n", 1086 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1087 onoff("SBA", rval, AGP_MODE_SBA); 1088 onoff("AGP", rval, AGP_MODE_AGP); 1089 onoff("Over 4G", rval, AGP_MODE_4G); 1090 onoff("Fast Write", rval, AGP_MODE_FW); 1091 if (isagp3) { 1092 printf(" Data Rate Enable: "); 1093 /* 1094 * The Data Rate Enable bits are used only on 3.0 and the 1095 * Command register has no AGP_MODE_MODE_3 bit, so pass the 1096 * flag to print correctly. 1097 */ 1098 pci_conf_print_agp_datarate(rval, isagp3); 1099 } 1100 } 1101 1102 static const char * 1103 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1104 { 1105 1106 switch ((caps >> 6) & 7) { 1107 case 0: return "self-powered"; 1108 case 1: return "55 mA"; 1109 case 2: return "100 mA"; 1110 case 3: return "160 mA"; 1111 case 4: return "220 mA"; 1112 case 5: return "270 mA"; 1113 case 6: return "320 mA"; 1114 case 7: 1115 default: return "375 mA"; 1116 } 1117 } 1118 1119 static const char * 1120 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1121 { 1122 static const char unk[] = "unknown"; 1123 static const char *pmrev[8] = { 1124 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1125 }; 1126 if (val > 7) 1127 return unk; 1128 return pmrev[val]; 1129 } 1130 1131 static void 1132 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1133 { 1134 uint16_t caps, pmcsr; 1135 pcireg_t reg; 1136 1137 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1138 reg = regs[o2i(capoff + PCI_PMCSR)]; 1139 pmcsr = reg & 0xffff; 1140 1141 printf("\n PCI Power Management Capabilities Register\n"); 1142 1143 printf(" Capabilities register: 0x%04x\n", caps); 1144 printf(" Version: %s\n", 1145 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1146 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1147 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1148 printf(" 3.3V auxiliary current: %s\n", 1149 pci_conf_print_pcipm_cap_aux(caps)); 1150 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1151 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1152 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1153 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1154 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1155 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1156 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1157 1158 printf(" Control/status register: 0x%04x\n", pmcsr); 1159 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1160 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1161 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1162 printf(" PME# assertion: %sabled\n", 1163 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1164 printf(" Data Select: %d\n", 1165 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK)); 1166 printf(" Data Scale: %d\n", 1167 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK)); 1168 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1169 printf(" Bridge Support Extensions register: 0x%02x\n", 1170 (reg >> 16) & 0xff); 1171 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1172 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1173 printf(" Data register: 0x%02x\n", __SHIFTOUT(reg, PCI_PMCSR_DATA)); 1174 1175 } 1176 1177 /* XXX pci_conf_print_vpd_cap */ 1178 /* XXX pci_conf_print_slotid_cap */ 1179 1180 static void 1181 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1182 { 1183 uint32_t ctl, mmc, mme; 1184 1185 regs += o2i(capoff); 1186 ctl = *regs++; 1187 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1188 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1189 1190 printf("\n PCI Message Signaled Interrupt\n"); 1191 1192 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1193 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1194 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1195 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1196 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1197 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1198 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1199 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1200 onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP); 1201 onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN); 1202 printf(" Message Address %sregister: 0x%08x\n", 1203 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1204 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1205 printf(" Message Address %sregister: 0x%08x\n", 1206 "(upper) ", *regs++); 1207 } 1208 printf(" Message Data register: 0x%04x\n", *regs & 0xffff); 1209 regs++; 1210 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1211 printf(" Vector Mask register: 0x%08x\n", *regs++); 1212 printf(" Vector Pending register: 0x%08x\n", *regs++); 1213 } 1214 } 1215 1216 /* XXX pci_conf_print_cpci_hostwap_cap */ 1217 1218 /* 1219 * For both command register and status register. 1220 * The argument "idx" is index number (0 to 7). 1221 */ 1222 static int 1223 pcix_split_trans(unsigned int idx) 1224 { 1225 static int table[8] = { 1226 1, 2, 3, 4, 8, 12, 16, 32 1227 }; 1228 1229 if (idx >= __arraycount(table)) 1230 return -1; 1231 return table[idx]; 1232 } 1233 1234 static void 1235 pci_conf_print_pcix_cap_2ndbusmode(int num) 1236 { 1237 const char *maxfreq, *maxperiod; 1238 1239 printf(" Mode: "); 1240 if (num <= 0x07) 1241 printf("PCI-X Mode 1\n"); 1242 else if (num <= 0x0b) 1243 printf("PCI-X 266 (Mode 2)\n"); 1244 else 1245 printf("PCI-X 533 (Mode 2)\n"); 1246 1247 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1248 switch (num & 0x03) { 1249 default: 1250 case 0: 1251 maxfreq = "N/A"; 1252 maxperiod = "N/A"; 1253 break; 1254 case 1: 1255 maxfreq = "66MHz"; 1256 maxperiod = "15ns"; 1257 break; 1258 case 2: 1259 maxfreq = "100MHz"; 1260 maxperiod = "10ns"; 1261 break; 1262 case 3: 1263 maxfreq = "133MHz"; 1264 maxperiod = "7.5ns"; 1265 break; 1266 } 1267 printf(" Max Clock Freq: %s\n", maxfreq); 1268 printf(" Min Clock Period: %s\n", maxperiod); 1269 } 1270 1271 static void 1272 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1273 { 1274 pcireg_t reg; 1275 int isbridge; 1276 int i; 1277 1278 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1279 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1280 printf("\n PCI-X %s Capabilities Register\n", 1281 isbridge ? "Bridge" : "Non-bridge"); 1282 1283 reg = regs[o2i(capoff)]; 1284 if (isbridge != 0) { 1285 printf(" Secondary status register: 0x%04x\n", 1286 (reg & 0xffff0000) >> 16); 1287 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1288 onoff("133MHz capable", reg, PCIX_STATUS_133); 1289 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1290 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1291 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1292 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1293 pci_conf_print_pcix_cap_2ndbusmode( 1294 __SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1295 printf(" Version: 0x%x\n", 1296 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1297 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1298 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1299 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1300 } else { 1301 printf(" Command register: 0x%04x\n", 1302 (reg & 0xffff0000) >> 16); 1303 onoff("Data Parity Error Recovery", reg, 1304 PCIX_CMD_PERR_RECOVER); 1305 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1306 printf(" Maximum Burst Read Count: %u\n", 1307 PCIX_CMD_BYTECNT(reg)); 1308 printf(" Maximum Split Transactions: %d\n", 1309 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1310 >> PCIX_CMD_SPLTRANS_SHIFT)); 1311 } 1312 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1313 printf(" %sStatus register: 0x%08x\n", 1314 isbridge ? "Bridge " : "", reg); 1315 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1316 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1317 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1318 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1319 onoff("133MHz capable", reg, PCIX_STATUS_133); 1320 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1321 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1322 if (isbridge != 0) { 1323 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1324 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1325 } else { 1326 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1327 "bridge device", "simple device"); 1328 printf(" Designed max memory read byte count: %d\n", 1329 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1330 >> PCIX_STATUS_MAXB_SHIFT)); 1331 printf(" Designed max outstanding split transaction: %d\n", 1332 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1333 >> PCIX_STATUS_MAXST_SHIFT)); 1334 printf(" MAX cumulative Read Size: %u\n", 1335 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1336 onoff("Received split completion error", reg, 1337 PCIX_STATUS_SCERR); 1338 } 1339 onoff("266MHz capable", reg, PCIX_STATUS_266); 1340 onoff("533MHz capable", reg, PCIX_STATUS_533); 1341 1342 if (isbridge == 0) 1343 return; 1344 1345 /* Only for bridge */ 1346 for (i = 0; i < 2; i++) { 1347 reg = regs[o2i(capoff+PCIX_BRIDGE_UP_STCR + (4 * i))]; 1348 printf(" %s split transaction control register: 0x%08x\n", 1349 (i == 0) ? "Upstream" : "Downstream", reg); 1350 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1351 printf(" Commitment Limit: %d\n", 1352 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1353 } 1354 } 1355 1356 /* pci_conf_print_ht_slave_cap */ 1357 /* pci_conf_print_ht_host_cap */ 1358 /* pci_conf_print_ht_switch_cap */ 1359 /* pci_conf_print_ht_intr_cap */ 1360 /* pci_conf_print_ht_revid_cap */ 1361 /* pci_conf_print_ht_unitid_cap */ 1362 /* pci_conf_print_ht_extcnf_cap */ 1363 /* pci_conf_print_ht_addrmap_cap */ 1364 /* pci_conf_print_ht_msimap_cap */ 1365 1366 static void 1367 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1368 { 1369 pcireg_t val; 1370 uint32_t lo, hi; 1371 1372 /* 1373 * Print the rest of the command register bits. Others are 1374 * printed in pci_conf_print_ht_cap(). 1375 */ 1376 val = regs[o2i(capoff + PCI_HT_CMD)]; 1377 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1378 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1379 1380 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1381 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1382 printf(" Address Low register: 0x%08x\n", lo); 1383 printf(" Address high register: 0x%08x\n", hi); 1384 printf(" Address: 0x%016" PRIx64 "\n", 1385 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1386 } 1387 1388 /* pci_conf_print_ht_droute_cap */ 1389 /* pci_conf_print_ht_vcset_cap */ 1390 /* pci_conf_print_ht_retry_cap */ 1391 /* pci_conf_print_ht_x86enc_cap */ 1392 /* pci_conf_print_ht_gen3_cap */ 1393 /* pci_conf_print_ht_fle_cap */ 1394 /* pci_conf_print_ht_pm_cap */ 1395 /* pci_conf_print_ht_hnc_cap */ 1396 1397 static const struct ht_types { 1398 pcireg_t cap; 1399 const char *name; 1400 void (*printfunc)(const pcireg_t *, int); 1401 } ht_captab[] = { 1402 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1403 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1404 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1405 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1406 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1407 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1408 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1409 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1410 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1411 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1412 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1413 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1414 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1415 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1416 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1417 {PCI_HT_CAP_PM, "Power Management", NULL }, 1418 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1419 }; 1420 1421 static void 1422 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1423 { 1424 pcireg_t val, foundcap; 1425 unsigned int off; 1426 1427 val = regs[o2i(capoff + PCI_HT_CMD)]; 1428 1429 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1430 1431 printf(" Command register: 0x%04x\n", val >> 16); 1432 foundcap = PCI_HT_CAP(val); 1433 for (off = 0; off < __arraycount(ht_captab); off++) { 1434 if (ht_captab[off].cap == foundcap) 1435 break; 1436 } 1437 printf(" Capability Type: 0x%02x ", foundcap); 1438 if (off >= __arraycount(ht_captab)) { 1439 printf("(unknown)\n"); 1440 return; 1441 } 1442 printf("(%s)\n", ht_captab[off].name); 1443 if (ht_captab[off].printfunc != NULL) 1444 ht_captab[off].printfunc(regs, capoff); 1445 } 1446 1447 static void 1448 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1449 { 1450 uint16_t caps; 1451 1452 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1453 1454 printf("\n PCI Vendor Specific Capabilities Register\n"); 1455 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1456 } 1457 1458 static void 1459 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1460 { 1461 pcireg_t val; 1462 1463 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1464 1465 printf("\n Debugport Capability Register\n"); 1466 printf(" Debug base Register: 0x%04x\n", 1467 val >> PCI_DEBUG_BASER_SHIFT); 1468 printf(" port offset: 0x%04x\n", 1469 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1470 printf(" BAR number: %u\n", 1471 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1472 } 1473 1474 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1475 /* XXX pci_conf_print_hotplug_cap */ 1476 1477 static void 1478 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1479 { 1480 pcireg_t reg; 1481 1482 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1483 1484 printf("\n Subsystem ID Capability Register\n"); 1485 printf(" Subsystem ID : 0x%08x\n", reg); 1486 } 1487 1488 /* XXX pci_conf_print_agp8_cap */ 1489 /* XXX pci_conf_print_secure_cap */ 1490 1491 static void 1492 pci_print_pcie_L0s_latency(uint32_t val) 1493 { 1494 1495 switch (val) { 1496 case 0x0: 1497 printf("Less than 64ns\n"); 1498 break; 1499 case 0x1: 1500 case 0x2: 1501 case 0x3: 1502 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1503 break; 1504 case 0x4: 1505 printf("512ns to less than 1us\n"); 1506 break; 1507 case 0x5: 1508 printf("1us to less than 2us\n"); 1509 break; 1510 case 0x6: 1511 printf("2us - 4us\n"); 1512 break; 1513 case 0x7: 1514 printf("More than 4us\n"); 1515 break; 1516 } 1517 } 1518 1519 static void 1520 pci_print_pcie_L1_latency(uint32_t val) 1521 { 1522 1523 switch (val) { 1524 case 0x0: 1525 printf("Less than 1us\n"); 1526 break; 1527 case 0x6: 1528 printf("32us - 64us\n"); 1529 break; 1530 case 0x7: 1531 printf("More than 64us\n"); 1532 break; 1533 default: 1534 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1535 break; 1536 } 1537 } 1538 1539 static void 1540 pci_print_pcie_compl_timeout(uint32_t val) 1541 { 1542 1543 switch (val) { 1544 case 0x0: 1545 printf("50us to 50ms\n"); 1546 break; 1547 case 0x5: 1548 printf("16ms to 55ms\n"); 1549 break; 1550 case 0x6: 1551 printf("65ms to 210ms\n"); 1552 break; 1553 case 0x9: 1554 printf("260ms to 900ms\n"); 1555 break; 1556 case 0xa: 1557 printf("1s to 3.5s\n"); 1558 break; 1559 default: 1560 printf("unknown %u value\n", val); 1561 break; 1562 } 1563 } 1564 1565 static const char * const pcie_linkspeeds[] = {"2.5", "2.5", "5.0", "8.0"}; 1566 1567 static void 1568 pci_print_pcie_linkspeed(pcireg_t val) 1569 { 1570 1571 if (val > __arraycount(pcie_linkspeeds)) 1572 printf("unknown value (%u)\n", val); 1573 else 1574 printf("%sGT/s\n", pcie_linkspeeds[val]); 1575 } 1576 1577 static void 1578 pci_print_pcie_linkspeedvector(pcireg_t val) 1579 { 1580 unsigned int i; 1581 1582 /* Start from 0 */ 1583 for (i = 0; i < 16; i++) 1584 if (((val >> i) & 0x01) != 0) { 1585 if (i >= __arraycount(pcie_linkspeeds)) 1586 printf(" unknown vector (0x%x)", 1 << i); 1587 else 1588 printf(" %sGT/s", pcie_linkspeeds[i]); 1589 } 1590 } 1591 1592 static void 1593 pci_print_pcie_link_deemphasis(pcireg_t val) 1594 { 1595 switch (val) { 1596 case 0: 1597 printf("-6dB"); 1598 break; 1599 case 1: 1600 printf("-3.5dB"); 1601 break; 1602 default: 1603 printf("(reserved value)"); 1604 } 1605 } 1606 1607 static void 1608 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1609 { 1610 pcireg_t reg; /* for each register */ 1611 pcireg_t val; /* for each bitfield */ 1612 bool check_link = false; 1613 bool check_slot = false; 1614 bool check_rootport = false; 1615 unsigned int pciever; 1616 unsigned int i; 1617 1618 printf("\n PCI Express Capabilities Register\n"); 1619 /* Capability Register */ 1620 reg = regs[o2i(capoff)]; 1621 printf(" Capability register: 0x%04x\n", reg >> 16); 1622 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1623 printf(" Capability version: %u\n", pciever); 1624 printf(" Device type: "); 1625 switch ((reg & 0x00f00000) >> 20) { 1626 case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */ 1627 printf("PCI Express Endpoint device\n"); 1628 check_link = true; 1629 break; 1630 case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */ 1631 printf("Legacy PCI Express Endpoint device\n"); 1632 check_link = true; 1633 break; 1634 case PCIE_XCAP_TYPE_ROOT: /* 0x4 */ 1635 printf("Root Port of PCI Express Root Complex\n"); 1636 check_link = true; 1637 check_slot = true; 1638 check_rootport = true; 1639 break; 1640 case PCIE_XCAP_TYPE_UP: /* 0x5 */ 1641 printf("Upstream Port of PCI Express Switch\n"); 1642 break; 1643 case PCIE_XCAP_TYPE_DOWN: /* 0x6 */ 1644 printf("Downstream Port of PCI Express Switch\n"); 1645 check_slot = true; 1646 check_rootport = true; 1647 break; 1648 case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */ 1649 printf("PCI Express to PCI/PCI-X Bridge\n"); 1650 break; 1651 case PCIE_XCAP_TYPE_PCI2PCIE: /* 0x8 */ 1652 printf("PCI/PCI-X to PCI Express Bridge\n"); 1653 break; 1654 case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */ 1655 printf("Root Complex Integrated Endpoint\n"); 1656 break; 1657 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */ 1658 check_rootport = true; 1659 printf("Root Complex Event Collector\n"); 1660 break; 1661 default: 1662 printf("unknown\n"); 1663 break; 1664 } 1665 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1666 printf(" Interrupt Message Number: 0x%02x\n", 1667 (unsigned int)__SHIFTOUT(reg, PCIE_XCAP_IRQ)); 1668 1669 /* Device Capability Register */ 1670 reg = regs[o2i(capoff + PCIE_DCAP)]; 1671 printf(" Device Capabilities Register: 0x%08x\n", reg); 1672 printf(" Max Payload Size Supported: %u bytes max\n", 1673 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1674 printf(" Phantom Functions Supported: "); 1675 switch (__SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) { 1676 case 0x0: 1677 printf("not available\n"); 1678 break; 1679 case 0x1: 1680 printf("MSB\n"); 1681 break; 1682 case 0x2: 1683 printf("two MSB\n"); 1684 break; 1685 case 0x3: 1686 printf("All three bits\n"); 1687 break; 1688 } 1689 printf(" Extended Tag Field Supported: %dbit\n", 1690 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1691 printf(" Endpoint L0 Acceptable Latency: "); 1692 pci_print_pcie_L0s_latency(__SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY)); 1693 printf(" Endpoint L1 Acceptable Latency: "); 1694 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY)); 1695 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1696 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1697 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1698 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1699 printf(" Captured Slot Power Limit Value: %u\n", 1700 (unsigned int)__SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL)); 1701 printf(" Captured Slot Power Limit Scale: %u\n", 1702 (unsigned int)__SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE)); 1703 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1704 1705 /* Device Control Register */ 1706 reg = regs[o2i(capoff + PCIE_DCSR)]; 1707 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1708 onoff("Correctable Error Reporting Enable", reg, 1709 PCIE_DCSR_ENA_COR_ERR); 1710 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1711 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1712 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1713 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1714 printf(" Max Payload Size: %d byte\n", 1715 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD)); 1716 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1717 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1718 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1719 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1720 printf(" Max Read Request Size: %d byte\n", 1721 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ)); 1722 1723 /* Device Status Register */ 1724 reg = regs[o2i(capoff + PCIE_DCSR)]; 1725 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1726 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1727 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1728 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1729 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1730 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1731 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1732 onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD); 1733 1734 if (check_link) { 1735 /* Link Capability Register */ 1736 reg = regs[o2i(capoff + PCIE_LCAP)]; 1737 printf(" Link Capabilities Register: 0x%08x\n", reg); 1738 printf(" Maximum Link Speed: "); 1739 pci_print_pcie_linkspeed(reg & PCIE_LCAP_MAX_SPEED); 1740 printf(" Maximum Link Width: x%u lanes\n", 1741 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH)); 1742 printf(" Active State PM Support: "); 1743 switch (__SHIFTOUT(reg, PCIE_LCAP_ASPM)) { 1744 case 0x0: 1745 printf("No ASPM support\n"); 1746 break; 1747 case 0x1: 1748 printf("L0s supported\n"); 1749 break; 1750 case 0x2: 1751 printf("L1 supported\n"); 1752 break; 1753 case 0x3: 1754 printf("L0s and L1 supported\n"); 1755 break; 1756 } 1757 printf(" L0 Exit Latency: "); 1758 pci_print_pcie_L0s_latency(__SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT)); 1759 printf(" L1 Exit Latency: "); 1760 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_LCAP_L1_EXIT)); 1761 printf(" Port Number: %u\n", 1762 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_PORT)); 1763 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1764 onoff("Surprise Down Error Report", reg, 1765 PCIE_LCAP_SURPRISE_DOWN); 1766 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1767 onoff("Link BW Notification Capable", reg, 1768 PCIE_LCAP_LINK_BW_NOTIFY); 1769 onoff("ASPM Optionally Compliance", reg, 1770 PCIE_LCAP_ASPM_COMPLIANCE); 1771 1772 /* Link Control Register */ 1773 reg = regs[o2i(capoff + PCIE_LCSR)]; 1774 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1775 printf(" Active State PM Control: "); 1776 switch (reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S)) { 1777 case 0: 1778 printf("disabled\n"); 1779 break; 1780 case 1: 1781 printf("L0s Entry Enabled\n"); 1782 break; 1783 case 2: 1784 printf("L1 Entry Enabled\n"); 1785 break; 1786 case 3: 1787 printf("L0s and L1 Entry Enabled\n"); 1788 break; 1789 } 1790 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1791 "128bytes", "64bytes"); 1792 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1793 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1794 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1795 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1796 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1797 onoff("Hardware Autonomous Width Disable", reg,PCIE_LCSR_HAWD); 1798 onoff("Link Bandwidth Management Interrupt Enable", reg, 1799 PCIE_LCSR_LBMIE); 1800 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1801 PCIE_LCSR_LABIE); 1802 printf(" DRS Signaling Control: "); 1803 switch (__SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) { 1804 case 0: 1805 printf("not reported\n"); 1806 break; 1807 case 1: 1808 printf("Interrupt Enabled\n"); 1809 break; 1810 case 2: 1811 printf("DRS to FRS Signaling Enabled\n"); 1812 break; 1813 default: 1814 printf("reserved\n"); 1815 break; 1816 } 1817 1818 /* Link Status Register */ 1819 reg = regs[o2i(capoff + PCIE_LCSR)]; 1820 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1821 printf(" Negotiated Link Speed: "); 1822 pci_print_pcie_linkspeed(__SHIFTOUT(reg, PCIE_LCSR_LINKSPEED)); 1823 printf(" Negotiated Link Width: x%u lanes\n", 1824 (unsigned int)__SHIFTOUT(reg, PCIE_LCSR_NLW)); 1825 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1826 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1827 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1828 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1829 onoff("Link Bandwidth Management Status", reg, 1830 PCIE_LCSR_LINK_BW_MGMT); 1831 onoff("Link Autonomous Bandwidth Status", reg, 1832 PCIE_LCSR_LINK_AUTO_BW); 1833 } 1834 1835 if (check_slot == true) { 1836 /* Slot Capability Register */ 1837 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1838 printf(" Slot Capability Register: 0x%08x\n", reg); 1839 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1840 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1841 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1842 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1843 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1844 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1845 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1846 printf(" Slot Power Limit Value: %d\n", 1847 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1848 printf(" Slot Power Limit Scale: %d\n", 1849 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1850 onoff("Electromechanical Interlock Present", reg, 1851 PCIE_SLCAP_EIP); 1852 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1853 printf(" Physical Slot Number: %d\n", 1854 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1855 1856 /* Slot Control Register */ 1857 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1858 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1859 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1860 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1861 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1862 onoff("Presense Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1863 onoff("Command Completed Interrupt Enabled", reg, 1864 PCIE_SLCSR_CCE); 1865 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1866 printf(" Attention Indicator Control: "); 1867 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1868 case 0x0: 1869 printf("reserved\n"); 1870 break; 1871 case 0x1: 1872 printf("on\n"); 1873 break; 1874 case 0x2: 1875 printf("blink\n"); 1876 break; 1877 case 0x3: 1878 printf("off\n"); 1879 break; 1880 } 1881 printf(" Power Indicator Control: "); 1882 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1883 case 0x0: 1884 printf("reserved\n"); 1885 break; 1886 case 0x1: 1887 printf("on\n"); 1888 break; 1889 case 0x2: 1890 printf("blink\n"); 1891 break; 1892 case 0x3: 1893 printf("off\n"); 1894 break; 1895 } 1896 printf(" Power Controller Control: Power %s\n", 1897 reg & PCIE_SLCSR_PCC ? "off" : "on"); 1898 onoff("Electromechanical Interlock Control", 1899 reg, PCIE_SLCSR_EIC); 1900 onoff("Data Link Layer State Changed Enable", reg, 1901 PCIE_SLCSR_DLLSCE); 1902 onoff("Auto Slot Power Limit Disable", reg, 1903 PCIE_SLCSR_AUTOSPLDIS); 1904 1905 /* Slot Status Register */ 1906 printf(" Slot Status Register: 0x%04x\n", reg >> 16); 1907 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1908 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1909 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1910 onoff("Presense Detect Changed", reg, PCIE_SLCSR_PDC); 1911 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1912 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1913 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1914 onoff("Electromechanical Interlock engaged", reg, 1915 PCIE_SLCSR_EIS); 1916 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 1917 } 1918 1919 if (check_rootport == true) { 1920 /* Root Control Register */ 1921 reg = regs[o2i(capoff + PCIE_RCR)]; 1922 printf(" Root Control Register: %04x\n", reg & 0xffff); 1923 onoff("SERR on Correctable Error Enable", reg, 1924 PCIE_RCR_SERR_CER); 1925 onoff("SERR on Non-Fatal Error Enable", reg, 1926 PCIE_RCR_SERR_NFER); 1927 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 1928 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 1929 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 1930 1931 /* Root Capability Register */ 1932 printf(" Root Capability Register: 0x%04x\n", 1933 reg >> 16); 1934 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 1935 1936 /* Root Status Register */ 1937 reg = regs[o2i(capoff + PCIE_RSR)]; 1938 printf(" Root Status Register: 0x%08x\n", reg); 1939 printf(" PME Requester ID: 0x%04x\n", 1940 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1941 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 1942 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 1943 } 1944 1945 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1946 if (pciever < 2) 1947 return; 1948 1949 /* Device Capabilities 2 */ 1950 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1951 printf(" Device Capabilities 2: 0x%08x\n", reg); 1952 printf(" Completion Timeout Ranges Supported: "); 1953 val = reg & PCIE_DCAP2_COMPT_RANGE; 1954 switch (val) { 1955 case 0: 1956 printf("not supported\n"); 1957 break; 1958 default: 1959 for (i = 0; i <= 3; i++) { 1960 if (((val >> i) & 0x01) != 0) 1961 printf("%c", 'A' + i); 1962 } 1963 printf("\n"); 1964 } 1965 onoff("Completion Timeout Disable Supported", reg, 1966 PCIE_DCAP2_COMPT_DIS); 1967 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 1968 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 1969 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 1970 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 1971 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 1972 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 1973 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 1974 printf(" TPH Completer Supported: "); 1975 switch (__SHIFTOUT(reg, PCIE_DCAP2_TPH_COMP)) { 1976 case 0: 1977 printf("Not supportted\n"); 1978 break; 1979 case 1: 1980 printf("TPH\n"); 1981 break; 1982 case 3: 1983 printf("TPH and Extended TPH\n"); 1984 break; 1985 default: 1986 printf("(reserved value)\n"); 1987 break; 1988 1989 } 1990 printf(" LN System CLS: "); 1991 switch (__SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 1992 case 0x0: 1993 printf("Not supported or not in effect\n"); 1994 break; 1995 case 0x1: 1996 printf("64byte cachelines in effect\n"); 1997 break; 1998 case 0x2: 1999 printf("128byte cachelines in effect\n"); 2000 break; 2001 case 0x3: 2002 printf("Reserved\n"); 2003 break; 2004 } 2005 printf(" OBFF Supported: "); 2006 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 2007 case 0x0: 2008 printf("Not supported\n"); 2009 break; 2010 case 0x1: 2011 printf("Message only\n"); 2012 break; 2013 case 0x2: 2014 printf("WAKE# only\n"); 2015 break; 2016 case 0x3: 2017 printf("Both\n"); 2018 break; 2019 } 2020 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 2021 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 2022 val = __SHIFTOUT(reg, PCIE_DCAP2_MAX_EETLP); 2023 printf(" Max End-End TLP Prefixes: %u\n", (val == 0) ? 4 : val); 2024 printf(" Emergency Power Reduction Supported: "); 2025 switch (__SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) { 2026 case 0x0: 2027 printf("Not supported\n"); 2028 break; 2029 case 0x1: 2030 printf("Device Specific mechanism\n"); 2031 break; 2032 case 0x2: 2033 printf("Form Factor spec or Device Specific mechanism\n"); 2034 break; 2035 case 0x3: 2036 printf("Reserved\n"); 2037 break; 2038 } 2039 onoff("Emergency Power Reduction Initialization Required", reg, 2040 PCIE_DCAP2_EMGPWRRED_INI); 2041 onoff("FRS Supported", reg, PCIE_DCAP2_FRS); 2042 2043 /* Device Control 2 */ 2044 reg = regs[o2i(capoff + PCIE_DCSR2)]; 2045 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 2046 printf(" Completion Timeout Value: "); 2047 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 2048 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 2049 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 2050 onoff("AtomicOp Rquester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 2051 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 2052 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 2053 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 2054 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 2055 onoff("Emergency Power Reduction Request", reg, 2056 PCIE_DCSR2_EMGPWRRED_REQ); 2057 printf(" OBFF: "); 2058 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 2059 case 0x0: 2060 printf("Disabled\n"); 2061 break; 2062 case 0x1: 2063 printf("Enabled with Message Signaling Variation A\n"); 2064 break; 2065 case 0x2: 2066 printf("Enabled with Message Signaling Variation B\n"); 2067 break; 2068 case 0x3: 2069 printf("Enabled using WAKE# signaling\n"); 2070 break; 2071 } 2072 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 2073 2074 if (check_link) { 2075 bool drs_supported = false; 2076 2077 /* Link Capability 2 */ 2078 reg = regs[o2i(capoff + PCIE_LCAP2)]; 2079 /* If the vector is 0, LCAP2 is not implemented */ 2080 if ((reg & PCIE_LCAP2_SUP_LNKSV) != 0) { 2081 printf(" Link Capabilities 2: 0x%08x\n", reg); 2082 printf(" Supported Link Speeds Vector:"); 2083 pci_print_pcie_linkspeedvector( 2084 __SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV)); 2085 printf("\n"); 2086 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 2087 printf(" " 2088 "Lower SKP OS Generation Supported Speed Vector:"); 2089 pci_print_pcie_linkspeedvector( 2090 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV)); 2091 printf("\n"); 2092 printf(" " 2093 "Lower SKP OS Reception Supported Speed Vector:"); 2094 pci_print_pcie_linkspeedvector( 2095 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV)); 2096 printf("\n"); 2097 onoff("DRS Supported", reg, PCIE_LCAP2_DRS); 2098 drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false; 2099 } 2100 2101 /* Link Control 2 */ 2102 reg = regs[o2i(capoff + PCIE_LCSR2)]; 2103 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 2104 printf(" Target Link Speed: "); 2105 pci_print_pcie_linkspeed(__SHIFTOUT(reg, 2106 PCIE_LCSR2_TGT_LSPEED)); 2107 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 2108 onoff("HW Autonomous Speed Disabled", reg, 2109 PCIE_LCSR2_HW_AS_DIS); 2110 printf(" Selectable De-emphasis: "); 2111 pci_print_pcie_link_deemphasis( 2112 __SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP)); 2113 printf("\n"); 2114 printf(" Transmit Margin: %u\n", 2115 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 2116 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 2117 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 2118 printf(" Compliance Present/De-emphasis: "); 2119 pci_print_pcie_link_deemphasis( 2120 __SHIFTOUT(reg, PCIE_LCSR2_COMP_DEEMP)); 2121 printf("\n"); 2122 2123 /* Link Status 2 */ 2124 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 2125 printf(" Current De-emphasis Level: "); 2126 pci_print_pcie_link_deemphasis( 2127 __SHIFTOUT(reg, PCIE_LCSR2_DEEMP_LVL)); 2128 printf("\n"); 2129 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 2130 onoff("Equalization Phase 1 Successful", reg, 2131 PCIE_LCSR2_EQP1_SUC); 2132 onoff("Equalization Phase 2 Successful", reg, 2133 PCIE_LCSR2_EQP2_SUC); 2134 onoff("Equalization Phase 3 Successful", reg, 2135 PCIE_LCSR2_EQP3_SUC); 2136 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 2137 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD); 2138 if (drs_supported) { 2139 printf(" Downstream Component Presence: "); 2140 switch (__SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) { 2141 case PCIE_DSCOMPN_DOWN_NOTDETERM: 2142 printf("Link Down - Presence Not" 2143 " Determined\n"); 2144 break; 2145 case PCIE_DSCOMPN_DOWN_NOTPRES: 2146 printf("Link Down - Component Not Present\n"); 2147 break; 2148 case PCIE_DSCOMPN_DOWN_PRES: 2149 printf("Link Down - Component Present\n"); 2150 break; 2151 case PCIE_DSCOMPN_UP_PRES: 2152 printf("Link Up - Component Present\n"); 2153 break; 2154 case PCIE_DSCOMPN_UP_PRES_DRS: 2155 printf("Link Up - Component Present and DRS" 2156 " received\n"); 2157 break; 2158 default: 2159 printf("reserved\n"); 2160 break; 2161 } 2162 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV); 2163 } 2164 } 2165 2166 /* Slot Capability 2 */ 2167 /* Slot Control 2 */ 2168 /* Slot Status 2 */ 2169 } 2170 2171 static void 2172 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 2173 { 2174 pcireg_t reg; 2175 2176 printf("\n MSI-X Capability Register\n"); 2177 2178 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2179 printf(" Message Control register: 0x%04x\n", 2180 (reg >> 16) & 0xff); 2181 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 2182 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 2183 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 2184 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 2185 printf(" Table offset register: 0x%08x\n", reg); 2186 printf(" Table offset: 0x%08x\n", 2187 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 2188 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 2189 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 2190 printf(" Pending bit array register: 0x%08x\n", reg); 2191 printf(" Pending bit array offset: 0x%08x\n", 2192 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 2193 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 2194 } 2195 2196 static void 2197 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 2198 { 2199 pcireg_t reg; 2200 2201 printf("\n Serial ATA Capability Register\n"); 2202 2203 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2204 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 2205 printf(" Revision: %u.%u\n", 2206 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 2207 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 2208 2209 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 2210 2211 printf(" BAR Register: 0x%08x\n", reg); 2212 printf(" Register location: "); 2213 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 2214 printf("in config space\n"); 2215 else { 2216 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 2217 printf(" BAR offset: 0x%08x\n", 2218 (pcireg_t)__SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 2219 } 2220 } 2221 2222 static void 2223 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 2224 { 2225 pcireg_t reg; 2226 2227 printf("\n Advanced Features Capability Register\n"); 2228 2229 reg = regs[o2i(capoff + PCI_AFCAPR)]; 2230 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 2231 printf(" AF Structure Length: 0x%02x\n", 2232 (pcireg_t)__SHIFTOUT(reg, PCI_AF_LENGTH)); 2233 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 2234 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 2235 reg = regs[o2i(capoff + PCI_AFCSR)]; 2236 printf(" AF Control register: 0x%02x\n", reg & 0xff); 2237 /* 2238 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 2239 * and it's always 0 on read 2240 */ 2241 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 2242 onoff("Transaction Pending", reg, PCI_AFSR_TP); 2243 } 2244 2245 static struct { 2246 pcireg_t cap; 2247 const char *name; 2248 void (*printfunc)(const pcireg_t *, int); 2249 } pci_captab[] = { 2250 { PCI_CAP_RESERVED0, "reserved", NULL }, 2251 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 2252 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 2253 { PCI_CAP_VPD, "VPD", NULL }, 2254 { PCI_CAP_SLOTID, "SlotID", NULL }, 2255 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 2256 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 2257 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2258 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2259 { PCI_CAP_VENDSPEC, "Vendor-specific", 2260 pci_conf_print_vendspec_cap }, 2261 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2262 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2263 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2264 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2265 pci_conf_print_subsystem_cap }, 2266 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2267 { PCI_CAP_SECURE, "Secure Device", NULL }, 2268 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2269 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2270 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2271 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2272 { PCI_CAP_EA, "Enhanced Allocation", NULL } 2273 }; 2274 2275 static int 2276 pci_conf_find_cap(const pcireg_t *regs, int capoff, unsigned int capid, 2277 int *offsetp) 2278 { 2279 pcireg_t rval; 2280 int off; 2281 2282 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2283 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2284 rval = regs[o2i(off)]; 2285 if (capid == PCI_CAPLIST_CAP(rval)) { 2286 if (offsetp != NULL) 2287 *offsetp = off; 2288 return 1; 2289 } 2290 } 2291 return 0; 2292 } 2293 2294 static void 2295 pci_conf_print_caplist( 2296 #ifdef _KERNEL 2297 pci_chipset_tag_t pc, pcitag_t tag, 2298 #endif 2299 const pcireg_t *regs, int capoff) 2300 { 2301 int off; 2302 pcireg_t foundcap; 2303 pcireg_t rval; 2304 bool foundtable[__arraycount(pci_captab)]; 2305 unsigned int i; 2306 2307 /* Clear table */ 2308 for (i = 0; i < __arraycount(pci_captab); i++) 2309 foundtable[i] = false; 2310 2311 /* Print capability register's offset and the type first */ 2312 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2313 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2314 rval = regs[o2i(off)]; 2315 printf(" Capability register at 0x%02x\n", off); 2316 2317 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2318 foundcap = PCI_CAPLIST_CAP(rval); 2319 if (foundcap < __arraycount(pci_captab)) { 2320 printf("%s)\n", pci_captab[foundcap].name); 2321 /* Mark as found */ 2322 foundtable[foundcap] = true; 2323 } else 2324 printf("unknown)\n"); 2325 } 2326 2327 /* 2328 * And then, print the detail of each capability registers 2329 * in capability value's order. 2330 */ 2331 for (i = 0; i < __arraycount(pci_captab); i++) { 2332 if (foundtable[i] == false) 2333 continue; 2334 2335 /* 2336 * The type was found. Search capability list again and 2337 * print all capabilities that the capabiliy type is 2338 * the same. This is required because some capabilities 2339 * appear multiple times (e.g. HyperTransport capability). 2340 */ 2341 #if 0 2342 if (pci_conf_find_cap(regs, capoff, i, &off)) { 2343 rval = regs[o2i(off)]; 2344 if (pci_captab[i].printfunc != NULL) 2345 pci_captab[i].printfunc(regs, off); 2346 } 2347 #else 2348 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2349 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2350 rval = regs[o2i(off)]; 2351 if ((PCI_CAPLIST_CAP(rval) == i) 2352 && (pci_captab[i].printfunc != NULL)) 2353 pci_captab[i].printfunc(regs, off); 2354 } 2355 #endif 2356 } 2357 } 2358 2359 /* Extended Capability */ 2360 2361 static void 2362 pci_conf_print_aer_cap_uc(pcireg_t reg) 2363 { 2364 2365 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2366 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2367 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2368 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP); 2369 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2370 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2371 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2372 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2373 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2374 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2375 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2376 onoff("Unsupported Request Error", reg, 2377 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2378 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2379 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2380 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2381 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2382 onoff("TLP Prefix Blocked Error", reg, 2383 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2384 onoff("Poisoned TLP Egress Blocked", reg, 2385 PCI_AER_UC_POISONTLP_EGRESS_BLOCKED); 2386 } 2387 2388 static void 2389 pci_conf_print_aer_cap_cor(pcireg_t reg) 2390 { 2391 2392 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2393 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2394 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2395 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2396 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2397 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2398 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2399 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2400 } 2401 2402 static void 2403 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2404 { 2405 2406 printf(" First Error Pointer: 0x%04x\n", 2407 (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2408 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2409 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2410 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2411 onoff("ECRC Check Enab", reg, PCI_AER_ECRC_CHECK_ENABLE); 2412 onoff("Multiple Header Recording Capable", reg, 2413 PCI_AER_MULT_HDR_CAPABLE); 2414 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE); 2415 onoff("Completion Timeout Prefix/Header Log Capable", reg, 2416 PCI_AER_COMPTOUTPRFXHDRLOG_CAP); 2417 2418 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2419 if (!tlp_prefix_log) 2420 return; 2421 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2422 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2423 } 2424 2425 static void 2426 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2427 { 2428 2429 onoff("Correctable Error Reporting Enable", reg, 2430 PCI_AER_ROOTERR_COR_ENABLE); 2431 onoff("Non-Fatal Error Reporting Enable", reg, 2432 PCI_AER_ROOTERR_NF_ENABLE); 2433 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2434 } 2435 2436 static void 2437 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2438 { 2439 2440 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2441 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2442 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2443 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2444 PCI_AER_ROOTERR_MULTI_UC_ERR); 2445 onoff("First Uncorrectable Fatal", reg,PCI_AER_ROOTERR_FIRST_UC_FATAL); 2446 onoff("Non-Fatal Error Messages Received", reg,PCI_AER_ROOTERR_NF_ERR); 2447 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2448 printf(" Advanced Error Interrupt Message Number: 0x%02x\n", 2449 (unsigned int)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2450 } 2451 2452 static void 2453 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2454 { 2455 2456 printf(" Correctable Source ID: 0x%04x\n", 2457 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2458 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2459 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2460 } 2461 2462 static void 2463 pci_conf_print_aer_cap(const pcireg_t *regs, int capoff, int extcapoff) 2464 { 2465 pcireg_t reg; 2466 int pcie_capoff; 2467 int pcie_devtype = -1; 2468 bool tlp_prefix_log = false; 2469 2470 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2471 reg = regs[o2i(pcie_capoff)]; 2472 pcie_devtype = PCIE_XCAP_TYPE(reg); 2473 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2474 if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2475 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2476 /* End-End TLP Prefix Supported */ 2477 if (reg & PCIE_DCAP2_EETLP_PREF) { 2478 tlp_prefix_log = true; 2479 } 2480 } 2481 } 2482 2483 printf("\n Advanced Error Reporting Register\n"); 2484 2485 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2486 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2487 pci_conf_print_aer_cap_uc(reg); 2488 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2489 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2490 pci_conf_print_aer_cap_uc(reg); 2491 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2492 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2493 pci_conf_print_aer_cap_uc(reg); 2494 2495 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2496 printf(" Correctable Error Status register: 0x%08x\n", reg); 2497 pci_conf_print_aer_cap_cor(reg); 2498 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2499 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2500 pci_conf_print_aer_cap_cor(reg); 2501 2502 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2503 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2504 reg); 2505 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2506 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2507 printf(" Header Log register:\n"); 2508 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2509 extcapoff + PCI_AER_ROOTERR_CMD); 2510 2511 switch (pcie_devtype) { 2512 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ 2513 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ 2514 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2515 printf(" Root Error Command register: 0x%08x\n", reg); 2516 pci_conf_print_aer_cap_rooterr_cmd(reg); 2517 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2518 printf(" Root Error Status register: 0x%08x\n", reg); 2519 pci_conf_print_aer_cap_rooterr_status(reg); 2520 2521 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2522 printf(" Error Source Identification: 0x%04x\n", reg); 2523 pci_conf_print_aer_cap_errsrc_id(reg); 2524 break; 2525 } 2526 2527 if (tlp_prefix_log) { 2528 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2529 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2530 } 2531 } 2532 2533 static void 2534 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2535 pcireg_t parbsel, int parbsize) 2536 { 2537 pcireg_t reg; 2538 int num = 16 << parbsel; 2539 int num_per_reg = sizeof(pcireg_t) / parbsize; 2540 int i, j; 2541 2542 /* First, dump the table */ 2543 for (i = 0; i < num; i += num_per_reg) { 2544 reg = regs[o2i(off + i / num_per_reg)]; 2545 printf(" %s Arbitration Table: 0x%08x\n", name, reg); 2546 } 2547 /* And then, decode each entry */ 2548 for (i = 0; i < num; i += num_per_reg) { 2549 reg = regs[o2i(off + i / num_per_reg)]; 2550 for (j = 0; j < num_per_reg; j++) 2551 printf(" Phase[%d]: %d\n", j, reg); 2552 } 2553 } 2554 2555 static void 2556 pci_conf_print_vc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2557 { 2558 pcireg_t reg, n; 2559 int parbtab, parbsize; 2560 pcireg_t parbsel; 2561 int varbtab, varbsize; 2562 pcireg_t varbsel; 2563 int i, count; 2564 2565 printf("\n Virtual Channel Register\n"); 2566 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2567 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2568 count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2569 printf(" Extended VC Count: %d\n", count); 2570 n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2571 printf(" Low Priority Extended VC Count: %u\n", n); 2572 n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2573 printf(" Reference Clock: %s\n", 2574 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 2575 parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2576 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2577 2578 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 2579 printf(" Port VC Capability register 2: 0x%08x\n", reg); 2580 onoff("Hardware fixed arbitration scheme", 2581 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 2582 onoff("WRR arbitration with 32 phases", 2583 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 2584 onoff("WRR arbitration with 64 phases", 2585 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 2586 onoff("WRR arbitration with 128 phases", 2587 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 2588 varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 2589 printf(" VC Arbitration Table Offset: 0x%x\n", varbtab); 2590 2591 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 2592 printf(" Port VC Control register: 0x%04x\n", reg); 2593 varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 2594 printf(" VC Arbitration Select: 0x%x\n", varbsel); 2595 2596 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 2597 printf(" Port VC Status register: 0x%04x\n", reg); 2598 onoff("VC Arbitration Table Status", 2599 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 2600 2601 for (i = 0; i < count + 1; i++) { 2602 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 2603 printf(" VC number %d\n", i); 2604 printf(" VC Resource Capability Register: 0x%08x\n", reg); 2605 onoff(" Non-configurable Hardware fixed arbitration scheme", 2606 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 2607 onoff(" WRR arbitration with 32 phases", 2608 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 2609 onoff(" WRR arbitration with 64 phases", 2610 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 2611 onoff(" WRR arbitration with 128 phases", 2612 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 2613 onoff(" Time-based WRR arbitration with 128 phases", 2614 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 2615 onoff(" WRR arbitration with 256 phases", 2616 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 2617 onoff(" Advanced Packet Switching", 2618 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 2619 onoff(" Reject Snoop Transaction", 2620 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 2621 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 2622 printf(" Maximum Time Slots: %d\n", n); 2623 parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S; 2624 printf(" Port Arbitration Table offset: 0x%02x\n", 2625 parbtab); 2626 2627 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 2628 printf(" VC Resource Control Register: 0x%08x\n", reg); 2629 printf(" TC/VC Map: 0x%02x\n", 2630 (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 2631 /* 2632 * The load Port Arbitration Table bit is used to update 2633 * the Port Arbitration logic and it's always 0 on read, so 2634 * we don't print it. 2635 */ 2636 parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 2637 printf(" Port Arbitration Select: 0x%x\n", parbsel); 2638 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 2639 printf(" VC ID %d\n", n); 2640 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 2641 2642 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 2643 printf(" VC Resource Status Register: 0x%08x\n", reg); 2644 onoff(" Port Arbitration Table Status", 2645 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 2646 onoff(" VC Negotiation Pending", 2647 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 2648 2649 if ((parbtab != 0) && (parbsel != 0)) 2650 pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab, 2651 "Port", parbsel, parbsize); 2652 } 2653 2654 varbsize = 8; 2655 if ((varbtab != 0) && (varbsel != 0)) 2656 pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab, 2657 " VC", varbsel, varbsize); 2658 } 2659 2660 static void 2661 pci_conf_print_pwrbdgt_base_power(uint8_t base, int scale) 2662 { 2663 int sdiv = 1; 2664 const char *s; 2665 int i; 2666 2667 if (base <= 0xef) { 2668 for (i = scale; i > 0; i--) 2669 sdiv *= 10; 2670 printf("%hhu", base / sdiv); 2671 if (scale != 0) { 2672 printf(".%hhu", base % sdiv); 2673 } 2674 printf ("W\n"); 2675 return; 2676 } 2677 switch (base) { 2678 case 0xf0: 2679 s = "239W < x <= 250W"; 2680 break; 2681 case 0xf1: 2682 s = "250W < x <= 275W"; 2683 break; 2684 case 0xf2: 2685 s = "275W < x <= 300W"; 2686 break; 2687 default: 2688 s = "reserved for above 300W"; 2689 break; 2690 } 2691 printf("%s\n", s); 2692 } 2693 2694 static const char * 2695 pci_conf_print_pwrbdgt_type(uint8_t reg) 2696 { 2697 2698 switch (reg) { 2699 case 0x00: 2700 return "PME Aux"; 2701 case 0x01: 2702 return "Auxilary"; 2703 case 0x02: 2704 return "Idle"; 2705 case 0x03: 2706 return "Sustained"; 2707 case 0x04: 2708 return "Sustained (Emergency Power Reduction)"; 2709 case 0x05: 2710 return "Maximum (Emergency Power Reduction)"; 2711 case 0x07: 2712 return "Maximum"; 2713 default: 2714 return "Unknown"; 2715 } 2716 } 2717 2718 static const char * 2719 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 2720 { 2721 2722 switch (reg) { 2723 case 0x00: 2724 return "Power(12V)"; 2725 case 0x01: 2726 return "Power(3.3V)"; 2727 case 0x02: 2728 return "Power(1.5V or 1.8V)"; 2729 case 0x07: 2730 return "Thermal"; 2731 default: 2732 return "Unknown"; 2733 } 2734 } 2735 2736 static void 2737 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff) 2738 { 2739 pcireg_t reg; 2740 unsigned int scale; 2741 2742 printf("\n Power Budgeting\n"); 2743 2744 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 2745 printf(" Data Select register: 0x%08x\n", reg); 2746 2747 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 2748 printf(" Data register: 0x%08x\n", reg); 2749 scale = __SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE); 2750 printf(" Base Power: "); 2751 pci_conf_print_pwrbdgt_base_power((uint8_t)reg, scale); 2752 printf(" PM Sub State: 0x%hhx\n", 2753 (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 2754 printf(" PM State: D%u\n", 2755 (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 2756 printf(" Type: %s\n", 2757 pci_conf_print_pwrbdgt_type( 2758 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 2759 printf(" Power Rail: %s\n", 2760 pci_conf_print_pwrbdgt_pwrrail( 2761 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 2762 2763 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 2764 printf(" Power Budget Capability register: 0x%08x\n", reg); 2765 onoff("System Allocated", 2766 reg, PCI_PWRBDGT_CAP_SYSALLOC); 2767 } 2768 2769 static const char * 2770 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 2771 { 2772 2773 switch (type) { 2774 case 0x00: 2775 return "Configuration Space Element"; 2776 case 0x01: 2777 return "System Egress Port or internal sink (memory)"; 2778 case 0x02: 2779 return "Internal Root Complex Link"; 2780 default: 2781 return "Unknown"; 2782 } 2783 } 2784 2785 static void 2786 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int capoff, int extcapoff) 2787 { 2788 pcireg_t reg; 2789 unsigned char nent, linktype; 2790 int i; 2791 2792 printf("\n Root Complex Link Declaration\n"); 2793 2794 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 2795 printf(" Element Self Description Register: 0x%08x\n", reg); 2796 printf(" Element Type: %s\n", 2797 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 2798 nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 2799 printf(" Number of Link Entries: %hhu\n", nent); 2800 printf(" Component ID: %hhu\n", 2801 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 2802 printf(" Port Number: %hhu\n", 2803 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 2804 for (i = 0; i < nent; i++) { 2805 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 2806 printf(" Link Entry %d:\n", i + 1); 2807 printf(" Link Description Register: 0x%08x\n", reg); 2808 onoff(" Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID); 2809 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 2810 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 2811 "Configuration Space", "Memory-Mapped Space"); 2812 onoff(" Associated RCRB Header", reg, 2813 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 2814 printf(" Target Component ID: %hhu\n", 2815 (unsigned char)__SHIFTOUT(reg, 2816 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 2817 printf(" Target Port Number: %hhu\n", 2818 (unsigned char)__SHIFTOUT(reg, 2819 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 2820 2821 if (linktype == 0) { 2822 /* Memory-Mapped Space */ 2823 reg = regs[o2i(extcapoff 2824 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 2825 printf(" Link Address Low Register: 0x%08x\n", 2826 reg); 2827 reg = regs[o2i(extcapoff 2828 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 2829 printf(" Link Address High Register: 0x%08x\n", 2830 reg); 2831 } else { 2832 unsigned int nb; 2833 pcireg_t lo, hi; 2834 2835 /* Configuration Space */ 2836 lo = regs[o2i(extcapoff 2837 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 2838 printf(" Configuration Space Low Register: " 2839 "0x%08x\n", lo); 2840 hi = regs[o2i(extcapoff 2841 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 2842 printf(" Configuration Space High Register: " 2843 "0x%08x\n", hi); 2844 nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 2845 printf(" N: %u\n", nb); 2846 printf(" Func: %hhu\n", 2847 (unsigned char)__SHIFTOUT(lo, 2848 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 2849 printf(" Dev: %hhu\n", 2850 (unsigned char)__SHIFTOUT(lo, 2851 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 2852 printf(" Bus: %hhu\n", 2853 (unsigned char)__SHIFTOUT(lo, 2854 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 2855 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 2856 printf(" Configuration Space Base Address: " 2857 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 2858 } 2859 } 2860 } 2861 2862 /* XXX pci_conf_print_rclink_ctl_cap */ 2863 2864 static void 2865 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2866 { 2867 pcireg_t reg; 2868 2869 printf("\n Root Complex Event Collector Association\n"); 2870 2871 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 2872 printf(" Association Bitmap for Root Complex Integrated Devices:" 2873 " 0x%08x\n", reg); 2874 } 2875 2876 /* XXX pci_conf_print_mfvc_cap */ 2877 /* XXX pci_conf_print_vc2_cap */ 2878 /* XXX pci_conf_print_rcrb_cap */ 2879 /* XXX pci_conf_print_vendor_cap */ 2880 /* XXX pci_conf_print_cac_cap */ 2881 2882 static void 2883 pci_conf_print_acs_cap(const pcireg_t *regs, int capoff, int extcapoff) 2884 { 2885 pcireg_t reg, cap, ctl; 2886 unsigned int size, i; 2887 2888 printf("\n Access Control Services\n"); 2889 2890 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 2891 cap = reg & 0xffff; 2892 ctl = reg >> 16; 2893 printf(" ACS Capability register: 0x%08x\n", cap); 2894 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 2895 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 2896 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 2897 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 2898 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 2899 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 2900 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 2901 size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 2902 if (size == 0) 2903 size = 256; 2904 printf(" Egress Control Vector Size: %u\n", size); 2905 printf(" ACS Control register: 0x%08x\n", ctl); 2906 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 2907 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 2908 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 2909 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 2910 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 2911 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 2912 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 2913 2914 /* 2915 * If the P2P Egress Control Capability bit is 0, ignore the Egress 2916 * Control vector. 2917 */ 2918 if ((cap & PCI_ACS_CAP_E) == 0) 2919 return; 2920 for (i = 0; i < size; i += 32) 2921 printf(" Egress Control Vector [%u..%u]: 0x%08x\n", i + 31, 2922 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 2923 } 2924 2925 static void 2926 pci_conf_print_ari_cap(const pcireg_t *regs, int capoff, int extcapoff) 2927 { 2928 pcireg_t reg, cap, ctl; 2929 2930 printf("\n Alternative Routing-ID Interpretation Register\n"); 2931 2932 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2933 cap = reg & 0xffff; 2934 ctl = reg >> 16; 2935 printf(" Capability register: 0x%08x\n", cap); 2936 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 2937 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 2938 printf(" Next Function Number: %u\n", 2939 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 2940 printf(" Control register: 0x%08x\n", ctl); 2941 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 2942 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 2943 printf(" Function Group: %u\n", 2944 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 2945 } 2946 2947 static void 2948 pci_conf_print_ats_cap(const pcireg_t *regs, int capoff, int extcapoff) 2949 { 2950 pcireg_t reg, cap, ctl; 2951 unsigned int num; 2952 2953 printf("\n Address Translation Services\n"); 2954 2955 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2956 cap = reg & 0xffff; 2957 ctl = reg >> 16; 2958 printf(" Capability register: 0x%04x\n", cap); 2959 num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 2960 if (num == 0) 2961 num = 32; 2962 printf(" Invalidate Queue Depth: %u\n", num); 2963 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 2964 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 2965 2966 printf(" Control register: 0x%04x\n", ctl); 2967 printf(" Smallest Translation Unit: %u\n", 2968 (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU)); 2969 onoff("Enable", reg, PCI_ATS_CTL_EN); 2970 } 2971 2972 static void 2973 pci_conf_print_sernum_cap(const pcireg_t *regs, int capoff, int extcapoff) 2974 { 2975 pcireg_t lo, hi; 2976 2977 printf("\n Device Serial Number Register\n"); 2978 2979 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 2980 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 2981 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 2982 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 2983 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 2984 } 2985 2986 static void 2987 pci_conf_print_sriov_cap(const pcireg_t *regs, int capoff, int extcapoff) 2988 { 2989 char buf[sizeof("99999 MB")]; 2990 pcireg_t reg; 2991 pcireg_t total_vfs; 2992 int i; 2993 bool first; 2994 2995 printf("\n Single Root IO Virtualization Register\n"); 2996 2997 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 2998 printf(" Capabilities register: 0x%08x\n", reg); 2999 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 3000 onoff("ARI Capable Hierarchy Preserved", reg, 3001 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 3002 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 3003 printf(" VF Migration Interrupt Message Number: 0x%03x\n", 3004 (pcireg_t)__SHIFTOUT(reg, 3005 PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 3006 } 3007 3008 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 3009 printf(" Control register: 0x%04x\n", reg); 3010 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 3011 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 3012 onoff("VF Migration Interrupt Enable", reg, 3013 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 3014 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 3015 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 3016 3017 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 3018 printf(" Status register: 0x%04x\n", reg); 3019 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 3020 3021 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 3022 printf(" InitialVFs register: 0x%04x\n", reg); 3023 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 3024 printf(" TotalVFs register: 0x%04x\n", reg); 3025 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 3026 printf(" NumVFs register: 0x%04x\n", reg); 3027 3028 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 3029 printf(" Function Dependency Link register: 0x%04x\n", reg); 3030 3031 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 3032 printf(" First VF Offset register: 0x%04x\n", reg); 3033 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 3034 printf(" VF Stride register: 0x%04x\n", reg); 3035 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_DID)] >> 16; 3036 printf(" Device ID: 0x%04x\n", reg); 3037 3038 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 3039 printf(" Supported Page Sizes register: 0x%08x\n", reg); 3040 printf(" Supported Page Size:"); 3041 for (i = 0, first = true; i < 32; i++) { 3042 if (reg & __BIT(i)) { 3043 #ifdef _KERNEL 3044 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 3045 #else 3046 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 3047 HN_AUTOSCALE, 0); 3048 #endif 3049 printf("%s %s", first ? "" : ",", buf); 3050 first = false; 3051 } 3052 } 3053 printf("\n"); 3054 3055 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 3056 printf(" System Page Sizes register: 0x%08x\n", reg); 3057 printf(" Page Size: "); 3058 if (reg != 0) { 3059 #ifdef _KERNEL 3060 format_bytes(buf, sizeof(buf), 1LL << (ffs(reg) + 12)); 3061 #else 3062 humanize_number(buf, sizeof(buf), 1LL << (ffs(reg) + 12), "B", 3063 HN_AUTOSCALE, 0); 3064 #endif 3065 printf("%s", buf); 3066 } else { 3067 printf("unknown"); 3068 } 3069 printf("\n"); 3070 3071 for (i = 0; i < 6; i++) { 3072 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 3073 printf(" VF BAR%d register: 0x%08x\n", i, reg); 3074 } 3075 3076 if (total_vfs > 0) { 3077 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 3078 printf(" VF Migration State Array Offset register: 0x%08x\n", 3079 reg); 3080 printf(" VF Migration State Offset: 0x%08x\n", 3081 (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 3082 i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 3083 printf(" VF Migration State BIR: "); 3084 if (i >= 0 && i <= 5) { 3085 printf("BAR%d", i); 3086 } else { 3087 printf("unknown BAR (%d)", i); 3088 } 3089 printf("\n"); 3090 } 3091 } 3092 3093 /* XXX pci_conf_print_mriov_cap */ 3094 3095 static void 3096 pci_conf_print_multicast_cap(const pcireg_t *regs, int capoff, int extcapoff) 3097 { 3098 pcireg_t reg, cap, ctl; 3099 pcireg_t regl, regh; 3100 uint64_t addr; 3101 int n; 3102 3103 printf("\n Multicast\n"); 3104 3105 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 3106 cap = reg & 0xffff; 3107 ctl = reg >> 16; 3108 printf(" Capability Register: 0x%04x\n", cap); 3109 printf(" Max Group: %u\n", 3110 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 3111 3112 /* Endpoint Only */ 3113 n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 3114 if (n > 0) 3115 printf(" Windw Size Requested: %d\n", 1 << (n - 1)); 3116 3117 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 3118 3119 printf(" Control Register: 0x%04x\n", ctl); 3120 printf(" Num Group: %u\n", 3121 (unsigned int)__SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 3122 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 3123 3124 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 3125 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 3126 printf(" Base Address Register 0: 0x%08x\n", regl); 3127 printf(" Base Address Register 1: 0x%08x\n", regh); 3128 printf(" Index Position: %u\n", 3129 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 3130 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 3131 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 3132 3133 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 3134 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 3135 printf(" Receive Register 0: 0x%08x\n", regl); 3136 printf(" Receive Register 1: 0x%08x\n", regh); 3137 3138 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 3139 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 3140 printf(" Block All Register 0: 0x%08x\n", regl); 3141 printf(" Block All Register 1: 0x%08x\n", regh); 3142 3143 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 3144 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 3145 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 3146 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 3147 3148 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 3149 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 3150 printf(" Overlay BAR 0: 0x%08x\n", regl); 3151 printf(" Overlay BAR 1: 0x%08x\n", regh); 3152 3153 n = regl & PCI_MCAST_OVERLAYL_SIZE; 3154 printf(" Overlay Size: "); 3155 if (n >= 6) 3156 printf("%d\n", n); 3157 else 3158 printf("off\n"); 3159 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 3160 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 3161 } 3162 3163 static void 3164 pci_conf_print_page_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3165 { 3166 pcireg_t reg, ctl, sta; 3167 3168 printf("\n Page Request\n"); 3169 3170 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 3171 ctl = reg & 0xffff; 3172 sta = reg >> 16; 3173 printf(" Control Register: 0x%04x\n", ctl); 3174 onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E); 3175 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 3176 3177 printf(" Status Register: 0x%04x\n", sta); 3178 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 3179 onoff("Unexpected Page Request Group Index", reg, 3180 PCI_PAGE_REQ_STA_UPRGI); 3181 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 3182 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 3183 3184 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 3185 printf(" Outstanding Page Request Capacity: %u\n", reg); 3186 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 3187 printf(" Outstanding Page Request Allocation: %u\n", reg); 3188 } 3189 3190 /* XXX pci_conf_print_amd_cap */ 3191 3192 #define MEM_PBUFSIZE sizeof("999GB") 3193 3194 static void 3195 pci_conf_print_resizbar_cap(const pcireg_t *regs, int capoff, int extcapoff) 3196 { 3197 pcireg_t cap, ctl; 3198 unsigned int bars, i, n; 3199 char pbuf[MEM_PBUFSIZE]; 3200 3201 printf("\n Resizable BAR\n"); 3202 3203 /* Get Number of Resizable BARs */ 3204 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))]; 3205 bars = __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR); 3206 printf(" Number of Resizable BARs: "); 3207 if (bars <= 6) 3208 printf("%u\n", bars); 3209 else { 3210 printf("incorrect (%u)\n", bars); 3211 return; 3212 } 3213 3214 for (n = 0; n < 6; n++) { 3215 cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))]; 3216 printf(" Capability register(%u): 0x%08x\n", n, cap); 3217 if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0) 3218 continue; /* Not Used */ 3219 printf(" Acceptable BAR sizes:"); 3220 for (i = 4; i <= 23; i++) { 3221 if ((cap & (1 << i)) != 0) { 3222 humanize_number(pbuf, MEM_PBUFSIZE, 3223 (int64_t)1024 * 1024 << (i - 4), "B", 3224 #ifdef _KERNEL 3225 1); 3226 #else 3227 HN_AUTOSCALE, HN_NOSPACE); 3228 #endif 3229 printf(" %s", pbuf); 3230 } 3231 } 3232 printf("\n"); 3233 3234 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))]; 3235 printf(" Control register(%u): 0x%08x\n", n, ctl); 3236 printf(" BAR Index: %u\n", 3237 (unsigned int)__SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX)); 3238 humanize_number(pbuf, MEM_PBUFSIZE, 3239 (int64_t)1024 * 1024 3240 << __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ), 3241 "B", 3242 #ifdef _KERNEL 3243 1); 3244 #else 3245 HN_AUTOSCALE, HN_NOSPACE); 3246 #endif 3247 printf(" BAR Size: %s\n", pbuf); 3248 } 3249 } 3250 3251 static void 3252 pci_conf_print_dpa_cap(const pcireg_t *regs, int capoff, int extcapoff) 3253 { 3254 pcireg_t reg; 3255 unsigned int substmax, i; 3256 3257 printf("\n Dynamic Power Allocation\n"); 3258 3259 reg = regs[o2i(extcapoff + PCI_DPA_CAP)]; 3260 printf(" Capability register: 0x%08x\n", reg); 3261 substmax = __SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX); 3262 printf(" Substate Max: %u\n", substmax); 3263 printf(" Transition Latency Unit: "); 3264 switch (__SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) { 3265 case 0: 3266 printf("1ms\n"); 3267 break; 3268 case 1: 3269 printf("10ms\n"); 3270 break; 3271 case 2: 3272 printf("100ms\n"); 3273 break; 3274 default: 3275 printf("reserved\n"); 3276 break; 3277 } 3278 printf(" Power Allocation Scale: "); 3279 switch (__SHIFTOUT(reg, PCI_DPA_CAP_PAS)) { 3280 case 0: 3281 printf("10.0x\n"); 3282 break; 3283 case 1: 3284 printf("1.0x\n"); 3285 break; 3286 case 2: 3287 printf("0.1x\n"); 3288 break; 3289 case 3: 3290 printf("0.01x\n"); 3291 break; 3292 } 3293 printf(" Transition Latency Value 0: %u\n", 3294 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY0)); 3295 printf(" Transition Latency Value 1: %u\n", 3296 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY1)); 3297 3298 reg = regs[o2i(extcapoff + PCI_DPA_LATIND)]; 3299 printf(" Latency Indicatior register: 0x%08x\n", reg); 3300 3301 reg = regs[o2i(extcapoff + PCI_DPA_CS)]; 3302 printf(" Status register: 0x%04x\n", reg & 0xffff); 3303 printf(" Substate Status: 0x%02x\n", 3304 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT)); 3305 onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN); 3306 printf(" Control register: 0x%04x\n", reg >> 16); 3307 printf(" Substate Control: 0x%02x\n", 3308 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL)); 3309 3310 for (i = 0; i <= substmax; i++) 3311 printf(" Substate Power Allocation register %d: 0x%02x\n", 3312 i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff)); 3313 } 3314 3315 static const char * 3316 pci_conf_print_tph_req_cap_sttabloc(unsigned char val) 3317 { 3318 3319 switch (val) { 3320 case 0x0: 3321 return "Not Present"; 3322 case 0x1: 3323 return "in the TPH Requester Capability Structure"; 3324 case 0x2: 3325 return "in the MSI-X Table"; 3326 default: 3327 return "Unknown"; 3328 } 3329 } 3330 3331 static void 3332 pci_conf_print_tph_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3333 { 3334 pcireg_t reg; 3335 int size, i, j; 3336 3337 printf("\n TPH Requester Extended Capability\n"); 3338 3339 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 3340 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 3341 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 3342 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 3343 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 3344 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 3345 printf(" ST Table Location: %s\n", 3346 pci_conf_print_tph_req_cap_sttabloc( 3347 (unsigned char)__SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC))); 3348 size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 3349 printf(" ST Table Size: %d\n", size); 3350 for (i = 0; i < size ; i += 2) { 3351 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 3352 for (j = 0; j < 2 ; j++) { 3353 uint32_t entry = reg; 3354 3355 if (j != 0) 3356 entry >>= 16; 3357 entry &= 0xffff; 3358 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 3359 i + j, entry); 3360 } 3361 } 3362 } 3363 3364 static void 3365 pci_conf_print_ltr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3366 { 3367 pcireg_t reg; 3368 3369 printf("\n Latency Tolerance Reporting\n"); 3370 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)] & 0xffff; 3371 printf(" Max Snoop Latency Register: 0x%04x\n", reg); 3372 printf(" Max Snoop LatencyValue: %u\n", 3373 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL)); 3374 printf(" Max Snoop LatencyScale: %uns\n", 3375 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE))); 3376 reg = regs[o2i(extcapoff + PCI_LTR_MAXNOSNOOPLAT)] >> 16; 3377 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg); 3378 printf(" Max No-Snoop LatencyValue: %u\n", 3379 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL)); 3380 printf(" Max No-Snoop LatencyScale: %uns\n", 3381 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE))); 3382 } 3383 3384 static void 3385 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int capoff, int extcapoff) 3386 { 3387 int pcie_capoff; 3388 pcireg_t reg; 3389 int i, maxlinkwidth; 3390 3391 printf("\n Secondary PCI Express Register\n"); 3392 3393 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3394 printf(" Link Control 3 register: 0x%08x\n", reg); 3395 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3396 onoff("Link Equalization Request Interrupt Enable", 3397 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3398 printf(" Enable Lower SKP OS Generation Vector:"); 3399 pci_print_pcie_linkspeedvector( 3400 __SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV)); 3401 printf("\n"); 3402 3403 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3404 printf(" Lane Error Status register: 0x%08x\n", reg); 3405 3406 /* Get Max Link Width */ 3407 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)){ 3408 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3409 maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3410 } else { 3411 printf("error: falied to get PCIe capablity\n"); 3412 return; 3413 } 3414 for (i = 0; i < maxlinkwidth; i++) { 3415 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3416 if (i % 2 != 0) 3417 reg >>= 16; 3418 else 3419 reg &= 0xffff; 3420 printf(" Equalization Control Register (Link %d): 0x%04x\n", 3421 i, reg); 3422 printf(" Downstream Port Transmit Preset: 0x%x\n", 3423 (pcireg_t)__SHIFTOUT(reg, 3424 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3425 printf(" Downstream Port Receive Hint: 0x%x\n", 3426 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3427 printf(" Upstream Port Transmit Preset: 0x%x\n", 3428 (pcireg_t)__SHIFTOUT(reg, 3429 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3430 printf(" Upstream Port Receive Hint: 0x%x\n", 3431 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3432 } 3433 } 3434 3435 /* XXX pci_conf_print_pmux_cap */ 3436 3437 static void 3438 pci_conf_print_pasid_cap(const pcireg_t *regs, int capoff, int extcapoff) 3439 { 3440 pcireg_t reg, cap, ctl; 3441 unsigned int num; 3442 3443 printf("\n Process Address Space ID\n"); 3444 3445 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3446 cap = reg & 0xffff; 3447 ctl = reg >> 16; 3448 printf(" PASID Capability Register: 0x%04x\n", cap); 3449 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3450 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3451 num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3452 printf(" Max PASID Width: %u\n", num); 3453 3454 printf(" PASID Control Register: 0x%04x\n", ctl); 3455 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3456 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3457 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 3458 } 3459 3460 static void 3461 pci_conf_print_lnr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3462 { 3463 pcireg_t reg, cap, ctl; 3464 unsigned int num; 3465 3466 printf("\n LN Requester\n"); 3467 3468 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 3469 cap = reg & 0xffff; 3470 ctl = reg >> 16; 3471 printf(" LNR Capability register: 0x%04x\n", cap); 3472 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 3473 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 3474 num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 3475 printf(" LNR Registration MAX: %u\n", num); 3476 3477 printf(" LNR Control register: 0x%04x\n", ctl); 3478 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 3479 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 3480 num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 3481 printf(" LNR Registration Limit: %u\n", num); 3482 } 3483 3484 /* XXX pci_conf_print_dpc_cap */ 3485 3486 static int 3487 pci_conf_l1pm_cap_tposcale(unsigned char scale) 3488 { 3489 3490 /* Return scale in us */ 3491 switch (scale) { 3492 case 0x0: 3493 return 2; 3494 case 0x1: 3495 return 10; 3496 case 0x2: 3497 return 100; 3498 default: 3499 return -1; 3500 } 3501 } 3502 3503 static void 3504 pci_conf_print_l1pm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3505 { 3506 pcireg_t reg; 3507 int scale, val; 3508 3509 printf("\n L1 PM Substates\n"); 3510 3511 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 3512 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 3513 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 3514 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 3515 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 3516 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 3517 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 3518 printf(" Port Common Mode Restore Time: %uus\n", 3519 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 3520 scale = pci_conf_l1pm_cap_tposcale( 3521 __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 3522 val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 3523 printf(" Port T_POWER_ON: "); 3524 if (scale == -1) 3525 printf("unknown\n"); 3526 else 3527 printf("%dus\n", val * scale); 3528 3529 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 3530 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 3531 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 3532 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 3533 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 3534 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 3535 printf(" Common Mode Restore Time: %uus\n", 3536 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 3537 scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 3538 val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 3539 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 3540 3541 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 3542 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 3543 scale = pci_conf_l1pm_cap_tposcale( 3544 __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 3545 val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 3546 printf(" T_POWER_ON: "); 3547 if (scale == -1) 3548 printf("unknown\n"); 3549 else 3550 printf("%dus\n", val * scale); 3551 } 3552 3553 static void 3554 pci_conf_print_ptm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3555 { 3556 pcireg_t reg; 3557 uint32_t val; 3558 3559 printf("\n Precision Time Management\n"); 3560 3561 reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; 3562 printf(" PTM Capability register: 0x%08x\n", reg); 3563 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ); 3564 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP); 3565 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT); 3566 printf(" Local Clock Granularity: "); 3567 val = __SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL); 3568 switch (val) { 3569 case 0: 3570 printf("Not implemented\n"); 3571 break; 3572 case 0xffff: 3573 printf("> 254ns\n"); 3574 break; 3575 default: 3576 printf("%uns\n", val); 3577 break; 3578 } 3579 3580 reg = regs[o2i(extcapoff + PCI_PTM_CTL)]; 3581 printf(" PTM Control register: 0x%08x\n", reg); 3582 onoff("PTM Enable", reg, PCI_PTM_CTL_EN); 3583 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL); 3584 printf(" Effective Granularity: "); 3585 val = __SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL); 3586 switch (val) { 3587 case 0: 3588 printf("Unknown\n"); 3589 break; 3590 case 0xffff: 3591 printf("> 254ns\n"); 3592 break; 3593 default: 3594 printf("%uns\n", val); 3595 break; 3596 } 3597 } 3598 3599 /* XXX pci_conf_print_mpcie_cap */ 3600 /* XXX pci_conf_print_frsq_cap */ 3601 /* XXX pci_conf_print_rtr_cap */ 3602 /* XXX pci_conf_print_desigvndsp_cap */ 3603 /* XXX pci_conf_print_vf_resizbar_cap */ 3604 3605 #undef MS 3606 #undef SM 3607 #undef RW 3608 3609 static struct { 3610 pcireg_t cap; 3611 const char *name; 3612 void (*printfunc)(const pcireg_t *, int, int); 3613 } pci_extcaptab[] = { 3614 { 0, "reserved", 3615 NULL }, 3616 { PCI_EXTCAP_AER, "Advanced Error Reporting", 3617 pci_conf_print_aer_cap }, 3618 { PCI_EXTCAP_VC, "Virtual Channel", 3619 pci_conf_print_vc_cap }, 3620 { PCI_EXTCAP_SERNUM, "Device Serial Number", 3621 pci_conf_print_sernum_cap }, 3622 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 3623 pci_conf_print_pwrbdgt_cap }, 3624 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 3625 pci_conf_print_rclink_dcl_cap }, 3626 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 3627 NULL }, 3628 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 3629 pci_conf_print_rcec_assoc_cap }, 3630 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 3631 NULL }, 3632 { PCI_EXTCAP_VC2, "Virtual Channel", 3633 NULL }, 3634 { PCI_EXTCAP_RCRB, "RCRB Header", 3635 NULL }, 3636 { PCI_EXTCAP_VENDOR, "Vendor Unique", 3637 NULL }, 3638 { PCI_EXTCAP_CAC, "Configuration Access Correction", 3639 NULL }, 3640 { PCI_EXTCAP_ACS, "Access Control Services", 3641 pci_conf_print_acs_cap }, 3642 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 3643 pci_conf_print_ari_cap }, 3644 { PCI_EXTCAP_ATS, "Address Translation Services", 3645 pci_conf_print_ats_cap }, 3646 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 3647 pci_conf_print_sriov_cap }, 3648 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 3649 NULL }, 3650 { PCI_EXTCAP_MCAST, "Multicast", 3651 pci_conf_print_multicast_cap }, 3652 { PCI_EXTCAP_PAGE_REQ, "Page Request", 3653 pci_conf_print_page_req_cap }, 3654 { PCI_EXTCAP_AMD, "Reserved for AMD", 3655 NULL }, 3656 { PCI_EXTCAP_RESIZBAR, "Resizable BAR", 3657 pci_conf_print_resizbar_cap }, 3658 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 3659 pci_conf_print_dpa_cap }, 3660 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 3661 pci_conf_print_tph_req_cap }, 3662 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 3663 pci_conf_print_ltr_cap }, 3664 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 3665 pci_conf_print_sec_pcie_cap }, 3666 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 3667 NULL }, 3668 { PCI_EXTCAP_PASID, "Process Address Space ID", 3669 pci_conf_print_pasid_cap }, 3670 { PCI_EXTCAP_LN_REQ, "LN Requester", 3671 pci_conf_print_lnr_cap }, 3672 { PCI_EXTCAP_DPC, "Downstream Port Containment", 3673 NULL }, 3674 { PCI_EXTCAP_L1PM, "L1 PM Substates", 3675 pci_conf_print_l1pm_cap }, 3676 { PCI_EXTCAP_PTM, "Precision Time Management", 3677 pci_conf_print_ptm_cap }, 3678 { PCI_EXTCAP_MPCIE, "M-PCIe", 3679 NULL }, 3680 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 3681 NULL }, 3682 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 3683 NULL }, 3684 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 3685 NULL }, 3686 { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs", 3687 NULL }, 3688 }; 3689 3690 static int 3691 pci_conf_find_extcap(const pcireg_t *regs, int capoff, unsigned int capid, 3692 int *offsetp) 3693 { 3694 int off; 3695 pcireg_t rval; 3696 3697 for (off = PCI_EXTCAPLIST_BASE; 3698 off != 0; 3699 off = PCI_EXTCAPLIST_NEXT(rval)) { 3700 rval = regs[o2i(off)]; 3701 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 3702 if (offsetp != NULL) 3703 *offsetp = off; 3704 return 1; 3705 } 3706 } 3707 return 0; 3708 } 3709 3710 static void 3711 pci_conf_print_extcaplist( 3712 #ifdef _KERNEL 3713 pci_chipset_tag_t pc, pcitag_t tag, 3714 #endif 3715 const pcireg_t *regs, int capoff) 3716 { 3717 int off; 3718 pcireg_t foundcap; 3719 pcireg_t rval; 3720 bool foundtable[__arraycount(pci_extcaptab)]; 3721 unsigned int i; 3722 3723 /* Check Extended capability structure */ 3724 off = PCI_EXTCAPLIST_BASE; 3725 rval = regs[o2i(off)]; 3726 if (rval == 0xffffffff || rval == 0) 3727 return; 3728 3729 /* Clear table */ 3730 for (i = 0; i < __arraycount(pci_extcaptab); i++) 3731 foundtable[i] = false; 3732 3733 /* Print extended capability register's offset and the type first */ 3734 for (;;) { 3735 printf(" Extended Capability Register at 0x%02x\n", off); 3736 3737 foundcap = PCI_EXTCAPLIST_CAP(rval); 3738 printf(" type: 0x%04x (", foundcap); 3739 if (foundcap < __arraycount(pci_extcaptab)) { 3740 printf("%s)\n", pci_extcaptab[foundcap].name); 3741 /* Mark as found */ 3742 foundtable[foundcap] = true; 3743 } else 3744 printf("unknown)\n"); 3745 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 3746 3747 off = PCI_EXTCAPLIST_NEXT(rval); 3748 if (off == 0) 3749 break; 3750 else if (off <= PCI_CONF_SIZE) { 3751 printf(" next pointer: 0x%03x (incorrect)\n", off); 3752 return; 3753 } 3754 rval = regs[o2i(off)]; 3755 } 3756 3757 /* 3758 * And then, print the detail of each capability registers 3759 * in capability value's order. 3760 */ 3761 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 3762 if (foundtable[i] == false) 3763 continue; 3764 3765 /* 3766 * The type was found. Search capability list again and 3767 * print all capabilities that the capabiliy type is 3768 * the same. 3769 */ 3770 if (pci_conf_find_extcap(regs, capoff, i, &off) == 0) 3771 continue; 3772 rval = regs[o2i(off)]; 3773 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 3774 || (pci_extcaptab[i].printfunc == NULL)) 3775 continue; 3776 3777 pci_extcaptab[i].printfunc(regs, capoff, off); 3778 3779 } 3780 } 3781 3782 /* Print the Secondary Status Register. */ 3783 static void 3784 pci_conf_print_ssr(pcireg_t rval) 3785 { 3786 pcireg_t devsel; 3787 3788 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 3789 onoff("66 MHz capable", rval, __BIT(5)); 3790 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 3791 onoff("Fast back-to-back capable", rval, __BIT(7)); 3792 onoff("Data parity error detected", rval, __BIT(8)); 3793 3794 printf(" DEVSEL timing: "); 3795 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 3796 switch (devsel) { 3797 case 0: 3798 printf("fast"); 3799 break; 3800 case 1: 3801 printf("medium"); 3802 break; 3803 case 2: 3804 printf("slow"); 3805 break; 3806 default: 3807 printf("unknown/reserved"); /* XXX */ 3808 break; 3809 } 3810 printf(" (0x%x)\n", devsel); 3811 3812 onoff("Signalled target abort", rval, __BIT(11)); 3813 onoff("Received target abort", rval, __BIT(12)); 3814 onoff("Received master abort", rval, __BIT(13)); 3815 onoff("Received system error", rval, __BIT(14)); 3816 onoff("Detected parity error", rval, __BIT(15)); 3817 } 3818 3819 static void 3820 pci_conf_print_type0( 3821 #ifdef _KERNEL 3822 pci_chipset_tag_t pc, pcitag_t tag, 3823 #endif 3824 const pcireg_t *regs 3825 #ifdef _KERNEL 3826 , int sizebars 3827 #endif 3828 ) 3829 { 3830 int off, width; 3831 pcireg_t rval; 3832 3833 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 3834 #ifdef _KERNEL 3835 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3836 #else 3837 width = pci_conf_print_bar(regs, off, NULL); 3838 #endif 3839 } 3840 3841 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 3842 3843 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 3844 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 3845 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 3846 3847 /* XXX */ 3848 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 3849 3850 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3851 printf(" Capability list pointer: 0x%02x\n", 3852 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 3853 else 3854 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 3855 3856 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 3857 3858 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3859 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 3860 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 3861 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 3862 switch (PCI_INTERRUPT_PIN(rval)) { 3863 case PCI_INTERRUPT_PIN_NONE: 3864 printf("(none)"); 3865 break; 3866 case PCI_INTERRUPT_PIN_A: 3867 printf("(pin A)"); 3868 break; 3869 case PCI_INTERRUPT_PIN_B: 3870 printf("(pin B)"); 3871 break; 3872 case PCI_INTERRUPT_PIN_C: 3873 printf("(pin C)"); 3874 break; 3875 case PCI_INTERRUPT_PIN_D: 3876 printf("(pin D)"); 3877 break; 3878 default: 3879 printf("(? ? ?)"); 3880 break; 3881 } 3882 printf("\n"); 3883 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 3884 } 3885 3886 static void 3887 pci_conf_print_type1( 3888 #ifdef _KERNEL 3889 pci_chipset_tag_t pc, pcitag_t tag, 3890 #endif 3891 const pcireg_t *regs 3892 #ifdef _KERNEL 3893 , int sizebars 3894 #endif 3895 ) 3896 { 3897 int off, width; 3898 pcireg_t rval; 3899 uint32_t base, limit; 3900 uint32_t base_h, limit_h; 3901 uint64_t pbase, plimit; 3902 int use_upper; 3903 3904 /* 3905 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 3906 * Bridge chip documentation, and may not be correct with 3907 * respect to various standards. (XXX) 3908 */ 3909 3910 for (off = 0x10; off < 0x18; off += width) { 3911 #ifdef _KERNEL 3912 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3913 #else 3914 width = pci_conf_print_bar(regs, off, NULL); 3915 #endif 3916 } 3917 3918 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 3919 printf(" Primary bus number: 0x%02x\n", 3920 PCI_BRIDGE_BUS_PRIMARY(rval)); 3921 printf(" Secondary bus number: 0x%02x\n", 3922 PCI_BRIDGE_BUS_SECONDARY(rval)); 3923 printf(" Subordinate bus number: 0x%02x\n", 3924 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 3925 printf(" Secondary bus latency timer: 0x%02x\n", 3926 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 3927 3928 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 3929 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 3930 3931 /* I/O region */ 3932 printf(" I/O region:\n"); 3933 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 3934 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 3935 if (PCI_BRIDGE_IO_32BITS(rval)) 3936 use_upper = 1; 3937 else 3938 use_upper = 0; 3939 onoff("32bit I/O", rval, use_upper); 3940 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 3941 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 3942 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 3943 limit |= 0x00000fff; 3944 3945 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 3946 base_h = (rval >> 0) & 0xffff; 3947 limit_h = (rval >> 16) & 0xffff; 3948 printf(" base upper 16 bits register: 0x%04x\n", base_h); 3949 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 3950 3951 if (use_upper == 1) { 3952 base |= base_h << 16; 3953 limit |= limit_h << 16; 3954 } 3955 if (base < limit) { 3956 if (use_upper == 1) 3957 printf(" range: 0x%08x-0x%08x\n", base, limit); 3958 else 3959 printf(" range: 0x%04x-0x%04x\n", base, limit); 3960 } else 3961 printf(" range: not set\n"); 3962 3963 /* Non-prefetchable memory region */ 3964 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 3965 printf(" Memory region:\n"); 3966 printf(" base register: 0x%04x\n", 3967 (rval >> 0) & 0xffff); 3968 printf(" limit register: 0x%04x\n", 3969 (rval >> 16) & 0xffff); 3970 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 3971 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 3972 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 3973 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 3974 if (base < limit) 3975 printf(" range: 0x%08x-0x%08x\n", base, limit); 3976 else 3977 printf(" range: not set\n"); 3978 3979 /* Prefetchable memory region */ 3980 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 3981 printf(" Prefetchable memory region:\n"); 3982 printf(" base register: 0x%04x\n", 3983 (rval >> 0) & 0xffff); 3984 printf(" limit register: 0x%04x\n", 3985 (rval >> 16) & 0xffff); 3986 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 3987 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 3988 printf(" base upper 32 bits register: 0x%08x\n", 3989 base_h); 3990 printf(" limit upper 32 bits register: 0x%08x\n", 3991 limit_h); 3992 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 3993 use_upper = 1; 3994 else 3995 use_upper = 0; 3996 onoff("64bit memory address", rval, use_upper); 3997 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 3998 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 3999 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 4000 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 4001 if (use_upper == 1) { 4002 pbase |= (uint64_t)base_h << 32; 4003 plimit |= (uint64_t)limit_h << 32; 4004 } 4005 if (pbase < plimit) { 4006 if (use_upper == 1) 4007 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 4008 "\n", pbase, plimit); 4009 else 4010 printf(" range: 0x%08x-0x%08x\n", 4011 (uint32_t)pbase, (uint32_t)plimit); 4012 } else 4013 printf(" range: not set\n"); 4014 4015 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4016 printf(" Capability list pointer: 0x%02x\n", 4017 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4018 else 4019 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4020 4021 /* XXX */ 4022 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 4023 4024 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4025 printf(" Interrupt line: 0x%02x\n", 4026 (rval >> 0) & 0xff); 4027 printf(" Interrupt pin: 0x%02x ", 4028 (rval >> 8) & 0xff); 4029 switch ((rval >> 8) & 0xff) { 4030 case PCI_INTERRUPT_PIN_NONE: 4031 printf("(none)"); 4032 break; 4033 case PCI_INTERRUPT_PIN_A: 4034 printf("(pin A)"); 4035 break; 4036 case PCI_INTERRUPT_PIN_B: 4037 printf("(pin B)"); 4038 break; 4039 case PCI_INTERRUPT_PIN_C: 4040 printf("(pin C)"); 4041 break; 4042 case PCI_INTERRUPT_PIN_D: 4043 printf("(pin D)"); 4044 break; 4045 default: 4046 printf("(? ? ?)"); 4047 break; 4048 } 4049 printf("\n"); 4050 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 4051 & PCI_BRIDGE_CONTROL_MASK; 4052 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 4053 onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE); 4054 onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR); 4055 onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA); 4056 onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA); 4057 onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT); 4058 onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR); 4059 onoff("Fast back-to-back capable", rval,PCI_BRIDGE_CONTROL_SECFASTB2B); 4060 } 4061 4062 static void 4063 pci_conf_print_type2( 4064 #ifdef _KERNEL 4065 pci_chipset_tag_t pc, pcitag_t tag, 4066 #endif 4067 const pcireg_t *regs 4068 #ifdef _KERNEL 4069 , int sizebars 4070 #endif 4071 ) 4072 { 4073 pcireg_t rval; 4074 4075 /* 4076 * XXX these need to be printed in more detail, need to be 4077 * XXX checked against specs/docs, etc. 4078 * 4079 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 4080 * controller chip documentation, and may not be correct with 4081 * respect to various standards. (XXX) 4082 */ 4083 4084 #ifdef _KERNEL 4085 pci_conf_print_bar(pc, tag, regs, 0x10, 4086 "CardBus socket/ExCA registers", sizebars); 4087 #else 4088 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 4089 #endif 4090 4091 /* Capability list pointer and secondary status register */ 4092 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 4093 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4094 printf(" Capability list pointer: 0x%02x\n", 4095 PCI_CAPLIST_PTR(rval)); 4096 else 4097 printf(" Reserved @ 0x14: 0x%04x\n", 4098 (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0))); 4099 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 4100 4101 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4102 printf(" PCI bus number: 0x%02x\n", 4103 (rval >> 0) & 0xff); 4104 printf(" CardBus bus number: 0x%02x\n", 4105 (rval >> 8) & 0xff); 4106 printf(" Subordinate bus number: 0x%02x\n", 4107 (rval >> 16) & 0xff); 4108 printf(" CardBus latency timer: 0x%02x\n", 4109 (rval >> 24) & 0xff); 4110 4111 /* XXX Print more prettily */ 4112 printf(" CardBus memory region 0:\n"); 4113 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 4114 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 4115 printf(" CardBus memory region 1:\n"); 4116 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 4117 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 4118 printf(" CardBus I/O region 0:\n"); 4119 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 4120 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 4121 printf(" CardBus I/O region 1:\n"); 4122 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 4123 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 4124 4125 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4126 printf(" Interrupt line: 0x%02x\n", 4127 (rval >> 0) & 0xff); 4128 printf(" Interrupt pin: 0x%02x ", 4129 (rval >> 8) & 0xff); 4130 switch ((rval >> 8) & 0xff) { 4131 case PCI_INTERRUPT_PIN_NONE: 4132 printf("(none)"); 4133 break; 4134 case PCI_INTERRUPT_PIN_A: 4135 printf("(pin A)"); 4136 break; 4137 case PCI_INTERRUPT_PIN_B: 4138 printf("(pin B)"); 4139 break; 4140 case PCI_INTERRUPT_PIN_C: 4141 printf("(pin C)"); 4142 break; 4143 case PCI_INTERRUPT_PIN_D: 4144 printf("(pin D)"); 4145 break; 4146 default: 4147 printf("(? ? ?)"); 4148 break; 4149 } 4150 printf("\n"); 4151 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 4152 printf(" Bridge control register: 0x%04x\n", rval); 4153 onoff("Parity error response", rval, __BIT(0)); 4154 onoff("SERR# enable", rval, __BIT(1)); 4155 onoff("ISA enable", rval, __BIT(2)); 4156 onoff("VGA enable", rval, __BIT(3)); 4157 onoff("Master abort mode", rval, __BIT(5)); 4158 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 4159 onoff("Functional interrupts routed by ExCA registers", rval, 4160 __BIT(7)); 4161 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 4162 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 4163 onoff("Write posting enable", rval, __BIT(10)); 4164 4165 rval = regs[o2i(0x40)]; 4166 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4167 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4168 4169 #ifdef _KERNEL 4170 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 4171 sizebars); 4172 #else 4173 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 4174 #endif 4175 } 4176 4177 void 4178 pci_conf_print( 4179 #ifdef _KERNEL 4180 pci_chipset_tag_t pc, pcitag_t tag, 4181 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 4182 #else 4183 int pcifd, u_int bus, u_int dev, u_int func 4184 #endif 4185 ) 4186 { 4187 pcireg_t regs[o2i(PCI_EXTCONF_SIZE)]; 4188 int off, capoff, endoff, hdrtype; 4189 const char *type_name; 4190 #ifdef _KERNEL 4191 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, 4192 int); 4193 int sizebars; 4194 #else 4195 void (*type_printfn)(const pcireg_t *); 4196 #endif 4197 4198 printf("PCI configuration registers:\n"); 4199 4200 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 4201 #ifdef _KERNEL 4202 regs[o2i(off)] = pci_conf_read(pc, tag, off); 4203 #else 4204 if (pcibus_conf_read(pcifd, bus, dev, func, off, 4205 ®s[o2i(off)]) == -1) 4206 regs[o2i(off)] = 0; 4207 #endif 4208 } 4209 4210 #ifdef _KERNEL 4211 sizebars = 1; 4212 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 4213 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 4214 sizebars = 0; 4215 #endif 4216 4217 /* common header */ 4218 printf(" Common header:\n"); 4219 pci_conf_print_regs(regs, 0, 16); 4220 4221 printf("\n"); 4222 #ifdef _KERNEL 4223 pci_conf_print_common(pc, tag, regs); 4224 #else 4225 pci_conf_print_common(regs); 4226 #endif 4227 printf("\n"); 4228 4229 /* type-dependent header */ 4230 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 4231 switch (hdrtype) { /* XXX make a table, eventually */ 4232 case 0: 4233 /* Standard device header */ 4234 type_name = "\"normal\" device"; 4235 type_printfn = &pci_conf_print_type0; 4236 capoff = PCI_CAPLISTPTR_REG; 4237 endoff = 64; 4238 break; 4239 case 1: 4240 /* PCI-PCI bridge header */ 4241 type_name = "PCI-PCI bridge"; 4242 type_printfn = &pci_conf_print_type1; 4243 capoff = PCI_CAPLISTPTR_REG; 4244 endoff = 64; 4245 break; 4246 case 2: 4247 /* PCI-CardBus bridge header */ 4248 type_name = "PCI-CardBus bridge"; 4249 type_printfn = &pci_conf_print_type2; 4250 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 4251 endoff = 72; 4252 break; 4253 default: 4254 type_name = NULL; 4255 type_printfn = 0; 4256 capoff = -1; 4257 endoff = 64; 4258 break; 4259 } 4260 printf(" Type %d ", hdrtype); 4261 if (type_name != NULL) 4262 printf("(%s) ", type_name); 4263 printf("header:\n"); 4264 pci_conf_print_regs(regs, 16, endoff); 4265 printf("\n"); 4266 if (type_printfn) { 4267 #ifdef _KERNEL 4268 (*type_printfn)(pc, tag, regs, sizebars); 4269 #else 4270 (*type_printfn)(regs); 4271 #endif 4272 } else 4273 printf(" Don't know how to pretty-print type %d header.\n", 4274 hdrtype); 4275 printf("\n"); 4276 4277 /* capability list, if present */ 4278 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4279 && (capoff > 0)) { 4280 #ifdef _KERNEL 4281 pci_conf_print_caplist(pc, tag, regs, capoff); 4282 #else 4283 pci_conf_print_caplist(regs, capoff); 4284 #endif 4285 printf("\n"); 4286 } 4287 4288 /* device-dependent header */ 4289 printf(" Device-dependent header:\n"); 4290 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 4291 printf("\n"); 4292 #ifdef _KERNEL 4293 if (printfn) 4294 (*printfn)(pc, tag, regs); 4295 else 4296 printf(" Don't know how to pretty-print device-dependent header.\n"); 4297 printf("\n"); 4298 #endif /* _KERNEL */ 4299 4300 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 4301 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 4302 return; 4303 4304 #ifdef _KERNEL 4305 pci_conf_print_extcaplist(pc, tag, regs, capoff); 4306 #else 4307 pci_conf_print_extcaplist(regs, capoff); 4308 #endif 4309 printf("\n"); 4310 4311 /* Extended Configuration Space, if present */ 4312 printf(" Extended Configuration Space:\n"); 4313 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 4314 } 4315
Indexes created Thu Sep 25 06:09:39 GMT 2025