pci_subr.c revision 1.163
1 /* $NetBSD: pci_subr.c,v 1.163 2017/03/14 08:09:31 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.163 2017/03/14 08:09:31 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdarg.h> 58 #include <stdbool.h> 59 #include <stdio.h> 60 #include <stdlib.h> 61 #include <string.h> 62 #endif 63 64 #include <dev/pci/pcireg.h> 65 #ifdef _KERNEL 66 #include <dev/pci/pcivar.h> 67 #else 68 #include <dev/pci/pci_verbose.h> 69 #include <dev/pci/pcidevs.h> 70 #include <dev/pci/pcidevs_data.h> 71 #endif 72 73 /* 74 * Descriptions of known PCI classes and subclasses. 75 * 76 * Subclasses are described in the same way as classes, but have a 77 * NULL subclass pointer. 78 */ 79 struct pci_class { 80 const char *name; 81 u_int val; /* as wide as pci_{,sub}class_t */ 82 const struct pci_class *subclasses; 83 }; 84 85 /* 86 * Class 0x00. 87 * Before rev. 2.0. 88 */ 89 static const struct pci_class pci_subclass_prehistoric[] = { 90 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 91 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 92 { NULL, 0, NULL, }, 93 }; 94 95 /* 96 * Class 0x01. 97 * Mass storage controller 98 */ 99 100 /* ATA programming interface */ 101 static const struct pci_class pci_interface_ata[] = { 102 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 103 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 104 { NULL, 0, NULL, }, 105 }; 106 107 /* SATA programming interface */ 108 static const struct pci_class pci_interface_sata[] = { 109 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 110 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 111 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 112 { NULL, 0, NULL, }, 113 }; 114 115 /* Flash programming interface */ 116 static const struct pci_class pci_interface_nvm[] = { 117 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 118 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 119 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 120 { NULL, 0, NULL, }, 121 }; 122 123 /* Subclasses */ 124 static const struct pci_class pci_subclass_mass_storage[] = { 125 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 126 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 127 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 128 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 129 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 130 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 131 pci_interface_ata, }, 132 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 133 pci_interface_sata, }, 134 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 135 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 136 pci_interface_nvm, }, 137 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 138 { NULL, 0, NULL, }, 139 }; 140 141 /* 142 * Class 0x02. 143 * Network controller. 144 */ 145 static const struct pci_class pci_subclass_network[] = { 146 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 147 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 148 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 149 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 150 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 151 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 152 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 153 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 154 { NULL, 0, NULL, }, 155 }; 156 157 /* 158 * Class 0x03. 159 * Display controller. 160 */ 161 162 /* VGA programming interface */ 163 static const struct pci_class pci_interface_vga[] = { 164 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 165 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 166 { NULL, 0, NULL, }, 167 }; 168 /* Subclasses */ 169 static const struct pci_class pci_subclass_display[] = { 170 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 171 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 172 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 173 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 174 { NULL, 0, NULL, }, 175 }; 176 177 /* 178 * Class 0x04. 179 * Multimedia device. 180 */ 181 static const struct pci_class pci_subclass_multimedia[] = { 182 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 183 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 184 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 185 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 186 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 187 { NULL, 0, NULL, }, 188 }; 189 190 /* 191 * Class 0x05. 192 * Memory controller. 193 */ 194 static const struct pci_class pci_subclass_memory[] = { 195 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 196 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 197 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 198 { NULL, 0, NULL, }, 199 }; 200 201 /* 202 * Class 0x06. 203 * Bridge device. 204 */ 205 206 /* PCI bridge programming interface */ 207 static const struct pci_class pci_interface_pcibridge[] = { 208 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 209 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 210 { NULL, 0, NULL, }, 211 }; 212 213 /* Semi-transparent PCI-to-PCI bridge programming interface */ 214 static const struct pci_class pci_interface_stpci[] = { 215 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 216 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 217 { NULL, 0, NULL, }, 218 }; 219 220 /* Advanced Switching programming interface */ 221 static const struct pci_class pci_interface_advsw[] = { 222 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 223 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 224 { NULL, 0, NULL, }, 225 }; 226 227 /* Subclasses */ 228 static const struct pci_class pci_subclass_bridge[] = { 229 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 230 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 231 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 232 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 233 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 234 pci_interface_pcibridge, }, 235 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 236 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 237 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 238 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 239 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 240 pci_interface_stpci, }, 241 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 242 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 243 pci_interface_advsw, }, 244 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 245 { NULL, 0, NULL, }, 246 }; 247 248 /* 249 * Class 0x07. 250 * Simple communications controller. 251 */ 252 253 /* Serial controller programming interface */ 254 static const struct pci_class pci_interface_serial[] = { 255 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 256 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 257 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 258 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 259 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 260 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 261 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 262 { NULL, 0, NULL, }, 263 }; 264 265 /* Parallel controller programming interface */ 266 static const struct pci_class pci_interface_parallel[] = { 267 { "", PCI_INTERFACE_PARALLEL, NULL,}, 268 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 269 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 270 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 271 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 272 { NULL, 0, NULL,}, 273 }; 274 275 /* Modem programming interface */ 276 static const struct pci_class pci_interface_modem[] = { 277 { "", PCI_INTERFACE_MODEM, NULL,}, 278 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 279 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 280 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 281 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 282 { NULL, 0, NULL,}, 283 }; 284 285 /* Subclasses */ 286 static const struct pci_class pci_subclass_communications[] = { 287 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 288 pci_interface_serial, }, 289 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 290 pci_interface_parallel, }, 291 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 292 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 293 pci_interface_modem, }, 294 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 295 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 296 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 297 { NULL, 0, NULL,}, 298 }; 299 300 /* 301 * Class 0x08. 302 * Base system peripheral. 303 */ 304 305 /* PIC programming interface */ 306 static const struct pci_class pci_interface_pic[] = { 307 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 308 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 309 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 310 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 311 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 312 { NULL, 0, NULL, }, 313 }; 314 315 /* DMA programming interface */ 316 static const struct pci_class pci_interface_dma[] = { 317 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 318 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 319 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 320 { NULL, 0, NULL, }, 321 }; 322 323 /* Timer programming interface */ 324 static const struct pci_class pci_interface_tmr[] = { 325 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 326 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 327 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 328 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 329 { NULL, 0, NULL, }, 330 }; 331 332 /* RTC programming interface */ 333 static const struct pci_class pci_interface_rtc[] = { 334 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 335 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 336 { NULL, 0, NULL, }, 337 }; 338 339 /* Subclasses */ 340 static const struct pci_class pci_subclass_system[] = { 341 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 342 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 343 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 344 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 345 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 346 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 347 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 348 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 349 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 350 { NULL, 0, NULL, }, 351 }; 352 353 /* 354 * Class 0x09. 355 * Input device. 356 */ 357 358 /* Gameport programming interface */ 359 static const struct pci_class pci_interface_game[] = { 360 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 361 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 362 { NULL, 0, NULL, }, 363 }; 364 365 /* Subclasses */ 366 static const struct pci_class pci_subclass_input[] = { 367 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 368 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 369 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 370 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 371 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 372 pci_interface_game, }, 373 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 374 { NULL, 0, NULL, }, 375 }; 376 377 /* 378 * Class 0x0a. 379 * Docking station. 380 */ 381 static const struct pci_class pci_subclass_dock[] = { 382 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 383 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 384 { NULL, 0, NULL, }, 385 }; 386 387 /* 388 * Class 0x0b. 389 * Processor. 390 */ 391 static const struct pci_class pci_subclass_processor[] = { 392 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 393 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 394 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 395 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 396 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 397 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 398 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 399 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 400 { NULL, 0, NULL, }, 401 }; 402 403 /* 404 * Class 0x0c. 405 * Serial bus controller. 406 */ 407 408 /* IEEE1394 programming interface */ 409 static const struct pci_class pci_interface_ieee1394[] = { 410 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 411 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 412 { NULL, 0, NULL,}, 413 }; 414 415 /* USB programming interface */ 416 static const struct pci_class pci_interface_usb[] = { 417 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 418 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 419 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 420 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 421 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 422 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 423 { NULL, 0, NULL, }, 424 }; 425 426 /* IPMI programming interface */ 427 static const struct pci_class pci_interface_ipmi[] = { 428 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 429 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 430 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 431 { NULL, 0, NULL,}, 432 }; 433 434 /* Subclasses */ 435 static const struct pci_class pci_subclass_serialbus[] = { 436 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 437 pci_interface_ieee1394, }, 438 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 439 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 440 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 441 pci_interface_usb, }, 442 /* XXX Fiber Channel/_FIBRECHANNEL */ 443 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 444 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 445 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 446 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 447 pci_interface_ipmi, }, 448 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 449 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 450 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 451 { NULL, 0, NULL, }, 452 }; 453 454 /* 455 * Class 0x0d. 456 * Wireless Controller. 457 */ 458 static const struct pci_class pci_subclass_wireless[] = { 459 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 460 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 461 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 462 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 463 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 464 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 465 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 466 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 467 { NULL, 0, NULL, }, 468 }; 469 470 /* 471 * Class 0x0e. 472 * Intelligent IO controller. 473 */ 474 475 /* Intelligent IO programming interface */ 476 static const struct pci_class pci_interface_i2o[] = { 477 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 478 { NULL, 0, NULL,}, 479 }; 480 481 /* Subclasses */ 482 static const struct pci_class pci_subclass_i2o[] = { 483 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 484 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 485 { NULL, 0, NULL, }, 486 }; 487 488 /* 489 * Class 0x0f. 490 * Satellite communication controller. 491 */ 492 static const struct pci_class pci_subclass_satcom[] = { 493 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 494 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 495 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 496 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 497 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 498 { NULL, 0, NULL, }, 499 }; 500 501 /* 502 * Class 0x10. 503 * Encryption/Decryption controller. 504 */ 505 static const struct pci_class pci_subclass_crypto[] = { 506 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 507 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 508 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 509 { NULL, 0, NULL, }, 510 }; 511 512 /* 513 * Class 0x11. 514 * Data aquuisition and signal processing controller. 515 */ 516 static const struct pci_class pci_subclass_dasp[] = { 517 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 518 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 519 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 520 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 521 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 522 { NULL, 0, NULL, }, 523 }; 524 525 /* List of classes */ 526 static const struct pci_class pci_classes[] = { 527 { "prehistoric", PCI_CLASS_PREHISTORIC, 528 pci_subclass_prehistoric, }, 529 { "mass storage", PCI_CLASS_MASS_STORAGE, 530 pci_subclass_mass_storage, }, 531 { "network", PCI_CLASS_NETWORK, 532 pci_subclass_network, }, 533 { "display", PCI_CLASS_DISPLAY, 534 pci_subclass_display, }, 535 { "multimedia", PCI_CLASS_MULTIMEDIA, 536 pci_subclass_multimedia, }, 537 { "memory", PCI_CLASS_MEMORY, 538 pci_subclass_memory, }, 539 { "bridge", PCI_CLASS_BRIDGE, 540 pci_subclass_bridge, }, 541 { "communications", PCI_CLASS_COMMUNICATIONS, 542 pci_subclass_communications, }, 543 { "system", PCI_CLASS_SYSTEM, 544 pci_subclass_system, }, 545 { "input", PCI_CLASS_INPUT, 546 pci_subclass_input, }, 547 { "dock", PCI_CLASS_DOCK, 548 pci_subclass_dock, }, 549 { "processor", PCI_CLASS_PROCESSOR, 550 pci_subclass_processor, }, 551 { "serial bus", PCI_CLASS_SERIALBUS, 552 pci_subclass_serialbus, }, 553 { "wireless", PCI_CLASS_WIRELESS, 554 pci_subclass_wireless, }, 555 { "I2O", PCI_CLASS_I2O, 556 pci_subclass_i2o, }, 557 { "satellite comm", PCI_CLASS_SATCOM, 558 pci_subclass_satcom, }, 559 { "crypto", PCI_CLASS_CRYPTO, 560 pci_subclass_crypto, }, 561 { "DASP", PCI_CLASS_DASP, 562 pci_subclass_dasp, }, 563 { "undefined", PCI_CLASS_UNDEFINED, 564 NULL, }, 565 { NULL, 0, 566 NULL, }, 567 }; 568 569 DEV_VERBOSE_DEFINE(pci); 570 571 /* 572 * Append a formatted string to dest without writing more than len 573 * characters (including the trailing NUL character). dest and len 574 * are updated for use in subsequent calls to snappendf(). 575 * 576 * Returns 0 on success, a negative value if vnsprintf() fails, or 577 * a positive value if the dest buffer would have overflowed. 578 */ 579 580 static int __printflike(3,4) 581 snappendf(char **dest, size_t *len, const char * restrict fmt, ...) 582 { 583 va_list ap; 584 int count; 585 586 va_start(ap, fmt); 587 count = vsnprintf(*dest, *len, fmt, ap); 588 va_end(ap); 589 590 /* Let vsnprintf() errors bubble up to caller */ 591 if (count < 0 || *len == 0) 592 return count; 593 594 /* Handle overflow */ 595 if ((size_t)count >= *len) { 596 *dest += *len - 1; 597 *len = 1; 598 return 1; 599 } 600 601 /* Update dest & len to point at trailing NUL */ 602 *dest += count; 603 *len -= count; 604 605 return 0; 606 } 607 608 void 609 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 610 size_t l) 611 { 612 pci_class_t class; 613 pci_subclass_t subclass; 614 pci_interface_t interface; 615 pci_revision_t revision; 616 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 617 const struct pci_class *classp, *subclassp, *interfacep; 618 619 class = PCI_CLASS(class_reg); 620 subclass = PCI_SUBCLASS(class_reg); 621 interface = PCI_INTERFACE(class_reg); 622 revision = PCI_REVISION(class_reg); 623 624 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 625 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 626 PCI_PRODUCT(id_reg)); 627 628 classp = pci_classes; 629 while (classp->name != NULL) { 630 if (class == classp->val) 631 break; 632 classp++; 633 } 634 635 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 636 while (subclassp && subclassp->name != NULL) { 637 if (subclass == subclassp->val) 638 break; 639 subclassp++; 640 } 641 642 interfacep = (subclassp && subclassp->name != NULL) ? 643 subclassp->subclasses : NULL; 644 while (interfacep && interfacep->name != NULL) { 645 if (interface == interfacep->val) 646 break; 647 interfacep++; 648 } 649 650 (void)snappendf(&cp, &l, "%s %s", vendor, product); 651 if (showclass) { 652 (void)snappendf(&cp, &l, " ("); 653 if (classp->name == NULL) 654 (void)snappendf(&cp, &l, 655 "class 0x%02x, subclass 0x%02x", 656 class, subclass); 657 else { 658 if (subclassp == NULL || subclassp->name == NULL) 659 (void)snappendf(&cp, &l, 660 "%s, subclass 0x%02x", 661 classp->name, subclass); 662 else 663 (void)snappendf(&cp, &l, "%s %s", 664 subclassp->name, classp->name); 665 } 666 if ((interfacep == NULL) || (interfacep->name == NULL)) { 667 if (interface != 0) 668 (void)snappendf(&cp, &l, ", interface 0x%02x", 669 interface); 670 } else if (strncmp(interfacep->name, "", 1) != 0) 671 (void)snappendf(&cp, &l, ", %s", interfacep->name); 672 if (revision != 0) 673 (void)snappendf(&cp, &l, ", revision 0x%02x", revision); 674 (void)snappendf(&cp, &l, ")"); 675 } 676 } 677 678 #ifdef _KERNEL 679 void 680 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 681 const char *known, int addrev) 682 { 683 char devinfo[256]; 684 685 if (known) { 686 aprint_normal(": %s", known); 687 if (addrev) 688 aprint_normal(" (rev. 0x%02x)", 689 PCI_REVISION(pa->pa_class)); 690 aprint_normal("\n"); 691 } else { 692 pci_devinfo(pa->pa_id, pa->pa_class, 0, 693 devinfo, sizeof(devinfo)); 694 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 695 PCI_REVISION(pa->pa_class)); 696 } 697 if (naive) 698 aprint_naive(": %s\n", naive); 699 else 700 aprint_naive("\n"); 701 } 702 #endif 703 704 /* 705 * Print out most of the PCI configuration registers. Typically used 706 * in a device attach routine like this: 707 * 708 * #ifdef MYDEV_DEBUG 709 * printf("%s: ", device_xname(sc->sc_dev)); 710 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 711 * #endif 712 */ 713 714 #define i2o(i) ((i) * 4) 715 #define o2i(o) ((o) / 4) 716 #define onoff2(str, rval, bit, onstr, offstr) \ 717 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 718 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 719 720 static void 721 pci_conf_print_common( 722 #ifdef _KERNEL 723 pci_chipset_tag_t pc, pcitag_t tag, 724 #endif 725 const pcireg_t *regs) 726 { 727 pci_class_t class; 728 pci_subclass_t subclass; 729 pci_interface_t interface; 730 pci_revision_t revision; 731 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 732 const struct pci_class *classp, *subclassp; 733 const char *name; 734 pcireg_t rval; 735 unsigned int num; 736 737 rval = regs[o2i(PCI_CLASS_REG)]; 738 class = PCI_CLASS(rval); 739 subclass = PCI_SUBCLASS(rval); 740 interface = PCI_INTERFACE(rval); 741 revision = PCI_REVISION(rval); 742 743 rval = regs[o2i(PCI_ID_REG)]; 744 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 745 if (name) 746 printf(" Vendor Name: %s (0x%04x)\n", name, 747 PCI_VENDOR(rval)); 748 else 749 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 750 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 751 PCI_PRODUCT(rval)); 752 if (name) 753 printf(" Device Name: %s (0x%04x)\n", name, 754 PCI_PRODUCT(rval)); 755 else 756 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 757 758 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 759 760 printf(" Command register: 0x%04x\n", rval & 0xffff); 761 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 762 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 763 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 764 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 765 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 766 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 767 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 768 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 769 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 770 onoff("Fast back-to-back transactions", rval, 771 PCI_COMMAND_BACKTOBACK_ENABLE); 772 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 773 774 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 775 onoff("Immediate Readness", rval, PCI_STATUS_IMMD_READNESS); 776 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 777 "inactive"); 778 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 779 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 780 onoff("User Definable Features (UDF) support", rval, 781 PCI_STATUS_UDF_SUPPORT); 782 onoff("Fast back-to-back capable", rval, 783 PCI_STATUS_BACKTOBACK_SUPPORT); 784 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 785 786 printf(" DEVSEL timing: "); 787 switch (rval & PCI_STATUS_DEVSEL_MASK) { 788 case PCI_STATUS_DEVSEL_FAST: 789 printf("fast"); 790 break; 791 case PCI_STATUS_DEVSEL_MEDIUM: 792 printf("medium"); 793 break; 794 case PCI_STATUS_DEVSEL_SLOW: 795 printf("slow"); 796 break; 797 default: 798 printf("unknown/reserved"); /* XXX */ 799 break; 800 } 801 printf(" (0x%x)\n", __SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK)); 802 803 onoff("Slave signaled Target Abort", rval, 804 PCI_STATUS_TARGET_TARGET_ABORT); 805 onoff("Master received Target Abort", rval, 806 PCI_STATUS_MASTER_TARGET_ABORT); 807 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 808 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 809 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 810 811 rval = regs[o2i(PCI_CLASS_REG)]; 812 for (classp = pci_classes; classp->name != NULL; classp++) { 813 if (class == classp->val) 814 break; 815 } 816 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 817 while (subclassp && subclassp->name != NULL) { 818 if (subclass == subclassp->val) 819 break; 820 subclassp++; 821 } 822 if (classp->name != NULL) { 823 printf(" Class Name: %s (0x%02x)\n", classp->name, class); 824 if (subclassp != NULL && subclassp->name != NULL) 825 printf(" Subclass Name: %s (0x%02x)\n", 826 subclassp->name, PCI_SUBCLASS(rval)); 827 else 828 printf(" Subclass ID: 0x%02x\n", 829 PCI_SUBCLASS(rval)); 830 } else { 831 printf(" Class ID: 0x%02x\n", class); 832 printf(" Subclass ID: 0x%02x\n", subclass); 833 } 834 printf(" Interface: 0x%02x\n", interface); 835 printf(" Revision ID: 0x%02x\n", revision); 836 837 rval = regs[o2i(PCI_BHLC_REG)]; 838 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 839 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 840 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 841 PCI_HDRTYPE(rval)); 842 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 843 num = PCI_CACHELINE(rval); 844 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 845 } 846 847 static int 848 pci_conf_print_bar( 849 #ifdef _KERNEL 850 pci_chipset_tag_t pc, pcitag_t tag, 851 #endif 852 const pcireg_t *regs, int reg, const char *name 853 #ifdef _KERNEL 854 , int sizebar 855 #endif 856 ) 857 { 858 int width; 859 pcireg_t rval, rval64h; 860 #ifdef _KERNEL 861 int s; 862 pcireg_t mask, mask64h; 863 #endif 864 865 width = 4; 866 867 /* 868 * Section 6.2.5.1, `Address Maps', tells us that: 869 * 870 * 1) The builtin software should have already mapped the 871 * device in a reasonable way. 872 * 873 * 2) A device which wants 2^n bytes of memory will hardwire 874 * the bottom n bits of the address to 0. As recommended, 875 * we write all 1s and see what we get back. 876 */ 877 878 rval = regs[o2i(reg)]; 879 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 880 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 881 rval64h = regs[o2i(reg + 4)]; 882 width = 8; 883 } else 884 rval64h = 0; 885 886 #ifdef _KERNEL 887 /* XXX don't size unknown memory type? */ 888 if (rval != 0 && sizebar) { 889 /* 890 * The following sequence seems to make some devices 891 * (e.g. host bus bridges, which don't normally 892 * have their space mapped) very unhappy, to 893 * the point of crashing the system. 894 * 895 * Therefore, if the mapping register is zero to 896 * start out with, don't bother trying. 897 */ 898 s = splhigh(); 899 pci_conf_write(pc, tag, reg, 0xffffffff); 900 mask = pci_conf_read(pc, tag, reg); 901 pci_conf_write(pc, tag, reg, rval); 902 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 903 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 904 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 905 mask64h = pci_conf_read(pc, tag, reg + 4); 906 pci_conf_write(pc, tag, reg + 4, rval64h); 907 } else 908 mask64h = 0; 909 splx(s); 910 } else 911 mask = mask64h = 0; 912 #endif /* _KERNEL */ 913 914 printf(" Base address register at 0x%02x", reg); 915 if (name) 916 printf(" (%s)", name); 917 printf("\n "); 918 if (rval == 0) { 919 printf("not implemented(?)\n"); 920 return width; 921 } 922 printf("type: "); 923 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 924 const char *type, *prefetch; 925 926 switch (PCI_MAPREG_MEM_TYPE(rval)) { 927 case PCI_MAPREG_MEM_TYPE_32BIT: 928 type = "32-bit"; 929 break; 930 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 931 type = "32-bit-1M"; 932 break; 933 case PCI_MAPREG_MEM_TYPE_64BIT: 934 type = "64-bit"; 935 break; 936 default: 937 type = "unknown (XXX)"; 938 break; 939 } 940 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 941 prefetch = ""; 942 else 943 prefetch = "non"; 944 printf("%s %sprefetchable memory\n", type, prefetch); 945 switch (PCI_MAPREG_MEM_TYPE(rval)) { 946 case PCI_MAPREG_MEM_TYPE_64BIT: 947 printf(" base: 0x%016llx, ", 948 PCI_MAPREG_MEM64_ADDR( 949 ((((long long) rval64h) << 32) | rval))); 950 #ifdef _KERNEL 951 if (sizebar) 952 printf("size: 0x%016llx", 953 PCI_MAPREG_MEM64_SIZE( 954 ((((long long) mask64h) << 32) | mask))); 955 else 956 #endif /* _KERNEL */ 957 printf("not sized"); 958 printf("\n"); 959 break; 960 case PCI_MAPREG_MEM_TYPE_32BIT: 961 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 962 default: 963 printf(" base: 0x%08x, ", 964 PCI_MAPREG_MEM_ADDR(rval)); 965 #ifdef _KERNEL 966 if (sizebar) 967 printf("size: 0x%08x", 968 PCI_MAPREG_MEM_SIZE(mask)); 969 else 970 #endif /* _KERNEL */ 971 printf("not sized"); 972 printf("\n"); 973 break; 974 } 975 } else { 976 #ifdef _KERNEL 977 if (sizebar) 978 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 979 #endif /* _KERNEL */ 980 printf("i/o\n"); 981 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 982 #ifdef _KERNEL 983 if (sizebar) 984 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 985 else 986 #endif /* _KERNEL */ 987 printf("not sized"); 988 printf("\n"); 989 } 990 991 return width; 992 } 993 994 static void 995 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 996 { 997 int off, needaddr, neednl; 998 999 needaddr = 1; 1000 neednl = 0; 1001 for (off = first; off < pastlast; off += 4) { 1002 if ((off % 16) == 0 || needaddr) { 1003 printf(" 0x%02x:", off); 1004 needaddr = 0; 1005 } 1006 printf(" 0x%08x", regs[o2i(off)]); 1007 neednl = 1; 1008 if ((off % 16) == 12) { 1009 printf("\n"); 1010 neednl = 0; 1011 } 1012 } 1013 if (neednl) 1014 printf("\n"); 1015 } 1016 1017 static const char * 1018 pci_conf_print_agp_calcycle(uint8_t cal) 1019 { 1020 1021 switch (cal) { 1022 case 0x0: 1023 return "4ms"; 1024 case 0x1: 1025 return "16ms"; 1026 case 0x2: 1027 return "64ms"; 1028 case 0x3: 1029 return "256ms"; 1030 case 0x7: 1031 return "Calibration Cycle Not Needed"; 1032 default: 1033 return "(reserved)"; 1034 } 1035 } 1036 1037 static void 1038 pci_conf_print_agp_datarate(pcireg_t reg, bool isagp3) 1039 { 1040 if (isagp3) { 1041 /* AGP 3.0 */ 1042 if (reg & AGP_MODE_V3_RATE_4x) 1043 printf("x4"); 1044 if (reg & AGP_MODE_V3_RATE_8x) 1045 printf("x8"); 1046 } else { 1047 /* AGP 2.0 */ 1048 if (reg & AGP_MODE_V2_RATE_1x) 1049 printf("x1"); 1050 if (reg & AGP_MODE_V2_RATE_2x) 1051 printf("x2"); 1052 if (reg & AGP_MODE_V2_RATE_4x) 1053 printf("x4"); 1054 } 1055 printf("\n"); 1056 } 1057 1058 static void 1059 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1060 { 1061 pcireg_t rval; 1062 bool isagp3; 1063 1064 printf("\n AGP Capabilities Register\n"); 1065 1066 rval = regs[o2i(capoff)]; 1067 printf(" Revision: %d.%d\n", 1068 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1069 1070 rval = regs[o2i(capoff + PCI_AGP_STATUS)]; 1071 printf(" Status register: 0x%04x\n", rval); 1072 printf(" RQ: %d\n", 1073 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1074 printf(" ARQSZ: %d\n", 1075 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1076 printf(" CAL cycle: %s\n", 1077 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1078 onoff("SBA", rval, AGP_MODE_SBA); 1079 onoff("htrans#", rval, AGP_MODE_HTRANS); 1080 onoff("Over 4G", rval, AGP_MODE_4G); 1081 onoff("Fast Write", rval, AGP_MODE_FW); 1082 onoff("AGP 3.0 Mode", rval, AGP_MODE_MODE_3); 1083 isagp3 = rval & AGP_MODE_MODE_3; 1084 printf(" Data Rate Support: "); 1085 pci_conf_print_agp_datarate(rval, isagp3); 1086 1087 rval = regs[o2i(capoff + PCI_AGP_COMMAND)]; 1088 printf(" Command register: 0x%08x\n", rval); 1089 printf(" PRQ: %d\n", 1090 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1091 printf(" PARQSZ: %d\n", 1092 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1093 printf(" PCAL cycle: %s\n", 1094 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1095 onoff("SBA", rval, AGP_MODE_SBA); 1096 onoff("AGP", rval, AGP_MODE_AGP); 1097 onoff("Over 4G", rval, AGP_MODE_4G); 1098 onoff("Fast Write", rval, AGP_MODE_FW); 1099 if (isagp3) { 1100 printf(" Data Rate Enable: "); 1101 /* 1102 * The Data Rate Enable bits are used only on 3.0 and the 1103 * Command register has no AGP_MODE_MODE_3 bit, so pass the 1104 * flag to print correctly. 1105 */ 1106 pci_conf_print_agp_datarate(rval, isagp3); 1107 } 1108 } 1109 1110 static const char * 1111 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1112 { 1113 1114 switch ((caps >> 6) & 7) { 1115 case 0: return "self-powered"; 1116 case 1: return "55 mA"; 1117 case 2: return "100 mA"; 1118 case 3: return "160 mA"; 1119 case 4: return "220 mA"; 1120 case 5: return "270 mA"; 1121 case 6: return "320 mA"; 1122 case 7: 1123 default: return "375 mA"; 1124 } 1125 } 1126 1127 static const char * 1128 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1129 { 1130 static const char unk[] = "unknown"; 1131 static const char *pmrev[8] = { 1132 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1133 }; 1134 if (val > 7) 1135 return unk; 1136 return pmrev[val]; 1137 } 1138 1139 static void 1140 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1141 { 1142 uint16_t caps, pmcsr; 1143 pcireg_t reg; 1144 1145 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1146 reg = regs[o2i(capoff + PCI_PMCSR)]; 1147 pmcsr = reg & 0xffff; 1148 1149 printf("\n PCI Power Management Capabilities Register\n"); 1150 1151 printf(" Capabilities register: 0x%04x\n", caps); 1152 printf(" Version: %s\n", 1153 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1154 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1155 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1156 printf(" 3.3V auxiliary current: %s\n", 1157 pci_conf_print_pcipm_cap_aux(caps)); 1158 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1159 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1160 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1161 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1162 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1163 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1164 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1165 1166 printf(" Control/status register: 0x%04x\n", pmcsr); 1167 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1168 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1169 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1170 printf(" PME# assertion: %sabled\n", 1171 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1172 printf(" Data Select: %d\n", 1173 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK)); 1174 printf(" Data Scale: %d\n", 1175 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK)); 1176 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1177 printf(" Bridge Support Extensions register: 0x%02x\n", 1178 (reg >> 16) & 0xff); 1179 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1180 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1181 printf(" Data register: 0x%02x\n", __SHIFTOUT(reg, PCI_PMCSR_DATA)); 1182 1183 } 1184 1185 /* XXX pci_conf_print_vpd_cap */ 1186 /* XXX pci_conf_print_slotid_cap */ 1187 1188 static void 1189 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1190 { 1191 uint32_t ctl, mmc, mme; 1192 1193 regs += o2i(capoff); 1194 ctl = *regs++; 1195 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1196 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1197 1198 printf("\n PCI Message Signaled Interrupt\n"); 1199 1200 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1201 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1202 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1203 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1204 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1205 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1206 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1207 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1208 onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP); 1209 onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN); 1210 printf(" Message Address %sregister: 0x%08x\n", 1211 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1212 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1213 printf(" Message Address %sregister: 0x%08x\n", 1214 "(upper) ", *regs++); 1215 } 1216 printf(" Message Data register: 0x%04x\n", *regs & 0xffff); 1217 regs++; 1218 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1219 printf(" Vector Mask register: 0x%08x\n", *regs++); 1220 printf(" Vector Pending register: 0x%08x\n", *regs++); 1221 } 1222 } 1223 1224 /* XXX pci_conf_print_cpci_hostwap_cap */ 1225 1226 /* 1227 * For both command register and status register. 1228 * The argument "idx" is index number (0 to 7). 1229 */ 1230 static int 1231 pcix_split_trans(unsigned int idx) 1232 { 1233 static int table[8] = { 1234 1, 2, 3, 4, 8, 12, 16, 32 1235 }; 1236 1237 if (idx >= __arraycount(table)) 1238 return -1; 1239 return table[idx]; 1240 } 1241 1242 static void 1243 pci_conf_print_pcix_cap_2ndbusmode(int num) 1244 { 1245 const char *maxfreq, *maxperiod; 1246 1247 printf(" Mode: "); 1248 if (num <= 0x07) 1249 printf("PCI-X Mode 1\n"); 1250 else if (num <= 0x0b) 1251 printf("PCI-X 266 (Mode 2)\n"); 1252 else 1253 printf("PCI-X 533 (Mode 2)\n"); 1254 1255 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1256 switch (num & 0x03) { 1257 default: 1258 case 0: 1259 maxfreq = "N/A"; 1260 maxperiod = "N/A"; 1261 break; 1262 case 1: 1263 maxfreq = "66MHz"; 1264 maxperiod = "15ns"; 1265 break; 1266 case 2: 1267 maxfreq = "100MHz"; 1268 maxperiod = "10ns"; 1269 break; 1270 case 3: 1271 maxfreq = "133MHz"; 1272 maxperiod = "7.5ns"; 1273 break; 1274 } 1275 printf(" Max Clock Freq: %s\n", maxfreq); 1276 printf(" Min Clock Period: %s\n", maxperiod); 1277 } 1278 1279 static void 1280 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1281 { 1282 pcireg_t reg; 1283 int isbridge; 1284 int i; 1285 1286 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1287 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1288 printf("\n PCI-X %s Capabilities Register\n", 1289 isbridge ? "Bridge" : "Non-bridge"); 1290 1291 reg = regs[o2i(capoff)]; 1292 if (isbridge != 0) { 1293 printf(" Secondary status register: 0x%04x\n", 1294 (reg & 0xffff0000) >> 16); 1295 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1296 onoff("133MHz capable", reg, PCIX_STATUS_133); 1297 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1298 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1299 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1300 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1301 pci_conf_print_pcix_cap_2ndbusmode( 1302 __SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1303 printf(" Version: 0x%x\n", 1304 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1305 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1306 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1307 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1308 } else { 1309 printf(" Command register: 0x%04x\n", 1310 (reg & 0xffff0000) >> 16); 1311 onoff("Data Parity Error Recovery", reg, 1312 PCIX_CMD_PERR_RECOVER); 1313 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1314 printf(" Maximum Burst Read Count: %u\n", 1315 PCIX_CMD_BYTECNT(reg)); 1316 printf(" Maximum Split Transactions: %d\n", 1317 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1318 >> PCIX_CMD_SPLTRANS_SHIFT)); 1319 } 1320 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1321 printf(" %sStatus register: 0x%08x\n", 1322 isbridge ? "Bridge " : "", reg); 1323 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1324 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1325 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1326 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1327 onoff("133MHz capable", reg, PCIX_STATUS_133); 1328 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1329 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1330 if (isbridge != 0) { 1331 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1332 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1333 } else { 1334 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1335 "bridge device", "simple device"); 1336 printf(" Designed max memory read byte count: %d\n", 1337 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1338 >> PCIX_STATUS_MAXB_SHIFT)); 1339 printf(" Designed max outstanding split transaction: %d\n", 1340 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1341 >> PCIX_STATUS_MAXST_SHIFT)); 1342 printf(" MAX cumulative Read Size: %u\n", 1343 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1344 onoff("Received split completion error", reg, 1345 PCIX_STATUS_SCERR); 1346 } 1347 onoff("266MHz capable", reg, PCIX_STATUS_266); 1348 onoff("533MHz capable", reg, PCIX_STATUS_533); 1349 1350 if (isbridge == 0) 1351 return; 1352 1353 /* Only for bridge */ 1354 for (i = 0; i < 2; i++) { 1355 reg = regs[o2i(capoff + PCIX_BRIDGE_UP_STCR + (4 * i))]; 1356 printf(" %s split transaction control register: 0x%08x\n", 1357 (i == 0) ? "Upstream" : "Downstream", reg); 1358 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1359 printf(" Commitment Limit: %d\n", 1360 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1361 } 1362 } 1363 1364 /* pci_conf_print_ht_slave_cap */ 1365 /* pci_conf_print_ht_host_cap */ 1366 /* pci_conf_print_ht_switch_cap */ 1367 /* pci_conf_print_ht_intr_cap */ 1368 /* pci_conf_print_ht_revid_cap */ 1369 /* pci_conf_print_ht_unitid_cap */ 1370 /* pci_conf_print_ht_extcnf_cap */ 1371 /* pci_conf_print_ht_addrmap_cap */ 1372 /* pci_conf_print_ht_msimap_cap */ 1373 1374 static void 1375 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1376 { 1377 pcireg_t val; 1378 uint32_t lo, hi; 1379 1380 /* 1381 * Print the rest of the command register bits. Others are 1382 * printed in pci_conf_print_ht_cap(). 1383 */ 1384 val = regs[o2i(capoff + PCI_HT_CMD)]; 1385 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1386 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1387 1388 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1389 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1390 printf(" Address Low register: 0x%08x\n", lo); 1391 printf(" Address high register: 0x%08x\n", hi); 1392 printf(" Address: 0x%016" PRIx64 "\n", 1393 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1394 } 1395 1396 /* pci_conf_print_ht_droute_cap */ 1397 /* pci_conf_print_ht_vcset_cap */ 1398 /* pci_conf_print_ht_retry_cap */ 1399 /* pci_conf_print_ht_x86enc_cap */ 1400 /* pci_conf_print_ht_gen3_cap */ 1401 /* pci_conf_print_ht_fle_cap */ 1402 /* pci_conf_print_ht_pm_cap */ 1403 /* pci_conf_print_ht_hnc_cap */ 1404 1405 static const struct ht_types { 1406 pcireg_t cap; 1407 const char *name; 1408 void (*printfunc)(const pcireg_t *, int); 1409 } ht_captab[] = { 1410 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1411 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1412 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1413 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1414 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1415 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1416 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1417 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1418 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1419 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1420 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1421 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1422 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1423 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1424 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1425 {PCI_HT_CAP_PM, "Power Management", NULL }, 1426 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1427 }; 1428 1429 static void 1430 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1431 { 1432 pcireg_t val, foundcap; 1433 unsigned int off; 1434 1435 val = regs[o2i(capoff + PCI_HT_CMD)]; 1436 1437 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1438 1439 printf(" Command register: 0x%04x\n", val >> 16); 1440 foundcap = PCI_HT_CAP(val); 1441 for (off = 0; off < __arraycount(ht_captab); off++) { 1442 if (ht_captab[off].cap == foundcap) 1443 break; 1444 } 1445 printf(" Capability Type: 0x%02x ", foundcap); 1446 if (off >= __arraycount(ht_captab)) { 1447 printf("(unknown)\n"); 1448 return; 1449 } 1450 printf("(%s)\n", ht_captab[off].name); 1451 if (ht_captab[off].printfunc != NULL) 1452 ht_captab[off].printfunc(regs, capoff); 1453 } 1454 1455 static void 1456 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1457 { 1458 uint16_t caps; 1459 1460 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1461 1462 printf("\n PCI Vendor Specific Capabilities Register\n"); 1463 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1464 } 1465 1466 static void 1467 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1468 { 1469 pcireg_t val; 1470 1471 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1472 1473 printf("\n Debugport Capability Register\n"); 1474 printf(" Debug base Register: 0x%04x\n", 1475 val >> PCI_DEBUG_BASER_SHIFT); 1476 printf(" port offset: 0x%04x\n", 1477 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1478 printf(" BAR number: %u\n", 1479 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1480 } 1481 1482 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1483 /* XXX pci_conf_print_hotplug_cap */ 1484 1485 static void 1486 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1487 { 1488 pcireg_t reg; 1489 1490 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1491 1492 printf("\n Subsystem ID Capability Register\n"); 1493 printf(" Subsystem ID : 0x%08x\n", reg); 1494 } 1495 1496 /* XXX pci_conf_print_agp8_cap */ 1497 /* XXX pci_conf_print_secure_cap */ 1498 1499 static void 1500 pci_print_pcie_L0s_latency(uint32_t val) 1501 { 1502 1503 switch (val) { 1504 case 0x0: 1505 printf("Less than 64ns\n"); 1506 break; 1507 case 0x1: 1508 case 0x2: 1509 case 0x3: 1510 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1511 break; 1512 case 0x4: 1513 printf("512ns to less than 1us\n"); 1514 break; 1515 case 0x5: 1516 printf("1us to less than 2us\n"); 1517 break; 1518 case 0x6: 1519 printf("2us - 4us\n"); 1520 break; 1521 case 0x7: 1522 printf("More than 4us\n"); 1523 break; 1524 } 1525 } 1526 1527 static void 1528 pci_print_pcie_L1_latency(uint32_t val) 1529 { 1530 1531 switch (val) { 1532 case 0x0: 1533 printf("Less than 1us\n"); 1534 break; 1535 case 0x6: 1536 printf("32us - 64us\n"); 1537 break; 1538 case 0x7: 1539 printf("More than 64us\n"); 1540 break; 1541 default: 1542 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1543 break; 1544 } 1545 } 1546 1547 static void 1548 pci_print_pcie_compl_timeout(uint32_t val) 1549 { 1550 1551 switch (val) { 1552 case 0x0: 1553 printf("50us to 50ms\n"); 1554 break; 1555 case 0x5: 1556 printf("16ms to 55ms\n"); 1557 break; 1558 case 0x6: 1559 printf("65ms to 210ms\n"); 1560 break; 1561 case 0x9: 1562 printf("260ms to 900ms\n"); 1563 break; 1564 case 0xa: 1565 printf("1s to 3.5s\n"); 1566 break; 1567 default: 1568 printf("unknown %u value\n", val); 1569 break; 1570 } 1571 } 1572 1573 static const char * const pcie_linkspeeds[] = {"2.5", "2.5", "5.0", "8.0"}; 1574 1575 static void 1576 pci_print_pcie_linkspeed(pcireg_t val) 1577 { 1578 1579 if (val > __arraycount(pcie_linkspeeds)) 1580 printf("unknown value (%u)\n", val); 1581 else 1582 printf("%sGT/s\n", pcie_linkspeeds[val]); 1583 } 1584 1585 static void 1586 pci_print_pcie_linkspeedvector(pcireg_t val) 1587 { 1588 unsigned int i; 1589 1590 /* Start from 0 */ 1591 for (i = 0; i < 16; i++) 1592 if (((val >> i) & 0x01) != 0) { 1593 if (i >= __arraycount(pcie_linkspeeds)) 1594 printf(" unknown vector (0x%x)", 1 << i); 1595 else 1596 printf(" %sGT/s", pcie_linkspeeds[i]); 1597 } 1598 } 1599 1600 static void 1601 pci_print_pcie_link_deemphasis(pcireg_t val) 1602 { 1603 switch (val) { 1604 case 0: 1605 printf("-6dB"); 1606 break; 1607 case 1: 1608 printf("-3.5dB"); 1609 break; 1610 default: 1611 printf("(reserved value)"); 1612 } 1613 } 1614 1615 static void 1616 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1617 { 1618 pcireg_t reg; /* for each register */ 1619 pcireg_t val; /* for each bitfield */ 1620 bool check_link = false; 1621 bool check_slot = false; 1622 bool check_rootport = false; 1623 unsigned int pciever; 1624 unsigned int i; 1625 1626 printf("\n PCI Express Capabilities Register\n"); 1627 /* Capability Register */ 1628 reg = regs[o2i(capoff)]; 1629 printf(" Capability register: 0x%04x\n", reg >> 16); 1630 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1631 printf(" Capability version: %u\n", pciever); 1632 printf(" Device type: "); 1633 switch ((reg & 0x00f00000) >> 20) { 1634 case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */ 1635 printf("PCI Express Endpoint device\n"); 1636 check_link = true; 1637 break; 1638 case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */ 1639 printf("Legacy PCI Express Endpoint device\n"); 1640 check_link = true; 1641 break; 1642 case PCIE_XCAP_TYPE_ROOT: /* 0x4 */ 1643 printf("Root Port of PCI Express Root Complex\n"); 1644 check_link = true; 1645 check_slot = true; 1646 check_rootport = true; 1647 break; 1648 case PCIE_XCAP_TYPE_UP: /* 0x5 */ 1649 printf("Upstream Port of PCI Express Switch\n"); 1650 break; 1651 case PCIE_XCAP_TYPE_DOWN: /* 0x6 */ 1652 printf("Downstream Port of PCI Express Switch\n"); 1653 check_slot = true; 1654 check_rootport = true; 1655 break; 1656 case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */ 1657 printf("PCI Express to PCI/PCI-X Bridge\n"); 1658 break; 1659 case PCIE_XCAP_TYPE_PCI2PCIE: /* 0x8 */ 1660 printf("PCI/PCI-X to PCI Express Bridge\n"); 1661 break; 1662 case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */ 1663 printf("Root Complex Integrated Endpoint\n"); 1664 break; 1665 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */ 1666 check_rootport = true; 1667 printf("Root Complex Event Collector\n"); 1668 break; 1669 default: 1670 printf("unknown\n"); 1671 break; 1672 } 1673 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1674 printf(" Interrupt Message Number: 0x%02x\n", 1675 (unsigned int)__SHIFTOUT(reg, PCIE_XCAP_IRQ)); 1676 1677 /* Device Capability Register */ 1678 reg = regs[o2i(capoff + PCIE_DCAP)]; 1679 printf(" Device Capabilities Register: 0x%08x\n", reg); 1680 printf(" Max Payload Size Supported: %u bytes max\n", 1681 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1682 printf(" Phantom Functions Supported: "); 1683 switch (__SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) { 1684 case 0x0: 1685 printf("not available\n"); 1686 break; 1687 case 0x1: 1688 printf("MSB\n"); 1689 break; 1690 case 0x2: 1691 printf("two MSB\n"); 1692 break; 1693 case 0x3: 1694 printf("All three bits\n"); 1695 break; 1696 } 1697 printf(" Extended Tag Field Supported: %dbit\n", 1698 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1699 printf(" Endpoint L0 Acceptable Latency: "); 1700 pci_print_pcie_L0s_latency(__SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY)); 1701 printf(" Endpoint L1 Acceptable Latency: "); 1702 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY)); 1703 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1704 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1705 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1706 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1707 printf(" Captured Slot Power Limit Value: %u\n", 1708 (unsigned int)__SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL)); 1709 printf(" Captured Slot Power Limit Scale: %u\n", 1710 (unsigned int)__SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE)); 1711 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1712 1713 /* Device Control Register */ 1714 reg = regs[o2i(capoff + PCIE_DCSR)]; 1715 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1716 onoff("Correctable Error Reporting Enable", reg, 1717 PCIE_DCSR_ENA_COR_ERR); 1718 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1719 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1720 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1721 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1722 printf(" Max Payload Size: %d byte\n", 1723 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD)); 1724 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1725 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1726 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1727 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1728 printf(" Max Read Request Size: %d byte\n", 1729 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ)); 1730 1731 /* Device Status Register */ 1732 reg = regs[o2i(capoff + PCIE_DCSR)]; 1733 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1734 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1735 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1736 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1737 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1738 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1739 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1740 onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD); 1741 1742 if (check_link) { 1743 /* Link Capability Register */ 1744 reg = regs[o2i(capoff + PCIE_LCAP)]; 1745 printf(" Link Capabilities Register: 0x%08x\n", reg); 1746 printf(" Maximum Link Speed: "); 1747 pci_print_pcie_linkspeed(reg & PCIE_LCAP_MAX_SPEED); 1748 printf(" Maximum Link Width: x%u lanes\n", 1749 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH)); 1750 printf(" Active State PM Support: "); 1751 switch (__SHIFTOUT(reg, PCIE_LCAP_ASPM)) { 1752 case 0x0: 1753 printf("No ASPM support\n"); 1754 break; 1755 case 0x1: 1756 printf("L0s supported\n"); 1757 break; 1758 case 0x2: 1759 printf("L1 supported\n"); 1760 break; 1761 case 0x3: 1762 printf("L0s and L1 supported\n"); 1763 break; 1764 } 1765 printf(" L0 Exit Latency: "); 1766 pci_print_pcie_L0s_latency(__SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT)); 1767 printf(" L1 Exit Latency: "); 1768 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_LCAP_L1_EXIT)); 1769 printf(" Port Number: %u\n", 1770 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_PORT)); 1771 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1772 onoff("Surprise Down Error Report", reg, 1773 PCIE_LCAP_SURPRISE_DOWN); 1774 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1775 onoff("Link BW Notification Capable", reg, 1776 PCIE_LCAP_LINK_BW_NOTIFY); 1777 onoff("ASPM Optionally Compliance", reg, 1778 PCIE_LCAP_ASPM_COMPLIANCE); 1779 1780 /* Link Control Register */ 1781 reg = regs[o2i(capoff + PCIE_LCSR)]; 1782 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1783 printf(" Active State PM Control: "); 1784 switch (reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S)) { 1785 case 0: 1786 printf("disabled\n"); 1787 break; 1788 case 1: 1789 printf("L0s Entry Enabled\n"); 1790 break; 1791 case 2: 1792 printf("L1 Entry Enabled\n"); 1793 break; 1794 case 3: 1795 printf("L0s and L1 Entry Enabled\n"); 1796 break; 1797 } 1798 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1799 "128bytes", "64bytes"); 1800 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1801 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1802 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1803 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1804 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1805 onoff("Hardware Autonomous Width Disable", reg,PCIE_LCSR_HAWD); 1806 onoff("Link Bandwidth Management Interrupt Enable", reg, 1807 PCIE_LCSR_LBMIE); 1808 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1809 PCIE_LCSR_LABIE); 1810 printf(" DRS Signaling Control: "); 1811 switch (__SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) { 1812 case 0: 1813 printf("not reported\n"); 1814 break; 1815 case 1: 1816 printf("Interrupt Enabled\n"); 1817 break; 1818 case 2: 1819 printf("DRS to FRS Signaling Enabled\n"); 1820 break; 1821 default: 1822 printf("reserved\n"); 1823 break; 1824 } 1825 1826 /* Link Status Register */ 1827 reg = regs[o2i(capoff + PCIE_LCSR)]; 1828 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1829 printf(" Negotiated Link Speed: "); 1830 pci_print_pcie_linkspeed(__SHIFTOUT(reg, PCIE_LCSR_LINKSPEED)); 1831 printf(" Negotiated Link Width: x%u lanes\n", 1832 (unsigned int)__SHIFTOUT(reg, PCIE_LCSR_NLW)); 1833 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1834 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1835 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1836 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1837 onoff("Link Bandwidth Management Status", reg, 1838 PCIE_LCSR_LINK_BW_MGMT); 1839 onoff("Link Autonomous Bandwidth Status", reg, 1840 PCIE_LCSR_LINK_AUTO_BW); 1841 } 1842 1843 if (check_slot == true) { 1844 /* Slot Capability Register */ 1845 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1846 printf(" Slot Capability Register: 0x%08x\n", reg); 1847 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1848 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1849 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1850 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1851 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1852 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1853 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1854 printf(" Slot Power Limit Value: %d\n", 1855 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1856 printf(" Slot Power Limit Scale: %d\n", 1857 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1858 onoff("Electromechanical Interlock Present", reg, 1859 PCIE_SLCAP_EIP); 1860 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1861 printf(" Physical Slot Number: %d\n", 1862 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1863 1864 /* Slot Control Register */ 1865 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1866 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1867 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1868 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1869 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1870 onoff("Presense Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1871 onoff("Command Completed Interrupt Enabled", reg, 1872 PCIE_SLCSR_CCE); 1873 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1874 printf(" Attention Indicator Control: "); 1875 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1876 case 0x0: 1877 printf("reserved\n"); 1878 break; 1879 case 0x1: 1880 printf("on\n"); 1881 break; 1882 case 0x2: 1883 printf("blink\n"); 1884 break; 1885 case 0x3: 1886 printf("off\n"); 1887 break; 1888 } 1889 printf(" Power Indicator Control: "); 1890 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1891 case 0x0: 1892 printf("reserved\n"); 1893 break; 1894 case 0x1: 1895 printf("on\n"); 1896 break; 1897 case 0x2: 1898 printf("blink\n"); 1899 break; 1900 case 0x3: 1901 printf("off\n"); 1902 break; 1903 } 1904 printf(" Power Controller Control: Power %s\n", 1905 reg & PCIE_SLCSR_PCC ? "off" : "on"); 1906 onoff("Electromechanical Interlock Control", 1907 reg, PCIE_SLCSR_EIC); 1908 onoff("Data Link Layer State Changed Enable", reg, 1909 PCIE_SLCSR_DLLSCE); 1910 onoff("Auto Slot Power Limit Disable", reg, 1911 PCIE_SLCSR_AUTOSPLDIS); 1912 1913 /* Slot Status Register */ 1914 printf(" Slot Status Register: 0x%04x\n", reg >> 16); 1915 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1916 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1917 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1918 onoff("Presense Detect Changed", reg, PCIE_SLCSR_PDC); 1919 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1920 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1921 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1922 onoff("Electromechanical Interlock engaged", reg, 1923 PCIE_SLCSR_EIS); 1924 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 1925 } 1926 1927 if (check_rootport == true) { 1928 /* Root Control Register */ 1929 reg = regs[o2i(capoff + PCIE_RCR)]; 1930 printf(" Root Control Register: %04x\n", reg & 0xffff); 1931 onoff("SERR on Correctable Error Enable", reg, 1932 PCIE_RCR_SERR_CER); 1933 onoff("SERR on Non-Fatal Error Enable", reg, 1934 PCIE_RCR_SERR_NFER); 1935 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 1936 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 1937 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 1938 1939 /* Root Capability Register */ 1940 printf(" Root Capability Register: 0x%04x\n", 1941 reg >> 16); 1942 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 1943 1944 /* Root Status Register */ 1945 reg = regs[o2i(capoff + PCIE_RSR)]; 1946 printf(" Root Status Register: 0x%08x\n", reg); 1947 printf(" PME Requester ID: 0x%04x\n", 1948 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1949 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 1950 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 1951 } 1952 1953 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1954 if (pciever < 2) 1955 return; 1956 1957 /* Device Capabilities 2 */ 1958 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1959 printf(" Device Capabilities 2: 0x%08x\n", reg); 1960 printf(" Completion Timeout Ranges Supported: "); 1961 val = reg & PCIE_DCAP2_COMPT_RANGE; 1962 switch (val) { 1963 case 0: 1964 printf("not supported\n"); 1965 break; 1966 default: 1967 for (i = 0; i <= 3; i++) { 1968 if (((val >> i) & 0x01) != 0) 1969 printf("%c", 'A' + i); 1970 } 1971 printf("\n"); 1972 } 1973 onoff("Completion Timeout Disable Supported", reg, 1974 PCIE_DCAP2_COMPT_DIS); 1975 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 1976 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 1977 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 1978 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 1979 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 1980 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 1981 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 1982 printf(" TPH Completer Supported: "); 1983 switch (__SHIFTOUT(reg, PCIE_DCAP2_TPH_COMP)) { 1984 case 0: 1985 printf("Not supportted\n"); 1986 break; 1987 case 1: 1988 printf("TPH\n"); 1989 break; 1990 case 3: 1991 printf("TPH and Extended TPH\n"); 1992 break; 1993 default: 1994 printf("(reserved value)\n"); 1995 break; 1996 1997 } 1998 printf(" LN System CLS: "); 1999 switch (__SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 2000 case 0x0: 2001 printf("Not supported or not in effect\n"); 2002 break; 2003 case 0x1: 2004 printf("64byte cachelines in effect\n"); 2005 break; 2006 case 0x2: 2007 printf("128byte cachelines in effect\n"); 2008 break; 2009 case 0x3: 2010 printf("Reserved\n"); 2011 break; 2012 } 2013 printf(" OBFF Supported: "); 2014 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 2015 case 0x0: 2016 printf("Not supported\n"); 2017 break; 2018 case 0x1: 2019 printf("Message only\n"); 2020 break; 2021 case 0x2: 2022 printf("WAKE# only\n"); 2023 break; 2024 case 0x3: 2025 printf("Both\n"); 2026 break; 2027 } 2028 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 2029 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 2030 val = __SHIFTOUT(reg, PCIE_DCAP2_MAX_EETLP); 2031 printf(" Max End-End TLP Prefixes: %u\n", (val == 0) ? 4 : val); 2032 printf(" Emergency Power Reduction Supported: "); 2033 switch (__SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) { 2034 case 0x0: 2035 printf("Not supported\n"); 2036 break; 2037 case 0x1: 2038 printf("Device Specific mechanism\n"); 2039 break; 2040 case 0x2: 2041 printf("Form Factor spec or Device Specific mechanism\n"); 2042 break; 2043 case 0x3: 2044 printf("Reserved\n"); 2045 break; 2046 } 2047 onoff("Emergency Power Reduction Initialization Required", reg, 2048 PCIE_DCAP2_EMGPWRRED_INI); 2049 onoff("FRS Supported", reg, PCIE_DCAP2_FRS); 2050 2051 /* Device Control 2 */ 2052 reg = regs[o2i(capoff + PCIE_DCSR2)]; 2053 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 2054 printf(" Completion Timeout Value: "); 2055 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 2056 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 2057 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 2058 onoff("AtomicOp Rquester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 2059 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 2060 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 2061 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 2062 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 2063 onoff("Emergency Power Reduction Request", reg, 2064 PCIE_DCSR2_EMGPWRRED_REQ); 2065 printf(" OBFF: "); 2066 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 2067 case 0x0: 2068 printf("Disabled\n"); 2069 break; 2070 case 0x1: 2071 printf("Enabled with Message Signaling Variation A\n"); 2072 break; 2073 case 0x2: 2074 printf("Enabled with Message Signaling Variation B\n"); 2075 break; 2076 case 0x3: 2077 printf("Enabled using WAKE# signaling\n"); 2078 break; 2079 } 2080 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 2081 2082 if (check_link) { 2083 bool drs_supported = false; 2084 2085 /* Link Capability 2 */ 2086 reg = regs[o2i(capoff + PCIE_LCAP2)]; 2087 /* If the vector is 0, LCAP2 is not implemented */ 2088 if ((reg & PCIE_LCAP2_SUP_LNKSV) != 0) { 2089 printf(" Link Capabilities 2: 0x%08x\n", reg); 2090 printf(" Supported Link Speeds Vector:"); 2091 pci_print_pcie_linkspeedvector( 2092 __SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV)); 2093 printf("\n"); 2094 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 2095 printf(" " 2096 "Lower SKP OS Generation Supported Speed Vector:"); 2097 pci_print_pcie_linkspeedvector( 2098 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV)); 2099 printf("\n"); 2100 printf(" " 2101 "Lower SKP OS Reception Supported Speed Vector:"); 2102 pci_print_pcie_linkspeedvector( 2103 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV)); 2104 printf("\n"); 2105 onoff("DRS Supported", reg, PCIE_LCAP2_DRS); 2106 drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false; 2107 } 2108 2109 /* Link Control 2 */ 2110 reg = regs[o2i(capoff + PCIE_LCSR2)]; 2111 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 2112 printf(" Target Link Speed: "); 2113 pci_print_pcie_linkspeed(__SHIFTOUT(reg, 2114 PCIE_LCSR2_TGT_LSPEED)); 2115 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 2116 onoff("HW Autonomous Speed Disabled", reg, 2117 PCIE_LCSR2_HW_AS_DIS); 2118 printf(" Selectable De-emphasis: "); 2119 pci_print_pcie_link_deemphasis( 2120 __SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP)); 2121 printf("\n"); 2122 printf(" Transmit Margin: %u\n", 2123 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 2124 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 2125 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 2126 printf(" Compliance Present/De-emphasis: "); 2127 pci_print_pcie_link_deemphasis( 2128 __SHIFTOUT(reg, PCIE_LCSR2_COMP_DEEMP)); 2129 printf("\n"); 2130 2131 /* Link Status 2 */ 2132 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 2133 printf(" Current De-emphasis Level: "); 2134 pci_print_pcie_link_deemphasis( 2135 __SHIFTOUT(reg, PCIE_LCSR2_DEEMP_LVL)); 2136 printf("\n"); 2137 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 2138 onoff("Equalization Phase 1 Successful", reg, 2139 PCIE_LCSR2_EQP1_SUC); 2140 onoff("Equalization Phase 2 Successful", reg, 2141 PCIE_LCSR2_EQP2_SUC); 2142 onoff("Equalization Phase 3 Successful", reg, 2143 PCIE_LCSR2_EQP3_SUC); 2144 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 2145 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD); 2146 if (drs_supported) { 2147 printf(" Downstream Component Presence: "); 2148 switch (__SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) { 2149 case PCIE_DSCOMPN_DOWN_NOTDETERM: 2150 printf("Link Down - Presence Not" 2151 " Determined\n"); 2152 break; 2153 case PCIE_DSCOMPN_DOWN_NOTPRES: 2154 printf("Link Down - Component Not Present\n"); 2155 break; 2156 case PCIE_DSCOMPN_DOWN_PRES: 2157 printf("Link Down - Component Present\n"); 2158 break; 2159 case PCIE_DSCOMPN_UP_PRES: 2160 printf("Link Up - Component Present\n"); 2161 break; 2162 case PCIE_DSCOMPN_UP_PRES_DRS: 2163 printf("Link Up - Component Present and DRS" 2164 " received\n"); 2165 break; 2166 default: 2167 printf("reserved\n"); 2168 break; 2169 } 2170 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV); 2171 } 2172 } 2173 2174 /* Slot Capability 2 */ 2175 /* Slot Control 2 */ 2176 /* Slot Status 2 */ 2177 } 2178 2179 static void 2180 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 2181 { 2182 pcireg_t reg; 2183 2184 printf("\n MSI-X Capability Register\n"); 2185 2186 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2187 printf(" Message Control register: 0x%04x\n", 2188 (reg >> 16) & 0xff); 2189 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 2190 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 2191 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 2192 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 2193 printf(" Table offset register: 0x%08x\n", reg); 2194 printf(" Table offset: 0x%08x\n", 2195 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 2196 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 2197 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 2198 printf(" Pending bit array register: 0x%08x\n", reg); 2199 printf(" Pending bit array offset: 0x%08x\n", 2200 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 2201 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 2202 } 2203 2204 static void 2205 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 2206 { 2207 pcireg_t reg; 2208 2209 printf("\n Serial ATA Capability Register\n"); 2210 2211 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2212 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 2213 printf(" Revision: %u.%u\n", 2214 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 2215 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 2216 2217 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 2218 2219 printf(" BAR Register: 0x%08x\n", reg); 2220 printf(" Register location: "); 2221 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 2222 printf("in config space\n"); 2223 else { 2224 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 2225 printf(" BAR offset: 0x%08x\n", 2226 (pcireg_t)__SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 2227 } 2228 } 2229 2230 static void 2231 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 2232 { 2233 pcireg_t reg; 2234 2235 printf("\n Advanced Features Capability Register\n"); 2236 2237 reg = regs[o2i(capoff + PCI_AFCAPR)]; 2238 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 2239 printf(" AF Structure Length: 0x%02x\n", 2240 (pcireg_t)__SHIFTOUT(reg, PCI_AF_LENGTH)); 2241 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 2242 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 2243 reg = regs[o2i(capoff + PCI_AFCSR)]; 2244 printf(" AF Control register: 0x%02x\n", reg & 0xff); 2245 /* 2246 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 2247 * and it's always 0 on read 2248 */ 2249 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 2250 onoff("Transaction Pending", reg, PCI_AFSR_TP); 2251 } 2252 2253 static struct { 2254 pcireg_t cap; 2255 const char *name; 2256 void (*printfunc)(const pcireg_t *, int); 2257 } pci_captab[] = { 2258 { PCI_CAP_RESERVED0, "reserved", NULL }, 2259 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 2260 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 2261 { PCI_CAP_VPD, "VPD", NULL }, 2262 { PCI_CAP_SLOTID, "SlotID", NULL }, 2263 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 2264 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 2265 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2266 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2267 { PCI_CAP_VENDSPEC, "Vendor-specific", 2268 pci_conf_print_vendspec_cap }, 2269 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2270 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2271 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2272 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2273 pci_conf_print_subsystem_cap }, 2274 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2275 { PCI_CAP_SECURE, "Secure Device", NULL }, 2276 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2277 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2278 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2279 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2280 { PCI_CAP_EA, "Enhanced Allocation", NULL } 2281 }; 2282 2283 static int 2284 pci_conf_find_cap(const pcireg_t *regs, int capoff, unsigned int capid, 2285 int *offsetp) 2286 { 2287 pcireg_t rval; 2288 int off; 2289 2290 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2291 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2292 rval = regs[o2i(off)]; 2293 if (capid == PCI_CAPLIST_CAP(rval)) { 2294 if (offsetp != NULL) 2295 *offsetp = off; 2296 return 1; 2297 } 2298 } 2299 return 0; 2300 } 2301 2302 static void 2303 pci_conf_print_caplist( 2304 #ifdef _KERNEL 2305 pci_chipset_tag_t pc, pcitag_t tag, 2306 #endif 2307 const pcireg_t *regs, int capoff) 2308 { 2309 int off; 2310 pcireg_t foundcap; 2311 pcireg_t rval; 2312 bool foundtable[__arraycount(pci_captab)]; 2313 unsigned int i; 2314 2315 /* Clear table */ 2316 for (i = 0; i < __arraycount(pci_captab); i++) 2317 foundtable[i] = false; 2318 2319 /* Print capability register's offset and the type first */ 2320 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2321 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2322 rval = regs[o2i(off)]; 2323 printf(" Capability register at 0x%02x\n", off); 2324 2325 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2326 foundcap = PCI_CAPLIST_CAP(rval); 2327 if (foundcap < __arraycount(pci_captab)) { 2328 printf("%s)\n", pci_captab[foundcap].name); 2329 /* Mark as found */ 2330 foundtable[foundcap] = true; 2331 } else 2332 printf("unknown)\n"); 2333 } 2334 2335 /* 2336 * And then, print the detail of each capability registers 2337 * in capability value's order. 2338 */ 2339 for (i = 0; i < __arraycount(pci_captab); i++) { 2340 if (foundtable[i] == false) 2341 continue; 2342 2343 /* 2344 * The type was found. Search capability list again and 2345 * print all capabilities that the capabiliy type is 2346 * the same. This is required because some capabilities 2347 * appear multiple times (e.g. HyperTransport capability). 2348 */ 2349 #if 0 2350 if (pci_conf_find_cap(regs, capoff, i, &off)) { 2351 rval = regs[o2i(off)]; 2352 if (pci_captab[i].printfunc != NULL) 2353 pci_captab[i].printfunc(regs, off); 2354 } 2355 #else 2356 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2357 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2358 rval = regs[o2i(off)]; 2359 if ((PCI_CAPLIST_CAP(rval) == i) 2360 && (pci_captab[i].printfunc != NULL)) 2361 pci_captab[i].printfunc(regs, off); 2362 } 2363 #endif 2364 } 2365 } 2366 2367 /* Extended Capability */ 2368 2369 static void 2370 pci_conf_print_aer_cap_uc(pcireg_t reg) 2371 { 2372 2373 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2374 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2375 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2376 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP); 2377 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2378 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2379 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2380 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2381 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2382 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2383 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2384 onoff("Unsupported Request Error", reg, 2385 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2386 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2387 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2388 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2389 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2390 onoff("TLP Prefix Blocked Error", reg, 2391 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2392 onoff("Poisoned TLP Egress Blocked", reg, 2393 PCI_AER_UC_POISONTLP_EGRESS_BLOCKED); 2394 } 2395 2396 static void 2397 pci_conf_print_aer_cap_cor(pcireg_t reg) 2398 { 2399 2400 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2401 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2402 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2403 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2404 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2405 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2406 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2407 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2408 } 2409 2410 static void 2411 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2412 { 2413 2414 printf(" First Error Pointer: 0x%04x\n", 2415 (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2416 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2417 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2418 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2419 onoff("ECRC Check Enab", reg, PCI_AER_ECRC_CHECK_ENABLE); 2420 onoff("Multiple Header Recording Capable", reg, 2421 PCI_AER_MULT_HDR_CAPABLE); 2422 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE); 2423 onoff("Completion Timeout Prefix/Header Log Capable", reg, 2424 PCI_AER_COMPTOUTPRFXHDRLOG_CAP); 2425 2426 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2427 if (!tlp_prefix_log) 2428 return; 2429 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2430 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2431 } 2432 2433 static void 2434 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2435 { 2436 2437 onoff("Correctable Error Reporting Enable", reg, 2438 PCI_AER_ROOTERR_COR_ENABLE); 2439 onoff("Non-Fatal Error Reporting Enable", reg, 2440 PCI_AER_ROOTERR_NF_ENABLE); 2441 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2442 } 2443 2444 static void 2445 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2446 { 2447 2448 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2449 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2450 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2451 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2452 PCI_AER_ROOTERR_MULTI_UC_ERR); 2453 onoff("First Uncorrectable Fatal", reg,PCI_AER_ROOTERR_FIRST_UC_FATAL); 2454 onoff("Non-Fatal Error Messages Received", reg,PCI_AER_ROOTERR_NF_ERR); 2455 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2456 printf(" Advanced Error Interrupt Message Number: 0x%02x\n", 2457 (unsigned int)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2458 } 2459 2460 static void 2461 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2462 { 2463 2464 printf(" Correctable Source ID: 0x%04x\n", 2465 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2466 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2467 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2468 } 2469 2470 static void 2471 pci_conf_print_aer_cap(const pcireg_t *regs, int capoff, int extcapoff) 2472 { 2473 pcireg_t reg; 2474 int pcie_capoff; 2475 int pcie_devtype = -1; 2476 bool tlp_prefix_log = false; 2477 2478 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2479 reg = regs[o2i(pcie_capoff)]; 2480 pcie_devtype = PCIE_XCAP_TYPE(reg); 2481 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2482 if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2483 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2484 /* End-End TLP Prefix Supported */ 2485 if (reg & PCIE_DCAP2_EETLP_PREF) { 2486 tlp_prefix_log = true; 2487 } 2488 } 2489 } 2490 2491 printf("\n Advanced Error Reporting Register\n"); 2492 2493 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2494 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2495 pci_conf_print_aer_cap_uc(reg); 2496 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2497 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2498 pci_conf_print_aer_cap_uc(reg); 2499 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2500 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2501 pci_conf_print_aer_cap_uc(reg); 2502 2503 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2504 printf(" Correctable Error Status register: 0x%08x\n", reg); 2505 pci_conf_print_aer_cap_cor(reg); 2506 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2507 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2508 pci_conf_print_aer_cap_cor(reg); 2509 2510 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2511 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2512 reg); 2513 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2514 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2515 printf(" Header Log register:\n"); 2516 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2517 extcapoff + PCI_AER_ROOTERR_CMD); 2518 2519 switch (pcie_devtype) { 2520 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ 2521 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ 2522 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2523 printf(" Root Error Command register: 0x%08x\n", reg); 2524 pci_conf_print_aer_cap_rooterr_cmd(reg); 2525 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2526 printf(" Root Error Status register: 0x%08x\n", reg); 2527 pci_conf_print_aer_cap_rooterr_status(reg); 2528 2529 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2530 printf(" Error Source Identification: 0x%04x\n", reg); 2531 pci_conf_print_aer_cap_errsrc_id(reg); 2532 break; 2533 } 2534 2535 if (tlp_prefix_log) { 2536 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2537 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2538 } 2539 } 2540 2541 static void 2542 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2543 pcireg_t parbsel, int parbsize) 2544 { 2545 pcireg_t reg; 2546 int num = 16 << parbsel; 2547 int num_per_reg = sizeof(pcireg_t) / parbsize; 2548 int i, j; 2549 2550 /* First, dump the table */ 2551 for (i = 0; i < num; i += num_per_reg) { 2552 reg = regs[o2i(off + i / num_per_reg)]; 2553 printf(" %s Arbitration Table: 0x%08x\n", name, reg); 2554 } 2555 /* And then, decode each entry */ 2556 for (i = 0; i < num; i += num_per_reg) { 2557 reg = regs[o2i(off + i / num_per_reg)]; 2558 for (j = 0; j < num_per_reg; j++) 2559 printf(" Phase[%d]: %d\n", j, reg); 2560 } 2561 } 2562 2563 static void 2564 pci_conf_print_vc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2565 { 2566 pcireg_t reg, n; 2567 int parbtab, parbsize; 2568 pcireg_t parbsel; 2569 int varbtab, varbsize; 2570 pcireg_t varbsel; 2571 int i, count; 2572 2573 printf("\n Virtual Channel Register\n"); 2574 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2575 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2576 count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2577 printf(" Extended VC Count: %d\n", count); 2578 n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2579 printf(" Low Priority Extended VC Count: %u\n", n); 2580 n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2581 printf(" Reference Clock: %s\n", 2582 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 2583 parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2584 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2585 2586 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 2587 printf(" Port VC Capability register 2: 0x%08x\n", reg); 2588 onoff("Hardware fixed arbitration scheme", 2589 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 2590 onoff("WRR arbitration with 32 phases", 2591 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 2592 onoff("WRR arbitration with 64 phases", 2593 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 2594 onoff("WRR arbitration with 128 phases", 2595 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 2596 varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 2597 printf(" VC Arbitration Table Offset: 0x%x\n", varbtab); 2598 2599 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 2600 printf(" Port VC Control register: 0x%04x\n", reg); 2601 varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 2602 printf(" VC Arbitration Select: 0x%x\n", varbsel); 2603 2604 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 2605 printf(" Port VC Status register: 0x%04x\n", reg); 2606 onoff("VC Arbitration Table Status", 2607 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 2608 2609 for (i = 0; i < count + 1; i++) { 2610 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 2611 printf(" VC number %d\n", i); 2612 printf(" VC Resource Capability Register: 0x%08x\n", reg); 2613 onoff(" Non-configurable Hardware fixed arbitration scheme", 2614 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 2615 onoff(" WRR arbitration with 32 phases", 2616 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 2617 onoff(" WRR arbitration with 64 phases", 2618 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 2619 onoff(" WRR arbitration with 128 phases", 2620 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 2621 onoff(" Time-based WRR arbitration with 128 phases", 2622 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 2623 onoff(" WRR arbitration with 256 phases", 2624 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 2625 onoff(" Advanced Packet Switching", 2626 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 2627 onoff(" Reject Snoop Transaction", 2628 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 2629 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 2630 printf(" Maximum Time Slots: %d\n", n); 2631 parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S; 2632 printf(" Port Arbitration Table offset: 0x%02x\n", 2633 parbtab); 2634 2635 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 2636 printf(" VC Resource Control Register: 0x%08x\n", reg); 2637 printf(" TC/VC Map: 0x%02x\n", 2638 (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 2639 /* 2640 * The load Port Arbitration Table bit is used to update 2641 * the Port Arbitration logic and it's always 0 on read, so 2642 * we don't print it. 2643 */ 2644 parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 2645 printf(" Port Arbitration Select: 0x%x\n", parbsel); 2646 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 2647 printf(" VC ID %d\n", n); 2648 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 2649 2650 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 2651 printf(" VC Resource Status Register: 0x%08x\n", reg); 2652 onoff(" Port Arbitration Table Status", 2653 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 2654 onoff(" VC Negotiation Pending", 2655 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 2656 2657 if ((parbtab != 0) && (parbsel != 0)) 2658 pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab, 2659 "Port", parbsel, parbsize); 2660 } 2661 2662 varbsize = 8; 2663 if ((varbtab != 0) && (varbsel != 0)) 2664 pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab, 2665 " VC", varbsel, varbsize); 2666 } 2667 2668 static void 2669 pci_conf_print_pwrbdgt_base_power(uint8_t base, unsigned int scale) 2670 { 2671 if (base <= 0xef) { 2672 unsigned int sdiv = 1; 2673 for (unsigned int i = scale; i > 0; i--) 2674 sdiv *= 10; 2675 2676 printf("%u", base / sdiv); 2677 2678 if (scale != 0) { 2679 printf(".%u", base % sdiv); 2680 } 2681 printf ("W\n"); 2682 return; 2683 } 2684 2685 const char *s; 2686 2687 switch (base) { 2688 case 0xf0: 2689 s = "239W < x <= 250W"; 2690 break; 2691 case 0xf1: 2692 s = "250W < x <= 275W"; 2693 break; 2694 case 0xf2: 2695 s = "275W < x <= 300W"; 2696 break; 2697 default: 2698 s = "reserved for above 300W"; 2699 break; 2700 } 2701 printf("%s\n", s); 2702 } 2703 2704 static const char * 2705 pci_conf_print_pwrbdgt_type(uint8_t reg) 2706 { 2707 2708 switch (reg) { 2709 case 0x00: 2710 return "PME Aux"; 2711 case 0x01: 2712 return "Auxilary"; 2713 case 0x02: 2714 return "Idle"; 2715 case 0x03: 2716 return "Sustained"; 2717 case 0x04: 2718 return "Sustained (Emergency Power Reduction)"; 2719 case 0x05: 2720 return "Maximum (Emergency Power Reduction)"; 2721 case 0x07: 2722 return "Maximum"; 2723 default: 2724 return "Unknown"; 2725 } 2726 } 2727 2728 static const char * 2729 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 2730 { 2731 2732 switch (reg) { 2733 case 0x00: 2734 return "Power(12V)"; 2735 case 0x01: 2736 return "Power(3.3V)"; 2737 case 0x02: 2738 return "Power(1.5V or 1.8V)"; 2739 case 0x07: 2740 return "Thermal"; 2741 default: 2742 return "Unknown"; 2743 } 2744 } 2745 2746 static void 2747 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff) 2748 { 2749 pcireg_t reg; 2750 unsigned int scale; 2751 2752 printf("\n Power Budgeting\n"); 2753 2754 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 2755 printf(" Data Select register: 0x%08x\n", reg); 2756 2757 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 2758 printf(" Data register: 0x%08x\n", reg); 2759 scale = __SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE); 2760 printf(" Base Power: "); 2761 pci_conf_print_pwrbdgt_base_power((uint8_t)reg, scale); 2762 printf(" PM Sub State: 0x%hhx\n", 2763 (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 2764 printf(" PM State: D%u\n", 2765 (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 2766 printf(" Type: %s\n", 2767 pci_conf_print_pwrbdgt_type( 2768 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 2769 printf(" Power Rail: %s\n", 2770 pci_conf_print_pwrbdgt_pwrrail( 2771 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 2772 2773 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 2774 printf(" Power Budget Capability register: 0x%08x\n", reg); 2775 onoff("System Allocated", 2776 reg, PCI_PWRBDGT_CAP_SYSALLOC); 2777 } 2778 2779 static const char * 2780 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 2781 { 2782 2783 switch (type) { 2784 case 0x00: 2785 return "Configuration Space Element"; 2786 case 0x01: 2787 return "System Egress Port or internal sink (memory)"; 2788 case 0x02: 2789 return "Internal Root Complex Link"; 2790 default: 2791 return "Unknown"; 2792 } 2793 } 2794 2795 static void 2796 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int capoff, int extcapoff) 2797 { 2798 pcireg_t reg; 2799 unsigned char nent, linktype; 2800 int i; 2801 2802 printf("\n Root Complex Link Declaration\n"); 2803 2804 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 2805 printf(" Element Self Description Register: 0x%08x\n", reg); 2806 printf(" Element Type: %s\n", 2807 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 2808 nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 2809 printf(" Number of Link Entries: %hhu\n", nent); 2810 printf(" Component ID: %hhu\n", 2811 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 2812 printf(" Port Number: %hhu\n", 2813 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 2814 for (i = 0; i < nent; i++) { 2815 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 2816 printf(" Link Entry %d:\n", i + 1); 2817 printf(" Link Description Register: 0x%08x\n", reg); 2818 onoff(" Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID); 2819 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 2820 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 2821 "Configuration Space", "Memory-Mapped Space"); 2822 onoff(" Associated RCRB Header", reg, 2823 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 2824 printf(" Target Component ID: %hhu\n", 2825 (unsigned char)__SHIFTOUT(reg, 2826 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 2827 printf(" Target Port Number: %hhu\n", 2828 (unsigned char)__SHIFTOUT(reg, 2829 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 2830 2831 if (linktype == 0) { 2832 /* Memory-Mapped Space */ 2833 reg = regs[o2i(extcapoff 2834 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 2835 printf(" Link Address Low Register: 0x%08x\n", 2836 reg); 2837 reg = regs[o2i(extcapoff 2838 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 2839 printf(" Link Address High Register: 0x%08x\n", 2840 reg); 2841 } else { 2842 unsigned int nb; 2843 pcireg_t lo, hi; 2844 2845 /* Configuration Space */ 2846 lo = regs[o2i(extcapoff 2847 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 2848 printf(" Configuration Space Low Register: " 2849 "0x%08x\n", lo); 2850 hi = regs[o2i(extcapoff 2851 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 2852 printf(" Configuration Space High Register: " 2853 "0x%08x\n", hi); 2854 nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 2855 printf(" N: %u\n", nb); 2856 printf(" Func: %hhu\n", 2857 (unsigned char)__SHIFTOUT(lo, 2858 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 2859 printf(" Dev: %hhu\n", 2860 (unsigned char)__SHIFTOUT(lo, 2861 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 2862 printf(" Bus: %hhu\n", 2863 (unsigned char)__SHIFTOUT(lo, 2864 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 2865 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 2866 printf(" Configuration Space Base Address: " 2867 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 2868 } 2869 } 2870 } 2871 2872 /* XXX pci_conf_print_rclink_ctl_cap */ 2873 2874 static void 2875 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2876 { 2877 pcireg_t reg; 2878 2879 printf("\n Root Complex Event Collector Association\n"); 2880 2881 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 2882 printf(" Association Bitmap for Root Complex Integrated Devices:" 2883 " 0x%08x\n", reg); 2884 } 2885 2886 /* XXX pci_conf_print_mfvc_cap */ 2887 /* XXX pci_conf_print_vc2_cap */ 2888 /* XXX pci_conf_print_rcrb_cap */ 2889 /* XXX pci_conf_print_vendor_cap */ 2890 /* XXX pci_conf_print_cac_cap */ 2891 2892 static void 2893 pci_conf_print_acs_cap(const pcireg_t *regs, int capoff, int extcapoff) 2894 { 2895 pcireg_t reg, cap, ctl; 2896 unsigned int size, i; 2897 2898 printf("\n Access Control Services\n"); 2899 2900 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 2901 cap = reg & 0xffff; 2902 ctl = reg >> 16; 2903 printf(" ACS Capability register: 0x%08x\n", cap); 2904 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 2905 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 2906 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 2907 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 2908 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 2909 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 2910 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 2911 size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 2912 if (size == 0) 2913 size = 256; 2914 printf(" Egress Control Vector Size: %u\n", size); 2915 printf(" ACS Control register: 0x%08x\n", ctl); 2916 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 2917 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 2918 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 2919 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 2920 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 2921 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 2922 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 2923 2924 /* 2925 * If the P2P Egress Control Capability bit is 0, ignore the Egress 2926 * Control vector. 2927 */ 2928 if ((cap & PCI_ACS_CAP_E) == 0) 2929 return; 2930 for (i = 0; i < size; i += 32) 2931 printf(" Egress Control Vector [%u..%u]: 0x%08x\n", i + 31, 2932 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 2933 } 2934 2935 static void 2936 pci_conf_print_ari_cap(const pcireg_t *regs, int capoff, int extcapoff) 2937 { 2938 pcireg_t reg, cap, ctl; 2939 2940 printf("\n Alternative Routing-ID Interpretation Register\n"); 2941 2942 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2943 cap = reg & 0xffff; 2944 ctl = reg >> 16; 2945 printf(" Capability register: 0x%08x\n", cap); 2946 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 2947 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 2948 printf(" Next Function Number: %u\n", 2949 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 2950 printf(" Control register: 0x%08x\n", ctl); 2951 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 2952 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 2953 printf(" Function Group: %u\n", 2954 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 2955 } 2956 2957 static void 2958 pci_conf_print_ats_cap(const pcireg_t *regs, int capoff, int extcapoff) 2959 { 2960 pcireg_t reg, cap, ctl; 2961 unsigned int num; 2962 2963 printf("\n Address Translation Services\n"); 2964 2965 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2966 cap = reg & 0xffff; 2967 ctl = reg >> 16; 2968 printf(" Capability register: 0x%04x\n", cap); 2969 num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 2970 if (num == 0) 2971 num = 32; 2972 printf(" Invalidate Queue Depth: %u\n", num); 2973 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 2974 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 2975 2976 printf(" Control register: 0x%04x\n", ctl); 2977 printf(" Smallest Translation Unit: %u\n", 2978 (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU)); 2979 onoff("Enable", reg, PCI_ATS_CTL_EN); 2980 } 2981 2982 static void 2983 pci_conf_print_sernum_cap(const pcireg_t *regs, int capoff, int extcapoff) 2984 { 2985 pcireg_t lo, hi; 2986 2987 printf("\n Device Serial Number Register\n"); 2988 2989 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 2990 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 2991 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 2992 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 2993 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 2994 } 2995 2996 static void 2997 pci_conf_print_sriov_cap(const pcireg_t *regs, int capoff, int extcapoff) 2998 { 2999 char buf[sizeof("99999 MB")]; 3000 pcireg_t reg; 3001 pcireg_t total_vfs; 3002 int i; 3003 bool first; 3004 3005 printf("\n Single Root IO Virtualization Register\n"); 3006 3007 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 3008 printf(" Capabilities register: 0x%08x\n", reg); 3009 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 3010 onoff("ARI Capable Hierarchy Preserved", reg, 3011 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 3012 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 3013 printf(" VF Migration Interrupt Message Number: 0x%03x\n", 3014 (pcireg_t)__SHIFTOUT(reg, 3015 PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 3016 } 3017 3018 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 3019 printf(" Control register: 0x%04x\n", reg); 3020 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 3021 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 3022 onoff("VF Migration Interrupt Enable", reg, 3023 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 3024 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 3025 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 3026 3027 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 3028 printf(" Status register: 0x%04x\n", reg); 3029 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 3030 3031 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 3032 printf(" InitialVFs register: 0x%04x\n", reg); 3033 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 3034 printf(" TotalVFs register: 0x%04x\n", reg); 3035 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 3036 printf(" NumVFs register: 0x%04x\n", reg); 3037 3038 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 3039 printf(" Function Dependency Link register: 0x%04x\n", reg); 3040 3041 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 3042 printf(" First VF Offset register: 0x%04x\n", reg); 3043 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 3044 printf(" VF Stride register: 0x%04x\n", reg); 3045 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_DID)] >> 16; 3046 printf(" Device ID: 0x%04x\n", reg); 3047 3048 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 3049 printf(" Supported Page Sizes register: 0x%08x\n", reg); 3050 printf(" Supported Page Size:"); 3051 for (i = 0, first = true; i < 32; i++) { 3052 if (reg & __BIT(i)) { 3053 #ifdef _KERNEL 3054 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 3055 #else 3056 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 3057 HN_AUTOSCALE, 0); 3058 #endif 3059 printf("%s %s", first ? "" : ",", buf); 3060 first = false; 3061 } 3062 } 3063 printf("\n"); 3064 3065 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 3066 printf(" System Page Sizes register: 0x%08x\n", reg); 3067 printf(" Page Size: "); 3068 if (reg != 0) { 3069 #ifdef _KERNEL 3070 format_bytes(buf, sizeof(buf), 1LL << (ffs(reg) + 12)); 3071 #else 3072 humanize_number(buf, sizeof(buf), 1LL << (ffs(reg) + 12), "B", 3073 HN_AUTOSCALE, 0); 3074 #endif 3075 printf("%s", buf); 3076 } else { 3077 printf("unknown"); 3078 } 3079 printf("\n"); 3080 3081 for (i = 0; i < 6; i++) { 3082 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 3083 printf(" VF BAR%d register: 0x%08x\n", i, reg); 3084 } 3085 3086 if (total_vfs > 0) { 3087 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 3088 printf(" VF Migration State Array Offset register: 0x%08x\n", 3089 reg); 3090 printf(" VF Migration State Offset: 0x%08x\n", 3091 (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 3092 i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 3093 printf(" VF Migration State BIR: "); 3094 if (i >= 0 && i <= 5) { 3095 printf("BAR%d", i); 3096 } else { 3097 printf("unknown BAR (%d)", i); 3098 } 3099 printf("\n"); 3100 } 3101 } 3102 3103 /* XXX pci_conf_print_mriov_cap */ 3104 3105 static void 3106 pci_conf_print_multicast_cap(const pcireg_t *regs, int capoff, int extcapoff) 3107 { 3108 pcireg_t reg, cap, ctl; 3109 pcireg_t regl, regh; 3110 uint64_t addr; 3111 int n; 3112 3113 printf("\n Multicast\n"); 3114 3115 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 3116 cap = reg & 0xffff; 3117 ctl = reg >> 16; 3118 printf(" Capability Register: 0x%04x\n", cap); 3119 printf(" Max Group: %u\n", 3120 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 3121 3122 /* Endpoint Only */ 3123 n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 3124 if (n > 0) 3125 printf(" Windw Size Requested: %d\n", 1 << (n - 1)); 3126 3127 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 3128 3129 printf(" Control Register: 0x%04x\n", ctl); 3130 printf(" Num Group: %u\n", 3131 (unsigned int)__SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 3132 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 3133 3134 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 3135 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 3136 printf(" Base Address Register 0: 0x%08x\n", regl); 3137 printf(" Base Address Register 1: 0x%08x\n", regh); 3138 printf(" Index Position: %u\n", 3139 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 3140 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 3141 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 3142 3143 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 3144 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 3145 printf(" Receive Register 0: 0x%08x\n", regl); 3146 printf(" Receive Register 1: 0x%08x\n", regh); 3147 3148 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 3149 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 3150 printf(" Block All Register 0: 0x%08x\n", regl); 3151 printf(" Block All Register 1: 0x%08x\n", regh); 3152 3153 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 3154 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 3155 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 3156 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 3157 3158 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 3159 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 3160 printf(" Overlay BAR 0: 0x%08x\n", regl); 3161 printf(" Overlay BAR 1: 0x%08x\n", regh); 3162 3163 n = regl & PCI_MCAST_OVERLAYL_SIZE; 3164 printf(" Overlay Size: "); 3165 if (n >= 6) 3166 printf("%d\n", n); 3167 else 3168 printf("off\n"); 3169 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 3170 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 3171 } 3172 3173 static void 3174 pci_conf_print_page_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3175 { 3176 pcireg_t reg, ctl, sta; 3177 3178 printf("\n Page Request\n"); 3179 3180 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 3181 ctl = reg & 0xffff; 3182 sta = reg >> 16; 3183 printf(" Control Register: 0x%04x\n", ctl); 3184 onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E); 3185 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 3186 3187 printf(" Status Register: 0x%04x\n", sta); 3188 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 3189 onoff("Unexpected Page Request Group Index", reg, 3190 PCI_PAGE_REQ_STA_UPRGI); 3191 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 3192 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 3193 3194 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 3195 printf(" Outstanding Page Request Capacity: %u\n", reg); 3196 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 3197 printf(" Outstanding Page Request Allocation: %u\n", reg); 3198 } 3199 3200 /* XXX pci_conf_print_amd_cap */ 3201 3202 #define MEM_PBUFSIZE sizeof("999GB") 3203 3204 static void 3205 pci_conf_print_resizbar_cap(const pcireg_t *regs, int capoff, int extcapoff) 3206 { 3207 pcireg_t cap, ctl; 3208 unsigned int bars, i, n; 3209 char pbuf[MEM_PBUFSIZE]; 3210 3211 printf("\n Resizable BAR\n"); 3212 3213 /* Get Number of Resizable BARs */ 3214 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))]; 3215 bars = __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR); 3216 printf(" Number of Resizable BARs: "); 3217 if (bars <= 6) 3218 printf("%u\n", bars); 3219 else { 3220 printf("incorrect (%u)\n", bars); 3221 return; 3222 } 3223 3224 for (n = 0; n < 6; n++) { 3225 cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))]; 3226 printf(" Capability register(%u): 0x%08x\n", n, cap); 3227 if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0) 3228 continue; /* Not Used */ 3229 printf(" Acceptable BAR sizes:"); 3230 for (i = 4; i <= 23; i++) { 3231 if ((cap & (1 << i)) != 0) { 3232 humanize_number(pbuf, MEM_PBUFSIZE, 3233 (int64_t)1024 * 1024 << (i - 4), "B", 3234 #ifdef _KERNEL 3235 1); 3236 #else 3237 HN_AUTOSCALE, HN_NOSPACE); 3238 #endif 3239 printf(" %s", pbuf); 3240 } 3241 } 3242 printf("\n"); 3243 3244 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))]; 3245 printf(" Control register(%u): 0x%08x\n", n, ctl); 3246 printf(" BAR Index: %u\n", 3247 (unsigned int)__SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX)); 3248 humanize_number(pbuf, MEM_PBUFSIZE, 3249 (int64_t)1024 * 1024 3250 << __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ), 3251 "B", 3252 #ifdef _KERNEL 3253 1); 3254 #else 3255 HN_AUTOSCALE, HN_NOSPACE); 3256 #endif 3257 printf(" BAR Size: %s\n", pbuf); 3258 } 3259 } 3260 3261 static void 3262 pci_conf_print_dpa_cap(const pcireg_t *regs, int capoff, int extcapoff) 3263 { 3264 pcireg_t reg; 3265 unsigned int substmax, i; 3266 3267 printf("\n Dynamic Power Allocation\n"); 3268 3269 reg = regs[o2i(extcapoff + PCI_DPA_CAP)]; 3270 printf(" Capability register: 0x%08x\n", reg); 3271 substmax = __SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX); 3272 printf(" Substate Max: %u\n", substmax); 3273 printf(" Transition Latency Unit: "); 3274 switch (__SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) { 3275 case 0: 3276 printf("1ms\n"); 3277 break; 3278 case 1: 3279 printf("10ms\n"); 3280 break; 3281 case 2: 3282 printf("100ms\n"); 3283 break; 3284 default: 3285 printf("reserved\n"); 3286 break; 3287 } 3288 printf(" Power Allocation Scale: "); 3289 switch (__SHIFTOUT(reg, PCI_DPA_CAP_PAS)) { 3290 case 0: 3291 printf("10.0x\n"); 3292 break; 3293 case 1: 3294 printf("1.0x\n"); 3295 break; 3296 case 2: 3297 printf("0.1x\n"); 3298 break; 3299 case 3: 3300 printf("0.01x\n"); 3301 break; 3302 } 3303 printf(" Transition Latency Value 0: %u\n", 3304 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY0)); 3305 printf(" Transition Latency Value 1: %u\n", 3306 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY1)); 3307 3308 reg = regs[o2i(extcapoff + PCI_DPA_LATIND)]; 3309 printf(" Latency Indicatior register: 0x%08x\n", reg); 3310 3311 reg = regs[o2i(extcapoff + PCI_DPA_CS)]; 3312 printf(" Status register: 0x%04x\n", reg & 0xffff); 3313 printf(" Substate Status: 0x%02x\n", 3314 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT)); 3315 onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN); 3316 printf(" Control register: 0x%04x\n", reg >> 16); 3317 printf(" Substate Control: 0x%02x\n", 3318 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL)); 3319 3320 for (i = 0; i <= substmax; i++) 3321 printf(" Substate Power Allocation register %d: 0x%02x\n", 3322 i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff)); 3323 } 3324 3325 static const char * 3326 pci_conf_print_tph_req_cap_sttabloc(unsigned char val) 3327 { 3328 3329 switch (val) { 3330 case 0x0: 3331 return "Not Present"; 3332 case 0x1: 3333 return "in the TPH Requester Capability Structure"; 3334 case 0x2: 3335 return "in the MSI-X Table"; 3336 default: 3337 return "Unknown"; 3338 } 3339 } 3340 3341 static void 3342 pci_conf_print_tph_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3343 { 3344 pcireg_t reg; 3345 int size, i, j; 3346 3347 printf("\n TPH Requester Extended Capability\n"); 3348 3349 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 3350 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 3351 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 3352 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 3353 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 3354 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 3355 printf(" ST Table Location: %s\n", 3356 pci_conf_print_tph_req_cap_sttabloc( 3357 (unsigned char)__SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC))); 3358 size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 3359 printf(" ST Table Size: %d\n", size); 3360 for (i = 0; i < size ; i += 2) { 3361 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 3362 for (j = 0; j < 2 ; j++) { 3363 uint32_t entry = reg; 3364 3365 if (j != 0) 3366 entry >>= 16; 3367 entry &= 0xffff; 3368 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 3369 i + j, entry); 3370 } 3371 } 3372 } 3373 3374 static void 3375 pci_conf_print_ltr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3376 { 3377 pcireg_t reg; 3378 3379 printf("\n Latency Tolerance Reporting\n"); 3380 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)] & 0xffff; 3381 printf(" Max Snoop Latency Register: 0x%04x\n", reg); 3382 printf(" Max Snoop LatencyValue: %u\n", 3383 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL)); 3384 printf(" Max Snoop LatencyScale: %uns\n", 3385 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE))); 3386 reg = regs[o2i(extcapoff + PCI_LTR_MAXNOSNOOPLAT)] >> 16; 3387 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg); 3388 printf(" Max No-Snoop LatencyValue: %u\n", 3389 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL)); 3390 printf(" Max No-Snoop LatencyScale: %uns\n", 3391 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE))); 3392 } 3393 3394 static void 3395 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int capoff, int extcapoff) 3396 { 3397 int pcie_capoff; 3398 pcireg_t reg; 3399 int i, maxlinkwidth; 3400 3401 printf("\n Secondary PCI Express Register\n"); 3402 3403 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3404 printf(" Link Control 3 register: 0x%08x\n", reg); 3405 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3406 onoff("Link Equalization Request Interrupt Enable", 3407 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3408 printf(" Enable Lower SKP OS Generation Vector:"); 3409 pci_print_pcie_linkspeedvector( 3410 __SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV)); 3411 printf("\n"); 3412 3413 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3414 printf(" Lane Error Status register: 0x%08x\n", reg); 3415 3416 /* Get Max Link Width */ 3417 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)){ 3418 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3419 maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3420 } else { 3421 printf("error: falied to get PCIe capablity\n"); 3422 return; 3423 } 3424 for (i = 0; i < maxlinkwidth; i++) { 3425 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3426 if (i % 2 != 0) 3427 reg >>= 16; 3428 else 3429 reg &= 0xffff; 3430 printf(" Equalization Control Register (Link %d): 0x%04x\n", 3431 i, reg); 3432 printf(" Downstream Port Transmit Preset: 0x%x\n", 3433 (pcireg_t)__SHIFTOUT(reg, 3434 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3435 printf(" Downstream Port Receive Hint: 0x%x\n", 3436 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3437 printf(" Upstream Port Transmit Preset: 0x%x\n", 3438 (pcireg_t)__SHIFTOUT(reg, 3439 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3440 printf(" Upstream Port Receive Hint: 0x%x\n", 3441 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3442 } 3443 } 3444 3445 /* XXX pci_conf_print_pmux_cap */ 3446 3447 static void 3448 pci_conf_print_pasid_cap(const pcireg_t *regs, int capoff, int extcapoff) 3449 { 3450 pcireg_t reg, cap, ctl; 3451 unsigned int num; 3452 3453 printf("\n Process Address Space ID\n"); 3454 3455 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3456 cap = reg & 0xffff; 3457 ctl = reg >> 16; 3458 printf(" PASID Capability Register: 0x%04x\n", cap); 3459 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3460 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3461 num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3462 printf(" Max PASID Width: %u\n", num); 3463 3464 printf(" PASID Control Register: 0x%04x\n", ctl); 3465 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3466 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3467 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 3468 } 3469 3470 static void 3471 pci_conf_print_lnr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3472 { 3473 pcireg_t reg, cap, ctl; 3474 unsigned int num; 3475 3476 printf("\n LN Requester\n"); 3477 3478 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 3479 cap = reg & 0xffff; 3480 ctl = reg >> 16; 3481 printf(" LNR Capability register: 0x%04x\n", cap); 3482 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 3483 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 3484 num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 3485 printf(" LNR Registration MAX: %u\n", num); 3486 3487 printf(" LNR Control register: 0x%04x\n", ctl); 3488 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 3489 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 3490 num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 3491 printf(" LNR Registration Limit: %u\n", num); 3492 } 3493 3494 /* XXX pci_conf_print_dpc_cap */ 3495 3496 static int 3497 pci_conf_l1pm_cap_tposcale(unsigned char scale) 3498 { 3499 3500 /* Return scale in us */ 3501 switch (scale) { 3502 case 0x0: 3503 return 2; 3504 case 0x1: 3505 return 10; 3506 case 0x2: 3507 return 100; 3508 default: 3509 return -1; 3510 } 3511 } 3512 3513 static void 3514 pci_conf_print_l1pm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3515 { 3516 pcireg_t reg; 3517 int scale, val; 3518 3519 printf("\n L1 PM Substates\n"); 3520 3521 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 3522 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 3523 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 3524 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 3525 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 3526 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 3527 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 3528 printf(" Port Common Mode Restore Time: %uus\n", 3529 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 3530 scale = pci_conf_l1pm_cap_tposcale( 3531 __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 3532 val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 3533 printf(" Port T_POWER_ON: "); 3534 if (scale == -1) 3535 printf("unknown\n"); 3536 else 3537 printf("%dus\n", val * scale); 3538 3539 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 3540 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 3541 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 3542 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 3543 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 3544 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 3545 printf(" Common Mode Restore Time: %uus\n", 3546 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 3547 scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 3548 val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 3549 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 3550 3551 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 3552 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 3553 scale = pci_conf_l1pm_cap_tposcale( 3554 __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 3555 val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 3556 printf(" T_POWER_ON: "); 3557 if (scale == -1) 3558 printf("unknown\n"); 3559 else 3560 printf("%dus\n", val * scale); 3561 } 3562 3563 static void 3564 pci_conf_print_ptm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3565 { 3566 pcireg_t reg; 3567 uint32_t val; 3568 3569 printf("\n Precision Time Management\n"); 3570 3571 reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; 3572 printf(" PTM Capability register: 0x%08x\n", reg); 3573 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ); 3574 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP); 3575 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT); 3576 printf(" Local Clock Granularity: "); 3577 val = __SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL); 3578 switch (val) { 3579 case 0: 3580 printf("Not implemented\n"); 3581 break; 3582 case 0xffff: 3583 printf("> 254ns\n"); 3584 break; 3585 default: 3586 printf("%uns\n", val); 3587 break; 3588 } 3589 3590 reg = regs[o2i(extcapoff + PCI_PTM_CTL)]; 3591 printf(" PTM Control register: 0x%08x\n", reg); 3592 onoff("PTM Enable", reg, PCI_PTM_CTL_EN); 3593 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL); 3594 printf(" Effective Granularity: "); 3595 val = __SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL); 3596 switch (val) { 3597 case 0: 3598 printf("Unknown\n"); 3599 break; 3600 case 0xffff: 3601 printf("> 254ns\n"); 3602 break; 3603 default: 3604 printf("%uns\n", val); 3605 break; 3606 } 3607 } 3608 3609 /* XXX pci_conf_print_mpcie_cap */ 3610 /* XXX pci_conf_print_frsq_cap */ 3611 /* XXX pci_conf_print_rtr_cap */ 3612 /* XXX pci_conf_print_desigvndsp_cap */ 3613 /* XXX pci_conf_print_vf_resizbar_cap */ 3614 3615 #undef MS 3616 #undef SM 3617 #undef RW 3618 3619 static struct { 3620 pcireg_t cap; 3621 const char *name; 3622 void (*printfunc)(const pcireg_t *, int, int); 3623 } pci_extcaptab[] = { 3624 { 0, "reserved", 3625 NULL }, 3626 { PCI_EXTCAP_AER, "Advanced Error Reporting", 3627 pci_conf_print_aer_cap }, 3628 { PCI_EXTCAP_VC, "Virtual Channel", 3629 pci_conf_print_vc_cap }, 3630 { PCI_EXTCAP_SERNUM, "Device Serial Number", 3631 pci_conf_print_sernum_cap }, 3632 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 3633 pci_conf_print_pwrbdgt_cap }, 3634 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 3635 pci_conf_print_rclink_dcl_cap }, 3636 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 3637 NULL }, 3638 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 3639 pci_conf_print_rcec_assoc_cap }, 3640 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 3641 NULL }, 3642 { PCI_EXTCAP_VC2, "Virtual Channel", 3643 NULL }, 3644 { PCI_EXTCAP_RCRB, "RCRB Header", 3645 NULL }, 3646 { PCI_EXTCAP_VENDOR, "Vendor Unique", 3647 NULL }, 3648 { PCI_EXTCAP_CAC, "Configuration Access Correction", 3649 NULL }, 3650 { PCI_EXTCAP_ACS, "Access Control Services", 3651 pci_conf_print_acs_cap }, 3652 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 3653 pci_conf_print_ari_cap }, 3654 { PCI_EXTCAP_ATS, "Address Translation Services", 3655 pci_conf_print_ats_cap }, 3656 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 3657 pci_conf_print_sriov_cap }, 3658 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 3659 NULL }, 3660 { PCI_EXTCAP_MCAST, "Multicast", 3661 pci_conf_print_multicast_cap }, 3662 { PCI_EXTCAP_PAGE_REQ, "Page Request", 3663 pci_conf_print_page_req_cap }, 3664 { PCI_EXTCAP_AMD, "Reserved for AMD", 3665 NULL }, 3666 { PCI_EXTCAP_RESIZBAR, "Resizable BAR", 3667 pci_conf_print_resizbar_cap }, 3668 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 3669 pci_conf_print_dpa_cap }, 3670 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 3671 pci_conf_print_tph_req_cap }, 3672 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 3673 pci_conf_print_ltr_cap }, 3674 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 3675 pci_conf_print_sec_pcie_cap }, 3676 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 3677 NULL }, 3678 { PCI_EXTCAP_PASID, "Process Address Space ID", 3679 pci_conf_print_pasid_cap }, 3680 { PCI_EXTCAP_LN_REQ, "LN Requester", 3681 pci_conf_print_lnr_cap }, 3682 { PCI_EXTCAP_DPC, "Downstream Port Containment", 3683 NULL }, 3684 { PCI_EXTCAP_L1PM, "L1 PM Substates", 3685 pci_conf_print_l1pm_cap }, 3686 { PCI_EXTCAP_PTM, "Precision Time Management", 3687 pci_conf_print_ptm_cap }, 3688 { PCI_EXTCAP_MPCIE, "M-PCIe", 3689 NULL }, 3690 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 3691 NULL }, 3692 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 3693 NULL }, 3694 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 3695 NULL }, 3696 { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs", 3697 NULL }, 3698 }; 3699 3700 static int 3701 pci_conf_find_extcap(const pcireg_t *regs, int capoff, unsigned int capid, 3702 int *offsetp) 3703 { 3704 int off; 3705 pcireg_t rval; 3706 3707 for (off = PCI_EXTCAPLIST_BASE; 3708 off != 0; 3709 off = PCI_EXTCAPLIST_NEXT(rval)) { 3710 rval = regs[o2i(off)]; 3711 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 3712 if (offsetp != NULL) 3713 *offsetp = off; 3714 return 1; 3715 } 3716 } 3717 return 0; 3718 } 3719 3720 static void 3721 pci_conf_print_extcaplist( 3722 #ifdef _KERNEL 3723 pci_chipset_tag_t pc, pcitag_t tag, 3724 #endif 3725 const pcireg_t *regs, int capoff) 3726 { 3727 int off; 3728 pcireg_t foundcap; 3729 pcireg_t rval; 3730 bool foundtable[__arraycount(pci_extcaptab)]; 3731 unsigned int i; 3732 3733 /* Check Extended capability structure */ 3734 off = PCI_EXTCAPLIST_BASE; 3735 rval = regs[o2i(off)]; 3736 if (rval == 0xffffffff || rval == 0) 3737 return; 3738 3739 /* Clear table */ 3740 for (i = 0; i < __arraycount(pci_extcaptab); i++) 3741 foundtable[i] = false; 3742 3743 /* Print extended capability register's offset and the type first */ 3744 for (;;) { 3745 printf(" Extended Capability Register at 0x%02x\n", off); 3746 3747 foundcap = PCI_EXTCAPLIST_CAP(rval); 3748 printf(" type: 0x%04x (", foundcap); 3749 if (foundcap < __arraycount(pci_extcaptab)) { 3750 printf("%s)\n", pci_extcaptab[foundcap].name); 3751 /* Mark as found */ 3752 foundtable[foundcap] = true; 3753 } else 3754 printf("unknown)\n"); 3755 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 3756 3757 off = PCI_EXTCAPLIST_NEXT(rval); 3758 if (off == 0) 3759 break; 3760 else if (off <= PCI_CONF_SIZE) { 3761 printf(" next pointer: 0x%03x (incorrect)\n", off); 3762 return; 3763 } 3764 rval = regs[o2i(off)]; 3765 } 3766 3767 /* 3768 * And then, print the detail of each capability registers 3769 * in capability value's order. 3770 */ 3771 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 3772 if (foundtable[i] == false) 3773 continue; 3774 3775 /* 3776 * The type was found. Search capability list again and 3777 * print all capabilities that the capabiliy type is 3778 * the same. 3779 */ 3780 if (pci_conf_find_extcap(regs, capoff, i, &off) == 0) 3781 continue; 3782 rval = regs[o2i(off)]; 3783 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 3784 || (pci_extcaptab[i].printfunc == NULL)) 3785 continue; 3786 3787 pci_extcaptab[i].printfunc(regs, capoff, off); 3788 3789 } 3790 } 3791 3792 /* Print the Secondary Status Register. */ 3793 static void 3794 pci_conf_print_ssr(pcireg_t rval) 3795 { 3796 pcireg_t devsel; 3797 3798 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 3799 onoff("66 MHz capable", rval, __BIT(5)); 3800 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 3801 onoff("Fast back-to-back capable", rval, __BIT(7)); 3802 onoff("Data parity error detected", rval, __BIT(8)); 3803 3804 printf(" DEVSEL timing: "); 3805 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 3806 switch (devsel) { 3807 case 0: 3808 printf("fast"); 3809 break; 3810 case 1: 3811 printf("medium"); 3812 break; 3813 case 2: 3814 printf("slow"); 3815 break; 3816 default: 3817 printf("unknown/reserved"); /* XXX */ 3818 break; 3819 } 3820 printf(" (0x%x)\n", devsel); 3821 3822 onoff("Signalled target abort", rval, __BIT(11)); 3823 onoff("Received target abort", rval, __BIT(12)); 3824 onoff("Received master abort", rval, __BIT(13)); 3825 onoff("Received system error", rval, __BIT(14)); 3826 onoff("Detected parity error", rval, __BIT(15)); 3827 } 3828 3829 static void 3830 pci_conf_print_type0( 3831 #ifdef _KERNEL 3832 pci_chipset_tag_t pc, pcitag_t tag, 3833 #endif 3834 const pcireg_t *regs 3835 #ifdef _KERNEL 3836 , int sizebars 3837 #endif 3838 ) 3839 { 3840 int off, width; 3841 pcireg_t rval; 3842 3843 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 3844 #ifdef _KERNEL 3845 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3846 #else 3847 width = pci_conf_print_bar(regs, off, NULL); 3848 #endif 3849 } 3850 3851 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 3852 3853 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 3854 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 3855 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 3856 3857 /* XXX */ 3858 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 3859 3860 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3861 printf(" Capability list pointer: 0x%02x\n", 3862 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 3863 else 3864 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 3865 3866 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 3867 3868 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3869 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 3870 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 3871 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 3872 switch (PCI_INTERRUPT_PIN(rval)) { 3873 case PCI_INTERRUPT_PIN_NONE: 3874 printf("(none)"); 3875 break; 3876 case PCI_INTERRUPT_PIN_A: 3877 printf("(pin A)"); 3878 break; 3879 case PCI_INTERRUPT_PIN_B: 3880 printf("(pin B)"); 3881 break; 3882 case PCI_INTERRUPT_PIN_C: 3883 printf("(pin C)"); 3884 break; 3885 case PCI_INTERRUPT_PIN_D: 3886 printf("(pin D)"); 3887 break; 3888 default: 3889 printf("(? ? ?)"); 3890 break; 3891 } 3892 printf("\n"); 3893 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 3894 } 3895 3896 static void 3897 pci_conf_print_type1( 3898 #ifdef _KERNEL 3899 pci_chipset_tag_t pc, pcitag_t tag, 3900 #endif 3901 const pcireg_t *regs 3902 #ifdef _KERNEL 3903 , int sizebars 3904 #endif 3905 ) 3906 { 3907 int off, width; 3908 pcireg_t rval; 3909 uint32_t base, limit; 3910 uint32_t base_h, limit_h; 3911 uint64_t pbase, plimit; 3912 int use_upper; 3913 3914 /* 3915 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 3916 * Bridge chip documentation, and may not be correct with 3917 * respect to various standards. (XXX) 3918 */ 3919 3920 for (off = 0x10; off < 0x18; off += width) { 3921 #ifdef _KERNEL 3922 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3923 #else 3924 width = pci_conf_print_bar(regs, off, NULL); 3925 #endif 3926 } 3927 3928 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 3929 printf(" Primary bus number: 0x%02x\n", 3930 PCI_BRIDGE_BUS_PRIMARY(rval)); 3931 printf(" Secondary bus number: 0x%02x\n", 3932 PCI_BRIDGE_BUS_SECONDARY(rval)); 3933 printf(" Subordinate bus number: 0x%02x\n", 3934 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 3935 printf(" Secondary bus latency timer: 0x%02x\n", 3936 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 3937 3938 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 3939 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 3940 3941 /* I/O region */ 3942 printf(" I/O region:\n"); 3943 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 3944 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 3945 if (PCI_BRIDGE_IO_32BITS(rval)) 3946 use_upper = 1; 3947 else 3948 use_upper = 0; 3949 onoff("32bit I/O", rval, use_upper); 3950 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 3951 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 3952 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 3953 limit |= 0x00000fff; 3954 3955 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 3956 base_h = (rval >> 0) & 0xffff; 3957 limit_h = (rval >> 16) & 0xffff; 3958 printf(" base upper 16 bits register: 0x%04x\n", base_h); 3959 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 3960 3961 if (use_upper == 1) { 3962 base |= base_h << 16; 3963 limit |= limit_h << 16; 3964 } 3965 if (base < limit) { 3966 if (use_upper == 1) 3967 printf(" range: 0x%08x-0x%08x\n", base, limit); 3968 else 3969 printf(" range: 0x%04x-0x%04x\n", base, limit); 3970 } else 3971 printf(" range: not set\n"); 3972 3973 /* Non-prefetchable memory region */ 3974 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 3975 printf(" Memory region:\n"); 3976 printf(" base register: 0x%04x\n", 3977 (rval >> 0) & 0xffff); 3978 printf(" limit register: 0x%04x\n", 3979 (rval >> 16) & 0xffff); 3980 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 3981 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 3982 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 3983 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 3984 if (base < limit) 3985 printf(" range: 0x%08x-0x%08x\n", base, limit); 3986 else 3987 printf(" range: not set\n"); 3988 3989 /* Prefetchable memory region */ 3990 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 3991 printf(" Prefetchable memory region:\n"); 3992 printf(" base register: 0x%04x\n", 3993 (rval >> 0) & 0xffff); 3994 printf(" limit register: 0x%04x\n", 3995 (rval >> 16) & 0xffff); 3996 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 3997 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 3998 printf(" base upper 32 bits register: 0x%08x\n", 3999 base_h); 4000 printf(" limit upper 32 bits register: 0x%08x\n", 4001 limit_h); 4002 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 4003 use_upper = 1; 4004 else 4005 use_upper = 0; 4006 onoff("64bit memory address", rval, use_upper); 4007 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 4008 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 4009 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 4010 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 4011 if (use_upper == 1) { 4012 pbase |= (uint64_t)base_h << 32; 4013 plimit |= (uint64_t)limit_h << 32; 4014 } 4015 if (pbase < plimit) { 4016 if (use_upper == 1) 4017 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 4018 "\n", pbase, plimit); 4019 else 4020 printf(" range: 0x%08x-0x%08x\n", 4021 (uint32_t)pbase, (uint32_t)plimit); 4022 } else 4023 printf(" range: not set\n"); 4024 4025 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4026 printf(" Capability list pointer: 0x%02x\n", 4027 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4028 else 4029 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4030 4031 /* XXX */ 4032 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 4033 4034 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4035 printf(" Interrupt line: 0x%02x\n", 4036 (rval >> 0) & 0xff); 4037 printf(" Interrupt pin: 0x%02x ", 4038 (rval >> 8) & 0xff); 4039 switch ((rval >> 8) & 0xff) { 4040 case PCI_INTERRUPT_PIN_NONE: 4041 printf("(none)"); 4042 break; 4043 case PCI_INTERRUPT_PIN_A: 4044 printf("(pin A)"); 4045 break; 4046 case PCI_INTERRUPT_PIN_B: 4047 printf("(pin B)"); 4048 break; 4049 case PCI_INTERRUPT_PIN_C: 4050 printf("(pin C)"); 4051 break; 4052 case PCI_INTERRUPT_PIN_D: 4053 printf("(pin D)"); 4054 break; 4055 default: 4056 printf("(? ? ?)"); 4057 break; 4058 } 4059 printf("\n"); 4060 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 4061 & PCI_BRIDGE_CONTROL_MASK; 4062 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 4063 onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE); 4064 onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR); 4065 onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA); 4066 onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA); 4067 onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT); 4068 onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR); 4069 onoff("Fast back-to-back capable", rval,PCI_BRIDGE_CONTROL_SECFASTB2B); 4070 } 4071 4072 static void 4073 pci_conf_print_type2( 4074 #ifdef _KERNEL 4075 pci_chipset_tag_t pc, pcitag_t tag, 4076 #endif 4077 const pcireg_t *regs 4078 #ifdef _KERNEL 4079 , int sizebars 4080 #endif 4081 ) 4082 { 4083 pcireg_t rval; 4084 4085 /* 4086 * XXX these need to be printed in more detail, need to be 4087 * XXX checked against specs/docs, etc. 4088 * 4089 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 4090 * controller chip documentation, and may not be correct with 4091 * respect to various standards. (XXX) 4092 */ 4093 4094 #ifdef _KERNEL 4095 pci_conf_print_bar(pc, tag, regs, 0x10, 4096 "CardBus socket/ExCA registers", sizebars); 4097 #else 4098 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 4099 #endif 4100 4101 /* Capability list pointer and secondary status register */ 4102 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 4103 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4104 printf(" Capability list pointer: 0x%02x\n", 4105 PCI_CAPLIST_PTR(rval)); 4106 else 4107 printf(" Reserved @ 0x14: 0x%04x\n", 4108 (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0))); 4109 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 4110 4111 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4112 printf(" PCI bus number: 0x%02x\n", 4113 (rval >> 0) & 0xff); 4114 printf(" CardBus bus number: 0x%02x\n", 4115 (rval >> 8) & 0xff); 4116 printf(" Subordinate bus number: 0x%02x\n", 4117 (rval >> 16) & 0xff); 4118 printf(" CardBus latency timer: 0x%02x\n", 4119 (rval >> 24) & 0xff); 4120 4121 /* XXX Print more prettily */ 4122 printf(" CardBus memory region 0:\n"); 4123 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 4124 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 4125 printf(" CardBus memory region 1:\n"); 4126 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 4127 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 4128 printf(" CardBus I/O region 0:\n"); 4129 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 4130 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 4131 printf(" CardBus I/O region 1:\n"); 4132 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 4133 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 4134 4135 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4136 printf(" Interrupt line: 0x%02x\n", 4137 (rval >> 0) & 0xff); 4138 printf(" Interrupt pin: 0x%02x ", 4139 (rval >> 8) & 0xff); 4140 switch ((rval >> 8) & 0xff) { 4141 case PCI_INTERRUPT_PIN_NONE: 4142 printf("(none)"); 4143 break; 4144 case PCI_INTERRUPT_PIN_A: 4145 printf("(pin A)"); 4146 break; 4147 case PCI_INTERRUPT_PIN_B: 4148 printf("(pin B)"); 4149 break; 4150 case PCI_INTERRUPT_PIN_C: 4151 printf("(pin C)"); 4152 break; 4153 case PCI_INTERRUPT_PIN_D: 4154 printf("(pin D)"); 4155 break; 4156 default: 4157 printf("(? ? ?)"); 4158 break; 4159 } 4160 printf("\n"); 4161 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 4162 printf(" Bridge control register: 0x%04x\n", rval); 4163 onoff("Parity error response", rval, __BIT(0)); 4164 onoff("SERR# enable", rval, __BIT(1)); 4165 onoff("ISA enable", rval, __BIT(2)); 4166 onoff("VGA enable", rval, __BIT(3)); 4167 onoff("Master abort mode", rval, __BIT(5)); 4168 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 4169 onoff("Functional interrupts routed by ExCA registers", rval, 4170 __BIT(7)); 4171 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 4172 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 4173 onoff("Write posting enable", rval, __BIT(10)); 4174 4175 rval = regs[o2i(0x40)]; 4176 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4177 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4178 4179 #ifdef _KERNEL 4180 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 4181 sizebars); 4182 #else 4183 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 4184 #endif 4185 } 4186 4187 void 4188 pci_conf_print( 4189 #ifdef _KERNEL 4190 pci_chipset_tag_t pc, pcitag_t tag, 4191 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 4192 #else 4193 int pcifd, u_int bus, u_int dev, u_int func 4194 #endif 4195 ) 4196 { 4197 pcireg_t regs[o2i(PCI_EXTCONF_SIZE)]; 4198 int off, capoff, endoff, hdrtype; 4199 const char *type_name; 4200 #ifdef _KERNEL 4201 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, 4202 int); 4203 int sizebars; 4204 #else 4205 void (*type_printfn)(const pcireg_t *); 4206 #endif 4207 4208 printf("PCI configuration registers:\n"); 4209 4210 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 4211 #ifdef _KERNEL 4212 regs[o2i(off)] = pci_conf_read(pc, tag, off); 4213 #else 4214 if (pcibus_conf_read(pcifd, bus, dev, func, off, 4215 ®s[o2i(off)]) == -1) 4216 regs[o2i(off)] = 0; 4217 #endif 4218 } 4219 4220 #ifdef _KERNEL 4221 sizebars = 1; 4222 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 4223 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 4224 sizebars = 0; 4225 #endif 4226 4227 /* common header */ 4228 printf(" Common header:\n"); 4229 pci_conf_print_regs(regs, 0, 16); 4230 4231 printf("\n"); 4232 #ifdef _KERNEL 4233 pci_conf_print_common(pc, tag, regs); 4234 #else 4235 pci_conf_print_common(regs); 4236 #endif 4237 printf("\n"); 4238 4239 /* type-dependent header */ 4240 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 4241 switch (hdrtype) { /* XXX make a table, eventually */ 4242 case 0: 4243 /* Standard device header */ 4244 type_name = "\"normal\" device"; 4245 type_printfn = &pci_conf_print_type0; 4246 capoff = PCI_CAPLISTPTR_REG; 4247 endoff = 64; 4248 break; 4249 case 1: 4250 /* PCI-PCI bridge header */ 4251 type_name = "PCI-PCI bridge"; 4252 type_printfn = &pci_conf_print_type1; 4253 capoff = PCI_CAPLISTPTR_REG; 4254 endoff = 64; 4255 break; 4256 case 2: 4257 /* PCI-CardBus bridge header */ 4258 type_name = "PCI-CardBus bridge"; 4259 type_printfn = &pci_conf_print_type2; 4260 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 4261 endoff = 72; 4262 break; 4263 default: 4264 type_name = NULL; 4265 type_printfn = 0; 4266 capoff = -1; 4267 endoff = 64; 4268 break; 4269 } 4270 printf(" Type %d ", hdrtype); 4271 if (type_name != NULL) 4272 printf("(%s) ", type_name); 4273 printf("header:\n"); 4274 pci_conf_print_regs(regs, 16, endoff); 4275 printf("\n"); 4276 if (type_printfn) { 4277 #ifdef _KERNEL 4278 (*type_printfn)(pc, tag, regs, sizebars); 4279 #else 4280 (*type_printfn)(regs); 4281 #endif 4282 } else 4283 printf(" Don't know how to pretty-print type %d header.\n", 4284 hdrtype); 4285 printf("\n"); 4286 4287 /* capability list, if present */ 4288 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4289 && (capoff > 0)) { 4290 #ifdef _KERNEL 4291 pci_conf_print_caplist(pc, tag, regs, capoff); 4292 #else 4293 pci_conf_print_caplist(regs, capoff); 4294 #endif 4295 printf("\n"); 4296 } 4297 4298 /* device-dependent header */ 4299 printf(" Device-dependent header:\n"); 4300 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 4301 printf("\n"); 4302 #ifdef _KERNEL 4303 if (printfn) 4304 (*printfn)(pc, tag, regs); 4305 else 4306 printf(" Don't know how to pretty-print device-dependent header.\n"); 4307 printf("\n"); 4308 #endif /* _KERNEL */ 4309 4310 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 4311 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 4312 return; 4313 4314 #ifdef _KERNEL 4315 pci_conf_print_extcaplist(pc, tag, regs, capoff); 4316 #else 4317 pci_conf_print_extcaplist(regs, capoff); 4318 #endif 4319 printf("\n"); 4320 4321 /* Extended Configuration Space, if present */ 4322 printf(" Extended Configuration Space:\n"); 4323 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 4324 } 4325
Indexes created Wed Sep 24 05:09:52 GMT 2025