pci_subr.c revision 1.165
1 /* $NetBSD: pci_subr.c,v 1.165 2017/03/14 08:25:35 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.165 2017/03/14 08:25:35 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdarg.h> 58 #include <stdbool.h> 59 #include <stdio.h> 60 #include <stdlib.h> 61 #include <string.h> 62 #endif 63 64 #include <dev/pci/pcireg.h> 65 #ifdef _KERNEL 66 #include <dev/pci/pcivar.h> 67 #else 68 #include <dev/pci/pci_verbose.h> 69 #include <dev/pci/pcidevs.h> 70 #include <dev/pci/pcidevs_data.h> 71 #endif 72 73 static int pci_conf_find_cap(const pcireg_t *, int, unsigned int, int *); 74 75 /* 76 * Descriptions of known PCI classes and subclasses. 77 * 78 * Subclasses are described in the same way as classes, but have a 79 * NULL subclass pointer. 80 */ 81 struct pci_class { 82 const char *name; 83 u_int val; /* as wide as pci_{,sub}class_t */ 84 const struct pci_class *subclasses; 85 }; 86 87 /* 88 * Class 0x00. 89 * Before rev. 2.0. 90 */ 91 static const struct pci_class pci_subclass_prehistoric[] = { 92 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 93 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 94 { NULL, 0, NULL, }, 95 }; 96 97 /* 98 * Class 0x01. 99 * Mass storage controller 100 */ 101 102 /* ATA programming interface */ 103 static const struct pci_class pci_interface_ata[] = { 104 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 105 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 106 { NULL, 0, NULL, }, 107 }; 108 109 /* SATA programming interface */ 110 static const struct pci_class pci_interface_sata[] = { 111 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 112 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 113 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 114 { NULL, 0, NULL, }, 115 }; 116 117 /* Flash programming interface */ 118 static const struct pci_class pci_interface_nvm[] = { 119 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 120 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 121 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 122 { NULL, 0, NULL, }, 123 }; 124 125 /* Subclasses */ 126 static const struct pci_class pci_subclass_mass_storage[] = { 127 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 128 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 129 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 130 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 131 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 132 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 133 pci_interface_ata, }, 134 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 135 pci_interface_sata, }, 136 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 137 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 138 pci_interface_nvm, }, 139 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 140 { NULL, 0, NULL, }, 141 }; 142 143 /* 144 * Class 0x02. 145 * Network controller. 146 */ 147 static const struct pci_class pci_subclass_network[] = { 148 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 149 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 150 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 151 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 152 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 153 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 154 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 155 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 156 { NULL, 0, NULL, }, 157 }; 158 159 /* 160 * Class 0x03. 161 * Display controller. 162 */ 163 164 /* VGA programming interface */ 165 static const struct pci_class pci_interface_vga[] = { 166 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 167 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 168 { NULL, 0, NULL, }, 169 }; 170 /* Subclasses */ 171 static const struct pci_class pci_subclass_display[] = { 172 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 173 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 174 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 175 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 176 { NULL, 0, NULL, }, 177 }; 178 179 /* 180 * Class 0x04. 181 * Multimedia device. 182 */ 183 static const struct pci_class pci_subclass_multimedia[] = { 184 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 185 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 186 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 187 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 188 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 189 { NULL, 0, NULL, }, 190 }; 191 192 /* 193 * Class 0x05. 194 * Memory controller. 195 */ 196 static const struct pci_class pci_subclass_memory[] = { 197 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 198 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 199 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 200 { NULL, 0, NULL, }, 201 }; 202 203 /* 204 * Class 0x06. 205 * Bridge device. 206 */ 207 208 /* PCI bridge programming interface */ 209 static const struct pci_class pci_interface_pcibridge[] = { 210 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 211 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 212 { NULL, 0, NULL, }, 213 }; 214 215 /* Semi-transparent PCI-to-PCI bridge programming interface */ 216 static const struct pci_class pci_interface_stpci[] = { 217 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 218 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 219 { NULL, 0, NULL, }, 220 }; 221 222 /* Advanced Switching programming interface */ 223 static const struct pci_class pci_interface_advsw[] = { 224 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 225 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 226 { NULL, 0, NULL, }, 227 }; 228 229 /* Subclasses */ 230 static const struct pci_class pci_subclass_bridge[] = { 231 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 232 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 233 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 234 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 235 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 236 pci_interface_pcibridge, }, 237 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 238 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 239 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 240 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 241 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 242 pci_interface_stpci, }, 243 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 244 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 245 pci_interface_advsw, }, 246 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 247 { NULL, 0, NULL, }, 248 }; 249 250 /* 251 * Class 0x07. 252 * Simple communications controller. 253 */ 254 255 /* Serial controller programming interface */ 256 static const struct pci_class pci_interface_serial[] = { 257 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 258 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 259 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 260 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 261 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 262 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 263 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 264 { NULL, 0, NULL, }, 265 }; 266 267 /* Parallel controller programming interface */ 268 static const struct pci_class pci_interface_parallel[] = { 269 { "", PCI_INTERFACE_PARALLEL, NULL,}, 270 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 271 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 272 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 273 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 274 { NULL, 0, NULL,}, 275 }; 276 277 /* Modem programming interface */ 278 static const struct pci_class pci_interface_modem[] = { 279 { "", PCI_INTERFACE_MODEM, NULL,}, 280 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 281 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 282 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 283 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 284 { NULL, 0, NULL,}, 285 }; 286 287 /* Subclasses */ 288 static const struct pci_class pci_subclass_communications[] = { 289 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 290 pci_interface_serial, }, 291 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 292 pci_interface_parallel, }, 293 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 294 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 295 pci_interface_modem, }, 296 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 297 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 298 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 299 { NULL, 0, NULL,}, 300 }; 301 302 /* 303 * Class 0x08. 304 * Base system peripheral. 305 */ 306 307 /* PIC programming interface */ 308 static const struct pci_class pci_interface_pic[] = { 309 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 310 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 311 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 312 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 313 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 314 { NULL, 0, NULL, }, 315 }; 316 317 /* DMA programming interface */ 318 static const struct pci_class pci_interface_dma[] = { 319 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 320 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 321 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 322 { NULL, 0, NULL, }, 323 }; 324 325 /* Timer programming interface */ 326 static const struct pci_class pci_interface_tmr[] = { 327 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 328 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 329 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 330 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 331 { NULL, 0, NULL, }, 332 }; 333 334 /* RTC programming interface */ 335 static const struct pci_class pci_interface_rtc[] = { 336 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 337 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 338 { NULL, 0, NULL, }, 339 }; 340 341 /* Subclasses */ 342 static const struct pci_class pci_subclass_system[] = { 343 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 344 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 345 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 346 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 347 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 348 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 349 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 350 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 351 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 352 { NULL, 0, NULL, }, 353 }; 354 355 /* 356 * Class 0x09. 357 * Input device. 358 */ 359 360 /* Gameport programming interface */ 361 static const struct pci_class pci_interface_game[] = { 362 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 363 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 364 { NULL, 0, NULL, }, 365 }; 366 367 /* Subclasses */ 368 static const struct pci_class pci_subclass_input[] = { 369 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 370 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 371 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 372 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 373 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 374 pci_interface_game, }, 375 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 376 { NULL, 0, NULL, }, 377 }; 378 379 /* 380 * Class 0x0a. 381 * Docking station. 382 */ 383 static const struct pci_class pci_subclass_dock[] = { 384 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 385 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 386 { NULL, 0, NULL, }, 387 }; 388 389 /* 390 * Class 0x0b. 391 * Processor. 392 */ 393 static const struct pci_class pci_subclass_processor[] = { 394 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 395 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 396 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 397 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 398 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 399 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 400 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 401 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 402 { NULL, 0, NULL, }, 403 }; 404 405 /* 406 * Class 0x0c. 407 * Serial bus controller. 408 */ 409 410 /* IEEE1394 programming interface */ 411 static const struct pci_class pci_interface_ieee1394[] = { 412 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 413 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 414 { NULL, 0, NULL,}, 415 }; 416 417 /* USB programming interface */ 418 static const struct pci_class pci_interface_usb[] = { 419 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 420 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 421 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 422 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 423 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 424 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 425 { NULL, 0, NULL, }, 426 }; 427 428 /* IPMI programming interface */ 429 static const struct pci_class pci_interface_ipmi[] = { 430 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 431 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 432 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 433 { NULL, 0, NULL,}, 434 }; 435 436 /* Subclasses */ 437 static const struct pci_class pci_subclass_serialbus[] = { 438 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 439 pci_interface_ieee1394, }, 440 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 441 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 442 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 443 pci_interface_usb, }, 444 /* XXX Fiber Channel/_FIBRECHANNEL */ 445 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 446 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 447 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 448 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 449 pci_interface_ipmi, }, 450 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 451 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 452 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 453 { NULL, 0, NULL, }, 454 }; 455 456 /* 457 * Class 0x0d. 458 * Wireless Controller. 459 */ 460 static const struct pci_class pci_subclass_wireless[] = { 461 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 462 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 463 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 464 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 465 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 466 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 467 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 468 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 469 { NULL, 0, NULL, }, 470 }; 471 472 /* 473 * Class 0x0e. 474 * Intelligent IO controller. 475 */ 476 477 /* Intelligent IO programming interface */ 478 static const struct pci_class pci_interface_i2o[] = { 479 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 480 { NULL, 0, NULL,}, 481 }; 482 483 /* Subclasses */ 484 static const struct pci_class pci_subclass_i2o[] = { 485 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 486 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 487 { NULL, 0, NULL, }, 488 }; 489 490 /* 491 * Class 0x0f. 492 * Satellite communication controller. 493 */ 494 static const struct pci_class pci_subclass_satcom[] = { 495 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 496 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 497 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 498 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 499 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 500 { NULL, 0, NULL, }, 501 }; 502 503 /* 504 * Class 0x10. 505 * Encryption/Decryption controller. 506 */ 507 static const struct pci_class pci_subclass_crypto[] = { 508 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 509 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 510 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 511 { NULL, 0, NULL, }, 512 }; 513 514 /* 515 * Class 0x11. 516 * Data aquuisition and signal processing controller. 517 */ 518 static const struct pci_class pci_subclass_dasp[] = { 519 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 520 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 521 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 522 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 523 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 524 { NULL, 0, NULL, }, 525 }; 526 527 /* List of classes */ 528 static const struct pci_class pci_classes[] = { 529 { "prehistoric", PCI_CLASS_PREHISTORIC, 530 pci_subclass_prehistoric, }, 531 { "mass storage", PCI_CLASS_MASS_STORAGE, 532 pci_subclass_mass_storage, }, 533 { "network", PCI_CLASS_NETWORK, 534 pci_subclass_network, }, 535 { "display", PCI_CLASS_DISPLAY, 536 pci_subclass_display, }, 537 { "multimedia", PCI_CLASS_MULTIMEDIA, 538 pci_subclass_multimedia, }, 539 { "memory", PCI_CLASS_MEMORY, 540 pci_subclass_memory, }, 541 { "bridge", PCI_CLASS_BRIDGE, 542 pci_subclass_bridge, }, 543 { "communications", PCI_CLASS_COMMUNICATIONS, 544 pci_subclass_communications, }, 545 { "system", PCI_CLASS_SYSTEM, 546 pci_subclass_system, }, 547 { "input", PCI_CLASS_INPUT, 548 pci_subclass_input, }, 549 { "dock", PCI_CLASS_DOCK, 550 pci_subclass_dock, }, 551 { "processor", PCI_CLASS_PROCESSOR, 552 pci_subclass_processor, }, 553 { "serial bus", PCI_CLASS_SERIALBUS, 554 pci_subclass_serialbus, }, 555 { "wireless", PCI_CLASS_WIRELESS, 556 pci_subclass_wireless, }, 557 { "I2O", PCI_CLASS_I2O, 558 pci_subclass_i2o, }, 559 { "satellite comm", PCI_CLASS_SATCOM, 560 pci_subclass_satcom, }, 561 { "crypto", PCI_CLASS_CRYPTO, 562 pci_subclass_crypto, }, 563 { "DASP", PCI_CLASS_DASP, 564 pci_subclass_dasp, }, 565 { "processing accelerators", PCI_CLASS_ACCEL, 566 NULL, }, 567 { "non-essential instrumentation", PCI_CLASS_INSTRUMENT, 568 NULL, }, 569 { "undefined", PCI_CLASS_UNDEFINED, 570 NULL, }, 571 { NULL, 0, 572 NULL, }, 573 }; 574 575 DEV_VERBOSE_DEFINE(pci); 576 577 /* 578 * Append a formatted string to dest without writing more than len 579 * characters (including the trailing NUL character). dest and len 580 * are updated for use in subsequent calls to snappendf(). 581 * 582 * Returns 0 on success, a negative value if vnsprintf() fails, or 583 * a positive value if the dest buffer would have overflowed. 584 */ 585 586 static int __printflike(3,4) 587 snappendf(char **dest, size_t *len, const char * restrict fmt, ...) 588 { 589 va_list ap; 590 int count; 591 592 va_start(ap, fmt); 593 count = vsnprintf(*dest, *len, fmt, ap); 594 va_end(ap); 595 596 /* Let vsnprintf() errors bubble up to caller */ 597 if (count < 0 || *len == 0) 598 return count; 599 600 /* Handle overflow */ 601 if ((size_t)count >= *len) { 602 *dest += *len - 1; 603 *len = 1; 604 return 1; 605 } 606 607 /* Update dest & len to point at trailing NUL */ 608 *dest += count; 609 *len -= count; 610 611 return 0; 612 } 613 614 void 615 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 616 size_t l) 617 { 618 pci_class_t class; 619 pci_subclass_t subclass; 620 pci_interface_t interface; 621 pci_revision_t revision; 622 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 623 const struct pci_class *classp, *subclassp, *interfacep; 624 625 class = PCI_CLASS(class_reg); 626 subclass = PCI_SUBCLASS(class_reg); 627 interface = PCI_INTERFACE(class_reg); 628 revision = PCI_REVISION(class_reg); 629 630 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 631 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 632 PCI_PRODUCT(id_reg)); 633 634 classp = pci_classes; 635 while (classp->name != NULL) { 636 if (class == classp->val) 637 break; 638 classp++; 639 } 640 641 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 642 while (subclassp && subclassp->name != NULL) { 643 if (subclass == subclassp->val) 644 break; 645 subclassp++; 646 } 647 648 interfacep = (subclassp && subclassp->name != NULL) ? 649 subclassp->subclasses : NULL; 650 while (interfacep && interfacep->name != NULL) { 651 if (interface == interfacep->val) 652 break; 653 interfacep++; 654 } 655 656 (void)snappendf(&cp, &l, "%s %s", vendor, product); 657 if (showclass) { 658 (void)snappendf(&cp, &l, " ("); 659 if (classp->name == NULL) 660 (void)snappendf(&cp, &l, 661 "class 0x%02x, subclass 0x%02x", 662 class, subclass); 663 else { 664 if (subclassp == NULL || subclassp->name == NULL) 665 (void)snappendf(&cp, &l, 666 "%s, subclass 0x%02x", 667 classp->name, subclass); 668 else 669 (void)snappendf(&cp, &l, "%s %s", 670 subclassp->name, classp->name); 671 } 672 if ((interfacep == NULL) || (interfacep->name == NULL)) { 673 if (interface != 0) 674 (void)snappendf(&cp, &l, ", interface 0x%02x", 675 interface); 676 } else if (strncmp(interfacep->name, "", 1) != 0) 677 (void)snappendf(&cp, &l, ", %s", interfacep->name); 678 if (revision != 0) 679 (void)snappendf(&cp, &l, ", revision 0x%02x", revision); 680 (void)snappendf(&cp, &l, ")"); 681 } 682 } 683 684 #ifdef _KERNEL 685 void 686 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 687 const char *known, int addrev) 688 { 689 char devinfo[256]; 690 691 if (known) { 692 aprint_normal(": %s", known); 693 if (addrev) 694 aprint_normal(" (rev. 0x%02x)", 695 PCI_REVISION(pa->pa_class)); 696 aprint_normal("\n"); 697 } else { 698 pci_devinfo(pa->pa_id, pa->pa_class, 0, 699 devinfo, sizeof(devinfo)); 700 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 701 PCI_REVISION(pa->pa_class)); 702 } 703 if (naive) 704 aprint_naive(": %s\n", naive); 705 else 706 aprint_naive("\n"); 707 } 708 #endif 709 710 /* 711 * Print out most of the PCI configuration registers. Typically used 712 * in a device attach routine like this: 713 * 714 * #ifdef MYDEV_DEBUG 715 * printf("%s: ", device_xname(sc->sc_dev)); 716 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 717 * #endif 718 */ 719 720 #define i2o(i) ((i) * 4) 721 #define o2i(o) ((o) / 4) 722 #define onoff2(str, rval, bit, onstr, offstr) \ 723 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 724 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 725 726 static void 727 pci_conf_print_common( 728 #ifdef _KERNEL 729 pci_chipset_tag_t pc, pcitag_t tag, 730 #endif 731 const pcireg_t *regs) 732 { 733 pci_class_t class; 734 pci_subclass_t subclass; 735 pci_interface_t interface; 736 pci_revision_t revision; 737 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 738 const struct pci_class *classp, *subclassp, *interfacep; 739 const char *name; 740 pcireg_t rval; 741 unsigned int num; 742 743 rval = regs[o2i(PCI_CLASS_REG)]; 744 class = PCI_CLASS(rval); 745 subclass = PCI_SUBCLASS(rval); 746 interface = PCI_INTERFACE(rval); 747 revision = PCI_REVISION(rval); 748 749 rval = regs[o2i(PCI_ID_REG)]; 750 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 751 if (name) 752 printf(" Vendor Name: %s (0x%04x)\n", name, 753 PCI_VENDOR(rval)); 754 else 755 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 756 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 757 PCI_PRODUCT(rval)); 758 if (name) 759 printf(" Device Name: %s (0x%04x)\n", name, 760 PCI_PRODUCT(rval)); 761 else 762 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 763 764 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 765 766 printf(" Command register: 0x%04x\n", rval & 0xffff); 767 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 768 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 769 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 770 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 771 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 772 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 773 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 774 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 775 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 776 onoff("Fast back-to-back transactions", rval, 777 PCI_COMMAND_BACKTOBACK_ENABLE); 778 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 779 780 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 781 onoff("Immediate Readness", rval, PCI_STATUS_IMMD_READNESS); 782 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 783 "inactive"); 784 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 785 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 786 onoff("User Definable Features (UDF) support", rval, 787 PCI_STATUS_UDF_SUPPORT); 788 onoff("Fast back-to-back capable", rval, 789 PCI_STATUS_BACKTOBACK_SUPPORT); 790 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 791 792 printf(" DEVSEL timing: "); 793 switch (rval & PCI_STATUS_DEVSEL_MASK) { 794 case PCI_STATUS_DEVSEL_FAST: 795 printf("fast"); 796 break; 797 case PCI_STATUS_DEVSEL_MEDIUM: 798 printf("medium"); 799 break; 800 case PCI_STATUS_DEVSEL_SLOW: 801 printf("slow"); 802 break; 803 default: 804 printf("unknown/reserved"); /* XXX */ 805 break; 806 } 807 printf(" (0x%x)\n", __SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK)); 808 809 onoff("Slave signaled Target Abort", rval, 810 PCI_STATUS_TARGET_TARGET_ABORT); 811 onoff("Master received Target Abort", rval, 812 PCI_STATUS_MASTER_TARGET_ABORT); 813 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 814 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 815 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 816 817 rval = regs[o2i(PCI_CLASS_REG)]; 818 for (classp = pci_classes; classp->name != NULL; classp++) { 819 if (class == classp->val) 820 break; 821 } 822 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 823 while (subclassp && subclassp->name != NULL) { 824 if (subclass == subclassp->val) 825 break; 826 subclassp++; 827 } 828 interfacep = (subclassp && subclassp->name != NULL) ? 829 subclassp->subclasses : NULL; 830 while (interfacep && interfacep->name != NULL) { 831 if (interface == interfacep->val) 832 break; 833 interfacep++; 834 } 835 836 if (classp->name != NULL) 837 printf(" Class Name: %s (0x%02x)\n", classp->name, class); 838 else 839 printf(" Class ID: 0x%02x\n", class); 840 if (subclassp != NULL && subclassp->name != NULL) 841 printf(" Subclass Name: %s (0x%02x)\n", 842 subclassp->name, PCI_SUBCLASS(rval)); 843 else 844 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 845 if ((interfacep != NULL) && (interfacep->name != NULL) 846 && (strncmp(interfacep->name, "", 1) != 0)) 847 printf(" Interface Name: %s (0x%02x)\n", 848 interfacep->name, interface); 849 else 850 printf(" Interface: 0x%02x\n", interface); 851 printf(" Revision ID: 0x%02x\n", revision); 852 853 rval = regs[o2i(PCI_BHLC_REG)]; 854 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 855 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 856 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 857 PCI_HDRTYPE(rval)); 858 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 859 num = PCI_CACHELINE(rval); 860 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 861 } 862 863 static int 864 pci_conf_print_bar( 865 #ifdef _KERNEL 866 pci_chipset_tag_t pc, pcitag_t tag, 867 #endif 868 const pcireg_t *regs, int reg, const char *name 869 #ifdef _KERNEL 870 , int sizebar 871 #endif 872 ) 873 { 874 int width; 875 pcireg_t rval, rval64h; 876 #ifdef _KERNEL 877 int s; 878 pcireg_t mask, mask64h; 879 #endif 880 881 width = 4; 882 883 /* 884 * Section 6.2.5.1, `Address Maps', tells us that: 885 * 886 * 1) The builtin software should have already mapped the 887 * device in a reasonable way. 888 * 889 * 2) A device which wants 2^n bytes of memory will hardwire 890 * the bottom n bits of the address to 0. As recommended, 891 * we write all 1s and see what we get back. 892 */ 893 894 rval = regs[o2i(reg)]; 895 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 896 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 897 rval64h = regs[o2i(reg + 4)]; 898 width = 8; 899 } else 900 rval64h = 0; 901 902 #ifdef _KERNEL 903 /* XXX don't size unknown memory type? */ 904 if (rval != 0 && sizebar) { 905 /* 906 * The following sequence seems to make some devices 907 * (e.g. host bus bridges, which don't normally 908 * have their space mapped) very unhappy, to 909 * the point of crashing the system. 910 * 911 * Therefore, if the mapping register is zero to 912 * start out with, don't bother trying. 913 */ 914 s = splhigh(); 915 pci_conf_write(pc, tag, reg, 0xffffffff); 916 mask = pci_conf_read(pc, tag, reg); 917 pci_conf_write(pc, tag, reg, rval); 918 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 919 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 920 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 921 mask64h = pci_conf_read(pc, tag, reg + 4); 922 pci_conf_write(pc, tag, reg + 4, rval64h); 923 } else 924 mask64h = 0; 925 splx(s); 926 } else 927 mask = mask64h = 0; 928 #endif /* _KERNEL */ 929 930 printf(" Base address register at 0x%02x", reg); 931 if (name) 932 printf(" (%s)", name); 933 printf("\n "); 934 if (rval == 0) { 935 printf("not implemented(?)\n"); 936 return width; 937 } 938 printf("type: "); 939 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 940 const char *type, *prefetch; 941 942 switch (PCI_MAPREG_MEM_TYPE(rval)) { 943 case PCI_MAPREG_MEM_TYPE_32BIT: 944 type = "32-bit"; 945 break; 946 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 947 type = "32-bit-1M"; 948 break; 949 case PCI_MAPREG_MEM_TYPE_64BIT: 950 type = "64-bit"; 951 break; 952 default: 953 type = "unknown (XXX)"; 954 break; 955 } 956 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 957 prefetch = ""; 958 else 959 prefetch = "non"; 960 printf("%s %sprefetchable memory\n", type, prefetch); 961 switch (PCI_MAPREG_MEM_TYPE(rval)) { 962 case PCI_MAPREG_MEM_TYPE_64BIT: 963 printf(" base: 0x%016llx, ", 964 PCI_MAPREG_MEM64_ADDR( 965 ((((long long) rval64h) << 32) | rval))); 966 #ifdef _KERNEL 967 if (sizebar) 968 printf("size: 0x%016llx", 969 PCI_MAPREG_MEM64_SIZE( 970 ((((long long) mask64h) << 32) | mask))); 971 else 972 #endif /* _KERNEL */ 973 printf("not sized"); 974 printf("\n"); 975 break; 976 case PCI_MAPREG_MEM_TYPE_32BIT: 977 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 978 default: 979 printf(" base: 0x%08x, ", 980 PCI_MAPREG_MEM_ADDR(rval)); 981 #ifdef _KERNEL 982 if (sizebar) 983 printf("size: 0x%08x", 984 PCI_MAPREG_MEM_SIZE(mask)); 985 else 986 #endif /* _KERNEL */ 987 printf("not sized"); 988 printf("\n"); 989 break; 990 } 991 } else { 992 #ifdef _KERNEL 993 if (sizebar) 994 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 995 #endif /* _KERNEL */ 996 printf("i/o\n"); 997 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 998 #ifdef _KERNEL 999 if (sizebar) 1000 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 1001 else 1002 #endif /* _KERNEL */ 1003 printf("not sized"); 1004 printf("\n"); 1005 } 1006 1007 return width; 1008 } 1009 1010 static void 1011 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 1012 { 1013 int off, needaddr, neednl; 1014 1015 needaddr = 1; 1016 neednl = 0; 1017 for (off = first; off < pastlast; off += 4) { 1018 if ((off % 16) == 0 || needaddr) { 1019 printf(" 0x%02x:", off); 1020 needaddr = 0; 1021 } 1022 printf(" 0x%08x", regs[o2i(off)]); 1023 neednl = 1; 1024 if ((off % 16) == 12) { 1025 printf("\n"); 1026 neednl = 0; 1027 } 1028 } 1029 if (neednl) 1030 printf("\n"); 1031 } 1032 1033 static const char * 1034 pci_conf_print_agp_calcycle(uint8_t cal) 1035 { 1036 1037 switch (cal) { 1038 case 0x0: 1039 return "4ms"; 1040 case 0x1: 1041 return "16ms"; 1042 case 0x2: 1043 return "64ms"; 1044 case 0x3: 1045 return "256ms"; 1046 case 0x7: 1047 return "Calibration Cycle Not Needed"; 1048 default: 1049 return "(reserved)"; 1050 } 1051 } 1052 1053 static void 1054 pci_conf_print_agp_datarate(pcireg_t reg, bool isagp3) 1055 { 1056 if (isagp3) { 1057 /* AGP 3.0 */ 1058 if (reg & AGP_MODE_V3_RATE_4x) 1059 printf("x4"); 1060 if (reg & AGP_MODE_V3_RATE_8x) 1061 printf("x8"); 1062 } else { 1063 /* AGP 2.0 */ 1064 if (reg & AGP_MODE_V2_RATE_1x) 1065 printf("x1"); 1066 if (reg & AGP_MODE_V2_RATE_2x) 1067 printf("x2"); 1068 if (reg & AGP_MODE_V2_RATE_4x) 1069 printf("x4"); 1070 } 1071 printf("\n"); 1072 } 1073 1074 static void 1075 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1076 { 1077 pcireg_t rval; 1078 bool isagp3; 1079 1080 printf("\n AGP Capabilities Register\n"); 1081 1082 rval = regs[o2i(capoff)]; 1083 printf(" Revision: %d.%d\n", 1084 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1085 1086 rval = regs[o2i(capoff + PCI_AGP_STATUS)]; 1087 printf(" Status register: 0x%04x\n", rval); 1088 printf(" RQ: %d\n", 1089 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1090 printf(" ARQSZ: %d\n", 1091 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1092 printf(" CAL cycle: %s\n", 1093 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1094 onoff("SBA", rval, AGP_MODE_SBA); 1095 onoff("htrans#", rval, AGP_MODE_HTRANS); 1096 onoff("Over 4G", rval, AGP_MODE_4G); 1097 onoff("Fast Write", rval, AGP_MODE_FW); 1098 onoff("AGP 3.0 Mode", rval, AGP_MODE_MODE_3); 1099 isagp3 = rval & AGP_MODE_MODE_3; 1100 printf(" Data Rate Support: "); 1101 pci_conf_print_agp_datarate(rval, isagp3); 1102 1103 rval = regs[o2i(capoff + PCI_AGP_COMMAND)]; 1104 printf(" Command register: 0x%08x\n", rval); 1105 printf(" PRQ: %d\n", 1106 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1107 printf(" PARQSZ: %d\n", 1108 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1109 printf(" PCAL cycle: %s\n", 1110 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1111 onoff("SBA", rval, AGP_MODE_SBA); 1112 onoff("AGP", rval, AGP_MODE_AGP); 1113 onoff("Over 4G", rval, AGP_MODE_4G); 1114 onoff("Fast Write", rval, AGP_MODE_FW); 1115 if (isagp3) { 1116 printf(" Data Rate Enable: "); 1117 /* 1118 * The Data Rate Enable bits are used only on 3.0 and the 1119 * Command register has no AGP_MODE_MODE_3 bit, so pass the 1120 * flag to print correctly. 1121 */ 1122 pci_conf_print_agp_datarate(rval, isagp3); 1123 } 1124 } 1125 1126 static const char * 1127 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1128 { 1129 1130 switch ((caps >> 6) & 7) { 1131 case 0: return "self-powered"; 1132 case 1: return "55 mA"; 1133 case 2: return "100 mA"; 1134 case 3: return "160 mA"; 1135 case 4: return "220 mA"; 1136 case 5: return "270 mA"; 1137 case 6: return "320 mA"; 1138 case 7: 1139 default: return "375 mA"; 1140 } 1141 } 1142 1143 static const char * 1144 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1145 { 1146 static const char unk[] = "unknown"; 1147 static const char *pmrev[8] = { 1148 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1149 }; 1150 if (val > 7) 1151 return unk; 1152 return pmrev[val]; 1153 } 1154 1155 static void 1156 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1157 { 1158 uint16_t caps, pmcsr; 1159 pcireg_t reg; 1160 1161 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1162 reg = regs[o2i(capoff + PCI_PMCSR)]; 1163 pmcsr = reg & 0xffff; 1164 1165 printf("\n PCI Power Management Capabilities Register\n"); 1166 1167 printf(" Capabilities register: 0x%04x\n", caps); 1168 printf(" Version: %s\n", 1169 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1170 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1171 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1172 printf(" 3.3V auxiliary current: %s\n", 1173 pci_conf_print_pcipm_cap_aux(caps)); 1174 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1175 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1176 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1177 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1178 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1179 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1180 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1181 1182 printf(" Control/status register: 0x%04x\n", pmcsr); 1183 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1184 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1185 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1186 printf(" PME# assertion: %sabled\n", 1187 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1188 printf(" Data Select: %d\n", 1189 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK)); 1190 printf(" Data Scale: %d\n", 1191 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK)); 1192 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1193 printf(" Bridge Support Extensions register: 0x%02x\n", 1194 (reg >> 16) & 0xff); 1195 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1196 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1197 printf(" Data register: 0x%02x\n", __SHIFTOUT(reg, PCI_PMCSR_DATA)); 1198 1199 } 1200 1201 /* XXX pci_conf_print_vpd_cap */ 1202 /* XXX pci_conf_print_slotid_cap */ 1203 1204 static void 1205 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1206 { 1207 uint32_t ctl, mmc, mme; 1208 1209 regs += o2i(capoff); 1210 ctl = *regs++; 1211 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1212 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1213 1214 printf("\n PCI Message Signaled Interrupt\n"); 1215 1216 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1217 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1218 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1219 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1220 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1221 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1222 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1223 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1224 onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP); 1225 onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN); 1226 printf(" Message Address %sregister: 0x%08x\n", 1227 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1228 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1229 printf(" Message Address %sregister: 0x%08x\n", 1230 "(upper) ", *regs++); 1231 } 1232 printf(" Message Data register: 0x%04x\n", *regs & 0xffff); 1233 regs++; 1234 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1235 printf(" Vector Mask register: 0x%08x\n", *regs++); 1236 printf(" Vector Pending register: 0x%08x\n", *regs++); 1237 } 1238 } 1239 1240 /* XXX pci_conf_print_cpci_hostwap_cap */ 1241 1242 /* 1243 * For both command register and status register. 1244 * The argument "idx" is index number (0 to 7). 1245 */ 1246 static int 1247 pcix_split_trans(unsigned int idx) 1248 { 1249 static int table[8] = { 1250 1, 2, 3, 4, 8, 12, 16, 32 1251 }; 1252 1253 if (idx >= __arraycount(table)) 1254 return -1; 1255 return table[idx]; 1256 } 1257 1258 static void 1259 pci_conf_print_pcix_cap_2ndbusmode(int num) 1260 { 1261 const char *maxfreq, *maxperiod; 1262 1263 printf(" Mode: "); 1264 if (num <= 0x07) 1265 printf("PCI-X Mode 1\n"); 1266 else if (num <= 0x0b) 1267 printf("PCI-X 266 (Mode 2)\n"); 1268 else 1269 printf("PCI-X 533 (Mode 2)\n"); 1270 1271 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1272 switch (num & 0x03) { 1273 default: 1274 case 0: 1275 maxfreq = "N/A"; 1276 maxperiod = "N/A"; 1277 break; 1278 case 1: 1279 maxfreq = "66MHz"; 1280 maxperiod = "15ns"; 1281 break; 1282 case 2: 1283 maxfreq = "100MHz"; 1284 maxperiod = "10ns"; 1285 break; 1286 case 3: 1287 maxfreq = "133MHz"; 1288 maxperiod = "7.5ns"; 1289 break; 1290 } 1291 printf(" Max Clock Freq: %s\n", maxfreq); 1292 printf(" Min Clock Period: %s\n", maxperiod); 1293 } 1294 1295 static void 1296 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1297 { 1298 pcireg_t reg; 1299 int isbridge; 1300 int i; 1301 1302 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1303 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1304 printf("\n PCI-X %s Capabilities Register\n", 1305 isbridge ? "Bridge" : "Non-bridge"); 1306 1307 reg = regs[o2i(capoff)]; 1308 if (isbridge != 0) { 1309 printf(" Secondary status register: 0x%04x\n", 1310 (reg & 0xffff0000) >> 16); 1311 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1312 onoff("133MHz capable", reg, PCIX_STATUS_133); 1313 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1314 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1315 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1316 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1317 pci_conf_print_pcix_cap_2ndbusmode( 1318 __SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1319 printf(" Version: 0x%x\n", 1320 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1321 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1322 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1323 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1324 } else { 1325 printf(" Command register: 0x%04x\n", 1326 (reg & 0xffff0000) >> 16); 1327 onoff("Data Parity Error Recovery", reg, 1328 PCIX_CMD_PERR_RECOVER); 1329 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1330 printf(" Maximum Burst Read Count: %u\n", 1331 PCIX_CMD_BYTECNT(reg)); 1332 printf(" Maximum Split Transactions: %d\n", 1333 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1334 >> PCIX_CMD_SPLTRANS_SHIFT)); 1335 } 1336 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1337 printf(" %sStatus register: 0x%08x\n", 1338 isbridge ? "Bridge " : "", reg); 1339 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1340 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1341 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1342 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1343 onoff("133MHz capable", reg, PCIX_STATUS_133); 1344 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1345 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1346 if (isbridge != 0) { 1347 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1348 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1349 } else { 1350 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1351 "bridge device", "simple device"); 1352 printf(" Designed max memory read byte count: %d\n", 1353 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1354 >> PCIX_STATUS_MAXB_SHIFT)); 1355 printf(" Designed max outstanding split transaction: %d\n", 1356 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1357 >> PCIX_STATUS_MAXST_SHIFT)); 1358 printf(" MAX cumulative Read Size: %u\n", 1359 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1360 onoff("Received split completion error", reg, 1361 PCIX_STATUS_SCERR); 1362 } 1363 onoff("266MHz capable", reg, PCIX_STATUS_266); 1364 onoff("533MHz capable", reg, PCIX_STATUS_533); 1365 1366 if (isbridge == 0) 1367 return; 1368 1369 /* Only for bridge */ 1370 for (i = 0; i < 2; i++) { 1371 reg = regs[o2i(capoff + PCIX_BRIDGE_UP_STCR + (4 * i))]; 1372 printf(" %s split transaction control register: 0x%08x\n", 1373 (i == 0) ? "Upstream" : "Downstream", reg); 1374 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1375 printf(" Commitment Limit: %d\n", 1376 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1377 } 1378 } 1379 1380 /* pci_conf_print_ht_slave_cap */ 1381 /* pci_conf_print_ht_host_cap */ 1382 /* pci_conf_print_ht_switch_cap */ 1383 /* pci_conf_print_ht_intr_cap */ 1384 /* pci_conf_print_ht_revid_cap */ 1385 /* pci_conf_print_ht_unitid_cap */ 1386 /* pci_conf_print_ht_extcnf_cap */ 1387 /* pci_conf_print_ht_addrmap_cap */ 1388 /* pci_conf_print_ht_msimap_cap */ 1389 1390 static void 1391 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1392 { 1393 pcireg_t val; 1394 uint32_t lo, hi; 1395 1396 /* 1397 * Print the rest of the command register bits. Others are 1398 * printed in pci_conf_print_ht_cap(). 1399 */ 1400 val = regs[o2i(capoff + PCI_HT_CMD)]; 1401 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1402 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1403 1404 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1405 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1406 printf(" Address Low register: 0x%08x\n", lo); 1407 printf(" Address high register: 0x%08x\n", hi); 1408 printf(" Address: 0x%016" PRIx64 "\n", 1409 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1410 } 1411 1412 /* pci_conf_print_ht_droute_cap */ 1413 /* pci_conf_print_ht_vcset_cap */ 1414 /* pci_conf_print_ht_retry_cap */ 1415 /* pci_conf_print_ht_x86enc_cap */ 1416 /* pci_conf_print_ht_gen3_cap */ 1417 /* pci_conf_print_ht_fle_cap */ 1418 /* pci_conf_print_ht_pm_cap */ 1419 /* pci_conf_print_ht_hnc_cap */ 1420 1421 static const struct ht_types { 1422 pcireg_t cap; 1423 const char *name; 1424 void (*printfunc)(const pcireg_t *, int); 1425 } ht_captab[] = { 1426 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1427 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1428 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1429 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1430 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1431 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1432 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1433 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1434 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1435 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1436 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1437 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1438 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1439 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1440 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1441 {PCI_HT_CAP_PM, "Power Management", NULL }, 1442 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1443 }; 1444 1445 static void 1446 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1447 { 1448 pcireg_t val, foundcap; 1449 unsigned int off; 1450 1451 val = regs[o2i(capoff + PCI_HT_CMD)]; 1452 1453 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1454 1455 printf(" Command register: 0x%04x\n", val >> 16); 1456 foundcap = PCI_HT_CAP(val); 1457 for (off = 0; off < __arraycount(ht_captab); off++) { 1458 if (ht_captab[off].cap == foundcap) 1459 break; 1460 } 1461 printf(" Capability Type: 0x%02x ", foundcap); 1462 if (off >= __arraycount(ht_captab)) { 1463 printf("(unknown)\n"); 1464 return; 1465 } 1466 printf("(%s)\n", ht_captab[off].name); 1467 if (ht_captab[off].printfunc != NULL) 1468 ht_captab[off].printfunc(regs, capoff); 1469 } 1470 1471 static void 1472 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1473 { 1474 uint16_t caps; 1475 1476 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1477 1478 printf("\n PCI Vendor Specific Capabilities Register\n"); 1479 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1480 } 1481 1482 static void 1483 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1484 { 1485 pcireg_t val; 1486 1487 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1488 1489 printf("\n Debugport Capability Register\n"); 1490 printf(" Debug base Register: 0x%04x\n", 1491 val >> PCI_DEBUG_BASER_SHIFT); 1492 printf(" port offset: 0x%04x\n", 1493 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1494 printf(" BAR number: %u\n", 1495 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1496 } 1497 1498 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1499 /* XXX pci_conf_print_hotplug_cap */ 1500 1501 static void 1502 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1503 { 1504 pcireg_t reg; 1505 1506 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1507 1508 printf("\n Subsystem ID Capability Register\n"); 1509 printf(" Subsystem ID : 0x%08x\n", reg); 1510 } 1511 1512 /* XXX pci_conf_print_agp8_cap */ 1513 /* XXX pci_conf_print_secure_cap */ 1514 1515 static void 1516 pci_print_pcie_L0s_latency(uint32_t val) 1517 { 1518 1519 switch (val) { 1520 case 0x0: 1521 printf("Less than 64ns\n"); 1522 break; 1523 case 0x1: 1524 case 0x2: 1525 case 0x3: 1526 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1527 break; 1528 case 0x4: 1529 printf("512ns to less than 1us\n"); 1530 break; 1531 case 0x5: 1532 printf("1us to less than 2us\n"); 1533 break; 1534 case 0x6: 1535 printf("2us - 4us\n"); 1536 break; 1537 case 0x7: 1538 printf("More than 4us\n"); 1539 break; 1540 } 1541 } 1542 1543 static void 1544 pci_print_pcie_L1_latency(uint32_t val) 1545 { 1546 1547 switch (val) { 1548 case 0x0: 1549 printf("Less than 1us\n"); 1550 break; 1551 case 0x6: 1552 printf("32us - 64us\n"); 1553 break; 1554 case 0x7: 1555 printf("More than 64us\n"); 1556 break; 1557 default: 1558 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1559 break; 1560 } 1561 } 1562 1563 static void 1564 pci_print_pcie_compl_timeout(uint32_t val) 1565 { 1566 1567 switch (val) { 1568 case 0x0: 1569 printf("50us to 50ms\n"); 1570 break; 1571 case 0x5: 1572 printf("16ms to 55ms\n"); 1573 break; 1574 case 0x6: 1575 printf("65ms to 210ms\n"); 1576 break; 1577 case 0x9: 1578 printf("260ms to 900ms\n"); 1579 break; 1580 case 0xa: 1581 printf("1s to 3.5s\n"); 1582 break; 1583 default: 1584 printf("unknown %u value\n", val); 1585 break; 1586 } 1587 } 1588 1589 static const char * const pcie_linkspeeds[] = {"2.5", "2.5", "5.0", "8.0"}; 1590 1591 static void 1592 pci_print_pcie_linkspeed(pcireg_t val) 1593 { 1594 1595 if (val > __arraycount(pcie_linkspeeds)) 1596 printf("unknown value (%u)\n", val); 1597 else 1598 printf("%sGT/s\n", pcie_linkspeeds[val]); 1599 } 1600 1601 static void 1602 pci_print_pcie_linkspeedvector(pcireg_t val) 1603 { 1604 unsigned int i; 1605 1606 /* Start from 0 */ 1607 for (i = 0; i < 16; i++) 1608 if (((val >> i) & 0x01) != 0) { 1609 if (i >= __arraycount(pcie_linkspeeds)) 1610 printf(" unknown vector (0x%x)", 1 << i); 1611 else 1612 printf(" %sGT/s", pcie_linkspeeds[i]); 1613 } 1614 } 1615 1616 static void 1617 pci_print_pcie_link_deemphasis(pcireg_t val) 1618 { 1619 switch (val) { 1620 case 0: 1621 printf("-6dB"); 1622 break; 1623 case 1: 1624 printf("-3.5dB"); 1625 break; 1626 default: 1627 printf("(reserved value)"); 1628 } 1629 } 1630 1631 static void 1632 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1633 { 1634 pcireg_t reg; /* for each register */ 1635 pcireg_t val; /* for each bitfield */ 1636 bool check_link = false; 1637 bool check_slot = false; 1638 bool check_rootport = false; 1639 unsigned int pciever; 1640 unsigned int i; 1641 1642 printf("\n PCI Express Capabilities Register\n"); 1643 /* Capability Register */ 1644 reg = regs[o2i(capoff)]; 1645 printf(" Capability register: 0x%04x\n", reg >> 16); 1646 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1647 printf(" Capability version: %u\n", pciever); 1648 printf(" Device type: "); 1649 switch ((reg & 0x00f00000) >> 20) { 1650 case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */ 1651 printf("PCI Express Endpoint device\n"); 1652 check_link = true; 1653 break; 1654 case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */ 1655 printf("Legacy PCI Express Endpoint device\n"); 1656 check_link = true; 1657 break; 1658 case PCIE_XCAP_TYPE_ROOT: /* 0x4 */ 1659 printf("Root Port of PCI Express Root Complex\n"); 1660 check_link = true; 1661 check_slot = true; 1662 check_rootport = true; 1663 break; 1664 case PCIE_XCAP_TYPE_UP: /* 0x5 */ 1665 printf("Upstream Port of PCI Express Switch\n"); 1666 break; 1667 case PCIE_XCAP_TYPE_DOWN: /* 0x6 */ 1668 printf("Downstream Port of PCI Express Switch\n"); 1669 check_slot = true; 1670 check_rootport = true; 1671 break; 1672 case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */ 1673 printf("PCI Express to PCI/PCI-X Bridge\n"); 1674 break; 1675 case PCIE_XCAP_TYPE_PCI2PCIE: /* 0x8 */ 1676 printf("PCI/PCI-X to PCI Express Bridge\n"); 1677 break; 1678 case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */ 1679 printf("Root Complex Integrated Endpoint\n"); 1680 break; 1681 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */ 1682 check_rootport = true; 1683 printf("Root Complex Event Collector\n"); 1684 break; 1685 default: 1686 printf("unknown\n"); 1687 break; 1688 } 1689 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1690 printf(" Interrupt Message Number: 0x%02x\n", 1691 (unsigned int)__SHIFTOUT(reg, PCIE_XCAP_IRQ)); 1692 1693 /* Device Capability Register */ 1694 reg = regs[o2i(capoff + PCIE_DCAP)]; 1695 printf(" Device Capabilities Register: 0x%08x\n", reg); 1696 printf(" Max Payload Size Supported: %u bytes max\n", 1697 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1698 printf(" Phantom Functions Supported: "); 1699 switch (__SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) { 1700 case 0x0: 1701 printf("not available\n"); 1702 break; 1703 case 0x1: 1704 printf("MSB\n"); 1705 break; 1706 case 0x2: 1707 printf("two MSB\n"); 1708 break; 1709 case 0x3: 1710 printf("All three bits\n"); 1711 break; 1712 } 1713 printf(" Extended Tag Field Supported: %dbit\n", 1714 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1715 printf(" Endpoint L0 Acceptable Latency: "); 1716 pci_print_pcie_L0s_latency(__SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY)); 1717 printf(" Endpoint L1 Acceptable Latency: "); 1718 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY)); 1719 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1720 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1721 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1722 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1723 printf(" Captured Slot Power Limit Value: %u\n", 1724 (unsigned int)__SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL)); 1725 printf(" Captured Slot Power Limit Scale: %u\n", 1726 (unsigned int)__SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE)); 1727 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1728 1729 /* Device Control Register */ 1730 reg = regs[o2i(capoff + PCIE_DCSR)]; 1731 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1732 onoff("Correctable Error Reporting Enable", reg, 1733 PCIE_DCSR_ENA_COR_ERR); 1734 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1735 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1736 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1737 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1738 printf(" Max Payload Size: %d byte\n", 1739 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD)); 1740 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1741 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1742 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1743 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1744 printf(" Max Read Request Size: %d byte\n", 1745 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ)); 1746 1747 /* Device Status Register */ 1748 reg = regs[o2i(capoff + PCIE_DCSR)]; 1749 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1750 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1751 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1752 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1753 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1754 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1755 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1756 onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD); 1757 1758 if (check_link) { 1759 /* Link Capability Register */ 1760 reg = regs[o2i(capoff + PCIE_LCAP)]; 1761 printf(" Link Capabilities Register: 0x%08x\n", reg); 1762 printf(" Maximum Link Speed: "); 1763 pci_print_pcie_linkspeed(reg & PCIE_LCAP_MAX_SPEED); 1764 printf(" Maximum Link Width: x%u lanes\n", 1765 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH)); 1766 printf(" Active State PM Support: "); 1767 switch (__SHIFTOUT(reg, PCIE_LCAP_ASPM)) { 1768 case 0x0: 1769 printf("No ASPM support\n"); 1770 break; 1771 case 0x1: 1772 printf("L0s supported\n"); 1773 break; 1774 case 0x2: 1775 printf("L1 supported\n"); 1776 break; 1777 case 0x3: 1778 printf("L0s and L1 supported\n"); 1779 break; 1780 } 1781 printf(" L0 Exit Latency: "); 1782 pci_print_pcie_L0s_latency(__SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT)); 1783 printf(" L1 Exit Latency: "); 1784 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_LCAP_L1_EXIT)); 1785 printf(" Port Number: %u\n", 1786 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_PORT)); 1787 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1788 onoff("Surprise Down Error Report", reg, 1789 PCIE_LCAP_SURPRISE_DOWN); 1790 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1791 onoff("Link BW Notification Capable", reg, 1792 PCIE_LCAP_LINK_BW_NOTIFY); 1793 onoff("ASPM Optionally Compliance", reg, 1794 PCIE_LCAP_ASPM_COMPLIANCE); 1795 1796 /* Link Control Register */ 1797 reg = regs[o2i(capoff + PCIE_LCSR)]; 1798 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1799 printf(" Active State PM Control: "); 1800 switch (reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S)) { 1801 case 0: 1802 printf("disabled\n"); 1803 break; 1804 case 1: 1805 printf("L0s Entry Enabled\n"); 1806 break; 1807 case 2: 1808 printf("L1 Entry Enabled\n"); 1809 break; 1810 case 3: 1811 printf("L0s and L1 Entry Enabled\n"); 1812 break; 1813 } 1814 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1815 "128bytes", "64bytes"); 1816 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1817 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1818 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1819 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1820 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1821 onoff("Hardware Autonomous Width Disable", reg,PCIE_LCSR_HAWD); 1822 onoff("Link Bandwidth Management Interrupt Enable", reg, 1823 PCIE_LCSR_LBMIE); 1824 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1825 PCIE_LCSR_LABIE); 1826 printf(" DRS Signaling Control: "); 1827 switch (__SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) { 1828 case 0: 1829 printf("not reported\n"); 1830 break; 1831 case 1: 1832 printf("Interrupt Enabled\n"); 1833 break; 1834 case 2: 1835 printf("DRS to FRS Signaling Enabled\n"); 1836 break; 1837 default: 1838 printf("reserved\n"); 1839 break; 1840 } 1841 1842 /* Link Status Register */ 1843 reg = regs[o2i(capoff + PCIE_LCSR)]; 1844 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1845 printf(" Negotiated Link Speed: "); 1846 pci_print_pcie_linkspeed(__SHIFTOUT(reg, PCIE_LCSR_LINKSPEED)); 1847 printf(" Negotiated Link Width: x%u lanes\n", 1848 (unsigned int)__SHIFTOUT(reg, PCIE_LCSR_NLW)); 1849 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1850 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1851 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1852 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1853 onoff("Link Bandwidth Management Status", reg, 1854 PCIE_LCSR_LINK_BW_MGMT); 1855 onoff("Link Autonomous Bandwidth Status", reg, 1856 PCIE_LCSR_LINK_AUTO_BW); 1857 } 1858 1859 if (check_slot == true) { 1860 /* Slot Capability Register */ 1861 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1862 printf(" Slot Capability Register: 0x%08x\n", reg); 1863 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1864 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1865 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1866 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1867 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1868 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1869 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1870 printf(" Slot Power Limit Value: %d\n", 1871 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1872 printf(" Slot Power Limit Scale: %d\n", 1873 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1874 onoff("Electromechanical Interlock Present", reg, 1875 PCIE_SLCAP_EIP); 1876 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1877 printf(" Physical Slot Number: %d\n", 1878 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1879 1880 /* Slot Control Register */ 1881 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1882 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1883 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1884 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1885 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1886 onoff("Presense Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1887 onoff("Command Completed Interrupt Enabled", reg, 1888 PCIE_SLCSR_CCE); 1889 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1890 printf(" Attention Indicator Control: "); 1891 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1892 case 0x0: 1893 printf("reserved\n"); 1894 break; 1895 case 0x1: 1896 printf("on\n"); 1897 break; 1898 case 0x2: 1899 printf("blink\n"); 1900 break; 1901 case 0x3: 1902 printf("off\n"); 1903 break; 1904 } 1905 printf(" Power Indicator Control: "); 1906 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1907 case 0x0: 1908 printf("reserved\n"); 1909 break; 1910 case 0x1: 1911 printf("on\n"); 1912 break; 1913 case 0x2: 1914 printf("blink\n"); 1915 break; 1916 case 0x3: 1917 printf("off\n"); 1918 break; 1919 } 1920 printf(" Power Controller Control: Power %s\n", 1921 reg & PCIE_SLCSR_PCC ? "off" : "on"); 1922 onoff("Electromechanical Interlock Control", 1923 reg, PCIE_SLCSR_EIC); 1924 onoff("Data Link Layer State Changed Enable", reg, 1925 PCIE_SLCSR_DLLSCE); 1926 onoff("Auto Slot Power Limit Disable", reg, 1927 PCIE_SLCSR_AUTOSPLDIS); 1928 1929 /* Slot Status Register */ 1930 printf(" Slot Status Register: 0x%04x\n", reg >> 16); 1931 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1932 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1933 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1934 onoff("Presense Detect Changed", reg, PCIE_SLCSR_PDC); 1935 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1936 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1937 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1938 onoff("Electromechanical Interlock engaged", reg, 1939 PCIE_SLCSR_EIS); 1940 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 1941 } 1942 1943 if (check_rootport == true) { 1944 /* Root Control Register */ 1945 reg = regs[o2i(capoff + PCIE_RCR)]; 1946 printf(" Root Control Register: %04x\n", reg & 0xffff); 1947 onoff("SERR on Correctable Error Enable", reg, 1948 PCIE_RCR_SERR_CER); 1949 onoff("SERR on Non-Fatal Error Enable", reg, 1950 PCIE_RCR_SERR_NFER); 1951 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 1952 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 1953 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 1954 1955 /* Root Capability Register */ 1956 printf(" Root Capability Register: 0x%04x\n", 1957 reg >> 16); 1958 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 1959 1960 /* Root Status Register */ 1961 reg = regs[o2i(capoff + PCIE_RSR)]; 1962 printf(" Root Status Register: 0x%08x\n", reg); 1963 printf(" PME Requester ID: 0x%04x\n", 1964 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1965 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 1966 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 1967 } 1968 1969 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1970 if (pciever < 2) 1971 return; 1972 1973 /* Device Capabilities 2 */ 1974 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1975 printf(" Device Capabilities 2: 0x%08x\n", reg); 1976 printf(" Completion Timeout Ranges Supported: "); 1977 val = reg & PCIE_DCAP2_COMPT_RANGE; 1978 switch (val) { 1979 case 0: 1980 printf("not supported\n"); 1981 break; 1982 default: 1983 for (i = 0; i <= 3; i++) { 1984 if (((val >> i) & 0x01) != 0) 1985 printf("%c", 'A' + i); 1986 } 1987 printf("\n"); 1988 } 1989 onoff("Completion Timeout Disable Supported", reg, 1990 PCIE_DCAP2_COMPT_DIS); 1991 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 1992 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 1993 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 1994 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 1995 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 1996 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 1997 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 1998 printf(" TPH Completer Supported: "); 1999 switch (__SHIFTOUT(reg, PCIE_DCAP2_TPH_COMP)) { 2000 case 0: 2001 printf("Not supportted\n"); 2002 break; 2003 case 1: 2004 printf("TPH\n"); 2005 break; 2006 case 3: 2007 printf("TPH and Extended TPH\n"); 2008 break; 2009 default: 2010 printf("(reserved value)\n"); 2011 break; 2012 2013 } 2014 printf(" LN System CLS: "); 2015 switch (__SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 2016 case 0x0: 2017 printf("Not supported or not in effect\n"); 2018 break; 2019 case 0x1: 2020 printf("64byte cachelines in effect\n"); 2021 break; 2022 case 0x2: 2023 printf("128byte cachelines in effect\n"); 2024 break; 2025 case 0x3: 2026 printf("Reserved\n"); 2027 break; 2028 } 2029 printf(" OBFF Supported: "); 2030 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 2031 case 0x0: 2032 printf("Not supported\n"); 2033 break; 2034 case 0x1: 2035 printf("Message only\n"); 2036 break; 2037 case 0x2: 2038 printf("WAKE# only\n"); 2039 break; 2040 case 0x3: 2041 printf("Both\n"); 2042 break; 2043 } 2044 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 2045 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 2046 val = __SHIFTOUT(reg, PCIE_DCAP2_MAX_EETLP); 2047 printf(" Max End-End TLP Prefixes: %u\n", (val == 0) ? 4 : val); 2048 printf(" Emergency Power Reduction Supported: "); 2049 switch (__SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) { 2050 case 0x0: 2051 printf("Not supported\n"); 2052 break; 2053 case 0x1: 2054 printf("Device Specific mechanism\n"); 2055 break; 2056 case 0x2: 2057 printf("Form Factor spec or Device Specific mechanism\n"); 2058 break; 2059 case 0x3: 2060 printf("Reserved\n"); 2061 break; 2062 } 2063 onoff("Emergency Power Reduction Initialization Required", reg, 2064 PCIE_DCAP2_EMGPWRRED_INI); 2065 onoff("FRS Supported", reg, PCIE_DCAP2_FRS); 2066 2067 /* Device Control 2 */ 2068 reg = regs[o2i(capoff + PCIE_DCSR2)]; 2069 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 2070 printf(" Completion Timeout Value: "); 2071 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 2072 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 2073 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 2074 onoff("AtomicOp Rquester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 2075 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 2076 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 2077 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 2078 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 2079 onoff("Emergency Power Reduction Request", reg, 2080 PCIE_DCSR2_EMGPWRRED_REQ); 2081 printf(" OBFF: "); 2082 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 2083 case 0x0: 2084 printf("Disabled\n"); 2085 break; 2086 case 0x1: 2087 printf("Enabled with Message Signaling Variation A\n"); 2088 break; 2089 case 0x2: 2090 printf("Enabled with Message Signaling Variation B\n"); 2091 break; 2092 case 0x3: 2093 printf("Enabled using WAKE# signaling\n"); 2094 break; 2095 } 2096 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 2097 2098 if (check_link) { 2099 bool drs_supported = false; 2100 2101 /* Link Capability 2 */ 2102 reg = regs[o2i(capoff + PCIE_LCAP2)]; 2103 /* If the vector is 0, LCAP2 is not implemented */ 2104 if ((reg & PCIE_LCAP2_SUP_LNKSV) != 0) { 2105 printf(" Link Capabilities 2: 0x%08x\n", reg); 2106 printf(" Supported Link Speeds Vector:"); 2107 pci_print_pcie_linkspeedvector( 2108 __SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV)); 2109 printf("\n"); 2110 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 2111 printf(" " 2112 "Lower SKP OS Generation Supported Speed Vector:"); 2113 pci_print_pcie_linkspeedvector( 2114 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV)); 2115 printf("\n"); 2116 printf(" " 2117 "Lower SKP OS Reception Supported Speed Vector:"); 2118 pci_print_pcie_linkspeedvector( 2119 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV)); 2120 printf("\n"); 2121 onoff("DRS Supported", reg, PCIE_LCAP2_DRS); 2122 drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false; 2123 } 2124 2125 /* Link Control 2 */ 2126 reg = regs[o2i(capoff + PCIE_LCSR2)]; 2127 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 2128 printf(" Target Link Speed: "); 2129 pci_print_pcie_linkspeed(__SHIFTOUT(reg, 2130 PCIE_LCSR2_TGT_LSPEED)); 2131 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 2132 onoff("HW Autonomous Speed Disabled", reg, 2133 PCIE_LCSR2_HW_AS_DIS); 2134 printf(" Selectable De-emphasis: "); 2135 pci_print_pcie_link_deemphasis( 2136 __SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP)); 2137 printf("\n"); 2138 printf(" Transmit Margin: %u\n", 2139 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 2140 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 2141 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 2142 printf(" Compliance Present/De-emphasis: "); 2143 pci_print_pcie_link_deemphasis( 2144 __SHIFTOUT(reg, PCIE_LCSR2_COMP_DEEMP)); 2145 printf("\n"); 2146 2147 /* Link Status 2 */ 2148 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 2149 printf(" Current De-emphasis Level: "); 2150 pci_print_pcie_link_deemphasis( 2151 __SHIFTOUT(reg, PCIE_LCSR2_DEEMP_LVL)); 2152 printf("\n"); 2153 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 2154 onoff("Equalization Phase 1 Successful", reg, 2155 PCIE_LCSR2_EQP1_SUC); 2156 onoff("Equalization Phase 2 Successful", reg, 2157 PCIE_LCSR2_EQP2_SUC); 2158 onoff("Equalization Phase 3 Successful", reg, 2159 PCIE_LCSR2_EQP3_SUC); 2160 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 2161 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD); 2162 if (drs_supported) { 2163 printf(" Downstream Component Presence: "); 2164 switch (__SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) { 2165 case PCIE_DSCOMPN_DOWN_NOTDETERM: 2166 printf("Link Down - Presence Not" 2167 " Determined\n"); 2168 break; 2169 case PCIE_DSCOMPN_DOWN_NOTPRES: 2170 printf("Link Down - Component Not Present\n"); 2171 break; 2172 case PCIE_DSCOMPN_DOWN_PRES: 2173 printf("Link Down - Component Present\n"); 2174 break; 2175 case PCIE_DSCOMPN_UP_PRES: 2176 printf("Link Up - Component Present\n"); 2177 break; 2178 case PCIE_DSCOMPN_UP_PRES_DRS: 2179 printf("Link Up - Component Present and DRS" 2180 " received\n"); 2181 break; 2182 default: 2183 printf("reserved\n"); 2184 break; 2185 } 2186 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV); 2187 } 2188 } 2189 2190 /* Slot Capability 2 */ 2191 /* Slot Control 2 */ 2192 /* Slot Status 2 */ 2193 } 2194 2195 static void 2196 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 2197 { 2198 pcireg_t reg; 2199 2200 printf("\n MSI-X Capability Register\n"); 2201 2202 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2203 printf(" Message Control register: 0x%04x\n", 2204 (reg >> 16) & 0xff); 2205 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 2206 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 2207 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 2208 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 2209 printf(" Table offset register: 0x%08x\n", reg); 2210 printf(" Table offset: 0x%08x\n", 2211 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 2212 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 2213 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 2214 printf(" Pending bit array register: 0x%08x\n", reg); 2215 printf(" Pending bit array offset: 0x%08x\n", 2216 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 2217 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 2218 } 2219 2220 static void 2221 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 2222 { 2223 pcireg_t reg; 2224 2225 printf("\n Serial ATA Capability Register\n"); 2226 2227 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2228 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 2229 printf(" Revision: %u.%u\n", 2230 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 2231 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 2232 2233 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 2234 2235 printf(" BAR Register: 0x%08x\n", reg); 2236 printf(" Register location: "); 2237 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 2238 printf("in config space\n"); 2239 else { 2240 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 2241 printf(" BAR offset: 0x%08x\n", 2242 (pcireg_t)__SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 2243 } 2244 } 2245 2246 static void 2247 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 2248 { 2249 pcireg_t reg; 2250 2251 printf("\n Advanced Features Capability Register\n"); 2252 2253 reg = regs[o2i(capoff + PCI_AFCAPR)]; 2254 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 2255 printf(" AF Structure Length: 0x%02x\n", 2256 (pcireg_t)__SHIFTOUT(reg, PCI_AF_LENGTH)); 2257 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 2258 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 2259 reg = regs[o2i(capoff + PCI_AFCSR)]; 2260 printf(" AF Control register: 0x%02x\n", reg & 0xff); 2261 /* 2262 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 2263 * and it's always 0 on read 2264 */ 2265 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 2266 onoff("Transaction Pending", reg, PCI_AFSR_TP); 2267 } 2268 2269 static struct { 2270 pcireg_t cap; 2271 const char *name; 2272 void (*printfunc)(const pcireg_t *, int); 2273 } pci_captab[] = { 2274 { PCI_CAP_RESERVED0, "reserved", NULL }, 2275 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 2276 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 2277 { PCI_CAP_VPD, "VPD", NULL }, 2278 { PCI_CAP_SLOTID, "SlotID", NULL }, 2279 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 2280 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 2281 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2282 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2283 { PCI_CAP_VENDSPEC, "Vendor-specific", 2284 pci_conf_print_vendspec_cap }, 2285 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2286 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2287 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2288 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2289 pci_conf_print_subsystem_cap }, 2290 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2291 { PCI_CAP_SECURE, "Secure Device", NULL }, 2292 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2293 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2294 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2295 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2296 { PCI_CAP_EA, "Enhanced Allocation", NULL } 2297 }; 2298 2299 static int 2300 pci_conf_find_cap(const pcireg_t *regs, int capoff, unsigned int capid, 2301 int *offsetp) 2302 { 2303 pcireg_t rval; 2304 int off; 2305 2306 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2307 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2308 rval = regs[o2i(off)]; 2309 if (capid == PCI_CAPLIST_CAP(rval)) { 2310 if (offsetp != NULL) 2311 *offsetp = off; 2312 return 1; 2313 } 2314 } 2315 return 0; 2316 } 2317 2318 static void 2319 pci_conf_print_caplist( 2320 #ifdef _KERNEL 2321 pci_chipset_tag_t pc, pcitag_t tag, 2322 #endif 2323 const pcireg_t *regs, int capoff) 2324 { 2325 int off; 2326 pcireg_t foundcap; 2327 pcireg_t rval; 2328 bool foundtable[__arraycount(pci_captab)]; 2329 unsigned int i; 2330 2331 /* Clear table */ 2332 for (i = 0; i < __arraycount(pci_captab); i++) 2333 foundtable[i] = false; 2334 2335 /* Print capability register's offset and the type first */ 2336 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2337 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2338 rval = regs[o2i(off)]; 2339 printf(" Capability register at 0x%02x\n", off); 2340 2341 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2342 foundcap = PCI_CAPLIST_CAP(rval); 2343 if (foundcap < __arraycount(pci_captab)) { 2344 printf("%s)\n", pci_captab[foundcap].name); 2345 /* Mark as found */ 2346 foundtable[foundcap] = true; 2347 } else 2348 printf("unknown)\n"); 2349 } 2350 2351 /* 2352 * And then, print the detail of each capability registers 2353 * in capability value's order. 2354 */ 2355 for (i = 0; i < __arraycount(pci_captab); i++) { 2356 if (foundtable[i] == false) 2357 continue; 2358 2359 /* 2360 * The type was found. Search capability list again and 2361 * print all capabilities that the capabiliy type is 2362 * the same. This is required because some capabilities 2363 * appear multiple times (e.g. HyperTransport capability). 2364 */ 2365 #if 0 2366 if (pci_conf_find_cap(regs, capoff, i, &off)) { 2367 rval = regs[o2i(off)]; 2368 if (pci_captab[i].printfunc != NULL) 2369 pci_captab[i].printfunc(regs, off); 2370 } 2371 #else 2372 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2373 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2374 rval = regs[o2i(off)]; 2375 if ((PCI_CAPLIST_CAP(rval) == i) 2376 && (pci_captab[i].printfunc != NULL)) 2377 pci_captab[i].printfunc(regs, off); 2378 } 2379 #endif 2380 } 2381 } 2382 2383 /* Extended Capability */ 2384 2385 static void 2386 pci_conf_print_aer_cap_uc(pcireg_t reg) 2387 { 2388 2389 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2390 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2391 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2392 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP); 2393 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2394 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2395 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2396 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2397 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2398 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2399 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2400 onoff("Unsupported Request Error", reg, 2401 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2402 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2403 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2404 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2405 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2406 onoff("TLP Prefix Blocked Error", reg, 2407 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2408 onoff("Poisoned TLP Egress Blocked", reg, 2409 PCI_AER_UC_POISONTLP_EGRESS_BLOCKED); 2410 } 2411 2412 static void 2413 pci_conf_print_aer_cap_cor(pcireg_t reg) 2414 { 2415 2416 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2417 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2418 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2419 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2420 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2421 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2422 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2423 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2424 } 2425 2426 static void 2427 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2428 { 2429 2430 printf(" First Error Pointer: 0x%04x\n", 2431 (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2432 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2433 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2434 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2435 onoff("ECRC Check Enab", reg, PCI_AER_ECRC_CHECK_ENABLE); 2436 onoff("Multiple Header Recording Capable", reg, 2437 PCI_AER_MULT_HDR_CAPABLE); 2438 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE); 2439 onoff("Completion Timeout Prefix/Header Log Capable", reg, 2440 PCI_AER_COMPTOUTPRFXHDRLOG_CAP); 2441 2442 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2443 if (!tlp_prefix_log) 2444 return; 2445 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2446 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2447 } 2448 2449 static void 2450 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2451 { 2452 2453 onoff("Correctable Error Reporting Enable", reg, 2454 PCI_AER_ROOTERR_COR_ENABLE); 2455 onoff("Non-Fatal Error Reporting Enable", reg, 2456 PCI_AER_ROOTERR_NF_ENABLE); 2457 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2458 } 2459 2460 static void 2461 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2462 { 2463 2464 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2465 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2466 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2467 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2468 PCI_AER_ROOTERR_MULTI_UC_ERR); 2469 onoff("First Uncorrectable Fatal", reg,PCI_AER_ROOTERR_FIRST_UC_FATAL); 2470 onoff("Non-Fatal Error Messages Received", reg,PCI_AER_ROOTERR_NF_ERR); 2471 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2472 printf(" Advanced Error Interrupt Message Number: 0x%02x\n", 2473 (unsigned int)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2474 } 2475 2476 static void 2477 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2478 { 2479 2480 printf(" Correctable Source ID: 0x%04x\n", 2481 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2482 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2483 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2484 } 2485 2486 static void 2487 pci_conf_print_aer_cap(const pcireg_t *regs, int capoff, int extcapoff) 2488 { 2489 pcireg_t reg; 2490 int pcie_capoff; 2491 int pcie_devtype = -1; 2492 bool tlp_prefix_log = false; 2493 2494 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2495 reg = regs[o2i(pcie_capoff)]; 2496 pcie_devtype = PCIE_XCAP_TYPE(reg); 2497 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2498 if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2499 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2500 /* End-End TLP Prefix Supported */ 2501 if (reg & PCIE_DCAP2_EETLP_PREF) { 2502 tlp_prefix_log = true; 2503 } 2504 } 2505 } 2506 2507 printf("\n Advanced Error Reporting Register\n"); 2508 2509 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2510 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2511 pci_conf_print_aer_cap_uc(reg); 2512 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2513 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2514 pci_conf_print_aer_cap_uc(reg); 2515 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2516 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2517 pci_conf_print_aer_cap_uc(reg); 2518 2519 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2520 printf(" Correctable Error Status register: 0x%08x\n", reg); 2521 pci_conf_print_aer_cap_cor(reg); 2522 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2523 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2524 pci_conf_print_aer_cap_cor(reg); 2525 2526 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2527 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2528 reg); 2529 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2530 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2531 printf(" Header Log register:\n"); 2532 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2533 extcapoff + PCI_AER_ROOTERR_CMD); 2534 2535 switch (pcie_devtype) { 2536 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ 2537 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ 2538 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2539 printf(" Root Error Command register: 0x%08x\n", reg); 2540 pci_conf_print_aer_cap_rooterr_cmd(reg); 2541 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2542 printf(" Root Error Status register: 0x%08x\n", reg); 2543 pci_conf_print_aer_cap_rooterr_status(reg); 2544 2545 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2546 printf(" Error Source Identification: 0x%04x\n", reg); 2547 pci_conf_print_aer_cap_errsrc_id(reg); 2548 break; 2549 } 2550 2551 if (tlp_prefix_log) { 2552 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2553 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2554 } 2555 } 2556 2557 static void 2558 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2559 pcireg_t parbsel, int parbsize) 2560 { 2561 pcireg_t reg; 2562 int num = 16 << parbsel; 2563 int num_per_reg = sizeof(pcireg_t) / parbsize; 2564 int i, j; 2565 2566 /* First, dump the table */ 2567 for (i = 0; i < num; i += num_per_reg) { 2568 reg = regs[o2i(off + i / num_per_reg)]; 2569 printf(" %s Arbitration Table: 0x%08x\n", name, reg); 2570 } 2571 /* And then, decode each entry */ 2572 for (i = 0; i < num; i += num_per_reg) { 2573 reg = regs[o2i(off + i / num_per_reg)]; 2574 for (j = 0; j < num_per_reg; j++) 2575 printf(" Phase[%d]: %d\n", j, reg); 2576 } 2577 } 2578 2579 static void 2580 pci_conf_print_vc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2581 { 2582 pcireg_t reg, n; 2583 int parbtab, parbsize; 2584 pcireg_t parbsel; 2585 int varbtab, varbsize; 2586 pcireg_t varbsel; 2587 int i, count; 2588 2589 printf("\n Virtual Channel Register\n"); 2590 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2591 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2592 count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2593 printf(" Extended VC Count: %d\n", count); 2594 n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2595 printf(" Low Priority Extended VC Count: %u\n", n); 2596 n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2597 printf(" Reference Clock: %s\n", 2598 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 2599 parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2600 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2601 2602 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 2603 printf(" Port VC Capability register 2: 0x%08x\n", reg); 2604 onoff("Hardware fixed arbitration scheme", 2605 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 2606 onoff("WRR arbitration with 32 phases", 2607 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 2608 onoff("WRR arbitration with 64 phases", 2609 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 2610 onoff("WRR arbitration with 128 phases", 2611 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 2612 varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 2613 printf(" VC Arbitration Table Offset: 0x%x\n", varbtab); 2614 2615 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 2616 printf(" Port VC Control register: 0x%04x\n", reg); 2617 varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 2618 printf(" VC Arbitration Select: 0x%x\n", varbsel); 2619 2620 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 2621 printf(" Port VC Status register: 0x%04x\n", reg); 2622 onoff("VC Arbitration Table Status", 2623 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 2624 2625 for (i = 0; i < count + 1; i++) { 2626 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 2627 printf(" VC number %d\n", i); 2628 printf(" VC Resource Capability Register: 0x%08x\n", reg); 2629 onoff(" Non-configurable Hardware fixed arbitration scheme", 2630 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 2631 onoff(" WRR arbitration with 32 phases", 2632 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 2633 onoff(" WRR arbitration with 64 phases", 2634 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 2635 onoff(" WRR arbitration with 128 phases", 2636 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 2637 onoff(" Time-based WRR arbitration with 128 phases", 2638 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 2639 onoff(" WRR arbitration with 256 phases", 2640 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 2641 onoff(" Advanced Packet Switching", 2642 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 2643 onoff(" Reject Snoop Transaction", 2644 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 2645 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 2646 printf(" Maximum Time Slots: %d\n", n); 2647 parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S; 2648 printf(" Port Arbitration Table offset: 0x%02x\n", 2649 parbtab); 2650 2651 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 2652 printf(" VC Resource Control Register: 0x%08x\n", reg); 2653 printf(" TC/VC Map: 0x%02x\n", 2654 (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 2655 /* 2656 * The load Port Arbitration Table bit is used to update 2657 * the Port Arbitration logic and it's always 0 on read, so 2658 * we don't print it. 2659 */ 2660 parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 2661 printf(" Port Arbitration Select: 0x%x\n", parbsel); 2662 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 2663 printf(" VC ID %d\n", n); 2664 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 2665 2666 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 2667 printf(" VC Resource Status Register: 0x%08x\n", reg); 2668 onoff(" Port Arbitration Table Status", 2669 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 2670 onoff(" VC Negotiation Pending", 2671 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 2672 2673 if ((parbtab != 0) && (parbsel != 0)) 2674 pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab, 2675 "Port", parbsel, parbsize); 2676 } 2677 2678 varbsize = 8; 2679 if ((varbtab != 0) && (varbsel != 0)) 2680 pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab, 2681 " VC", varbsel, varbsize); 2682 } 2683 2684 static void 2685 pci_conf_print_pwrbdgt_base_power(uint8_t base, unsigned int scale) 2686 { 2687 if (base <= 0xef) { 2688 unsigned int sdiv = 1; 2689 for (unsigned int i = scale; i > 0; i--) 2690 sdiv *= 10; 2691 2692 printf("%u", base / sdiv); 2693 2694 if (scale != 0) { 2695 printf(".%u", base % sdiv); 2696 } 2697 printf ("W\n"); 2698 return; 2699 } 2700 2701 const char *s; 2702 2703 switch (base) { 2704 case 0xf0: 2705 s = "239W < x <= 250W"; 2706 break; 2707 case 0xf1: 2708 s = "250W < x <= 275W"; 2709 break; 2710 case 0xf2: 2711 s = "275W < x <= 300W"; 2712 break; 2713 default: 2714 s = "reserved for above 300W"; 2715 break; 2716 } 2717 printf("%s\n", s); 2718 } 2719 2720 static const char * 2721 pci_conf_print_pwrbdgt_type(uint8_t reg) 2722 { 2723 2724 switch (reg) { 2725 case 0x00: 2726 return "PME Aux"; 2727 case 0x01: 2728 return "Auxilary"; 2729 case 0x02: 2730 return "Idle"; 2731 case 0x03: 2732 return "Sustained"; 2733 case 0x04: 2734 return "Sustained (Emergency Power Reduction)"; 2735 case 0x05: 2736 return "Maximum (Emergency Power Reduction)"; 2737 case 0x07: 2738 return "Maximum"; 2739 default: 2740 return "Unknown"; 2741 } 2742 } 2743 2744 static const char * 2745 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 2746 { 2747 2748 switch (reg) { 2749 case 0x00: 2750 return "Power(12V)"; 2751 case 0x01: 2752 return "Power(3.3V)"; 2753 case 0x02: 2754 return "Power(1.5V or 1.8V)"; 2755 case 0x07: 2756 return "Thermal"; 2757 default: 2758 return "Unknown"; 2759 } 2760 } 2761 2762 static void 2763 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff) 2764 { 2765 pcireg_t reg; 2766 unsigned int scale; 2767 2768 printf("\n Power Budgeting\n"); 2769 2770 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 2771 printf(" Data Select register: 0x%08x\n", reg); 2772 2773 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 2774 printf(" Data register: 0x%08x\n", reg); 2775 scale = __SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE); 2776 printf(" Base Power: "); 2777 pci_conf_print_pwrbdgt_base_power((uint8_t)reg, scale); 2778 printf(" PM Sub State: 0x%hhx\n", 2779 (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 2780 printf(" PM State: D%u\n", 2781 (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 2782 printf(" Type: %s\n", 2783 pci_conf_print_pwrbdgt_type( 2784 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 2785 printf(" Power Rail: %s\n", 2786 pci_conf_print_pwrbdgt_pwrrail( 2787 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 2788 2789 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 2790 printf(" Power Budget Capability register: 0x%08x\n", reg); 2791 onoff("System Allocated", 2792 reg, PCI_PWRBDGT_CAP_SYSALLOC); 2793 } 2794 2795 static const char * 2796 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 2797 { 2798 2799 switch (type) { 2800 case 0x00: 2801 return "Configuration Space Element"; 2802 case 0x01: 2803 return "System Egress Port or internal sink (memory)"; 2804 case 0x02: 2805 return "Internal Root Complex Link"; 2806 default: 2807 return "Unknown"; 2808 } 2809 } 2810 2811 static void 2812 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int capoff, int extcapoff) 2813 { 2814 pcireg_t reg; 2815 unsigned char nent, linktype; 2816 int i; 2817 2818 printf("\n Root Complex Link Declaration\n"); 2819 2820 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 2821 printf(" Element Self Description Register: 0x%08x\n", reg); 2822 printf(" Element Type: %s\n", 2823 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 2824 nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 2825 printf(" Number of Link Entries: %hhu\n", nent); 2826 printf(" Component ID: %hhu\n", 2827 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 2828 printf(" Port Number: %hhu\n", 2829 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 2830 for (i = 0; i < nent; i++) { 2831 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 2832 printf(" Link Entry %d:\n", i + 1); 2833 printf(" Link Description Register: 0x%08x\n", reg); 2834 onoff(" Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID); 2835 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 2836 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 2837 "Configuration Space", "Memory-Mapped Space"); 2838 onoff(" Associated RCRB Header", reg, 2839 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 2840 printf(" Target Component ID: %hhu\n", 2841 (unsigned char)__SHIFTOUT(reg, 2842 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 2843 printf(" Target Port Number: %hhu\n", 2844 (unsigned char)__SHIFTOUT(reg, 2845 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 2846 2847 if (linktype == 0) { 2848 /* Memory-Mapped Space */ 2849 reg = regs[o2i(extcapoff 2850 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 2851 printf(" Link Address Low Register: 0x%08x\n", 2852 reg); 2853 reg = regs[o2i(extcapoff 2854 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 2855 printf(" Link Address High Register: 0x%08x\n", 2856 reg); 2857 } else { 2858 unsigned int nb; 2859 pcireg_t lo, hi; 2860 2861 /* Configuration Space */ 2862 lo = regs[o2i(extcapoff 2863 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 2864 printf(" Configuration Space Low Register: " 2865 "0x%08x\n", lo); 2866 hi = regs[o2i(extcapoff 2867 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 2868 printf(" Configuration Space High Register: " 2869 "0x%08x\n", hi); 2870 nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 2871 printf(" N: %u\n", nb); 2872 printf(" Func: %hhu\n", 2873 (unsigned char)__SHIFTOUT(lo, 2874 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 2875 printf(" Dev: %hhu\n", 2876 (unsigned char)__SHIFTOUT(lo, 2877 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 2878 printf(" Bus: %hhu\n", 2879 (unsigned char)__SHIFTOUT(lo, 2880 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 2881 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 2882 printf(" Configuration Space Base Address: " 2883 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 2884 } 2885 } 2886 } 2887 2888 /* XXX pci_conf_print_rclink_ctl_cap */ 2889 2890 static void 2891 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2892 { 2893 pcireg_t reg; 2894 2895 printf("\n Root Complex Event Collector Association\n"); 2896 2897 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 2898 printf(" Association Bitmap for Root Complex Integrated Devices:" 2899 " 0x%08x\n", reg); 2900 } 2901 2902 /* XXX pci_conf_print_mfvc_cap */ 2903 /* XXX pci_conf_print_vc2_cap */ 2904 /* XXX pci_conf_print_rcrb_cap */ 2905 /* XXX pci_conf_print_vendor_cap */ 2906 /* XXX pci_conf_print_cac_cap */ 2907 2908 static void 2909 pci_conf_print_acs_cap(const pcireg_t *regs, int capoff, int extcapoff) 2910 { 2911 pcireg_t reg, cap, ctl; 2912 unsigned int size, i; 2913 2914 printf("\n Access Control Services\n"); 2915 2916 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 2917 cap = reg & 0xffff; 2918 ctl = reg >> 16; 2919 printf(" ACS Capability register: 0x%08x\n", cap); 2920 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 2921 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 2922 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 2923 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 2924 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 2925 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 2926 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 2927 size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 2928 if (size == 0) 2929 size = 256; 2930 printf(" Egress Control Vector Size: %u\n", size); 2931 printf(" ACS Control register: 0x%08x\n", ctl); 2932 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 2933 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 2934 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 2935 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 2936 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 2937 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 2938 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 2939 2940 /* 2941 * If the P2P Egress Control Capability bit is 0, ignore the Egress 2942 * Control vector. 2943 */ 2944 if ((cap & PCI_ACS_CAP_E) == 0) 2945 return; 2946 for (i = 0; i < size; i += 32) 2947 printf(" Egress Control Vector [%u..%u]: 0x%08x\n", i + 31, 2948 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 2949 } 2950 2951 static void 2952 pci_conf_print_ari_cap(const pcireg_t *regs, int capoff, int extcapoff) 2953 { 2954 pcireg_t reg, cap, ctl; 2955 2956 printf("\n Alternative Routing-ID Interpretation Register\n"); 2957 2958 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2959 cap = reg & 0xffff; 2960 ctl = reg >> 16; 2961 printf(" Capability register: 0x%08x\n", cap); 2962 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 2963 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 2964 printf(" Next Function Number: %u\n", 2965 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 2966 printf(" Control register: 0x%08x\n", ctl); 2967 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 2968 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 2969 printf(" Function Group: %u\n", 2970 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 2971 } 2972 2973 static void 2974 pci_conf_print_ats_cap(const pcireg_t *regs, int capoff, int extcapoff) 2975 { 2976 pcireg_t reg, cap, ctl; 2977 unsigned int num; 2978 2979 printf("\n Address Translation Services\n"); 2980 2981 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2982 cap = reg & 0xffff; 2983 ctl = reg >> 16; 2984 printf(" Capability register: 0x%04x\n", cap); 2985 num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 2986 if (num == 0) 2987 num = 32; 2988 printf(" Invalidate Queue Depth: %u\n", num); 2989 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 2990 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 2991 2992 printf(" Control register: 0x%04x\n", ctl); 2993 printf(" Smallest Translation Unit: %u\n", 2994 (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU)); 2995 onoff("Enable", reg, PCI_ATS_CTL_EN); 2996 } 2997 2998 static void 2999 pci_conf_print_sernum_cap(const pcireg_t *regs, int capoff, int extcapoff) 3000 { 3001 pcireg_t lo, hi; 3002 3003 printf("\n Device Serial Number Register\n"); 3004 3005 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 3006 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 3007 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 3008 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 3009 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 3010 } 3011 3012 static void 3013 pci_conf_print_sriov_cap(const pcireg_t *regs, int capoff, int extcapoff) 3014 { 3015 char buf[sizeof("99999 MB")]; 3016 pcireg_t reg; 3017 pcireg_t total_vfs; 3018 int i; 3019 bool first; 3020 3021 printf("\n Single Root IO Virtualization Register\n"); 3022 3023 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 3024 printf(" Capabilities register: 0x%08x\n", reg); 3025 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 3026 onoff("ARI Capable Hierarchy Preserved", reg, 3027 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 3028 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 3029 printf(" VF Migration Interrupt Message Number: 0x%03x\n", 3030 (pcireg_t)__SHIFTOUT(reg, 3031 PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 3032 } 3033 3034 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 3035 printf(" Control register: 0x%04x\n", reg); 3036 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 3037 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 3038 onoff("VF Migration Interrupt Enable", reg, 3039 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 3040 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 3041 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 3042 3043 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 3044 printf(" Status register: 0x%04x\n", reg); 3045 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 3046 3047 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 3048 printf(" InitialVFs register: 0x%04x\n", reg); 3049 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 3050 printf(" TotalVFs register: 0x%04x\n", reg); 3051 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 3052 printf(" NumVFs register: 0x%04x\n", reg); 3053 3054 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 3055 printf(" Function Dependency Link register: 0x%04x\n", reg); 3056 3057 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 3058 printf(" First VF Offset register: 0x%04x\n", reg); 3059 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 3060 printf(" VF Stride register: 0x%04x\n", reg); 3061 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_DID)] >> 16; 3062 printf(" Device ID: 0x%04x\n", reg); 3063 3064 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 3065 printf(" Supported Page Sizes register: 0x%08x\n", reg); 3066 printf(" Supported Page Size:"); 3067 for (i = 0, first = true; i < 32; i++) { 3068 if (reg & __BIT(i)) { 3069 #ifdef _KERNEL 3070 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 3071 #else 3072 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 3073 HN_AUTOSCALE, 0); 3074 #endif 3075 printf("%s %s", first ? "" : ",", buf); 3076 first = false; 3077 } 3078 } 3079 printf("\n"); 3080 3081 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 3082 printf(" System Page Sizes register: 0x%08x\n", reg); 3083 printf(" Page Size: "); 3084 if (reg != 0) { 3085 #ifdef _KERNEL 3086 format_bytes(buf, sizeof(buf), 1LL << (ffs(reg) + 12)); 3087 #else 3088 humanize_number(buf, sizeof(buf), 1LL << (ffs(reg) + 12), "B", 3089 HN_AUTOSCALE, 0); 3090 #endif 3091 printf("%s", buf); 3092 } else { 3093 printf("unknown"); 3094 } 3095 printf("\n"); 3096 3097 for (i = 0; i < 6; i++) { 3098 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 3099 printf(" VF BAR%d register: 0x%08x\n", i, reg); 3100 } 3101 3102 if (total_vfs > 0) { 3103 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 3104 printf(" VF Migration State Array Offset register: 0x%08x\n", 3105 reg); 3106 printf(" VF Migration State Offset: 0x%08x\n", 3107 (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 3108 i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 3109 printf(" VF Migration State BIR: "); 3110 if (i >= 0 && i <= 5) { 3111 printf("BAR%d", i); 3112 } else { 3113 printf("unknown BAR (%d)", i); 3114 } 3115 printf("\n"); 3116 } 3117 } 3118 3119 /* XXX pci_conf_print_mriov_cap */ 3120 3121 static void 3122 pci_conf_print_multicast_cap(const pcireg_t *regs, int capoff, int extcapoff) 3123 { 3124 pcireg_t reg, cap, ctl; 3125 pcireg_t regl, regh; 3126 uint64_t addr; 3127 int n; 3128 3129 printf("\n Multicast\n"); 3130 3131 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 3132 cap = reg & 0xffff; 3133 ctl = reg >> 16; 3134 printf(" Capability Register: 0x%04x\n", cap); 3135 printf(" Max Group: %u\n", 3136 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 3137 3138 /* Endpoint Only */ 3139 n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 3140 if (n > 0) 3141 printf(" Windw Size Requested: %d\n", 1 << (n - 1)); 3142 3143 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 3144 3145 printf(" Control Register: 0x%04x\n", ctl); 3146 printf(" Num Group: %u\n", 3147 (unsigned int)__SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 3148 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 3149 3150 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 3151 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 3152 printf(" Base Address Register 0: 0x%08x\n", regl); 3153 printf(" Base Address Register 1: 0x%08x\n", regh); 3154 printf(" Index Position: %u\n", 3155 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 3156 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 3157 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 3158 3159 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 3160 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 3161 printf(" Receive Register 0: 0x%08x\n", regl); 3162 printf(" Receive Register 1: 0x%08x\n", regh); 3163 3164 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 3165 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 3166 printf(" Block All Register 0: 0x%08x\n", regl); 3167 printf(" Block All Register 1: 0x%08x\n", regh); 3168 3169 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 3170 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 3171 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 3172 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 3173 3174 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 3175 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 3176 printf(" Overlay BAR 0: 0x%08x\n", regl); 3177 printf(" Overlay BAR 1: 0x%08x\n", regh); 3178 3179 n = regl & PCI_MCAST_OVERLAYL_SIZE; 3180 printf(" Overlay Size: "); 3181 if (n >= 6) 3182 printf("%d\n", n); 3183 else 3184 printf("off\n"); 3185 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 3186 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 3187 } 3188 3189 static void 3190 pci_conf_print_page_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3191 { 3192 pcireg_t reg, ctl, sta; 3193 3194 printf("\n Page Request\n"); 3195 3196 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 3197 ctl = reg & 0xffff; 3198 sta = reg >> 16; 3199 printf(" Control Register: 0x%04x\n", ctl); 3200 onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E); 3201 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 3202 3203 printf(" Status Register: 0x%04x\n", sta); 3204 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 3205 onoff("Unexpected Page Request Group Index", reg, 3206 PCI_PAGE_REQ_STA_UPRGI); 3207 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 3208 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 3209 3210 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 3211 printf(" Outstanding Page Request Capacity: %u\n", reg); 3212 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 3213 printf(" Outstanding Page Request Allocation: %u\n", reg); 3214 } 3215 3216 /* XXX pci_conf_print_amd_cap */ 3217 3218 #define MEM_PBUFSIZE sizeof("999GB") 3219 3220 static void 3221 pci_conf_print_resizbar_cap(const pcireg_t *regs, int capoff, int extcapoff) 3222 { 3223 pcireg_t cap, ctl; 3224 unsigned int bars, i, n; 3225 char pbuf[MEM_PBUFSIZE]; 3226 3227 printf("\n Resizable BAR\n"); 3228 3229 /* Get Number of Resizable BARs */ 3230 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))]; 3231 bars = __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR); 3232 printf(" Number of Resizable BARs: "); 3233 if (bars <= 6) 3234 printf("%u\n", bars); 3235 else { 3236 printf("incorrect (%u)\n", bars); 3237 return; 3238 } 3239 3240 for (n = 0; n < 6; n++) { 3241 cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))]; 3242 printf(" Capability register(%u): 0x%08x\n", n, cap); 3243 if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0) 3244 continue; /* Not Used */ 3245 printf(" Acceptable BAR sizes:"); 3246 for (i = 4; i <= 23; i++) { 3247 if ((cap & (1 << i)) != 0) { 3248 humanize_number(pbuf, MEM_PBUFSIZE, 3249 (int64_t)1024 * 1024 << (i - 4), "B", 3250 #ifdef _KERNEL 3251 1); 3252 #else 3253 HN_AUTOSCALE, HN_NOSPACE); 3254 #endif 3255 printf(" %s", pbuf); 3256 } 3257 } 3258 printf("\n"); 3259 3260 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))]; 3261 printf(" Control register(%u): 0x%08x\n", n, ctl); 3262 printf(" BAR Index: %u\n", 3263 (unsigned int)__SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX)); 3264 humanize_number(pbuf, MEM_PBUFSIZE, 3265 (int64_t)1024 * 1024 3266 << __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ), 3267 "B", 3268 #ifdef _KERNEL 3269 1); 3270 #else 3271 HN_AUTOSCALE, HN_NOSPACE); 3272 #endif 3273 printf(" BAR Size: %s\n", pbuf); 3274 } 3275 } 3276 3277 static void 3278 pci_conf_print_dpa_cap(const pcireg_t *regs, int capoff, int extcapoff) 3279 { 3280 pcireg_t reg; 3281 unsigned int substmax, i; 3282 3283 printf("\n Dynamic Power Allocation\n"); 3284 3285 reg = regs[o2i(extcapoff + PCI_DPA_CAP)]; 3286 printf(" Capability register: 0x%08x\n", reg); 3287 substmax = __SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX); 3288 printf(" Substate Max: %u\n", substmax); 3289 printf(" Transition Latency Unit: "); 3290 switch (__SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) { 3291 case 0: 3292 printf("1ms\n"); 3293 break; 3294 case 1: 3295 printf("10ms\n"); 3296 break; 3297 case 2: 3298 printf("100ms\n"); 3299 break; 3300 default: 3301 printf("reserved\n"); 3302 break; 3303 } 3304 printf(" Power Allocation Scale: "); 3305 switch (__SHIFTOUT(reg, PCI_DPA_CAP_PAS)) { 3306 case 0: 3307 printf("10.0x\n"); 3308 break; 3309 case 1: 3310 printf("1.0x\n"); 3311 break; 3312 case 2: 3313 printf("0.1x\n"); 3314 break; 3315 case 3: 3316 printf("0.01x\n"); 3317 break; 3318 } 3319 printf(" Transition Latency Value 0: %u\n", 3320 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY0)); 3321 printf(" Transition Latency Value 1: %u\n", 3322 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY1)); 3323 3324 reg = regs[o2i(extcapoff + PCI_DPA_LATIND)]; 3325 printf(" Latency Indicatior register: 0x%08x\n", reg); 3326 3327 reg = regs[o2i(extcapoff + PCI_DPA_CS)]; 3328 printf(" Status register: 0x%04x\n", reg & 0xffff); 3329 printf(" Substate Status: 0x%02x\n", 3330 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT)); 3331 onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN); 3332 printf(" Control register: 0x%04x\n", reg >> 16); 3333 printf(" Substate Control: 0x%02x\n", 3334 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL)); 3335 3336 for (i = 0; i <= substmax; i++) 3337 printf(" Substate Power Allocation register %d: 0x%02x\n", 3338 i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff)); 3339 } 3340 3341 static const char * 3342 pci_conf_print_tph_req_cap_sttabloc(unsigned char val) 3343 { 3344 3345 switch (val) { 3346 case 0x0: 3347 return "Not Present"; 3348 case 0x1: 3349 return "in the TPH Requester Capability Structure"; 3350 case 0x2: 3351 return "in the MSI-X Table"; 3352 default: 3353 return "Unknown"; 3354 } 3355 } 3356 3357 static void 3358 pci_conf_print_tph_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3359 { 3360 pcireg_t reg; 3361 int size, i, j; 3362 3363 printf("\n TPH Requester Extended Capability\n"); 3364 3365 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 3366 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 3367 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 3368 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 3369 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 3370 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 3371 printf(" ST Table Location: %s\n", 3372 pci_conf_print_tph_req_cap_sttabloc( 3373 (unsigned char)__SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC))); 3374 size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 3375 printf(" ST Table Size: %d\n", size); 3376 for (i = 0; i < size ; i += 2) { 3377 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 3378 for (j = 0; j < 2 ; j++) { 3379 uint32_t entry = reg; 3380 3381 if (j != 0) 3382 entry >>= 16; 3383 entry &= 0xffff; 3384 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 3385 i + j, entry); 3386 } 3387 } 3388 } 3389 3390 static void 3391 pci_conf_print_ltr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3392 { 3393 pcireg_t reg; 3394 3395 printf("\n Latency Tolerance Reporting\n"); 3396 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)] & 0xffff; 3397 printf(" Max Snoop Latency Register: 0x%04x\n", reg); 3398 printf(" Max Snoop LatencyValue: %u\n", 3399 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL)); 3400 printf(" Max Snoop LatencyScale: %uns\n", 3401 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE))); 3402 reg = regs[o2i(extcapoff + PCI_LTR_MAXNOSNOOPLAT)] >> 16; 3403 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg); 3404 printf(" Max No-Snoop LatencyValue: %u\n", 3405 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL)); 3406 printf(" Max No-Snoop LatencyScale: %uns\n", 3407 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE))); 3408 } 3409 3410 static void 3411 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int capoff, int extcapoff) 3412 { 3413 int pcie_capoff; 3414 pcireg_t reg; 3415 int i, maxlinkwidth; 3416 3417 printf("\n Secondary PCI Express Register\n"); 3418 3419 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3420 printf(" Link Control 3 register: 0x%08x\n", reg); 3421 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3422 onoff("Link Equalization Request Interrupt Enable", 3423 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3424 printf(" Enable Lower SKP OS Generation Vector:"); 3425 pci_print_pcie_linkspeedvector( 3426 __SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV)); 3427 printf("\n"); 3428 3429 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3430 printf(" Lane Error Status register: 0x%08x\n", reg); 3431 3432 /* Get Max Link Width */ 3433 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)){ 3434 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3435 maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3436 } else { 3437 printf("error: falied to get PCIe capablity\n"); 3438 return; 3439 } 3440 for (i = 0; i < maxlinkwidth; i++) { 3441 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3442 if (i % 2 != 0) 3443 reg >>= 16; 3444 else 3445 reg &= 0xffff; 3446 printf(" Equalization Control Register (Link %d): 0x%04x\n", 3447 i, reg); 3448 printf(" Downstream Port Transmit Preset: 0x%x\n", 3449 (pcireg_t)__SHIFTOUT(reg, 3450 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3451 printf(" Downstream Port Receive Hint: 0x%x\n", 3452 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3453 printf(" Upstream Port Transmit Preset: 0x%x\n", 3454 (pcireg_t)__SHIFTOUT(reg, 3455 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3456 printf(" Upstream Port Receive Hint: 0x%x\n", 3457 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3458 } 3459 } 3460 3461 /* XXX pci_conf_print_pmux_cap */ 3462 3463 static void 3464 pci_conf_print_pasid_cap(const pcireg_t *regs, int capoff, int extcapoff) 3465 { 3466 pcireg_t reg, cap, ctl; 3467 unsigned int num; 3468 3469 printf("\n Process Address Space ID\n"); 3470 3471 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3472 cap = reg & 0xffff; 3473 ctl = reg >> 16; 3474 printf(" PASID Capability Register: 0x%04x\n", cap); 3475 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3476 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3477 num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3478 printf(" Max PASID Width: %u\n", num); 3479 3480 printf(" PASID Control Register: 0x%04x\n", ctl); 3481 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3482 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3483 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 3484 } 3485 3486 static void 3487 pci_conf_print_lnr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3488 { 3489 pcireg_t reg, cap, ctl; 3490 unsigned int num; 3491 3492 printf("\n LN Requester\n"); 3493 3494 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 3495 cap = reg & 0xffff; 3496 ctl = reg >> 16; 3497 printf(" LNR Capability register: 0x%04x\n", cap); 3498 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 3499 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 3500 num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 3501 printf(" LNR Registration MAX: %u\n", num); 3502 3503 printf(" LNR Control register: 0x%04x\n", ctl); 3504 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 3505 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 3506 num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 3507 printf(" LNR Registration Limit: %u\n", num); 3508 } 3509 3510 /* XXX pci_conf_print_dpc_cap */ 3511 3512 static int 3513 pci_conf_l1pm_cap_tposcale(unsigned char scale) 3514 { 3515 3516 /* Return scale in us */ 3517 switch (scale) { 3518 case 0x0: 3519 return 2; 3520 case 0x1: 3521 return 10; 3522 case 0x2: 3523 return 100; 3524 default: 3525 return -1; 3526 } 3527 } 3528 3529 static void 3530 pci_conf_print_l1pm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3531 { 3532 pcireg_t reg; 3533 int scale, val; 3534 3535 printf("\n L1 PM Substates\n"); 3536 3537 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 3538 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 3539 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 3540 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 3541 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 3542 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 3543 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 3544 printf(" Port Common Mode Restore Time: %uus\n", 3545 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 3546 scale = pci_conf_l1pm_cap_tposcale( 3547 __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 3548 val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 3549 printf(" Port T_POWER_ON: "); 3550 if (scale == -1) 3551 printf("unknown\n"); 3552 else 3553 printf("%dus\n", val * scale); 3554 3555 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 3556 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 3557 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 3558 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 3559 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 3560 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 3561 printf(" Common Mode Restore Time: %uus\n", 3562 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 3563 scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 3564 val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 3565 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 3566 3567 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 3568 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 3569 scale = pci_conf_l1pm_cap_tposcale( 3570 __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 3571 val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 3572 printf(" T_POWER_ON: "); 3573 if (scale == -1) 3574 printf("unknown\n"); 3575 else 3576 printf("%dus\n", val * scale); 3577 } 3578 3579 static void 3580 pci_conf_print_ptm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3581 { 3582 pcireg_t reg; 3583 uint32_t val; 3584 3585 printf("\n Precision Time Management\n"); 3586 3587 reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; 3588 printf(" PTM Capability register: 0x%08x\n", reg); 3589 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ); 3590 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP); 3591 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT); 3592 printf(" Local Clock Granularity: "); 3593 val = __SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL); 3594 switch (val) { 3595 case 0: 3596 printf("Not implemented\n"); 3597 break; 3598 case 0xffff: 3599 printf("> 254ns\n"); 3600 break; 3601 default: 3602 printf("%uns\n", val); 3603 break; 3604 } 3605 3606 reg = regs[o2i(extcapoff + PCI_PTM_CTL)]; 3607 printf(" PTM Control register: 0x%08x\n", reg); 3608 onoff("PTM Enable", reg, PCI_PTM_CTL_EN); 3609 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL); 3610 printf(" Effective Granularity: "); 3611 val = __SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL); 3612 switch (val) { 3613 case 0: 3614 printf("Unknown\n"); 3615 break; 3616 case 0xffff: 3617 printf("> 254ns\n"); 3618 break; 3619 default: 3620 printf("%uns\n", val); 3621 break; 3622 } 3623 } 3624 3625 /* XXX pci_conf_print_mpcie_cap */ 3626 /* XXX pci_conf_print_frsq_cap */ 3627 /* XXX pci_conf_print_rtr_cap */ 3628 /* XXX pci_conf_print_desigvndsp_cap */ 3629 /* XXX pci_conf_print_vf_resizbar_cap */ 3630 3631 #undef MS 3632 #undef SM 3633 #undef RW 3634 3635 static struct { 3636 pcireg_t cap; 3637 const char *name; 3638 void (*printfunc)(const pcireg_t *, int, int); 3639 } pci_extcaptab[] = { 3640 { 0, "reserved", 3641 NULL }, 3642 { PCI_EXTCAP_AER, "Advanced Error Reporting", 3643 pci_conf_print_aer_cap }, 3644 { PCI_EXTCAP_VC, "Virtual Channel", 3645 pci_conf_print_vc_cap }, 3646 { PCI_EXTCAP_SERNUM, "Device Serial Number", 3647 pci_conf_print_sernum_cap }, 3648 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 3649 pci_conf_print_pwrbdgt_cap }, 3650 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 3651 pci_conf_print_rclink_dcl_cap }, 3652 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 3653 NULL }, 3654 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 3655 pci_conf_print_rcec_assoc_cap }, 3656 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 3657 NULL }, 3658 { PCI_EXTCAP_VC2, "Virtual Channel", 3659 NULL }, 3660 { PCI_EXTCAP_RCRB, "RCRB Header", 3661 NULL }, 3662 { PCI_EXTCAP_VENDOR, "Vendor Unique", 3663 NULL }, 3664 { PCI_EXTCAP_CAC, "Configuration Access Correction", 3665 NULL }, 3666 { PCI_EXTCAP_ACS, "Access Control Services", 3667 pci_conf_print_acs_cap }, 3668 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 3669 pci_conf_print_ari_cap }, 3670 { PCI_EXTCAP_ATS, "Address Translation Services", 3671 pci_conf_print_ats_cap }, 3672 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 3673 pci_conf_print_sriov_cap }, 3674 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 3675 NULL }, 3676 { PCI_EXTCAP_MCAST, "Multicast", 3677 pci_conf_print_multicast_cap }, 3678 { PCI_EXTCAP_PAGE_REQ, "Page Request", 3679 pci_conf_print_page_req_cap }, 3680 { PCI_EXTCAP_AMD, "Reserved for AMD", 3681 NULL }, 3682 { PCI_EXTCAP_RESIZBAR, "Resizable BAR", 3683 pci_conf_print_resizbar_cap }, 3684 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 3685 pci_conf_print_dpa_cap }, 3686 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 3687 pci_conf_print_tph_req_cap }, 3688 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 3689 pci_conf_print_ltr_cap }, 3690 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 3691 pci_conf_print_sec_pcie_cap }, 3692 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 3693 NULL }, 3694 { PCI_EXTCAP_PASID, "Process Address Space ID", 3695 pci_conf_print_pasid_cap }, 3696 { PCI_EXTCAP_LN_REQ, "LN Requester", 3697 pci_conf_print_lnr_cap }, 3698 { PCI_EXTCAP_DPC, "Downstream Port Containment", 3699 NULL }, 3700 { PCI_EXTCAP_L1PM, "L1 PM Substates", 3701 pci_conf_print_l1pm_cap }, 3702 { PCI_EXTCAP_PTM, "Precision Time Management", 3703 pci_conf_print_ptm_cap }, 3704 { PCI_EXTCAP_MPCIE, "M-PCIe", 3705 NULL }, 3706 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 3707 NULL }, 3708 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 3709 NULL }, 3710 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 3711 NULL }, 3712 { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs", 3713 NULL }, 3714 }; 3715 3716 static int 3717 pci_conf_find_extcap(const pcireg_t *regs, int capoff, unsigned int capid, 3718 int *offsetp) 3719 { 3720 int off; 3721 pcireg_t rval; 3722 3723 for (off = PCI_EXTCAPLIST_BASE; 3724 off != 0; 3725 off = PCI_EXTCAPLIST_NEXT(rval)) { 3726 rval = regs[o2i(off)]; 3727 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 3728 if (offsetp != NULL) 3729 *offsetp = off; 3730 return 1; 3731 } 3732 } 3733 return 0; 3734 } 3735 3736 static void 3737 pci_conf_print_extcaplist( 3738 #ifdef _KERNEL 3739 pci_chipset_tag_t pc, pcitag_t tag, 3740 #endif 3741 const pcireg_t *regs, int capoff) 3742 { 3743 int off; 3744 pcireg_t foundcap; 3745 pcireg_t rval; 3746 bool foundtable[__arraycount(pci_extcaptab)]; 3747 unsigned int i; 3748 3749 /* Check Extended capability structure */ 3750 off = PCI_EXTCAPLIST_BASE; 3751 rval = regs[o2i(off)]; 3752 if (rval == 0xffffffff || rval == 0) 3753 return; 3754 3755 /* Clear table */ 3756 for (i = 0; i < __arraycount(pci_extcaptab); i++) 3757 foundtable[i] = false; 3758 3759 /* Print extended capability register's offset and the type first */ 3760 for (;;) { 3761 printf(" Extended Capability Register at 0x%02x\n", off); 3762 3763 foundcap = PCI_EXTCAPLIST_CAP(rval); 3764 printf(" type: 0x%04x (", foundcap); 3765 if (foundcap < __arraycount(pci_extcaptab)) { 3766 printf("%s)\n", pci_extcaptab[foundcap].name); 3767 /* Mark as found */ 3768 foundtable[foundcap] = true; 3769 } else 3770 printf("unknown)\n"); 3771 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 3772 3773 off = PCI_EXTCAPLIST_NEXT(rval); 3774 if (off == 0) 3775 break; 3776 else if (off <= PCI_CONF_SIZE) { 3777 printf(" next pointer: 0x%03x (incorrect)\n", off); 3778 return; 3779 } 3780 rval = regs[o2i(off)]; 3781 } 3782 3783 /* 3784 * And then, print the detail of each capability registers 3785 * in capability value's order. 3786 */ 3787 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 3788 if (foundtable[i] == false) 3789 continue; 3790 3791 /* 3792 * The type was found. Search capability list again and 3793 * print all capabilities that the capabiliy type is 3794 * the same. 3795 */ 3796 if (pci_conf_find_extcap(regs, capoff, i, &off) == 0) 3797 continue; 3798 rval = regs[o2i(off)]; 3799 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 3800 || (pci_extcaptab[i].printfunc == NULL)) 3801 continue; 3802 3803 pci_extcaptab[i].printfunc(regs, capoff, off); 3804 3805 } 3806 } 3807 3808 /* Print the Secondary Status Register. */ 3809 static void 3810 pci_conf_print_ssr(pcireg_t rval) 3811 { 3812 pcireg_t devsel; 3813 3814 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 3815 onoff("66 MHz capable", rval, __BIT(5)); 3816 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 3817 onoff("Fast back-to-back capable", rval, __BIT(7)); 3818 onoff("Data parity error detected", rval, __BIT(8)); 3819 3820 printf(" DEVSEL timing: "); 3821 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 3822 switch (devsel) { 3823 case 0: 3824 printf("fast"); 3825 break; 3826 case 1: 3827 printf("medium"); 3828 break; 3829 case 2: 3830 printf("slow"); 3831 break; 3832 default: 3833 printf("unknown/reserved"); /* XXX */ 3834 break; 3835 } 3836 printf(" (0x%x)\n", devsel); 3837 3838 onoff("Signalled target abort", rval, __BIT(11)); 3839 onoff("Received target abort", rval, __BIT(12)); 3840 onoff("Received master abort", rval, __BIT(13)); 3841 onoff("Received system error", rval, __BIT(14)); 3842 onoff("Detected parity error", rval, __BIT(15)); 3843 } 3844 3845 static void 3846 pci_conf_print_type0( 3847 #ifdef _KERNEL 3848 pci_chipset_tag_t pc, pcitag_t tag, 3849 #endif 3850 const pcireg_t *regs 3851 #ifdef _KERNEL 3852 , int sizebars 3853 #endif 3854 ) 3855 { 3856 int off, width; 3857 pcireg_t rval; 3858 3859 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 3860 #ifdef _KERNEL 3861 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3862 #else 3863 width = pci_conf_print_bar(regs, off, NULL); 3864 #endif 3865 } 3866 3867 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 3868 3869 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 3870 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 3871 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 3872 3873 /* XXX */ 3874 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 3875 3876 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3877 printf(" Capability list pointer: 0x%02x\n", 3878 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 3879 else 3880 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 3881 3882 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 3883 3884 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3885 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 3886 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 3887 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 3888 switch (PCI_INTERRUPT_PIN(rval)) { 3889 case PCI_INTERRUPT_PIN_NONE: 3890 printf("(none)"); 3891 break; 3892 case PCI_INTERRUPT_PIN_A: 3893 printf("(pin A)"); 3894 break; 3895 case PCI_INTERRUPT_PIN_B: 3896 printf("(pin B)"); 3897 break; 3898 case PCI_INTERRUPT_PIN_C: 3899 printf("(pin C)"); 3900 break; 3901 case PCI_INTERRUPT_PIN_D: 3902 printf("(pin D)"); 3903 break; 3904 default: 3905 printf("(? ? ?)"); 3906 break; 3907 } 3908 printf("\n"); 3909 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 3910 } 3911 3912 static void 3913 pci_conf_print_type1( 3914 #ifdef _KERNEL 3915 pci_chipset_tag_t pc, pcitag_t tag, 3916 #endif 3917 const pcireg_t *regs 3918 #ifdef _KERNEL 3919 , int sizebars 3920 #endif 3921 ) 3922 { 3923 int off, width; 3924 pcireg_t rval; 3925 uint32_t base, limit; 3926 uint32_t base_h, limit_h; 3927 uint64_t pbase, plimit; 3928 int use_upper; 3929 3930 /* 3931 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 3932 * Bridge chip documentation, and may not be correct with 3933 * respect to various standards. (XXX) 3934 */ 3935 3936 for (off = 0x10; off < 0x18; off += width) { 3937 #ifdef _KERNEL 3938 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3939 #else 3940 width = pci_conf_print_bar(regs, off, NULL); 3941 #endif 3942 } 3943 3944 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 3945 printf(" Primary bus number: 0x%02x\n", 3946 PCI_BRIDGE_BUS_PRIMARY(rval)); 3947 printf(" Secondary bus number: 0x%02x\n", 3948 PCI_BRIDGE_BUS_SECONDARY(rval)); 3949 printf(" Subordinate bus number: 0x%02x\n", 3950 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 3951 printf(" Secondary bus latency timer: 0x%02x\n", 3952 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 3953 3954 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 3955 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 3956 3957 /* I/O region */ 3958 printf(" I/O region:\n"); 3959 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 3960 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 3961 if (PCI_BRIDGE_IO_32BITS(rval)) 3962 use_upper = 1; 3963 else 3964 use_upper = 0; 3965 onoff("32bit I/O", rval, use_upper); 3966 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 3967 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 3968 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 3969 limit |= 0x00000fff; 3970 3971 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 3972 base_h = (rval >> 0) & 0xffff; 3973 limit_h = (rval >> 16) & 0xffff; 3974 printf(" base upper 16 bits register: 0x%04x\n", base_h); 3975 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 3976 3977 if (use_upper == 1) { 3978 base |= base_h << 16; 3979 limit |= limit_h << 16; 3980 } 3981 if (base < limit) { 3982 if (use_upper == 1) 3983 printf(" range: 0x%08x-0x%08x\n", base, limit); 3984 else 3985 printf(" range: 0x%04x-0x%04x\n", base, limit); 3986 } else 3987 printf(" range: not set\n"); 3988 3989 /* Non-prefetchable memory region */ 3990 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 3991 printf(" Memory region:\n"); 3992 printf(" base register: 0x%04x\n", 3993 (rval >> 0) & 0xffff); 3994 printf(" limit register: 0x%04x\n", 3995 (rval >> 16) & 0xffff); 3996 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 3997 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 3998 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 3999 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 4000 if (base < limit) 4001 printf(" range: 0x%08x-0x%08x\n", base, limit); 4002 else 4003 printf(" range: not set\n"); 4004 4005 /* Prefetchable memory region */ 4006 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 4007 printf(" Prefetchable memory region:\n"); 4008 printf(" base register: 0x%04x\n", 4009 (rval >> 0) & 0xffff); 4010 printf(" limit register: 0x%04x\n", 4011 (rval >> 16) & 0xffff); 4012 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 4013 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 4014 printf(" base upper 32 bits register: 0x%08x\n", 4015 base_h); 4016 printf(" limit upper 32 bits register: 0x%08x\n", 4017 limit_h); 4018 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 4019 use_upper = 1; 4020 else 4021 use_upper = 0; 4022 onoff("64bit memory address", rval, use_upper); 4023 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 4024 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 4025 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 4026 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 4027 if (use_upper == 1) { 4028 pbase |= (uint64_t)base_h << 32; 4029 plimit |= (uint64_t)limit_h << 32; 4030 } 4031 if (pbase < plimit) { 4032 if (use_upper == 1) 4033 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 4034 "\n", pbase, plimit); 4035 else 4036 printf(" range: 0x%08x-0x%08x\n", 4037 (uint32_t)pbase, (uint32_t)plimit); 4038 } else 4039 printf(" range: not set\n"); 4040 4041 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4042 printf(" Capability list pointer: 0x%02x\n", 4043 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4044 else 4045 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4046 4047 /* XXX */ 4048 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 4049 4050 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4051 printf(" Interrupt line: 0x%02x\n", 4052 (rval >> 0) & 0xff); 4053 printf(" Interrupt pin: 0x%02x ", 4054 (rval >> 8) & 0xff); 4055 switch ((rval >> 8) & 0xff) { 4056 case PCI_INTERRUPT_PIN_NONE: 4057 printf("(none)"); 4058 break; 4059 case PCI_INTERRUPT_PIN_A: 4060 printf("(pin A)"); 4061 break; 4062 case PCI_INTERRUPT_PIN_B: 4063 printf("(pin B)"); 4064 break; 4065 case PCI_INTERRUPT_PIN_C: 4066 printf("(pin C)"); 4067 break; 4068 case PCI_INTERRUPT_PIN_D: 4069 printf("(pin D)"); 4070 break; 4071 default: 4072 printf("(? ? ?)"); 4073 break; 4074 } 4075 printf("\n"); 4076 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 4077 & PCI_BRIDGE_CONTROL_MASK; 4078 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 4079 onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE); 4080 onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR); 4081 onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA); 4082 onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA); 4083 onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT); 4084 onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR); 4085 onoff("Fast back-to-back capable", rval,PCI_BRIDGE_CONTROL_SECFASTB2B); 4086 } 4087 4088 static void 4089 pci_conf_print_type2( 4090 #ifdef _KERNEL 4091 pci_chipset_tag_t pc, pcitag_t tag, 4092 #endif 4093 const pcireg_t *regs 4094 #ifdef _KERNEL 4095 , int sizebars 4096 #endif 4097 ) 4098 { 4099 pcireg_t rval; 4100 4101 /* 4102 * XXX these need to be printed in more detail, need to be 4103 * XXX checked against specs/docs, etc. 4104 * 4105 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 4106 * controller chip documentation, and may not be correct with 4107 * respect to various standards. (XXX) 4108 */ 4109 4110 #ifdef _KERNEL 4111 pci_conf_print_bar(pc, tag, regs, 0x10, 4112 "CardBus socket/ExCA registers", sizebars); 4113 #else 4114 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 4115 #endif 4116 4117 /* Capability list pointer and secondary status register */ 4118 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 4119 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4120 printf(" Capability list pointer: 0x%02x\n", 4121 PCI_CAPLIST_PTR(rval)); 4122 else 4123 printf(" Reserved @ 0x14: 0x%04x\n", 4124 (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0))); 4125 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 4126 4127 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4128 printf(" PCI bus number: 0x%02x\n", 4129 (rval >> 0) & 0xff); 4130 printf(" CardBus bus number: 0x%02x\n", 4131 (rval >> 8) & 0xff); 4132 printf(" Subordinate bus number: 0x%02x\n", 4133 (rval >> 16) & 0xff); 4134 printf(" CardBus latency timer: 0x%02x\n", 4135 (rval >> 24) & 0xff); 4136 4137 /* XXX Print more prettily */ 4138 printf(" CardBus memory region 0:\n"); 4139 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 4140 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 4141 printf(" CardBus memory region 1:\n"); 4142 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 4143 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 4144 printf(" CardBus I/O region 0:\n"); 4145 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 4146 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 4147 printf(" CardBus I/O region 1:\n"); 4148 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 4149 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 4150 4151 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4152 printf(" Interrupt line: 0x%02x\n", 4153 (rval >> 0) & 0xff); 4154 printf(" Interrupt pin: 0x%02x ", 4155 (rval >> 8) & 0xff); 4156 switch ((rval >> 8) & 0xff) { 4157 case PCI_INTERRUPT_PIN_NONE: 4158 printf("(none)"); 4159 break; 4160 case PCI_INTERRUPT_PIN_A: 4161 printf("(pin A)"); 4162 break; 4163 case PCI_INTERRUPT_PIN_B: 4164 printf("(pin B)"); 4165 break; 4166 case PCI_INTERRUPT_PIN_C: 4167 printf("(pin C)"); 4168 break; 4169 case PCI_INTERRUPT_PIN_D: 4170 printf("(pin D)"); 4171 break; 4172 default: 4173 printf("(? ? ?)"); 4174 break; 4175 } 4176 printf("\n"); 4177 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 4178 printf(" Bridge control register: 0x%04x\n", rval); 4179 onoff("Parity error response", rval, __BIT(0)); 4180 onoff("SERR# enable", rval, __BIT(1)); 4181 onoff("ISA enable", rval, __BIT(2)); 4182 onoff("VGA enable", rval, __BIT(3)); 4183 onoff("Master abort mode", rval, __BIT(5)); 4184 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 4185 onoff("Functional interrupts routed by ExCA registers", rval, 4186 __BIT(7)); 4187 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 4188 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 4189 onoff("Write posting enable", rval, __BIT(10)); 4190 4191 rval = regs[o2i(0x40)]; 4192 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4193 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4194 4195 #ifdef _KERNEL 4196 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 4197 sizebars); 4198 #else 4199 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 4200 #endif 4201 } 4202 4203 void 4204 pci_conf_print( 4205 #ifdef _KERNEL 4206 pci_chipset_tag_t pc, pcitag_t tag, 4207 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 4208 #else 4209 int pcifd, u_int bus, u_int dev, u_int func 4210 #endif 4211 ) 4212 { 4213 pcireg_t regs[o2i(PCI_EXTCONF_SIZE)]; 4214 int off, capoff, endoff, hdrtype; 4215 const char *type_name; 4216 #ifdef _KERNEL 4217 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, 4218 int); 4219 int sizebars; 4220 #else 4221 void (*type_printfn)(const pcireg_t *); 4222 #endif 4223 4224 printf("PCI configuration registers:\n"); 4225 4226 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 4227 #ifdef _KERNEL 4228 regs[o2i(off)] = pci_conf_read(pc, tag, off); 4229 #else 4230 if (pcibus_conf_read(pcifd, bus, dev, func, off, 4231 ®s[o2i(off)]) == -1) 4232 regs[o2i(off)] = 0; 4233 #endif 4234 } 4235 4236 #ifdef _KERNEL 4237 sizebars = 1; 4238 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 4239 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 4240 sizebars = 0; 4241 #endif 4242 4243 /* common header */ 4244 printf(" Common header:\n"); 4245 pci_conf_print_regs(regs, 0, 16); 4246 4247 printf("\n"); 4248 #ifdef _KERNEL 4249 pci_conf_print_common(pc, tag, regs); 4250 #else 4251 pci_conf_print_common(regs); 4252 #endif 4253 printf("\n"); 4254 4255 /* type-dependent header */ 4256 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 4257 switch (hdrtype) { /* XXX make a table, eventually */ 4258 case 0: 4259 /* Standard device header */ 4260 type_name = "\"normal\" device"; 4261 type_printfn = &pci_conf_print_type0; 4262 capoff = PCI_CAPLISTPTR_REG; 4263 endoff = 64; 4264 break; 4265 case 1: 4266 /* PCI-PCI bridge header */ 4267 type_name = "PCI-PCI bridge"; 4268 type_printfn = &pci_conf_print_type1; 4269 capoff = PCI_CAPLISTPTR_REG; 4270 endoff = 64; 4271 break; 4272 case 2: 4273 /* PCI-CardBus bridge header */ 4274 type_name = "PCI-CardBus bridge"; 4275 type_printfn = &pci_conf_print_type2; 4276 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 4277 endoff = 72; 4278 break; 4279 default: 4280 type_name = NULL; 4281 type_printfn = 0; 4282 capoff = -1; 4283 endoff = 64; 4284 break; 4285 } 4286 printf(" Type %d ", hdrtype); 4287 if (type_name != NULL) 4288 printf("(%s) ", type_name); 4289 printf("header:\n"); 4290 pci_conf_print_regs(regs, 16, endoff); 4291 printf("\n"); 4292 if (type_printfn) { 4293 #ifdef _KERNEL 4294 (*type_printfn)(pc, tag, regs, sizebars); 4295 #else 4296 (*type_printfn)(regs); 4297 #endif 4298 } else 4299 printf(" Don't know how to pretty-print type %d header.\n", 4300 hdrtype); 4301 printf("\n"); 4302 4303 /* capability list, if present */ 4304 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4305 && (capoff > 0)) { 4306 #ifdef _KERNEL 4307 pci_conf_print_caplist(pc, tag, regs, capoff); 4308 #else 4309 pci_conf_print_caplist(regs, capoff); 4310 #endif 4311 printf("\n"); 4312 } 4313 4314 /* device-dependent header */ 4315 printf(" Device-dependent header:\n"); 4316 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 4317 printf("\n"); 4318 #ifdef _KERNEL 4319 if (printfn) 4320 (*printfn)(pc, tag, regs); 4321 else 4322 printf(" Don't know how to pretty-print device-dependent header.\n"); 4323 printf("\n"); 4324 #endif /* _KERNEL */ 4325 4326 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 4327 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 4328 return; 4329 4330 #ifdef _KERNEL 4331 pci_conf_print_extcaplist(pc, tag, regs, capoff); 4332 #else 4333 pci_conf_print_extcaplist(regs, capoff); 4334 #endif 4335 printf("\n"); 4336 4337 /* Extended Configuration Space, if present */ 4338 printf(" Extended Configuration Space:\n"); 4339 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 4340 } 4341
Indexes created Fri Sep 26 20:09:58 GMT 2025