pci_subr.c revision 1.166
1 /* $NetBSD: pci_subr.c,v 1.166 2017/03/14 08:27:13 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.166 2017/03/14 08:27:13 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdarg.h> 58 #include <stdbool.h> 59 #include <stdio.h> 60 #include <stdlib.h> 61 #include <string.h> 62 #endif 63 64 #include <dev/pci/pcireg.h> 65 #ifdef _KERNEL 66 #include <dev/pci/pcivar.h> 67 #else 68 #include <dev/pci/pci_verbose.h> 69 #include <dev/pci/pcidevs.h> 70 #include <dev/pci/pcidevs_data.h> 71 #endif 72 73 static int pci_conf_find_cap(const pcireg_t *, int, unsigned int, int *); 74 75 /* 76 * Descriptions of known PCI classes and subclasses. 77 * 78 * Subclasses are described in the same way as classes, but have a 79 * NULL subclass pointer. 80 */ 81 struct pci_class { 82 const char *name; 83 u_int val; /* as wide as pci_{,sub}class_t */ 84 const struct pci_class *subclasses; 85 }; 86 87 /* 88 * Class 0x00. 89 * Before rev. 2.0. 90 */ 91 static const struct pci_class pci_subclass_prehistoric[] = { 92 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 93 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 94 { NULL, 0, NULL, }, 95 }; 96 97 /* 98 * Class 0x01. 99 * Mass storage controller 100 */ 101 102 /* ATA programming interface */ 103 static const struct pci_class pci_interface_ata[] = { 104 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 105 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 106 { NULL, 0, NULL, }, 107 }; 108 109 /* SATA programming interface */ 110 static const struct pci_class pci_interface_sata[] = { 111 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 112 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 113 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 114 { NULL, 0, NULL, }, 115 }; 116 117 /* Flash programming interface */ 118 static const struct pci_class pci_interface_nvm[] = { 119 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 120 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 121 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 122 { NULL, 0, NULL, }, 123 }; 124 125 /* Subclasses */ 126 static const struct pci_class pci_subclass_mass_storage[] = { 127 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 128 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 129 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 130 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 131 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 132 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 133 pci_interface_ata, }, 134 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 135 pci_interface_sata, }, 136 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 137 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 138 pci_interface_nvm, }, 139 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 140 { NULL, 0, NULL, }, 141 }; 142 143 /* 144 * Class 0x02. 145 * Network controller. 146 */ 147 static const struct pci_class pci_subclass_network[] = { 148 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 149 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 150 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 151 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 152 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 153 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 154 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 155 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 156 { NULL, 0, NULL, }, 157 }; 158 159 /* 160 * Class 0x03. 161 * Display controller. 162 */ 163 164 /* VGA programming interface */ 165 static const struct pci_class pci_interface_vga[] = { 166 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 167 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 168 { NULL, 0, NULL, }, 169 }; 170 /* Subclasses */ 171 static const struct pci_class pci_subclass_display[] = { 172 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 173 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 174 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 175 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 176 { NULL, 0, NULL, }, 177 }; 178 179 /* 180 * Class 0x04. 181 * Multimedia device. 182 */ 183 static const struct pci_class pci_subclass_multimedia[] = { 184 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 185 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 186 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 187 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 188 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 189 { NULL, 0, NULL, }, 190 }; 191 192 /* 193 * Class 0x05. 194 * Memory controller. 195 */ 196 static const struct pci_class pci_subclass_memory[] = { 197 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 198 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 199 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 200 { NULL, 0, NULL, }, 201 }; 202 203 /* 204 * Class 0x06. 205 * Bridge device. 206 */ 207 208 /* PCI bridge programming interface */ 209 static const struct pci_class pci_interface_pcibridge[] = { 210 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 211 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 212 { NULL, 0, NULL, }, 213 }; 214 215 /* Semi-transparent PCI-to-PCI bridge programming interface */ 216 static const struct pci_class pci_interface_stpci[] = { 217 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 218 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 219 { NULL, 0, NULL, }, 220 }; 221 222 /* Advanced Switching programming interface */ 223 static const struct pci_class pci_interface_advsw[] = { 224 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 225 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 226 { NULL, 0, NULL, }, 227 }; 228 229 /* Subclasses */ 230 static const struct pci_class pci_subclass_bridge[] = { 231 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 232 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 233 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 234 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 235 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 236 pci_interface_pcibridge, }, 237 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 238 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 239 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 240 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 241 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 242 pci_interface_stpci, }, 243 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 244 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 245 pci_interface_advsw, }, 246 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 247 { NULL, 0, NULL, }, 248 }; 249 250 /* 251 * Class 0x07. 252 * Simple communications controller. 253 */ 254 255 /* Serial controller programming interface */ 256 static const struct pci_class pci_interface_serial[] = { 257 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 258 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 259 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 260 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 261 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 262 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 263 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 264 { NULL, 0, NULL, }, 265 }; 266 267 /* Parallel controller programming interface */ 268 static const struct pci_class pci_interface_parallel[] = { 269 { "", PCI_INTERFACE_PARALLEL, NULL,}, 270 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 271 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 272 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 273 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 274 { NULL, 0, NULL,}, 275 }; 276 277 /* Modem programming interface */ 278 static const struct pci_class pci_interface_modem[] = { 279 { "", PCI_INTERFACE_MODEM, NULL,}, 280 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 281 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 282 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 283 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 284 { NULL, 0, NULL,}, 285 }; 286 287 /* Subclasses */ 288 static const struct pci_class pci_subclass_communications[] = { 289 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 290 pci_interface_serial, }, 291 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 292 pci_interface_parallel, }, 293 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 294 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 295 pci_interface_modem, }, 296 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 297 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 298 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 299 { NULL, 0, NULL,}, 300 }; 301 302 /* 303 * Class 0x08. 304 * Base system peripheral. 305 */ 306 307 /* PIC programming interface */ 308 static const struct pci_class pci_interface_pic[] = { 309 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 310 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 311 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 312 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 313 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 314 { NULL, 0, NULL, }, 315 }; 316 317 /* DMA programming interface */ 318 static const struct pci_class pci_interface_dma[] = { 319 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 320 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 321 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 322 { NULL, 0, NULL, }, 323 }; 324 325 /* Timer programming interface */ 326 static const struct pci_class pci_interface_tmr[] = { 327 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 328 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 329 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 330 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 331 { NULL, 0, NULL, }, 332 }; 333 334 /* RTC programming interface */ 335 static const struct pci_class pci_interface_rtc[] = { 336 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 337 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 338 { NULL, 0, NULL, }, 339 }; 340 341 /* Subclasses */ 342 static const struct pci_class pci_subclass_system[] = { 343 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 344 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 345 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 346 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 347 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 348 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 349 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 350 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 351 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 352 { NULL, 0, NULL, }, 353 }; 354 355 /* 356 * Class 0x09. 357 * Input device. 358 */ 359 360 /* Gameport programming interface */ 361 static const struct pci_class pci_interface_game[] = { 362 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 363 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 364 { NULL, 0, NULL, }, 365 }; 366 367 /* Subclasses */ 368 static const struct pci_class pci_subclass_input[] = { 369 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 370 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 371 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 372 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 373 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 374 pci_interface_game, }, 375 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 376 { NULL, 0, NULL, }, 377 }; 378 379 /* 380 * Class 0x0a. 381 * Docking station. 382 */ 383 static const struct pci_class pci_subclass_dock[] = { 384 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 385 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 386 { NULL, 0, NULL, }, 387 }; 388 389 /* 390 * Class 0x0b. 391 * Processor. 392 */ 393 static const struct pci_class pci_subclass_processor[] = { 394 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 395 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 396 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 397 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 398 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 399 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 400 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 401 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 402 { NULL, 0, NULL, }, 403 }; 404 405 /* 406 * Class 0x0c. 407 * Serial bus controller. 408 */ 409 410 /* IEEE1394 programming interface */ 411 static const struct pci_class pci_interface_ieee1394[] = { 412 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 413 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 414 { NULL, 0, NULL,}, 415 }; 416 417 /* USB programming interface */ 418 static const struct pci_class pci_interface_usb[] = { 419 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 420 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 421 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 422 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 423 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 424 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 425 { NULL, 0, NULL, }, 426 }; 427 428 /* IPMI programming interface */ 429 static const struct pci_class pci_interface_ipmi[] = { 430 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 431 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 432 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 433 { NULL, 0, NULL,}, 434 }; 435 436 /* Subclasses */ 437 static const struct pci_class pci_subclass_serialbus[] = { 438 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 439 pci_interface_ieee1394, }, 440 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 441 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 442 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 443 pci_interface_usb, }, 444 /* XXX Fiber Channel/_FIBRECHANNEL */ 445 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 446 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 447 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 448 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 449 pci_interface_ipmi, }, 450 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 451 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 452 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 453 { NULL, 0, NULL, }, 454 }; 455 456 /* 457 * Class 0x0d. 458 * Wireless Controller. 459 */ 460 static const struct pci_class pci_subclass_wireless[] = { 461 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 462 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 463 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 464 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 465 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 466 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 467 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 468 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 469 { NULL, 0, NULL, }, 470 }; 471 472 /* 473 * Class 0x0e. 474 * Intelligent IO controller. 475 */ 476 477 /* Intelligent IO programming interface */ 478 static const struct pci_class pci_interface_i2o[] = { 479 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 480 { NULL, 0, NULL,}, 481 }; 482 483 /* Subclasses */ 484 static const struct pci_class pci_subclass_i2o[] = { 485 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 486 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 487 { NULL, 0, NULL, }, 488 }; 489 490 /* 491 * Class 0x0f. 492 * Satellite communication controller. 493 */ 494 static const struct pci_class pci_subclass_satcom[] = { 495 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 496 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 497 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 498 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 499 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 500 { NULL, 0, NULL, }, 501 }; 502 503 /* 504 * Class 0x10. 505 * Encryption/Decryption controller. 506 */ 507 static const struct pci_class pci_subclass_crypto[] = { 508 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 509 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 510 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 511 { NULL, 0, NULL, }, 512 }; 513 514 /* 515 * Class 0x11. 516 * Data aquuisition and signal processing controller. 517 */ 518 static const struct pci_class pci_subclass_dasp[] = { 519 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 520 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 521 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 522 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 523 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 524 { NULL, 0, NULL, }, 525 }; 526 527 /* List of classes */ 528 static const struct pci_class pci_classes[] = { 529 { "prehistoric", PCI_CLASS_PREHISTORIC, 530 pci_subclass_prehistoric, }, 531 { "mass storage", PCI_CLASS_MASS_STORAGE, 532 pci_subclass_mass_storage, }, 533 { "network", PCI_CLASS_NETWORK, 534 pci_subclass_network, }, 535 { "display", PCI_CLASS_DISPLAY, 536 pci_subclass_display, }, 537 { "multimedia", PCI_CLASS_MULTIMEDIA, 538 pci_subclass_multimedia, }, 539 { "memory", PCI_CLASS_MEMORY, 540 pci_subclass_memory, }, 541 { "bridge", PCI_CLASS_BRIDGE, 542 pci_subclass_bridge, }, 543 { "communications", PCI_CLASS_COMMUNICATIONS, 544 pci_subclass_communications, }, 545 { "system", PCI_CLASS_SYSTEM, 546 pci_subclass_system, }, 547 { "input", PCI_CLASS_INPUT, 548 pci_subclass_input, }, 549 { "dock", PCI_CLASS_DOCK, 550 pci_subclass_dock, }, 551 { "processor", PCI_CLASS_PROCESSOR, 552 pci_subclass_processor, }, 553 { "serial bus", PCI_CLASS_SERIALBUS, 554 pci_subclass_serialbus, }, 555 { "wireless", PCI_CLASS_WIRELESS, 556 pci_subclass_wireless, }, 557 { "I2O", PCI_CLASS_I2O, 558 pci_subclass_i2o, }, 559 { "satellite comm", PCI_CLASS_SATCOM, 560 pci_subclass_satcom, }, 561 { "crypto", PCI_CLASS_CRYPTO, 562 pci_subclass_crypto, }, 563 { "DASP", PCI_CLASS_DASP, 564 pci_subclass_dasp, }, 565 { "processing accelerators", PCI_CLASS_ACCEL, 566 NULL, }, 567 { "non-essential instrumentation", PCI_CLASS_INSTRUMENT, 568 NULL, }, 569 { "undefined", PCI_CLASS_UNDEFINED, 570 NULL, }, 571 { NULL, 0, 572 NULL, }, 573 }; 574 575 DEV_VERBOSE_DEFINE(pci); 576 577 /* 578 * Append a formatted string to dest without writing more than len 579 * characters (including the trailing NUL character). dest and len 580 * are updated for use in subsequent calls to snappendf(). 581 * 582 * Returns 0 on success, a negative value if vnsprintf() fails, or 583 * a positive value if the dest buffer would have overflowed. 584 */ 585 586 static int __printflike(3,4) 587 snappendf(char **dest, size_t *len, const char * restrict fmt, ...) 588 { 589 va_list ap; 590 int count; 591 592 va_start(ap, fmt); 593 count = vsnprintf(*dest, *len, fmt, ap); 594 va_end(ap); 595 596 /* Let vsnprintf() errors bubble up to caller */ 597 if (count < 0 || *len == 0) 598 return count; 599 600 /* Handle overflow */ 601 if ((size_t)count >= *len) { 602 *dest += *len - 1; 603 *len = 1; 604 return 1; 605 } 606 607 /* Update dest & len to point at trailing NUL */ 608 *dest += count; 609 *len -= count; 610 611 return 0; 612 } 613 614 void 615 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 616 size_t l) 617 { 618 pci_class_t class; 619 pci_subclass_t subclass; 620 pci_interface_t interface; 621 pci_revision_t revision; 622 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 623 const struct pci_class *classp, *subclassp, *interfacep; 624 625 class = PCI_CLASS(class_reg); 626 subclass = PCI_SUBCLASS(class_reg); 627 interface = PCI_INTERFACE(class_reg); 628 revision = PCI_REVISION(class_reg); 629 630 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 631 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 632 PCI_PRODUCT(id_reg)); 633 634 classp = pci_classes; 635 while (classp->name != NULL) { 636 if (class == classp->val) 637 break; 638 classp++; 639 } 640 641 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 642 while (subclassp && subclassp->name != NULL) { 643 if (subclass == subclassp->val) 644 break; 645 subclassp++; 646 } 647 648 interfacep = (subclassp && subclassp->name != NULL) ? 649 subclassp->subclasses : NULL; 650 while (interfacep && interfacep->name != NULL) { 651 if (interface == interfacep->val) 652 break; 653 interfacep++; 654 } 655 656 (void)snappendf(&cp, &l, "%s %s", vendor, product); 657 if (showclass) { 658 (void)snappendf(&cp, &l, " ("); 659 if (classp->name == NULL) 660 (void)snappendf(&cp, &l, 661 "class 0x%02x, subclass 0x%02x", 662 class, subclass); 663 else { 664 if (subclassp == NULL || subclassp->name == NULL) 665 (void)snappendf(&cp, &l, 666 "%s, subclass 0x%02x", 667 classp->name, subclass); 668 else 669 (void)snappendf(&cp, &l, "%s %s", 670 subclassp->name, classp->name); 671 } 672 if ((interfacep == NULL) || (interfacep->name == NULL)) { 673 if (interface != 0) 674 (void)snappendf(&cp, &l, ", interface 0x%02x", 675 interface); 676 } else if (strncmp(interfacep->name, "", 1) != 0) 677 (void)snappendf(&cp, &l, ", %s", interfacep->name); 678 if (revision != 0) 679 (void)snappendf(&cp, &l, ", revision 0x%02x", revision); 680 (void)snappendf(&cp, &l, ")"); 681 } 682 } 683 684 #ifdef _KERNEL 685 void 686 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 687 const char *known, int addrev) 688 { 689 char devinfo[256]; 690 691 if (known) { 692 aprint_normal(": %s", known); 693 if (addrev) 694 aprint_normal(" (rev. 0x%02x)", 695 PCI_REVISION(pa->pa_class)); 696 aprint_normal("\n"); 697 } else { 698 pci_devinfo(pa->pa_id, pa->pa_class, 0, 699 devinfo, sizeof(devinfo)); 700 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 701 PCI_REVISION(pa->pa_class)); 702 } 703 if (naive) 704 aprint_naive(": %s\n", naive); 705 else 706 aprint_naive("\n"); 707 } 708 #endif 709 710 /* 711 * Print out most of the PCI configuration registers. Typically used 712 * in a device attach routine like this: 713 * 714 * #ifdef MYDEV_DEBUG 715 * printf("%s: ", device_xname(sc->sc_dev)); 716 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 717 * #endif 718 */ 719 720 #define i2o(i) ((i) * 4) 721 #define o2i(o) ((o) / 4) 722 #define onoff2(str, rval, bit, onstr, offstr) \ 723 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 724 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 725 726 static void 727 pci_conf_print_common( 728 #ifdef _KERNEL 729 pci_chipset_tag_t pc, pcitag_t tag, 730 #endif 731 const pcireg_t *regs) 732 { 733 pci_class_t class; 734 pci_subclass_t subclass; 735 pci_interface_t interface; 736 pci_revision_t revision; 737 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 738 const struct pci_class *classp, *subclassp, *interfacep; 739 const char *name; 740 pcireg_t rval; 741 unsigned int num; 742 743 rval = regs[o2i(PCI_CLASS_REG)]; 744 class = PCI_CLASS(rval); 745 subclass = PCI_SUBCLASS(rval); 746 interface = PCI_INTERFACE(rval); 747 revision = PCI_REVISION(rval); 748 749 rval = regs[o2i(PCI_ID_REG)]; 750 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 751 if (name) 752 printf(" Vendor Name: %s (0x%04x)\n", name, 753 PCI_VENDOR(rval)); 754 else 755 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 756 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 757 PCI_PRODUCT(rval)); 758 if (name) 759 printf(" Device Name: %s (0x%04x)\n", name, 760 PCI_PRODUCT(rval)); 761 else 762 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 763 764 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 765 766 printf(" Command register: 0x%04x\n", rval & 0xffff); 767 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 768 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 769 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 770 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 771 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 772 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 773 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 774 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 775 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 776 onoff("Fast back-to-back transactions", rval, 777 PCI_COMMAND_BACKTOBACK_ENABLE); 778 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 779 780 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 781 onoff("Immediate Readness", rval, PCI_STATUS_IMMD_READNESS); 782 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 783 "inactive"); 784 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 785 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 786 onoff("User Definable Features (UDF) support", rval, 787 PCI_STATUS_UDF_SUPPORT); 788 onoff("Fast back-to-back capable", rval, 789 PCI_STATUS_BACKTOBACK_SUPPORT); 790 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 791 792 printf(" DEVSEL timing: "); 793 switch (rval & PCI_STATUS_DEVSEL_MASK) { 794 case PCI_STATUS_DEVSEL_FAST: 795 printf("fast"); 796 break; 797 case PCI_STATUS_DEVSEL_MEDIUM: 798 printf("medium"); 799 break; 800 case PCI_STATUS_DEVSEL_SLOW: 801 printf("slow"); 802 break; 803 default: 804 printf("unknown/reserved"); /* XXX */ 805 break; 806 } 807 printf(" (0x%x)\n", __SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK)); 808 809 onoff("Slave signaled Target Abort", rval, 810 PCI_STATUS_TARGET_TARGET_ABORT); 811 onoff("Master received Target Abort", rval, 812 PCI_STATUS_MASTER_TARGET_ABORT); 813 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 814 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 815 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 816 817 rval = regs[o2i(PCI_CLASS_REG)]; 818 for (classp = pci_classes; classp->name != NULL; classp++) { 819 if (class == classp->val) 820 break; 821 } 822 823 /* 824 * ECN: Change Root Complex Event Collector Class Code 825 * Old RCEC has subclass 0x06. It's the same as IOMMU. Read the type 826 * in PCIe extend capability to know whether it's RCEC or IOMMU. 827 */ 828 if ((class == PCI_CLASS_SYSTEM) 829 && (subclass == PCI_SUBCLASS_SYSTEM_IOMMU)) { 830 int pcie_capoff; 831 pcireg_t reg; 832 833 if (pci_conf_find_cap(regs, PCI_CAPLISTPTR_REG, 834 PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 835 reg = regs[o2i(pcie_capoff + PCIE_XCAP)]; 836 if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_ROOT_EVNTC) 837 subclass = PCI_SUBCLASS_SYSTEM_RCEC; 838 } 839 } 840 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 841 while (subclassp && subclassp->name != NULL) { 842 if (subclass == subclassp->val) 843 break; 844 subclassp++; 845 } 846 847 interfacep = (subclassp && subclassp->name != NULL) ? 848 subclassp->subclasses : NULL; 849 while (interfacep && interfacep->name != NULL) { 850 if (interface == interfacep->val) 851 break; 852 interfacep++; 853 } 854 855 if (classp->name != NULL) 856 printf(" Class Name: %s (0x%02x)\n", classp->name, class); 857 else 858 printf(" Class ID: 0x%02x\n", class); 859 if (subclassp != NULL && subclassp->name != NULL) 860 printf(" Subclass Name: %s (0x%02x)\n", 861 subclassp->name, PCI_SUBCLASS(rval)); 862 else 863 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 864 if ((interfacep != NULL) && (interfacep->name != NULL) 865 && (strncmp(interfacep->name, "", 1) != 0)) 866 printf(" Interface Name: %s (0x%02x)\n", 867 interfacep->name, interface); 868 else 869 printf(" Interface: 0x%02x\n", interface); 870 printf(" Revision ID: 0x%02x\n", revision); 871 872 rval = regs[o2i(PCI_BHLC_REG)]; 873 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 874 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 875 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 876 PCI_HDRTYPE(rval)); 877 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 878 num = PCI_CACHELINE(rval); 879 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 880 } 881 882 static int 883 pci_conf_print_bar( 884 #ifdef _KERNEL 885 pci_chipset_tag_t pc, pcitag_t tag, 886 #endif 887 const pcireg_t *regs, int reg, const char *name 888 #ifdef _KERNEL 889 , int sizebar 890 #endif 891 ) 892 { 893 int width; 894 pcireg_t rval, rval64h; 895 #ifdef _KERNEL 896 int s; 897 pcireg_t mask, mask64h; 898 #endif 899 900 width = 4; 901 902 /* 903 * Section 6.2.5.1, `Address Maps', tells us that: 904 * 905 * 1) The builtin software should have already mapped the 906 * device in a reasonable way. 907 * 908 * 2) A device which wants 2^n bytes of memory will hardwire 909 * the bottom n bits of the address to 0. As recommended, 910 * we write all 1s and see what we get back. 911 */ 912 913 rval = regs[o2i(reg)]; 914 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 915 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 916 rval64h = regs[o2i(reg + 4)]; 917 width = 8; 918 } else 919 rval64h = 0; 920 921 #ifdef _KERNEL 922 /* XXX don't size unknown memory type? */ 923 if (rval != 0 && sizebar) { 924 /* 925 * The following sequence seems to make some devices 926 * (e.g. host bus bridges, which don't normally 927 * have their space mapped) very unhappy, to 928 * the point of crashing the system. 929 * 930 * Therefore, if the mapping register is zero to 931 * start out with, don't bother trying. 932 */ 933 s = splhigh(); 934 pci_conf_write(pc, tag, reg, 0xffffffff); 935 mask = pci_conf_read(pc, tag, reg); 936 pci_conf_write(pc, tag, reg, rval); 937 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 938 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 939 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 940 mask64h = pci_conf_read(pc, tag, reg + 4); 941 pci_conf_write(pc, tag, reg + 4, rval64h); 942 } else 943 mask64h = 0; 944 splx(s); 945 } else 946 mask = mask64h = 0; 947 #endif /* _KERNEL */ 948 949 printf(" Base address register at 0x%02x", reg); 950 if (name) 951 printf(" (%s)", name); 952 printf("\n "); 953 if (rval == 0) { 954 printf("not implemented(?)\n"); 955 return width; 956 } 957 printf("type: "); 958 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 959 const char *type, *prefetch; 960 961 switch (PCI_MAPREG_MEM_TYPE(rval)) { 962 case PCI_MAPREG_MEM_TYPE_32BIT: 963 type = "32-bit"; 964 break; 965 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 966 type = "32-bit-1M"; 967 break; 968 case PCI_MAPREG_MEM_TYPE_64BIT: 969 type = "64-bit"; 970 break; 971 default: 972 type = "unknown (XXX)"; 973 break; 974 } 975 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 976 prefetch = ""; 977 else 978 prefetch = "non"; 979 printf("%s %sprefetchable memory\n", type, prefetch); 980 switch (PCI_MAPREG_MEM_TYPE(rval)) { 981 case PCI_MAPREG_MEM_TYPE_64BIT: 982 printf(" base: 0x%016llx, ", 983 PCI_MAPREG_MEM64_ADDR( 984 ((((long long) rval64h) << 32) | rval))); 985 #ifdef _KERNEL 986 if (sizebar) 987 printf("size: 0x%016llx", 988 PCI_MAPREG_MEM64_SIZE( 989 ((((long long) mask64h) << 32) | mask))); 990 else 991 #endif /* _KERNEL */ 992 printf("not sized"); 993 printf("\n"); 994 break; 995 case PCI_MAPREG_MEM_TYPE_32BIT: 996 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 997 default: 998 printf(" base: 0x%08x, ", 999 PCI_MAPREG_MEM_ADDR(rval)); 1000 #ifdef _KERNEL 1001 if (sizebar) 1002 printf("size: 0x%08x", 1003 PCI_MAPREG_MEM_SIZE(mask)); 1004 else 1005 #endif /* _KERNEL */ 1006 printf("not sized"); 1007 printf("\n"); 1008 break; 1009 } 1010 } else { 1011 #ifdef _KERNEL 1012 if (sizebar) 1013 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 1014 #endif /* _KERNEL */ 1015 printf("i/o\n"); 1016 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 1017 #ifdef _KERNEL 1018 if (sizebar) 1019 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 1020 else 1021 #endif /* _KERNEL */ 1022 printf("not sized"); 1023 printf("\n"); 1024 } 1025 1026 return width; 1027 } 1028 1029 static void 1030 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 1031 { 1032 int off, needaddr, neednl; 1033 1034 needaddr = 1; 1035 neednl = 0; 1036 for (off = first; off < pastlast; off += 4) { 1037 if ((off % 16) == 0 || needaddr) { 1038 printf(" 0x%02x:", off); 1039 needaddr = 0; 1040 } 1041 printf(" 0x%08x", regs[o2i(off)]); 1042 neednl = 1; 1043 if ((off % 16) == 12) { 1044 printf("\n"); 1045 neednl = 0; 1046 } 1047 } 1048 if (neednl) 1049 printf("\n"); 1050 } 1051 1052 static const char * 1053 pci_conf_print_agp_calcycle(uint8_t cal) 1054 { 1055 1056 switch (cal) { 1057 case 0x0: 1058 return "4ms"; 1059 case 0x1: 1060 return "16ms"; 1061 case 0x2: 1062 return "64ms"; 1063 case 0x3: 1064 return "256ms"; 1065 case 0x7: 1066 return "Calibration Cycle Not Needed"; 1067 default: 1068 return "(reserved)"; 1069 } 1070 } 1071 1072 static void 1073 pci_conf_print_agp_datarate(pcireg_t reg, bool isagp3) 1074 { 1075 if (isagp3) { 1076 /* AGP 3.0 */ 1077 if (reg & AGP_MODE_V3_RATE_4x) 1078 printf("x4"); 1079 if (reg & AGP_MODE_V3_RATE_8x) 1080 printf("x8"); 1081 } else { 1082 /* AGP 2.0 */ 1083 if (reg & AGP_MODE_V2_RATE_1x) 1084 printf("x1"); 1085 if (reg & AGP_MODE_V2_RATE_2x) 1086 printf("x2"); 1087 if (reg & AGP_MODE_V2_RATE_4x) 1088 printf("x4"); 1089 } 1090 printf("\n"); 1091 } 1092 1093 static void 1094 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1095 { 1096 pcireg_t rval; 1097 bool isagp3; 1098 1099 printf("\n AGP Capabilities Register\n"); 1100 1101 rval = regs[o2i(capoff)]; 1102 printf(" Revision: %d.%d\n", 1103 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1104 1105 rval = regs[o2i(capoff + PCI_AGP_STATUS)]; 1106 printf(" Status register: 0x%04x\n", rval); 1107 printf(" RQ: %d\n", 1108 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1109 printf(" ARQSZ: %d\n", 1110 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1111 printf(" CAL cycle: %s\n", 1112 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1113 onoff("SBA", rval, AGP_MODE_SBA); 1114 onoff("htrans#", rval, AGP_MODE_HTRANS); 1115 onoff("Over 4G", rval, AGP_MODE_4G); 1116 onoff("Fast Write", rval, AGP_MODE_FW); 1117 onoff("AGP 3.0 Mode", rval, AGP_MODE_MODE_3); 1118 isagp3 = rval & AGP_MODE_MODE_3; 1119 printf(" Data Rate Support: "); 1120 pci_conf_print_agp_datarate(rval, isagp3); 1121 1122 rval = regs[o2i(capoff + PCI_AGP_COMMAND)]; 1123 printf(" Command register: 0x%08x\n", rval); 1124 printf(" PRQ: %d\n", 1125 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1126 printf(" PARQSZ: %d\n", 1127 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1128 printf(" PCAL cycle: %s\n", 1129 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1130 onoff("SBA", rval, AGP_MODE_SBA); 1131 onoff("AGP", rval, AGP_MODE_AGP); 1132 onoff("Over 4G", rval, AGP_MODE_4G); 1133 onoff("Fast Write", rval, AGP_MODE_FW); 1134 if (isagp3) { 1135 printf(" Data Rate Enable: "); 1136 /* 1137 * The Data Rate Enable bits are used only on 3.0 and the 1138 * Command register has no AGP_MODE_MODE_3 bit, so pass the 1139 * flag to print correctly. 1140 */ 1141 pci_conf_print_agp_datarate(rval, isagp3); 1142 } 1143 } 1144 1145 static const char * 1146 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1147 { 1148 1149 switch ((caps >> 6) & 7) { 1150 case 0: return "self-powered"; 1151 case 1: return "55 mA"; 1152 case 2: return "100 mA"; 1153 case 3: return "160 mA"; 1154 case 4: return "220 mA"; 1155 case 5: return "270 mA"; 1156 case 6: return "320 mA"; 1157 case 7: 1158 default: return "375 mA"; 1159 } 1160 } 1161 1162 static const char * 1163 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1164 { 1165 static const char unk[] = "unknown"; 1166 static const char *pmrev[8] = { 1167 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1168 }; 1169 if (val > 7) 1170 return unk; 1171 return pmrev[val]; 1172 } 1173 1174 static void 1175 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1176 { 1177 uint16_t caps, pmcsr; 1178 pcireg_t reg; 1179 1180 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1181 reg = regs[o2i(capoff + PCI_PMCSR)]; 1182 pmcsr = reg & 0xffff; 1183 1184 printf("\n PCI Power Management Capabilities Register\n"); 1185 1186 printf(" Capabilities register: 0x%04x\n", caps); 1187 printf(" Version: %s\n", 1188 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1189 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1190 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1191 printf(" 3.3V auxiliary current: %s\n", 1192 pci_conf_print_pcipm_cap_aux(caps)); 1193 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1194 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1195 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1196 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1197 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1198 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1199 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1200 1201 printf(" Control/status register: 0x%04x\n", pmcsr); 1202 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1203 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1204 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1205 printf(" PME# assertion: %sabled\n", 1206 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1207 printf(" Data Select: %d\n", 1208 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK)); 1209 printf(" Data Scale: %d\n", 1210 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK)); 1211 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1212 printf(" Bridge Support Extensions register: 0x%02x\n", 1213 (reg >> 16) & 0xff); 1214 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1215 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1216 printf(" Data register: 0x%02x\n", __SHIFTOUT(reg, PCI_PMCSR_DATA)); 1217 1218 } 1219 1220 /* XXX pci_conf_print_vpd_cap */ 1221 /* XXX pci_conf_print_slotid_cap */ 1222 1223 static void 1224 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1225 { 1226 uint32_t ctl, mmc, mme; 1227 1228 regs += o2i(capoff); 1229 ctl = *regs++; 1230 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1231 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1232 1233 printf("\n PCI Message Signaled Interrupt\n"); 1234 1235 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1236 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1237 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1238 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1239 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1240 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1241 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1242 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1243 onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP); 1244 onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN); 1245 printf(" Message Address %sregister: 0x%08x\n", 1246 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1247 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1248 printf(" Message Address %sregister: 0x%08x\n", 1249 "(upper) ", *regs++); 1250 } 1251 printf(" Message Data register: 0x%04x\n", *regs & 0xffff); 1252 regs++; 1253 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1254 printf(" Vector Mask register: 0x%08x\n", *regs++); 1255 printf(" Vector Pending register: 0x%08x\n", *regs++); 1256 } 1257 } 1258 1259 /* XXX pci_conf_print_cpci_hostwap_cap */ 1260 1261 /* 1262 * For both command register and status register. 1263 * The argument "idx" is index number (0 to 7). 1264 */ 1265 static int 1266 pcix_split_trans(unsigned int idx) 1267 { 1268 static int table[8] = { 1269 1, 2, 3, 4, 8, 12, 16, 32 1270 }; 1271 1272 if (idx >= __arraycount(table)) 1273 return -1; 1274 return table[idx]; 1275 } 1276 1277 static void 1278 pci_conf_print_pcix_cap_2ndbusmode(int num) 1279 { 1280 const char *maxfreq, *maxperiod; 1281 1282 printf(" Mode: "); 1283 if (num <= 0x07) 1284 printf("PCI-X Mode 1\n"); 1285 else if (num <= 0x0b) 1286 printf("PCI-X 266 (Mode 2)\n"); 1287 else 1288 printf("PCI-X 533 (Mode 2)\n"); 1289 1290 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1291 switch (num & 0x03) { 1292 default: 1293 case 0: 1294 maxfreq = "N/A"; 1295 maxperiod = "N/A"; 1296 break; 1297 case 1: 1298 maxfreq = "66MHz"; 1299 maxperiod = "15ns"; 1300 break; 1301 case 2: 1302 maxfreq = "100MHz"; 1303 maxperiod = "10ns"; 1304 break; 1305 case 3: 1306 maxfreq = "133MHz"; 1307 maxperiod = "7.5ns"; 1308 break; 1309 } 1310 printf(" Max Clock Freq: %s\n", maxfreq); 1311 printf(" Min Clock Period: %s\n", maxperiod); 1312 } 1313 1314 static void 1315 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1316 { 1317 pcireg_t reg; 1318 int isbridge; 1319 int i; 1320 1321 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1322 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1323 printf("\n PCI-X %s Capabilities Register\n", 1324 isbridge ? "Bridge" : "Non-bridge"); 1325 1326 reg = regs[o2i(capoff)]; 1327 if (isbridge != 0) { 1328 printf(" Secondary status register: 0x%04x\n", 1329 (reg & 0xffff0000) >> 16); 1330 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1331 onoff("133MHz capable", reg, PCIX_STATUS_133); 1332 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1333 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1334 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1335 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1336 pci_conf_print_pcix_cap_2ndbusmode( 1337 __SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1338 printf(" Version: 0x%x\n", 1339 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1340 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1341 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1342 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1343 } else { 1344 printf(" Command register: 0x%04x\n", 1345 (reg & 0xffff0000) >> 16); 1346 onoff("Data Parity Error Recovery", reg, 1347 PCIX_CMD_PERR_RECOVER); 1348 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1349 printf(" Maximum Burst Read Count: %u\n", 1350 PCIX_CMD_BYTECNT(reg)); 1351 printf(" Maximum Split Transactions: %d\n", 1352 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1353 >> PCIX_CMD_SPLTRANS_SHIFT)); 1354 } 1355 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1356 printf(" %sStatus register: 0x%08x\n", 1357 isbridge ? "Bridge " : "", reg); 1358 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1359 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1360 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1361 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1362 onoff("133MHz capable", reg, PCIX_STATUS_133); 1363 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1364 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1365 if (isbridge != 0) { 1366 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1367 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1368 } else { 1369 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1370 "bridge device", "simple device"); 1371 printf(" Designed max memory read byte count: %d\n", 1372 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1373 >> PCIX_STATUS_MAXB_SHIFT)); 1374 printf(" Designed max outstanding split transaction: %d\n", 1375 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1376 >> PCIX_STATUS_MAXST_SHIFT)); 1377 printf(" MAX cumulative Read Size: %u\n", 1378 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1379 onoff("Received split completion error", reg, 1380 PCIX_STATUS_SCERR); 1381 } 1382 onoff("266MHz capable", reg, PCIX_STATUS_266); 1383 onoff("533MHz capable", reg, PCIX_STATUS_533); 1384 1385 if (isbridge == 0) 1386 return; 1387 1388 /* Only for bridge */ 1389 for (i = 0; i < 2; i++) { 1390 reg = regs[o2i(capoff + PCIX_BRIDGE_UP_STCR + (4 * i))]; 1391 printf(" %s split transaction control register: 0x%08x\n", 1392 (i == 0) ? "Upstream" : "Downstream", reg); 1393 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1394 printf(" Commitment Limit: %d\n", 1395 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1396 } 1397 } 1398 1399 /* pci_conf_print_ht_slave_cap */ 1400 /* pci_conf_print_ht_host_cap */ 1401 /* pci_conf_print_ht_switch_cap */ 1402 /* pci_conf_print_ht_intr_cap */ 1403 /* pci_conf_print_ht_revid_cap */ 1404 /* pci_conf_print_ht_unitid_cap */ 1405 /* pci_conf_print_ht_extcnf_cap */ 1406 /* pci_conf_print_ht_addrmap_cap */ 1407 /* pci_conf_print_ht_msimap_cap */ 1408 1409 static void 1410 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1411 { 1412 pcireg_t val; 1413 uint32_t lo, hi; 1414 1415 /* 1416 * Print the rest of the command register bits. Others are 1417 * printed in pci_conf_print_ht_cap(). 1418 */ 1419 val = regs[o2i(capoff + PCI_HT_CMD)]; 1420 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1421 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1422 1423 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1424 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1425 printf(" Address Low register: 0x%08x\n", lo); 1426 printf(" Address high register: 0x%08x\n", hi); 1427 printf(" Address: 0x%016" PRIx64 "\n", 1428 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1429 } 1430 1431 /* pci_conf_print_ht_droute_cap */ 1432 /* pci_conf_print_ht_vcset_cap */ 1433 /* pci_conf_print_ht_retry_cap */ 1434 /* pci_conf_print_ht_x86enc_cap */ 1435 /* pci_conf_print_ht_gen3_cap */ 1436 /* pci_conf_print_ht_fle_cap */ 1437 /* pci_conf_print_ht_pm_cap */ 1438 /* pci_conf_print_ht_hnc_cap */ 1439 1440 static const struct ht_types { 1441 pcireg_t cap; 1442 const char *name; 1443 void (*printfunc)(const pcireg_t *, int); 1444 } ht_captab[] = { 1445 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1446 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1447 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1448 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1449 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1450 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1451 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1452 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1453 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1454 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1455 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1456 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1457 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1458 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1459 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1460 {PCI_HT_CAP_PM, "Power Management", NULL }, 1461 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1462 }; 1463 1464 static void 1465 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1466 { 1467 pcireg_t val, foundcap; 1468 unsigned int off; 1469 1470 val = regs[o2i(capoff + PCI_HT_CMD)]; 1471 1472 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1473 1474 printf(" Command register: 0x%04x\n", val >> 16); 1475 foundcap = PCI_HT_CAP(val); 1476 for (off = 0; off < __arraycount(ht_captab); off++) { 1477 if (ht_captab[off].cap == foundcap) 1478 break; 1479 } 1480 printf(" Capability Type: 0x%02x ", foundcap); 1481 if (off >= __arraycount(ht_captab)) { 1482 printf("(unknown)\n"); 1483 return; 1484 } 1485 printf("(%s)\n", ht_captab[off].name); 1486 if (ht_captab[off].printfunc != NULL) 1487 ht_captab[off].printfunc(regs, capoff); 1488 } 1489 1490 static void 1491 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1492 { 1493 uint16_t caps; 1494 1495 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1496 1497 printf("\n PCI Vendor Specific Capabilities Register\n"); 1498 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1499 } 1500 1501 static void 1502 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1503 { 1504 pcireg_t val; 1505 1506 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1507 1508 printf("\n Debugport Capability Register\n"); 1509 printf(" Debug base Register: 0x%04x\n", 1510 val >> PCI_DEBUG_BASER_SHIFT); 1511 printf(" port offset: 0x%04x\n", 1512 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1513 printf(" BAR number: %u\n", 1514 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1515 } 1516 1517 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1518 /* XXX pci_conf_print_hotplug_cap */ 1519 1520 static void 1521 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1522 { 1523 pcireg_t reg; 1524 1525 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1526 1527 printf("\n Subsystem ID Capability Register\n"); 1528 printf(" Subsystem ID : 0x%08x\n", reg); 1529 } 1530 1531 /* XXX pci_conf_print_agp8_cap */ 1532 /* XXX pci_conf_print_secure_cap */ 1533 1534 static void 1535 pci_print_pcie_L0s_latency(uint32_t val) 1536 { 1537 1538 switch (val) { 1539 case 0x0: 1540 printf("Less than 64ns\n"); 1541 break; 1542 case 0x1: 1543 case 0x2: 1544 case 0x3: 1545 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1546 break; 1547 case 0x4: 1548 printf("512ns to less than 1us\n"); 1549 break; 1550 case 0x5: 1551 printf("1us to less than 2us\n"); 1552 break; 1553 case 0x6: 1554 printf("2us - 4us\n"); 1555 break; 1556 case 0x7: 1557 printf("More than 4us\n"); 1558 break; 1559 } 1560 } 1561 1562 static void 1563 pci_print_pcie_L1_latency(uint32_t val) 1564 { 1565 1566 switch (val) { 1567 case 0x0: 1568 printf("Less than 1us\n"); 1569 break; 1570 case 0x6: 1571 printf("32us - 64us\n"); 1572 break; 1573 case 0x7: 1574 printf("More than 64us\n"); 1575 break; 1576 default: 1577 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1578 break; 1579 } 1580 } 1581 1582 static void 1583 pci_print_pcie_compl_timeout(uint32_t val) 1584 { 1585 1586 switch (val) { 1587 case 0x0: 1588 printf("50us to 50ms\n"); 1589 break; 1590 case 0x5: 1591 printf("16ms to 55ms\n"); 1592 break; 1593 case 0x6: 1594 printf("65ms to 210ms\n"); 1595 break; 1596 case 0x9: 1597 printf("260ms to 900ms\n"); 1598 break; 1599 case 0xa: 1600 printf("1s to 3.5s\n"); 1601 break; 1602 default: 1603 printf("unknown %u value\n", val); 1604 break; 1605 } 1606 } 1607 1608 static const char * const pcie_linkspeeds[] = {"2.5", "2.5", "5.0", "8.0"}; 1609 1610 static void 1611 pci_print_pcie_linkspeed(pcireg_t val) 1612 { 1613 1614 if (val > __arraycount(pcie_linkspeeds)) 1615 printf("unknown value (%u)\n", val); 1616 else 1617 printf("%sGT/s\n", pcie_linkspeeds[val]); 1618 } 1619 1620 static void 1621 pci_print_pcie_linkspeedvector(pcireg_t val) 1622 { 1623 unsigned int i; 1624 1625 /* Start from 0 */ 1626 for (i = 0; i < 16; i++) 1627 if (((val >> i) & 0x01) != 0) { 1628 if (i >= __arraycount(pcie_linkspeeds)) 1629 printf(" unknown vector (0x%x)", 1 << i); 1630 else 1631 printf(" %sGT/s", pcie_linkspeeds[i]); 1632 } 1633 } 1634 1635 static void 1636 pci_print_pcie_link_deemphasis(pcireg_t val) 1637 { 1638 switch (val) { 1639 case 0: 1640 printf("-6dB"); 1641 break; 1642 case 1: 1643 printf("-3.5dB"); 1644 break; 1645 default: 1646 printf("(reserved value)"); 1647 } 1648 } 1649 1650 static void 1651 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1652 { 1653 pcireg_t reg; /* for each register */ 1654 pcireg_t val; /* for each bitfield */ 1655 bool check_link = false; 1656 bool check_slot = false; 1657 bool check_rootport = false; 1658 unsigned int pciever; 1659 unsigned int i; 1660 1661 printf("\n PCI Express Capabilities Register\n"); 1662 /* Capability Register */ 1663 reg = regs[o2i(capoff)]; 1664 printf(" Capability register: 0x%04x\n", reg >> 16); 1665 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1666 printf(" Capability version: %u\n", pciever); 1667 printf(" Device type: "); 1668 switch ((reg & 0x00f00000) >> 20) { 1669 case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */ 1670 printf("PCI Express Endpoint device\n"); 1671 check_link = true; 1672 break; 1673 case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */ 1674 printf("Legacy PCI Express Endpoint device\n"); 1675 check_link = true; 1676 break; 1677 case PCIE_XCAP_TYPE_ROOT: /* 0x4 */ 1678 printf("Root Port of PCI Express Root Complex\n"); 1679 check_link = true; 1680 check_slot = true; 1681 check_rootport = true; 1682 break; 1683 case PCIE_XCAP_TYPE_UP: /* 0x5 */ 1684 printf("Upstream Port of PCI Express Switch\n"); 1685 break; 1686 case PCIE_XCAP_TYPE_DOWN: /* 0x6 */ 1687 printf("Downstream Port of PCI Express Switch\n"); 1688 check_slot = true; 1689 check_rootport = true; 1690 break; 1691 case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */ 1692 printf("PCI Express to PCI/PCI-X Bridge\n"); 1693 break; 1694 case PCIE_XCAP_TYPE_PCI2PCIE: /* 0x8 */ 1695 printf("PCI/PCI-X to PCI Express Bridge\n"); 1696 break; 1697 case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */ 1698 printf("Root Complex Integrated Endpoint\n"); 1699 break; 1700 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */ 1701 check_rootport = true; 1702 printf("Root Complex Event Collector\n"); 1703 break; 1704 default: 1705 printf("unknown\n"); 1706 break; 1707 } 1708 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1709 printf(" Interrupt Message Number: 0x%02x\n", 1710 (unsigned int)__SHIFTOUT(reg, PCIE_XCAP_IRQ)); 1711 1712 /* Device Capability Register */ 1713 reg = regs[o2i(capoff + PCIE_DCAP)]; 1714 printf(" Device Capabilities Register: 0x%08x\n", reg); 1715 printf(" Max Payload Size Supported: %u bytes max\n", 1716 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1717 printf(" Phantom Functions Supported: "); 1718 switch (__SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) { 1719 case 0x0: 1720 printf("not available\n"); 1721 break; 1722 case 0x1: 1723 printf("MSB\n"); 1724 break; 1725 case 0x2: 1726 printf("two MSB\n"); 1727 break; 1728 case 0x3: 1729 printf("All three bits\n"); 1730 break; 1731 } 1732 printf(" Extended Tag Field Supported: %dbit\n", 1733 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1734 printf(" Endpoint L0 Acceptable Latency: "); 1735 pci_print_pcie_L0s_latency(__SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY)); 1736 printf(" Endpoint L1 Acceptable Latency: "); 1737 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY)); 1738 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1739 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1740 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1741 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1742 printf(" Captured Slot Power Limit Value: %u\n", 1743 (unsigned int)__SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL)); 1744 printf(" Captured Slot Power Limit Scale: %u\n", 1745 (unsigned int)__SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE)); 1746 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1747 1748 /* Device Control Register */ 1749 reg = regs[o2i(capoff + PCIE_DCSR)]; 1750 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1751 onoff("Correctable Error Reporting Enable", reg, 1752 PCIE_DCSR_ENA_COR_ERR); 1753 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1754 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1755 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1756 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1757 printf(" Max Payload Size: %d byte\n", 1758 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD)); 1759 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1760 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1761 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1762 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1763 printf(" Max Read Request Size: %d byte\n", 1764 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ)); 1765 1766 /* Device Status Register */ 1767 reg = regs[o2i(capoff + PCIE_DCSR)]; 1768 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1769 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1770 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1771 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1772 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1773 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1774 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1775 onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD); 1776 1777 if (check_link) { 1778 /* Link Capability Register */ 1779 reg = regs[o2i(capoff + PCIE_LCAP)]; 1780 printf(" Link Capabilities Register: 0x%08x\n", reg); 1781 printf(" Maximum Link Speed: "); 1782 pci_print_pcie_linkspeed(reg & PCIE_LCAP_MAX_SPEED); 1783 printf(" Maximum Link Width: x%u lanes\n", 1784 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH)); 1785 printf(" Active State PM Support: "); 1786 switch (__SHIFTOUT(reg, PCIE_LCAP_ASPM)) { 1787 case 0x0: 1788 printf("No ASPM support\n"); 1789 break; 1790 case 0x1: 1791 printf("L0s supported\n"); 1792 break; 1793 case 0x2: 1794 printf("L1 supported\n"); 1795 break; 1796 case 0x3: 1797 printf("L0s and L1 supported\n"); 1798 break; 1799 } 1800 printf(" L0 Exit Latency: "); 1801 pci_print_pcie_L0s_latency(__SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT)); 1802 printf(" L1 Exit Latency: "); 1803 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_LCAP_L1_EXIT)); 1804 printf(" Port Number: %u\n", 1805 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_PORT)); 1806 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1807 onoff("Surprise Down Error Report", reg, 1808 PCIE_LCAP_SURPRISE_DOWN); 1809 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1810 onoff("Link BW Notification Capable", reg, 1811 PCIE_LCAP_LINK_BW_NOTIFY); 1812 onoff("ASPM Optionally Compliance", reg, 1813 PCIE_LCAP_ASPM_COMPLIANCE); 1814 1815 /* Link Control Register */ 1816 reg = regs[o2i(capoff + PCIE_LCSR)]; 1817 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1818 printf(" Active State PM Control: "); 1819 switch (reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S)) { 1820 case 0: 1821 printf("disabled\n"); 1822 break; 1823 case 1: 1824 printf("L0s Entry Enabled\n"); 1825 break; 1826 case 2: 1827 printf("L1 Entry Enabled\n"); 1828 break; 1829 case 3: 1830 printf("L0s and L1 Entry Enabled\n"); 1831 break; 1832 } 1833 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1834 "128bytes", "64bytes"); 1835 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1836 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1837 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1838 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1839 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1840 onoff("Hardware Autonomous Width Disable", reg,PCIE_LCSR_HAWD); 1841 onoff("Link Bandwidth Management Interrupt Enable", reg, 1842 PCIE_LCSR_LBMIE); 1843 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1844 PCIE_LCSR_LABIE); 1845 printf(" DRS Signaling Control: "); 1846 switch (__SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) { 1847 case 0: 1848 printf("not reported\n"); 1849 break; 1850 case 1: 1851 printf("Interrupt Enabled\n"); 1852 break; 1853 case 2: 1854 printf("DRS to FRS Signaling Enabled\n"); 1855 break; 1856 default: 1857 printf("reserved\n"); 1858 break; 1859 } 1860 1861 /* Link Status Register */ 1862 reg = regs[o2i(capoff + PCIE_LCSR)]; 1863 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1864 printf(" Negotiated Link Speed: "); 1865 pci_print_pcie_linkspeed(__SHIFTOUT(reg, PCIE_LCSR_LINKSPEED)); 1866 printf(" Negotiated Link Width: x%u lanes\n", 1867 (unsigned int)__SHIFTOUT(reg, PCIE_LCSR_NLW)); 1868 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1869 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1870 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1871 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1872 onoff("Link Bandwidth Management Status", reg, 1873 PCIE_LCSR_LINK_BW_MGMT); 1874 onoff("Link Autonomous Bandwidth Status", reg, 1875 PCIE_LCSR_LINK_AUTO_BW); 1876 } 1877 1878 if (check_slot == true) { 1879 /* Slot Capability Register */ 1880 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1881 printf(" Slot Capability Register: 0x%08x\n", reg); 1882 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1883 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1884 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1885 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1886 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1887 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1888 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1889 printf(" Slot Power Limit Value: %d\n", 1890 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1891 printf(" Slot Power Limit Scale: %d\n", 1892 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1893 onoff("Electromechanical Interlock Present", reg, 1894 PCIE_SLCAP_EIP); 1895 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1896 printf(" Physical Slot Number: %d\n", 1897 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1898 1899 /* Slot Control Register */ 1900 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1901 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1902 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1903 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1904 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1905 onoff("Presense Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1906 onoff("Command Completed Interrupt Enabled", reg, 1907 PCIE_SLCSR_CCE); 1908 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1909 printf(" Attention Indicator Control: "); 1910 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1911 case 0x0: 1912 printf("reserved\n"); 1913 break; 1914 case 0x1: 1915 printf("on\n"); 1916 break; 1917 case 0x2: 1918 printf("blink\n"); 1919 break; 1920 case 0x3: 1921 printf("off\n"); 1922 break; 1923 } 1924 printf(" Power Indicator Control: "); 1925 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1926 case 0x0: 1927 printf("reserved\n"); 1928 break; 1929 case 0x1: 1930 printf("on\n"); 1931 break; 1932 case 0x2: 1933 printf("blink\n"); 1934 break; 1935 case 0x3: 1936 printf("off\n"); 1937 break; 1938 } 1939 printf(" Power Controller Control: Power %s\n", 1940 reg & PCIE_SLCSR_PCC ? "off" : "on"); 1941 onoff("Electromechanical Interlock Control", 1942 reg, PCIE_SLCSR_EIC); 1943 onoff("Data Link Layer State Changed Enable", reg, 1944 PCIE_SLCSR_DLLSCE); 1945 onoff("Auto Slot Power Limit Disable", reg, 1946 PCIE_SLCSR_AUTOSPLDIS); 1947 1948 /* Slot Status Register */ 1949 printf(" Slot Status Register: 0x%04x\n", reg >> 16); 1950 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1951 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1952 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1953 onoff("Presense Detect Changed", reg, PCIE_SLCSR_PDC); 1954 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1955 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1956 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1957 onoff("Electromechanical Interlock engaged", reg, 1958 PCIE_SLCSR_EIS); 1959 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 1960 } 1961 1962 if (check_rootport == true) { 1963 /* Root Control Register */ 1964 reg = regs[o2i(capoff + PCIE_RCR)]; 1965 printf(" Root Control Register: %04x\n", reg & 0xffff); 1966 onoff("SERR on Correctable Error Enable", reg, 1967 PCIE_RCR_SERR_CER); 1968 onoff("SERR on Non-Fatal Error Enable", reg, 1969 PCIE_RCR_SERR_NFER); 1970 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 1971 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 1972 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 1973 1974 /* Root Capability Register */ 1975 printf(" Root Capability Register: 0x%04x\n", 1976 reg >> 16); 1977 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 1978 1979 /* Root Status Register */ 1980 reg = regs[o2i(capoff + PCIE_RSR)]; 1981 printf(" Root Status Register: 0x%08x\n", reg); 1982 printf(" PME Requester ID: 0x%04x\n", 1983 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1984 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 1985 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 1986 } 1987 1988 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1989 if (pciever < 2) 1990 return; 1991 1992 /* Device Capabilities 2 */ 1993 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1994 printf(" Device Capabilities 2: 0x%08x\n", reg); 1995 printf(" Completion Timeout Ranges Supported: "); 1996 val = reg & PCIE_DCAP2_COMPT_RANGE; 1997 switch (val) { 1998 case 0: 1999 printf("not supported\n"); 2000 break; 2001 default: 2002 for (i = 0; i <= 3; i++) { 2003 if (((val >> i) & 0x01) != 0) 2004 printf("%c", 'A' + i); 2005 } 2006 printf("\n"); 2007 } 2008 onoff("Completion Timeout Disable Supported", reg, 2009 PCIE_DCAP2_COMPT_DIS); 2010 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 2011 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 2012 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 2013 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 2014 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 2015 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 2016 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 2017 printf(" TPH Completer Supported: "); 2018 switch (__SHIFTOUT(reg, PCIE_DCAP2_TPH_COMP)) { 2019 case 0: 2020 printf("Not supportted\n"); 2021 break; 2022 case 1: 2023 printf("TPH\n"); 2024 break; 2025 case 3: 2026 printf("TPH and Extended TPH\n"); 2027 break; 2028 default: 2029 printf("(reserved value)\n"); 2030 break; 2031 2032 } 2033 printf(" LN System CLS: "); 2034 switch (__SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 2035 case 0x0: 2036 printf("Not supported or not in effect\n"); 2037 break; 2038 case 0x1: 2039 printf("64byte cachelines in effect\n"); 2040 break; 2041 case 0x2: 2042 printf("128byte cachelines in effect\n"); 2043 break; 2044 case 0x3: 2045 printf("Reserved\n"); 2046 break; 2047 } 2048 printf(" OBFF Supported: "); 2049 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 2050 case 0x0: 2051 printf("Not supported\n"); 2052 break; 2053 case 0x1: 2054 printf("Message only\n"); 2055 break; 2056 case 0x2: 2057 printf("WAKE# only\n"); 2058 break; 2059 case 0x3: 2060 printf("Both\n"); 2061 break; 2062 } 2063 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 2064 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 2065 val = __SHIFTOUT(reg, PCIE_DCAP2_MAX_EETLP); 2066 printf(" Max End-End TLP Prefixes: %u\n", (val == 0) ? 4 : val); 2067 printf(" Emergency Power Reduction Supported: "); 2068 switch (__SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) { 2069 case 0x0: 2070 printf("Not supported\n"); 2071 break; 2072 case 0x1: 2073 printf("Device Specific mechanism\n"); 2074 break; 2075 case 0x2: 2076 printf("Form Factor spec or Device Specific mechanism\n"); 2077 break; 2078 case 0x3: 2079 printf("Reserved\n"); 2080 break; 2081 } 2082 onoff("Emergency Power Reduction Initialization Required", reg, 2083 PCIE_DCAP2_EMGPWRRED_INI); 2084 onoff("FRS Supported", reg, PCIE_DCAP2_FRS); 2085 2086 /* Device Control 2 */ 2087 reg = regs[o2i(capoff + PCIE_DCSR2)]; 2088 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 2089 printf(" Completion Timeout Value: "); 2090 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 2091 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 2092 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 2093 onoff("AtomicOp Rquester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 2094 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 2095 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 2096 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 2097 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 2098 onoff("Emergency Power Reduction Request", reg, 2099 PCIE_DCSR2_EMGPWRRED_REQ); 2100 printf(" OBFF: "); 2101 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 2102 case 0x0: 2103 printf("Disabled\n"); 2104 break; 2105 case 0x1: 2106 printf("Enabled with Message Signaling Variation A\n"); 2107 break; 2108 case 0x2: 2109 printf("Enabled with Message Signaling Variation B\n"); 2110 break; 2111 case 0x3: 2112 printf("Enabled using WAKE# signaling\n"); 2113 break; 2114 } 2115 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 2116 2117 if (check_link) { 2118 bool drs_supported = false; 2119 2120 /* Link Capability 2 */ 2121 reg = regs[o2i(capoff + PCIE_LCAP2)]; 2122 /* If the vector is 0, LCAP2 is not implemented */ 2123 if ((reg & PCIE_LCAP2_SUP_LNKSV) != 0) { 2124 printf(" Link Capabilities 2: 0x%08x\n", reg); 2125 printf(" Supported Link Speeds Vector:"); 2126 pci_print_pcie_linkspeedvector( 2127 __SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV)); 2128 printf("\n"); 2129 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 2130 printf(" " 2131 "Lower SKP OS Generation Supported Speed Vector:"); 2132 pci_print_pcie_linkspeedvector( 2133 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV)); 2134 printf("\n"); 2135 printf(" " 2136 "Lower SKP OS Reception Supported Speed Vector:"); 2137 pci_print_pcie_linkspeedvector( 2138 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV)); 2139 printf("\n"); 2140 onoff("DRS Supported", reg, PCIE_LCAP2_DRS); 2141 drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false; 2142 } 2143 2144 /* Link Control 2 */ 2145 reg = regs[o2i(capoff + PCIE_LCSR2)]; 2146 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 2147 printf(" Target Link Speed: "); 2148 pci_print_pcie_linkspeed(__SHIFTOUT(reg, 2149 PCIE_LCSR2_TGT_LSPEED)); 2150 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 2151 onoff("HW Autonomous Speed Disabled", reg, 2152 PCIE_LCSR2_HW_AS_DIS); 2153 printf(" Selectable De-emphasis: "); 2154 pci_print_pcie_link_deemphasis( 2155 __SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP)); 2156 printf("\n"); 2157 printf(" Transmit Margin: %u\n", 2158 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 2159 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 2160 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 2161 printf(" Compliance Present/De-emphasis: "); 2162 pci_print_pcie_link_deemphasis( 2163 __SHIFTOUT(reg, PCIE_LCSR2_COMP_DEEMP)); 2164 printf("\n"); 2165 2166 /* Link Status 2 */ 2167 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 2168 printf(" Current De-emphasis Level: "); 2169 pci_print_pcie_link_deemphasis( 2170 __SHIFTOUT(reg, PCIE_LCSR2_DEEMP_LVL)); 2171 printf("\n"); 2172 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 2173 onoff("Equalization Phase 1 Successful", reg, 2174 PCIE_LCSR2_EQP1_SUC); 2175 onoff("Equalization Phase 2 Successful", reg, 2176 PCIE_LCSR2_EQP2_SUC); 2177 onoff("Equalization Phase 3 Successful", reg, 2178 PCIE_LCSR2_EQP3_SUC); 2179 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 2180 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD); 2181 if (drs_supported) { 2182 printf(" Downstream Component Presence: "); 2183 switch (__SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) { 2184 case PCIE_DSCOMPN_DOWN_NOTDETERM: 2185 printf("Link Down - Presence Not" 2186 " Determined\n"); 2187 break; 2188 case PCIE_DSCOMPN_DOWN_NOTPRES: 2189 printf("Link Down - Component Not Present\n"); 2190 break; 2191 case PCIE_DSCOMPN_DOWN_PRES: 2192 printf("Link Down - Component Present\n"); 2193 break; 2194 case PCIE_DSCOMPN_UP_PRES: 2195 printf("Link Up - Component Present\n"); 2196 break; 2197 case PCIE_DSCOMPN_UP_PRES_DRS: 2198 printf("Link Up - Component Present and DRS" 2199 " received\n"); 2200 break; 2201 default: 2202 printf("reserved\n"); 2203 break; 2204 } 2205 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV); 2206 } 2207 } 2208 2209 /* Slot Capability 2 */ 2210 /* Slot Control 2 */ 2211 /* Slot Status 2 */ 2212 } 2213 2214 static void 2215 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 2216 { 2217 pcireg_t reg; 2218 2219 printf("\n MSI-X Capability Register\n"); 2220 2221 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2222 printf(" Message Control register: 0x%04x\n", 2223 (reg >> 16) & 0xff); 2224 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 2225 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 2226 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 2227 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 2228 printf(" Table offset register: 0x%08x\n", reg); 2229 printf(" Table offset: 0x%08x\n", 2230 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 2231 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 2232 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 2233 printf(" Pending bit array register: 0x%08x\n", reg); 2234 printf(" Pending bit array offset: 0x%08x\n", 2235 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 2236 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 2237 } 2238 2239 static void 2240 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 2241 { 2242 pcireg_t reg; 2243 2244 printf("\n Serial ATA Capability Register\n"); 2245 2246 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2247 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 2248 printf(" Revision: %u.%u\n", 2249 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 2250 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 2251 2252 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 2253 2254 printf(" BAR Register: 0x%08x\n", reg); 2255 printf(" Register location: "); 2256 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 2257 printf("in config space\n"); 2258 else { 2259 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 2260 printf(" BAR offset: 0x%08x\n", 2261 (pcireg_t)__SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 2262 } 2263 } 2264 2265 static void 2266 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 2267 { 2268 pcireg_t reg; 2269 2270 printf("\n Advanced Features Capability Register\n"); 2271 2272 reg = regs[o2i(capoff + PCI_AFCAPR)]; 2273 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 2274 printf(" AF Structure Length: 0x%02x\n", 2275 (pcireg_t)__SHIFTOUT(reg, PCI_AF_LENGTH)); 2276 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 2277 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 2278 reg = regs[o2i(capoff + PCI_AFCSR)]; 2279 printf(" AF Control register: 0x%02x\n", reg & 0xff); 2280 /* 2281 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 2282 * and it's always 0 on read 2283 */ 2284 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 2285 onoff("Transaction Pending", reg, PCI_AFSR_TP); 2286 } 2287 2288 static struct { 2289 pcireg_t cap; 2290 const char *name; 2291 void (*printfunc)(const pcireg_t *, int); 2292 } pci_captab[] = { 2293 { PCI_CAP_RESERVED0, "reserved", NULL }, 2294 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 2295 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 2296 { PCI_CAP_VPD, "VPD", NULL }, 2297 { PCI_CAP_SLOTID, "SlotID", NULL }, 2298 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 2299 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 2300 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2301 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2302 { PCI_CAP_VENDSPEC, "Vendor-specific", 2303 pci_conf_print_vendspec_cap }, 2304 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2305 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2306 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2307 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2308 pci_conf_print_subsystem_cap }, 2309 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2310 { PCI_CAP_SECURE, "Secure Device", NULL }, 2311 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2312 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2313 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2314 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2315 { PCI_CAP_EA, "Enhanced Allocation", NULL } 2316 }; 2317 2318 static int 2319 pci_conf_find_cap(const pcireg_t *regs, int capoff, unsigned int capid, 2320 int *offsetp) 2321 { 2322 pcireg_t rval; 2323 int off; 2324 2325 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2326 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2327 rval = regs[o2i(off)]; 2328 if (capid == PCI_CAPLIST_CAP(rval)) { 2329 if (offsetp != NULL) 2330 *offsetp = off; 2331 return 1; 2332 } 2333 } 2334 return 0; 2335 } 2336 2337 static void 2338 pci_conf_print_caplist( 2339 #ifdef _KERNEL 2340 pci_chipset_tag_t pc, pcitag_t tag, 2341 #endif 2342 const pcireg_t *regs, int capoff) 2343 { 2344 int off; 2345 pcireg_t foundcap; 2346 pcireg_t rval; 2347 bool foundtable[__arraycount(pci_captab)]; 2348 unsigned int i; 2349 2350 /* Clear table */ 2351 for (i = 0; i < __arraycount(pci_captab); i++) 2352 foundtable[i] = false; 2353 2354 /* Print capability register's offset and the type first */ 2355 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2356 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2357 rval = regs[o2i(off)]; 2358 printf(" Capability register at 0x%02x\n", off); 2359 2360 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2361 foundcap = PCI_CAPLIST_CAP(rval); 2362 if (foundcap < __arraycount(pci_captab)) { 2363 printf("%s)\n", pci_captab[foundcap].name); 2364 /* Mark as found */ 2365 foundtable[foundcap] = true; 2366 } else 2367 printf("unknown)\n"); 2368 } 2369 2370 /* 2371 * And then, print the detail of each capability registers 2372 * in capability value's order. 2373 */ 2374 for (i = 0; i < __arraycount(pci_captab); i++) { 2375 if (foundtable[i] == false) 2376 continue; 2377 2378 /* 2379 * The type was found. Search capability list again and 2380 * print all capabilities that the capabiliy type is 2381 * the same. This is required because some capabilities 2382 * appear multiple times (e.g. HyperTransport capability). 2383 */ 2384 #if 0 2385 if (pci_conf_find_cap(regs, capoff, i, &off)) { 2386 rval = regs[o2i(off)]; 2387 if (pci_captab[i].printfunc != NULL) 2388 pci_captab[i].printfunc(regs, off); 2389 } 2390 #else 2391 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2392 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2393 rval = regs[o2i(off)]; 2394 if ((PCI_CAPLIST_CAP(rval) == i) 2395 && (pci_captab[i].printfunc != NULL)) 2396 pci_captab[i].printfunc(regs, off); 2397 } 2398 #endif 2399 } 2400 } 2401 2402 /* Extended Capability */ 2403 2404 static void 2405 pci_conf_print_aer_cap_uc(pcireg_t reg) 2406 { 2407 2408 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2409 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2410 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2411 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP); 2412 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2413 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2414 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2415 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2416 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2417 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2418 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2419 onoff("Unsupported Request Error", reg, 2420 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2421 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2422 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2423 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2424 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2425 onoff("TLP Prefix Blocked Error", reg, 2426 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2427 onoff("Poisoned TLP Egress Blocked", reg, 2428 PCI_AER_UC_POISONTLP_EGRESS_BLOCKED); 2429 } 2430 2431 static void 2432 pci_conf_print_aer_cap_cor(pcireg_t reg) 2433 { 2434 2435 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2436 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2437 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2438 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2439 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2440 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2441 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2442 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2443 } 2444 2445 static void 2446 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2447 { 2448 2449 printf(" First Error Pointer: 0x%04x\n", 2450 (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2451 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2452 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2453 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2454 onoff("ECRC Check Enab", reg, PCI_AER_ECRC_CHECK_ENABLE); 2455 onoff("Multiple Header Recording Capable", reg, 2456 PCI_AER_MULT_HDR_CAPABLE); 2457 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE); 2458 onoff("Completion Timeout Prefix/Header Log Capable", reg, 2459 PCI_AER_COMPTOUTPRFXHDRLOG_CAP); 2460 2461 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2462 if (!tlp_prefix_log) 2463 return; 2464 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2465 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2466 } 2467 2468 static void 2469 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2470 { 2471 2472 onoff("Correctable Error Reporting Enable", reg, 2473 PCI_AER_ROOTERR_COR_ENABLE); 2474 onoff("Non-Fatal Error Reporting Enable", reg, 2475 PCI_AER_ROOTERR_NF_ENABLE); 2476 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2477 } 2478 2479 static void 2480 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2481 { 2482 2483 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2484 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2485 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2486 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2487 PCI_AER_ROOTERR_MULTI_UC_ERR); 2488 onoff("First Uncorrectable Fatal", reg,PCI_AER_ROOTERR_FIRST_UC_FATAL); 2489 onoff("Non-Fatal Error Messages Received", reg,PCI_AER_ROOTERR_NF_ERR); 2490 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2491 printf(" Advanced Error Interrupt Message Number: 0x%02x\n", 2492 (unsigned int)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2493 } 2494 2495 static void 2496 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2497 { 2498 2499 printf(" Correctable Source ID: 0x%04x\n", 2500 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2501 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2502 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2503 } 2504 2505 static void 2506 pci_conf_print_aer_cap(const pcireg_t *regs, int capoff, int extcapoff) 2507 { 2508 pcireg_t reg; 2509 int pcie_capoff; 2510 int pcie_devtype = -1; 2511 bool tlp_prefix_log = false; 2512 2513 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2514 reg = regs[o2i(pcie_capoff)]; 2515 pcie_devtype = PCIE_XCAP_TYPE(reg); 2516 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2517 if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2518 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2519 /* End-End TLP Prefix Supported */ 2520 if (reg & PCIE_DCAP2_EETLP_PREF) { 2521 tlp_prefix_log = true; 2522 } 2523 } 2524 } 2525 2526 printf("\n Advanced Error Reporting Register\n"); 2527 2528 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2529 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2530 pci_conf_print_aer_cap_uc(reg); 2531 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2532 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2533 pci_conf_print_aer_cap_uc(reg); 2534 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2535 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2536 pci_conf_print_aer_cap_uc(reg); 2537 2538 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2539 printf(" Correctable Error Status register: 0x%08x\n", reg); 2540 pci_conf_print_aer_cap_cor(reg); 2541 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2542 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2543 pci_conf_print_aer_cap_cor(reg); 2544 2545 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2546 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2547 reg); 2548 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2549 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2550 printf(" Header Log register:\n"); 2551 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2552 extcapoff + PCI_AER_ROOTERR_CMD); 2553 2554 switch (pcie_devtype) { 2555 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ 2556 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ 2557 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2558 printf(" Root Error Command register: 0x%08x\n", reg); 2559 pci_conf_print_aer_cap_rooterr_cmd(reg); 2560 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2561 printf(" Root Error Status register: 0x%08x\n", reg); 2562 pci_conf_print_aer_cap_rooterr_status(reg); 2563 2564 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2565 printf(" Error Source Identification: 0x%04x\n", reg); 2566 pci_conf_print_aer_cap_errsrc_id(reg); 2567 break; 2568 } 2569 2570 if (tlp_prefix_log) { 2571 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2572 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2573 } 2574 } 2575 2576 static void 2577 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2578 pcireg_t parbsel, int parbsize) 2579 { 2580 pcireg_t reg; 2581 int num = 16 << parbsel; 2582 int num_per_reg = sizeof(pcireg_t) / parbsize; 2583 int i, j; 2584 2585 /* First, dump the table */ 2586 for (i = 0; i < num; i += num_per_reg) { 2587 reg = regs[o2i(off + i / num_per_reg)]; 2588 printf(" %s Arbitration Table: 0x%08x\n", name, reg); 2589 } 2590 /* And then, decode each entry */ 2591 for (i = 0; i < num; i += num_per_reg) { 2592 reg = regs[o2i(off + i / num_per_reg)]; 2593 for (j = 0; j < num_per_reg; j++) 2594 printf(" Phase[%d]: %d\n", j, reg); 2595 } 2596 } 2597 2598 static void 2599 pci_conf_print_vc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2600 { 2601 pcireg_t reg, n; 2602 int parbtab, parbsize; 2603 pcireg_t parbsel; 2604 int varbtab, varbsize; 2605 pcireg_t varbsel; 2606 int i, count; 2607 2608 printf("\n Virtual Channel Register\n"); 2609 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2610 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2611 count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2612 printf(" Extended VC Count: %d\n", count); 2613 n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2614 printf(" Low Priority Extended VC Count: %u\n", n); 2615 n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2616 printf(" Reference Clock: %s\n", 2617 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 2618 parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2619 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2620 2621 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 2622 printf(" Port VC Capability register 2: 0x%08x\n", reg); 2623 onoff("Hardware fixed arbitration scheme", 2624 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 2625 onoff("WRR arbitration with 32 phases", 2626 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 2627 onoff("WRR arbitration with 64 phases", 2628 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 2629 onoff("WRR arbitration with 128 phases", 2630 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 2631 varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 2632 printf(" VC Arbitration Table Offset: 0x%x\n", varbtab); 2633 2634 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 2635 printf(" Port VC Control register: 0x%04x\n", reg); 2636 varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 2637 printf(" VC Arbitration Select: 0x%x\n", varbsel); 2638 2639 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 2640 printf(" Port VC Status register: 0x%04x\n", reg); 2641 onoff("VC Arbitration Table Status", 2642 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 2643 2644 for (i = 0; i < count + 1; i++) { 2645 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 2646 printf(" VC number %d\n", i); 2647 printf(" VC Resource Capability Register: 0x%08x\n", reg); 2648 onoff(" Non-configurable Hardware fixed arbitration scheme", 2649 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 2650 onoff(" WRR arbitration with 32 phases", 2651 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 2652 onoff(" WRR arbitration with 64 phases", 2653 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 2654 onoff(" WRR arbitration with 128 phases", 2655 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 2656 onoff(" Time-based WRR arbitration with 128 phases", 2657 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 2658 onoff(" WRR arbitration with 256 phases", 2659 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 2660 onoff(" Advanced Packet Switching", 2661 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 2662 onoff(" Reject Snoop Transaction", 2663 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 2664 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 2665 printf(" Maximum Time Slots: %d\n", n); 2666 parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S; 2667 printf(" Port Arbitration Table offset: 0x%02x\n", 2668 parbtab); 2669 2670 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 2671 printf(" VC Resource Control Register: 0x%08x\n", reg); 2672 printf(" TC/VC Map: 0x%02x\n", 2673 (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 2674 /* 2675 * The load Port Arbitration Table bit is used to update 2676 * the Port Arbitration logic and it's always 0 on read, so 2677 * we don't print it. 2678 */ 2679 parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 2680 printf(" Port Arbitration Select: 0x%x\n", parbsel); 2681 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 2682 printf(" VC ID %d\n", n); 2683 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 2684 2685 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 2686 printf(" VC Resource Status Register: 0x%08x\n", reg); 2687 onoff(" Port Arbitration Table Status", 2688 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 2689 onoff(" VC Negotiation Pending", 2690 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 2691 2692 if ((parbtab != 0) && (parbsel != 0)) 2693 pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab, 2694 "Port", parbsel, parbsize); 2695 } 2696 2697 varbsize = 8; 2698 if ((varbtab != 0) && (varbsel != 0)) 2699 pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab, 2700 " VC", varbsel, varbsize); 2701 } 2702 2703 static void 2704 pci_conf_print_pwrbdgt_base_power(uint8_t base, unsigned int scale) 2705 { 2706 if (base <= 0xef) { 2707 unsigned int sdiv = 1; 2708 for (unsigned int i = scale; i > 0; i--) 2709 sdiv *= 10; 2710 2711 printf("%u", base / sdiv); 2712 2713 if (scale != 0) { 2714 printf(".%u", base % sdiv); 2715 } 2716 printf ("W\n"); 2717 return; 2718 } 2719 2720 const char *s; 2721 2722 switch (base) { 2723 case 0xf0: 2724 s = "239W < x <= 250W"; 2725 break; 2726 case 0xf1: 2727 s = "250W < x <= 275W"; 2728 break; 2729 case 0xf2: 2730 s = "275W < x <= 300W"; 2731 break; 2732 default: 2733 s = "reserved for above 300W"; 2734 break; 2735 } 2736 printf("%s\n", s); 2737 } 2738 2739 static const char * 2740 pci_conf_print_pwrbdgt_type(uint8_t reg) 2741 { 2742 2743 switch (reg) { 2744 case 0x00: 2745 return "PME Aux"; 2746 case 0x01: 2747 return "Auxilary"; 2748 case 0x02: 2749 return "Idle"; 2750 case 0x03: 2751 return "Sustained"; 2752 case 0x04: 2753 return "Sustained (Emergency Power Reduction)"; 2754 case 0x05: 2755 return "Maximum (Emergency Power Reduction)"; 2756 case 0x07: 2757 return "Maximum"; 2758 default: 2759 return "Unknown"; 2760 } 2761 } 2762 2763 static const char * 2764 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 2765 { 2766 2767 switch (reg) { 2768 case 0x00: 2769 return "Power(12V)"; 2770 case 0x01: 2771 return "Power(3.3V)"; 2772 case 0x02: 2773 return "Power(1.5V or 1.8V)"; 2774 case 0x07: 2775 return "Thermal"; 2776 default: 2777 return "Unknown"; 2778 } 2779 } 2780 2781 static void 2782 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff) 2783 { 2784 pcireg_t reg; 2785 unsigned int scale; 2786 2787 printf("\n Power Budgeting\n"); 2788 2789 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 2790 printf(" Data Select register: 0x%08x\n", reg); 2791 2792 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 2793 printf(" Data register: 0x%08x\n", reg); 2794 scale = __SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE); 2795 printf(" Base Power: "); 2796 pci_conf_print_pwrbdgt_base_power((uint8_t)reg, scale); 2797 printf(" PM Sub State: 0x%hhx\n", 2798 (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 2799 printf(" PM State: D%u\n", 2800 (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 2801 printf(" Type: %s\n", 2802 pci_conf_print_pwrbdgt_type( 2803 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 2804 printf(" Power Rail: %s\n", 2805 pci_conf_print_pwrbdgt_pwrrail( 2806 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 2807 2808 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 2809 printf(" Power Budget Capability register: 0x%08x\n", reg); 2810 onoff("System Allocated", 2811 reg, PCI_PWRBDGT_CAP_SYSALLOC); 2812 } 2813 2814 static const char * 2815 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 2816 { 2817 2818 switch (type) { 2819 case 0x00: 2820 return "Configuration Space Element"; 2821 case 0x01: 2822 return "System Egress Port or internal sink (memory)"; 2823 case 0x02: 2824 return "Internal Root Complex Link"; 2825 default: 2826 return "Unknown"; 2827 } 2828 } 2829 2830 static void 2831 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int capoff, int extcapoff) 2832 { 2833 pcireg_t reg; 2834 unsigned char nent, linktype; 2835 int i; 2836 2837 printf("\n Root Complex Link Declaration\n"); 2838 2839 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 2840 printf(" Element Self Description Register: 0x%08x\n", reg); 2841 printf(" Element Type: %s\n", 2842 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 2843 nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 2844 printf(" Number of Link Entries: %hhu\n", nent); 2845 printf(" Component ID: %hhu\n", 2846 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 2847 printf(" Port Number: %hhu\n", 2848 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 2849 for (i = 0; i < nent; i++) { 2850 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 2851 printf(" Link Entry %d:\n", i + 1); 2852 printf(" Link Description Register: 0x%08x\n", reg); 2853 onoff(" Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID); 2854 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 2855 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 2856 "Configuration Space", "Memory-Mapped Space"); 2857 onoff(" Associated RCRB Header", reg, 2858 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 2859 printf(" Target Component ID: %hhu\n", 2860 (unsigned char)__SHIFTOUT(reg, 2861 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 2862 printf(" Target Port Number: %hhu\n", 2863 (unsigned char)__SHIFTOUT(reg, 2864 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 2865 2866 if (linktype == 0) { 2867 /* Memory-Mapped Space */ 2868 reg = regs[o2i(extcapoff 2869 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 2870 printf(" Link Address Low Register: 0x%08x\n", 2871 reg); 2872 reg = regs[o2i(extcapoff 2873 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 2874 printf(" Link Address High Register: 0x%08x\n", 2875 reg); 2876 } else { 2877 unsigned int nb; 2878 pcireg_t lo, hi; 2879 2880 /* Configuration Space */ 2881 lo = regs[o2i(extcapoff 2882 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 2883 printf(" Configuration Space Low Register: " 2884 "0x%08x\n", lo); 2885 hi = regs[o2i(extcapoff 2886 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 2887 printf(" Configuration Space High Register: " 2888 "0x%08x\n", hi); 2889 nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 2890 printf(" N: %u\n", nb); 2891 printf(" Func: %hhu\n", 2892 (unsigned char)__SHIFTOUT(lo, 2893 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 2894 printf(" Dev: %hhu\n", 2895 (unsigned char)__SHIFTOUT(lo, 2896 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 2897 printf(" Bus: %hhu\n", 2898 (unsigned char)__SHIFTOUT(lo, 2899 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 2900 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 2901 printf(" Configuration Space Base Address: " 2902 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 2903 } 2904 } 2905 } 2906 2907 /* XXX pci_conf_print_rclink_ctl_cap */ 2908 2909 static void 2910 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2911 { 2912 pcireg_t reg; 2913 2914 printf("\n Root Complex Event Collector Association\n"); 2915 2916 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 2917 printf(" Association Bitmap for Root Complex Integrated Devices:" 2918 " 0x%08x\n", reg); 2919 } 2920 2921 /* XXX pci_conf_print_mfvc_cap */ 2922 /* XXX pci_conf_print_vc2_cap */ 2923 /* XXX pci_conf_print_rcrb_cap */ 2924 /* XXX pci_conf_print_vendor_cap */ 2925 /* XXX pci_conf_print_cac_cap */ 2926 2927 static void 2928 pci_conf_print_acs_cap(const pcireg_t *regs, int capoff, int extcapoff) 2929 { 2930 pcireg_t reg, cap, ctl; 2931 unsigned int size, i; 2932 2933 printf("\n Access Control Services\n"); 2934 2935 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 2936 cap = reg & 0xffff; 2937 ctl = reg >> 16; 2938 printf(" ACS Capability register: 0x%08x\n", cap); 2939 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 2940 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 2941 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 2942 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 2943 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 2944 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 2945 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 2946 size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 2947 if (size == 0) 2948 size = 256; 2949 printf(" Egress Control Vector Size: %u\n", size); 2950 printf(" ACS Control register: 0x%08x\n", ctl); 2951 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 2952 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 2953 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 2954 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 2955 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 2956 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 2957 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 2958 2959 /* 2960 * If the P2P Egress Control Capability bit is 0, ignore the Egress 2961 * Control vector. 2962 */ 2963 if ((cap & PCI_ACS_CAP_E) == 0) 2964 return; 2965 for (i = 0; i < size; i += 32) 2966 printf(" Egress Control Vector [%u..%u]: 0x%08x\n", i + 31, 2967 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 2968 } 2969 2970 static void 2971 pci_conf_print_ari_cap(const pcireg_t *regs, int capoff, int extcapoff) 2972 { 2973 pcireg_t reg, cap, ctl; 2974 2975 printf("\n Alternative Routing-ID Interpretation Register\n"); 2976 2977 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2978 cap = reg & 0xffff; 2979 ctl = reg >> 16; 2980 printf(" Capability register: 0x%08x\n", cap); 2981 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 2982 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 2983 printf(" Next Function Number: %u\n", 2984 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 2985 printf(" Control register: 0x%08x\n", ctl); 2986 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 2987 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 2988 printf(" Function Group: %u\n", 2989 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 2990 } 2991 2992 static void 2993 pci_conf_print_ats_cap(const pcireg_t *regs, int capoff, int extcapoff) 2994 { 2995 pcireg_t reg, cap, ctl; 2996 unsigned int num; 2997 2998 printf("\n Address Translation Services\n"); 2999 3000 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3001 cap = reg & 0xffff; 3002 ctl = reg >> 16; 3003 printf(" Capability register: 0x%04x\n", cap); 3004 num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 3005 if (num == 0) 3006 num = 32; 3007 printf(" Invalidate Queue Depth: %u\n", num); 3008 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 3009 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 3010 3011 printf(" Control register: 0x%04x\n", ctl); 3012 printf(" Smallest Translation Unit: %u\n", 3013 (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU)); 3014 onoff("Enable", reg, PCI_ATS_CTL_EN); 3015 } 3016 3017 static void 3018 pci_conf_print_sernum_cap(const pcireg_t *regs, int capoff, int extcapoff) 3019 { 3020 pcireg_t lo, hi; 3021 3022 printf("\n Device Serial Number Register\n"); 3023 3024 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 3025 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 3026 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 3027 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 3028 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 3029 } 3030 3031 static void 3032 pci_conf_print_sriov_cap(const pcireg_t *regs, int capoff, int extcapoff) 3033 { 3034 char buf[sizeof("99999 MB")]; 3035 pcireg_t reg; 3036 pcireg_t total_vfs; 3037 int i; 3038 bool first; 3039 3040 printf("\n Single Root IO Virtualization Register\n"); 3041 3042 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 3043 printf(" Capabilities register: 0x%08x\n", reg); 3044 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 3045 onoff("ARI Capable Hierarchy Preserved", reg, 3046 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 3047 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 3048 printf(" VF Migration Interrupt Message Number: 0x%03x\n", 3049 (pcireg_t)__SHIFTOUT(reg, 3050 PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 3051 } 3052 3053 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 3054 printf(" Control register: 0x%04x\n", reg); 3055 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 3056 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 3057 onoff("VF Migration Interrupt Enable", reg, 3058 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 3059 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 3060 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 3061 3062 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 3063 printf(" Status register: 0x%04x\n", reg); 3064 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 3065 3066 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 3067 printf(" InitialVFs register: 0x%04x\n", reg); 3068 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 3069 printf(" TotalVFs register: 0x%04x\n", reg); 3070 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 3071 printf(" NumVFs register: 0x%04x\n", reg); 3072 3073 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 3074 printf(" Function Dependency Link register: 0x%04x\n", reg); 3075 3076 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 3077 printf(" First VF Offset register: 0x%04x\n", reg); 3078 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 3079 printf(" VF Stride register: 0x%04x\n", reg); 3080 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_DID)] >> 16; 3081 printf(" Device ID: 0x%04x\n", reg); 3082 3083 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 3084 printf(" Supported Page Sizes register: 0x%08x\n", reg); 3085 printf(" Supported Page Size:"); 3086 for (i = 0, first = true; i < 32; i++) { 3087 if (reg & __BIT(i)) { 3088 #ifdef _KERNEL 3089 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 3090 #else 3091 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 3092 HN_AUTOSCALE, 0); 3093 #endif 3094 printf("%s %s", first ? "" : ",", buf); 3095 first = false; 3096 } 3097 } 3098 printf("\n"); 3099 3100 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 3101 printf(" System Page Sizes register: 0x%08x\n", reg); 3102 printf(" Page Size: "); 3103 if (reg != 0) { 3104 #ifdef _KERNEL 3105 format_bytes(buf, sizeof(buf), 1LL << (ffs(reg) + 12)); 3106 #else 3107 humanize_number(buf, sizeof(buf), 1LL << (ffs(reg) + 12), "B", 3108 HN_AUTOSCALE, 0); 3109 #endif 3110 printf("%s", buf); 3111 } else { 3112 printf("unknown"); 3113 } 3114 printf("\n"); 3115 3116 for (i = 0; i < 6; i++) { 3117 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 3118 printf(" VF BAR%d register: 0x%08x\n", i, reg); 3119 } 3120 3121 if (total_vfs > 0) { 3122 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 3123 printf(" VF Migration State Array Offset register: 0x%08x\n", 3124 reg); 3125 printf(" VF Migration State Offset: 0x%08x\n", 3126 (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 3127 i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 3128 printf(" VF Migration State BIR: "); 3129 if (i >= 0 && i <= 5) { 3130 printf("BAR%d", i); 3131 } else { 3132 printf("unknown BAR (%d)", i); 3133 } 3134 printf("\n"); 3135 } 3136 } 3137 3138 /* XXX pci_conf_print_mriov_cap */ 3139 3140 static void 3141 pci_conf_print_multicast_cap(const pcireg_t *regs, int capoff, int extcapoff) 3142 { 3143 pcireg_t reg, cap, ctl; 3144 pcireg_t regl, regh; 3145 uint64_t addr; 3146 int n; 3147 3148 printf("\n Multicast\n"); 3149 3150 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 3151 cap = reg & 0xffff; 3152 ctl = reg >> 16; 3153 printf(" Capability Register: 0x%04x\n", cap); 3154 printf(" Max Group: %u\n", 3155 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 3156 3157 /* Endpoint Only */ 3158 n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 3159 if (n > 0) 3160 printf(" Windw Size Requested: %d\n", 1 << (n - 1)); 3161 3162 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 3163 3164 printf(" Control Register: 0x%04x\n", ctl); 3165 printf(" Num Group: %u\n", 3166 (unsigned int)__SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 3167 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 3168 3169 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 3170 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 3171 printf(" Base Address Register 0: 0x%08x\n", regl); 3172 printf(" Base Address Register 1: 0x%08x\n", regh); 3173 printf(" Index Position: %u\n", 3174 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 3175 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 3176 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 3177 3178 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 3179 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 3180 printf(" Receive Register 0: 0x%08x\n", regl); 3181 printf(" Receive Register 1: 0x%08x\n", regh); 3182 3183 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 3184 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 3185 printf(" Block All Register 0: 0x%08x\n", regl); 3186 printf(" Block All Register 1: 0x%08x\n", regh); 3187 3188 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 3189 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 3190 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 3191 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 3192 3193 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 3194 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 3195 printf(" Overlay BAR 0: 0x%08x\n", regl); 3196 printf(" Overlay BAR 1: 0x%08x\n", regh); 3197 3198 n = regl & PCI_MCAST_OVERLAYL_SIZE; 3199 printf(" Overlay Size: "); 3200 if (n >= 6) 3201 printf("%d\n", n); 3202 else 3203 printf("off\n"); 3204 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 3205 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 3206 } 3207 3208 static void 3209 pci_conf_print_page_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3210 { 3211 pcireg_t reg, ctl, sta; 3212 3213 printf("\n Page Request\n"); 3214 3215 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 3216 ctl = reg & 0xffff; 3217 sta = reg >> 16; 3218 printf(" Control Register: 0x%04x\n", ctl); 3219 onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E); 3220 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 3221 3222 printf(" Status Register: 0x%04x\n", sta); 3223 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 3224 onoff("Unexpected Page Request Group Index", reg, 3225 PCI_PAGE_REQ_STA_UPRGI); 3226 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 3227 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 3228 3229 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 3230 printf(" Outstanding Page Request Capacity: %u\n", reg); 3231 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 3232 printf(" Outstanding Page Request Allocation: %u\n", reg); 3233 } 3234 3235 /* XXX pci_conf_print_amd_cap */ 3236 3237 #define MEM_PBUFSIZE sizeof("999GB") 3238 3239 static void 3240 pci_conf_print_resizbar_cap(const pcireg_t *regs, int capoff, int extcapoff) 3241 { 3242 pcireg_t cap, ctl; 3243 unsigned int bars, i, n; 3244 char pbuf[MEM_PBUFSIZE]; 3245 3246 printf("\n Resizable BAR\n"); 3247 3248 /* Get Number of Resizable BARs */ 3249 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))]; 3250 bars = __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR); 3251 printf(" Number of Resizable BARs: "); 3252 if (bars <= 6) 3253 printf("%u\n", bars); 3254 else { 3255 printf("incorrect (%u)\n", bars); 3256 return; 3257 } 3258 3259 for (n = 0; n < 6; n++) { 3260 cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))]; 3261 printf(" Capability register(%u): 0x%08x\n", n, cap); 3262 if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0) 3263 continue; /* Not Used */ 3264 printf(" Acceptable BAR sizes:"); 3265 for (i = 4; i <= 23; i++) { 3266 if ((cap & (1 << i)) != 0) { 3267 humanize_number(pbuf, MEM_PBUFSIZE, 3268 (int64_t)1024 * 1024 << (i - 4), "B", 3269 #ifdef _KERNEL 3270 1); 3271 #else 3272 HN_AUTOSCALE, HN_NOSPACE); 3273 #endif 3274 printf(" %s", pbuf); 3275 } 3276 } 3277 printf("\n"); 3278 3279 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))]; 3280 printf(" Control register(%u): 0x%08x\n", n, ctl); 3281 printf(" BAR Index: %u\n", 3282 (unsigned int)__SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX)); 3283 humanize_number(pbuf, MEM_PBUFSIZE, 3284 (int64_t)1024 * 1024 3285 << __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ), 3286 "B", 3287 #ifdef _KERNEL 3288 1); 3289 #else 3290 HN_AUTOSCALE, HN_NOSPACE); 3291 #endif 3292 printf(" BAR Size: %s\n", pbuf); 3293 } 3294 } 3295 3296 static void 3297 pci_conf_print_dpa_cap(const pcireg_t *regs, int capoff, int extcapoff) 3298 { 3299 pcireg_t reg; 3300 unsigned int substmax, i; 3301 3302 printf("\n Dynamic Power Allocation\n"); 3303 3304 reg = regs[o2i(extcapoff + PCI_DPA_CAP)]; 3305 printf(" Capability register: 0x%08x\n", reg); 3306 substmax = __SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX); 3307 printf(" Substate Max: %u\n", substmax); 3308 printf(" Transition Latency Unit: "); 3309 switch (__SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) { 3310 case 0: 3311 printf("1ms\n"); 3312 break; 3313 case 1: 3314 printf("10ms\n"); 3315 break; 3316 case 2: 3317 printf("100ms\n"); 3318 break; 3319 default: 3320 printf("reserved\n"); 3321 break; 3322 } 3323 printf(" Power Allocation Scale: "); 3324 switch (__SHIFTOUT(reg, PCI_DPA_CAP_PAS)) { 3325 case 0: 3326 printf("10.0x\n"); 3327 break; 3328 case 1: 3329 printf("1.0x\n"); 3330 break; 3331 case 2: 3332 printf("0.1x\n"); 3333 break; 3334 case 3: 3335 printf("0.01x\n"); 3336 break; 3337 } 3338 printf(" Transition Latency Value 0: %u\n", 3339 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY0)); 3340 printf(" Transition Latency Value 1: %u\n", 3341 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY1)); 3342 3343 reg = regs[o2i(extcapoff + PCI_DPA_LATIND)]; 3344 printf(" Latency Indicatior register: 0x%08x\n", reg); 3345 3346 reg = regs[o2i(extcapoff + PCI_DPA_CS)]; 3347 printf(" Status register: 0x%04x\n", reg & 0xffff); 3348 printf(" Substate Status: 0x%02x\n", 3349 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT)); 3350 onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN); 3351 printf(" Control register: 0x%04x\n", reg >> 16); 3352 printf(" Substate Control: 0x%02x\n", 3353 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL)); 3354 3355 for (i = 0; i <= substmax; i++) 3356 printf(" Substate Power Allocation register %d: 0x%02x\n", 3357 i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff)); 3358 } 3359 3360 static const char * 3361 pci_conf_print_tph_req_cap_sttabloc(unsigned char val) 3362 { 3363 3364 switch (val) { 3365 case 0x0: 3366 return "Not Present"; 3367 case 0x1: 3368 return "in the TPH Requester Capability Structure"; 3369 case 0x2: 3370 return "in the MSI-X Table"; 3371 default: 3372 return "Unknown"; 3373 } 3374 } 3375 3376 static void 3377 pci_conf_print_tph_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3378 { 3379 pcireg_t reg; 3380 int size, i, j; 3381 3382 printf("\n TPH Requester Extended Capability\n"); 3383 3384 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 3385 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 3386 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 3387 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 3388 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 3389 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 3390 printf(" ST Table Location: %s\n", 3391 pci_conf_print_tph_req_cap_sttabloc( 3392 (unsigned char)__SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC))); 3393 size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 3394 printf(" ST Table Size: %d\n", size); 3395 for (i = 0; i < size ; i += 2) { 3396 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 3397 for (j = 0; j < 2 ; j++) { 3398 uint32_t entry = reg; 3399 3400 if (j != 0) 3401 entry >>= 16; 3402 entry &= 0xffff; 3403 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 3404 i + j, entry); 3405 } 3406 } 3407 } 3408 3409 static void 3410 pci_conf_print_ltr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3411 { 3412 pcireg_t reg; 3413 3414 printf("\n Latency Tolerance Reporting\n"); 3415 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)] & 0xffff; 3416 printf(" Max Snoop Latency Register: 0x%04x\n", reg); 3417 printf(" Max Snoop LatencyValue: %u\n", 3418 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL)); 3419 printf(" Max Snoop LatencyScale: %uns\n", 3420 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE))); 3421 reg = regs[o2i(extcapoff + PCI_LTR_MAXNOSNOOPLAT)] >> 16; 3422 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg); 3423 printf(" Max No-Snoop LatencyValue: %u\n", 3424 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL)); 3425 printf(" Max No-Snoop LatencyScale: %uns\n", 3426 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE))); 3427 } 3428 3429 static void 3430 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int capoff, int extcapoff) 3431 { 3432 int pcie_capoff; 3433 pcireg_t reg; 3434 int i, maxlinkwidth; 3435 3436 printf("\n Secondary PCI Express Register\n"); 3437 3438 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3439 printf(" Link Control 3 register: 0x%08x\n", reg); 3440 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3441 onoff("Link Equalization Request Interrupt Enable", 3442 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3443 printf(" Enable Lower SKP OS Generation Vector:"); 3444 pci_print_pcie_linkspeedvector( 3445 __SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV)); 3446 printf("\n"); 3447 3448 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3449 printf(" Lane Error Status register: 0x%08x\n", reg); 3450 3451 /* Get Max Link Width */ 3452 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)){ 3453 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3454 maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3455 } else { 3456 printf("error: falied to get PCIe capablity\n"); 3457 return; 3458 } 3459 for (i = 0; i < maxlinkwidth; i++) { 3460 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3461 if (i % 2 != 0) 3462 reg >>= 16; 3463 else 3464 reg &= 0xffff; 3465 printf(" Equalization Control Register (Link %d): 0x%04x\n", 3466 i, reg); 3467 printf(" Downstream Port Transmit Preset: 0x%x\n", 3468 (pcireg_t)__SHIFTOUT(reg, 3469 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3470 printf(" Downstream Port Receive Hint: 0x%x\n", 3471 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3472 printf(" Upstream Port Transmit Preset: 0x%x\n", 3473 (pcireg_t)__SHIFTOUT(reg, 3474 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3475 printf(" Upstream Port Receive Hint: 0x%x\n", 3476 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3477 } 3478 } 3479 3480 /* XXX pci_conf_print_pmux_cap */ 3481 3482 static void 3483 pci_conf_print_pasid_cap(const pcireg_t *regs, int capoff, int extcapoff) 3484 { 3485 pcireg_t reg, cap, ctl; 3486 unsigned int num; 3487 3488 printf("\n Process Address Space ID\n"); 3489 3490 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3491 cap = reg & 0xffff; 3492 ctl = reg >> 16; 3493 printf(" PASID Capability Register: 0x%04x\n", cap); 3494 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3495 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3496 num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3497 printf(" Max PASID Width: %u\n", num); 3498 3499 printf(" PASID Control Register: 0x%04x\n", ctl); 3500 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3501 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3502 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 3503 } 3504 3505 static void 3506 pci_conf_print_lnr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3507 { 3508 pcireg_t reg, cap, ctl; 3509 unsigned int num; 3510 3511 printf("\n LN Requester\n"); 3512 3513 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 3514 cap = reg & 0xffff; 3515 ctl = reg >> 16; 3516 printf(" LNR Capability register: 0x%04x\n", cap); 3517 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 3518 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 3519 num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 3520 printf(" LNR Registration MAX: %u\n", num); 3521 3522 printf(" LNR Control register: 0x%04x\n", ctl); 3523 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 3524 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 3525 num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 3526 printf(" LNR Registration Limit: %u\n", num); 3527 } 3528 3529 /* XXX pci_conf_print_dpc_cap */ 3530 3531 static int 3532 pci_conf_l1pm_cap_tposcale(unsigned char scale) 3533 { 3534 3535 /* Return scale in us */ 3536 switch (scale) { 3537 case 0x0: 3538 return 2; 3539 case 0x1: 3540 return 10; 3541 case 0x2: 3542 return 100; 3543 default: 3544 return -1; 3545 } 3546 } 3547 3548 static void 3549 pci_conf_print_l1pm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3550 { 3551 pcireg_t reg; 3552 int scale, val; 3553 3554 printf("\n L1 PM Substates\n"); 3555 3556 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 3557 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 3558 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 3559 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 3560 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 3561 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 3562 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 3563 printf(" Port Common Mode Restore Time: %uus\n", 3564 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 3565 scale = pci_conf_l1pm_cap_tposcale( 3566 __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 3567 val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 3568 printf(" Port T_POWER_ON: "); 3569 if (scale == -1) 3570 printf("unknown\n"); 3571 else 3572 printf("%dus\n", val * scale); 3573 3574 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 3575 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 3576 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 3577 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 3578 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 3579 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 3580 printf(" Common Mode Restore Time: %uus\n", 3581 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 3582 scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 3583 val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 3584 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 3585 3586 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 3587 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 3588 scale = pci_conf_l1pm_cap_tposcale( 3589 __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 3590 val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 3591 printf(" T_POWER_ON: "); 3592 if (scale == -1) 3593 printf("unknown\n"); 3594 else 3595 printf("%dus\n", val * scale); 3596 } 3597 3598 static void 3599 pci_conf_print_ptm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3600 { 3601 pcireg_t reg; 3602 uint32_t val; 3603 3604 printf("\n Precision Time Management\n"); 3605 3606 reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; 3607 printf(" PTM Capability register: 0x%08x\n", reg); 3608 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ); 3609 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP); 3610 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT); 3611 printf(" Local Clock Granularity: "); 3612 val = __SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL); 3613 switch (val) { 3614 case 0: 3615 printf("Not implemented\n"); 3616 break; 3617 case 0xffff: 3618 printf("> 254ns\n"); 3619 break; 3620 default: 3621 printf("%uns\n", val); 3622 break; 3623 } 3624 3625 reg = regs[o2i(extcapoff + PCI_PTM_CTL)]; 3626 printf(" PTM Control register: 0x%08x\n", reg); 3627 onoff("PTM Enable", reg, PCI_PTM_CTL_EN); 3628 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL); 3629 printf(" Effective Granularity: "); 3630 val = __SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL); 3631 switch (val) { 3632 case 0: 3633 printf("Unknown\n"); 3634 break; 3635 case 0xffff: 3636 printf("> 254ns\n"); 3637 break; 3638 default: 3639 printf("%uns\n", val); 3640 break; 3641 } 3642 } 3643 3644 /* XXX pci_conf_print_mpcie_cap */ 3645 /* XXX pci_conf_print_frsq_cap */ 3646 /* XXX pci_conf_print_rtr_cap */ 3647 /* XXX pci_conf_print_desigvndsp_cap */ 3648 /* XXX pci_conf_print_vf_resizbar_cap */ 3649 3650 #undef MS 3651 #undef SM 3652 #undef RW 3653 3654 static struct { 3655 pcireg_t cap; 3656 const char *name; 3657 void (*printfunc)(const pcireg_t *, int, int); 3658 } pci_extcaptab[] = { 3659 { 0, "reserved", 3660 NULL }, 3661 { PCI_EXTCAP_AER, "Advanced Error Reporting", 3662 pci_conf_print_aer_cap }, 3663 { PCI_EXTCAP_VC, "Virtual Channel", 3664 pci_conf_print_vc_cap }, 3665 { PCI_EXTCAP_SERNUM, "Device Serial Number", 3666 pci_conf_print_sernum_cap }, 3667 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 3668 pci_conf_print_pwrbdgt_cap }, 3669 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 3670 pci_conf_print_rclink_dcl_cap }, 3671 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 3672 NULL }, 3673 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 3674 pci_conf_print_rcec_assoc_cap }, 3675 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 3676 NULL }, 3677 { PCI_EXTCAP_VC2, "Virtual Channel", 3678 NULL }, 3679 { PCI_EXTCAP_RCRB, "RCRB Header", 3680 NULL }, 3681 { PCI_EXTCAP_VENDOR, "Vendor Unique", 3682 NULL }, 3683 { PCI_EXTCAP_CAC, "Configuration Access Correction", 3684 NULL }, 3685 { PCI_EXTCAP_ACS, "Access Control Services", 3686 pci_conf_print_acs_cap }, 3687 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 3688 pci_conf_print_ari_cap }, 3689 { PCI_EXTCAP_ATS, "Address Translation Services", 3690 pci_conf_print_ats_cap }, 3691 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 3692 pci_conf_print_sriov_cap }, 3693 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 3694 NULL }, 3695 { PCI_EXTCAP_MCAST, "Multicast", 3696 pci_conf_print_multicast_cap }, 3697 { PCI_EXTCAP_PAGE_REQ, "Page Request", 3698 pci_conf_print_page_req_cap }, 3699 { PCI_EXTCAP_AMD, "Reserved for AMD", 3700 NULL }, 3701 { PCI_EXTCAP_RESIZBAR, "Resizable BAR", 3702 pci_conf_print_resizbar_cap }, 3703 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 3704 pci_conf_print_dpa_cap }, 3705 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 3706 pci_conf_print_tph_req_cap }, 3707 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 3708 pci_conf_print_ltr_cap }, 3709 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 3710 pci_conf_print_sec_pcie_cap }, 3711 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 3712 NULL }, 3713 { PCI_EXTCAP_PASID, "Process Address Space ID", 3714 pci_conf_print_pasid_cap }, 3715 { PCI_EXTCAP_LN_REQ, "LN Requester", 3716 pci_conf_print_lnr_cap }, 3717 { PCI_EXTCAP_DPC, "Downstream Port Containment", 3718 NULL }, 3719 { PCI_EXTCAP_L1PM, "L1 PM Substates", 3720 pci_conf_print_l1pm_cap }, 3721 { PCI_EXTCAP_PTM, "Precision Time Management", 3722 pci_conf_print_ptm_cap }, 3723 { PCI_EXTCAP_MPCIE, "M-PCIe", 3724 NULL }, 3725 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 3726 NULL }, 3727 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 3728 NULL }, 3729 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 3730 NULL }, 3731 { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs", 3732 NULL }, 3733 }; 3734 3735 static int 3736 pci_conf_find_extcap(const pcireg_t *regs, int capoff, unsigned int capid, 3737 int *offsetp) 3738 { 3739 int off; 3740 pcireg_t rval; 3741 3742 for (off = PCI_EXTCAPLIST_BASE; 3743 off != 0; 3744 off = PCI_EXTCAPLIST_NEXT(rval)) { 3745 rval = regs[o2i(off)]; 3746 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 3747 if (offsetp != NULL) 3748 *offsetp = off; 3749 return 1; 3750 } 3751 } 3752 return 0; 3753 } 3754 3755 static void 3756 pci_conf_print_extcaplist( 3757 #ifdef _KERNEL 3758 pci_chipset_tag_t pc, pcitag_t tag, 3759 #endif 3760 const pcireg_t *regs, int capoff) 3761 { 3762 int off; 3763 pcireg_t foundcap; 3764 pcireg_t rval; 3765 bool foundtable[__arraycount(pci_extcaptab)]; 3766 unsigned int i; 3767 3768 /* Check Extended capability structure */ 3769 off = PCI_EXTCAPLIST_BASE; 3770 rval = regs[o2i(off)]; 3771 if (rval == 0xffffffff || rval == 0) 3772 return; 3773 3774 /* Clear table */ 3775 for (i = 0; i < __arraycount(pci_extcaptab); i++) 3776 foundtable[i] = false; 3777 3778 /* Print extended capability register's offset and the type first */ 3779 for (;;) { 3780 printf(" Extended Capability Register at 0x%02x\n", off); 3781 3782 foundcap = PCI_EXTCAPLIST_CAP(rval); 3783 printf(" type: 0x%04x (", foundcap); 3784 if (foundcap < __arraycount(pci_extcaptab)) { 3785 printf("%s)\n", pci_extcaptab[foundcap].name); 3786 /* Mark as found */ 3787 foundtable[foundcap] = true; 3788 } else 3789 printf("unknown)\n"); 3790 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 3791 3792 off = PCI_EXTCAPLIST_NEXT(rval); 3793 if (off == 0) 3794 break; 3795 else if (off <= PCI_CONF_SIZE) { 3796 printf(" next pointer: 0x%03x (incorrect)\n", off); 3797 return; 3798 } 3799 rval = regs[o2i(off)]; 3800 } 3801 3802 /* 3803 * And then, print the detail of each capability registers 3804 * in capability value's order. 3805 */ 3806 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 3807 if (foundtable[i] == false) 3808 continue; 3809 3810 /* 3811 * The type was found. Search capability list again and 3812 * print all capabilities that the capabiliy type is 3813 * the same. 3814 */ 3815 if (pci_conf_find_extcap(regs, capoff, i, &off) == 0) 3816 continue; 3817 rval = regs[o2i(off)]; 3818 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 3819 || (pci_extcaptab[i].printfunc == NULL)) 3820 continue; 3821 3822 pci_extcaptab[i].printfunc(regs, capoff, off); 3823 3824 } 3825 } 3826 3827 /* Print the Secondary Status Register. */ 3828 static void 3829 pci_conf_print_ssr(pcireg_t rval) 3830 { 3831 pcireg_t devsel; 3832 3833 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 3834 onoff("66 MHz capable", rval, __BIT(5)); 3835 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 3836 onoff("Fast back-to-back capable", rval, __BIT(7)); 3837 onoff("Data parity error detected", rval, __BIT(8)); 3838 3839 printf(" DEVSEL timing: "); 3840 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 3841 switch (devsel) { 3842 case 0: 3843 printf("fast"); 3844 break; 3845 case 1: 3846 printf("medium"); 3847 break; 3848 case 2: 3849 printf("slow"); 3850 break; 3851 default: 3852 printf("unknown/reserved"); /* XXX */ 3853 break; 3854 } 3855 printf(" (0x%x)\n", devsel); 3856 3857 onoff("Signalled target abort", rval, __BIT(11)); 3858 onoff("Received target abort", rval, __BIT(12)); 3859 onoff("Received master abort", rval, __BIT(13)); 3860 onoff("Received system error", rval, __BIT(14)); 3861 onoff("Detected parity error", rval, __BIT(15)); 3862 } 3863 3864 static void 3865 pci_conf_print_type0( 3866 #ifdef _KERNEL 3867 pci_chipset_tag_t pc, pcitag_t tag, 3868 #endif 3869 const pcireg_t *regs 3870 #ifdef _KERNEL 3871 , int sizebars 3872 #endif 3873 ) 3874 { 3875 int off, width; 3876 pcireg_t rval; 3877 3878 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 3879 #ifdef _KERNEL 3880 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3881 #else 3882 width = pci_conf_print_bar(regs, off, NULL); 3883 #endif 3884 } 3885 3886 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 3887 3888 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 3889 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 3890 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 3891 3892 /* XXX */ 3893 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 3894 3895 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3896 printf(" Capability list pointer: 0x%02x\n", 3897 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 3898 else 3899 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 3900 3901 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 3902 3903 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3904 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 3905 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 3906 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 3907 switch (PCI_INTERRUPT_PIN(rval)) { 3908 case PCI_INTERRUPT_PIN_NONE: 3909 printf("(none)"); 3910 break; 3911 case PCI_INTERRUPT_PIN_A: 3912 printf("(pin A)"); 3913 break; 3914 case PCI_INTERRUPT_PIN_B: 3915 printf("(pin B)"); 3916 break; 3917 case PCI_INTERRUPT_PIN_C: 3918 printf("(pin C)"); 3919 break; 3920 case PCI_INTERRUPT_PIN_D: 3921 printf("(pin D)"); 3922 break; 3923 default: 3924 printf("(? ? ?)"); 3925 break; 3926 } 3927 printf("\n"); 3928 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 3929 } 3930 3931 static void 3932 pci_conf_print_type1( 3933 #ifdef _KERNEL 3934 pci_chipset_tag_t pc, pcitag_t tag, 3935 #endif 3936 const pcireg_t *regs 3937 #ifdef _KERNEL 3938 , int sizebars 3939 #endif 3940 ) 3941 { 3942 int off, width; 3943 pcireg_t rval; 3944 uint32_t base, limit; 3945 uint32_t base_h, limit_h; 3946 uint64_t pbase, plimit; 3947 int use_upper; 3948 3949 /* 3950 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 3951 * Bridge chip documentation, and may not be correct with 3952 * respect to various standards. (XXX) 3953 */ 3954 3955 for (off = 0x10; off < 0x18; off += width) { 3956 #ifdef _KERNEL 3957 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 3958 #else 3959 width = pci_conf_print_bar(regs, off, NULL); 3960 #endif 3961 } 3962 3963 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 3964 printf(" Primary bus number: 0x%02x\n", 3965 PCI_BRIDGE_BUS_PRIMARY(rval)); 3966 printf(" Secondary bus number: 0x%02x\n", 3967 PCI_BRIDGE_BUS_SECONDARY(rval)); 3968 printf(" Subordinate bus number: 0x%02x\n", 3969 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 3970 printf(" Secondary bus latency timer: 0x%02x\n", 3971 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 3972 3973 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 3974 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 3975 3976 /* I/O region */ 3977 printf(" I/O region:\n"); 3978 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 3979 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 3980 if (PCI_BRIDGE_IO_32BITS(rval)) 3981 use_upper = 1; 3982 else 3983 use_upper = 0; 3984 onoff("32bit I/O", rval, use_upper); 3985 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 3986 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 3987 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 3988 limit |= 0x00000fff; 3989 3990 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 3991 base_h = (rval >> 0) & 0xffff; 3992 limit_h = (rval >> 16) & 0xffff; 3993 printf(" base upper 16 bits register: 0x%04x\n", base_h); 3994 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 3995 3996 if (use_upper == 1) { 3997 base |= base_h << 16; 3998 limit |= limit_h << 16; 3999 } 4000 if (base < limit) { 4001 if (use_upper == 1) 4002 printf(" range: 0x%08x-0x%08x\n", base, limit); 4003 else 4004 printf(" range: 0x%04x-0x%04x\n", base, limit); 4005 } else 4006 printf(" range: not set\n"); 4007 4008 /* Non-prefetchable memory region */ 4009 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 4010 printf(" Memory region:\n"); 4011 printf(" base register: 0x%04x\n", 4012 (rval >> 0) & 0xffff); 4013 printf(" limit register: 0x%04x\n", 4014 (rval >> 16) & 0xffff); 4015 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 4016 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 4017 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 4018 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 4019 if (base < limit) 4020 printf(" range: 0x%08x-0x%08x\n", base, limit); 4021 else 4022 printf(" range: not set\n"); 4023 4024 /* Prefetchable memory region */ 4025 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 4026 printf(" Prefetchable memory region:\n"); 4027 printf(" base register: 0x%04x\n", 4028 (rval >> 0) & 0xffff); 4029 printf(" limit register: 0x%04x\n", 4030 (rval >> 16) & 0xffff); 4031 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 4032 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 4033 printf(" base upper 32 bits register: 0x%08x\n", 4034 base_h); 4035 printf(" limit upper 32 bits register: 0x%08x\n", 4036 limit_h); 4037 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 4038 use_upper = 1; 4039 else 4040 use_upper = 0; 4041 onoff("64bit memory address", rval, use_upper); 4042 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 4043 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 4044 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 4045 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 4046 if (use_upper == 1) { 4047 pbase |= (uint64_t)base_h << 32; 4048 plimit |= (uint64_t)limit_h << 32; 4049 } 4050 if (pbase < plimit) { 4051 if (use_upper == 1) 4052 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 4053 "\n", pbase, plimit); 4054 else 4055 printf(" range: 0x%08x-0x%08x\n", 4056 (uint32_t)pbase, (uint32_t)plimit); 4057 } else 4058 printf(" range: not set\n"); 4059 4060 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4061 printf(" Capability list pointer: 0x%02x\n", 4062 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4063 else 4064 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4065 4066 /* XXX */ 4067 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 4068 4069 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4070 printf(" Interrupt line: 0x%02x\n", 4071 (rval >> 0) & 0xff); 4072 printf(" Interrupt pin: 0x%02x ", 4073 (rval >> 8) & 0xff); 4074 switch ((rval >> 8) & 0xff) { 4075 case PCI_INTERRUPT_PIN_NONE: 4076 printf("(none)"); 4077 break; 4078 case PCI_INTERRUPT_PIN_A: 4079 printf("(pin A)"); 4080 break; 4081 case PCI_INTERRUPT_PIN_B: 4082 printf("(pin B)"); 4083 break; 4084 case PCI_INTERRUPT_PIN_C: 4085 printf("(pin C)"); 4086 break; 4087 case PCI_INTERRUPT_PIN_D: 4088 printf("(pin D)"); 4089 break; 4090 default: 4091 printf("(? ? ?)"); 4092 break; 4093 } 4094 printf("\n"); 4095 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 4096 & PCI_BRIDGE_CONTROL_MASK; 4097 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 4098 onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE); 4099 onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR); 4100 onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA); 4101 onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA); 4102 onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT); 4103 onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR); 4104 onoff("Fast back-to-back capable", rval,PCI_BRIDGE_CONTROL_SECFASTB2B); 4105 } 4106 4107 static void 4108 pci_conf_print_type2( 4109 #ifdef _KERNEL 4110 pci_chipset_tag_t pc, pcitag_t tag, 4111 #endif 4112 const pcireg_t *regs 4113 #ifdef _KERNEL 4114 , int sizebars 4115 #endif 4116 ) 4117 { 4118 pcireg_t rval; 4119 4120 /* 4121 * XXX these need to be printed in more detail, need to be 4122 * XXX checked against specs/docs, etc. 4123 * 4124 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 4125 * controller chip documentation, and may not be correct with 4126 * respect to various standards. (XXX) 4127 */ 4128 4129 #ifdef _KERNEL 4130 pci_conf_print_bar(pc, tag, regs, 0x10, 4131 "CardBus socket/ExCA registers", sizebars); 4132 #else 4133 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 4134 #endif 4135 4136 /* Capability list pointer and secondary status register */ 4137 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 4138 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4139 printf(" Capability list pointer: 0x%02x\n", 4140 PCI_CAPLIST_PTR(rval)); 4141 else 4142 printf(" Reserved @ 0x14: 0x%04x\n", 4143 (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0))); 4144 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 4145 4146 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4147 printf(" PCI bus number: 0x%02x\n", 4148 (rval >> 0) & 0xff); 4149 printf(" CardBus bus number: 0x%02x\n", 4150 (rval >> 8) & 0xff); 4151 printf(" Subordinate bus number: 0x%02x\n", 4152 (rval >> 16) & 0xff); 4153 printf(" CardBus latency timer: 0x%02x\n", 4154 (rval >> 24) & 0xff); 4155 4156 /* XXX Print more prettily */ 4157 printf(" CardBus memory region 0:\n"); 4158 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 4159 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 4160 printf(" CardBus memory region 1:\n"); 4161 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 4162 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 4163 printf(" CardBus I/O region 0:\n"); 4164 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 4165 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 4166 printf(" CardBus I/O region 1:\n"); 4167 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 4168 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 4169 4170 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4171 printf(" Interrupt line: 0x%02x\n", 4172 (rval >> 0) & 0xff); 4173 printf(" Interrupt pin: 0x%02x ", 4174 (rval >> 8) & 0xff); 4175 switch ((rval >> 8) & 0xff) { 4176 case PCI_INTERRUPT_PIN_NONE: 4177 printf("(none)"); 4178 break; 4179 case PCI_INTERRUPT_PIN_A: 4180 printf("(pin A)"); 4181 break; 4182 case PCI_INTERRUPT_PIN_B: 4183 printf("(pin B)"); 4184 break; 4185 case PCI_INTERRUPT_PIN_C: 4186 printf("(pin C)"); 4187 break; 4188 case PCI_INTERRUPT_PIN_D: 4189 printf("(pin D)"); 4190 break; 4191 default: 4192 printf("(? ? ?)"); 4193 break; 4194 } 4195 printf("\n"); 4196 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 4197 printf(" Bridge control register: 0x%04x\n", rval); 4198 onoff("Parity error response", rval, __BIT(0)); 4199 onoff("SERR# enable", rval, __BIT(1)); 4200 onoff("ISA enable", rval, __BIT(2)); 4201 onoff("VGA enable", rval, __BIT(3)); 4202 onoff("Master abort mode", rval, __BIT(5)); 4203 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 4204 onoff("Functional interrupts routed by ExCA registers", rval, 4205 __BIT(7)); 4206 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 4207 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 4208 onoff("Write posting enable", rval, __BIT(10)); 4209 4210 rval = regs[o2i(0x40)]; 4211 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4212 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4213 4214 #ifdef _KERNEL 4215 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 4216 sizebars); 4217 #else 4218 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 4219 #endif 4220 } 4221 4222 void 4223 pci_conf_print( 4224 #ifdef _KERNEL 4225 pci_chipset_tag_t pc, pcitag_t tag, 4226 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 4227 #else 4228 int pcifd, u_int bus, u_int dev, u_int func 4229 #endif 4230 ) 4231 { 4232 pcireg_t regs[o2i(PCI_EXTCONF_SIZE)]; 4233 int off, capoff, endoff, hdrtype; 4234 const char *type_name; 4235 #ifdef _KERNEL 4236 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, 4237 int); 4238 int sizebars; 4239 #else 4240 void (*type_printfn)(const pcireg_t *); 4241 #endif 4242 4243 printf("PCI configuration registers:\n"); 4244 4245 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 4246 #ifdef _KERNEL 4247 regs[o2i(off)] = pci_conf_read(pc, tag, off); 4248 #else 4249 if (pcibus_conf_read(pcifd, bus, dev, func, off, 4250 ®s[o2i(off)]) == -1) 4251 regs[o2i(off)] = 0; 4252 #endif 4253 } 4254 4255 #ifdef _KERNEL 4256 sizebars = 1; 4257 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 4258 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 4259 sizebars = 0; 4260 #endif 4261 4262 /* common header */ 4263 printf(" Common header:\n"); 4264 pci_conf_print_regs(regs, 0, 16); 4265 4266 printf("\n"); 4267 #ifdef _KERNEL 4268 pci_conf_print_common(pc, tag, regs); 4269 #else 4270 pci_conf_print_common(regs); 4271 #endif 4272 printf("\n"); 4273 4274 /* type-dependent header */ 4275 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 4276 switch (hdrtype) { /* XXX make a table, eventually */ 4277 case 0: 4278 /* Standard device header */ 4279 type_name = "\"normal\" device"; 4280 type_printfn = &pci_conf_print_type0; 4281 capoff = PCI_CAPLISTPTR_REG; 4282 endoff = 64; 4283 break; 4284 case 1: 4285 /* PCI-PCI bridge header */ 4286 type_name = "PCI-PCI bridge"; 4287 type_printfn = &pci_conf_print_type1; 4288 capoff = PCI_CAPLISTPTR_REG; 4289 endoff = 64; 4290 break; 4291 case 2: 4292 /* PCI-CardBus bridge header */ 4293 type_name = "PCI-CardBus bridge"; 4294 type_printfn = &pci_conf_print_type2; 4295 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 4296 endoff = 72; 4297 break; 4298 default: 4299 type_name = NULL; 4300 type_printfn = 0; 4301 capoff = -1; 4302 endoff = 64; 4303 break; 4304 } 4305 printf(" Type %d ", hdrtype); 4306 if (type_name != NULL) 4307 printf("(%s) ", type_name); 4308 printf("header:\n"); 4309 pci_conf_print_regs(regs, 16, endoff); 4310 printf("\n"); 4311 if (type_printfn) { 4312 #ifdef _KERNEL 4313 (*type_printfn)(pc, tag, regs, sizebars); 4314 #else 4315 (*type_printfn)(regs); 4316 #endif 4317 } else 4318 printf(" Don't know how to pretty-print type %d header.\n", 4319 hdrtype); 4320 printf("\n"); 4321 4322 /* capability list, if present */ 4323 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4324 && (capoff > 0)) { 4325 #ifdef _KERNEL 4326 pci_conf_print_caplist(pc, tag, regs, capoff); 4327 #else 4328 pci_conf_print_caplist(regs, capoff); 4329 #endif 4330 printf("\n"); 4331 } 4332 4333 /* device-dependent header */ 4334 printf(" Device-dependent header:\n"); 4335 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 4336 printf("\n"); 4337 #ifdef _KERNEL 4338 if (printfn) 4339 (*printfn)(pc, tag, regs); 4340 else 4341 printf(" Don't know how to pretty-print device-dependent header.\n"); 4342 printf("\n"); 4343 #endif /* _KERNEL */ 4344 4345 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 4346 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 4347 return; 4348 4349 #ifdef _KERNEL 4350 pci_conf_print_extcaplist(pc, tag, regs, capoff); 4351 #else 4352 pci_conf_print_extcaplist(regs, capoff); 4353 #endif 4354 printf("\n"); 4355 4356 /* Extended Configuration Space, if present */ 4357 printf(" Extended Configuration Space:\n"); 4358 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 4359 } 4360
Indexes created Thu Sep 25 16:09:42 GMT 2025